intel_hdmi.c 48.8 KB
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/*
 * Copyright 2006 Dave Airlie <airlied@linux.ie>
 * Copyright © 2006-2009 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 *	Jesse Barnes <jesse.barnes@intel.com>
 */

#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/hdmi.h>
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#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_edid.h>
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#include "intel_drv.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"

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static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
{
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	return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
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}

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static void
assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
{
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	struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
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	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t enabled_bits;

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	enabled_bits = HAS_DDI(dev) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
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	WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
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	     "HDMI port enabled, expecting disabled\n");
}

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struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
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{
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	struct intel_digital_port *intel_dig_port =
		container_of(encoder, struct intel_digital_port, base.base);
	return &intel_dig_port->hdmi;
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}

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static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
{
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	return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
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}

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static u32 g4x_infoframe_index(enum hdmi_infoframe_type type)
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{
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	switch (type) {
	case HDMI_INFOFRAME_TYPE_AVI:
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		return VIDEO_DIP_SELECT_AVI;
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	case HDMI_INFOFRAME_TYPE_SPD:
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		return VIDEO_DIP_SELECT_SPD;
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	case HDMI_INFOFRAME_TYPE_VENDOR:
		return VIDEO_DIP_SELECT_VENDOR;
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	default:
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		DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
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		return 0;
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	}
}

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static u32 g4x_infoframe_enable(enum hdmi_infoframe_type type)
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{
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	switch (type) {
	case HDMI_INFOFRAME_TYPE_AVI:
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		return VIDEO_DIP_ENABLE_AVI;
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	case HDMI_INFOFRAME_TYPE_SPD:
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		return VIDEO_DIP_ENABLE_SPD;
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	case HDMI_INFOFRAME_TYPE_VENDOR:
		return VIDEO_DIP_ENABLE_VENDOR;
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	default:
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		DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
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		return 0;
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	}
}

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static u32 hsw_infoframe_enable(enum hdmi_infoframe_type type)
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{
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	switch (type) {
	case HDMI_INFOFRAME_TYPE_AVI:
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		return VIDEO_DIP_ENABLE_AVI_HSW;
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	case HDMI_INFOFRAME_TYPE_SPD:
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		return VIDEO_DIP_ENABLE_SPD_HSW;
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	case HDMI_INFOFRAME_TYPE_VENDOR:
		return VIDEO_DIP_ENABLE_VS_HSW;
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	default:
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		DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
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		return 0;
	}
}

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static u32 hsw_infoframe_data_reg(enum hdmi_infoframe_type type,
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				  enum transcoder cpu_transcoder,
				  struct drm_i915_private *dev_priv)
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{
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	switch (type) {
	case HDMI_INFOFRAME_TYPE_AVI:
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		return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder);
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	case HDMI_INFOFRAME_TYPE_SPD:
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		return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder);
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	case HDMI_INFOFRAME_TYPE_VENDOR:
		return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder);
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	default:
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		DRM_DEBUG_DRIVER("unknown info frame type %d\n", type);
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		return 0;
	}
}

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static void g4x_write_infoframe(struct drm_encoder *encoder,
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				enum hdmi_infoframe_type type,
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				const void *frame, ssize_t len)
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{
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	const uint32_t *data = frame;
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	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	u32 val = I915_READ(VIDEO_DIP_CTL);
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	int i;
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	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");

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	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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	val |= g4x_infoframe_index(type);
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	val &= ~g4x_infoframe_enable(type);
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	I915_WRITE(VIDEO_DIP_CTL, val);
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	mmiowb();
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	for (i = 0; i < len; i += 4) {
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		I915_WRITE(VIDEO_DIP_DATA, *data);
		data++;
	}
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	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		I915_WRITE(VIDEO_DIP_DATA, 0);
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	mmiowb();
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	val |= g4x_infoframe_enable(type);
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	val &= ~VIDEO_DIP_FREQ_MASK;
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	val |= VIDEO_DIP_FREQ_VSYNC;
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	I915_WRITE(VIDEO_DIP_CTL, val);
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	POSTING_READ(VIDEO_DIP_CTL);
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}

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static void ibx_write_infoframe(struct drm_encoder *encoder,
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				enum hdmi_infoframe_type type,
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				const void *frame, ssize_t len)
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{
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	const uint32_t *data = frame;
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	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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	int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
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	u32 val = I915_READ(reg);

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	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");

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	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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	val |= g4x_infoframe_index(type);
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	val &= ~g4x_infoframe_enable(type);
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	I915_WRITE(reg, val);

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	mmiowb();
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	for (i = 0; i < len; i += 4) {
		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		data++;
	}
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	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
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	mmiowb();
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	val |= g4x_infoframe_enable(type);
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	val &= ~VIDEO_DIP_FREQ_MASK;
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	val |= VIDEO_DIP_FREQ_VSYNC;
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	I915_WRITE(reg, val);
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	POSTING_READ(reg);
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}

static void cpt_write_infoframe(struct drm_encoder *encoder,
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				enum hdmi_infoframe_type type,
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				const void *frame, ssize_t len)
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{
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	const uint32_t *data = frame;
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	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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	int i, reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
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	u32 val = I915_READ(reg);
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	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");

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	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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	val |= g4x_infoframe_index(type);
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	/* The DIP control register spec says that we need to update the AVI
	 * infoframe without clearing its enable bit */
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	if (type != HDMI_INFOFRAME_TYPE_AVI)
		val &= ~g4x_infoframe_enable(type);
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	I915_WRITE(reg, val);
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	mmiowb();
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	for (i = 0; i < len; i += 4) {
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		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		data++;
	}
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	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
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	mmiowb();
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	val |= g4x_infoframe_enable(type);
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	val &= ~VIDEO_DIP_FREQ_MASK;
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	val |= VIDEO_DIP_FREQ_VSYNC;
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	I915_WRITE(reg, val);
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	POSTING_READ(reg);
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}
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static void vlv_write_infoframe(struct drm_encoder *encoder,
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				enum hdmi_infoframe_type type,
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				const void *frame, ssize_t len)
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{
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	const uint32_t *data = frame;
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	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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	int i, reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
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	u32 val = I915_READ(reg);
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	WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");

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	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
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	val |= g4x_infoframe_index(type);
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	val &= ~g4x_infoframe_enable(type);
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	I915_WRITE(reg, val);
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	mmiowb();
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	for (i = 0; i < len; i += 4) {
		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
		data++;
	}
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	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
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	mmiowb();
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	val |= g4x_infoframe_enable(type);
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	val &= ~VIDEO_DIP_FREQ_MASK;
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	val |= VIDEO_DIP_FREQ_VSYNC;
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	I915_WRITE(reg, val);
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	POSTING_READ(reg);
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}

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static void hsw_write_infoframe(struct drm_encoder *encoder,
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				enum hdmi_infoframe_type type,
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				const void *frame, ssize_t len)
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{
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	const uint32_t *data = frame;
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	struct drm_device *dev = encoder->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
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	u32 data_reg;
	int i;
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	u32 val = I915_READ(ctl_reg);
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	data_reg = hsw_infoframe_data_reg(type,
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					  intel_crtc->config.cpu_transcoder,
					  dev_priv);
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	if (data_reg == 0)
		return;

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	val &= ~hsw_infoframe_enable(type);
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	I915_WRITE(ctl_reg, val);

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	mmiowb();
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	for (i = 0; i < len; i += 4) {
		I915_WRITE(data_reg + i, *data);
		data++;
	}
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	/* Write every possible data byte to force correct ECC calculation. */
	for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
		I915_WRITE(data_reg + i, 0);
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	mmiowb();
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	val |= hsw_infoframe_enable(type);
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	I915_WRITE(ctl_reg, val);
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	POSTING_READ(ctl_reg);
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}

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/*
 * The data we write to the DIP data buffer registers is 1 byte bigger than the
 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
 * used for both technologies.
 *
 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
 * DW1:       DB3       | DB2 | DB1 | DB0
 * DW2:       DB7       | DB6 | DB5 | DB4
 * DW3: ...
 *
 * (HB is Header Byte, DB is Data Byte)
 *
 * The hdmi pack() functions don't know about that hardware specific hole so we
 * trick them by giving an offset into the buffer and moving back the header
 * bytes by one.
 */
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static void intel_write_infoframe(struct drm_encoder *encoder,
				  union hdmi_infoframe *frame)
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{
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
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	uint8_t buffer[VIDEO_DIP_DATA_SIZE];
	ssize_t len;
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	/* see comment above for the reason for this offset */
	len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
	if (len < 0)
		return;

	/* Insert the 'hole' (see big comment above) at position 3 */
	buffer[0] = buffer[1];
	buffer[1] = buffer[2];
	buffer[2] = buffer[3];
	buffer[3] = 0;
	len++;
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	intel_hdmi->write_infoframe(encoder, frame->any.type, buffer, len);
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}

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static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
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					 struct drm_display_mode *adjusted_mode)
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{
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	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
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	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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	union hdmi_infoframe frame;
	int ret;
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	/* Set user selected PAR to incoming mode's member */
	adjusted_mode->picture_aspect_ratio = intel_hdmi->aspect_ratio;

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	ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
						       adjusted_mode);
	if (ret < 0) {
		DRM_ERROR("couldn't fill AVI infoframe\n");
		return;
	}
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	if (intel_hdmi->rgb_quant_range_selectable) {
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		if (intel_crtc->config.limited_color_range)
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			frame.avi.quantization_range =
				HDMI_QUANTIZATION_RANGE_LIMITED;
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		else
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			frame.avi.quantization_range =
				HDMI_QUANTIZATION_RANGE_FULL;
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	}

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	intel_write_infoframe(encoder, &frame);
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}

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static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
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{
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	union hdmi_infoframe frame;
	int ret;

	ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
	if (ret < 0) {
		DRM_ERROR("couldn't fill SPD infoframe\n");
		return;
	}
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	frame.spd.sdi = HDMI_SPD_SDI_PC;
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	intel_write_infoframe(encoder, &frame);
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}

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static void
intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
			      struct drm_display_mode *adjusted_mode)
{
	union hdmi_infoframe frame;
	int ret;

	ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
							  adjusted_mode);
	if (ret < 0)
		return;

	intel_write_infoframe(encoder, &frame);
}

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static void g4x_set_infoframes(struct drm_encoder *encoder,
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			       bool enable,
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			       struct drm_display_mode *adjusted_mode)
{
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	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
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	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
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	u32 reg = VIDEO_DIP_CTL;
	u32 val = I915_READ(reg);
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	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
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	assert_hdmi_port_disabled(intel_hdmi);

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	/* If the registers were not initialized yet, they might be zeroes,
	 * which means we're selecting the AVI DIP and we're setting its
	 * frequency to once. This seems to really confuse the HW and make
	 * things stop working (the register spec says the AVI always needs to
	 * be sent every VSync). So here we avoid writing to the register more
	 * than we need and also explicitly select the AVI DIP and explicitly
	 * set its frequency to every VSync. Avoiding to write it twice seems to
	 * be enough to solve the problem, but being defensive shouldn't hurt us
	 * either. */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;

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	if (!enable) {
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		if (!(val & VIDEO_DIP_ENABLE))
			return;
		val &= ~VIDEO_DIP_ENABLE;
		I915_WRITE(reg, val);
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		POSTING_READ(reg);
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		return;
	}

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	if (port != (val & VIDEO_DIP_PORT_MASK)) {
		if (val & VIDEO_DIP_ENABLE) {
			val &= ~VIDEO_DIP_ENABLE;
			I915_WRITE(reg, val);
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			POSTING_READ(reg);
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		}
		val &= ~VIDEO_DIP_PORT_MASK;
		val |= port;
	}

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	val |= VIDEO_DIP_ENABLE;
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	val &= ~VIDEO_DIP_ENABLE_VENDOR;
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	I915_WRITE(reg, val);
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	POSTING_READ(reg);
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	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
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	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
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}

static void ibx_set_infoframes(struct drm_encoder *encoder,
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			       bool enable,
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			       struct drm_display_mode *adjusted_mode)
{
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	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
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	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
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	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);
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	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
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	assert_hdmi_port_disabled(intel_hdmi);

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	/* See the big comment in g4x_set_infoframes() */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;

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	if (!enable) {
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		if (!(val & VIDEO_DIP_ENABLE))
			return;
		val &= ~VIDEO_DIP_ENABLE;
		I915_WRITE(reg, val);
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		POSTING_READ(reg);
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		return;
	}

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	if (port != (val & VIDEO_DIP_PORT_MASK)) {
		if (val & VIDEO_DIP_ENABLE) {
			val &= ~VIDEO_DIP_ENABLE;
			I915_WRITE(reg, val);
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			POSTING_READ(reg);
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		}
		val &= ~VIDEO_DIP_PORT_MASK;
		val |= port;
	}

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	val |= VIDEO_DIP_ENABLE;
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	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		 VIDEO_DIP_ENABLE_GCP);
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	I915_WRITE(reg, val);
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	POSTING_READ(reg);
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	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
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	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
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}

static void cpt_set_infoframes(struct drm_encoder *encoder,
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			       bool enable,
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			       struct drm_display_mode *adjusted_mode)
{
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	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);

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	assert_hdmi_port_disabled(intel_hdmi);

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	/* See the big comment in g4x_set_infoframes() */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;

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	if (!enable) {
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		if (!(val & VIDEO_DIP_ENABLE))
			return;
		val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI);
		I915_WRITE(reg, val);
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		POSTING_READ(reg);
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		return;
	}

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	/* Set both together, unset both together: see the spec. */
	val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
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	val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
		 VIDEO_DIP_ENABLE_GCP);
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	I915_WRITE(reg, val);
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	POSTING_READ(reg);
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	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
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	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
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}

static void vlv_set_infoframes(struct drm_encoder *encoder,
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			       bool enable,
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			       struct drm_display_mode *adjusted_mode)
{
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	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
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	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
568 569 570 571
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
	u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
	u32 val = I915_READ(reg);
572
	u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
573

574 575
	assert_hdmi_port_disabled(intel_hdmi);

576 577 578
	/* See the big comment in g4x_set_infoframes() */
	val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;

579
	if (!enable) {
580 581 582 583
		if (!(val & VIDEO_DIP_ENABLE))
			return;
		val &= ~VIDEO_DIP_ENABLE;
		I915_WRITE(reg, val);
584
		POSTING_READ(reg);
585 586 587
		return;
	}

588 589 590 591 592 593 594 595 596 597
	if (port != (val & VIDEO_DIP_PORT_MASK)) {
		if (val & VIDEO_DIP_ENABLE) {
			val &= ~VIDEO_DIP_ENABLE;
			I915_WRITE(reg, val);
			POSTING_READ(reg);
		}
		val &= ~VIDEO_DIP_PORT_MASK;
		val |= port;
	}

598
	val |= VIDEO_DIP_ENABLE;
599 600
	val &= ~(VIDEO_DIP_ENABLE_AVI | VIDEO_DIP_ENABLE_VENDOR |
		 VIDEO_DIP_ENABLE_GAMUT | VIDEO_DIP_ENABLE_GCP);
601 602

	I915_WRITE(reg, val);
603
	POSTING_READ(reg);
604

605 606
	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
607
	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
608 609 610
}

static void hsw_set_infoframes(struct drm_encoder *encoder,
611
			       bool enable,
612 613
			       struct drm_display_mode *adjusted_mode)
{
614 615 616
	struct drm_i915_private *dev_priv = encoder->dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
617
	u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
618
	u32 val = I915_READ(reg);
619

620 621
	assert_hdmi_port_disabled(intel_hdmi);

622
	if (!enable) {
623
		I915_WRITE(reg, 0);
624
		POSTING_READ(reg);
625 626 627
		return;
	}

628 629 630 631
	val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_GCP_HSW |
		 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW);

	I915_WRITE(reg, val);
632
	POSTING_READ(reg);
633

634 635
	intel_hdmi_set_avi_infoframe(encoder, adjusted_mode);
	intel_hdmi_set_spd_infoframe(encoder);
636
	intel_hdmi_set_hdmi_infoframe(encoder, adjusted_mode);
637 638
}

639
static void intel_hdmi_prepare(struct intel_encoder *encoder)
640
{
641
	struct drm_device *dev = encoder->base.dev;
642
	struct drm_i915_private *dev_priv = dev->dev_private;
643 644 645
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
646
	u32 hdmi_val;
647

648
	hdmi_val = SDVO_ENCODING_HDMI;
649
	if (!HAS_PCH_SPLIT(dev))
650
		hdmi_val |= intel_hdmi->color_range;
651
	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
652
		hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
653
	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
654
		hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
655

656
	if (crtc->config.pipe_bpp > 24)
657
		hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
658
	else
659
		hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
660

661
	if (crtc->config.has_hdmi_sink)
662
		hdmi_val |= HDMI_MODE_SELECT_HDMI;
663

664
	if (crtc->config.has_audio) {
665
		WARN_ON(!crtc->config.has_hdmi_sink);
666
		DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
667
				 pipe_name(crtc->pipe));
668
		hdmi_val |= SDVO_AUDIO_ENABLE;
669
		intel_write_eld(&encoder->base, adjusted_mode);
670
	}
671

672
	if (HAS_PCH_CPT(dev))
673
		hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
674 675
	else if (IS_CHERRYVIEW(dev))
		hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
676
	else
677
		hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
678

679 680
	I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
	POSTING_READ(intel_hdmi->hdmi_reg);
681 682
}

683 684
static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
				    enum pipe *pipe)
685
{
686
	struct drm_device *dev = encoder->base.dev;
687
	struct drm_i915_private *dev_priv = dev->dev_private;
688
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
689
	enum intel_display_power_domain power_domain;
690 691
	u32 tmp;

692 693 694 695
	power_domain = intel_display_port_power_domain(encoder);
	if (!intel_display_power_enabled(dev_priv, power_domain))
		return false;

696
	tmp = I915_READ(intel_hdmi->hdmi_reg);
697 698 699 700 701 702

	if (!(tmp & SDVO_ENABLE))
		return false;

	if (HAS_PCH_CPT(dev))
		*pipe = PORT_TO_PIPE_CPT(tmp);
703 704
	else if (IS_CHERRYVIEW(dev))
		*pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
705 706 707 708 709 710
	else
		*pipe = PORT_TO_PIPE(tmp);

	return true;
}

711 712 713 714 715 716
static void intel_hdmi_get_config(struct intel_encoder *encoder,
				  struct intel_crtc_config *pipe_config)
{
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
	u32 tmp, flags = 0;
717
	int dotclock;
718 719 720 721 722 723 724 725 726 727 728 729 730

	tmp = I915_READ(intel_hdmi->hdmi_reg);

	if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
		flags |= DRM_MODE_FLAG_PHSYNC;
	else
		flags |= DRM_MODE_FLAG_NHSYNC;

	if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
		flags |= DRM_MODE_FLAG_PVSYNC;
	else
		flags |= DRM_MODE_FLAG_NVSYNC;

731 732 733
	if (tmp & HDMI_MODE_SELECT_HDMI)
		pipe_config->has_hdmi_sink = true;

734 735 736
	if (tmp & HDMI_MODE_SELECT_HDMI)
		pipe_config->has_audio = true;

737
	pipe_config->adjusted_mode.flags |= flags;
738 739 740 741 742 743 744 745 746

	if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
		dotclock = pipe_config->port_clock * 2 / 3;
	else
		dotclock = pipe_config->port_clock;

	if (HAS_PCH_SPLIT(dev_priv->dev))
		ironlake_check_encoder_dotclock(pipe_config, dotclock);

747
	pipe_config->adjusted_mode.crtc_clock = dotclock;
748 749
}

750
static void intel_enable_hdmi(struct intel_encoder *encoder)
751
{
752
	struct drm_device *dev = encoder->base.dev;
753
	struct drm_i915_private *dev_priv = dev->dev_private;
754
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
755
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
756
	u32 temp;
757 758
	u32 enable_bits = SDVO_ENABLE;

759
	if (intel_crtc->config.has_audio)
760
		enable_bits |= SDVO_AUDIO_ENABLE;
761

762
	temp = I915_READ(intel_hdmi->hdmi_reg);
763

764
	/* HW workaround for IBX, we need to move the port to transcoder A
765 766 767
	 * before disabling it, so restore the transcoder select bit here. */
	if (HAS_PCH_IBX(dev))
		enable_bits |= SDVO_PIPE_SEL(intel_crtc->pipe);
768

769 770 771
	/* HW workaround, need to toggle enable bit off and on for 12bpc, but
	 * we do this anyway which shows more stable in testing.
	 */
772
	if (HAS_PCH_SPLIT(dev)) {
773 774
		I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
		POSTING_READ(intel_hdmi->hdmi_reg);
775 776
	}

777 778
	temp |= enable_bits;

779 780
	I915_WRITE(intel_hdmi->hdmi_reg, temp);
	POSTING_READ(intel_hdmi->hdmi_reg);
781 782 783 784 785

	/* HW workaround, need to write this twice for issue that may result
	 * in first write getting masked.
	 */
	if (HAS_PCH_SPLIT(dev)) {
786 787
		I915_WRITE(intel_hdmi->hdmi_reg, temp);
		POSTING_READ(intel_hdmi->hdmi_reg);
788
	}
789
}
790

791 792
static void vlv_enable_hdmi(struct intel_encoder *encoder)
{
793 794 795 796 797 798 799 800
}

static void intel_disable_hdmi(struct intel_encoder *encoder)
{
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	u32 temp;
801
	u32 enable_bits = SDVO_ENABLE | SDVO_AUDIO_ENABLE;
802

803
	temp = I915_READ(intel_hdmi->hdmi_reg);
804 805 806 807 808 809 810 811 812

	/* HW workaround for IBX, we need to move the port to transcoder A
	 * before disabling it. */
	if (HAS_PCH_IBX(dev)) {
		struct drm_crtc *crtc = encoder->base.crtc;
		int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;

		if (temp & SDVO_PIPE_B_SELECT) {
			temp &= ~SDVO_PIPE_B_SELECT;
813 814
			I915_WRITE(intel_hdmi->hdmi_reg, temp);
			POSTING_READ(intel_hdmi->hdmi_reg);
815 816

			/* Again we need to write this twice. */
817 818
			I915_WRITE(intel_hdmi->hdmi_reg, temp);
			POSTING_READ(intel_hdmi->hdmi_reg);
819 820 821 822 823 824 825 826

			/* Transcoder selection bits only update
			 * effectively on vblank. */
			if (crtc)
				intel_wait_for_vblank(dev, pipe);
			else
				msleep(50);
		}
827
	}
828

829 830 831 832
	/* HW workaround, need to toggle enable bit off and on for 12bpc, but
	 * we do this anyway which shows more stable in testing.
	 */
	if (HAS_PCH_SPLIT(dev)) {
833 834
		I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
		POSTING_READ(intel_hdmi->hdmi_reg);
835 836 837
	}

	temp &= ~enable_bits;
838

839 840
	I915_WRITE(intel_hdmi->hdmi_reg, temp);
	POSTING_READ(intel_hdmi->hdmi_reg);
841 842 843 844

	/* HW workaround, need to write this twice for issue that may result
	 * in first write getting masked.
	 */
845
	if (HAS_PCH_SPLIT(dev)) {
846 847
		I915_WRITE(intel_hdmi->hdmi_reg, temp);
		POSTING_READ(intel_hdmi->hdmi_reg);
848
	}
849 850
}

851
static int hdmi_portclock_limit(struct intel_hdmi *hdmi, bool respect_dvi_limit)
852 853 854
{
	struct drm_device *dev = intel_hdmi_to_dev(hdmi);

855
	if ((respect_dvi_limit && !hdmi->has_hdmi_sink) || IS_G4X(dev))
856
		return 165000;
857
	else if (IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8)
858 859 860 861 862
		return 300000;
	else
		return 225000;
}

863 864 865
static enum drm_mode_status
intel_hdmi_mode_valid(struct drm_connector *connector,
		      struct drm_display_mode *mode)
866
{
867 868
	if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector),
					       true))
869 870
		return MODE_CLOCK_HIGH;
	if (mode->clock < 20000)
871
		return MODE_CLOCK_LOW;
872 873 874 875 876 877 878

	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
		return MODE_NO_DBLESCAN;

	return MODE_OK;
}

879 880 881 882 883 884
static bool hdmi_12bpc_possible(struct intel_crtc *crtc)
{
	struct drm_device *dev = crtc->base.dev;
	struct intel_encoder *encoder;
	int count = 0, count_hdmi = 0;

885
	if (HAS_GMCH_DISPLAY(dev))
886 887 888 889 890 891 892 893 894 895 896 897 898 899 900 901 902
		return false;

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		if (encoder->new_crtc != crtc)
			continue;

		count_hdmi += encoder->type == INTEL_OUTPUT_HDMI;
		count++;
	}

	/*
	 * HDMI 12bpc affects the clocks, so it's only possible
	 * when not cloning with other encoder types.
	 */
	return count_hdmi > 0 && count_hdmi == count;
}

903 904
bool intel_hdmi_compute_config(struct intel_encoder *encoder,
			       struct intel_crtc_config *pipe_config)
905
{
906 907 908
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
909
	int clock_12bpc = pipe_config->adjusted_mode.crtc_clock * 3 / 2;
910
	int portclock_limit = hdmi_portclock_limit(intel_hdmi, false);
911
	int desired_bpp;
912

913 914
	pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;

915 916
	if (intel_hdmi->color_range_auto) {
		/* See CEA-861-E - 5.1 Default Encoding Parameters */
917
		if (pipe_config->has_hdmi_sink &&
918
		    drm_match_cea_mode(adjusted_mode) > 1)
919
			intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
920 921 922 923
		else
			intel_hdmi->color_range = 0;
	}

924
	if (intel_hdmi->color_range)
925
		pipe_config->limited_color_range = true;
926

927 928 929
	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev))
		pipe_config->has_pch_encoder = true;

930 931 932
	if (pipe_config->has_hdmi_sink && intel_hdmi->has_audio)
		pipe_config->has_audio = true;

933 934 935
	/*
	 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
	 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
936 937
	 * outputs. We also need to check that the higher clock still fits
	 * within limits.
938
	 */
939
	if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink &&
940 941
	    clock_12bpc <= portclock_limit &&
	    hdmi_12bpc_possible(encoder->new_crtc)) {
942 943
		DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
		desired_bpp = 12*3;
944 945

		/* Need to adjust the port link by 1.5x for 12bpc. */
946
		pipe_config->port_clock = clock_12bpc;
947
	} else {
948 949 950 951 952 953 954
		DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
		desired_bpp = 8*3;
	}

	if (!pipe_config->bw_constrained) {
		DRM_DEBUG_KMS("forcing pipe bpc to %i for HDMI\n", desired_bpp);
		pipe_config->pipe_bpp = desired_bpp;
955 956
	}

957
	if (adjusted_mode->crtc_clock > portclock_limit) {
958 959 960 961
		DRM_DEBUG_KMS("too high HDMI clock, rejecting mode\n");
		return false;
	}

962 963 964
	return true;
}

965
static enum drm_connector_status
966
intel_hdmi_detect(struct drm_connector *connector, bool force)
967
{
968
	struct drm_device *dev = connector->dev;
969
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
970 971 972
	struct intel_digital_port *intel_dig_port =
		hdmi_to_dig_port(intel_hdmi);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
973
	struct drm_i915_private *dev_priv = dev->dev_private;
974
	struct edid *edid;
975
	enum intel_display_power_domain power_domain;
976
	enum drm_connector_status status = connector_status_disconnected;
977

978
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
979
		      connector->base.id, connector->name);
980

981 982 983
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);

C
Chris Wilson 已提交
984
	intel_hdmi->has_hdmi_sink = false;
985
	intel_hdmi->has_audio = false;
986
	intel_hdmi->rgb_quant_range_selectable = false;
987
	edid = drm_get_edid(connector,
988 989
			    intel_gmbus_get_adapter(dev_priv,
						    intel_hdmi->ddc_bus));
990

991
	if (edid) {
992
		if (edid->input & DRM_EDID_INPUT_DIGITAL) {
993
			status = connector_status_connected;
994 995 996
			if (intel_hdmi->force_audio != HDMI_AUDIO_OFF_DVI)
				intel_hdmi->has_hdmi_sink =
						drm_detect_hdmi_monitor(edid);
997
			intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
998 999
			intel_hdmi->rgb_quant_range_selectable =
				drm_rgb_quant_range_selectable(edid);
1000 1001
		}
		kfree(edid);
1002
	}
1003

1004
	if (status == connector_status_connected) {
1005 1006 1007
		if (intel_hdmi->force_audio != HDMI_AUDIO_AUTO)
			intel_hdmi->has_audio =
				(intel_hdmi->force_audio == HDMI_AUDIO_ON);
1008
		intel_encoder->type = INTEL_OUTPUT_HDMI;
1009 1010
	}

1011 1012
	intel_display_power_put(dev_priv, power_domain);

1013
	return status;
1014 1015 1016 1017
}

static int intel_hdmi_get_modes(struct drm_connector *connector)
{
1018 1019
	struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
1020
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
1021 1022
	enum intel_display_power_domain power_domain;
	int ret;
1023 1024 1025 1026 1027

	/* We should parse the EDID data and find out if it's an HDMI sink so
	 * we can send audio to it.
	 */

1028 1029 1030 1031
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);

	ret = intel_ddc_get_modes(connector,
1032 1033
				   intel_gmbus_get_adapter(dev_priv,
							   intel_hdmi->ddc_bus));
1034 1035 1036 1037

	intel_display_power_put(dev_priv, power_domain);

	return ret;
1038 1039
}

1040 1041 1042
static bool
intel_hdmi_detect_audio(struct drm_connector *connector)
{
1043 1044
	struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
1045
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
1046
	enum intel_display_power_domain power_domain;
1047 1048 1049
	struct edid *edid;
	bool has_audio = false;

1050 1051 1052
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);

1053
	edid = drm_get_edid(connector,
1054 1055
			    intel_gmbus_get_adapter(dev_priv,
						    intel_hdmi->ddc_bus));
1056 1057 1058 1059 1060 1061
	if (edid) {
		if (edid->input & DRM_EDID_INPUT_DIGITAL)
			has_audio = drm_detect_monitor_audio(edid);
		kfree(edid);
	}

1062 1063
	intel_display_power_put(dev_priv, power_domain);

1064 1065 1066
	return has_audio;
}

1067 1068
static int
intel_hdmi_set_property(struct drm_connector *connector,
1069 1070
			struct drm_property *property,
			uint64_t val)
1071 1072
{
	struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1073 1074
	struct intel_digital_port *intel_dig_port =
		hdmi_to_dig_port(intel_hdmi);
1075
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
1076 1077
	int ret;

1078
	ret = drm_object_property_set_value(&connector->base, property, val);
1079 1080 1081
	if (ret)
		return ret;

1082
	if (property == dev_priv->force_audio_property) {
1083
		enum hdmi_force_audio i = val;
1084 1085 1086
		bool has_audio;

		if (i == intel_hdmi->force_audio)
1087 1088
			return 0;

1089
		intel_hdmi->force_audio = i;
1090

1091
		if (i == HDMI_AUDIO_AUTO)
1092 1093
			has_audio = intel_hdmi_detect_audio(connector);
		else
1094
			has_audio = (i == HDMI_AUDIO_ON);
1095

1096 1097
		if (i == HDMI_AUDIO_OFF_DVI)
			intel_hdmi->has_hdmi_sink = 0;
1098

1099
		intel_hdmi->has_audio = has_audio;
1100 1101 1102
		goto done;
	}

1103
	if (property == dev_priv->broadcast_rgb_property) {
1104 1105 1106
		bool old_auto = intel_hdmi->color_range_auto;
		uint32_t old_range = intel_hdmi->color_range;

1107 1108 1109 1110 1111 1112 1113 1114 1115 1116
		switch (val) {
		case INTEL_BROADCAST_RGB_AUTO:
			intel_hdmi->color_range_auto = true;
			break;
		case INTEL_BROADCAST_RGB_FULL:
			intel_hdmi->color_range_auto = false;
			intel_hdmi->color_range = 0;
			break;
		case INTEL_BROADCAST_RGB_LIMITED:
			intel_hdmi->color_range_auto = false;
1117
			intel_hdmi->color_range = HDMI_COLOR_RANGE_16_235;
1118 1119 1120 1121
			break;
		default:
			return -EINVAL;
		}
1122 1123 1124 1125 1126

		if (old_auto == intel_hdmi->color_range_auto &&
		    old_range == intel_hdmi->color_range)
			return 0;

1127 1128 1129
		goto done;
	}

1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146
	if (property == connector->dev->mode_config.aspect_ratio_property) {
		switch (val) {
		case DRM_MODE_PICTURE_ASPECT_NONE:
			intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
			break;
		case DRM_MODE_PICTURE_ASPECT_4_3:
			intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_4_3;
			break;
		case DRM_MODE_PICTURE_ASPECT_16_9:
			intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_16_9;
			break;
		default:
			return -EINVAL;
		}
		goto done;
	}

1147 1148 1149
	return -EINVAL;

done:
1150 1151
	if (intel_dig_port->base.base.crtc)
		intel_crtc_restore_mode(intel_dig_port->base.base.crtc);
1152 1153 1154 1155

	return 0;
}

1156 1157 1158 1159 1160 1161 1162
static void intel_hdmi_pre_enable(struct intel_encoder *encoder)
{
	struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
	struct drm_display_mode *adjusted_mode =
		&intel_crtc->config.adjusted_mode;

1163 1164
	intel_hdmi_prepare(encoder);

1165 1166 1167
	intel_hdmi->set_infoframes(&encoder->base,
				   intel_crtc->config.has_hdmi_sink,
				   adjusted_mode);
1168 1169
}

1170
static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1171 1172
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1173
	struct intel_hdmi *intel_hdmi = &dport->hdmi;
1174 1175 1176 1177
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
1178 1179
	struct drm_display_mode *adjusted_mode =
		&intel_crtc->config.adjusted_mode;
1180
	enum dpio_channel port = vlv_dport_to_channel(dport);
1181 1182 1183 1184
	int pipe = intel_crtc->pipe;
	u32 val;

	/* Enable clock channels for this port */
1185
	mutex_lock(&dev_priv->dpio_lock);
1186
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1187 1188 1189 1190 1191 1192
	val = 0;
	if (pipe)
		val |= (1<<21);
	else
		val &= ~(1<<21);
	val |= 0x001000c4;
1193
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1194 1195

	/* HDMI 1.0V-2dB */
1196 1197 1198 1199 1200 1201 1202 1203
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
	vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1204 1205

	/* Program lane clock */
1206 1207
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1208
	mutex_unlock(&dev_priv->dpio_lock);
1209

1210 1211 1212
	intel_hdmi->set_infoframes(&encoder->base,
				   intel_crtc->config.has_hdmi_sink,
				   adjusted_mode);
1213

1214 1215
	intel_enable_hdmi(encoder);

1216
	vlv_wait_port_ready(dev_priv, dport);
1217 1218
}

1219
static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1220 1221 1222 1223
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1224 1225
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
1226
	enum dpio_channel port = vlv_dport_to_channel(dport);
1227
	int pipe = intel_crtc->pipe;
1228

1229 1230
	intel_hdmi_prepare(encoder);

1231
	/* Program Tx lane resets to default */
1232
	mutex_lock(&dev_priv->dpio_lock);
1233
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1234 1235
			 DPIO_PCS_TX_LANE2_RESET |
			 DPIO_PCS_TX_LANE1_RESET);
1236
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1237 1238 1239 1240 1241 1242
			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
			 DPIO_PCS_CLK_SOFT_RESET);

	/* Fix up inter-pair skew failure */
1243 1244 1245 1246 1247 1248
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);

	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1249
	mutex_unlock(&dev_priv->dpio_lock);
1250 1251
}

1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262
static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel ch = vlv_dport_to_channel(dport);
	enum pipe pipe = intel_crtc->pipe;
	u32 val;

1263 1264
	intel_hdmi_prepare(encoder);

1265 1266
	mutex_lock(&dev_priv->dpio_lock);

1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285
	/* program left/right clock distribution */
	if (pipe != PIPE_B) {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
		if (ch == DPIO_CH0)
			val |= CHV_BUFLEFTENA1_FORCE;
		if (ch == DPIO_CH1)
			val |= CHV_BUFRIGHTENA1_FORCE;
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
	} else {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
		if (ch == DPIO_CH0)
			val |= CHV_BUFLEFTENA2_FORCE;
		if (ch == DPIO_CH1)
			val |= CHV_BUFRIGHTENA2_FORCE;
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
	}

1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317
	/* program clock channel usage */
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
	if (pipe != PIPE_B)
		val &= ~CHV_PCS_USEDCLKCHANNEL;
	else
		val |= CHV_PCS_USEDCLKCHANNEL;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
	if (pipe != PIPE_B)
		val &= ~CHV_PCS_USEDCLKCHANNEL;
	else
		val |= CHV_PCS_USEDCLKCHANNEL;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);

	/*
	 * This a a bit weird since generally CL
	 * matches the pipe, but here we need to
	 * pick the CL based on the port.
	 */
	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
	if (pipe != PIPE_B)
		val &= ~CHV_CMN_USEDCLKCHANNEL;
	else
		val |= CHV_CMN_USEDCLKCHANNEL;
	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);

	mutex_unlock(&dev_priv->dpio_lock);
}

1318
static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1319 1320 1321
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1322 1323
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
1324
	enum dpio_channel port = vlv_dport_to_channel(dport);
1325
	int pipe = intel_crtc->pipe;
1326 1327 1328

	/* Reset lanes to avoid HDMI flicker (VLV w/a) */
	mutex_lock(&dev_priv->dpio_lock);
1329 1330
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1331 1332 1333
	mutex_unlock(&dev_priv->dpio_lock);
}

1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347
static void chv_hdmi_post_disable(struct intel_encoder *encoder)
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel ch = vlv_dport_to_channel(dport);
	enum pipe pipe = intel_crtc->pipe;
	u32 val;

	mutex_lock(&dev_priv->dpio_lock);

	/* Propagate soft reset to data lane reset */
1348
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1349
	val |= CHV_PCS_REQ_SOFTRESET_EN;
1350
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1351

1352 1353 1354 1355 1356 1357 1358 1359 1360
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
	val |= CHV_PCS_REQ_SOFTRESET_EN;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1361
	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1362
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1363 1364 1365 1366

	mutex_unlock(&dev_priv->dpio_lock);
}

1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379
static void chv_hdmi_pre_enable(struct intel_encoder *encoder)
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel ch = vlv_dport_to_channel(dport);
	int pipe = intel_crtc->pipe;
	int data, i;
	u32 val;

	mutex_lock(&dev_priv->dpio_lock);
1380 1381

	/* Deassert soft data lane reset*/
1382
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1383
	val |= CHV_PCS_REQ_SOFTRESET_EN;
1384 1385 1386 1387 1388 1389 1390 1391 1392
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
	val |= CHV_PCS_REQ_SOFTRESET_EN;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
1393

1394
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
1395
	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
1396
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
1397 1398

	/* Program Tx latency optimal setting */
1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414
	for (i = 0; i < 4; i++) {
		/* Set the latency optimal bit */
		data = (i == 1) ? 0x0 : 0x6;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
				data << DPIO_FRC_LATENCY_SHFIT);

		/* Set the upar bit */
		data = (i == 1) ? 0x0 : 0x1;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
				data << DPIO_UPAR_SHIFT);
	}

	/* Data lane stagger programming */
	/* FIXME: Fix up value only after power analysis */

	/* Clear calc init */
1415 1416 1417 1418 1419 1420 1421
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1422 1423 1424

	/* FIXME: Program the support xxx V-dB */
	/* Use 800mV-0dB */
1425 1426 1427 1428 1429 1430
	for (i = 0; i < 4; i++) {
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
		val |= 128 << DPIO_SWING_DEEMPH9P5_SHIFT;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
	}
1431

1432 1433 1434 1435 1436 1437
	for (i = 0; i < 4; i++) {
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
		val &= ~DPIO_SWING_MARGIN_MASK;
		val |= 102 << DPIO_SWING_MARGIN_SHIFT;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
	}
1438 1439

	/* Disable unique transition scale */
1440 1441 1442 1443 1444
	for (i = 0; i < 4; i++) {
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
		val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
	}
1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459

	/* Additional steps for 1200mV-0dB */
#if 0
	val = vlv_dpio_read(dev_priv, pipe, VLV_TX_DW3(ch));
	if (ch)
		val |= DPIO_TX_UNIQ_TRANS_SCALE_CH1;
	else
		val |= DPIO_TX_UNIQ_TRANS_SCALE_CH0;
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(ch), val);

	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(ch),
			vlv_dpio_read(dev_priv, pipe, VLV_TX_DW2(ch)) |
				(0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT));
#endif
	/* Start swing calculation */
1460 1461 1462 1463 1464 1465 1466
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
1467 1468 1469 1470 1471 1472 1473 1474 1475 1476 1477 1478 1479

	/* LRC Bypass */
	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
	val |= DPIO_LRC_BYPASS;
	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);

	mutex_unlock(&dev_priv->dpio_lock);

	intel_enable_hdmi(encoder);

	vlv_wait_port_ready(dev_priv, dport);
}

1480 1481 1482
static void intel_hdmi_destroy(struct drm_connector *connector)
{
	drm_connector_cleanup(connector);
1483
	kfree(connector);
1484 1485 1486
}

static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1487
	.dpms = intel_connector_dpms,
1488 1489
	.detect = intel_hdmi_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
1490
	.set_property = intel_hdmi_set_property,
1491 1492 1493 1494 1495 1496
	.destroy = intel_hdmi_destroy,
};

static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
	.get_modes = intel_hdmi_get_modes,
	.mode_valid = intel_hdmi_mode_valid,
1497
	.best_encoder = intel_best_encoder,
1498 1499 1500
};

static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
C
Chris Wilson 已提交
1501
	.destroy = intel_encoder_destroy,
1502 1503
};

1504 1505 1506 1507 1508 1509 1510 1511 1512
static void
intel_attach_aspect_ratio_property(struct drm_connector *connector)
{
	if (!drm_mode_create_aspect_ratio_property(connector->dev))
		drm_object_attach_property(&connector->base,
			connector->dev->mode_config.aspect_ratio_property,
			DRM_MODE_PICTURE_ASPECT_NONE);
}

1513 1514 1515
static void
intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
{
1516
	intel_attach_force_audio_property(connector);
1517
	intel_attach_broadcast_rgb_property(connector);
1518
	intel_hdmi->color_range_auto = true;
1519 1520
	intel_attach_aspect_ratio_property(connector);
	intel_hdmi->aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1521 1522
}

P
Paulo Zanoni 已提交
1523 1524
void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
			       struct intel_connector *intel_connector)
1525
{
1526 1527 1528 1529
	struct drm_connector *connector = &intel_connector->base;
	struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
1530
	struct drm_i915_private *dev_priv = dev->dev_private;
1531
	enum port port = intel_dig_port->port;
1532

1533
	drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
1534
			   DRM_MODE_CONNECTOR_HDMIA);
1535 1536
	drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);

1537
	connector->interlace_allowed = 1;
1538
	connector->doublescan_allowed = 0;
1539
	connector->stereo_allowed = 1;
1540

1541 1542
	switch (port) {
	case PORT_B:
1543
		intel_hdmi->ddc_bus = GMBUS_PORT_DPB;
1544
		intel_encoder->hpd_pin = HPD_PORT_B;
1545 1546
		break;
	case PORT_C:
1547
		intel_hdmi->ddc_bus = GMBUS_PORT_DPC;
1548
		intel_encoder->hpd_pin = HPD_PORT_C;
1549 1550
		break;
	case PORT_D:
1551 1552 1553 1554
		if (IS_CHERRYVIEW(dev))
			intel_hdmi->ddc_bus = GMBUS_PORT_DPD_CHV;
		else
			intel_hdmi->ddc_bus = GMBUS_PORT_DPD;
1555
		intel_encoder->hpd_pin = HPD_PORT_D;
1556 1557
		break;
	case PORT_A:
1558
		intel_encoder->hpd_pin = HPD_PORT_A;
1559 1560
		/* Internal port only for eDP. */
	default:
1561
		BUG();
1562
	}
1563

1564
	if (IS_VALLEYVIEW(dev)) {
1565
		intel_hdmi->write_infoframe = vlv_write_infoframe;
1566
		intel_hdmi->set_infoframes = vlv_set_infoframes;
1567
	} else if (IS_G4X(dev)) {
1568 1569
		intel_hdmi->write_infoframe = g4x_write_infoframe;
		intel_hdmi->set_infoframes = g4x_set_infoframes;
1570
	} else if (HAS_DDI(dev)) {
1571
		intel_hdmi->write_infoframe = hsw_write_infoframe;
1572
		intel_hdmi->set_infoframes = hsw_set_infoframes;
1573 1574
	} else if (HAS_PCH_IBX(dev)) {
		intel_hdmi->write_infoframe = ibx_write_infoframe;
1575
		intel_hdmi->set_infoframes = ibx_set_infoframes;
1576 1577
	} else {
		intel_hdmi->write_infoframe = cpt_write_infoframe;
1578
		intel_hdmi->set_infoframes = cpt_set_infoframes;
1579
	}
1580

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	if (HAS_DDI(dev))
1582 1583 1584
		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
	else
		intel_connector->get_hw_state = intel_connector_get_hw_state;
1585
	intel_connector->unregister = intel_connector_unregister;
1586 1587 1588 1589

	intel_hdmi_add_properties(intel_hdmi, connector);

	intel_connector_attach_encoder(intel_connector, intel_encoder);
1590
	drm_connector_register(connector);
1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601

	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
}

1602
void intel_hdmi_init(struct drm_device *dev, int hdmi_reg, enum port port)
1603 1604 1605 1606 1607
{
	struct intel_digital_port *intel_dig_port;
	struct intel_encoder *intel_encoder;
	struct intel_connector *intel_connector;

1608
	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
1609 1610 1611
	if (!intel_dig_port)
		return;

1612
	intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
1613 1614 1615 1616 1617 1618 1619 1620 1621
	if (!intel_connector) {
		kfree(intel_dig_port);
		return;
	}

	intel_encoder = &intel_dig_port->base;

	drm_encoder_init(dev, &intel_encoder->base, &intel_hdmi_enc_funcs,
			 DRM_MODE_ENCODER_TMDS);
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1622

1623
	intel_encoder->compute_config = intel_hdmi_compute_config;
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1624 1625
	intel_encoder->disable = intel_disable_hdmi;
	intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
1626
	intel_encoder->get_config = intel_hdmi_get_config;
1627
	if (IS_CHERRYVIEW(dev)) {
1628
		intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
1629 1630
		intel_encoder->pre_enable = chv_hdmi_pre_enable;
		intel_encoder->enable = vlv_enable_hdmi;
1631
		intel_encoder->post_disable = chv_hdmi_post_disable;
1632
	} else if (IS_VALLEYVIEW(dev)) {
1633 1634
		intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
		intel_encoder->pre_enable = vlv_hdmi_pre_enable;
1635
		intel_encoder->enable = vlv_enable_hdmi;
1636
		intel_encoder->post_disable = vlv_hdmi_post_disable;
1637
	} else {
1638
		intel_encoder->pre_enable = intel_hdmi_pre_enable;
1639
		intel_encoder->enable = intel_enable_hdmi;
1640
	}
1641

1642
	intel_encoder->type = INTEL_OUTPUT_HDMI;
1643 1644 1645 1646 1647 1648 1649 1650
	if (IS_CHERRYVIEW(dev)) {
		if (port == PORT_D)
			intel_encoder->crtc_mask = 1 << 2;
		else
			intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
	} else {
		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
	}
1651
	intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
1652 1653 1654 1655 1656 1657 1658
	/*
	 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
	 * to work on real hardware. And since g4x can send infoframes to
	 * only one port anyway, nothing is lost by allowing it.
	 */
	if (IS_G4X(dev))
		intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
1659

1660
	intel_dig_port->port = port;
1661
	intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
1662
	intel_dig_port->dp.output_reg = 0;
1663

1664
	intel_hdmi_init_connector(intel_dig_port, intel_connector);
1665
}