intel_dp.c 137.2 KB
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/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <linux/notifier.h>
#include <linux/reboot.h>
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#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
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#include "intel_drv.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"

#define DP_LINK_CHECK_TIMEOUT	(10 * 1000)

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struct dp_link_dpll {
	int link_bw;
	struct dpll dpll;
};

static const struct dp_link_dpll gen4_dpll[] = {
	{ DP_LINK_BW_1_62,
		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
	{ DP_LINK_BW_2_7,
		{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
};

static const struct dp_link_dpll pch_dpll[] = {
	{ DP_LINK_BW_1_62,
		{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
	{ DP_LINK_BW_2_7,
		{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
};

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static const struct dp_link_dpll vlv_dpll[] = {
	{ DP_LINK_BW_1_62,
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		{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
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	{ DP_LINK_BW_2_7,
		{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
};

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/*
 * CHV supports eDP 1.4 that have  more link rates.
 * Below only provides the fixed rate but exclude variable rate.
 */
static const struct dp_link_dpll chv_dpll[] = {
	/*
	 * CHV requires to program fractional division for m2.
	 * m2 is stored in fixed point format using formula below
	 * (m2_int << 22) | m2_fraction
	 */
	{ DP_LINK_BW_1_62,	/* m2_int = 32, m2_fraction = 1677722 */
		{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
	{ DP_LINK_BW_2_7,	/* m2_int = 27, m2_fraction = 0 */
		{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
	{ DP_LINK_BW_5_4,	/* m2_int = 27, m2_fraction = 0 */
		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
};

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/**
 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 * @intel_dp: DP struct
 *
 * If a CPU or PCH DP output is attached to an eDP panel, this function
 * will return true, and false otherwise.
 */
static bool is_edp(struct intel_dp *intel_dp)
{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
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}

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static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
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{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.base.dev;
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}

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static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
{
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	return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
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}

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static void intel_dp_link_down(struct intel_dp *intel_dp);
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static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
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static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
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int
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intel_dp_max_link_bw(struct intel_dp *intel_dp)
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{
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	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
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	struct drm_device *dev = intel_dp->attached_connector->base.dev;
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	switch (max_link_bw) {
	case DP_LINK_BW_1_62:
	case DP_LINK_BW_2_7:
		break;
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	case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
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		if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
		     INTEL_INFO(dev)->gen >= 8) &&
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		    intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
			max_link_bw = DP_LINK_BW_5_4;
		else
			max_link_bw = DP_LINK_BW_2_7;
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		break;
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	default:
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		WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
		     max_link_bw);
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		max_link_bw = DP_LINK_BW_1_62;
		break;
	}
	return max_link_bw;
}

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static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	u8 source_max, sink_max;

	source_max = 4;
	if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
	    (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
		source_max = 2;

	sink_max = drm_dp_max_lane_count(intel_dp->dpcd);

	return min(source_max, sink_max);
}

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/*
 * The units on the numbers in the next two are... bizarre.  Examples will
 * make it clearer; this one parallels an example in the eDP spec.
 *
 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 *
 *     270000 * 1 * 8 / 10 == 216000
 *
 * The actual data capacity of that configuration is 2.16Gbit/s, so the
 * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 * 119000.  At 18bpp that's 2142000 kilobits per second.
 *
 * Thus the strange-looking division by 10 in intel_dp_link_required, to
 * get the result in decakilobits instead of kilobits.
 */

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static int
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intel_dp_link_required(int pixel_clock, int bpp)
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{
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	return (pixel_clock * bpp + 9) / 10;
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}

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static int
intel_dp_max_data_rate(int max_link_clock, int max_lanes)
{
	return (max_link_clock * max_lanes * 8) / 10;
}

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static enum drm_mode_status
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intel_dp_mode_valid(struct drm_connector *connector,
		    struct drm_display_mode *mode)
{
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	struct intel_dp *intel_dp = intel_attached_dp(connector);
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	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
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	int target_clock = mode->clock;
	int max_rate, mode_rate, max_lanes, max_link_clock;
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	if (is_edp(intel_dp) && fixed_mode) {
		if (mode->hdisplay > fixed_mode->hdisplay)
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			return MODE_PANEL;

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		if (mode->vdisplay > fixed_mode->vdisplay)
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			return MODE_PANEL;
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		target_clock = fixed_mode->clock;
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	}

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	max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
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	max_lanes = intel_dp_max_lane_count(intel_dp);
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	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
	mode_rate = intel_dp_link_required(target_clock, 18);

	if (mode_rate > max_rate)
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		return MODE_CLOCK_HIGH;
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	if (mode->clock < 10000)
		return MODE_CLOCK_LOW;

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	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		return MODE_H_ILLEGAL;

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	return MODE_OK;
}

static uint32_t
pack_aux(uint8_t *src, int src_bytes)
{
	int	i;
	uint32_t v = 0;

	if (src_bytes > 4)
		src_bytes = 4;
	for (i = 0; i < src_bytes; i++)
		v |= ((uint32_t) src[i]) << ((3-i) * 8);
	return v;
}

static void
unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
{
	int i;
	if (dst_bytes > 4)
		dst_bytes = 4;
	for (i = 0; i < dst_bytes; i++)
		dst[i] = src >> ((3-i) * 8);
}

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/* hrawclock is 1/4 the FSB frequency */
static int
intel_hrawclk(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t clkcfg;

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	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
	if (IS_VALLEYVIEW(dev))
		return 200;

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	clkcfg = I915_READ(CLKCFG);
	switch (clkcfg & CLKCFG_FSB_MASK) {
	case CLKCFG_FSB_400:
		return 100;
	case CLKCFG_FSB_533:
		return 133;
	case CLKCFG_FSB_667:
		return 166;
	case CLKCFG_FSB_800:
		return 200;
	case CLKCFG_FSB_1067:
		return 266;
	case CLKCFG_FSB_1333:
		return 333;
	/* these two are just a guess; one of them might be right */
	case CLKCFG_FSB_1600:
	case CLKCFG_FSB_1600_ALT:
		return 400;
	default:
		return 133;
	}
}

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static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
				    struct intel_dp *intel_dp,
				    struct edp_power_seq *out);
static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
					      struct intel_dp *intel_dp,
					      struct edp_power_seq *out);

static enum pipe
vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;
	enum pipe pipe;

	/* modeset should have pipe */
	if (crtc)
		return to_intel_crtc(crtc)->pipe;

	/* init time, try to find a pipe with this port selected */
	for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
		u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
			PANEL_PORT_SELECT_MASK;
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		if (port_sel == PANEL_PORT_SELECT_VLV(port))
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			return pipe;
	}

	/* shrug */
	return PIPE_A;
}

static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

	if (HAS_PCH_SPLIT(dev))
		return PCH_PP_CONTROL;
	else
		return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
}

static u32 _pp_stat_reg(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

	if (HAS_PCH_SPLIT(dev))
		return PCH_PP_STATUS;
	else
		return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
}

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/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
   This function only applicable when panel PM state is not to be tracked */
static int edp_notify_handler(struct notifier_block *this, unsigned long code,
			      void *unused)
{
	struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
						 edp_notifier);
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp_div;
	u32 pp_ctrl_reg, pp_div_reg;
	enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

	if (!is_edp(intel_dp) || code != SYS_RESTART)
		return 0;

	if (IS_VALLEYVIEW(dev)) {
		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
		pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
		pp_div = I915_READ(pp_div_reg);
		pp_div &= PP_REFERENCE_DIVIDER_MASK;

		/* 0x1F write to PP_DIV_REG sets max cycle delay */
		I915_WRITE(pp_div_reg, pp_div | 0x1F);
		I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
		msleep(intel_dp->panel_power_cycle_delay);
	}

	return 0;
}

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static bool edp_have_panel_power(struct intel_dp *intel_dp)
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{
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	struct drm_device *dev = intel_dp_to_dev(intel_dp);
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	struct drm_i915_private *dev_priv = dev->dev_private;

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	return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
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}

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static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
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{
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	struct drm_device *dev = intel_dp_to_dev(intel_dp);
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	enum intel_display_power_domain power_domain;
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	power_domain = intel_display_port_power_domain(intel_encoder);
	return intel_display_power_enabled(dev_priv, power_domain) &&
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	       (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
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}

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static void
intel_dp_check_edp(struct intel_dp *intel_dp)
{
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	struct drm_device *dev = intel_dp_to_dev(intel_dp);
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	if (!is_edp(intel_dp))
		return;
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	if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
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		WARN(1, "eDP powered off while attempting aux channel communication.\n");
		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
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			      I915_READ(_pp_stat_reg(intel_dp)),
			      I915_READ(_pp_ctrl_reg(intel_dp)));
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	}
}

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static uint32_t
intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
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	uint32_t status;
	bool done;

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#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
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	if (has_aux_irq)
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		done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
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					  msecs_to_jiffies_timeout(10));
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	else
		done = wait_for_atomic(C, 10) == 0;
	if (!done)
		DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
			  has_aux_irq);
#undef C

	return status;
}

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static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
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{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
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	/*
	 * The clock divider is based off the hrawclk, and would like to run at
	 * 2MHz.  So, take the hrawclk value and divide by 2 and use that
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	 */
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	return index ? 0 : intel_hrawclk(dev) / 2;
}

static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;

	if (index)
		return 0;

	if (intel_dig_port->port == PORT_A) {
		if (IS_GEN6(dev) || IS_GEN7(dev))
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			return 200; /* SNB & IVB eDP input clock at 400Mhz */
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		else
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			return 225; /* eDP input clock at 450Mhz */
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	} else {
		return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
	}
}

static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (intel_dig_port->port == PORT_A) {
		if (index)
			return 0;
		return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
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	} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
		/* Workaround for non-ULT HSW */
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		switch (index) {
		case 0: return 63;
		case 1: return 72;
		default: return 0;
		}
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	} else  {
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		return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
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	}
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}

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static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	return index ? 0 : 100;
}

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static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
				      bool has_aux_irq,
				      int send_bytes,
				      uint32_t aux_clock_divider)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	uint32_t precharge, timeout;

	if (IS_GEN6(dev))
		precharge = 3;
	else
		precharge = 5;

	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
		timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
	else
		timeout = DP_AUX_CH_CTL_TIME_OUT_400us;

	return DP_AUX_CH_CTL_SEND_BUSY |
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	       DP_AUX_CH_CTL_DONE |
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	       (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
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	       DP_AUX_CH_CTL_TIME_OUT_ERROR |
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	       timeout |
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	       DP_AUX_CH_CTL_RECEIVE_ERROR |
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	       (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
	       (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
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	       (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
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}

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static int
intel_dp_aux_ch(struct intel_dp *intel_dp,
		uint8_t *send, int send_bytes,
		uint8_t *recv, int recv_size)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
	uint32_t ch_data = ch_ctl + 4;
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	uint32_t aux_clock_divider;
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	int i, ret, recv_bytes;
	uint32_t status;
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	int try, clock = 0;
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	bool has_aux_irq = HAS_AUX_IRQ(dev);
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	bool vdd;

	vdd = _edp_panel_vdd_on(intel_dp);
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	/* dp aux is extremely sensitive to irq latency, hence request the
	 * lowest possible wakeup latency and so prevent the cpu from going into
	 * deep sleep states.
	 */
	pm_qos_update_request(&dev_priv->pm_qos, 0);

	intel_dp_check_edp(intel_dp);
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	intel_aux_display_runtime_get(dev_priv);

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	/* Try to wait for any previous AUX channel activity */
	for (try = 0; try < 3; try++) {
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		status = I915_READ_NOTRACE(ch_ctl);
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		if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
			break;
		msleep(1);
	}

	if (try == 3) {
		WARN(1, "dp_aux_ch not started status 0x%08x\n",
		     I915_READ(ch_ctl));
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		ret = -EBUSY;
		goto out;
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	}

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	/* Only 5 data registers! */
	if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
		ret = -E2BIG;
		goto out;
	}

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	while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
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		u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
							  has_aux_irq,
							  send_bytes,
							  aux_clock_divider);
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		/* Must try at least 3 times according to DP spec */
		for (try = 0; try < 5; try++) {
			/* Load the send data into the aux channel data registers */
			for (i = 0; i < send_bytes; i += 4)
				I915_WRITE(ch_data + i,
					   pack_aux(send + i, send_bytes - i));

			/* Send the command and wait for it to complete */
583
			I915_WRITE(ch_ctl, send_ctl);
584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599

			status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);

			/* Clear done status and any errors */
			I915_WRITE(ch_ctl,
				   status |
				   DP_AUX_CH_CTL_DONE |
				   DP_AUX_CH_CTL_TIME_OUT_ERROR |
				   DP_AUX_CH_CTL_RECEIVE_ERROR);

			if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
				      DP_AUX_CH_CTL_RECEIVE_ERROR))
				continue;
			if (status & DP_AUX_CH_CTL_DONE)
				break;
		}
600
		if (status & DP_AUX_CH_CTL_DONE)
601 602 603 604
			break;
	}

	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
605
		DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
606 607
		ret = -EBUSY;
		goto out;
608 609 610 611 612
	}

	/* Check for timeout or receive error.
	 * Timeouts occur when the sink is not connected
	 */
613
	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
614
		DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
615 616
		ret = -EIO;
		goto out;
617
	}
618 619 620

	/* Timeouts occur when the device isn't connected, so they're
	 * "normal" -- don't fill the kernel log with these */
621
	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
622
		DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
623 624
		ret = -ETIMEDOUT;
		goto out;
625 626 627 628 629 630 631
	}

	/* Unload any bytes sent back from the other side */
	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
		      DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
	if (recv_bytes > recv_size)
		recv_bytes = recv_size;
632

633 634 635
	for (i = 0; i < recv_bytes; i += 4)
		unpack_aux(I915_READ(ch_data + i),
			   recv + i, recv_bytes - i);
636

637 638 639
	ret = recv_bytes;
out:
	pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
640
	intel_aux_display_runtime_put(dev_priv);
641

642 643 644
	if (vdd)
		edp_panel_vdd_off(intel_dp, false);

645
	return ret;
646 647
}

648 649
#define BARE_ADDRESS_SIZE	3
#define HEADER_SIZE		(BARE_ADDRESS_SIZE + 1)
650 651
static ssize_t
intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
652
{
653 654 655
	struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
	uint8_t txbuf[20], rxbuf[20];
	size_t txsize, rxsize;
656 657
	int ret;

658 659 660 661
	txbuf[0] = msg->request << 4;
	txbuf[1] = msg->address >> 8;
	txbuf[2] = msg->address & 0xff;
	txbuf[3] = msg->size - 1;
662

663 664 665
	switch (msg->request & ~DP_AUX_I2C_MOT) {
	case DP_AUX_NATIVE_WRITE:
	case DP_AUX_I2C_WRITE:
666
		txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
667
		rxsize = 1;
668

669 670
		if (WARN_ON(txsize > 20))
			return -E2BIG;
671

672
		memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
673

674 675 676
		ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
		if (ret > 0) {
			msg->reply = rxbuf[0] >> 4;
677

678 679 680 681
			/* Return payload size. */
			ret = msg->size;
		}
		break;
682

683 684
	case DP_AUX_NATIVE_READ:
	case DP_AUX_I2C_READ:
685
		txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
686
		rxsize = msg->size + 1;
687

688 689
		if (WARN_ON(rxsize > 20))
			return -E2BIG;
690

691 692 693 694 695 696 697 698 699 700 701
		ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
		if (ret > 0) {
			msg->reply = rxbuf[0] >> 4;
			/*
			 * Assume happy day, and copy the data. The caller is
			 * expected to check msg->reply before touching it.
			 *
			 * Return payload size.
			 */
			ret--;
			memcpy(msg->buffer, rxbuf + 1, ret);
702
		}
703 704 705 706 707
		break;

	default:
		ret = -EINVAL;
		break;
708
	}
709

710
	return ret;
711 712
}

713 714 715 716
static void
intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
717 718
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	enum port port = intel_dig_port->port;
719
	const char *name = NULL;
720 721
	int ret;

722 723 724
	switch (port) {
	case PORT_A:
		intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
725
		name = "DPDDC-A";
726
		break;
727 728
	case PORT_B:
		intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
729
		name = "DPDDC-B";
730
		break;
731 732
	case PORT_C:
		intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
733
		name = "DPDDC-C";
734
		break;
735 736
	case PORT_D:
		intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
737
		name = "DPDDC-D";
738 739 740
		break;
	default:
		BUG();
741 742
	}

743 744
	if (!HAS_DDI(dev))
		intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
745

746
	intel_dp->aux.name = name;
747 748
	intel_dp->aux.dev = dev->dev;
	intel_dp->aux.transfer = intel_dp_aux_transfer;
749

750 751
	DRM_DEBUG_KMS("registering %s bus for %s\n", name,
		      connector->base.kdev->kobj.name);
752

753
	ret = drm_dp_aux_register(&intel_dp->aux);
754
	if (ret < 0) {
755
		DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
756 757
			  name, ret);
		return;
758
	}
759

760 761 762 763 764
	ret = sysfs_create_link(&connector->base.kdev->kobj,
				&intel_dp->aux.ddc.dev.kobj,
				intel_dp->aux.ddc.dev.kobj.name);
	if (ret < 0) {
		DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
765
		drm_dp_aux_unregister(&intel_dp->aux);
766
	}
767 768
}

769 770 771 772 773
static void
intel_dp_connector_unregister(struct intel_connector *intel_connector)
{
	struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);

774 775 776
	if (!intel_connector->mst_port)
		sysfs_remove_link(&intel_connector->base.kdev->kobj,
				  intel_dp->aux.ddc.dev.kobj.name);
777 778 779
	intel_connector_unregister(intel_connector);
}

780 781 782 783 784 785 786 787 788 789 790 791 792 793 794 795
static void
hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
{
	switch (link_bw) {
	case DP_LINK_BW_1_62:
		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
		break;
	case DP_LINK_BW_2_7:
		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
		break;
	case DP_LINK_BW_5_4:
		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
		break;
	}
}

796 797 798 799 800
static void
intel_dp_set_clock(struct intel_encoder *encoder,
		   struct intel_crtc_config *pipe_config, int link_bw)
{
	struct drm_device *dev = encoder->base.dev;
801 802
	const struct dp_link_dpll *divisor = NULL;
	int i, count = 0;
803 804

	if (IS_G4X(dev)) {
805 806
		divisor = gen4_dpll;
		count = ARRAY_SIZE(gen4_dpll);
807
	} else if (HAS_PCH_SPLIT(dev)) {
808 809
		divisor = pch_dpll;
		count = ARRAY_SIZE(pch_dpll);
810 811 812
	} else if (IS_CHERRYVIEW(dev)) {
		divisor = chv_dpll;
		count = ARRAY_SIZE(chv_dpll);
813
	} else if (IS_VALLEYVIEW(dev)) {
814 815
		divisor = vlv_dpll;
		count = ARRAY_SIZE(vlv_dpll);
816
	}
817 818 819 820 821 822 823 824 825

	if (divisor && count) {
		for (i = 0; i < count; i++) {
			if (link_bw == divisor[i].link_bw) {
				pipe_config->dpll = divisor[i].dpll;
				pipe_config->clock_set = true;
				break;
			}
		}
826 827 828
	}
}

P
Paulo Zanoni 已提交
829
bool
830 831
intel_dp_compute_config(struct intel_encoder *encoder,
			struct intel_crtc_config *pipe_config)
832
{
833
	struct drm_device *dev = encoder->base.dev;
834
	struct drm_i915_private *dev_priv = dev->dev_private;
835 836
	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
837
	enum port port = dp_to_dig_port(intel_dp)->port;
838
	struct intel_crtc *intel_crtc = encoder->new_crtc;
839
	struct intel_connector *intel_connector = intel_dp->attached_connector;
840
	int lane_count, clock;
841
	int min_lane_count = 1;
842
	int max_lane_count = intel_dp_max_lane_count(intel_dp);
843
	/* Conveniently, the link BW constants become indices with a shift...*/
844
	int min_clock = 0;
845
	int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
846
	int bpp, mode_rate;
847
	static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
848
	int link_avail, link_clock;
849

850
	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
851 852
		pipe_config->has_pch_encoder = true;

853
	pipe_config->has_dp_encoder = true;
854
	pipe_config->has_drrs = false;
855
	pipe_config->has_audio = intel_dp->has_audio;
856

857 858 859
	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
		intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
				       adjusted_mode);
860 861 862 863
		if (!HAS_PCH_SPLIT(dev))
			intel_gmch_panel_fitting(intel_crtc, pipe_config,
						 intel_connector->panel.fitting_mode);
		else
864 865
			intel_pch_panel_fitting(intel_crtc, pipe_config,
						intel_connector->panel.fitting_mode);
866 867
	}

868
	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
869 870
		return false;

871 872
	DRM_DEBUG_KMS("DP link computation with max lane count %i "
		      "max bw %02x pixel clock %iKHz\n",
873 874
		      max_lane_count, bws[max_clock],
		      adjusted_mode->crtc_clock);
875

876 877
	/* Walk through all bpp values. Luckily they're all nicely spaced with 2
	 * bpc in between. */
878
	bpp = pipe_config->pipe_bpp;
879 880 881 882 883 884 885
	if (is_edp(intel_dp)) {
		if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
			DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
				      dev_priv->vbt.edp_bpp);
			bpp = dev_priv->vbt.edp_bpp;
		}

886 887 888 889 890 891
		if (IS_BROADWELL(dev)) {
			/* Yes, it's an ugly hack. */
			min_lane_count = max_lane_count;
			DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
				      min_lane_count);
		} else if (dev_priv->vbt.edp_lanes) {
892 893 894 895 896 897 898 899 900 901 902
			min_lane_count = min(dev_priv->vbt.edp_lanes,
					     max_lane_count);
			DRM_DEBUG_KMS("using min %u lanes per VBT\n",
				      min_lane_count);
		}

		if (dev_priv->vbt.edp_rate) {
			min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
			DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
				      bws[min_clock]);
		}
903
	}
904

905
	for (; bpp >= 6*3; bpp -= 2*3) {
906 907
		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
						   bpp);
908

909 910
		for (clock = min_clock; clock <= max_clock; clock++) {
			for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
911 912 913 914 915 916 917 918 919 920
				link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
				link_avail = intel_dp_max_data_rate(link_clock,
								    lane_count);

				if (mode_rate <= link_avail) {
					goto found;
				}
			}
		}
	}
921

922
	return false;
923

924
found:
925 926 927 928 929 930
	if (intel_dp->color_range_auto) {
		/*
		 * See:
		 * CEA-861-E - 5.1 Default Encoding Parameters
		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
		 */
931
		if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
932 933 934 935 936
			intel_dp->color_range = DP_COLOR_RANGE_16_235;
		else
			intel_dp->color_range = 0;
	}

937
	if (intel_dp->color_range)
938
		pipe_config->limited_color_range = true;
939

940 941
	intel_dp->link_bw = bws[clock];
	intel_dp->lane_count = lane_count;
942
	pipe_config->pipe_bpp = bpp;
943
	pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
944

945 946
	DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
		      intel_dp->link_bw, intel_dp->lane_count,
947
		      pipe_config->port_clock, bpp);
948 949
	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
		      mode_rate, link_avail);
950

951
	intel_link_compute_m_n(bpp, lane_count,
952 953
			       adjusted_mode->crtc_clock,
			       pipe_config->port_clock,
954
			       &pipe_config->dp_m_n);
955

956 957
	if (intel_connector->panel.downclock_mode != NULL &&
		intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
958
			pipe_config->has_drrs = true;
959 960 961 962 963 964
			intel_link_compute_m_n(bpp, lane_count,
				intel_connector->panel.downclock_mode->clock,
				pipe_config->port_clock,
				&pipe_config->dp_m2_n2);
	}

965
	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
966 967 968
		hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
	else
		intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
969

970
	return true;
971 972
}

973
static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
974
{
975 976 977
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
	struct drm_device *dev = crtc->base.dev;
978 979 980
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

981
	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
982 983 984
	dpa_ctl = I915_READ(DP_A);
	dpa_ctl &= ~DP_PLL_FREQ_MASK;

985
	if (crtc->config.port_clock == 162000) {
986 987 988 989
		/* For a long time we've carried around a ILK-DevA w/a for the
		 * 160MHz clock. If we're really unlucky, it's still required.
		 */
		DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
990
		dpa_ctl |= DP_PLL_FREQ_160MHZ;
991
		intel_dp->DP |= DP_PLL_FREQ_160MHZ;
992 993
	} else {
		dpa_ctl |= DP_PLL_FREQ_270MHZ;
994
		intel_dp->DP |= DP_PLL_FREQ_270MHZ;
995
	}
996

997 998 999 1000 1001 1002
	I915_WRITE(DP_A, dpa_ctl);

	POSTING_READ(DP_A);
	udelay(500);
}

1003
static void intel_dp_prepare(struct intel_encoder *encoder)
1004
{
1005
	struct drm_device *dev = encoder->base.dev;
1006
	struct drm_i915_private *dev_priv = dev->dev_private;
1007
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1008
	enum port port = dp_to_dig_port(intel_dp)->port;
1009 1010
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
1011

1012
	/*
K
Keith Packard 已提交
1013
	 * There are four kinds of DP registers:
1014 1015
	 *
	 * 	IBX PCH
K
Keith Packard 已提交
1016 1017
	 * 	SNB CPU
	 *	IVB CPU
1018 1019 1020 1021 1022 1023 1024 1025 1026 1027
	 * 	CPT PCH
	 *
	 * IBX PCH and CPU are the same for almost everything,
	 * except that the CPU DP PLL is configured in this
	 * register
	 *
	 * CPT PCH is quite different, having many bits moved
	 * to the TRANS_DP_CTL register instead. That
	 * configuration happens (oddly) in ironlake_pch_enable
	 */
1028

1029 1030 1031 1032
	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1033

1034 1035
	/* Handle DP bits in common between all three register formats */
	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1036
	intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1037

1038
	if (crtc->config.has_audio) {
1039
		DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1040
				 pipe_name(crtc->pipe));
C
Chris Wilson 已提交
1041
		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1042
		intel_write_eld(&encoder->base, adjusted_mode);
1043
	}
1044

1045
	/* Split out the IBX/CPU vs CPT settings */
1046

1047
	if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
K
Keith Packard 已提交
1048 1049 1050 1051 1052 1053
		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

1054
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
K
Keith Packard 已提交
1055 1056
			intel_dp->DP |= DP_ENHANCED_FRAMING;

1057
		intel_dp->DP |= crtc->pipe << 29;
1058
	} else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1059
		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1060
			intel_dp->DP |= intel_dp->color_range;
1061 1062 1063 1064 1065 1066 1067

		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF;

1068
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1069 1070
			intel_dp->DP |= DP_ENHANCED_FRAMING;

1071 1072 1073 1074 1075 1076
		if (!IS_CHERRYVIEW(dev)) {
			if (crtc->pipe == 1)
				intel_dp->DP |= DP_PIPEB_SELECT;
		} else {
			intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
		}
1077 1078
	} else {
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1079
	}
1080 1081
}

1082 1083
#define IDLE_ON_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
#define IDLE_ON_VALUE   	(PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1084

1085 1086
#define IDLE_OFF_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
#define IDLE_OFF_VALUE		(0     | PP_SEQUENCE_NONE | 0                     | 0)
1087

1088 1089
#define IDLE_CYCLE_MASK		(PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
#define IDLE_CYCLE_VALUE	(0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1090

1091
static void wait_panel_status(struct intel_dp *intel_dp,
1092 1093
				       u32 mask,
				       u32 value)
1094
{
1095
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1096
	struct drm_i915_private *dev_priv = dev->dev_private;
1097 1098
	u32 pp_stat_reg, pp_ctrl_reg;

1099 1100
	pp_stat_reg = _pp_stat_reg(intel_dp);
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1101

1102
	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1103 1104 1105
			mask, value,
			I915_READ(pp_stat_reg),
			I915_READ(pp_ctrl_reg));
1106

1107
	if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1108
		DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1109 1110
				I915_READ(pp_stat_reg),
				I915_READ(pp_ctrl_reg));
1111
	}
1112 1113

	DRM_DEBUG_KMS("Wait complete\n");
1114
}
1115

1116
static void wait_panel_on(struct intel_dp *intel_dp)
1117 1118
{
	DRM_DEBUG_KMS("Wait for panel power on\n");
1119
	wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1120 1121
}

1122
static void wait_panel_off(struct intel_dp *intel_dp)
1123 1124
{
	DRM_DEBUG_KMS("Wait for panel power off time\n");
1125
	wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1126 1127
}

1128
static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1129 1130
{
	DRM_DEBUG_KMS("Wait for panel power cycle\n");
1131 1132 1133 1134 1135 1136

	/* When we disable the VDD override bit last we have to do the manual
	 * wait. */
	wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
				       intel_dp->panel_power_cycle_delay);

1137
	wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1138 1139
}

1140
static void wait_backlight_on(struct intel_dp *intel_dp)
1141 1142 1143 1144 1145
{
	wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
				       intel_dp->backlight_on_delay);
}

1146
static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1147 1148 1149 1150
{
	wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
				       intel_dp->backlight_off_delay);
}
1151

1152 1153 1154 1155
/* Read the current pp_control value, unlocking the register if it
 * is locked
 */

1156
static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1157
{
1158 1159 1160
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 control;
1161

1162
	control = I915_READ(_pp_ctrl_reg(intel_dp));
1163 1164 1165
	control &= ~PANEL_UNLOCK_MASK;
	control |= PANEL_UNLOCK_REGS;
	return control;
1166 1167
}

1168
static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
1169
{
1170
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1171 1172
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
1173
	struct drm_i915_private *dev_priv = dev->dev_private;
1174
	enum intel_display_power_domain power_domain;
1175
	u32 pp;
1176
	u32 pp_stat_reg, pp_ctrl_reg;
1177
	bool need_to_disable = !intel_dp->want_panel_vdd;
1178

1179
	if (!is_edp(intel_dp))
1180
		return false;
1181 1182

	intel_dp->want_panel_vdd = true;
1183

1184
	if (edp_have_panel_vdd(intel_dp))
1185
		return need_to_disable;
1186

1187 1188
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);
1189

1190
	DRM_DEBUG_KMS("Turning eDP VDD on\n");
1191

1192 1193
	if (!edp_have_panel_power(intel_dp))
		wait_panel_power_cycle(intel_dp);
1194

1195
	pp = ironlake_get_pp_control(intel_dp);
1196
	pp |= EDP_FORCE_VDD;
1197

1198 1199
	pp_stat_reg = _pp_stat_reg(intel_dp);
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1200 1201 1202 1203 1204

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
			I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1205 1206 1207
	/*
	 * If the panel wasn't on, delay before accessing aux channel
	 */
1208
	if (!edp_have_panel_power(intel_dp)) {
1209
		DRM_DEBUG_KMS("eDP was not running\n");
1210 1211
		msleep(intel_dp->panel_power_up_delay);
	}
1212 1213 1214 1215

	return need_to_disable;
}

1216
void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1217 1218 1219 1220 1221 1222
{
	if (is_edp(intel_dp)) {
		bool vdd = _edp_panel_vdd_on(intel_dp);

		WARN(!vdd, "eDP VDD already requested on\n");
	}
1223 1224
}

1225
static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1226
{
1227
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1228 1229
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
1230
	u32 pp_stat_reg, pp_ctrl_reg;
1231

1232
	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1233

1234
	if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1235 1236 1237 1238 1239
		struct intel_digital_port *intel_dig_port =
						dp_to_dig_port(intel_dp);
		struct intel_encoder *intel_encoder = &intel_dig_port->base;
		enum intel_display_power_domain power_domain;

1240 1241
		DRM_DEBUG_KMS("Turning eDP VDD off\n");

1242
		pp = ironlake_get_pp_control(intel_dp);
1243 1244
		pp &= ~EDP_FORCE_VDD;

1245 1246
		pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
		pp_stat_reg = _pp_stat_reg(intel_dp);
1247 1248 1249

		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1250

1251 1252 1253
		/* Make sure sequencer is idle before allowing subsequent activity */
		DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
		I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
P
Paulo Zanoni 已提交
1254 1255

		if ((pp & POWER_TARGET_ON) == 0)
1256
			intel_dp->last_power_cycle = jiffies;
1257

1258 1259
		power_domain = intel_display_port_power_domain(intel_encoder);
		intel_display_power_put(dev_priv, power_domain);
1260 1261
	}
}
1262

1263
static void edp_panel_vdd_work(struct work_struct *__work)
1264 1265 1266
{
	struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
						 struct intel_dp, panel_vdd_work);
1267
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1268

1269
	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1270
	edp_panel_vdd_off_sync(intel_dp);
1271
	drm_modeset_unlock(&dev->mode_config.connection_mutex);
1272 1273
}

1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286
static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
{
	unsigned long delay;

	/*
	 * Queue the timer to fire a long time from now (relative to the power
	 * down delay) to keep the panel power up across a sequence of
	 * operations.
	 */
	delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
	schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
}

1287
static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1288
{
1289 1290
	if (!is_edp(intel_dp))
		return;
1291

1292
	WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1293

1294 1295
	intel_dp->want_panel_vdd = false;

1296
	if (sync)
1297
		edp_panel_vdd_off_sync(intel_dp);
1298 1299
	else
		edp_panel_vdd_schedule_off(intel_dp);
1300 1301
}

1302
void intel_edp_panel_on(struct intel_dp *intel_dp)
1303
{
1304
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1305
	struct drm_i915_private *dev_priv = dev->dev_private;
1306
	u32 pp;
1307
	u32 pp_ctrl_reg;
1308

1309
	if (!is_edp(intel_dp))
1310
		return;
1311 1312 1313

	DRM_DEBUG_KMS("Turn eDP power on\n");

1314
	if (edp_have_panel_power(intel_dp)) {
1315
		DRM_DEBUG_KMS("eDP power already on\n");
1316
		return;
1317
	}
1318

1319
	wait_panel_power_cycle(intel_dp);
1320

1321
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1322
	pp = ironlake_get_pp_control(intel_dp);
1323 1324 1325
	if (IS_GEN5(dev)) {
		/* ILK workaround: disable reset around power sequence */
		pp &= ~PANEL_POWER_RESET;
1326 1327
		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1328
	}
1329

1330
	pp |= POWER_TARGET_ON;
1331 1332 1333
	if (!IS_GEN5(dev))
		pp |= PANEL_POWER_RESET;

1334 1335
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1336

1337
	wait_panel_on(intel_dp);
1338
	intel_dp->last_power_on = jiffies;
1339

1340 1341
	if (IS_GEN5(dev)) {
		pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1342 1343
		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1344
	}
1345 1346
}

1347
void intel_edp_panel_off(struct intel_dp *intel_dp)
1348
{
1349 1350
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
1351
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1352
	struct drm_i915_private *dev_priv = dev->dev_private;
1353
	enum intel_display_power_domain power_domain;
1354
	u32 pp;
1355
	u32 pp_ctrl_reg;
1356

1357 1358
	if (!is_edp(intel_dp))
		return;
1359

1360
	DRM_DEBUG_KMS("Turn eDP power off\n");
1361

1362 1363
	WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");

1364
	pp = ironlake_get_pp_control(intel_dp);
1365 1366
	/* We need to switch off panel power _and_ force vdd, for otherwise some
	 * panels get very unhappy and cease to work. */
1367 1368
	pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
		EDP_BLC_ENABLE);
1369

1370
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1371

1372 1373
	intel_dp->want_panel_vdd = false;

1374 1375
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1376

1377
	intel_dp->last_power_cycle = jiffies;
1378
	wait_panel_off(intel_dp);
1379 1380

	/* We got a reference when we enabled the VDD. */
1381 1382
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_put(dev_priv, power_domain);
1383 1384
}

1385 1386
/* Enable backlight in the panel power control. */
static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
1387
{
1388 1389
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
1390 1391
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
1392
	u32 pp_ctrl_reg;
1393

1394 1395 1396 1397 1398 1399
	/*
	 * If we enable the backlight right away following a panel power
	 * on, we may see slight flicker as the panel syncs with the eDP
	 * link.  So delay a bit to make sure the image is solid before
	 * allowing it to appear.
	 */
1400
	wait_backlight_on(intel_dp);
1401
	pp = ironlake_get_pp_control(intel_dp);
1402
	pp |= EDP_BLC_ENABLE;
1403

1404
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1405 1406 1407

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1408 1409
}

1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 1420 1421 1422 1423
/* Enable backlight PWM and backlight PP control. */
void intel_edp_backlight_on(struct intel_dp *intel_dp)
{
	if (!is_edp(intel_dp))
		return;

	DRM_DEBUG_KMS("\n");

	intel_panel_enable_backlight(intel_dp->attached_connector);
	_intel_edp_backlight_on(intel_dp);
}

/* Disable backlight in the panel power control. */
static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
1424
{
1425
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1426 1427
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
1428
	u32 pp_ctrl_reg;
1429

1430
	pp = ironlake_get_pp_control(intel_dp);
1431
	pp &= ~EDP_BLC_ENABLE;
1432

1433
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1434 1435 1436

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1437
	intel_dp->last_backlight_off = jiffies;
1438 1439

	edp_wait_backlight_off(intel_dp);
1440 1441 1442 1443 1444 1445 1446 1447 1448
}

/* Disable backlight PP control and backlight PWM. */
void intel_edp_backlight_off(struct intel_dp *intel_dp)
{
	if (!is_edp(intel_dp))
		return;

	DRM_DEBUG_KMS("\n");
1449

1450
	_intel_edp_backlight_off(intel_dp);
1451
	intel_panel_disable_backlight(intel_dp->attached_connector);
1452
}
1453

1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474
/*
 * Hook for controlling the panel power control backlight through the bl_power
 * sysfs attribute. Take care to handle multiple calls.
 */
static void intel_edp_backlight_power(struct intel_connector *connector,
				      bool enable)
{
	struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
	bool is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;

	if (is_enabled == enable)
		return;

	DRM_DEBUG_KMS("\n");

	if (enable)
		_intel_edp_backlight_on(intel_dp);
	else
		_intel_edp_backlight_off(intel_dp);
}

1475
static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1476
{
1477 1478 1479
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = crtc->dev;
1480 1481 1482
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

1483 1484 1485
	assert_pipe_disabled(dev_priv,
			     to_intel_crtc(crtc)->pipe);

1486 1487
	DRM_DEBUG_KMS("\n");
	dpa_ctl = I915_READ(DP_A);
1488 1489 1490 1491 1492 1493 1494 1495 1496
	WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");

	/* We don't adjust intel_dp->DP while tearing down the link, to
	 * facilitate link retraining (e.g. after hotplug). Hence clear all
	 * enable bits here to ensure that we don't enable too much. */
	intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
	intel_dp->DP |= DP_PLL_ENABLE;
	I915_WRITE(DP_A, intel_dp->DP);
1497 1498
	POSTING_READ(DP_A);
	udelay(200);
1499 1500
}

1501
static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1502
{
1503 1504 1505
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = crtc->dev;
1506 1507 1508
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

1509 1510 1511
	assert_pipe_disabled(dev_priv,
			     to_intel_crtc(crtc)->pipe);

1512
	dpa_ctl = I915_READ(DP_A);
1513 1514 1515 1516 1517 1518 1519
	WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
	     "dp pll off, should be on\n");
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");

	/* We can't rely on the value tracked for the DP register in
	 * intel_dp->DP because link_down must not change that (otherwise link
	 * re-training will fail. */
1520
	dpa_ctl &= ~DP_PLL_ENABLE;
1521
	I915_WRITE(DP_A, dpa_ctl);
1522
	POSTING_READ(DP_A);
1523 1524 1525
	udelay(200);
}

1526
/* If the sink supports it, try to set the power state appropriately */
1527
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1528 1529 1530 1531 1532 1533 1534 1535
{
	int ret, i;

	/* Should have a valid DPCD by this point */
	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
		return;

	if (mode != DRM_MODE_DPMS_ON) {
1536 1537
		ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
					 DP_SET_POWER_D3);
1538 1539 1540 1541 1542 1543 1544 1545
		if (ret != 1)
			DRM_DEBUG_DRIVER("failed to write sink power state\n");
	} else {
		/*
		 * When turning on, we need to retry for 1ms to give the sink
		 * time to wake up.
		 */
		for (i = 0; i < 3; i++) {
1546 1547
			ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
						 DP_SET_POWER_D0);
1548 1549 1550 1551 1552 1553 1554
			if (ret == 1)
				break;
			msleep(1);
		}
	}
}

1555 1556
static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
				  enum pipe *pipe)
1557
{
1558
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1559
	enum port port = dp_to_dig_port(intel_dp)->port;
1560 1561
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1562 1563 1564 1565 1566 1567 1568 1569
	enum intel_display_power_domain power_domain;
	u32 tmp;

	power_domain = intel_display_port_power_domain(encoder);
	if (!intel_display_power_enabled(dev_priv, power_domain))
		return false;

	tmp = I915_READ(intel_dp->output_reg);
1570 1571 1572 1573

	if (!(tmp & DP_PORT_EN))
		return false;

1574
	if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1575
		*pipe = PORT_TO_PIPE_CPT(tmp);
1576 1577
	} else if (IS_CHERRYVIEW(dev)) {
		*pipe = DP_PORT_TO_PIPE_CHV(tmp);
1578
	} else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598
		*pipe = PORT_TO_PIPE(tmp);
	} else {
		u32 trans_sel;
		u32 trans_dp;
		int i;

		switch (intel_dp->output_reg) {
		case PCH_DP_B:
			trans_sel = TRANS_DP_PORT_SEL_B;
			break;
		case PCH_DP_C:
			trans_sel = TRANS_DP_PORT_SEL_C;
			break;
		case PCH_DP_D:
			trans_sel = TRANS_DP_PORT_SEL_D;
			break;
		default:
			return true;
		}

1599
		for_each_pipe(dev_priv, i) {
1600 1601 1602 1603 1604 1605 1606
			trans_dp = I915_READ(TRANS_DP_CTL(i));
			if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
				*pipe = i;
				return true;
			}
		}

1607 1608 1609
		DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
			      intel_dp->output_reg);
	}
1610

1611 1612
	return true;
}
1613

1614 1615 1616 1617 1618
static void intel_dp_get_config(struct intel_encoder *encoder,
				struct intel_crtc_config *pipe_config)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	u32 tmp, flags = 0;
1619 1620 1621 1622
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = dp_to_dig_port(intel_dp)->port;
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1623
	int dotclock;
1624

1625 1626 1627 1628
	tmp = I915_READ(intel_dp->output_reg);
	if (tmp & DP_AUDIO_OUTPUT_ENABLE)
		pipe_config->has_audio = true;

1629 1630 1631 1632 1633
	if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
		if (tmp & DP_SYNC_HS_HIGH)
			flags |= DRM_MODE_FLAG_PHSYNC;
		else
			flags |= DRM_MODE_FLAG_NHSYNC;
1634

1635 1636 1637 1638 1639 1640 1641 1642 1643 1644
		if (tmp & DP_SYNC_VS_HIGH)
			flags |= DRM_MODE_FLAG_PVSYNC;
		else
			flags |= DRM_MODE_FLAG_NVSYNC;
	} else {
		tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
		if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
			flags |= DRM_MODE_FLAG_PHSYNC;
		else
			flags |= DRM_MODE_FLAG_NHSYNC;
1645

1646 1647 1648 1649 1650
		if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
			flags |= DRM_MODE_FLAG_PVSYNC;
		else
			flags |= DRM_MODE_FLAG_NVSYNC;
	}
1651 1652

	pipe_config->adjusted_mode.flags |= flags;
1653

1654 1655 1656 1657
	pipe_config->has_dp_encoder = true;

	intel_dp_get_m_n(crtc, pipe_config);

1658
	if (port == PORT_A) {
1659 1660 1661 1662 1663
		if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
			pipe_config->port_clock = 162000;
		else
			pipe_config->port_clock = 270000;
	}
1664 1665 1666 1667 1668 1669 1670

	dotclock = intel_dotclock_calculate(pipe_config->port_clock,
					    &pipe_config->dp_m_n);

	if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
		ironlake_check_encoder_dotclock(pipe_config, dotclock);

1671
	pipe_config->adjusted_mode.crtc_clock = dotclock;
1672

1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691
	if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
	    pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
		/*
		 * This is a big fat ugly hack.
		 *
		 * Some machines in UEFI boot mode provide us a VBT that has 18
		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
		 * unknown we fail to light up. Yet the same BIOS boots up with
		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
		 * max, not what it tells us to use.
		 *
		 * Note: This will still be broken if the eDP panel is not lit
		 * up by the BIOS, and thus we can't get the mode at module
		 * load.
		 */
		DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
			      pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
		dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
	}
1692 1693
}

1694
static bool is_edp_psr(struct intel_dp *intel_dp)
1695
{
1696
	return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1697 1698
}

R
Rodrigo Vivi 已提交
1699 1700 1701 1702
static bool intel_edp_is_psr_enabled(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

1703
	if (!HAS_PSR(dev))
R
Rodrigo Vivi 已提交
1704 1705
		return false;

1706
	return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
R
Rodrigo Vivi 已提交
1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752
}

static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
				    struct edp_vsc_psr *vsc_psr)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
	u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
	uint32_t *data = (uint32_t *) vsc_psr;
	unsigned int i;

	/* As per BSPec (Pipe Video Data Island Packet), we need to disable
	   the video DIP being updated before program video DIP data buffer
	   registers for DIP being updated. */
	I915_WRITE(ctl_reg, 0);
	POSTING_READ(ctl_reg);

	for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
		if (i < sizeof(struct edp_vsc_psr))
			I915_WRITE(data_reg + i, *data++);
		else
			I915_WRITE(data_reg + i, 0);
	}

	I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
	POSTING_READ(ctl_reg);
}

static void intel_edp_psr_setup(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct edp_vsc_psr psr_vsc;

	/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
	memset(&psr_vsc, 0, sizeof(psr_vsc));
	psr_vsc.sdp_header.HB0 = 0;
	psr_vsc.sdp_header.HB1 = 0x7;
	psr_vsc.sdp_header.HB2 = 0x2;
	psr_vsc.sdp_header.HB3 = 0x8;
	intel_edp_psr_write_vsc(intel_dp, &psr_vsc);

	/* Avoid continuous PSR exit by masking memup and hpd */
1753
	I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1754
		   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
R
Rodrigo Vivi 已提交
1755 1756 1757 1758
}

static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
{
1759 1760
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
R
Rodrigo Vivi 已提交
1761
	struct drm_i915_private *dev_priv = dev->dev_private;
1762
	uint32_t aux_clock_divider;
R
Rodrigo Vivi 已提交
1763 1764
	int precharge = 0x3;
	int msg_size = 5;       /* Header(4) + Message(1) */
1765
	bool only_standby = false;
R
Rodrigo Vivi 已提交
1766

1767 1768
	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);

1769 1770 1771
	if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
		only_standby = true;

R
Rodrigo Vivi 已提交
1772
	/* Enable PSR in sink */
1773
	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
1774 1775
		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
				   DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
R
Rodrigo Vivi 已提交
1776
	else
1777 1778
		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
				   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
R
Rodrigo Vivi 已提交
1779 1780

	/* Setup AUX registers */
1781 1782 1783
	I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
	I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
	I915_WRITE(EDP_PSR_AUX_CTL(dev),
R
Rodrigo Vivi 已提交
1784 1785 1786 1787 1788 1789 1790 1791
		   DP_AUX_CH_CTL_TIME_OUT_400us |
		   (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
		   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
		   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
}

static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
{
1792 1793
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
R
Rodrigo Vivi 已提交
1794 1795 1796 1797
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t max_sleep_time = 0x1f;
	uint32_t idle_frames = 1;
	uint32_t val = 0x0;
B
Ben Widawsky 已提交
1798
	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1799 1800 1801 1802
	bool only_standby = false;

	if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
		only_standby = true;
R
Rodrigo Vivi 已提交
1803

1804
	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
R
Rodrigo Vivi 已提交
1805 1806 1807 1808
		val |= EDP_PSR_LINK_STANDBY;
		val |= EDP_PSR_TP2_TP3_TIME_0us;
		val |= EDP_PSR_TP1_TIME_0us;
		val |= EDP_PSR_SKIP_AUX_EXIT;
1809
		val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
R
Rodrigo Vivi 已提交
1810 1811 1812
	} else
		val |= EDP_PSR_LINK_DISABLE;

1813
	I915_WRITE(EDP_PSR_CTL(dev), val |
B
Ben Widawsky 已提交
1814
		   (IS_BROADWELL(dev) ? 0 : link_entry_time) |
R
Rodrigo Vivi 已提交
1815 1816 1817 1818 1819
		   max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
		   idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
		   EDP_PSR_ENABLE);
}

1820 1821 1822 1823 1824 1825 1826 1827
static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dig_port->base.base.crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

1828 1829 1830 1831
	lockdep_assert_held(&dev_priv->psr.lock);
	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
	WARN_ON(!drm_modeset_is_locked(&crtc->mutex));

R
Rodrigo Vivi 已提交
1832 1833
	dev_priv->psr.source_ok = false;

1834
	if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
1835 1836 1837 1838
		DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
		return false;
	}

1839
	if (!i915.enable_psr) {
1840 1841 1842 1843
		DRM_DEBUG_KMS("PSR disable by flag\n");
		return false;
	}

1844 1845 1846 1847
	/* Below limitations aren't valid for Broadwell */
	if (IS_BROADWELL(dev))
		goto out;

1848 1849 1850 1851 1852 1853
	if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
	    S3D_ENABLE) {
		DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
		return false;
	}

1854
	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1855 1856 1857 1858
		DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
		return false;
	}

1859
 out:
R
Rodrigo Vivi 已提交
1860
	dev_priv->psr.source_ok = true;
1861 1862 1863
	return true;
}

1864
static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
R
Rodrigo Vivi 已提交
1865
{
1866 1867 1868
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
R
Rodrigo Vivi 已提交
1869

1870 1871
	WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
	WARN_ON(dev_priv->psr.active);
1872
	lockdep_assert_held(&dev_priv->psr.lock);
R
Rodrigo Vivi 已提交
1873 1874 1875 1876 1877 1878

	/* Enable PSR on the panel */
	intel_edp_psr_enable_sink(intel_dp);

	/* Enable PSR on the host */
	intel_edp_psr_enable_source(intel_dp);
1879 1880

	dev_priv->psr.active = true;
R
Rodrigo Vivi 已提交
1881 1882
}

1883 1884 1885
void intel_edp_psr_enable(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1886
	struct drm_i915_private *dev_priv = dev->dev_private;
1887

1888 1889 1890 1891 1892
	if (!HAS_PSR(dev)) {
		DRM_DEBUG_KMS("PSR not supported on this platform\n");
		return;
	}

1893 1894 1895 1896 1897
	if (!is_edp_psr(intel_dp)) {
		DRM_DEBUG_KMS("PSR not supported by this panel\n");
		return;
	}

1898
	mutex_lock(&dev_priv->psr.lock);
1899 1900
	if (dev_priv->psr.enabled) {
		DRM_DEBUG_KMS("PSR already in use\n");
1901
		mutex_unlock(&dev_priv->psr.lock);
1902 1903 1904
		return;
	}

1905 1906
	dev_priv->psr.busy_frontbuffer_bits = 0;

1907 1908 1909
	/* Setup PSR once */
	intel_edp_psr_setup(intel_dp);

1910
	if (intel_edp_psr_match_conditions(intel_dp))
1911
		dev_priv->psr.enabled = intel_dp;
1912
	mutex_unlock(&dev_priv->psr.lock);
1913 1914
}

R
Rodrigo Vivi 已提交
1915 1916 1917 1918 1919
void intel_edp_psr_disable(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;

1920 1921 1922 1923 1924 1925
	mutex_lock(&dev_priv->psr.lock);
	if (!dev_priv->psr.enabled) {
		mutex_unlock(&dev_priv->psr.lock);
		return;
	}

1926 1927 1928 1929 1930 1931 1932 1933
	if (dev_priv->psr.active) {
		I915_WRITE(EDP_PSR_CTL(dev),
			   I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);

		/* Wait till PSR is idle */
		if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
			       EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
			DRM_ERROR("Timed out waiting for PSR Idle State\n");
R
Rodrigo Vivi 已提交
1934

1935 1936 1937 1938
		dev_priv->psr.active = false;
	} else {
		WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
	}
1939

1940
	dev_priv->psr.enabled = NULL;
1941
	mutex_unlock(&dev_priv->psr.lock);
1942 1943

	cancel_delayed_work_sync(&dev_priv->psr.work);
R
Rodrigo Vivi 已提交
1944 1945
}

1946
static void intel_edp_psr_work(struct work_struct *work)
1947 1948 1949
{
	struct drm_i915_private *dev_priv =
		container_of(work, typeof(*dev_priv), psr.work.work);
1950 1951
	struct intel_dp *intel_dp = dev_priv->psr.enabled;

1952 1953 1954
	mutex_lock(&dev_priv->psr.lock);
	intel_dp = dev_priv->psr.enabled;

1955
	if (!intel_dp)
1956
		goto unlock;
1957

1958 1959 1960 1961 1962 1963 1964 1965 1966
	/*
	 * The delayed work can race with an invalidate hence we need to
	 * recheck. Since psr_flush first clears this and then reschedules we
	 * won't ever miss a flush when bailing out here.
	 */
	if (dev_priv->psr.busy_frontbuffer_bits)
		goto unlock;

	intel_edp_psr_do_enable(intel_dp);
1967 1968
unlock:
	mutex_unlock(&dev_priv->psr.lock);
1969 1970
}

1971
static void intel_edp_psr_do_exit(struct drm_device *dev)
1972 1973 1974
{
	struct drm_i915_private *dev_priv = dev->dev_private;

1975 1976 1977 1978 1979 1980 1981 1982 1983
	if (dev_priv->psr.active) {
		u32 val = I915_READ(EDP_PSR_CTL(dev));

		WARN_ON(!(val & EDP_PSR_ENABLE));

		I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);

		dev_priv->psr.active = false;
	}
1984

1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040
}

void intel_edp_psr_invalidate(struct drm_device *dev,
			      unsigned frontbuffer_bits)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
	enum pipe pipe;

	mutex_lock(&dev_priv->psr.lock);
	if (!dev_priv->psr.enabled) {
		mutex_unlock(&dev_priv->psr.lock);
		return;
	}

	crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
	pipe = to_intel_crtc(crtc)->pipe;

	intel_edp_psr_do_exit(dev);

	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);

	dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
	mutex_unlock(&dev_priv->psr.lock);
}

void intel_edp_psr_flush(struct drm_device *dev,
			 unsigned frontbuffer_bits)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
	enum pipe pipe;

	mutex_lock(&dev_priv->psr.lock);
	if (!dev_priv->psr.enabled) {
		mutex_unlock(&dev_priv->psr.lock);
		return;
	}

	crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
	pipe = to_intel_crtc(crtc)->pipe;
	dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;

	/*
	 * On Haswell sprite plane updates don't result in a psr invalidating
	 * signal in the hardware. Which means we need to manually fake this in
	 * software for all flushes, not just when we've seen a preceding
	 * invalidation through frontbuffer rendering.
	 */
	if (IS_HASWELL(dev) &&
	    (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
		intel_edp_psr_do_exit(dev);

	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
		schedule_delayed_work(&dev_priv->psr.work,
				      msecs_to_jiffies(100));
2041
	mutex_unlock(&dev_priv->psr.lock);
2042 2043 2044 2045 2046 2047 2048
}

void intel_edp_psr_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
2049
	mutex_init(&dev_priv->psr.lock);
2050 2051
}

2052
static void intel_disable_dp(struct intel_encoder *encoder)
2053
{
2054
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2055 2056
	enum port port = dp_to_dig_port(intel_dp)->port;
	struct drm_device *dev = encoder->base.dev;
2057 2058 2059

	/* Make sure the panel is off before trying to change the mode. But also
	 * ensure that we have vdd while we switch off the panel. */
2060
	intel_edp_panel_vdd_on(intel_dp);
2061
	intel_edp_backlight_off(intel_dp);
2062
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2063
	intel_edp_panel_off(intel_dp);
2064 2065

	/* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
2066
	if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
2067
		intel_dp_link_down(intel_dp);
2068 2069
}

2070
static void g4x_post_disable_dp(struct intel_encoder *encoder)
2071
{
2072
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2073
	enum port port = dp_to_dig_port(intel_dp)->port;
2074

2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086
	if (port != PORT_A)
		return;

	intel_dp_link_down(intel_dp);
	ironlake_edp_pll_off(intel_dp);
}

static void vlv_post_disable_dp(struct intel_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

	intel_dp_link_down(intel_dp);
2087 2088
}

2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105
static void chv_post_disable_dp(struct intel_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel ch = vlv_dport_to_channel(dport);
	enum pipe pipe = intel_crtc->pipe;
	u32 val;

	intel_dp_link_down(intel_dp);

	mutex_lock(&dev_priv->dpio_lock);

	/* Propagate soft reset to data lane reset */
2106
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2107
	val |= CHV_PCS_REQ_SOFTRESET_EN;
2108
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2109

2110 2111 2112 2113 2114 2115 2116 2117 2118
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
	val |= CHV_PCS_REQ_SOFTRESET_EN;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2119
	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2120
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2121 2122 2123 2124

	mutex_unlock(&dev_priv->dpio_lock);
}

2125
static void intel_enable_dp(struct intel_encoder *encoder)
2126
{
2127 2128 2129 2130
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2131

2132 2133
	if (WARN_ON(dp_reg & DP_PORT_EN))
		return;
2134

2135
	intel_edp_panel_vdd_on(intel_dp);
2136
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2137
	intel_dp_start_link_train(intel_dp);
2138 2139
	intel_edp_panel_on(intel_dp);
	edp_panel_vdd_off(intel_dp, true);
2140
	intel_dp_complete_link_train(intel_dp);
2141
	intel_dp_stop_link_train(intel_dp);
2142
}
2143

2144 2145
static void g4x_enable_dp(struct intel_encoder *encoder)
{
2146 2147
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

2148
	intel_enable_dp(encoder);
2149
	intel_edp_backlight_on(intel_dp);
2150
}
2151

2152 2153
static void vlv_enable_dp(struct intel_encoder *encoder)
{
2154 2155
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

2156
	intel_edp_backlight_on(intel_dp);
2157 2158
}

2159
static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2160 2161 2162 2163
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);

2164 2165
	intel_dp_prepare(encoder);

2166 2167 2168
	/* Only ilk+ has port A */
	if (dport->port == PORT_A) {
		ironlake_set_pll_cpu_edp(intel_dp);
2169
		ironlake_edp_pll_on(intel_dp);
2170
	}
2171 2172 2173
}

static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2174
{
2175
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2176
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2177
	struct drm_device *dev = encoder->base.dev;
2178
	struct drm_i915_private *dev_priv = dev->dev_private;
2179
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2180
	enum dpio_channel port = vlv_dport_to_channel(dport);
2181
	int pipe = intel_crtc->pipe;
2182
	struct edp_power_seq power_seq;
2183
	u32 val;
2184

2185
	mutex_lock(&dev_priv->dpio_lock);
2186

2187
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2188 2189 2190 2191 2192 2193
	val = 0;
	if (pipe)
		val |= (1<<21);
	else
		val &= ~(1<<21);
	val |= 0x001000c4;
2194 2195 2196
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2197

2198 2199
	mutex_unlock(&dev_priv->dpio_lock);

2200 2201 2202 2203 2204 2205
	if (is_edp(intel_dp)) {
		/* init power sequencer on this pipe and port */
		intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
		intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
							      &power_seq);
	}
2206

2207 2208
	intel_enable_dp(encoder);

2209
	vlv_wait_port_ready(dev_priv, dport);
2210 2211
}

2212
static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2213 2214 2215 2216
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2217 2218
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
2219
	enum dpio_channel port = vlv_dport_to_channel(dport);
2220
	int pipe = intel_crtc->pipe;
2221

2222 2223
	intel_dp_prepare(encoder);

2224
	/* Program Tx lane resets to default */
2225
	mutex_lock(&dev_priv->dpio_lock);
2226
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2227 2228
			 DPIO_PCS_TX_LANE2_RESET |
			 DPIO_PCS_TX_LANE1_RESET);
2229
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2230 2231 2232 2233 2234 2235
			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
				 DPIO_PCS_CLK_SOFT_RESET);

	/* Fix up inter-pair skew failure */
2236 2237 2238
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2239
	mutex_unlock(&dev_priv->dpio_lock);
2240 2241
}

2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253
static void chv_pre_enable_dp(struct intel_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct edp_power_seq power_seq;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel ch = vlv_dport_to_channel(dport);
	int pipe = intel_crtc->pipe;
	int data, i;
2254
	u32 val;
2255 2256

	mutex_lock(&dev_priv->dpio_lock);
2257 2258

	/* Deassert soft data lane reset*/
2259
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2260
	val |= CHV_PCS_REQ_SOFTRESET_EN;
2261 2262 2263 2264 2265 2266 2267 2268 2269
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
	val |= CHV_PCS_REQ_SOFTRESET_EN;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2270

2271
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2272
	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2273
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2274 2275

	/* Program Tx lane latency optimal setting*/
2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304
	for (i = 0; i < 4; i++) {
		/* Set the latency optimal bit */
		data = (i == 1) ? 0x0 : 0x6;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
				data << DPIO_FRC_LATENCY_SHFIT);

		/* Set the upar bit */
		data = (i == 1) ? 0x0 : 0x1;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
				data << DPIO_UPAR_SHIFT);
	}

	/* Data lane stagger programming */
	/* FIXME: Fix up value only after power analysis */

	mutex_unlock(&dev_priv->dpio_lock);

	if (is_edp(intel_dp)) {
		/* init power sequencer on this pipe and port */
		intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
		intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
							      &power_seq);
	}

	intel_enable_dp(encoder);

	vlv_wait_port_ready(dev_priv, dport);
}

2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315
static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel ch = vlv_dport_to_channel(dport);
	enum pipe pipe = intel_crtc->pipe;
	u32 val;

2316 2317
	intel_dp_prepare(encoder);

2318 2319
	mutex_lock(&dev_priv->dpio_lock);

2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338
	/* program left/right clock distribution */
	if (pipe != PIPE_B) {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
		if (ch == DPIO_CH0)
			val |= CHV_BUFLEFTENA1_FORCE;
		if (ch == DPIO_CH1)
			val |= CHV_BUFRIGHTENA1_FORCE;
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
	} else {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
		if (ch == DPIO_CH0)
			val |= CHV_BUFLEFTENA2_FORCE;
		if (ch == DPIO_CH1)
			val |= CHV_BUFRIGHTENA2_FORCE;
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
	}

2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370
	/* program clock channel usage */
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
	if (pipe != PIPE_B)
		val &= ~CHV_PCS_USEDCLKCHANNEL;
	else
		val |= CHV_PCS_USEDCLKCHANNEL;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
	if (pipe != PIPE_B)
		val &= ~CHV_PCS_USEDCLKCHANNEL;
	else
		val |= CHV_PCS_USEDCLKCHANNEL;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);

	/*
	 * This a a bit weird since generally CL
	 * matches the pipe, but here we need to
	 * pick the CL based on the port.
	 */
	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
	if (pipe != PIPE_B)
		val &= ~CHV_CMN_USEDCLKCHANNEL;
	else
		val |= CHV_CMN_USEDCLKCHANNEL;
	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);

	mutex_unlock(&dev_priv->dpio_lock);
}

2371
/*
2372 2373
 * Native read with retry for link status and receiver capability reads for
 * cases where the sink may still be asleep.
2374 2375 2376
 *
 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
 * supposed to retry 3 times per the spec.
2377
 */
2378 2379 2380
static ssize_t
intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
			void *buffer, size_t size)
2381
{
2382 2383
	ssize_t ret;
	int i;
2384 2385

	for (i = 0; i < 3; i++) {
2386 2387 2388
		ret = drm_dp_dpcd_read(aux, offset, buffer, size);
		if (ret == size)
			return ret;
2389 2390
		msleep(1);
	}
2391

2392
	return ret;
2393 2394 2395 2396 2397 2398 2399
}

/*
 * Fetch AUX CH registers 0x202 - 0x207 which contain
 * link status information
 */
static bool
2400
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2401
{
2402 2403 2404 2405
	return intel_dp_dpcd_read_wake(&intel_dp->aux,
				       DP_LANE0_1_STATUS,
				       link_status,
				       DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2406 2407
}

2408
/* These are source-specific values. */
2409
static uint8_t
K
Keith Packard 已提交
2410
intel_dp_voltage_max(struct intel_dp *intel_dp)
2411
{
2412
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2413
	enum port port = dp_to_dig_port(intel_dp)->port;
K
Keith Packard 已提交
2414

2415
	if (IS_VALLEYVIEW(dev))
2416
		return DP_TRAIN_VOLTAGE_SWING_1200;
2417
	else if (IS_GEN7(dev) && port == PORT_A)
K
Keith Packard 已提交
2418
		return DP_TRAIN_VOLTAGE_SWING_800;
2419
	else if (HAS_PCH_CPT(dev) && port != PORT_A)
K
Keith Packard 已提交
2420 2421 2422 2423 2424 2425 2426 2427
		return DP_TRAIN_VOLTAGE_SWING_1200;
	else
		return DP_TRAIN_VOLTAGE_SWING_800;
}

static uint8_t
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
{
2428
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2429
	enum port port = dp_to_dig_port(intel_dp)->port;
K
Keith Packard 已提交
2430

2431
	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_9_5;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454
	} else if (IS_VALLEYVIEW(dev)) {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_9_5;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
2455
	} else if (IS_GEN7(dev) && port == PORT_A) {
K
Keith Packard 已提交
2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_600:
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
	} else {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
2477 2478 2479
	}
}

2480 2481 2482 2483 2484
static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2485 2486
	struct intel_crtc *intel_crtc =
		to_intel_crtc(dport->base.base.crtc);
2487 2488 2489
	unsigned long demph_reg_value, preemph_reg_value,
		uniqtranscale_reg_value;
	uint8_t train_set = intel_dp->train_set[0];
2490
	enum dpio_channel port = vlv_dport_to_channel(dport);
2491
	int pipe = intel_crtc->pipe;
2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565

	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
	case DP_TRAIN_PRE_EMPHASIS_0:
		preemph_reg_value = 0x0004000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x552AB83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5548B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_800:
			demph_reg_value = 0x2B245555;
			uniqtranscale_reg_value = 0x5560B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_1200:
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x5598DA3A;
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_3_5:
		preemph_reg_value = 0x0002000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5552B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			demph_reg_value = 0x2B404848;
			uniqtranscale_reg_value = 0x5580B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_800:
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_6:
		preemph_reg_value = 0x0000000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x2B305555;
			uniqtranscale_reg_value = 0x5570B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			demph_reg_value = 0x2B2B4040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_9_5:
		preemph_reg_value = 0x0006000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x1B405555;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	default:
		return 0;
	}

2566
	mutex_lock(&dev_priv->dpio_lock);
2567 2568 2569
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2570
			 uniqtranscale_reg_value);
2571 2572 2573 2574
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2575
	mutex_unlock(&dev_priv->dpio_lock);
2576 2577 2578 2579

	return 0;
}

2580 2581 2582 2583 2584 2585
static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
	struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
2586
	u32 deemph_reg_value, margin_reg_value, val;
2587 2588
	uint8_t train_set = intel_dp->train_set[0];
	enum dpio_channel ch = vlv_dport_to_channel(dport);
2589 2590
	enum pipe pipe = intel_crtc->pipe;
	int i;
2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664

	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
	case DP_TRAIN_PRE_EMPHASIS_0:
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			deemph_reg_value = 128;
			margin_reg_value = 52;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			deemph_reg_value = 128;
			margin_reg_value = 77;
			break;
		case DP_TRAIN_VOLTAGE_SWING_800:
			deemph_reg_value = 128;
			margin_reg_value = 102;
			break;
		case DP_TRAIN_VOLTAGE_SWING_1200:
			deemph_reg_value = 128;
			margin_reg_value = 154;
			/* FIXME extra to set for 1200 */
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_3_5:
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			deemph_reg_value = 85;
			margin_reg_value = 78;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			deemph_reg_value = 85;
			margin_reg_value = 116;
			break;
		case DP_TRAIN_VOLTAGE_SWING_800:
			deemph_reg_value = 85;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_6:
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			deemph_reg_value = 64;
			margin_reg_value = 104;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			deemph_reg_value = 64;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_9_5:
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			deemph_reg_value = 43;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
	default:
		return 0;
	}

	mutex_lock(&dev_priv->dpio_lock);

	/* Clear calc init */
2665 2666 2667 2668 2669 2670 2671
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2672 2673

	/* Program swing deemph */
2674 2675 2676 2677 2678 2679
	for (i = 0; i < 4; i++) {
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
		val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
	}
2680 2681

	/* Program swing margin */
2682 2683
	for (i = 0; i < 4; i++) {
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
2684 2685
		val &= ~DPIO_SWING_MARGIN000_MASK;
		val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
2686 2687
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
	}
2688 2689

	/* Disable unique transition scale */
2690 2691 2692 2693 2694
	for (i = 0; i < 4; i++) {
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
		val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
	}
2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706

	if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
			== DP_TRAIN_PRE_EMPHASIS_0) &&
		((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
			== DP_TRAIN_VOLTAGE_SWING_1200)) {

		/*
		 * The document said it needs to set bit 27 for ch0 and bit 26
		 * for ch1. Might be a typo in the doc.
		 * For now, for this unique transition scale selection, set bit
		 * 27 for ch0 and ch1.
		 */
2707 2708 2709 2710 2711
		for (i = 0; i < 4; i++) {
			val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
			val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
			vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
		}
2712

2713 2714 2715 2716 2717 2718
		for (i = 0; i < 4; i++) {
			val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
			val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
			val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
			vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
		}
2719 2720 2721
	}

	/* Start swing calculation */
2722 2723 2724 2725 2726 2727 2728
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739

	/* LRC Bypass */
	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
	val |= DPIO_LRC_BYPASS;
	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);

	mutex_unlock(&dev_priv->dpio_lock);

	return 0;
}

2740
static void
J
Jani Nikula 已提交
2741 2742
intel_get_adjust_train(struct intel_dp *intel_dp,
		       const uint8_t link_status[DP_LINK_STATUS_SIZE])
2743 2744 2745 2746
{
	uint8_t v = 0;
	uint8_t p = 0;
	int lane;
K
Keith Packard 已提交
2747 2748
	uint8_t voltage_max;
	uint8_t preemph_max;
2749

2750
	for (lane = 0; lane < intel_dp->lane_count; lane++) {
2751 2752
		uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
		uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2753 2754 2755 2756 2757 2758 2759

		if (this_v > v)
			v = this_v;
		if (this_p > p)
			p = this_p;
	}

K
Keith Packard 已提交
2760
	voltage_max = intel_dp_voltage_max(intel_dp);
2761 2762
	if (v >= voltage_max)
		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2763

K
Keith Packard 已提交
2764 2765 2766
	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
	if (p >= preemph_max)
		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2767 2768

	for (lane = 0; lane < 4; lane++)
2769
		intel_dp->train_set[lane] = v | p;
2770 2771 2772
}

static uint32_t
2773
intel_gen4_signal_levels(uint8_t train_set)
2774
{
2775
	uint32_t	signal_levels = 0;
2776

2777
	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791
	case DP_TRAIN_VOLTAGE_SWING_400:
	default:
		signal_levels |= DP_VOLTAGE_0_4;
		break;
	case DP_TRAIN_VOLTAGE_SWING_600:
		signal_levels |= DP_VOLTAGE_0_6;
		break;
	case DP_TRAIN_VOLTAGE_SWING_800:
		signal_levels |= DP_VOLTAGE_0_8;
		break;
	case DP_TRAIN_VOLTAGE_SWING_1200:
		signal_levels |= DP_VOLTAGE_1_2;
		break;
	}
2792
	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809
	case DP_TRAIN_PRE_EMPHASIS_0:
	default:
		signal_levels |= DP_PRE_EMPHASIS_0;
		break;
	case DP_TRAIN_PRE_EMPHASIS_3_5:
		signal_levels |= DP_PRE_EMPHASIS_3_5;
		break;
	case DP_TRAIN_PRE_EMPHASIS_6:
		signal_levels |= DP_PRE_EMPHASIS_6;
		break;
	case DP_TRAIN_PRE_EMPHASIS_9_5:
		signal_levels |= DP_PRE_EMPHASIS_9_5;
		break;
	}
	return signal_levels;
}

2810 2811 2812 2813
/* Gen6's DP voltage swing and pre-emphasis control */
static uint32_t
intel_gen6_edp_signal_levels(uint8_t train_set)
{
2814 2815 2816
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
2817
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2818 2819 2820 2821
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2822
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2823 2824
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
		return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2825
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2826 2827
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2828
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2829 2830
	case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2831
	default:
2832 2833 2834
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2835 2836 2837
	}
}

K
Keith Packard 已提交
2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864 2865 2866 2867 2868
/* Gen7's DP voltage swing and pre-emphasis control */
static uint32_t
intel_gen7_edp_signal_levels(uint8_t train_set)
{
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_400MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
		return EDP_LINK_TRAIN_400MV_6DB_IVB;

	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_600MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_600MV_3_5DB_IVB;

	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_800MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_800MV_3_5DB_IVB;

	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_500MV_0DB_IVB;
	}
}

2869 2870
/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
static uint32_t
2871
intel_hsw_signal_levels(uint8_t train_set)
2872
{
2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_400MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_400MV_3_5DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
		return DDI_BUF_EMP_400MV_6DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
		return DDI_BUF_EMP_400MV_9_5DB_HSW;
2884

2885 2886 2887 2888 2889 2890
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_600MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_600MV_3_5DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
		return DDI_BUF_EMP_600MV_6DB_HSW;
2891

2892 2893 2894 2895 2896 2897 2898 2899
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_800MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_800MV_3_5DB_HSW;
	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return DDI_BUF_EMP_400MV_0DB_HSW;
2900 2901 2902
	}
}

2903 2904 2905 2906 2907
/* Properly updates "DP" with the correct signal levels. */
static void
intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2908
	enum port port = intel_dig_port->port;
2909 2910 2911 2912
	struct drm_device *dev = intel_dig_port->base.base.dev;
	uint32_t signal_levels, mask;
	uint8_t train_set = intel_dp->train_set[0];

2913
	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2914 2915
		signal_levels = intel_hsw_signal_levels(train_set);
		mask = DDI_BUF_EMP_MASK;
2916 2917 2918
	} else if (IS_CHERRYVIEW(dev)) {
		signal_levels = intel_chv_signal_levels(intel_dp);
		mask = 0;
2919 2920 2921
	} else if (IS_VALLEYVIEW(dev)) {
		signal_levels = intel_vlv_signal_levels(intel_dp);
		mask = 0;
2922
	} else if (IS_GEN7(dev) && port == PORT_A) {
2923 2924
		signal_levels = intel_gen7_edp_signal_levels(train_set);
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2925
	} else if (IS_GEN6(dev) && port == PORT_A) {
2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937
		signal_levels = intel_gen6_edp_signal_levels(train_set);
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
	} else {
		signal_levels = intel_gen4_signal_levels(train_set);
		mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
	}

	DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);

	*DP = (*DP & ~mask) | signal_levels;
}

2938
static bool
C
Chris Wilson 已提交
2939
intel_dp_set_link_train(struct intel_dp *intel_dp,
2940
			uint32_t *DP,
2941
			uint8_t dp_train_pat)
2942
{
2943 2944
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
2945
	struct drm_i915_private *dev_priv = dev->dev_private;
2946
	enum port port = intel_dig_port->port;
2947 2948
	uint8_t buf[sizeof(intel_dp->train_set) + 1];
	int ret, len;
2949

2950
	if (HAS_DDI(dev)) {
2951
		uint32_t temp = I915_READ(DP_TP_CTL(port));
2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973

		if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
			temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
		else
			temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;

		temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;

			break;
		case DP_TRAINING_PATTERN_1:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
			break;
		case DP_TRAINING_PATTERN_2:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
			break;
		case DP_TRAINING_PATTERN_3:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
			break;
		}
2974
		I915_WRITE(DP_TP_CTL(port), temp);
2975

2976
	} else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2977
		*DP &= ~DP_LINK_TRAIN_MASK_CPT;
2978 2979 2980

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
2981
			*DP |= DP_LINK_TRAIN_OFF_CPT;
2982 2983
			break;
		case DP_TRAINING_PATTERN_1:
2984
			*DP |= DP_LINK_TRAIN_PAT_1_CPT;
2985 2986
			break;
		case DP_TRAINING_PATTERN_2:
2987
			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
2988 2989 2990
			break;
		case DP_TRAINING_PATTERN_3:
			DRM_ERROR("DP training pattern 3 not supported\n");
2991
			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
2992 2993 2994 2995
			break;
		}

	} else {
2996 2997 2998 2999
		if (IS_CHERRYVIEW(dev))
			*DP &= ~DP_LINK_TRAIN_MASK_CHV;
		else
			*DP &= ~DP_LINK_TRAIN_MASK;
3000 3001 3002

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
3003
			*DP |= DP_LINK_TRAIN_OFF;
3004 3005
			break;
		case DP_TRAINING_PATTERN_1:
3006
			*DP |= DP_LINK_TRAIN_PAT_1;
3007 3008
			break;
		case DP_TRAINING_PATTERN_2:
3009
			*DP |= DP_LINK_TRAIN_PAT_2;
3010 3011
			break;
		case DP_TRAINING_PATTERN_3:
3012 3013 3014 3015 3016 3017
			if (IS_CHERRYVIEW(dev)) {
				*DP |= DP_LINK_TRAIN_PAT_3_CHV;
			} else {
				DRM_ERROR("DP training pattern 3 not supported\n");
				*DP |= DP_LINK_TRAIN_PAT_2;
			}
3018 3019 3020 3021
			break;
		}
	}

3022
	I915_WRITE(intel_dp->output_reg, *DP);
C
Chris Wilson 已提交
3023
	POSTING_READ(intel_dp->output_reg);
3024

3025 3026
	buf[0] = dp_train_pat;
	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3027
	    DP_TRAINING_PATTERN_DISABLE) {
3028 3029 3030 3031 3032 3033
		/* don't write DP_TRAINING_LANEx_SET on disable */
		len = 1;
	} else {
		/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
		memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
		len = intel_dp->lane_count + 1;
3034
	}
3035

3036 3037
	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
				buf, len);
3038 3039

	return ret == len;
3040 3041
}

3042 3043 3044 3045
static bool
intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
			uint8_t dp_train_pat)
{
3046
	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3047 3048 3049 3050 3051 3052
	intel_dp_set_signal_levels(intel_dp, DP);
	return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
}

static bool
intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
J
Jani Nikula 已提交
3053
			   const uint8_t link_status[DP_LINK_STATUS_SIZE])
3054 3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	intel_get_adjust_train(intel_dp, link_status);
	intel_dp_set_signal_levels(intel_dp, DP);

	I915_WRITE(intel_dp->output_reg, *DP);
	POSTING_READ(intel_dp->output_reg);

3066 3067
	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
				intel_dp->train_set, intel_dp->lane_count);
3068 3069 3070 3071

	return ret == intel_dp->lane_count;
}

3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102
static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;
	uint32_t val;

	if (!HAS_DDI(dev))
		return;

	val = I915_READ(DP_TP_CTL(port));
	val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
	val |= DP_TP_CTL_LINK_TRAIN_IDLE;
	I915_WRITE(DP_TP_CTL(port), val);

	/*
	 * On PORT_A we can have only eDP in SST mode. There the only reason
	 * we need to set idle transmission mode is to work around a HW issue
	 * where we enable the pipe while not in idle link-training mode.
	 * In this case there is requirement to wait for a minimum number of
	 * idle patterns to be sent.
	 */
	if (port == PORT_A)
		return;

	if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
		     1))
		DRM_ERROR("Timed out waiting for DP idle patterns\n");
}

3103
/* Enable corresponding port and start training pattern 1 */
3104
void
3105
intel_dp_start_link_train(struct intel_dp *intel_dp)
3106
{
3107
	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3108
	struct drm_device *dev = encoder->dev;
3109 3110
	int i;
	uint8_t voltage;
3111
	int voltage_tries, loop_tries;
C
Chris Wilson 已提交
3112
	uint32_t DP = intel_dp->DP;
3113
	uint8_t link_config[2];
3114

P
Paulo Zanoni 已提交
3115
	if (HAS_DDI(dev))
3116 3117
		intel_ddi_prepare_link_retrain(encoder);

3118
	/* Write the link configuration data */
3119 3120 3121 3122
	link_config[0] = intel_dp->link_bw;
	link_config[1] = intel_dp->lane_count;
	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3123
	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3124 3125 3126

	link_config[0] = 0;
	link_config[1] = DP_SET_ANSI_8B10B;
3127
	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3128 3129

	DP |= DP_PORT_EN;
K
Keith Packard 已提交
3130

3131 3132 3133 3134 3135 3136 3137 3138
	/* clock recovery */
	if (!intel_dp_reset_link_train(intel_dp, &DP,
				       DP_TRAINING_PATTERN_1 |
				       DP_LINK_SCRAMBLING_DISABLE)) {
		DRM_ERROR("failed to enable link training\n");
		return;
	}

3139
	voltage = 0xff;
3140 3141
	voltage_tries = 0;
	loop_tries = 0;
3142
	for (;;) {
3143
		uint8_t link_status[DP_LINK_STATUS_SIZE];
3144

3145
		drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3146 3147
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
3148
			break;
3149
		}
3150

3151
		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3152
			DRM_DEBUG_KMS("clock recovery OK\n");
3153 3154 3155 3156 3157 3158
			break;
		}

		/* Check to see if we've tried the max voltage */
		for (i = 0; i < intel_dp->lane_count; i++)
			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3159
				break;
3160
		if (i == intel_dp->lane_count) {
3161 3162
			++loop_tries;
			if (loop_tries == 5) {
3163
				DRM_ERROR("too many full retries, give up\n");
3164 3165
				break;
			}
3166 3167 3168
			intel_dp_reset_link_train(intel_dp, &DP,
						  DP_TRAINING_PATTERN_1 |
						  DP_LINK_SCRAMBLING_DISABLE);
3169 3170 3171
			voltage_tries = 0;
			continue;
		}
3172

3173
		/* Check to see if we've tried the same voltage 5 times */
3174
		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3175
			++voltage_tries;
3176
			if (voltage_tries == 5) {
3177
				DRM_ERROR("too many voltage retries, give up\n");
3178 3179 3180 3181 3182
				break;
			}
		} else
			voltage_tries = 0;
		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3183

3184 3185 3186 3187 3188
		/* Update training set as requested by target */
		if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
			DRM_ERROR("failed to update link training\n");
			break;
		}
3189 3190
	}

3191 3192 3193
	intel_dp->DP = DP;
}

3194
void
3195 3196 3197
intel_dp_complete_link_train(struct intel_dp *intel_dp)
{
	bool channel_eq = false;
3198
	int tries, cr_tries;
3199
	uint32_t DP = intel_dp->DP;
3200 3201 3202 3203 3204
	uint32_t training_pattern = DP_TRAINING_PATTERN_2;

	/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
	if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
		training_pattern = DP_TRAINING_PATTERN_3;
3205

3206
	/* channel equalization */
3207
	if (!intel_dp_set_link_train(intel_dp, &DP,
3208
				     training_pattern |
3209 3210 3211 3212 3213
				     DP_LINK_SCRAMBLING_DISABLE)) {
		DRM_ERROR("failed to start channel equalization\n");
		return;
	}

3214
	tries = 0;
3215
	cr_tries = 0;
3216 3217
	channel_eq = false;
	for (;;) {
3218
		uint8_t link_status[DP_LINK_STATUS_SIZE];
3219

3220 3221 3222 3223 3224
		if (cr_tries > 5) {
			DRM_ERROR("failed to train DP, aborting\n");
			break;
		}

3225
		drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3226 3227
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
3228
			break;
3229
		}
3230

3231
		/* Make sure clock is still ok */
3232
		if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3233
			intel_dp_start_link_train(intel_dp);
3234
			intel_dp_set_link_train(intel_dp, &DP,
3235
						training_pattern |
3236
						DP_LINK_SCRAMBLING_DISABLE);
3237 3238 3239 3240
			cr_tries++;
			continue;
		}

3241
		if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3242 3243 3244
			channel_eq = true;
			break;
		}
3245

3246 3247 3248 3249
		/* Try 5 times, then try clock recovery if that fails */
		if (tries > 5) {
			intel_dp_link_down(intel_dp);
			intel_dp_start_link_train(intel_dp);
3250
			intel_dp_set_link_train(intel_dp, &DP,
3251
						training_pattern |
3252
						DP_LINK_SCRAMBLING_DISABLE);
3253 3254 3255 3256
			tries = 0;
			cr_tries++;
			continue;
		}
3257

3258 3259 3260 3261 3262
		/* Update training set as requested by target */
		if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
			DRM_ERROR("failed to update link training\n");
			break;
		}
3263
		++tries;
3264
	}
3265

3266 3267 3268 3269
	intel_dp_set_idle_link_train(intel_dp);

	intel_dp->DP = DP;

3270
	if (channel_eq)
M
Masanari Iida 已提交
3271
		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3272

3273 3274 3275 3276
}

void intel_dp_stop_link_train(struct intel_dp *intel_dp)
{
3277
	intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3278
				DP_TRAINING_PATTERN_DISABLE);
3279 3280 3281
}

static void
C
Chris Wilson 已提交
3282
intel_dp_link_down(struct intel_dp *intel_dp)
3283
{
3284
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3285
	enum port port = intel_dig_port->port;
3286
	struct drm_device *dev = intel_dig_port->base.base.dev;
3287
	struct drm_i915_private *dev_priv = dev->dev_private;
3288 3289
	struct intel_crtc *intel_crtc =
		to_intel_crtc(intel_dig_port->base.base.crtc);
C
Chris Wilson 已提交
3290
	uint32_t DP = intel_dp->DP;
3291

3292
	if (WARN_ON(HAS_DDI(dev)))
3293 3294
		return;

3295
	if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3296 3297
		return;

3298
	DRM_DEBUG_KMS("\n");
3299

3300
	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3301
		DP &= ~DP_LINK_TRAIN_MASK_CPT;
C
Chris Wilson 已提交
3302
		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3303
	} else {
3304 3305 3306 3307
		if (IS_CHERRYVIEW(dev))
			DP &= ~DP_LINK_TRAIN_MASK_CHV;
		else
			DP &= ~DP_LINK_TRAIN_MASK;
C
Chris Wilson 已提交
3308
		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3309
	}
3310
	POSTING_READ(intel_dp->output_reg);
3311

3312
	if (HAS_PCH_IBX(dev) &&
3313
	    I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3314
		struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
3315

3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329
		/* Hardware workaround: leaving our transcoder select
		 * set to transcoder B while it's off will prevent the
		 * corresponding HDMI output on transcoder A.
		 *
		 * Combine this with another hardware workaround:
		 * transcoder select bit can only be cleared while the
		 * port is enabled.
		 */
		DP &= ~DP_PIPEB_SELECT;
		I915_WRITE(intel_dp->output_reg, DP);

		/* Changes to enable or select take place the vblank
		 * after being written.
		 */
3330 3331 3332 3333
		if (WARN_ON(crtc == NULL)) {
			/* We should never try to disable a port without a crtc
			 * attached. For paranoia keep the code around for a
			 * bit. */
3334 3335 3336
			POSTING_READ(intel_dp->output_reg);
			msleep(50);
		} else
3337
			intel_wait_for_vblank(dev, intel_crtc->pipe);
3338 3339
	}

3340
	DP &= ~DP_AUDIO_OUTPUT_ENABLE;
C
Chris Wilson 已提交
3341 3342
	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);
3343
	msleep(intel_dp->panel_power_down_delay);
3344 3345
}

3346 3347
static bool
intel_dp_get_dpcd(struct intel_dp *intel_dp)
3348
{
R
Rodrigo Vivi 已提交
3349 3350 3351 3352
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

3353 3354
	char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];

3355 3356
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
				    sizeof(intel_dp->dpcd)) < 0)
3357
		return false; /* aux transfer failed */
3358

3359 3360 3361 3362
	hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
			   32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
	DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);

3363 3364 3365
	if (intel_dp->dpcd[DP_DPCD_REV] == 0)
		return false; /* DPCD not present */

3366 3367
	/* Check if the panel supports PSR */
	memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3368
	if (is_edp(intel_dp)) {
3369 3370 3371
		intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
					intel_dp->psr_dpcd,
					sizeof(intel_dp->psr_dpcd));
R
Rodrigo Vivi 已提交
3372 3373
		if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
			dev_priv->psr.sink_support = true;
3374
			DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
R
Rodrigo Vivi 已提交
3375
		}
3376 3377
	}

3378 3379 3380 3381 3382 3383 3384 3385
	/* Training Pattern 3 support */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
	    intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
		intel_dp->use_tps3 = true;
		DRM_DEBUG_KMS("Displayport TPS3 supported");
	} else
		intel_dp->use_tps3 = false;

3386 3387 3388 3389 3390 3391 3392
	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
	      DP_DWN_STRM_PORT_PRESENT))
		return true; /* native DP sink */

	if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
		return true; /* no per-port downstream info */

3393 3394 3395
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
				    intel_dp->downstream_ports,
				    DP_MAX_DOWNSTREAM_PORTS) < 0)
3396 3397 3398
		return false; /* downstream port status fetch failed */

	return true;
3399 3400
}

3401 3402 3403 3404 3405 3406 3407 3408
static void
intel_dp_probe_oui(struct intel_dp *intel_dp)
{
	u8 buf[3];

	if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
		return;

3409
	intel_edp_panel_vdd_on(intel_dp);
D
Daniel Vetter 已提交
3410

3411
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3412 3413 3414
		DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);

3415
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3416 3417
		DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);
D
Daniel Vetter 已提交
3418

3419
	edp_panel_vdd_off(intel_dp, false);
3420 3421
}

3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446 3447 3448
static bool
intel_dp_probe_mst(struct intel_dp *intel_dp)
{
	u8 buf[1];

	if (!intel_dp->can_mst)
		return false;

	if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
		return false;

	_edp_panel_vdd_on(intel_dp);
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
		if (buf[0] & DP_MST_CAP) {
			DRM_DEBUG_KMS("Sink is MST capable\n");
			intel_dp->is_mst = true;
		} else {
			DRM_DEBUG_KMS("Sink is not MST capable\n");
			intel_dp->is_mst = false;
		}
	}
	edp_panel_vdd_off(intel_dp, false);

	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
	return intel_dp->is_mst;
}

3449 3450 3451 3452 3453 3454 3455 3456
int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(intel_dig_port->base.base.crtc);
	u8 buf[1];

3457
	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
3458 3459 3460 3461 3462
		return -EAGAIN;

	if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
		return -ENOTTY;

3463 3464
	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
			       DP_TEST_SINK_START) < 0)
3465 3466 3467 3468 3469 3470
		return -EAGAIN;

	/* Wait 2 vblanks to be sure we will have the correct CRC value */
	intel_wait_for_vblank(dev, intel_crtc->pipe);
	intel_wait_for_vblank(dev, intel_crtc->pipe);

3471
	if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
3472 3473
		return -EAGAIN;

3474
	drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
3475 3476 3477
	return 0;
}

3478 3479 3480
static bool
intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
3481 3482 3483
	return intel_dp_dpcd_read_wake(&intel_dp->aux,
				       DP_DEVICE_SERVICE_IRQ_VECTOR,
				       sink_irq_vector, 1) == 1;
3484 3485
}

3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499
static bool
intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
	int ret;

	ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
					     DP_SINK_COUNT_ESI,
					     sink_irq_vector, 14);
	if (ret != 14)
		return false;

	return true;
}

3500 3501 3502 3503
static void
intel_dp_handle_test_request(struct intel_dp *intel_dp)
{
	/* NAK by default */
3504
	drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
3505 3506
}

3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563
static int
intel_dp_check_mst_status(struct intel_dp *intel_dp)
{
	bool bret;

	if (intel_dp->is_mst) {
		u8 esi[16] = { 0 };
		int ret = 0;
		int retry;
		bool handled;
		bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
go_again:
		if (bret == true) {

			/* check link status - esi[10] = 0x200c */
			if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
				DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
				intel_dp_start_link_train(intel_dp);
				intel_dp_complete_link_train(intel_dp);
				intel_dp_stop_link_train(intel_dp);
			}

			DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
			ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);

			if (handled) {
				for (retry = 0; retry < 3; retry++) {
					int wret;
					wret = drm_dp_dpcd_write(&intel_dp->aux,
								 DP_SINK_COUNT_ESI+1,
								 &esi[1], 3);
					if (wret == 3) {
						break;
					}
				}

				bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
				if (bret == true) {
					DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
					goto go_again;
				}
			} else
				ret = 0;

			return ret;
		} else {
			struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
			DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
			intel_dp->is_mst = false;
			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
			/* send a hotplug event */
			drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
		}
	}
	return -EINVAL;
}

3564 3565 3566 3567 3568 3569 3570 3571
/*
 * According to DP spec
 * 5.1.2:
 *  1. Read DPCD
 *  2. Configure link according to Receiver Capabilities
 *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
 *  4. Check link status on receipt of hot-plug interrupt
 */
P
Paulo Zanoni 已提交
3572
void
C
Chris Wilson 已提交
3573
intel_dp_check_link_status(struct intel_dp *intel_dp)
3574
{
3575
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3576
	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3577
	u8 sink_irq_vector;
3578
	u8 link_status[DP_LINK_STATUS_SIZE];
3579

3580 3581
	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));

3582
	if (!intel_encoder->connectors_active)
3583
		return;
3584

3585
	if (WARN_ON(!intel_encoder->base.crtc))
3586 3587
		return;

3588 3589 3590
	if (!to_intel_crtc(intel_encoder->base.crtc)->active)
		return;

3591
	/* Try to read receiver status if the link appears to be up */
3592
	if (!intel_dp_get_link_status(intel_dp, link_status)) {
3593 3594 3595
		return;
	}

3596
	/* Now read the DPCD to see if it's actually running */
3597
	if (!intel_dp_get_dpcd(intel_dp)) {
3598 3599 3600
		return;
	}

3601 3602 3603 3604
	/* Try to read the source of the interrupt */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
		/* Clear interrupt source */
3605 3606 3607
		drm_dp_dpcd_writeb(&intel_dp->aux,
				   DP_DEVICE_SERVICE_IRQ_VECTOR,
				   sink_irq_vector);
3608 3609 3610 3611 3612 3613 3614

		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
			intel_dp_handle_test_request(intel_dp);
		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
	}

3615
	if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3616
		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3617
			      intel_encoder->base.name);
3618 3619
		intel_dp_start_link_train(intel_dp);
		intel_dp_complete_link_train(intel_dp);
3620
		intel_dp_stop_link_train(intel_dp);
3621
	}
3622 3623
}

3624
/* XXX this is probably wrong for multiple downstream ports */
3625
static enum drm_connector_status
3626
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3627
{
3628 3629 3630 3631 3632 3633 3634 3635
	uint8_t *dpcd = intel_dp->dpcd;
	uint8_t type;

	if (!intel_dp_get_dpcd(intel_dp))
		return connector_status_disconnected;

	/* if there's no downstream port, we're done */
	if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3636
		return connector_status_connected;
3637 3638

	/* If we're HPD-aware, SINK_COUNT changes dynamically */
3639 3640
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3641
		uint8_t reg;
3642 3643 3644

		if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
					    &reg, 1) < 0)
3645
			return connector_status_unknown;
3646

3647 3648
		return DP_GET_SINK_COUNT(reg) ? connector_status_connected
					      : connector_status_disconnected;
3649 3650 3651
	}

	/* If no HPD, poke DDC gently */
3652
	if (drm_probe_ddc(&intel_dp->aux.ddc))
3653
		return connector_status_connected;
3654 3655

	/* Well we tried, say unknown for unreliable port types */
3656 3657 3658 3659 3660 3661 3662 3663 3664 3665 3666 3667
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
		type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
		if (type == DP_DS_PORT_TYPE_VGA ||
		    type == DP_DS_PORT_TYPE_NON_EDID)
			return connector_status_unknown;
	} else {
		type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
			DP_DWN_STRM_PORT_TYPE_MASK;
		if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
		    type == DP_DWN_STRM_PORT_TYPE_OTHER)
			return connector_status_unknown;
	}
3668 3669 3670

	/* Anything else is out of spec, warn and ignore */
	DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3671
	return connector_status_disconnected;
3672 3673
}

3674
static enum drm_connector_status
Z
Zhenyu Wang 已提交
3675
ironlake_dp_detect(struct intel_dp *intel_dp)
3676
{
3677
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3678 3679
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3680 3681
	enum drm_connector_status status;

3682 3683
	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp)) {
3684
		status = intel_panel_detect(dev);
3685 3686 3687 3688
		if (status == connector_status_unknown)
			status = connector_status_connected;
		return status;
	}
3689

3690 3691 3692
	if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
		return connector_status_disconnected;

3693
	return intel_dp_detect_dpcd(intel_dp);
3694 3695
}

3696
static enum drm_connector_status
Z
Zhenyu Wang 已提交
3697
g4x_dp_detect(struct intel_dp *intel_dp)
3698
{
3699
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3700
	struct drm_i915_private *dev_priv = dev->dev_private;
3701
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3702
	uint32_t bit;
3703

3704 3705 3706 3707 3708 3709 3710 3711 3712 3713
	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp)) {
		enum drm_connector_status status;

		status = intel_panel_detect(dev);
		if (status == connector_status_unknown)
			status = connector_status_connected;
		return status;
	}

3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741
	if (IS_VALLEYVIEW(dev)) {
		switch (intel_dig_port->port) {
		case PORT_B:
			bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
			break;
		case PORT_C:
			bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
			break;
		case PORT_D:
			bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
			break;
		default:
			return connector_status_unknown;
		}
	} else {
		switch (intel_dig_port->port) {
		case PORT_B:
			bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
			break;
		case PORT_C:
			bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
			break;
		case PORT_D:
			bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
			break;
		default:
			return connector_status_unknown;
		}
3742 3743
	}

3744
	if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3745 3746
		return connector_status_disconnected;

3747
	return intel_dp_detect_dpcd(intel_dp);
Z
Zhenyu Wang 已提交
3748 3749
}

3750 3751 3752
static struct edid *
intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
{
3753
	struct intel_connector *intel_connector = to_intel_connector(connector);
3754

3755 3756 3757 3758
	/* use cached edid if we have one */
	if (intel_connector->edid) {
		/* invalid edid */
		if (IS_ERR(intel_connector->edid))
3759 3760
			return NULL;

J
Jani Nikula 已提交
3761
		return drm_edid_duplicate(intel_connector->edid);
3762
	}
3763

3764
	return drm_get_edid(connector, adapter);
3765 3766 3767 3768 3769
}

static int
intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
{
3770
	struct intel_connector *intel_connector = to_intel_connector(connector);
3771

3772 3773 3774 3775 3776 3777 3778 3779
	/* use cached edid if we have one */
	if (intel_connector->edid) {
		/* invalid edid */
		if (IS_ERR(intel_connector->edid))
			return 0;

		return intel_connector_update_modes(connector,
						    intel_connector->edid);
3780 3781
	}

3782
	return intel_ddc_get_modes(connector, adapter);
3783 3784
}

Z
Zhenyu Wang 已提交
3785 3786 3787 3788
static enum drm_connector_status
intel_dp_detect(struct drm_connector *connector, bool force)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
3789 3790
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
3791
	struct drm_device *dev = connector->dev;
3792
	struct drm_i915_private *dev_priv = dev->dev_private;
Z
Zhenyu Wang 已提交
3793
	enum drm_connector_status status;
3794
	enum intel_display_power_domain power_domain;
Z
Zhenyu Wang 已提交
3795
	struct edid *edid = NULL;
3796
	bool ret;
Z
Zhenyu Wang 已提交
3797

3798 3799 3800
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);

3801
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3802
		      connector->base.id, connector->name);
3803

3804 3805 3806 3807 3808 3809 3810 3811
	if (intel_dp->is_mst) {
		/* MST devices are disconnected from a monitor POV */
		if (intel_encoder->type != INTEL_OUTPUT_EDP)
			intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
		status = connector_status_disconnected;
		goto out;
	}

Z
Zhenyu Wang 已提交
3812 3813 3814 3815 3816 3817
	intel_dp->has_audio = false;

	if (HAS_PCH_SPLIT(dev))
		status = ironlake_dp_detect(intel_dp);
	else
		status = g4x_dp_detect(intel_dp);
3818

Z
Zhenyu Wang 已提交
3819
	if (status != connector_status_connected)
3820
		goto out;
Z
Zhenyu Wang 已提交
3821

3822 3823
	intel_dp_probe_oui(intel_dp);

3824 3825 3826 3827 3828 3829 3830 3831 3832 3833
	ret = intel_dp_probe_mst(intel_dp);
	if (ret) {
		/* if we are in MST mode then this connector
		   won't appear connected or have anything with EDID on it */
		if (intel_encoder->type != INTEL_OUTPUT_EDP)
			intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
		status = connector_status_disconnected;
		goto out;
	}

3834 3835
	if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
		intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3836
	} else {
3837
		edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3838 3839 3840 3841
		if (edid) {
			intel_dp->has_audio = drm_detect_monitor_audio(edid);
			kfree(edid);
		}
Z
Zhenyu Wang 已提交
3842 3843
	}

3844 3845
	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3846 3847 3848
	status = connector_status_connected;

out:
3849
	intel_display_power_put(dev_priv, power_domain);
3850
	return status;
3851 3852 3853 3854
}

static int intel_dp_get_modes(struct drm_connector *connector)
{
3855
	struct intel_dp *intel_dp = intel_attached_dp(connector);
3856 3857
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
3858
	struct intel_connector *intel_connector = to_intel_connector(connector);
3859
	struct drm_device *dev = connector->dev;
3860 3861
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum intel_display_power_domain power_domain;
3862
	int ret;
3863 3864 3865 3866

	/* We should parse the EDID data and find out if it has an audio sink
	 */

3867 3868 3869
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);

3870
	ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
3871
	intel_display_power_put(dev_priv, power_domain);
3872
	if (ret)
3873 3874
		return ret;

3875
	/* if eDP has no EDID, fall back to fixed mode */
3876
	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3877
		struct drm_display_mode *mode;
3878 3879
		mode = drm_mode_duplicate(dev,
					  intel_connector->panel.fixed_mode);
3880
		if (mode) {
3881 3882 3883 3884 3885
			drm_mode_probed_add(connector, mode);
			return 1;
		}
	}
	return 0;
3886 3887
}

3888 3889 3890 3891
static bool
intel_dp_detect_audio(struct drm_connector *connector)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
3892 3893 3894 3895 3896
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = connector->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum intel_display_power_domain power_domain;
3897 3898 3899
	struct edid *edid;
	bool has_audio = false;

3900 3901 3902
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);

3903
	edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3904 3905 3906 3907 3908
	if (edid) {
		has_audio = drm_detect_monitor_audio(edid);
		kfree(edid);
	}

3909 3910
	intel_display_power_put(dev_priv, power_domain);

3911 3912 3913
	return has_audio;
}

3914 3915 3916 3917 3918
static int
intel_dp_set_property(struct drm_connector *connector,
		      struct drm_property *property,
		      uint64_t val)
{
3919
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
3920
	struct intel_connector *intel_connector = to_intel_connector(connector);
3921 3922
	struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3923 3924
	int ret;

3925
	ret = drm_object_property_set_value(&connector->base, property, val);
3926 3927 3928
	if (ret)
		return ret;

3929
	if (property == dev_priv->force_audio_property) {
3930 3931 3932 3933
		int i = val;
		bool has_audio;

		if (i == intel_dp->force_audio)
3934 3935
			return 0;

3936
		intel_dp->force_audio = i;
3937

3938
		if (i == HDMI_AUDIO_AUTO)
3939 3940
			has_audio = intel_dp_detect_audio(connector);
		else
3941
			has_audio = (i == HDMI_AUDIO_ON);
3942 3943

		if (has_audio == intel_dp->has_audio)
3944 3945
			return 0;

3946
		intel_dp->has_audio = has_audio;
3947 3948 3949
		goto done;
	}

3950
	if (property == dev_priv->broadcast_rgb_property) {
3951 3952 3953
		bool old_auto = intel_dp->color_range_auto;
		uint32_t old_range = intel_dp->color_range;

3954 3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968
		switch (val) {
		case INTEL_BROADCAST_RGB_AUTO:
			intel_dp->color_range_auto = true;
			break;
		case INTEL_BROADCAST_RGB_FULL:
			intel_dp->color_range_auto = false;
			intel_dp->color_range = 0;
			break;
		case INTEL_BROADCAST_RGB_LIMITED:
			intel_dp->color_range_auto = false;
			intel_dp->color_range = DP_COLOR_RANGE_16_235;
			break;
		default:
			return -EINVAL;
		}
3969 3970 3971 3972 3973

		if (old_auto == intel_dp->color_range_auto &&
		    old_range == intel_dp->color_range)
			return 0;

3974 3975 3976
		goto done;
	}

3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992
	if (is_edp(intel_dp) &&
	    property == connector->dev->mode_config.scaling_mode_property) {
		if (val == DRM_MODE_SCALE_NONE) {
			DRM_DEBUG_KMS("no scaling not supported\n");
			return -EINVAL;
		}

		if (intel_connector->panel.fitting_mode == val) {
			/* the eDP scaling property is not changed */
			return 0;
		}
		intel_connector->panel.fitting_mode = val;

		goto done;
	}

3993 3994 3995
	return -EINVAL;

done:
3996 3997
	if (intel_encoder->base.crtc)
		intel_crtc_restore_mode(intel_encoder->base.crtc);
3998 3999 4000 4001

	return 0;
}

4002
static void
4003
intel_dp_connector_destroy(struct drm_connector *connector)
4004
{
4005
	struct intel_connector *intel_connector = to_intel_connector(connector);
4006

4007 4008 4009
	if (!IS_ERR_OR_NULL(intel_connector->edid))
		kfree(intel_connector->edid);

4010 4011 4012
	/* Can't call is_edp() since the encoder may have been destroyed
	 * already. */
	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4013
		intel_panel_fini(&intel_connector->panel);
4014

4015
	drm_connector_cleanup(connector);
4016
	kfree(connector);
4017 4018
}

P
Paulo Zanoni 已提交
4019
void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4020
{
4021 4022
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_dp *intel_dp = &intel_dig_port->dp;
4023
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
4024

4025
	drm_dp_aux_unregister(&intel_dp->aux);
4026
	intel_dp_mst_encoder_cleanup(intel_dig_port);
4027
	drm_encoder_cleanup(encoder);
4028 4029
	if (is_edp(intel_dp)) {
		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4030
		drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4031
		edp_panel_vdd_off_sync(intel_dp);
4032
		drm_modeset_unlock(&dev->mode_config.connection_mutex);
4033 4034 4035 4036
		if (intel_dp->edp_notifier.notifier_call) {
			unregister_reboot_notifier(&intel_dp->edp_notifier);
			intel_dp->edp_notifier.notifier_call = NULL;
		}
4037
	}
4038
	kfree(intel_dig_port);
4039 4040
}

4041 4042 4043 4044 4045 4046 4047 4048 4049 4050
static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);

	if (!is_edp(intel_dp))
		return;

	edp_panel_vdd_off_sync(intel_dp);
}

4051 4052 4053 4054 4055
static void intel_dp_encoder_reset(struct drm_encoder *encoder)
{
	intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
}

4056
static const struct drm_connector_funcs intel_dp_connector_funcs = {
4057
	.dpms = intel_connector_dpms,
4058 4059
	.detect = intel_dp_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
4060
	.set_property = intel_dp_set_property,
4061
	.destroy = intel_dp_connector_destroy,
4062 4063 4064 4065 4066
};

static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
	.get_modes = intel_dp_get_modes,
	.mode_valid = intel_dp_mode_valid,
4067
	.best_encoder = intel_best_encoder,
4068 4069 4070
};

static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4071
	.reset = intel_dp_encoder_reset,
4072
	.destroy = intel_dp_encoder_destroy,
4073 4074
};

4075
void
4076
intel_dp_hot_plug(struct intel_encoder *intel_encoder)
4077
{
4078
	return;
4079
}
4080

4081 4082 4083 4084
bool
intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
{
	struct intel_dp *intel_dp = &intel_dig_port->dp;
4085
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
4086 4087
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
4088 4089 4090
	enum intel_display_power_domain power_domain;
	bool ret = true;

4091 4092
	if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
		intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4093

4094 4095
	DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
		      port_name(intel_dig_port->port),
4096
		      long_hpd ? "long" : "short");
4097

4098 4099 4100
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);

4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114 4115
	if (long_hpd) {
		if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
			goto mst_fail;

		if (!intel_dp_get_dpcd(intel_dp)) {
			goto mst_fail;
		}

		intel_dp_probe_oui(intel_dp);

		if (!intel_dp_probe_mst(intel_dp))
			goto mst_fail;

	} else {
		if (intel_dp->is_mst) {
4116
			if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
4117 4118 4119 4120 4121 4122 4123 4124
				goto mst_fail;
		}

		if (!intel_dp->is_mst) {
			/*
			 * we'll check the link status via the normal hot plug path later -
			 * but for short hpds we should check it now
			 */
4125
			drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4126
			intel_dp_check_link_status(intel_dp);
4127
			drm_modeset_unlock(&dev->mode_config.connection_mutex);
4128 4129
		}
	}
4130 4131
	ret = false;
	goto put_power;
4132 4133 4134 4135 4136 4137 4138
mst_fail:
	/* if we were in MST mode, and device is not there get out of MST mode */
	if (intel_dp->is_mst) {
		DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
		intel_dp->is_mst = false;
		drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
	}
4139 4140 4141 4142
put_power:
	intel_display_power_put(dev_priv, power_domain);

	return ret;
4143 4144
}

4145 4146
/* Return which DP Port should be selected for Transcoder DP control */
int
4147
intel_trans_dp_port_sel(struct drm_crtc *crtc)
4148 4149
{
	struct drm_device *dev = crtc->dev;
4150 4151
	struct intel_encoder *intel_encoder;
	struct intel_dp *intel_dp;
4152

4153 4154
	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		intel_dp = enc_to_intel_dp(&intel_encoder->base);
4155

4156 4157
		if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
		    intel_encoder->type == INTEL_OUTPUT_EDP)
C
Chris Wilson 已提交
4158
			return intel_dp->output_reg;
4159
	}
C
Chris Wilson 已提交
4160

4161 4162 4163
	return -1;
}

4164
/* check the VBT to see whether the eDP is on DP-D port */
4165
bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4166 4167
{
	struct drm_i915_private *dev_priv = dev->dev_private;
4168
	union child_device_config *p_child;
4169
	int i;
4170 4171 4172 4173 4174
	static const short port_mapping[] = {
		[PORT_B] = PORT_IDPB,
		[PORT_C] = PORT_IDPC,
		[PORT_D] = PORT_IDPD,
	};
4175

4176 4177 4178
	if (port == PORT_A)
		return true;

4179
	if (!dev_priv->vbt.child_dev_num)
4180 4181
		return false;

4182 4183
	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
		p_child = dev_priv->vbt.child_dev + i;
4184

4185
		if (p_child->common.dvo_port == port_mapping[port] &&
4186 4187
		    (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
		    (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
4188 4189 4190 4191 4192
			return true;
	}
	return false;
}

4193
void
4194 4195
intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
{
4196 4197
	struct intel_connector *intel_connector = to_intel_connector(connector);

4198
	intel_attach_force_audio_property(connector);
4199
	intel_attach_broadcast_rgb_property(connector);
4200
	intel_dp->color_range_auto = true;
4201 4202 4203

	if (is_edp(intel_dp)) {
		drm_mode_create_scaling_mode_property(connector->dev);
4204 4205
		drm_object_attach_property(
			&connector->base,
4206
			connector->dev->mode_config.scaling_mode_property,
4207 4208
			DRM_MODE_SCALE_ASPECT);
		intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4209
	}
4210 4211
}

4212 4213 4214 4215 4216 4217 4218
static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
{
	intel_dp->last_power_cycle = jiffies;
	intel_dp->last_power_on = jiffies;
	intel_dp->last_backlight_off = jiffies;
}

4219 4220
static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4221 4222
				    struct intel_dp *intel_dp,
				    struct edp_power_seq *out)
4223 4224 4225 4226
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct edp_power_seq cur, vbt, spec, final;
	u32 pp_on, pp_off, pp_div, pp;
4227
	int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
4228 4229

	if (HAS_PCH_SPLIT(dev)) {
4230
		pp_ctrl_reg = PCH_PP_CONTROL;
4231 4232 4233 4234
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
4235 4236 4237 4238 4239 4240
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4241
	}
4242 4243 4244

	/* Workaround: Need to write PP_CONTROL with the unlock key as
	 * the very first thing. */
4245
	pp = ironlake_get_pp_control(intel_dp);
4246
	I915_WRITE(pp_ctrl_reg, pp);
4247

4248 4249 4250
	pp_on = I915_READ(pp_on_reg);
	pp_off = I915_READ(pp_off_reg);
	pp_div = I915_READ(pp_div_reg);
4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264 4265 4266 4267 4268 4269 4270

	/* Pull timing values out of registers */
	cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
		PANEL_POWER_UP_DELAY_SHIFT;

	cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
		PANEL_LIGHT_ON_DELAY_SHIFT;

	cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
		PANEL_LIGHT_OFF_DELAY_SHIFT;

	cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
		PANEL_POWER_DOWN_DELAY_SHIFT;

	cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
		       PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;

	DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);

4271
	vbt = dev_priv->vbt.edp_pps;
4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295 4296 4297 4298 4299 4300 4301 4302 4303 4304 4305 4306 4307

	/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
	 * our hw here, which are all in 100usec. */
	spec.t1_t3 = 210 * 10;
	spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
	spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
	spec.t10 = 500 * 10;
	/* This one is special and actually in units of 100ms, but zero
	 * based in the hw (so we need to add 100 ms). But the sw vbt
	 * table multiplies it with 1000 to make it in units of 100usec,
	 * too. */
	spec.t11_t12 = (510 + 100) * 10;

	DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);

	/* Use the max of the register settings and vbt. If both are
	 * unset, fall back to the spec limits. */
#define assign_final(field)	final.field = (max(cur.field, vbt.field) == 0 ? \
				       spec.field : \
				       max(cur.field, vbt.field))
	assign_final(t1_t3);
	assign_final(t8);
	assign_final(t9);
	assign_final(t10);
	assign_final(t11_t12);
#undef assign_final

#define get_delay(field)	(DIV_ROUND_UP(final.field, 10))
	intel_dp->panel_power_up_delay = get_delay(t1_t3);
	intel_dp->backlight_on_delay = get_delay(t8);
	intel_dp->backlight_off_delay = get_delay(t9);
	intel_dp->panel_power_down_delay = get_delay(t10);
	intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
#undef get_delay

4308 4309 4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324
	DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
		      intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
		      intel_dp->panel_power_cycle_delay);

	DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
		      intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);

	if (out)
		*out = final;
}

static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
					      struct intel_dp *intel_dp,
					      struct edp_power_seq *seq)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
4325 4326 4327
	u32 pp_on, pp_off, pp_div, port_sel = 0;
	int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
	int pp_on_reg, pp_off_reg, pp_div_reg;
4328
	enum port port = dp_to_dig_port(intel_dp)->port;
4329 4330 4331 4332 4333 4334

	if (HAS_PCH_SPLIT(dev)) {
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
4335 4336 4337 4338 4339
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4340 4341
	}

4342 4343 4344 4345 4346 4347 4348 4349
	/*
	 * And finally store the new values in the power sequencer. The
	 * backlight delays are set to 1 because we do manual waits on them. For
	 * T8, even BSpec recommends doing it. For T9, if we don't do this,
	 * we'll end up waiting for the backlight off delay twice: once when we
	 * do the manual sleep, and once when we disable the panel and wait for
	 * the PP_STATUS bit to become zero.
	 */
4350
	pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4351 4352
		(1 << PANEL_LIGHT_ON_DELAY_SHIFT);
	pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4353
		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4354 4355
	/* Compute the divisor for the pp clock, simply match the Bspec
	 * formula. */
4356
	pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4357
	pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4358 4359 4360 4361
			<< PANEL_POWER_CYCLE_DELAY_SHIFT);

	/* Haswell doesn't have any port selection bits for the panel
	 * power sequencer any more. */
4362
	if (IS_VALLEYVIEW(dev)) {
4363
		port_sel = PANEL_PORT_SELECT_VLV(port);
4364
	} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4365
		if (port == PORT_A)
4366
			port_sel = PANEL_PORT_SELECT_DPA;
4367
		else
4368
			port_sel = PANEL_PORT_SELECT_DPD;
4369 4370
	}

4371 4372 4373 4374 4375
	pp_on |= port_sel;

	I915_WRITE(pp_on_reg, pp_on);
	I915_WRITE(pp_off_reg, pp_off);
	I915_WRITE(pp_div_reg, pp_div);
4376 4377

	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4378 4379 4380
		      I915_READ(pp_on_reg),
		      I915_READ(pp_off_reg),
		      I915_READ(pp_div_reg));
4381 4382
}

4383 4384 4385 4386 4387 4388 4389 4390 4391 4392 4393 4394 4395 4396 4397 4398 4399 4400 4401 4402 4403
void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *encoder;
	struct intel_dp *intel_dp = NULL;
	struct intel_crtc_config *config = NULL;
	struct intel_crtc *intel_crtc = NULL;
	struct intel_connector *intel_connector = dev_priv->drrs.connector;
	u32 reg, val;
	enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;

	if (refresh_rate <= 0) {
		DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
		return;
	}

	if (intel_connector == NULL) {
		DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
		return;
	}

4404 4405 4406 4407 4408
	/*
	 * FIXME: This needs proper synchronization with psr state. But really
	 * hard to tell without seeing the user of this function of this code.
	 * Check locking and ordering once that lands.
	 */
4409 4410 4411 4412 4413 4414 4415 4416 4417 4418 4419 4420 4421 4422 4423 4424 4425 4426 4427 4428 4429 4430 4431 4432 4433 4434 4435 4436 4437 4438 4439 4440 4441 4442 4443 4444 4445 4446 4447 4448
	if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
		DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
		return;
	}

	encoder = intel_attached_encoder(&intel_connector->base);
	intel_dp = enc_to_intel_dp(&encoder->base);
	intel_crtc = encoder->new_crtc;

	if (!intel_crtc) {
		DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
		return;
	}

	config = &intel_crtc->config;

	if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
		DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
		return;
	}

	if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
		index = DRRS_LOW_RR;

	if (index == intel_dp->drrs_state.refresh_rate_type) {
		DRM_DEBUG_KMS(
			"DRRS requested for previously set RR...ignoring\n");
		return;
	}

	if (!intel_crtc->active) {
		DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
		return;
	}

	if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
		reg = PIPECONF(intel_crtc->config.cpu_transcoder);
		val = I915_READ(reg);
		if (index > DRRS_HIGH_RR) {
			val |= PIPECONF_EDP_RR_MODE_SWITCH;
4449
			intel_dp_set_m_n(intel_crtc);
4450 4451 4452 4453 4454 4455 4456 4457 4458 4459 4460 4461 4462 4463 4464 4465 4466 4467 4468 4469 4470 4471
		} else {
			val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
		}
		I915_WRITE(reg, val);
	}

	/*
	 * mutex taken to ensure that there is no race between differnt
	 * drrs calls trying to update refresh rate. This scenario may occur
	 * in future when idleness detection based DRRS in kernel and
	 * possible calls from user space to set differnt RR are made.
	 */

	mutex_lock(&intel_dp->drrs_state.mutex);

	intel_dp->drrs_state.refresh_rate_type = index;

	mutex_unlock(&intel_dp->drrs_state.mutex);

	DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
}

4472 4473 4474 4475 4476 4477 4478 4479 4480 4481 4482 4483 4484 4485 4486 4487 4488
static struct drm_display_mode *
intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
			struct intel_connector *intel_connector,
			struct drm_display_mode *fixed_mode)
{
	struct drm_connector *connector = &intel_connector->base;
	struct intel_dp *intel_dp = &intel_dig_port->dp;
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_display_mode *downclock_mode = NULL;

	if (INTEL_INFO(dev)->gen <= 6) {
		DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
		return NULL;
	}

	if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
4489
		DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
4490 4491 4492 4493 4494 4495 4496
		return NULL;
	}

	downclock_mode = intel_find_panel_downclock
					(dev, fixed_mode, connector);

	if (!downclock_mode) {
4497
		DRM_DEBUG_KMS("DRRS not supported\n");
4498 4499 4500
		return NULL;
	}

4501 4502 4503 4504
	dev_priv->drrs.connector = intel_connector;

	mutex_init(&intel_dp->drrs_state.mutex);

4505 4506 4507
	intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;

	intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
4508
	DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
4509 4510 4511
	return downclock_mode;
}

4512 4513 4514 4515 4516 4517 4518 4519 4520 4521 4522 4523 4524 4525 4526 4527 4528 4529 4530 4531 4532 4533 4534 4535 4536 4537
void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
{
	struct drm_device *dev = intel_encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_dp *intel_dp;
	enum intel_display_power_domain power_domain;

	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		return;

	intel_dp = enc_to_intel_dp(&intel_encoder->base);
	if (!edp_have_panel_vdd(intel_dp))
		return;
	/*
	 * The VDD bit needs a power domain reference, so if the bit is
	 * already enabled when we boot or resume, grab this reference and
	 * schedule a vdd off, so we don't hold on to the reference
	 * indefinitely.
	 */
	DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);

	edp_panel_vdd_schedule_off(intel_dp);
}

4538
static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4539 4540
				     struct intel_connector *intel_connector,
				     struct edp_power_seq *power_seq)
4541 4542 4543
{
	struct drm_connector *connector = &intel_connector->base;
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4544 4545
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
4546 4547
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_display_mode *fixed_mode = NULL;
4548
	struct drm_display_mode *downclock_mode = NULL;
4549 4550 4551 4552
	bool has_dpcd;
	struct drm_display_mode *scan;
	struct edid *edid;

4553 4554
	intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;

4555 4556 4557
	if (!is_edp(intel_dp))
		return true;

4558
	intel_edp_panel_vdd_sanitize(intel_encoder);
4559

4560
	/* Cache DPCD and EDID for edp. */
4561
	intel_edp_panel_vdd_on(intel_dp);
4562
	has_dpcd = intel_dp_get_dpcd(intel_dp);
4563
	edp_panel_vdd_off(intel_dp, false);
4564 4565 4566 4567 4568 4569 4570 4571 4572 4573 4574 4575 4576

	if (has_dpcd) {
		if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
			dev_priv->no_aux_handshake =
				intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
				DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
	} else {
		/* if this fails, presume the device is a ghost */
		DRM_INFO("failed to retrieve link info, disabling eDP\n");
		return false;
	}

	/* We now know it's not a ghost, init power sequence regs. */
4577
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
4578

4579
	mutex_lock(&dev->mode_config.mutex);
4580
	edid = drm_get_edid(connector, &intel_dp->aux.ddc);
4581 4582 4583 4584 4585 4586 4587 4588 4589 4590 4591 4592 4593 4594 4595 4596 4597 4598
	if (edid) {
		if (drm_add_edid_modes(connector, edid)) {
			drm_mode_connector_update_edid_property(connector,
								edid);
			drm_edid_to_eld(connector, edid);
		} else {
			kfree(edid);
			edid = ERR_PTR(-EINVAL);
		}
	} else {
		edid = ERR_PTR(-ENOENT);
	}
	intel_connector->edid = edid;

	/* prefer fixed mode from EDID if available */
	list_for_each_entry(scan, &connector->probed_modes, head) {
		if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
			fixed_mode = drm_mode_duplicate(dev, scan);
4599 4600 4601
			downclock_mode = intel_dp_drrs_init(
						intel_dig_port,
						intel_connector, fixed_mode);
4602 4603 4604 4605 4606 4607 4608 4609 4610 4611 4612
			break;
		}
	}

	/* fallback to VBT if available for eDP */
	if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
		fixed_mode = drm_mode_duplicate(dev,
					dev_priv->vbt.lfp_lvds_vbt_mode);
		if (fixed_mode)
			fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
	}
4613
	mutex_unlock(&dev->mode_config.mutex);
4614

4615 4616 4617 4618 4619
	if (IS_VALLEYVIEW(dev)) {
		intel_dp->edp_notifier.notifier_call = edp_notify_handler;
		register_reboot_notifier(&intel_dp->edp_notifier);
	}

4620
	intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
4621
	intel_connector->panel.backlight_power = intel_edp_backlight_power;
4622 4623 4624 4625 4626
	intel_panel_setup_backlight(connector);

	return true;
}

4627
bool
4628 4629
intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
			struct intel_connector *intel_connector)
4630
{
4631 4632 4633 4634
	struct drm_connector *connector = &intel_connector->base;
	struct intel_dp *intel_dp = &intel_dig_port->dp;
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
4635
	struct drm_i915_private *dev_priv = dev->dev_private;
4636
	enum port port = intel_dig_port->port;
4637
	struct edp_power_seq power_seq = { 0 };
4638
	int type;
4639

4640 4641 4642 4643 4644 4645 4646 4647 4648 4649
	/* intel_dp vfuncs */
	if (IS_VALLEYVIEW(dev))
		intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
		intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
	else if (HAS_PCH_SPLIT(dev))
		intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
	else
		intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;

4650 4651
	intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;

4652 4653
	/* Preserve the current hw state. */
	intel_dp->DP = I915_READ(intel_dp->output_reg);
4654
	intel_dp->attached_connector = intel_connector;
4655

4656
	if (intel_dp_is_edp(dev, port))
4657
		type = DRM_MODE_CONNECTOR_eDP;
4658 4659
	else
		type = DRM_MODE_CONNECTOR_DisplayPort;
4660

4661 4662 4663 4664 4665 4666 4667 4668
	/*
	 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
	 * for DP the encoder type can be set by the caller to
	 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
	 */
	if (type == DRM_MODE_CONNECTOR_eDP)
		intel_encoder->type = INTEL_OUTPUT_EDP;

4669 4670 4671 4672
	DRM_DEBUG_KMS("Adding %s connector on port %c\n",
			type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
			port_name(port));

4673
	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
4674 4675 4676 4677 4678
	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);

	connector->interlace_allowed = true;
	connector->doublescan_allowed = 0;

4679
	INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4680
			  edp_panel_vdd_work);
4681

4682
	intel_connector_attach_encoder(intel_connector, intel_encoder);
4683
	drm_connector_register(connector);
4684

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Paulo Zanoni 已提交
4685
	if (HAS_DDI(dev))
4686 4687 4688
		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
	else
		intel_connector->get_hw_state = intel_connector_get_hw_state;
4689
	intel_connector->unregister = intel_dp_connector_unregister;
4690

4691
	/* Set up the hotplug pin. */
4692 4693
	switch (port) {
	case PORT_A:
4694
		intel_encoder->hpd_pin = HPD_PORT_A;
4695 4696
		break;
	case PORT_B:
4697
		intel_encoder->hpd_pin = HPD_PORT_B;
4698 4699
		break;
	case PORT_C:
4700
		intel_encoder->hpd_pin = HPD_PORT_C;
4701 4702
		break;
	case PORT_D:
4703
		intel_encoder->hpd_pin = HPD_PORT_D;
4704 4705
		break;
	default:
4706
		BUG();
4707 4708
	}

4709 4710
	if (is_edp(intel_dp)) {
		intel_dp_init_panel_power_timestamps(intel_dp);
4711
		intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
4712
	}
4713

4714
	intel_dp_aux_init(intel_dp, intel_connector);
4715

4716 4717 4718 4719 4720 4721 4722
	/* init MST on ports that can support it */
	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
		if (port == PORT_B || port == PORT_C || port == PORT_D) {
			intel_dp_mst_encoder_init(intel_dig_port, intel_connector->base.base.id);
		}
	}

4723
	if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4724
		drm_dp_aux_unregister(&intel_dp->aux);
4725 4726
		if (is_edp(intel_dp)) {
			cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4727
			drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4728
			edp_panel_vdd_off_sync(intel_dp);
4729
			drm_modeset_unlock(&dev->mode_config.connection_mutex);
4730
		}
4731
		drm_connector_unregister(connector);
4732
		drm_connector_cleanup(connector);
4733
		return false;
4734
	}
4735

4736 4737
	intel_dp_add_properties(intel_dp, connector);

4738 4739 4740 4741 4742 4743 4744 4745
	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
4746 4747

	return true;
4748
}
4749 4750 4751 4752

void
intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
{
4753
	struct drm_i915_private *dev_priv = dev->dev_private;
4754 4755 4756 4757 4758
	struct intel_digital_port *intel_dig_port;
	struct intel_encoder *intel_encoder;
	struct drm_encoder *encoder;
	struct intel_connector *intel_connector;

4759
	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4760 4761 4762
	if (!intel_dig_port)
		return;

4763
	intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
4764 4765 4766 4767 4768 4769 4770 4771 4772 4773 4774
	if (!intel_connector) {
		kfree(intel_dig_port);
		return;
	}

	intel_encoder = &intel_dig_port->base;
	encoder = &intel_encoder->base;

	drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
			 DRM_MODE_ENCODER_TMDS);

4775
	intel_encoder->compute_config = intel_dp_compute_config;
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4776 4777
	intel_encoder->disable = intel_disable_dp;
	intel_encoder->get_hw_state = intel_dp_get_hw_state;
4778
	intel_encoder->get_config = intel_dp_get_config;
4779
	intel_encoder->suspend = intel_dp_encoder_suspend;
4780
	if (IS_CHERRYVIEW(dev)) {
4781
		intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
4782 4783
		intel_encoder->pre_enable = chv_pre_enable_dp;
		intel_encoder->enable = vlv_enable_dp;
4784
		intel_encoder->post_disable = chv_post_disable_dp;
4785
	} else if (IS_VALLEYVIEW(dev)) {
4786
		intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
4787 4788
		intel_encoder->pre_enable = vlv_pre_enable_dp;
		intel_encoder->enable = vlv_enable_dp;
4789
		intel_encoder->post_disable = vlv_post_disable_dp;
4790
	} else {
4791 4792
		intel_encoder->pre_enable = g4x_pre_enable_dp;
		intel_encoder->enable = g4x_enable_dp;
4793
		intel_encoder->post_disable = g4x_post_disable_dp;
4794
	}
4795

4796
	intel_dig_port->port = port;
4797 4798
	intel_dig_port->dp.output_reg = output_reg;

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Paulo Zanoni 已提交
4799
	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4800 4801 4802 4803 4804 4805 4806 4807
	if (IS_CHERRYVIEW(dev)) {
		if (port == PORT_D)
			intel_encoder->crtc_mask = 1 << 2;
		else
			intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
	} else {
		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
	}
4808
	intel_encoder->cloneable = 0;
4809 4810
	intel_encoder->hot_plug = intel_dp_hot_plug;

4811 4812 4813
	intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
	dev_priv->hpd_irq_port[port] = intel_dig_port;

4814 4815 4816
	if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
		drm_encoder_cleanup(encoder);
		kfree(intel_dig_port);
4817
		kfree(intel_connector);
4818
	}
4819
}
4820 4821 4822 4823 4824 4825 4826 4827 4828 4829 4830 4831 4832 4833 4834 4835 4836 4837 4838 4839 4840 4841 4842 4843 4844 4845 4846 4847 4848 4849 4850 4851 4852 4853 4854 4855 4856 4857 4858 4859 4860 4861 4862

void intel_dp_mst_suspend(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	/* disable MST */
	for (i = 0; i < I915_MAX_PORTS; i++) {
		struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
		if (!intel_dig_port)
			continue;

		if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
			if (!intel_dig_port->dp.can_mst)
				continue;
			if (intel_dig_port->dp.is_mst)
				drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
		}
	}
}

void intel_dp_mst_resume(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	for (i = 0; i < I915_MAX_PORTS; i++) {
		struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
		if (!intel_dig_port)
			continue;
		if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
			int ret;

			if (!intel_dig_port->dp.can_mst)
				continue;

			ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
			if (ret != 0) {
				intel_dp_check_mst_status(&intel_dig_port->dp);
			}
		}
	}
}