intel_dp.c 126.7 KB
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/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
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#include "intel_drv.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"

#define DP_LINK_CHECK_TIMEOUT	(10 * 1000)

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struct dp_link_dpll {
	int link_bw;
	struct dpll dpll;
};

static const struct dp_link_dpll gen4_dpll[] = {
	{ DP_LINK_BW_1_62,
		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
	{ DP_LINK_BW_2_7,
		{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
};

static const struct dp_link_dpll pch_dpll[] = {
	{ DP_LINK_BW_1_62,
		{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
	{ DP_LINK_BW_2_7,
		{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
};

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static const struct dp_link_dpll vlv_dpll[] = {
	{ DP_LINK_BW_1_62,
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		{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
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	{ DP_LINK_BW_2_7,
		{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
};

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/*
 * CHV supports eDP 1.4 that have  more link rates.
 * Below only provides the fixed rate but exclude variable rate.
 */
static const struct dp_link_dpll chv_dpll[] = {
	/*
	 * CHV requires to program fractional division for m2.
	 * m2 is stored in fixed point format using formula below
	 * (m2_int << 22) | m2_fraction
	 */
	{ DP_LINK_BW_1_62,	/* m2_int = 32, m2_fraction = 1677722 */
		{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
	{ DP_LINK_BW_2_7,	/* m2_int = 27, m2_fraction = 0 */
		{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
	{ DP_LINK_BW_5_4,	/* m2_int = 27, m2_fraction = 0 */
		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
};

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/**
 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 * @intel_dp: DP struct
 *
 * If a CPU or PCH DP output is attached to an eDP panel, this function
 * will return true, and false otherwise.
 */
static bool is_edp(struct intel_dp *intel_dp)
{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
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}

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static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
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{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.base.dev;
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}

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static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
{
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	return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
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}

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static void intel_dp_link_down(struct intel_dp *intel_dp);
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static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
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static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
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static int
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intel_dp_max_link_bw(struct intel_dp *intel_dp)
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{
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	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
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	struct drm_device *dev = intel_dp->attached_connector->base.dev;
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	switch (max_link_bw) {
	case DP_LINK_BW_1_62:
	case DP_LINK_BW_2_7:
		break;
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	case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
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		if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
		     INTEL_INFO(dev)->gen >= 8) &&
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		    intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
			max_link_bw = DP_LINK_BW_5_4;
		else
			max_link_bw = DP_LINK_BW_2_7;
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		break;
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	default:
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		WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
		     max_link_bw);
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		max_link_bw = DP_LINK_BW_1_62;
		break;
	}
	return max_link_bw;
}

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static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	u8 source_max, sink_max;

	source_max = 4;
	if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
	    (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
		source_max = 2;

	sink_max = drm_dp_max_lane_count(intel_dp->dpcd);

	return min(source_max, sink_max);
}

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/*
 * The units on the numbers in the next two are... bizarre.  Examples will
 * make it clearer; this one parallels an example in the eDP spec.
 *
 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 *
 *     270000 * 1 * 8 / 10 == 216000
 *
 * The actual data capacity of that configuration is 2.16Gbit/s, so the
 * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 * 119000.  At 18bpp that's 2142000 kilobits per second.
 *
 * Thus the strange-looking division by 10 in intel_dp_link_required, to
 * get the result in decakilobits instead of kilobits.
 */

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static int
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intel_dp_link_required(int pixel_clock, int bpp)
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{
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	return (pixel_clock * bpp + 9) / 10;
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}

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static int
intel_dp_max_data_rate(int max_link_clock, int max_lanes)
{
	return (max_link_clock * max_lanes * 8) / 10;
}

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static enum drm_mode_status
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intel_dp_mode_valid(struct drm_connector *connector,
		    struct drm_display_mode *mode)
{
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	struct intel_dp *intel_dp = intel_attached_dp(connector);
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	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
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	int target_clock = mode->clock;
	int max_rate, mode_rate, max_lanes, max_link_clock;
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	if (is_edp(intel_dp) && fixed_mode) {
		if (mode->hdisplay > fixed_mode->hdisplay)
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			return MODE_PANEL;

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		if (mode->vdisplay > fixed_mode->vdisplay)
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			return MODE_PANEL;
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		target_clock = fixed_mode->clock;
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	}

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	max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
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	max_lanes = intel_dp_max_lane_count(intel_dp);
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	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
	mode_rate = intel_dp_link_required(target_clock, 18);

	if (mode_rate > max_rate)
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		return MODE_CLOCK_HIGH;
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	if (mode->clock < 10000)
		return MODE_CLOCK_LOW;

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	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		return MODE_H_ILLEGAL;

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	return MODE_OK;
}

static uint32_t
pack_aux(uint8_t *src, int src_bytes)
{
	int	i;
	uint32_t v = 0;

	if (src_bytes > 4)
		src_bytes = 4;
	for (i = 0; i < src_bytes; i++)
		v |= ((uint32_t) src[i]) << ((3-i) * 8);
	return v;
}

static void
unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
{
	int i;
	if (dst_bytes > 4)
		dst_bytes = 4;
	for (i = 0; i < dst_bytes; i++)
		dst[i] = src >> ((3-i) * 8);
}

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/* hrawclock is 1/4 the FSB frequency */
static int
intel_hrawclk(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t clkcfg;

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	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
	if (IS_VALLEYVIEW(dev))
		return 200;

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	clkcfg = I915_READ(CLKCFG);
	switch (clkcfg & CLKCFG_FSB_MASK) {
	case CLKCFG_FSB_400:
		return 100;
	case CLKCFG_FSB_533:
		return 133;
	case CLKCFG_FSB_667:
		return 166;
	case CLKCFG_FSB_800:
		return 200;
	case CLKCFG_FSB_1067:
		return 266;
	case CLKCFG_FSB_1333:
		return 333;
	/* these two are just a guess; one of them might be right */
	case CLKCFG_FSB_1600:
	case CLKCFG_FSB_1600_ALT:
		return 400;
	default:
		return 133;
	}
}

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static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
				    struct intel_dp *intel_dp,
				    struct edp_power_seq *out);
static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
					      struct intel_dp *intel_dp,
					      struct edp_power_seq *out);

static enum pipe
vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;
	enum pipe pipe;

	/* modeset should have pipe */
	if (crtc)
		return to_intel_crtc(crtc)->pipe;

	/* init time, try to find a pipe with this port selected */
	for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
		u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
			PANEL_PORT_SELECT_MASK;
		if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
			return pipe;
		if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
			return pipe;
	}

	/* shrug */
	return PIPE_A;
}

static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

	if (HAS_PCH_SPLIT(dev))
		return PCH_PP_CONTROL;
	else
		return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
}

static u32 _pp_stat_reg(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

	if (HAS_PCH_SPLIT(dev))
		return PCH_PP_STATUS;
	else
		return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
}

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static bool edp_have_panel_power(struct intel_dp *intel_dp)
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{
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	struct drm_device *dev = intel_dp_to_dev(intel_dp);
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	struct drm_i915_private *dev_priv = dev->dev_private;

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	return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
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}

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static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
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{
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	struct drm_device *dev = intel_dp_to_dev(intel_dp);
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	enum intel_display_power_domain power_domain;
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	power_domain = intel_display_port_power_domain(intel_encoder);
	return intel_display_power_enabled(dev_priv, power_domain) &&
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	       (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
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}

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static void
intel_dp_check_edp(struct intel_dp *intel_dp)
{
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	struct drm_device *dev = intel_dp_to_dev(intel_dp);
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	if (!is_edp(intel_dp))
		return;
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	if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
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		WARN(1, "eDP powered off while attempting aux channel communication.\n");
		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
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			      I915_READ(_pp_stat_reg(intel_dp)),
			      I915_READ(_pp_ctrl_reg(intel_dp)));
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	}
}

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static uint32_t
intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
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	uint32_t status;
	bool done;

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#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
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	if (has_aux_irq)
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		done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
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					  msecs_to_jiffies_timeout(10));
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	else
		done = wait_for_atomic(C, 10) == 0;
	if (!done)
		DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
			  has_aux_irq);
#undef C

	return status;
}

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static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
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{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
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	/*
	 * The clock divider is based off the hrawclk, and would like to run at
	 * 2MHz.  So, take the hrawclk value and divide by 2 and use that
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	 */
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	return index ? 0 : intel_hrawclk(dev) / 2;
}

static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;

	if (index)
		return 0;

	if (intel_dig_port->port == PORT_A) {
		if (IS_GEN6(dev) || IS_GEN7(dev))
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			return 200; /* SNB & IVB eDP input clock at 400Mhz */
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		else
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			return 225; /* eDP input clock at 450Mhz */
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	} else {
		return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
	}
}

static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (intel_dig_port->port == PORT_A) {
		if (index)
			return 0;
		return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
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	} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
		/* Workaround for non-ULT HSW */
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		switch (index) {
		case 0: return 63;
		case 1: return 72;
		default: return 0;
		}
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	} else  {
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		return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
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	}
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}

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static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	return index ? 0 : 100;
}

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static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
				      bool has_aux_irq,
				      int send_bytes,
				      uint32_t aux_clock_divider)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	uint32_t precharge, timeout;

	if (IS_GEN6(dev))
		precharge = 3;
	else
		precharge = 5;

	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
		timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
	else
		timeout = DP_AUX_CH_CTL_TIME_OUT_400us;

	return DP_AUX_CH_CTL_SEND_BUSY |
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	       DP_AUX_CH_CTL_DONE |
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	       (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
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	       DP_AUX_CH_CTL_TIME_OUT_ERROR |
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	       timeout |
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	       DP_AUX_CH_CTL_RECEIVE_ERROR |
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	       (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
	       (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
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	       (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
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}

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static int
intel_dp_aux_ch(struct intel_dp *intel_dp,
		uint8_t *send, int send_bytes,
		uint8_t *recv, int recv_size)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
	uint32_t ch_data = ch_ctl + 4;
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	uint32_t aux_clock_divider;
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	int i, ret, recv_bytes;
	uint32_t status;
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	int try, clock = 0;
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	bool has_aux_irq = HAS_AUX_IRQ(dev);
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	bool vdd;

	vdd = _edp_panel_vdd_on(intel_dp);
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	/* dp aux is extremely sensitive to irq latency, hence request the
	 * lowest possible wakeup latency and so prevent the cpu from going into
	 * deep sleep states.
	 */
	pm_qos_update_request(&dev_priv->pm_qos, 0);

	intel_dp_check_edp(intel_dp);
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	intel_aux_display_runtime_get(dev_priv);

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	/* Try to wait for any previous AUX channel activity */
	for (try = 0; try < 3; try++) {
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		status = I915_READ_NOTRACE(ch_ctl);
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		if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
			break;
		msleep(1);
	}

	if (try == 3) {
		WARN(1, "dp_aux_ch not started status 0x%08x\n",
		     I915_READ(ch_ctl));
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		ret = -EBUSY;
		goto out;
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	}

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	/* Only 5 data registers! */
	if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
		ret = -E2BIG;
		goto out;
	}

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	while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
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		u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
							  has_aux_irq,
							  send_bytes,
							  aux_clock_divider);
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		/* Must try at least 3 times according to DP spec */
		for (try = 0; try < 5; try++) {
			/* Load the send data into the aux channel data registers */
			for (i = 0; i < send_bytes; i += 4)
				I915_WRITE(ch_data + i,
					   pack_aux(send + i, send_bytes - i));

			/* Send the command and wait for it to complete */
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			I915_WRITE(ch_ctl, send_ctl);
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			status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);

			/* Clear done status and any errors */
			I915_WRITE(ch_ctl,
				   status |
				   DP_AUX_CH_CTL_DONE |
				   DP_AUX_CH_CTL_TIME_OUT_ERROR |
				   DP_AUX_CH_CTL_RECEIVE_ERROR);

			if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
				      DP_AUX_CH_CTL_RECEIVE_ERROR))
				continue;
			if (status & DP_AUX_CH_CTL_DONE)
				break;
		}
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		if (status & DP_AUX_CH_CTL_DONE)
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			break;
	}

	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
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		DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
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		ret = -EBUSY;
		goto out;
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	}

	/* Check for timeout or receive error.
	 * Timeouts occur when the sink is not connected
	 */
582
	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
583
		DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
584 585
		ret = -EIO;
		goto out;
586
	}
587 588 589

	/* Timeouts occur when the device isn't connected, so they're
	 * "normal" -- don't fill the kernel log with these */
590
	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
591
		DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
592 593
		ret = -ETIMEDOUT;
		goto out;
594 595 596 597 598 599 600
	}

	/* Unload any bytes sent back from the other side */
	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
		      DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
	if (recv_bytes > recv_size)
		recv_bytes = recv_size;
601

602 603 604
	for (i = 0; i < recv_bytes; i += 4)
		unpack_aux(I915_READ(ch_data + i),
			   recv + i, recv_bytes - i);
605

606 607 608
	ret = recv_bytes;
out:
	pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
609
	intel_aux_display_runtime_put(dev_priv);
610

611 612 613
	if (vdd)
		edp_panel_vdd_off(intel_dp, false);

614
	return ret;
615 616
}

617 618
#define BARE_ADDRESS_SIZE	3
#define HEADER_SIZE		(BARE_ADDRESS_SIZE + 1)
619 620
static ssize_t
intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
621
{
622 623 624
	struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
	uint8_t txbuf[20], rxbuf[20];
	size_t txsize, rxsize;
625 626
	int ret;

627 628 629 630
	txbuf[0] = msg->request << 4;
	txbuf[1] = msg->address >> 8;
	txbuf[2] = msg->address & 0xff;
	txbuf[3] = msg->size - 1;
631

632 633 634
	switch (msg->request & ~DP_AUX_I2C_MOT) {
	case DP_AUX_NATIVE_WRITE:
	case DP_AUX_I2C_WRITE:
635
		txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
636
		rxsize = 1;
637

638 639
		if (WARN_ON(txsize > 20))
			return -E2BIG;
640

641
		memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
642

643 644 645
		ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
		if (ret > 0) {
			msg->reply = rxbuf[0] >> 4;
646

647 648 649 650
			/* Return payload size. */
			ret = msg->size;
		}
		break;
651

652 653
	case DP_AUX_NATIVE_READ:
	case DP_AUX_I2C_READ:
654
		txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
655
		rxsize = msg->size + 1;
656

657 658
		if (WARN_ON(rxsize > 20))
			return -E2BIG;
659

660 661 662 663 664 665 666 667 668 669 670
		ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
		if (ret > 0) {
			msg->reply = rxbuf[0] >> 4;
			/*
			 * Assume happy day, and copy the data. The caller is
			 * expected to check msg->reply before touching it.
			 *
			 * Return payload size.
			 */
			ret--;
			memcpy(msg->buffer, rxbuf + 1, ret);
671
		}
672 673 674 675 676
		break;

	default:
		ret = -EINVAL;
		break;
677
	}
678

679
	return ret;
680 681
}

682 683 684 685
static void
intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
686 687
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	enum port port = intel_dig_port->port;
688
	const char *name = NULL;
689 690
	int ret;

691 692 693
	switch (port) {
	case PORT_A:
		intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
694
		name = "DPDDC-A";
695
		break;
696 697
	case PORT_B:
		intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
698
		name = "DPDDC-B";
699
		break;
700 701
	case PORT_C:
		intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
702
		name = "DPDDC-C";
703
		break;
704 705
	case PORT_D:
		intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
706
		name = "DPDDC-D";
707 708 709
		break;
	default:
		BUG();
710 711
	}

712 713
	if (!HAS_DDI(dev))
		intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
714

715
	intel_dp->aux.name = name;
716 717
	intel_dp->aux.dev = dev->dev;
	intel_dp->aux.transfer = intel_dp_aux_transfer;
718

719 720
	DRM_DEBUG_KMS("registering %s bus for %s\n", name,
		      connector->base.kdev->kobj.name);
721

722
	ret = drm_dp_aux_register(&intel_dp->aux);
723
	if (ret < 0) {
724
		DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
725 726
			  name, ret);
		return;
727
	}
728

729 730 731 732 733
	ret = sysfs_create_link(&connector->base.kdev->kobj,
				&intel_dp->aux.ddc.dev.kobj,
				intel_dp->aux.ddc.dev.kobj.name);
	if (ret < 0) {
		DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
734
		drm_dp_aux_unregister(&intel_dp->aux);
735
	}
736 737
}

738 739 740 741 742 743
static void
intel_dp_connector_unregister(struct intel_connector *intel_connector)
{
	struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);

	sysfs_remove_link(&intel_connector->base.kdev->kobj,
744
			  intel_dp->aux.ddc.dev.kobj.name);
745 746 747
	intel_connector_unregister(intel_connector);
}

748 749 750 751 752
static void
intel_dp_set_clock(struct intel_encoder *encoder,
		   struct intel_crtc_config *pipe_config, int link_bw)
{
	struct drm_device *dev = encoder->base.dev;
753 754
	const struct dp_link_dpll *divisor = NULL;
	int i, count = 0;
755 756

	if (IS_G4X(dev)) {
757 758
		divisor = gen4_dpll;
		count = ARRAY_SIZE(gen4_dpll);
759 760 761
	} else if (IS_HASWELL(dev)) {
		/* Haswell has special-purpose DP DDI clocks. */
	} else if (HAS_PCH_SPLIT(dev)) {
762 763
		divisor = pch_dpll;
		count = ARRAY_SIZE(pch_dpll);
764 765 766
	} else if (IS_CHERRYVIEW(dev)) {
		divisor = chv_dpll;
		count = ARRAY_SIZE(chv_dpll);
767
	} else if (IS_VALLEYVIEW(dev)) {
768 769
		divisor = vlv_dpll;
		count = ARRAY_SIZE(vlv_dpll);
770
	}
771 772 773 774 775 776 777 778 779

	if (divisor && count) {
		for (i = 0; i < count; i++) {
			if (link_bw == divisor[i].link_bw) {
				pipe_config->dpll = divisor[i].dpll;
				pipe_config->clock_set = true;
				break;
			}
		}
780 781 782
	}
}

783 784 785 786 787 788 789 790 791 792 793 794 795 796
static void
intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum transcoder transcoder = crtc->config.cpu_transcoder;

	I915_WRITE(PIPE_DATA_M2(transcoder),
		TU_SIZE(m_n->tu) | m_n->gmch_m);
	I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
	I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
	I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
}

P
Paulo Zanoni 已提交
797
bool
798 799
intel_dp_compute_config(struct intel_encoder *encoder,
			struct intel_crtc_config *pipe_config)
800
{
801
	struct drm_device *dev = encoder->base.dev;
802
	struct drm_i915_private *dev_priv = dev->dev_private;
803 804
	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
805
	enum port port = dp_to_dig_port(intel_dp)->port;
806
	struct intel_crtc *intel_crtc = encoder->new_crtc;
807
	struct intel_connector *intel_connector = intel_dp->attached_connector;
808
	int lane_count, clock;
809
	int min_lane_count = 1;
810
	int max_lane_count = intel_dp_max_lane_count(intel_dp);
811
	/* Conveniently, the link BW constants become indices with a shift...*/
812
	int min_clock = 0;
813
	int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
814
	int bpp, mode_rate;
815
	static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
816
	int link_avail, link_clock;
817

818
	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
819 820
		pipe_config->has_pch_encoder = true;

821
	pipe_config->has_dp_encoder = true;
822
	pipe_config->has_audio = intel_dp->has_audio;
823

824 825 826
	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
		intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
				       adjusted_mode);
827 828 829 830
		if (!HAS_PCH_SPLIT(dev))
			intel_gmch_panel_fitting(intel_crtc, pipe_config,
						 intel_connector->panel.fitting_mode);
		else
831 832
			intel_pch_panel_fitting(intel_crtc, pipe_config,
						intel_connector->panel.fitting_mode);
833 834
	}

835
	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
836 837
		return false;

838 839
	DRM_DEBUG_KMS("DP link computation with max lane count %i "
		      "max bw %02x pixel clock %iKHz\n",
840 841
		      max_lane_count, bws[max_clock],
		      adjusted_mode->crtc_clock);
842

843 844
	/* Walk through all bpp values. Luckily they're all nicely spaced with 2
	 * bpc in between. */
845
	bpp = pipe_config->pipe_bpp;
846 847 848 849 850 851 852
	if (is_edp(intel_dp)) {
		if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
			DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
				      dev_priv->vbt.edp_bpp);
			bpp = dev_priv->vbt.edp_bpp;
		}

853 854 855 856 857 858
		if (IS_BROADWELL(dev)) {
			/* Yes, it's an ugly hack. */
			min_lane_count = max_lane_count;
			DRM_DEBUG_KMS("forcing lane count to max (%u) on BDW\n",
				      min_lane_count);
		} else if (dev_priv->vbt.edp_lanes) {
859 860 861 862 863 864 865 866 867 868 869
			min_lane_count = min(dev_priv->vbt.edp_lanes,
					     max_lane_count);
			DRM_DEBUG_KMS("using min %u lanes per VBT\n",
				      min_lane_count);
		}

		if (dev_priv->vbt.edp_rate) {
			min_clock = min(dev_priv->vbt.edp_rate >> 3, max_clock);
			DRM_DEBUG_KMS("using min %02x link bw per VBT\n",
				      bws[min_clock]);
		}
870
	}
871

872
	for (; bpp >= 6*3; bpp -= 2*3) {
873 874
		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
						   bpp);
875

876 877
		for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
			for (clock = min_clock; clock <= max_clock; clock++) {
878 879 880 881 882 883 884 885 886 887
				link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
				link_avail = intel_dp_max_data_rate(link_clock,
								    lane_count);

				if (mode_rate <= link_avail) {
					goto found;
				}
			}
		}
	}
888

889
	return false;
890

891
found:
892 893 894 895 896 897
	if (intel_dp->color_range_auto) {
		/*
		 * See:
		 * CEA-861-E - 5.1 Default Encoding Parameters
		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
		 */
898
		if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
899 900 901 902 903
			intel_dp->color_range = DP_COLOR_RANGE_16_235;
		else
			intel_dp->color_range = 0;
	}

904
	if (intel_dp->color_range)
905
		pipe_config->limited_color_range = true;
906

907 908
	intel_dp->link_bw = bws[clock];
	intel_dp->lane_count = lane_count;
909
	pipe_config->pipe_bpp = bpp;
910
	pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
911

912 913
	DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
		      intel_dp->link_bw, intel_dp->lane_count,
914
		      pipe_config->port_clock, bpp);
915 916
	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
		      mode_rate, link_avail);
917

918
	intel_link_compute_m_n(bpp, lane_count,
919 920
			       adjusted_mode->crtc_clock,
			       pipe_config->port_clock,
921
			       &pipe_config->dp_m_n);
922

923 924 925 926 927 928 929 930
	if (intel_connector->panel.downclock_mode != NULL &&
		intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
			intel_link_compute_m_n(bpp, lane_count,
				intel_connector->panel.downclock_mode->clock,
				pipe_config->port_clock,
				&pipe_config->dp_m2_n2);
	}

931 932
	intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);

933
	return true;
934 935
}

936
static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
937
{
938 939 940
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
	struct drm_device *dev = crtc->base.dev;
941 942 943
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

944
	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
945 946 947
	dpa_ctl = I915_READ(DP_A);
	dpa_ctl &= ~DP_PLL_FREQ_MASK;

948
	if (crtc->config.port_clock == 162000) {
949 950 951 952
		/* For a long time we've carried around a ILK-DevA w/a for the
		 * 160MHz clock. If we're really unlucky, it's still required.
		 */
		DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
953
		dpa_ctl |= DP_PLL_FREQ_160MHZ;
954
		intel_dp->DP |= DP_PLL_FREQ_160MHZ;
955 956
	} else {
		dpa_ctl |= DP_PLL_FREQ_270MHZ;
957
		intel_dp->DP |= DP_PLL_FREQ_270MHZ;
958
	}
959

960 961 962 963 964 965
	I915_WRITE(DP_A, dpa_ctl);

	POSTING_READ(DP_A);
	udelay(500);
}

966
static void intel_dp_prepare(struct intel_encoder *encoder)
967
{
968
	struct drm_device *dev = encoder->base.dev;
969
	struct drm_i915_private *dev_priv = dev->dev_private;
970
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
971
	enum port port = dp_to_dig_port(intel_dp)->port;
972 973
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
974

975
	/*
K
Keith Packard 已提交
976
	 * There are four kinds of DP registers:
977 978
	 *
	 * 	IBX PCH
K
Keith Packard 已提交
979 980
	 * 	SNB CPU
	 *	IVB CPU
981 982 983 984 985 986 987 988 989 990
	 * 	CPT PCH
	 *
	 * IBX PCH and CPU are the same for almost everything,
	 * except that the CPU DP PLL is configured in this
	 * register
	 *
	 * CPT PCH is quite different, having many bits moved
	 * to the TRANS_DP_CTL register instead. That
	 * configuration happens (oddly) in ironlake_pch_enable
	 */
991

992 993 994 995
	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
996

997 998
	/* Handle DP bits in common between all three register formats */
	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
999
	intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1000

1001
	if (crtc->config.has_audio) {
1002
		DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1003
				 pipe_name(crtc->pipe));
C
Chris Wilson 已提交
1004
		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1005
		intel_write_eld(&encoder->base, adjusted_mode);
1006
	}
1007

1008
	/* Split out the IBX/CPU vs CPT settings */
1009

1010
	if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
K
Keith Packard 已提交
1011 1012 1013 1014 1015 1016
		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

1017
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
K
Keith Packard 已提交
1018 1019
			intel_dp->DP |= DP_ENHANCED_FRAMING;

1020
		intel_dp->DP |= crtc->pipe << 29;
1021
	} else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1022
		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1023
			intel_dp->DP |= intel_dp->color_range;
1024 1025 1026 1027 1028 1029 1030

		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF;

1031
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1032 1033
			intel_dp->DP |= DP_ENHANCED_FRAMING;

1034 1035 1036 1037 1038 1039
		if (!IS_CHERRYVIEW(dev)) {
			if (crtc->pipe == 1)
				intel_dp->DP |= DP_PIPEB_SELECT;
		} else {
			intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
		}
1040 1041
	} else {
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1042
	}
1043 1044
}

1045 1046
#define IDLE_ON_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
#define IDLE_ON_VALUE   	(PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1047

1048 1049
#define IDLE_OFF_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
#define IDLE_OFF_VALUE		(0     | PP_SEQUENCE_NONE | 0                     | 0)
1050

1051 1052
#define IDLE_CYCLE_MASK		(PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
#define IDLE_CYCLE_VALUE	(0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1053

1054
static void wait_panel_status(struct intel_dp *intel_dp,
1055 1056
				       u32 mask,
				       u32 value)
1057
{
1058
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1059
	struct drm_i915_private *dev_priv = dev->dev_private;
1060 1061
	u32 pp_stat_reg, pp_ctrl_reg;

1062 1063
	pp_stat_reg = _pp_stat_reg(intel_dp);
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1064

1065
	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1066 1067 1068
			mask, value,
			I915_READ(pp_stat_reg),
			I915_READ(pp_ctrl_reg));
1069

1070
	if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1071
		DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1072 1073
				I915_READ(pp_stat_reg),
				I915_READ(pp_ctrl_reg));
1074
	}
1075 1076

	DRM_DEBUG_KMS("Wait complete\n");
1077
}
1078

1079
static void wait_panel_on(struct intel_dp *intel_dp)
1080 1081
{
	DRM_DEBUG_KMS("Wait for panel power on\n");
1082
	wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1083 1084
}

1085
static void wait_panel_off(struct intel_dp *intel_dp)
1086 1087
{
	DRM_DEBUG_KMS("Wait for panel power off time\n");
1088
	wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1089 1090
}

1091
static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1092 1093
{
	DRM_DEBUG_KMS("Wait for panel power cycle\n");
1094 1095 1096 1097 1098 1099

	/* When we disable the VDD override bit last we have to do the manual
	 * wait. */
	wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
				       intel_dp->panel_power_cycle_delay);

1100
	wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1101 1102
}

1103
static void wait_backlight_on(struct intel_dp *intel_dp)
1104 1105 1106 1107 1108
{
	wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
				       intel_dp->backlight_on_delay);
}

1109
static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1110 1111 1112 1113
{
	wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
				       intel_dp->backlight_off_delay);
}
1114

1115 1116 1117 1118
/* Read the current pp_control value, unlocking the register if it
 * is locked
 */

1119
static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1120
{
1121 1122 1123
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 control;
1124

1125
	control = I915_READ(_pp_ctrl_reg(intel_dp));
1126 1127 1128
	control &= ~PANEL_UNLOCK_MASK;
	control |= PANEL_UNLOCK_REGS;
	return control;
1129 1130
}

1131
static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
1132
{
1133
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1134 1135
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
1136
	struct drm_i915_private *dev_priv = dev->dev_private;
1137
	enum intel_display_power_domain power_domain;
1138
	u32 pp;
1139
	u32 pp_stat_reg, pp_ctrl_reg;
1140
	bool need_to_disable = !intel_dp->want_panel_vdd;
1141

1142
	if (!is_edp(intel_dp))
1143
		return false;
1144 1145

	intel_dp->want_panel_vdd = true;
1146

1147
	if (edp_have_panel_vdd(intel_dp))
1148
		return need_to_disable;
1149

1150 1151
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);
1152

1153
	DRM_DEBUG_KMS("Turning eDP VDD on\n");
1154

1155 1156
	if (!edp_have_panel_power(intel_dp))
		wait_panel_power_cycle(intel_dp);
1157

1158
	pp = ironlake_get_pp_control(intel_dp);
1159
	pp |= EDP_FORCE_VDD;
1160

1161 1162
	pp_stat_reg = _pp_stat_reg(intel_dp);
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1163 1164 1165 1166 1167

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
			I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1168 1169 1170
	/*
	 * If the panel wasn't on, delay before accessing aux channel
	 */
1171
	if (!edp_have_panel_power(intel_dp)) {
1172
		DRM_DEBUG_KMS("eDP was not running\n");
1173 1174
		msleep(intel_dp->panel_power_up_delay);
	}
1175 1176 1177 1178

	return need_to_disable;
}

1179
void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1180 1181 1182 1183 1184 1185
{
	if (is_edp(intel_dp)) {
		bool vdd = _edp_panel_vdd_on(intel_dp);

		WARN(!vdd, "eDP VDD already requested on\n");
	}
1186 1187
}

1188
static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1189
{
1190
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1191 1192
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
1193
	u32 pp_stat_reg, pp_ctrl_reg;
1194

1195
	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
1196

1197
	if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1198 1199 1200 1201 1202
		struct intel_digital_port *intel_dig_port =
						dp_to_dig_port(intel_dp);
		struct intel_encoder *intel_encoder = &intel_dig_port->base;
		enum intel_display_power_domain power_domain;

1203 1204
		DRM_DEBUG_KMS("Turning eDP VDD off\n");

1205
		pp = ironlake_get_pp_control(intel_dp);
1206 1207
		pp &= ~EDP_FORCE_VDD;

1208 1209
		pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
		pp_stat_reg = _pp_stat_reg(intel_dp);
1210 1211 1212

		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1213

1214 1215 1216
		/* Make sure sequencer is idle before allowing subsequent activity */
		DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
		I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
P
Paulo Zanoni 已提交
1217 1218

		if ((pp & POWER_TARGET_ON) == 0)
1219
			intel_dp->last_power_cycle = jiffies;
1220

1221 1222
		power_domain = intel_display_port_power_domain(intel_encoder);
		intel_display_power_put(dev_priv, power_domain);
1223 1224
	}
}
1225

1226
static void edp_panel_vdd_work(struct work_struct *__work)
1227 1228 1229
{
	struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
						 struct intel_dp, panel_vdd_work);
1230
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1231

1232
	drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
1233
	edp_panel_vdd_off_sync(intel_dp);
1234
	drm_modeset_unlock(&dev->mode_config.connection_mutex);
1235 1236
}

1237
static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1238
{
1239 1240
	if (!is_edp(intel_dp))
		return;
1241

1242
	WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1243

1244 1245 1246
	intel_dp->want_panel_vdd = false;

	if (sync) {
1247
		edp_panel_vdd_off_sync(intel_dp);
1248 1249 1250 1251 1252 1253 1254 1255 1256
	} else {
		/*
		 * Queue the timer to fire a long
		 * time from now (relative to the power down delay)
		 * to keep the panel power up across a sequence of operations
		 */
		schedule_delayed_work(&intel_dp->panel_vdd_work,
				      msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
	}
1257 1258
}

1259
void intel_edp_panel_on(struct intel_dp *intel_dp)
1260
{
1261
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1262
	struct drm_i915_private *dev_priv = dev->dev_private;
1263
	u32 pp;
1264
	u32 pp_ctrl_reg;
1265

1266
	if (!is_edp(intel_dp))
1267
		return;
1268 1269 1270

	DRM_DEBUG_KMS("Turn eDP power on\n");

1271
	if (edp_have_panel_power(intel_dp)) {
1272
		DRM_DEBUG_KMS("eDP power already on\n");
1273
		return;
1274
	}
1275

1276
	wait_panel_power_cycle(intel_dp);
1277

1278
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1279
	pp = ironlake_get_pp_control(intel_dp);
1280 1281 1282
	if (IS_GEN5(dev)) {
		/* ILK workaround: disable reset around power sequence */
		pp &= ~PANEL_POWER_RESET;
1283 1284
		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1285
	}
1286

1287
	pp |= POWER_TARGET_ON;
1288 1289 1290
	if (!IS_GEN5(dev))
		pp |= PANEL_POWER_RESET;

1291 1292
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1293

1294
	wait_panel_on(intel_dp);
1295
	intel_dp->last_power_on = jiffies;
1296

1297 1298
	if (IS_GEN5(dev)) {
		pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1299 1300
		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1301
	}
1302 1303
}

1304
void intel_edp_panel_off(struct intel_dp *intel_dp)
1305
{
1306 1307
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
1308
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1309
	struct drm_i915_private *dev_priv = dev->dev_private;
1310
	enum intel_display_power_domain power_domain;
1311
	u32 pp;
1312
	u32 pp_ctrl_reg;
1313

1314 1315
	if (!is_edp(intel_dp))
		return;
1316

1317
	DRM_DEBUG_KMS("Turn eDP power off\n");
1318

1319
	edp_wait_backlight_off(intel_dp);
1320

1321 1322
	WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");

1323
	pp = ironlake_get_pp_control(intel_dp);
1324 1325
	/* We need to switch off panel power _and_ force vdd, for otherwise some
	 * panels get very unhappy and cease to work. */
1326 1327
	pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
		EDP_BLC_ENABLE);
1328

1329
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1330

1331 1332
	intel_dp->want_panel_vdd = false;

1333 1334
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1335

1336
	intel_dp->last_power_cycle = jiffies;
1337
	wait_panel_off(intel_dp);
1338 1339

	/* We got a reference when we enabled the VDD. */
1340 1341
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_put(dev_priv, power_domain);
1342 1343
}

1344
void intel_edp_backlight_on(struct intel_dp *intel_dp)
1345
{
1346 1347
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
1348 1349
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
1350
	u32 pp_ctrl_reg;
1351

1352 1353 1354
	if (!is_edp(intel_dp))
		return;

1355
	DRM_DEBUG_KMS("\n");
1356 1357 1358 1359 1360 1361
	/*
	 * If we enable the backlight right away following a panel power
	 * on, we may see slight flicker as the panel syncs with the eDP
	 * link.  So delay a bit to make sure the image is solid before
	 * allowing it to appear.
	 */
1362
	wait_backlight_on(intel_dp);
1363
	pp = ironlake_get_pp_control(intel_dp);
1364
	pp |= EDP_BLC_ENABLE;
1365

1366
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1367 1368 1369

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1370

1371
	intel_panel_enable_backlight(intel_dp->attached_connector);
1372 1373
}

1374
void intel_edp_backlight_off(struct intel_dp *intel_dp)
1375
{
1376
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1377 1378
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
1379
	u32 pp_ctrl_reg;
1380

1381 1382 1383
	if (!is_edp(intel_dp))
		return;

1384
	intel_panel_disable_backlight(intel_dp->attached_connector);
1385

1386
	DRM_DEBUG_KMS("\n");
1387
	pp = ironlake_get_pp_control(intel_dp);
1388
	pp &= ~EDP_BLC_ENABLE;
1389

1390
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1391 1392 1393

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1394
	intel_dp->last_backlight_off = jiffies;
1395
}
1396

1397
static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1398
{
1399 1400 1401
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = crtc->dev;
1402 1403 1404
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

1405 1406 1407
	assert_pipe_disabled(dev_priv,
			     to_intel_crtc(crtc)->pipe);

1408 1409
	DRM_DEBUG_KMS("\n");
	dpa_ctl = I915_READ(DP_A);
1410 1411 1412 1413 1414 1415 1416 1417 1418
	WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");

	/* We don't adjust intel_dp->DP while tearing down the link, to
	 * facilitate link retraining (e.g. after hotplug). Hence clear all
	 * enable bits here to ensure that we don't enable too much. */
	intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
	intel_dp->DP |= DP_PLL_ENABLE;
	I915_WRITE(DP_A, intel_dp->DP);
1419 1420
	POSTING_READ(DP_A);
	udelay(200);
1421 1422
}

1423
static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1424
{
1425 1426 1427
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = crtc->dev;
1428 1429 1430
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

1431 1432 1433
	assert_pipe_disabled(dev_priv,
			     to_intel_crtc(crtc)->pipe);

1434
	dpa_ctl = I915_READ(DP_A);
1435 1436 1437 1438 1439 1440 1441
	WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
	     "dp pll off, should be on\n");
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");

	/* We can't rely on the value tracked for the DP register in
	 * intel_dp->DP because link_down must not change that (otherwise link
	 * re-training will fail. */
1442
	dpa_ctl &= ~DP_PLL_ENABLE;
1443
	I915_WRITE(DP_A, dpa_ctl);
1444
	POSTING_READ(DP_A);
1445 1446 1447
	udelay(200);
}

1448
/* If the sink supports it, try to set the power state appropriately */
1449
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1450 1451 1452 1453 1454 1455 1456 1457
{
	int ret, i;

	/* Should have a valid DPCD by this point */
	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
		return;

	if (mode != DRM_MODE_DPMS_ON) {
1458 1459
		ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
					 DP_SET_POWER_D3);
1460 1461 1462 1463 1464 1465 1466 1467
		if (ret != 1)
			DRM_DEBUG_DRIVER("failed to write sink power state\n");
	} else {
		/*
		 * When turning on, we need to retry for 1ms to give the sink
		 * time to wake up.
		 */
		for (i = 0; i < 3; i++) {
1468 1469
			ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
						 DP_SET_POWER_D0);
1470 1471 1472 1473 1474 1475 1476
			if (ret == 1)
				break;
			msleep(1);
		}
	}
}

1477 1478
static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
				  enum pipe *pipe)
1479
{
1480
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1481
	enum port port = dp_to_dig_port(intel_dp)->port;
1482 1483
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1484 1485 1486 1487 1488 1489 1490 1491
	enum intel_display_power_domain power_domain;
	u32 tmp;

	power_domain = intel_display_port_power_domain(encoder);
	if (!intel_display_power_enabled(dev_priv, power_domain))
		return false;

	tmp = I915_READ(intel_dp->output_reg);
1492 1493 1494 1495

	if (!(tmp & DP_PORT_EN))
		return false;

1496
	if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1497
		*pipe = PORT_TO_PIPE_CPT(tmp);
1498 1499
	} else if (IS_CHERRYVIEW(dev)) {
		*pipe = DP_PORT_TO_PIPE_CHV(tmp);
1500
	} else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524 1525 1526 1527 1528
		*pipe = PORT_TO_PIPE(tmp);
	} else {
		u32 trans_sel;
		u32 trans_dp;
		int i;

		switch (intel_dp->output_reg) {
		case PCH_DP_B:
			trans_sel = TRANS_DP_PORT_SEL_B;
			break;
		case PCH_DP_C:
			trans_sel = TRANS_DP_PORT_SEL_C;
			break;
		case PCH_DP_D:
			trans_sel = TRANS_DP_PORT_SEL_D;
			break;
		default:
			return true;
		}

		for_each_pipe(i) {
			trans_dp = I915_READ(TRANS_DP_CTL(i));
			if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
				*pipe = i;
				return true;
			}
		}

1529 1530 1531
		DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
			      intel_dp->output_reg);
	}
1532

1533 1534
	return true;
}
1535

1536 1537 1538 1539 1540
static void intel_dp_get_config(struct intel_encoder *encoder,
				struct intel_crtc_config *pipe_config)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	u32 tmp, flags = 0;
1541 1542 1543 1544
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = dp_to_dig_port(intel_dp)->port;
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1545
	int dotclock;
1546

1547 1548 1549 1550
	tmp = I915_READ(intel_dp->output_reg);
	if (tmp & DP_AUDIO_OUTPUT_ENABLE)
		pipe_config->has_audio = true;

1551 1552 1553 1554 1555
	if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
		if (tmp & DP_SYNC_HS_HIGH)
			flags |= DRM_MODE_FLAG_PHSYNC;
		else
			flags |= DRM_MODE_FLAG_NHSYNC;
1556

1557 1558 1559 1560 1561 1562 1563 1564 1565 1566
		if (tmp & DP_SYNC_VS_HIGH)
			flags |= DRM_MODE_FLAG_PVSYNC;
		else
			flags |= DRM_MODE_FLAG_NVSYNC;
	} else {
		tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
		if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
			flags |= DRM_MODE_FLAG_PHSYNC;
		else
			flags |= DRM_MODE_FLAG_NHSYNC;
1567

1568 1569 1570 1571 1572
		if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
			flags |= DRM_MODE_FLAG_PVSYNC;
		else
			flags |= DRM_MODE_FLAG_NVSYNC;
	}
1573 1574

	pipe_config->adjusted_mode.flags |= flags;
1575

1576 1577 1578 1579
	pipe_config->has_dp_encoder = true;

	intel_dp_get_m_n(crtc, pipe_config);

1580
	if (port == PORT_A) {
1581 1582 1583 1584 1585
		if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
			pipe_config->port_clock = 162000;
		else
			pipe_config->port_clock = 270000;
	}
1586 1587 1588 1589 1590 1591 1592

	dotclock = intel_dotclock_calculate(pipe_config->port_clock,
					    &pipe_config->dp_m_n);

	if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
		ironlake_check_encoder_dotclock(pipe_config, dotclock);

1593
	pipe_config->adjusted_mode.crtc_clock = dotclock;
1594

1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613
	if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
	    pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
		/*
		 * This is a big fat ugly hack.
		 *
		 * Some machines in UEFI boot mode provide us a VBT that has 18
		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
		 * unknown we fail to light up. Yet the same BIOS boots up with
		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
		 * max, not what it tells us to use.
		 *
		 * Note: This will still be broken if the eDP panel is not lit
		 * up by the BIOS, and thus we can't get the mode at module
		 * load.
		 */
		DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
			      pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
		dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
	}
1614 1615
}

1616
static bool is_edp_psr(struct intel_dp *intel_dp)
1617
{
1618
	return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
1619 1620
}

R
Rodrigo Vivi 已提交
1621 1622 1623 1624
static bool intel_edp_is_psr_enabled(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

1625
	if (!HAS_PSR(dev))
R
Rodrigo Vivi 已提交
1626 1627
		return false;

1628
	return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
R
Rodrigo Vivi 已提交
1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663 1664 1665
}

static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
				    struct edp_vsc_psr *vsc_psr)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
	u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
	uint32_t *data = (uint32_t *) vsc_psr;
	unsigned int i;

	/* As per BSPec (Pipe Video Data Island Packet), we need to disable
	   the video DIP being updated before program video DIP data buffer
	   registers for DIP being updated. */
	I915_WRITE(ctl_reg, 0);
	POSTING_READ(ctl_reg);

	for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
		if (i < sizeof(struct edp_vsc_psr))
			I915_WRITE(data_reg + i, *data++);
		else
			I915_WRITE(data_reg + i, 0);
	}

	I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
	POSTING_READ(ctl_reg);
}

static void intel_edp_psr_setup(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct edp_vsc_psr psr_vsc;

1666
	if (dev_priv->psr.setup_done)
R
Rodrigo Vivi 已提交
1667 1668 1669 1670 1671 1672 1673 1674 1675 1676 1677
		return;

	/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
	memset(&psr_vsc, 0, sizeof(psr_vsc));
	psr_vsc.sdp_header.HB0 = 0;
	psr_vsc.sdp_header.HB1 = 0x7;
	psr_vsc.sdp_header.HB2 = 0x2;
	psr_vsc.sdp_header.HB3 = 0x8;
	intel_edp_psr_write_vsc(intel_dp, &psr_vsc);

	/* Avoid continuous PSR exit by masking memup and hpd */
1678
	I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1679
		   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
R
Rodrigo Vivi 已提交
1680

1681
	dev_priv->psr.setup_done = true;
R
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1682 1683 1684 1685
}

static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
{
1686 1687
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
R
Rodrigo Vivi 已提交
1688
	struct drm_i915_private *dev_priv = dev->dev_private;
1689
	uint32_t aux_clock_divider;
R
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1690 1691
	int precharge = 0x3;
	int msg_size = 5;       /* Header(4) + Message(1) */
1692
	bool only_standby = false;
R
Rodrigo Vivi 已提交
1693

1694 1695
	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);

1696 1697 1698
	if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
		only_standby = true;

R
Rodrigo Vivi 已提交
1699
	/* Enable PSR in sink */
1700
	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
1701 1702
		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
				   DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
R
Rodrigo Vivi 已提交
1703
	else
1704 1705
		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
				   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
R
Rodrigo Vivi 已提交
1706 1707

	/* Setup AUX registers */
1708 1709 1710
	I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
	I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
	I915_WRITE(EDP_PSR_AUX_CTL(dev),
R
Rodrigo Vivi 已提交
1711 1712 1713 1714 1715 1716 1717 1718
		   DP_AUX_CH_CTL_TIME_OUT_400us |
		   (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
		   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
		   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
}

static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
{
1719 1720
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
R
Rodrigo Vivi 已提交
1721 1722 1723 1724
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t max_sleep_time = 0x1f;
	uint32_t idle_frames = 1;
	uint32_t val = 0x0;
B
Ben Widawsky 已提交
1725
	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
1726 1727 1728 1729
	bool only_standby = false;

	if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
		only_standby = true;
R
Rodrigo Vivi 已提交
1730

1731
	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
R
Rodrigo Vivi 已提交
1732 1733 1734 1735
		val |= EDP_PSR_LINK_STANDBY;
		val |= EDP_PSR_TP2_TP3_TIME_0us;
		val |= EDP_PSR_TP1_TIME_0us;
		val |= EDP_PSR_SKIP_AUX_EXIT;
1736
		val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
R
Rodrigo Vivi 已提交
1737 1738 1739
	} else
		val |= EDP_PSR_LINK_DISABLE;

1740
	I915_WRITE(EDP_PSR_CTL(dev), val |
B
Ben Widawsky 已提交
1741
		   (IS_BROADWELL(dev) ? 0 : link_entry_time) |
R
Rodrigo Vivi 已提交
1742 1743 1744 1745 1746
		   max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
		   idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
		   EDP_PSR_ENABLE);
}

1747 1748 1749 1750 1751 1752 1753
static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dig_port->base.base.crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1754
	struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
1755 1756
	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;

R
Rodrigo Vivi 已提交
1757 1758
	dev_priv->psr.source_ok = false;

1759 1760 1761 1762 1763 1764 1765
	if (!HAS_PSR(dev)) {
		DRM_DEBUG_KMS("PSR not supported on this platform\n");
		return false;
	}

	if (IS_HASWELL(dev) && (intel_encoder->type != INTEL_OUTPUT_EDP ||
				dig_port->port != PORT_A)) {
1766 1767 1768 1769
		DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
		return false;
	}

1770
	if (!i915.enable_psr) {
1771 1772 1773 1774
		DRM_DEBUG_KMS("PSR disable by flag\n");
		return false;
	}

1775 1776 1777 1778 1779 1780 1781
	crtc = dig_port->base.base.crtc;
	if (crtc == NULL) {
		DRM_DEBUG_KMS("crtc not active for PSR\n");
		return false;
	}

	intel_crtc = to_intel_crtc(crtc);
1782
	if (!intel_crtc_active(crtc)) {
1783 1784 1785 1786
		DRM_DEBUG_KMS("crtc not active for PSR\n");
		return false;
	}

1787
	obj = to_intel_framebuffer(crtc->primary->fb)->obj;
1788 1789 1790 1791 1792 1793
	if (obj->tiling_mode != I915_TILING_X ||
	    obj->fence_reg == I915_FENCE_REG_NONE) {
		DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
		return false;
	}

1794 1795 1796 1797
	/* Below limitations aren't valid for Broadwell */
	if (IS_BROADWELL(dev))
		goto out;

1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808
	if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
		DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
		return false;
	}

	if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
	    S3D_ENABLE) {
		DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
		return false;
	}

1809
	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1810 1811 1812 1813
		DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
		return false;
	}

1814
 out:
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Rodrigo Vivi 已提交
1815
	dev_priv->psr.source_ok = true;
1816 1817 1818
	return true;
}

1819
static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
R
Rodrigo Vivi 已提交
1820
{
1821 1822 1823
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
R
Rodrigo Vivi 已提交
1824

1825
	if (intel_edp_is_psr_enabled(dev))
R
Rodrigo Vivi 已提交
1826 1827 1828 1829 1830 1831 1832
		return;

	/* Enable PSR on the panel */
	intel_edp_psr_enable_sink(intel_dp);

	/* Enable PSR on the host */
	intel_edp_psr_enable_source(intel_dp);
1833 1834 1835

	dev_priv->psr.enabled = true;
	dev_priv->psr.active = true;
R
Rodrigo Vivi 已提交
1836 1837
}

1838 1839 1840 1841
void intel_edp_psr_enable(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

1842 1843 1844 1845 1846
	if (!HAS_PSR(dev)) {
		DRM_DEBUG_KMS("PSR not supported on this platform\n");
		return;
	}

1847 1848 1849 1850 1851
	if (!is_edp_psr(intel_dp)) {
		DRM_DEBUG_KMS("PSR not supported by this panel\n");
		return;
	}

1852 1853 1854
	/* Setup PSR once */
	intel_edp_psr_setup(intel_dp);

1855
	if (intel_edp_psr_match_conditions(intel_dp))
1856 1857 1858
		intel_edp_psr_do_enable(intel_dp);
}

R
Rodrigo Vivi 已提交
1859 1860 1861 1862 1863
void intel_edp_psr_disable(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;

1864
	if (!dev_priv->psr.enabled)
R
Rodrigo Vivi 已提交
1865 1866
		return;

1867 1868
	I915_WRITE(EDP_PSR_CTL(dev),
		   I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
R
Rodrigo Vivi 已提交
1869 1870

	/* Wait till PSR is idle */
1871
	if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
R
Rodrigo Vivi 已提交
1872 1873
		       EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
		DRM_ERROR("Timed out waiting for PSR Idle State\n");
1874 1875

	dev_priv->psr.enabled = false;
R
Rodrigo Vivi 已提交
1876 1877
}

1878
static void intel_edp_psr_work(struct work_struct *work)
1879 1880 1881 1882 1883 1884 1885
{
	struct drm_i915_private *dev_priv =
		container_of(work, typeof(*dev_priv), psr.work.work);
	struct drm_device *dev = dev_priv->dev;
	struct intel_encoder *encoder;
	struct intel_dp *intel_dp = NULL;

1886 1887 1888 1889 1890 1891 1892
	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
		if (encoder->type == INTEL_OUTPUT_EDP) {
			intel_dp = enc_to_intel_dp(&encoder->base);

			if (!intel_edp_psr_match_conditions(intel_dp))
				intel_edp_psr_disable(intel_dp);
			else
1893
				intel_edp_psr_do_enable(intel_dp);
1894 1895 1896
		}
}

1897
static void intel_edp_psr_inactivate(struct drm_device *dev)
1898 1899 1900
{
	struct drm_i915_private *dev_priv = dev->dev_private;

1901
	dev_priv->psr.active = false;
1902

1903 1904
	I915_WRITE(EDP_PSR_CTL(dev), I915_READ(EDP_PSR_CTL(dev))
		   & ~EDP_PSR_ENABLE);
1905 1906
}

1907
void intel_edp_psr_exit(struct drm_device *dev)
1908 1909 1910 1911 1912 1913 1914 1915 1916 1917 1918 1919 1920 1921
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!HAS_PSR(dev))
		return;

	if (!dev_priv->psr.setup_done)
		return;

	cancel_delayed_work_sync(&dev_priv->psr.work);

	if (dev_priv->psr.active)
		intel_edp_psr_inactivate(dev);

1922 1923
	schedule_delayed_work(&dev_priv->psr.work,
			      msecs_to_jiffies(100));
1924 1925 1926 1927 1928 1929 1930 1931 1932 1933 1934 1935
}

void intel_edp_psr_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!HAS_PSR(dev))
		return;

	INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
}

1936
static void intel_disable_dp(struct intel_encoder *encoder)
1937
{
1938
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1939 1940
	enum port port = dp_to_dig_port(intel_dp)->port;
	struct drm_device *dev = encoder->base.dev;
1941 1942 1943

	/* Make sure the panel is off before trying to change the mode. But also
	 * ensure that we have vdd while we switch off the panel. */
1944
	intel_edp_panel_vdd_on(intel_dp);
1945
	intel_edp_backlight_off(intel_dp);
1946
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1947
	intel_edp_panel_off(intel_dp);
1948 1949

	/* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1950
	if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1951
		intel_dp_link_down(intel_dp);
1952 1953
}

1954
static void g4x_post_disable_dp(struct intel_encoder *encoder)
1955
{
1956
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1957
	enum port port = dp_to_dig_port(intel_dp)->port;
1958

1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969 1970
	if (port != PORT_A)
		return;

	intel_dp_link_down(intel_dp);
	ironlake_edp_pll_off(intel_dp);
}

static void vlv_post_disable_dp(struct intel_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

	intel_dp_link_down(intel_dp);
1971 1972
}

1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989
static void chv_post_disable_dp(struct intel_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel ch = vlv_dport_to_channel(dport);
	enum pipe pipe = intel_crtc->pipe;
	u32 val;

	intel_dp_link_down(intel_dp);

	mutex_lock(&dev_priv->dpio_lock);

	/* Propagate soft reset to data lane reset */
1990
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
1991
	val |= CHV_PCS_REQ_SOFTRESET_EN;
1992
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
1993

1994 1995 1996 1997 1998 1999 2000 2001 2002
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
	val |= CHV_PCS_REQ_SOFTRESET_EN;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2003
	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2004
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2005 2006 2007 2008

	mutex_unlock(&dev_priv->dpio_lock);
}

2009
static void intel_enable_dp(struct intel_encoder *encoder)
2010
{
2011 2012 2013 2014
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2015

2016 2017
	if (WARN_ON(dp_reg & DP_PORT_EN))
		return;
2018

2019
	intel_edp_panel_vdd_on(intel_dp);
2020
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2021
	intel_dp_start_link_train(intel_dp);
2022 2023
	intel_edp_panel_on(intel_dp);
	edp_panel_vdd_off(intel_dp, true);
2024
	intel_dp_complete_link_train(intel_dp);
2025
	intel_dp_stop_link_train(intel_dp);
2026
}
2027

2028 2029
static void g4x_enable_dp(struct intel_encoder *encoder)
{
2030 2031
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

2032
	intel_enable_dp(encoder);
2033
	intel_edp_backlight_on(intel_dp);
2034
}
2035

2036 2037
static void vlv_enable_dp(struct intel_encoder *encoder)
{
2038 2039
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

2040
	intel_edp_backlight_on(intel_dp);
2041 2042
}

2043
static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2044 2045 2046 2047
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);

2048 2049
	intel_dp_prepare(encoder);

2050 2051 2052
	/* Only ilk+ has port A */
	if (dport->port == PORT_A) {
		ironlake_set_pll_cpu_edp(intel_dp);
2053
		ironlake_edp_pll_on(intel_dp);
2054
	}
2055 2056 2057
}

static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2058
{
2059
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2060
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2061
	struct drm_device *dev = encoder->base.dev;
2062
	struct drm_i915_private *dev_priv = dev->dev_private;
2063
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2064
	enum dpio_channel port = vlv_dport_to_channel(dport);
2065
	int pipe = intel_crtc->pipe;
2066
	struct edp_power_seq power_seq;
2067
	u32 val;
2068

2069
	mutex_lock(&dev_priv->dpio_lock);
2070

2071
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2072 2073 2074 2075 2076 2077
	val = 0;
	if (pipe)
		val |= (1<<21);
	else
		val &= ~(1<<21);
	val |= 0x001000c4;
2078 2079 2080
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2081

2082 2083
	mutex_unlock(&dev_priv->dpio_lock);

2084 2085 2086 2087 2088 2089
	if (is_edp(intel_dp)) {
		/* init power sequencer on this pipe and port */
		intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
		intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
							      &power_seq);
	}
2090

2091 2092
	intel_enable_dp(encoder);

2093
	vlv_wait_port_ready(dev_priv, dport);
2094 2095
}

2096
static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2097 2098 2099 2100
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2101 2102
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
2103
	enum dpio_channel port = vlv_dport_to_channel(dport);
2104
	int pipe = intel_crtc->pipe;
2105

2106 2107
	intel_dp_prepare(encoder);

2108
	/* Program Tx lane resets to default */
2109
	mutex_lock(&dev_priv->dpio_lock);
2110
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2111 2112
			 DPIO_PCS_TX_LANE2_RESET |
			 DPIO_PCS_TX_LANE1_RESET);
2113
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2114 2115 2116 2117 2118 2119
			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
				 DPIO_PCS_CLK_SOFT_RESET);

	/* Fix up inter-pair skew failure */
2120 2121 2122
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2123
	mutex_unlock(&dev_priv->dpio_lock);
2124 2125
}

2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137
static void chv_pre_enable_dp(struct intel_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct edp_power_seq power_seq;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel ch = vlv_dport_to_channel(dport);
	int pipe = intel_crtc->pipe;
	int data, i;
2138
	u32 val;
2139 2140

	mutex_lock(&dev_priv->dpio_lock);
2141 2142

	/* Deassert soft data lane reset*/
2143
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2144
	val |= CHV_PCS_REQ_SOFTRESET_EN;
2145 2146 2147 2148 2149 2150 2151 2152 2153
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
	val |= CHV_PCS_REQ_SOFTRESET_EN;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2154

2155
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2156
	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2157
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2158 2159

	/* Program Tx lane latency optimal setting*/
2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188
	for (i = 0; i < 4; i++) {
		/* Set the latency optimal bit */
		data = (i == 1) ? 0x0 : 0x6;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
				data << DPIO_FRC_LATENCY_SHFIT);

		/* Set the upar bit */
		data = (i == 1) ? 0x0 : 0x1;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
				data << DPIO_UPAR_SHIFT);
	}

	/* Data lane stagger programming */
	/* FIXME: Fix up value only after power analysis */

	mutex_unlock(&dev_priv->dpio_lock);

	if (is_edp(intel_dp)) {
		/* init power sequencer on this pipe and port */
		intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
		intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
							      &power_seq);
	}

	intel_enable_dp(encoder);

	vlv_wait_port_ready(dev_priv, dport);
}

2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201
static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel ch = vlv_dport_to_channel(dport);
	enum pipe pipe = intel_crtc->pipe;
	u32 val;

	mutex_lock(&dev_priv->dpio_lock);

2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220
	/* program left/right clock distribution */
	if (pipe != PIPE_B) {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
		if (ch == DPIO_CH0)
			val |= CHV_BUFLEFTENA1_FORCE;
		if (ch == DPIO_CH1)
			val |= CHV_BUFRIGHTENA1_FORCE;
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
	} else {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
		if (ch == DPIO_CH0)
			val |= CHV_BUFLEFTENA2_FORCE;
		if (ch == DPIO_CH1)
			val |= CHV_BUFRIGHTENA2_FORCE;
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
	}

2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252
	/* program clock channel usage */
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
	if (pipe != PIPE_B)
		val &= ~CHV_PCS_USEDCLKCHANNEL;
	else
		val |= CHV_PCS_USEDCLKCHANNEL;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
	if (pipe != PIPE_B)
		val &= ~CHV_PCS_USEDCLKCHANNEL;
	else
		val |= CHV_PCS_USEDCLKCHANNEL;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);

	/*
	 * This a a bit weird since generally CL
	 * matches the pipe, but here we need to
	 * pick the CL based on the port.
	 */
	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
	if (pipe != PIPE_B)
		val &= ~CHV_CMN_USEDCLKCHANNEL;
	else
		val |= CHV_CMN_USEDCLKCHANNEL;
	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);

	mutex_unlock(&dev_priv->dpio_lock);
}

2253
/*
2254 2255
 * Native read with retry for link status and receiver capability reads for
 * cases where the sink may still be asleep.
2256 2257 2258
 *
 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
 * supposed to retry 3 times per the spec.
2259
 */
2260 2261 2262
static ssize_t
intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
			void *buffer, size_t size)
2263
{
2264 2265
	ssize_t ret;
	int i;
2266 2267

	for (i = 0; i < 3; i++) {
2268 2269 2270
		ret = drm_dp_dpcd_read(aux, offset, buffer, size);
		if (ret == size)
			return ret;
2271 2272
		msleep(1);
	}
2273

2274
	return ret;
2275 2276 2277 2278 2279 2280 2281
}

/*
 * Fetch AUX CH registers 0x202 - 0x207 which contain
 * link status information
 */
static bool
2282
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2283
{
2284 2285 2286 2287
	return intel_dp_dpcd_read_wake(&intel_dp->aux,
				       DP_LANE0_1_STATUS,
				       link_status,
				       DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2288 2289
}

2290
/* These are source-specific values. */
2291
static uint8_t
K
Keith Packard 已提交
2292
intel_dp_voltage_max(struct intel_dp *intel_dp)
2293
{
2294
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2295
	enum port port = dp_to_dig_port(intel_dp)->port;
K
Keith Packard 已提交
2296

2297
	if (IS_VALLEYVIEW(dev))
2298
		return DP_TRAIN_VOLTAGE_SWING_1200;
2299
	else if (IS_GEN7(dev) && port == PORT_A)
K
Keith Packard 已提交
2300
		return DP_TRAIN_VOLTAGE_SWING_800;
2301
	else if (HAS_PCH_CPT(dev) && port != PORT_A)
K
Keith Packard 已提交
2302 2303 2304 2305 2306 2307 2308 2309
		return DP_TRAIN_VOLTAGE_SWING_1200;
	else
		return DP_TRAIN_VOLTAGE_SWING_800;
}

static uint8_t
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
{
2310
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2311
	enum port port = dp_to_dig_port(intel_dp)->port;
K
Keith Packard 已提交
2312

2313
	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_9_5;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336
	} else if (IS_VALLEYVIEW(dev)) {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_9_5;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
2337
	} else if (IS_GEN7(dev) && port == PORT_A) {
K
Keith Packard 已提交
2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_600:
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
	} else {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
2359 2360 2361
	}
}

2362 2363 2364 2365 2366
static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2367 2368
	struct intel_crtc *intel_crtc =
		to_intel_crtc(dport->base.base.crtc);
2369 2370 2371
	unsigned long demph_reg_value, preemph_reg_value,
		uniqtranscale_reg_value;
	uint8_t train_set = intel_dp->train_set[0];
2372
	enum dpio_channel port = vlv_dport_to_channel(dport);
2373
	int pipe = intel_crtc->pipe;
2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447

	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
	case DP_TRAIN_PRE_EMPHASIS_0:
		preemph_reg_value = 0x0004000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x552AB83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5548B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_800:
			demph_reg_value = 0x2B245555;
			uniqtranscale_reg_value = 0x5560B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_1200:
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x5598DA3A;
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_3_5:
		preemph_reg_value = 0x0002000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5552B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			demph_reg_value = 0x2B404848;
			uniqtranscale_reg_value = 0x5580B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_800:
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_6:
		preemph_reg_value = 0x0000000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x2B305555;
			uniqtranscale_reg_value = 0x5570B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			demph_reg_value = 0x2B2B4040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_9_5:
		preemph_reg_value = 0x0006000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x1B405555;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	default:
		return 0;
	}

2448
	mutex_lock(&dev_priv->dpio_lock);
2449 2450 2451
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2452
			 uniqtranscale_reg_value);
2453 2454 2455 2456
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2457
	mutex_unlock(&dev_priv->dpio_lock);
2458 2459 2460 2461

	return 0;
}

2462 2463 2464 2465 2466 2467
static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
	struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
2468
	u32 deemph_reg_value, margin_reg_value, val;
2469 2470
	uint8_t train_set = intel_dp->train_set[0];
	enum dpio_channel ch = vlv_dport_to_channel(dport);
2471 2472
	enum pipe pipe = intel_crtc->pipe;
	int i;
2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546

	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
	case DP_TRAIN_PRE_EMPHASIS_0:
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			deemph_reg_value = 128;
			margin_reg_value = 52;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			deemph_reg_value = 128;
			margin_reg_value = 77;
			break;
		case DP_TRAIN_VOLTAGE_SWING_800:
			deemph_reg_value = 128;
			margin_reg_value = 102;
			break;
		case DP_TRAIN_VOLTAGE_SWING_1200:
			deemph_reg_value = 128;
			margin_reg_value = 154;
			/* FIXME extra to set for 1200 */
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_3_5:
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			deemph_reg_value = 85;
			margin_reg_value = 78;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			deemph_reg_value = 85;
			margin_reg_value = 116;
			break;
		case DP_TRAIN_VOLTAGE_SWING_800:
			deemph_reg_value = 85;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_6:
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			deemph_reg_value = 64;
			margin_reg_value = 104;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			deemph_reg_value = 64;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_9_5:
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			deemph_reg_value = 43;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
	default:
		return 0;
	}

	mutex_lock(&dev_priv->dpio_lock);

	/* Clear calc init */
2547 2548 2549 2550 2551 2552 2553
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2554 2555

	/* Program swing deemph */
2556 2557 2558 2559 2560 2561
	for (i = 0; i < 4; i++) {
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
		val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
	}
2562 2563

	/* Program swing margin */
2564 2565 2566 2567 2568 2569
	for (i = 0; i < 4; i++) {
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
		val &= ~DPIO_SWING_MARGIN_MASK;
		val |= margin_reg_value << DPIO_SWING_MARGIN_SHIFT;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
	}
2570 2571

	/* Disable unique transition scale */
2572 2573 2574 2575 2576
	for (i = 0; i < 4; i++) {
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
		val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
	}
2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588

	if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
			== DP_TRAIN_PRE_EMPHASIS_0) &&
		((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
			== DP_TRAIN_VOLTAGE_SWING_1200)) {

		/*
		 * The document said it needs to set bit 27 for ch0 and bit 26
		 * for ch1. Might be a typo in the doc.
		 * For now, for this unique transition scale selection, set bit
		 * 27 for ch0 and ch1.
		 */
2589 2590 2591 2592 2593
		for (i = 0; i < 4; i++) {
			val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
			val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
			vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
		}
2594

2595 2596 2597 2598 2599 2600
		for (i = 0; i < 4; i++) {
			val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
			val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
			val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
			vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
		}
2601 2602 2603
	}

	/* Start swing calculation */
2604 2605 2606 2607 2608 2609 2610
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621

	/* LRC Bypass */
	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
	val |= DPIO_LRC_BYPASS;
	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);

	mutex_unlock(&dev_priv->dpio_lock);

	return 0;
}

2622
static void
J
Jani Nikula 已提交
2623 2624
intel_get_adjust_train(struct intel_dp *intel_dp,
		       const uint8_t link_status[DP_LINK_STATUS_SIZE])
2625 2626 2627 2628
{
	uint8_t v = 0;
	uint8_t p = 0;
	int lane;
K
Keith Packard 已提交
2629 2630
	uint8_t voltage_max;
	uint8_t preemph_max;
2631

2632
	for (lane = 0; lane < intel_dp->lane_count; lane++) {
2633 2634
		uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
		uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2635 2636 2637 2638 2639 2640 2641

		if (this_v > v)
			v = this_v;
		if (this_p > p)
			p = this_p;
	}

K
Keith Packard 已提交
2642
	voltage_max = intel_dp_voltage_max(intel_dp);
2643 2644
	if (v >= voltage_max)
		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2645

K
Keith Packard 已提交
2646 2647 2648
	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
	if (p >= preemph_max)
		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2649 2650

	for (lane = 0; lane < 4; lane++)
2651
		intel_dp->train_set[lane] = v | p;
2652 2653 2654
}

static uint32_t
2655
intel_gen4_signal_levels(uint8_t train_set)
2656
{
2657
	uint32_t	signal_levels = 0;
2658

2659
	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673
	case DP_TRAIN_VOLTAGE_SWING_400:
	default:
		signal_levels |= DP_VOLTAGE_0_4;
		break;
	case DP_TRAIN_VOLTAGE_SWING_600:
		signal_levels |= DP_VOLTAGE_0_6;
		break;
	case DP_TRAIN_VOLTAGE_SWING_800:
		signal_levels |= DP_VOLTAGE_0_8;
		break;
	case DP_TRAIN_VOLTAGE_SWING_1200:
		signal_levels |= DP_VOLTAGE_1_2;
		break;
	}
2674
	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691
	case DP_TRAIN_PRE_EMPHASIS_0:
	default:
		signal_levels |= DP_PRE_EMPHASIS_0;
		break;
	case DP_TRAIN_PRE_EMPHASIS_3_5:
		signal_levels |= DP_PRE_EMPHASIS_3_5;
		break;
	case DP_TRAIN_PRE_EMPHASIS_6:
		signal_levels |= DP_PRE_EMPHASIS_6;
		break;
	case DP_TRAIN_PRE_EMPHASIS_9_5:
		signal_levels |= DP_PRE_EMPHASIS_9_5;
		break;
	}
	return signal_levels;
}

2692 2693 2694 2695
/* Gen6's DP voltage swing and pre-emphasis control */
static uint32_t
intel_gen6_edp_signal_levels(uint8_t train_set)
{
2696 2697 2698
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
2699
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2700 2701 2702 2703
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2704
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2705 2706
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
		return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2707
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2708 2709
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2710
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2711 2712
	case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2713
	default:
2714 2715 2716
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2717 2718 2719
	}
}

K
Keith Packard 已提交
2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748 2749 2750
/* Gen7's DP voltage swing and pre-emphasis control */
static uint32_t
intel_gen7_edp_signal_levels(uint8_t train_set)
{
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_400MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
		return EDP_LINK_TRAIN_400MV_6DB_IVB;

	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_600MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_600MV_3_5DB_IVB;

	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_800MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_800MV_3_5DB_IVB;

	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_500MV_0DB_IVB;
	}
}

2751 2752
/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
static uint32_t
2753
intel_hsw_signal_levels(uint8_t train_set)
2754
{
2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_400MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_400MV_3_5DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
		return DDI_BUF_EMP_400MV_6DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
		return DDI_BUF_EMP_400MV_9_5DB_HSW;
2766

2767 2768 2769 2770 2771 2772
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_600MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_600MV_3_5DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
		return DDI_BUF_EMP_600MV_6DB_HSW;
2773

2774 2775 2776 2777 2778 2779 2780 2781
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_800MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_800MV_3_5DB_HSW;
	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return DDI_BUF_EMP_400MV_0DB_HSW;
2782 2783 2784
	}
}

2785 2786 2787 2788 2789
/* Properly updates "DP" with the correct signal levels. */
static void
intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2790
	enum port port = intel_dig_port->port;
2791 2792 2793 2794
	struct drm_device *dev = intel_dig_port->base.base.dev;
	uint32_t signal_levels, mask;
	uint8_t train_set = intel_dp->train_set[0];

2795
	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2796 2797
		signal_levels = intel_hsw_signal_levels(train_set);
		mask = DDI_BUF_EMP_MASK;
2798 2799 2800
	} else if (IS_CHERRYVIEW(dev)) {
		signal_levels = intel_chv_signal_levels(intel_dp);
		mask = 0;
2801 2802 2803
	} else if (IS_VALLEYVIEW(dev)) {
		signal_levels = intel_vlv_signal_levels(intel_dp);
		mask = 0;
2804
	} else if (IS_GEN7(dev) && port == PORT_A) {
2805 2806
		signal_levels = intel_gen7_edp_signal_levels(train_set);
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2807
	} else if (IS_GEN6(dev) && port == PORT_A) {
2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819
		signal_levels = intel_gen6_edp_signal_levels(train_set);
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
	} else {
		signal_levels = intel_gen4_signal_levels(train_set);
		mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
	}

	DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);

	*DP = (*DP & ~mask) | signal_levels;
}

2820
static bool
C
Chris Wilson 已提交
2821
intel_dp_set_link_train(struct intel_dp *intel_dp,
2822
			uint32_t *DP,
2823
			uint8_t dp_train_pat)
2824
{
2825 2826
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
2827
	struct drm_i915_private *dev_priv = dev->dev_private;
2828
	enum port port = intel_dig_port->port;
2829 2830
	uint8_t buf[sizeof(intel_dp->train_set) + 1];
	int ret, len;
2831

2832
	if (HAS_DDI(dev)) {
2833
		uint32_t temp = I915_READ(DP_TP_CTL(port));
2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855

		if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
			temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
		else
			temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;

		temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;

			break;
		case DP_TRAINING_PATTERN_1:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
			break;
		case DP_TRAINING_PATTERN_2:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
			break;
		case DP_TRAINING_PATTERN_3:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
			break;
		}
2856
		I915_WRITE(DP_TP_CTL(port), temp);
2857

2858
	} else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2859
		*DP &= ~DP_LINK_TRAIN_MASK_CPT;
2860 2861 2862

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
2863
			*DP |= DP_LINK_TRAIN_OFF_CPT;
2864 2865
			break;
		case DP_TRAINING_PATTERN_1:
2866
			*DP |= DP_LINK_TRAIN_PAT_1_CPT;
2867 2868
			break;
		case DP_TRAINING_PATTERN_2:
2869
			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
2870 2871 2872
			break;
		case DP_TRAINING_PATTERN_3:
			DRM_ERROR("DP training pattern 3 not supported\n");
2873
			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
2874 2875 2876 2877
			break;
		}

	} else {
2878
		*DP &= ~DP_LINK_TRAIN_MASK;
2879 2880 2881

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
2882
			*DP |= DP_LINK_TRAIN_OFF;
2883 2884
			break;
		case DP_TRAINING_PATTERN_1:
2885
			*DP |= DP_LINK_TRAIN_PAT_1;
2886 2887
			break;
		case DP_TRAINING_PATTERN_2:
2888
			*DP |= DP_LINK_TRAIN_PAT_2;
2889 2890 2891
			break;
		case DP_TRAINING_PATTERN_3:
			DRM_ERROR("DP training pattern 3 not supported\n");
2892
			*DP |= DP_LINK_TRAIN_PAT_2;
2893 2894 2895 2896
			break;
		}
	}

2897
	I915_WRITE(intel_dp->output_reg, *DP);
C
Chris Wilson 已提交
2898
	POSTING_READ(intel_dp->output_reg);
2899

2900 2901
	buf[0] = dp_train_pat;
	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2902
	    DP_TRAINING_PATTERN_DISABLE) {
2903 2904 2905 2906 2907 2908
		/* don't write DP_TRAINING_LANEx_SET on disable */
		len = 1;
	} else {
		/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
		memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
		len = intel_dp->lane_count + 1;
2909
	}
2910

2911 2912
	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
				buf, len);
2913 2914

	return ret == len;
2915 2916
}

2917 2918 2919 2920
static bool
intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
			uint8_t dp_train_pat)
{
2921
	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2922 2923 2924 2925 2926 2927
	intel_dp_set_signal_levels(intel_dp, DP);
	return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
}

static bool
intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
J
Jani Nikula 已提交
2928
			   const uint8_t link_status[DP_LINK_STATUS_SIZE])
2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	intel_get_adjust_train(intel_dp, link_status);
	intel_dp_set_signal_levels(intel_dp, DP);

	I915_WRITE(intel_dp->output_reg, *DP);
	POSTING_READ(intel_dp->output_reg);

2941 2942
	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
				intel_dp->train_set, intel_dp->lane_count);
2943 2944 2945 2946

	return ret == intel_dp->lane_count;
}

2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977
static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;
	uint32_t val;

	if (!HAS_DDI(dev))
		return;

	val = I915_READ(DP_TP_CTL(port));
	val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
	val |= DP_TP_CTL_LINK_TRAIN_IDLE;
	I915_WRITE(DP_TP_CTL(port), val);

	/*
	 * On PORT_A we can have only eDP in SST mode. There the only reason
	 * we need to set idle transmission mode is to work around a HW issue
	 * where we enable the pipe while not in idle link-training mode.
	 * In this case there is requirement to wait for a minimum number of
	 * idle patterns to be sent.
	 */
	if (port == PORT_A)
		return;

	if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
		     1))
		DRM_ERROR("Timed out waiting for DP idle patterns\n");
}

2978
/* Enable corresponding port and start training pattern 1 */
2979
void
2980
intel_dp_start_link_train(struct intel_dp *intel_dp)
2981
{
2982
	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2983
	struct drm_device *dev = encoder->dev;
2984 2985
	int i;
	uint8_t voltage;
2986
	int voltage_tries, loop_tries;
C
Chris Wilson 已提交
2987
	uint32_t DP = intel_dp->DP;
2988
	uint8_t link_config[2];
2989

P
Paulo Zanoni 已提交
2990
	if (HAS_DDI(dev))
2991 2992
		intel_ddi_prepare_link_retrain(encoder);

2993
	/* Write the link configuration data */
2994 2995 2996 2997
	link_config[0] = intel_dp->link_bw;
	link_config[1] = intel_dp->lane_count;
	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2998
	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
2999 3000 3001

	link_config[0] = 0;
	link_config[1] = DP_SET_ANSI_8B10B;
3002
	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3003 3004

	DP |= DP_PORT_EN;
K
Keith Packard 已提交
3005

3006 3007 3008 3009 3010 3011 3012 3013
	/* clock recovery */
	if (!intel_dp_reset_link_train(intel_dp, &DP,
				       DP_TRAINING_PATTERN_1 |
				       DP_LINK_SCRAMBLING_DISABLE)) {
		DRM_ERROR("failed to enable link training\n");
		return;
	}

3014
	voltage = 0xff;
3015 3016
	voltage_tries = 0;
	loop_tries = 0;
3017
	for (;;) {
3018
		uint8_t link_status[DP_LINK_STATUS_SIZE];
3019

3020
		drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3021 3022
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
3023
			break;
3024
		}
3025

3026
		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3027
			DRM_DEBUG_KMS("clock recovery OK\n");
3028 3029 3030 3031 3032 3033
			break;
		}

		/* Check to see if we've tried the max voltage */
		for (i = 0; i < intel_dp->lane_count; i++)
			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3034
				break;
3035
		if (i == intel_dp->lane_count) {
3036 3037
			++loop_tries;
			if (loop_tries == 5) {
3038
				DRM_ERROR("too many full retries, give up\n");
3039 3040
				break;
			}
3041 3042 3043
			intel_dp_reset_link_train(intel_dp, &DP,
						  DP_TRAINING_PATTERN_1 |
						  DP_LINK_SCRAMBLING_DISABLE);
3044 3045 3046
			voltage_tries = 0;
			continue;
		}
3047

3048
		/* Check to see if we've tried the same voltage 5 times */
3049
		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3050
			++voltage_tries;
3051
			if (voltage_tries == 5) {
3052
				DRM_ERROR("too many voltage retries, give up\n");
3053 3054 3055 3056 3057
				break;
			}
		} else
			voltage_tries = 0;
		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3058

3059 3060 3061 3062 3063
		/* Update training set as requested by target */
		if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
			DRM_ERROR("failed to update link training\n");
			break;
		}
3064 3065
	}

3066 3067 3068
	intel_dp->DP = DP;
}

3069
void
3070 3071 3072
intel_dp_complete_link_train(struct intel_dp *intel_dp)
{
	bool channel_eq = false;
3073
	int tries, cr_tries;
3074
	uint32_t DP = intel_dp->DP;
3075 3076 3077 3078 3079
	uint32_t training_pattern = DP_TRAINING_PATTERN_2;

	/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
	if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
		training_pattern = DP_TRAINING_PATTERN_3;
3080

3081
	/* channel equalization */
3082
	if (!intel_dp_set_link_train(intel_dp, &DP,
3083
				     training_pattern |
3084 3085 3086 3087 3088
				     DP_LINK_SCRAMBLING_DISABLE)) {
		DRM_ERROR("failed to start channel equalization\n");
		return;
	}

3089
	tries = 0;
3090
	cr_tries = 0;
3091 3092
	channel_eq = false;
	for (;;) {
3093
		uint8_t link_status[DP_LINK_STATUS_SIZE];
3094

3095 3096 3097 3098 3099
		if (cr_tries > 5) {
			DRM_ERROR("failed to train DP, aborting\n");
			break;
		}

3100
		drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3101 3102
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
3103
			break;
3104
		}
3105

3106
		/* Make sure clock is still ok */
3107
		if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3108
			intel_dp_start_link_train(intel_dp);
3109
			intel_dp_set_link_train(intel_dp, &DP,
3110
						training_pattern |
3111
						DP_LINK_SCRAMBLING_DISABLE);
3112 3113 3114 3115
			cr_tries++;
			continue;
		}

3116
		if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3117 3118 3119
			channel_eq = true;
			break;
		}
3120

3121 3122 3123 3124
		/* Try 5 times, then try clock recovery if that fails */
		if (tries > 5) {
			intel_dp_link_down(intel_dp);
			intel_dp_start_link_train(intel_dp);
3125
			intel_dp_set_link_train(intel_dp, &DP,
3126
						training_pattern |
3127
						DP_LINK_SCRAMBLING_DISABLE);
3128 3129 3130 3131
			tries = 0;
			cr_tries++;
			continue;
		}
3132

3133 3134 3135 3136 3137
		/* Update training set as requested by target */
		if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
			DRM_ERROR("failed to update link training\n");
			break;
		}
3138
		++tries;
3139
	}
3140

3141 3142 3143 3144
	intel_dp_set_idle_link_train(intel_dp);

	intel_dp->DP = DP;

3145
	if (channel_eq)
M
Masanari Iida 已提交
3146
		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3147

3148 3149 3150 3151
}

void intel_dp_stop_link_train(struct intel_dp *intel_dp)
{
3152
	intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3153
				DP_TRAINING_PATTERN_DISABLE);
3154 3155 3156
}

static void
C
Chris Wilson 已提交
3157
intel_dp_link_down(struct intel_dp *intel_dp)
3158
{
3159
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3160
	enum port port = intel_dig_port->port;
3161
	struct drm_device *dev = intel_dig_port->base.base.dev;
3162
	struct drm_i915_private *dev_priv = dev->dev_private;
3163 3164
	struct intel_crtc *intel_crtc =
		to_intel_crtc(intel_dig_port->base.base.crtc);
C
Chris Wilson 已提交
3165
	uint32_t DP = intel_dp->DP;
3166

3167
	if (WARN_ON(HAS_DDI(dev)))
3168 3169
		return;

3170
	if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3171 3172
		return;

3173
	DRM_DEBUG_KMS("\n");
3174

3175
	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3176
		DP &= ~DP_LINK_TRAIN_MASK_CPT;
C
Chris Wilson 已提交
3177
		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3178 3179
	} else {
		DP &= ~DP_LINK_TRAIN_MASK;
C
Chris Wilson 已提交
3180
		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3181
	}
3182
	POSTING_READ(intel_dp->output_reg);
3183

3184
	if (HAS_PCH_IBX(dev) &&
3185
	    I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3186
		struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
3187

3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201
		/* Hardware workaround: leaving our transcoder select
		 * set to transcoder B while it's off will prevent the
		 * corresponding HDMI output on transcoder A.
		 *
		 * Combine this with another hardware workaround:
		 * transcoder select bit can only be cleared while the
		 * port is enabled.
		 */
		DP &= ~DP_PIPEB_SELECT;
		I915_WRITE(intel_dp->output_reg, DP);

		/* Changes to enable or select take place the vblank
		 * after being written.
		 */
3202 3203 3204 3205
		if (WARN_ON(crtc == NULL)) {
			/* We should never try to disable a port without a crtc
			 * attached. For paranoia keep the code around for a
			 * bit. */
3206 3207 3208
			POSTING_READ(intel_dp->output_reg);
			msleep(50);
		} else
3209
			intel_wait_for_vblank(dev, intel_crtc->pipe);
3210 3211
	}

3212
	DP &= ~DP_AUDIO_OUTPUT_ENABLE;
C
Chris Wilson 已提交
3213 3214
	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);
3215
	msleep(intel_dp->panel_power_down_delay);
3216 3217
}

3218 3219
static bool
intel_dp_get_dpcd(struct intel_dp *intel_dp)
3220
{
R
Rodrigo Vivi 已提交
3221 3222 3223 3224
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

3225 3226
	char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];

3227 3228
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
				    sizeof(intel_dp->dpcd)) < 0)
3229
		return false; /* aux transfer failed */
3230

3231 3232 3233 3234
	hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
			   32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
	DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);

3235 3236 3237
	if (intel_dp->dpcd[DP_DPCD_REV] == 0)
		return false; /* DPCD not present */

3238 3239
	/* Check if the panel supports PSR */
	memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3240
	if (is_edp(intel_dp)) {
3241 3242 3243
		intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
					intel_dp->psr_dpcd,
					sizeof(intel_dp->psr_dpcd));
R
Rodrigo Vivi 已提交
3244 3245
		if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
			dev_priv->psr.sink_support = true;
3246
			DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
R
Rodrigo Vivi 已提交
3247
		}
3248 3249
	}

3250 3251 3252 3253 3254 3255 3256 3257
	/* Training Pattern 3 support */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
	    intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
		intel_dp->use_tps3 = true;
		DRM_DEBUG_KMS("Displayport TPS3 supported");
	} else
		intel_dp->use_tps3 = false;

3258 3259 3260 3261 3262 3263 3264
	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
	      DP_DWN_STRM_PORT_PRESENT))
		return true; /* native DP sink */

	if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
		return true; /* no per-port downstream info */

3265 3266 3267
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
				    intel_dp->downstream_ports,
				    DP_MAX_DOWNSTREAM_PORTS) < 0)
3268 3269 3270
		return false; /* downstream port status fetch failed */

	return true;
3271 3272
}

3273 3274 3275 3276 3277 3278 3279 3280
static void
intel_dp_probe_oui(struct intel_dp *intel_dp)
{
	u8 buf[3];

	if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
		return;

3281
	intel_edp_panel_vdd_on(intel_dp);
D
Daniel Vetter 已提交
3282

3283
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3284 3285 3286
		DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);

3287
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3288 3289
		DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);
D
Daniel Vetter 已提交
3290

3291
	edp_panel_vdd_off(intel_dp, false);
3292 3293
}

3294 3295 3296 3297 3298 3299 3300 3301
int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(intel_dig_port->base.base.crtc);
	u8 buf[1];

3302
	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
3303 3304 3305 3306 3307
		return -EAGAIN;

	if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
		return -ENOTTY;

3308 3309
	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
			       DP_TEST_SINK_START) < 0)
3310 3311 3312 3313 3314 3315
		return -EAGAIN;

	/* Wait 2 vblanks to be sure we will have the correct CRC value */
	intel_wait_for_vblank(dev, intel_crtc->pipe);
	intel_wait_for_vblank(dev, intel_crtc->pipe);

3316
	if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
3317 3318
		return -EAGAIN;

3319
	drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
3320 3321 3322
	return 0;
}

3323 3324 3325
static bool
intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
3326 3327 3328
	return intel_dp_dpcd_read_wake(&intel_dp->aux,
				       DP_DEVICE_SERVICE_IRQ_VECTOR,
				       sink_irq_vector, 1) == 1;
3329 3330 3331 3332 3333 3334
}

static void
intel_dp_handle_test_request(struct intel_dp *intel_dp)
{
	/* NAK by default */
3335
	drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
3336 3337
}

3338 3339 3340 3341 3342 3343 3344 3345 3346
/*
 * According to DP spec
 * 5.1.2:
 *  1. Read DPCD
 *  2. Configure link according to Receiver Capabilities
 *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
 *  4. Check link status on receipt of hot-plug interrupt
 */

P
Paulo Zanoni 已提交
3347
void
C
Chris Wilson 已提交
3348
intel_dp_check_link_status(struct intel_dp *intel_dp)
3349
{
3350
	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
3351
	u8 sink_irq_vector;
3352
	u8 link_status[DP_LINK_STATUS_SIZE];
3353

3354
	/* FIXME: This access isn't protected by any locks. */
3355
	if (!intel_encoder->connectors_active)
3356
		return;
3357

3358
	if (WARN_ON(!intel_encoder->base.crtc))
3359 3360
		return;

3361
	/* Try to read receiver status if the link appears to be up */
3362
	if (!intel_dp_get_link_status(intel_dp, link_status)) {
3363 3364 3365
		return;
	}

3366
	/* Now read the DPCD to see if it's actually running */
3367
	if (!intel_dp_get_dpcd(intel_dp)) {
3368 3369 3370
		return;
	}

3371 3372 3373 3374
	/* Try to read the source of the interrupt */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
		/* Clear interrupt source */
3375 3376 3377
		drm_dp_dpcd_writeb(&intel_dp->aux,
				   DP_DEVICE_SERVICE_IRQ_VECTOR,
				   sink_irq_vector);
3378 3379 3380 3381 3382 3383 3384

		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
			intel_dp_handle_test_request(intel_dp);
		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
	}

3385
	if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3386
		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
3387
			      intel_encoder->base.name);
3388 3389
		intel_dp_start_link_train(intel_dp);
		intel_dp_complete_link_train(intel_dp);
3390
		intel_dp_stop_link_train(intel_dp);
3391
	}
3392 3393
}

3394
/* XXX this is probably wrong for multiple downstream ports */
3395
static enum drm_connector_status
3396
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
3397
{
3398 3399 3400 3401 3402 3403 3404 3405
	uint8_t *dpcd = intel_dp->dpcd;
	uint8_t type;

	if (!intel_dp_get_dpcd(intel_dp))
		return connector_status_disconnected;

	/* if there's no downstream port, we're done */
	if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3406
		return connector_status_connected;
3407 3408

	/* If we're HPD-aware, SINK_COUNT changes dynamically */
3409 3410
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3411
		uint8_t reg;
3412 3413 3414

		if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
					    &reg, 1) < 0)
3415
			return connector_status_unknown;
3416

3417 3418
		return DP_GET_SINK_COUNT(reg) ? connector_status_connected
					      : connector_status_disconnected;
3419 3420 3421
	}

	/* If no HPD, poke DDC gently */
3422
	if (drm_probe_ddc(&intel_dp->aux.ddc))
3423
		return connector_status_connected;
3424 3425

	/* Well we tried, say unknown for unreliable port types */
3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
		type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
		if (type == DP_DS_PORT_TYPE_VGA ||
		    type == DP_DS_PORT_TYPE_NON_EDID)
			return connector_status_unknown;
	} else {
		type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
			DP_DWN_STRM_PORT_TYPE_MASK;
		if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
		    type == DP_DWN_STRM_PORT_TYPE_OTHER)
			return connector_status_unknown;
	}
3438 3439 3440

	/* Anything else is out of spec, warn and ignore */
	DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3441
	return connector_status_disconnected;
3442 3443
}

3444
static enum drm_connector_status
Z
Zhenyu Wang 已提交
3445
ironlake_dp_detect(struct intel_dp *intel_dp)
3446
{
3447
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3448 3449
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3450 3451
	enum drm_connector_status status;

3452 3453
	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp)) {
3454
		status = intel_panel_detect(dev);
3455 3456 3457 3458
		if (status == connector_status_unknown)
			status = connector_status_connected;
		return status;
	}
3459

3460 3461 3462
	if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
		return connector_status_disconnected;

3463
	return intel_dp_detect_dpcd(intel_dp);
3464 3465
}

3466
static enum drm_connector_status
Z
Zhenyu Wang 已提交
3467
g4x_dp_detect(struct intel_dp *intel_dp)
3468
{
3469
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3470
	struct drm_i915_private *dev_priv = dev->dev_private;
3471
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3472
	uint32_t bit;
3473

3474 3475 3476 3477 3478 3479 3480 3481 3482 3483
	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp)) {
		enum drm_connector_status status;

		status = intel_panel_detect(dev);
		if (status == connector_status_unknown)
			status = connector_status_connected;
		return status;
	}

3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511
	if (IS_VALLEYVIEW(dev)) {
		switch (intel_dig_port->port) {
		case PORT_B:
			bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
			break;
		case PORT_C:
			bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
			break;
		case PORT_D:
			bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
			break;
		default:
			return connector_status_unknown;
		}
	} else {
		switch (intel_dig_port->port) {
		case PORT_B:
			bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
			break;
		case PORT_C:
			bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
			break;
		case PORT_D:
			bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
			break;
		default:
			return connector_status_unknown;
		}
3512 3513
	}

3514
	if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3515 3516
		return connector_status_disconnected;

3517
	return intel_dp_detect_dpcd(intel_dp);
Z
Zhenyu Wang 已提交
3518 3519
}

3520 3521 3522
static struct edid *
intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
{
3523
	struct intel_connector *intel_connector = to_intel_connector(connector);
3524

3525 3526 3527 3528
	/* use cached edid if we have one */
	if (intel_connector->edid) {
		/* invalid edid */
		if (IS_ERR(intel_connector->edid))
3529 3530
			return NULL;

J
Jani Nikula 已提交
3531
		return drm_edid_duplicate(intel_connector->edid);
3532
	}
3533

3534
	return drm_get_edid(connector, adapter);
3535 3536 3537 3538 3539
}

static int
intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
{
3540
	struct intel_connector *intel_connector = to_intel_connector(connector);
3541

3542 3543 3544 3545 3546 3547 3548 3549
	/* use cached edid if we have one */
	if (intel_connector->edid) {
		/* invalid edid */
		if (IS_ERR(intel_connector->edid))
			return 0;

		return intel_connector_update_modes(connector,
						    intel_connector->edid);
3550 3551
	}

3552
	return intel_ddc_get_modes(connector, adapter);
3553 3554
}

Z
Zhenyu Wang 已提交
3555 3556 3557 3558
static enum drm_connector_status
intel_dp_detect(struct drm_connector *connector, bool force)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
3559 3560
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
3561
	struct drm_device *dev = connector->dev;
3562
	struct drm_i915_private *dev_priv = dev->dev_private;
Z
Zhenyu Wang 已提交
3563
	enum drm_connector_status status;
3564
	enum intel_display_power_domain power_domain;
Z
Zhenyu Wang 已提交
3565 3566
	struct edid *edid = NULL;

3567 3568
	intel_runtime_pm_get(dev_priv);

3569 3570 3571
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);

3572
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3573
		      connector->base.id, connector->name);
3574

Z
Zhenyu Wang 已提交
3575 3576 3577 3578 3579 3580
	intel_dp->has_audio = false;

	if (HAS_PCH_SPLIT(dev))
		status = ironlake_dp_detect(intel_dp);
	else
		status = g4x_dp_detect(intel_dp);
3581

Z
Zhenyu Wang 已提交
3582
	if (status != connector_status_connected)
3583
		goto out;
Z
Zhenyu Wang 已提交
3584

3585 3586
	intel_dp_probe_oui(intel_dp);

3587 3588
	if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
		intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3589
	} else {
3590
		edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3591 3592 3593 3594
		if (edid) {
			intel_dp->has_audio = drm_detect_monitor_audio(edid);
			kfree(edid);
		}
Z
Zhenyu Wang 已提交
3595 3596
	}

3597 3598
	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3599 3600 3601
	status = connector_status_connected;

out:
3602 3603
	intel_display_power_put(dev_priv, power_domain);

3604
	intel_runtime_pm_put(dev_priv);
3605

3606
	return status;
3607 3608 3609 3610
}

static int intel_dp_get_modes(struct drm_connector *connector)
{
3611
	struct intel_dp *intel_dp = intel_attached_dp(connector);
3612 3613
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
3614
	struct intel_connector *intel_connector = to_intel_connector(connector);
3615
	struct drm_device *dev = connector->dev;
3616 3617
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum intel_display_power_domain power_domain;
3618
	int ret;
3619 3620 3621 3622

	/* We should parse the EDID data and find out if it has an audio sink
	 */

3623 3624 3625
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);

3626
	ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
3627
	intel_display_power_put(dev_priv, power_domain);
3628
	if (ret)
3629 3630
		return ret;

3631
	/* if eDP has no EDID, fall back to fixed mode */
3632
	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3633
		struct drm_display_mode *mode;
3634 3635
		mode = drm_mode_duplicate(dev,
					  intel_connector->panel.fixed_mode);
3636
		if (mode) {
3637 3638 3639 3640 3641
			drm_mode_probed_add(connector, mode);
			return 1;
		}
	}
	return 0;
3642 3643
}

3644 3645 3646 3647
static bool
intel_dp_detect_audio(struct drm_connector *connector)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
3648 3649 3650 3651 3652
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = connector->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum intel_display_power_domain power_domain;
3653 3654 3655
	struct edid *edid;
	bool has_audio = false;

3656 3657 3658
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);

3659
	edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3660 3661 3662 3663 3664
	if (edid) {
		has_audio = drm_detect_monitor_audio(edid);
		kfree(edid);
	}

3665 3666
	intel_display_power_put(dev_priv, power_domain);

3667 3668 3669
	return has_audio;
}

3670 3671 3672 3673 3674
static int
intel_dp_set_property(struct drm_connector *connector,
		      struct drm_property *property,
		      uint64_t val)
{
3675
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
3676
	struct intel_connector *intel_connector = to_intel_connector(connector);
3677 3678
	struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3679 3680
	int ret;

3681
	ret = drm_object_property_set_value(&connector->base, property, val);
3682 3683 3684
	if (ret)
		return ret;

3685
	if (property == dev_priv->force_audio_property) {
3686 3687 3688 3689
		int i = val;
		bool has_audio;

		if (i == intel_dp->force_audio)
3690 3691
			return 0;

3692
		intel_dp->force_audio = i;
3693

3694
		if (i == HDMI_AUDIO_AUTO)
3695 3696
			has_audio = intel_dp_detect_audio(connector);
		else
3697
			has_audio = (i == HDMI_AUDIO_ON);
3698 3699

		if (has_audio == intel_dp->has_audio)
3700 3701
			return 0;

3702
		intel_dp->has_audio = has_audio;
3703 3704 3705
		goto done;
	}

3706
	if (property == dev_priv->broadcast_rgb_property) {
3707 3708 3709
		bool old_auto = intel_dp->color_range_auto;
		uint32_t old_range = intel_dp->color_range;

3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724
		switch (val) {
		case INTEL_BROADCAST_RGB_AUTO:
			intel_dp->color_range_auto = true;
			break;
		case INTEL_BROADCAST_RGB_FULL:
			intel_dp->color_range_auto = false;
			intel_dp->color_range = 0;
			break;
		case INTEL_BROADCAST_RGB_LIMITED:
			intel_dp->color_range_auto = false;
			intel_dp->color_range = DP_COLOR_RANGE_16_235;
			break;
		default:
			return -EINVAL;
		}
3725 3726 3727 3728 3729

		if (old_auto == intel_dp->color_range_auto &&
		    old_range == intel_dp->color_range)
			return 0;

3730 3731 3732
		goto done;
	}

3733 3734 3735 3736 3737 3738 3739 3740 3741 3742 3743 3744 3745 3746 3747 3748
	if (is_edp(intel_dp) &&
	    property == connector->dev->mode_config.scaling_mode_property) {
		if (val == DRM_MODE_SCALE_NONE) {
			DRM_DEBUG_KMS("no scaling not supported\n");
			return -EINVAL;
		}

		if (intel_connector->panel.fitting_mode == val) {
			/* the eDP scaling property is not changed */
			return 0;
		}
		intel_connector->panel.fitting_mode = val;

		goto done;
	}

3749 3750 3751
	return -EINVAL;

done:
3752 3753
	if (intel_encoder->base.crtc)
		intel_crtc_restore_mode(intel_encoder->base.crtc);
3754 3755 3756 3757

	return 0;
}

3758
static void
3759
intel_dp_connector_destroy(struct drm_connector *connector)
3760
{
3761
	struct intel_connector *intel_connector = to_intel_connector(connector);
3762

3763 3764 3765
	if (!IS_ERR_OR_NULL(intel_connector->edid))
		kfree(intel_connector->edid);

3766 3767 3768
	/* Can't call is_edp() since the encoder may have been destroyed
	 * already. */
	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3769
		intel_panel_fini(&intel_connector->panel);
3770

3771
	drm_connector_cleanup(connector);
3772
	kfree(connector);
3773 3774
}

P
Paulo Zanoni 已提交
3775
void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3776
{
3777 3778
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_dp *intel_dp = &intel_dig_port->dp;
3779
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3780

3781
	drm_dp_aux_unregister(&intel_dp->aux);
3782
	drm_encoder_cleanup(encoder);
3783 3784
	if (is_edp(intel_dp)) {
		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3785
		drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
3786
		edp_panel_vdd_off_sync(intel_dp);
3787
		drm_modeset_unlock(&dev->mode_config.connection_mutex);
3788
	}
3789
	kfree(intel_dig_port);
3790 3791
}

3792
static const struct drm_connector_funcs intel_dp_connector_funcs = {
3793
	.dpms = intel_connector_dpms,
3794 3795
	.detect = intel_dp_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
3796
	.set_property = intel_dp_set_property,
3797
	.destroy = intel_dp_connector_destroy,
3798 3799 3800 3801 3802
};

static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
	.get_modes = intel_dp_get_modes,
	.mode_valid = intel_dp_mode_valid,
3803
	.best_encoder = intel_best_encoder,
3804 3805 3806
};

static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3807
	.destroy = intel_dp_encoder_destroy,
3808 3809
};

3810
static void
3811
intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3812
{
3813
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3814

3815
	intel_dp_check_link_status(intel_dp);
3816
}
3817

3818 3819 3820 3821 3822 3823 3824 3825 3826 3827 3828 3829 3830 3831 3832 3833
bool
intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
{
	struct intel_dp *intel_dp = &intel_dig_port->dp;

	if (long_hpd)
		return true;

	/*
	 * we'll check the link status via the normal hot plug path later -
	 * but for short hpds we should check it now
	 */
	intel_dp_check_link_status(intel_dp);
	return false;
}

3834 3835
/* Return which DP Port should be selected for Transcoder DP control */
int
3836
intel_trans_dp_port_sel(struct drm_crtc *crtc)
3837 3838
{
	struct drm_device *dev = crtc->dev;
3839 3840
	struct intel_encoder *intel_encoder;
	struct intel_dp *intel_dp;
3841

3842 3843
	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		intel_dp = enc_to_intel_dp(&intel_encoder->base);
3844

3845 3846
		if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
		    intel_encoder->type == INTEL_OUTPUT_EDP)
C
Chris Wilson 已提交
3847
			return intel_dp->output_reg;
3848
	}
C
Chris Wilson 已提交
3849

3850 3851 3852
	return -1;
}

3853
/* check the VBT to see whether the eDP is on DP-D port */
3854
bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3855 3856
{
	struct drm_i915_private *dev_priv = dev->dev_private;
3857
	union child_device_config *p_child;
3858
	int i;
3859 3860 3861 3862 3863
	static const short port_mapping[] = {
		[PORT_B] = PORT_IDPB,
		[PORT_C] = PORT_IDPC,
		[PORT_D] = PORT_IDPD,
	};
3864

3865 3866 3867
	if (port == PORT_A)
		return true;

3868
	if (!dev_priv->vbt.child_dev_num)
3869 3870
		return false;

3871 3872
	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
		p_child = dev_priv->vbt.child_dev + i;
3873

3874
		if (p_child->common.dvo_port == port_mapping[port] &&
3875 3876
		    (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
		    (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3877 3878 3879 3880 3881
			return true;
	}
	return false;
}

3882 3883 3884
static void
intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
{
3885 3886
	struct intel_connector *intel_connector = to_intel_connector(connector);

3887
	intel_attach_force_audio_property(connector);
3888
	intel_attach_broadcast_rgb_property(connector);
3889
	intel_dp->color_range_auto = true;
3890 3891 3892

	if (is_edp(intel_dp)) {
		drm_mode_create_scaling_mode_property(connector->dev);
3893 3894
		drm_object_attach_property(
			&connector->base,
3895
			connector->dev->mode_config.scaling_mode_property,
3896 3897
			DRM_MODE_SCALE_ASPECT);
		intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3898
	}
3899 3900
}

3901 3902 3903 3904 3905 3906 3907
static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
{
	intel_dp->last_power_cycle = jiffies;
	intel_dp->last_power_on = jiffies;
	intel_dp->last_backlight_off = jiffies;
}

3908 3909
static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3910 3911
				    struct intel_dp *intel_dp,
				    struct edp_power_seq *out)
3912 3913 3914 3915
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct edp_power_seq cur, vbt, spec, final;
	u32 pp_on, pp_off, pp_div, pp;
3916
	int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3917 3918

	if (HAS_PCH_SPLIT(dev)) {
3919
		pp_ctrl_reg = PCH_PP_CONTROL;
3920 3921 3922 3923
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
3924 3925 3926 3927 3928 3929
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3930
	}
3931 3932 3933

	/* Workaround: Need to write PP_CONTROL with the unlock key as
	 * the very first thing. */
3934
	pp = ironlake_get_pp_control(intel_dp);
3935
	I915_WRITE(pp_ctrl_reg, pp);
3936

3937 3938 3939
	pp_on = I915_READ(pp_on_reg);
	pp_off = I915_READ(pp_off_reg);
	pp_div = I915_READ(pp_div_reg);
3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955 3956 3957 3958 3959

	/* Pull timing values out of registers */
	cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
		PANEL_POWER_UP_DELAY_SHIFT;

	cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
		PANEL_LIGHT_ON_DELAY_SHIFT;

	cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
		PANEL_LIGHT_OFF_DELAY_SHIFT;

	cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
		PANEL_POWER_DOWN_DELAY_SHIFT;

	cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
		       PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;

	DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);

3960
	vbt = dev_priv->vbt.edp_pps;
3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996

	/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
	 * our hw here, which are all in 100usec. */
	spec.t1_t3 = 210 * 10;
	spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
	spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
	spec.t10 = 500 * 10;
	/* This one is special and actually in units of 100ms, but zero
	 * based in the hw (so we need to add 100 ms). But the sw vbt
	 * table multiplies it with 1000 to make it in units of 100usec,
	 * too. */
	spec.t11_t12 = (510 + 100) * 10;

	DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);

	/* Use the max of the register settings and vbt. If both are
	 * unset, fall back to the spec limits. */
#define assign_final(field)	final.field = (max(cur.field, vbt.field) == 0 ? \
				       spec.field : \
				       max(cur.field, vbt.field))
	assign_final(t1_t3);
	assign_final(t8);
	assign_final(t9);
	assign_final(t10);
	assign_final(t11_t12);
#undef assign_final

#define get_delay(field)	(DIV_ROUND_UP(final.field, 10))
	intel_dp->panel_power_up_delay = get_delay(t1_t3);
	intel_dp->backlight_on_delay = get_delay(t8);
	intel_dp->backlight_off_delay = get_delay(t9);
	intel_dp->panel_power_down_delay = get_delay(t10);
	intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
#undef get_delay

3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012 4013
	DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
		      intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
		      intel_dp->panel_power_cycle_delay);

	DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
		      intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);

	if (out)
		*out = final;
}

static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
					      struct intel_dp *intel_dp,
					      struct edp_power_seq *seq)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
4014 4015 4016 4017 4018 4019 4020 4021 4022
	u32 pp_on, pp_off, pp_div, port_sel = 0;
	int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
	int pp_on_reg, pp_off_reg, pp_div_reg;

	if (HAS_PCH_SPLIT(dev)) {
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
4023 4024 4025 4026 4027
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4028 4029
	}

4030 4031 4032 4033 4034 4035 4036 4037
	/*
	 * And finally store the new values in the power sequencer. The
	 * backlight delays are set to 1 because we do manual waits on them. For
	 * T8, even BSpec recommends doing it. For T9, if we don't do this,
	 * we'll end up waiting for the backlight off delay twice: once when we
	 * do the manual sleep, and once when we disable the panel and wait for
	 * the PP_STATUS bit to become zero.
	 */
4038
	pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4039 4040
		(1 << PANEL_LIGHT_ON_DELAY_SHIFT);
	pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4041
		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4042 4043
	/* Compute the divisor for the pp clock, simply match the Bspec
	 * formula. */
4044
	pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4045
	pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4046 4047 4048 4049
			<< PANEL_POWER_CYCLE_DELAY_SHIFT);

	/* Haswell doesn't have any port selection bits for the panel
	 * power sequencer any more. */
4050
	if (IS_VALLEYVIEW(dev)) {
4051 4052 4053 4054
		if (dp_to_dig_port(intel_dp)->port == PORT_B)
			port_sel = PANEL_PORT_SELECT_DPB_VLV;
		else
			port_sel = PANEL_PORT_SELECT_DPC_VLV;
4055 4056
	} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
		if (dp_to_dig_port(intel_dp)->port == PORT_A)
4057
			port_sel = PANEL_PORT_SELECT_DPA;
4058
		else
4059
			port_sel = PANEL_PORT_SELECT_DPD;
4060 4061
	}

4062 4063 4064 4065 4066
	pp_on |= port_sel;

	I915_WRITE(pp_on_reg, pp_on);
	I915_WRITE(pp_off_reg, pp_off);
	I915_WRITE(pp_div_reg, pp_div);
4067 4068

	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4069 4070 4071
		      I915_READ(pp_on_reg),
		      I915_READ(pp_off_reg),
		      I915_READ(pp_div_reg));
4072 4073
}

4074 4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114 4115 4116 4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131 4132 4133 4134 4135 4136 4137 4138 4139 4140 4141 4142 4143 4144 4145 4146 4147 4148 4149 4150 4151 4152 4153 4154 4155 4156 4157
void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *encoder;
	struct intel_dp *intel_dp = NULL;
	struct intel_crtc_config *config = NULL;
	struct intel_crtc *intel_crtc = NULL;
	struct intel_connector *intel_connector = dev_priv->drrs.connector;
	u32 reg, val;
	enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;

	if (refresh_rate <= 0) {
		DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
		return;
	}

	if (intel_connector == NULL) {
		DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
		return;
	}

	if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
		DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
		return;
	}

	encoder = intel_attached_encoder(&intel_connector->base);
	intel_dp = enc_to_intel_dp(&encoder->base);
	intel_crtc = encoder->new_crtc;

	if (!intel_crtc) {
		DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
		return;
	}

	config = &intel_crtc->config;

	if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
		DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
		return;
	}

	if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
		index = DRRS_LOW_RR;

	if (index == intel_dp->drrs_state.refresh_rate_type) {
		DRM_DEBUG_KMS(
			"DRRS requested for previously set RR...ignoring\n");
		return;
	}

	if (!intel_crtc->active) {
		DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
		return;
	}

	if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
		reg = PIPECONF(intel_crtc->config.cpu_transcoder);
		val = I915_READ(reg);
		if (index > DRRS_HIGH_RR) {
			val |= PIPECONF_EDP_RR_MODE_SWITCH;
			intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
		} else {
			val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
		}
		I915_WRITE(reg, val);
	}

	/*
	 * mutex taken to ensure that there is no race between differnt
	 * drrs calls trying to update refresh rate. This scenario may occur
	 * in future when idleness detection based DRRS in kernel and
	 * possible calls from user space to set differnt RR are made.
	 */

	mutex_lock(&intel_dp->drrs_state.mutex);

	intel_dp->drrs_state.refresh_rate_type = index;

	mutex_unlock(&intel_dp->drrs_state.mutex);

	DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
}

4158 4159 4160 4161 4162 4163 4164 4165 4166 4167 4168 4169 4170 4171 4172 4173 4174 4175 4176 4177 4178 4179 4180 4181 4182 4183 4184 4185 4186
static struct drm_display_mode *
intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
			struct intel_connector *intel_connector,
			struct drm_display_mode *fixed_mode)
{
	struct drm_connector *connector = &intel_connector->base;
	struct intel_dp *intel_dp = &intel_dig_port->dp;
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_display_mode *downclock_mode = NULL;

	if (INTEL_INFO(dev)->gen <= 6) {
		DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
		return NULL;
	}

	if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
		DRM_INFO("VBT doesn't support DRRS\n");
		return NULL;
	}

	downclock_mode = intel_find_panel_downclock
					(dev, fixed_mode, connector);

	if (!downclock_mode) {
		DRM_INFO("DRRS not supported\n");
		return NULL;
	}

4187 4188 4189 4190
	dev_priv->drrs.connector = intel_connector;

	mutex_init(&intel_dp->drrs_state.mutex);

4191 4192 4193 4194 4195 4196 4197
	intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;

	intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
	DRM_INFO("seamless DRRS supported for eDP panel.\n");
	return downclock_mode;
}

4198
static bool intel_edp_init_connector(struct intel_dp *intel_dp,
4199 4200
				     struct intel_connector *intel_connector,
				     struct edp_power_seq *power_seq)
4201 4202 4203
{
	struct drm_connector *connector = &intel_connector->base;
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4204 4205
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
4206 4207
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_display_mode *fixed_mode = NULL;
4208
	struct drm_display_mode *downclock_mode = NULL;
4209 4210 4211 4212
	bool has_dpcd;
	struct drm_display_mode *scan;
	struct edid *edid;

4213 4214
	intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;

4215 4216 4217
	if (!is_edp(intel_dp))
		return true;

4218 4219 4220 4221 4222 4223 4224 4225
	/* The VDD bit needs a power domain reference, so if the bit is already
	 * enabled when we boot, grab this reference. */
	if (edp_have_panel_vdd(intel_dp)) {
		enum intel_display_power_domain power_domain;
		power_domain = intel_display_port_power_domain(intel_encoder);
		intel_display_power_get(dev_priv, power_domain);
	}

4226
	/* Cache DPCD and EDID for edp. */
4227
	intel_edp_panel_vdd_on(intel_dp);
4228
	has_dpcd = intel_dp_get_dpcd(intel_dp);
4229
	edp_panel_vdd_off(intel_dp, false);
4230 4231 4232 4233 4234 4235 4236 4237 4238 4239 4240 4241 4242

	if (has_dpcd) {
		if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
			dev_priv->no_aux_handshake =
				intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
				DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
	} else {
		/* if this fails, presume the device is a ghost */
		DRM_INFO("failed to retrieve link info, disabling eDP\n");
		return false;
	}

	/* We now know it's not a ghost, init power sequence regs. */
4243
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
4244

4245
	mutex_lock(&dev->mode_config.mutex);
4246
	edid = drm_get_edid(connector, &intel_dp->aux.ddc);
4247 4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264
	if (edid) {
		if (drm_add_edid_modes(connector, edid)) {
			drm_mode_connector_update_edid_property(connector,
								edid);
			drm_edid_to_eld(connector, edid);
		} else {
			kfree(edid);
			edid = ERR_PTR(-EINVAL);
		}
	} else {
		edid = ERR_PTR(-ENOENT);
	}
	intel_connector->edid = edid;

	/* prefer fixed mode from EDID if available */
	list_for_each_entry(scan, &connector->probed_modes, head) {
		if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
			fixed_mode = drm_mode_duplicate(dev, scan);
4265 4266 4267
			downclock_mode = intel_dp_drrs_init(
						intel_dig_port,
						intel_connector, fixed_mode);
4268 4269 4270 4271 4272 4273 4274 4275 4276 4277 4278
			break;
		}
	}

	/* fallback to VBT if available for eDP */
	if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
		fixed_mode = drm_mode_duplicate(dev,
					dev_priv->vbt.lfp_lvds_vbt_mode);
		if (fixed_mode)
			fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
	}
4279
	mutex_unlock(&dev->mode_config.mutex);
4280

4281
	intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
4282 4283 4284 4285 4286
	intel_panel_setup_backlight(connector);

	return true;
}

4287
bool
4288 4289
intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
			struct intel_connector *intel_connector)
4290
{
4291 4292 4293 4294
	struct drm_connector *connector = &intel_connector->base;
	struct intel_dp *intel_dp = &intel_dig_port->dp;
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
4295
	struct drm_i915_private *dev_priv = dev->dev_private;
4296
	enum port port = intel_dig_port->port;
4297
	struct edp_power_seq power_seq = { 0 };
4298
	int type;
4299

4300 4301 4302 4303 4304 4305 4306 4307 4308 4309
	/* intel_dp vfuncs */
	if (IS_VALLEYVIEW(dev))
		intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
		intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
	else if (HAS_PCH_SPLIT(dev))
		intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
	else
		intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;

4310 4311
	intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;

4312 4313
	/* Preserve the current hw state. */
	intel_dp->DP = I915_READ(intel_dp->output_reg);
4314
	intel_dp->attached_connector = intel_connector;
4315

4316
	if (intel_dp_is_edp(dev, port))
4317
		type = DRM_MODE_CONNECTOR_eDP;
4318 4319
	else
		type = DRM_MODE_CONNECTOR_DisplayPort;
4320

4321 4322 4323 4324 4325 4326 4327 4328
	/*
	 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
	 * for DP the encoder type can be set by the caller to
	 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
	 */
	if (type == DRM_MODE_CONNECTOR_eDP)
		intel_encoder->type = INTEL_OUTPUT_EDP;

4329 4330 4331 4332
	DRM_DEBUG_KMS("Adding %s connector on port %c\n",
			type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
			port_name(port));

4333
	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
4334 4335 4336 4337 4338
	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);

	connector->interlace_allowed = true;
	connector->doublescan_allowed = 0;

4339
	INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
4340
			  edp_panel_vdd_work);
4341

4342
	intel_connector_attach_encoder(intel_connector, intel_encoder);
4343 4344
	drm_sysfs_connector_add(connector);

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4345
	if (HAS_DDI(dev))
4346 4347 4348
		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
	else
		intel_connector->get_hw_state = intel_connector_get_hw_state;
4349
	intel_connector->unregister = intel_dp_connector_unregister;
4350

4351
	/* Set up the hotplug pin. */
4352 4353
	switch (port) {
	case PORT_A:
4354
		intel_encoder->hpd_pin = HPD_PORT_A;
4355 4356
		break;
	case PORT_B:
4357
		intel_encoder->hpd_pin = HPD_PORT_B;
4358 4359
		break;
	case PORT_C:
4360
		intel_encoder->hpd_pin = HPD_PORT_C;
4361 4362
		break;
	case PORT_D:
4363
		intel_encoder->hpd_pin = HPD_PORT_D;
4364 4365
		break;
	default:
4366
		BUG();
4367 4368
	}

4369 4370
	if (is_edp(intel_dp)) {
		intel_dp_init_panel_power_timestamps(intel_dp);
4371
		intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
4372
	}
4373

4374
	intel_dp_aux_init(intel_dp, intel_connector);
4375

4376
	if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
4377
		drm_dp_aux_unregister(&intel_dp->aux);
4378 4379
		if (is_edp(intel_dp)) {
			cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4380
			drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4381
			edp_panel_vdd_off_sync(intel_dp);
4382
			drm_modeset_unlock(&dev->mode_config.connection_mutex);
4383
		}
4384 4385
		drm_sysfs_connector_remove(connector);
		drm_connector_cleanup(connector);
4386
		return false;
4387
	}
4388

4389 4390
	intel_dp_add_properties(intel_dp, connector);

4391 4392 4393 4394 4395 4396 4397 4398
	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
4399 4400

	return true;
4401
}
4402 4403 4404 4405

void
intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
{
4406
	struct drm_i915_private *dev_priv = dev->dev_private;
4407 4408 4409 4410 4411
	struct intel_digital_port *intel_dig_port;
	struct intel_encoder *intel_encoder;
	struct drm_encoder *encoder;
	struct intel_connector *intel_connector;

4412
	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
4413 4414 4415
	if (!intel_dig_port)
		return;

4416
	intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
4417 4418 4419 4420 4421 4422 4423 4424 4425 4426 4427
	if (!intel_connector) {
		kfree(intel_dig_port);
		return;
	}

	intel_encoder = &intel_dig_port->base;
	encoder = &intel_encoder->base;

	drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
			 DRM_MODE_ENCODER_TMDS);

4428
	intel_encoder->compute_config = intel_dp_compute_config;
P
Paulo Zanoni 已提交
4429 4430
	intel_encoder->disable = intel_disable_dp;
	intel_encoder->get_hw_state = intel_dp_get_hw_state;
4431
	intel_encoder->get_config = intel_dp_get_config;
4432
	if (IS_CHERRYVIEW(dev)) {
4433
		intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
4434 4435
		intel_encoder->pre_enable = chv_pre_enable_dp;
		intel_encoder->enable = vlv_enable_dp;
4436
		intel_encoder->post_disable = chv_post_disable_dp;
4437
	} else if (IS_VALLEYVIEW(dev)) {
4438
		intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
4439 4440
		intel_encoder->pre_enable = vlv_pre_enable_dp;
		intel_encoder->enable = vlv_enable_dp;
4441
		intel_encoder->post_disable = vlv_post_disable_dp;
4442
	} else {
4443 4444
		intel_encoder->pre_enable = g4x_pre_enable_dp;
		intel_encoder->enable = g4x_enable_dp;
4445
		intel_encoder->post_disable = g4x_post_disable_dp;
4446
	}
4447

4448
	intel_dig_port->port = port;
4449 4450
	intel_dig_port->dp.output_reg = output_reg;

P
Paulo Zanoni 已提交
4451
	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4452 4453 4454 4455 4456 4457 4458 4459
	if (IS_CHERRYVIEW(dev)) {
		if (port == PORT_D)
			intel_encoder->crtc_mask = 1 << 2;
		else
			intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
	} else {
		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
	}
4460
	intel_encoder->cloneable = 0;
4461 4462
	intel_encoder->hot_plug = intel_dp_hot_plug;

4463 4464 4465
	intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
	dev_priv->hpd_irq_port[port] = intel_dig_port;

4466 4467 4468
	if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
		drm_encoder_cleanup(encoder);
		kfree(intel_dig_port);
4469
		kfree(intel_connector);
4470
	}
4471
}