intel_dp.c 114.4 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/i2c.h>
29
#include <linux/slab.h>
30
#include <linux/export.h>
31 32 33 34
#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
35
#include "intel_drv.h"
36
#include <drm/i915_drm.h>
37 38 39 40
#include "i915_drv.h"

#define DP_LINK_CHECK_TIMEOUT	(10 * 1000)

41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59
struct dp_link_dpll {
	int link_bw;
	struct dpll dpll;
};

static const struct dp_link_dpll gen4_dpll[] = {
	{ DP_LINK_BW_1_62,
		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
	{ DP_LINK_BW_2_7,
		{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
};

static const struct dp_link_dpll pch_dpll[] = {
	{ DP_LINK_BW_1_62,
		{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
	{ DP_LINK_BW_2_7,
		{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
};

60 61
static const struct dp_link_dpll vlv_dpll[] = {
	{ DP_LINK_BW_1_62,
C
Chon Ming Lee 已提交
62
		{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
63 64 65 66
	{ DP_LINK_BW_2_7,
		{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
};

67 68 69 70 71 72 73 74 75
/**
 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 * @intel_dp: DP struct
 *
 * If a CPU or PCH DP output is attached to an eDP panel, this function
 * will return true, and false otherwise.
 */
static bool is_edp(struct intel_dp *intel_dp)
{
76 77 78
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
79 80
}

81
static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
82
{
83 84 85
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.base.dev;
86 87
}

88 89
static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
{
90
	return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
91 92
}

C
Chris Wilson 已提交
93
static void intel_dp_link_down(struct intel_dp *intel_dp);
94
static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
95
static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
96 97

static int
C
Chris Wilson 已提交
98
intel_dp_max_link_bw(struct intel_dp *intel_dp)
99
{
100
	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
101
	struct drm_device *dev = intel_dp->attached_connector->base.dev;
102 103 104 105 106

	switch (max_link_bw) {
	case DP_LINK_BW_1_62:
	case DP_LINK_BW_2_7:
		break;
107
	case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
108 109 110 111 112
		if ((IS_HASWELL(dev) || INTEL_INFO(dev)->gen >= 8) &&
		    intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
			max_link_bw = DP_LINK_BW_5_4;
		else
			max_link_bw = DP_LINK_BW_2_7;
113
		break;
114
	default:
115 116
		WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
		     max_link_bw);
117 118 119 120 121 122
		max_link_bw = DP_LINK_BW_1_62;
		break;
	}
	return max_link_bw;
}

123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139
/*
 * The units on the numbers in the next two are... bizarre.  Examples will
 * make it clearer; this one parallels an example in the eDP spec.
 *
 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 *
 *     270000 * 1 * 8 / 10 == 216000
 *
 * The actual data capacity of that configuration is 2.16Gbit/s, so the
 * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 * 119000.  At 18bpp that's 2142000 kilobits per second.
 *
 * Thus the strange-looking division by 10 in intel_dp_link_required, to
 * get the result in decakilobits instead of kilobits.
 */

140
static int
141
intel_dp_link_required(int pixel_clock, int bpp)
142
{
143
	return (pixel_clock * bpp + 9) / 10;
144 145
}

146 147 148 149 150 151
static int
intel_dp_max_data_rate(int max_link_clock, int max_lanes)
{
	return (max_link_clock * max_lanes * 8) / 10;
}

152
static enum drm_mode_status
153 154 155
intel_dp_mode_valid(struct drm_connector *connector,
		    struct drm_display_mode *mode)
{
156
	struct intel_dp *intel_dp = intel_attached_dp(connector);
157 158
	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
159 160
	int target_clock = mode->clock;
	int max_rate, mode_rate, max_lanes, max_link_clock;
161

162 163
	if (is_edp(intel_dp) && fixed_mode) {
		if (mode->hdisplay > fixed_mode->hdisplay)
164 165
			return MODE_PANEL;

166
		if (mode->vdisplay > fixed_mode->vdisplay)
167
			return MODE_PANEL;
168 169

		target_clock = fixed_mode->clock;
170 171
	}

172 173 174 175 176 177 178
	max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
	max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);

	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
	mode_rate = intel_dp_link_required(target_clock, 18);

	if (mode_rate > max_rate)
179
		return MODE_CLOCK_HIGH;
180 181 182 183

	if (mode->clock < 10000)
		return MODE_CLOCK_LOW;

184 185 186
	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		return MODE_H_ILLEGAL;

187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212
	return MODE_OK;
}

static uint32_t
pack_aux(uint8_t *src, int src_bytes)
{
	int	i;
	uint32_t v = 0;

	if (src_bytes > 4)
		src_bytes = 4;
	for (i = 0; i < src_bytes; i++)
		v |= ((uint32_t) src[i]) << ((3-i) * 8);
	return v;
}

static void
unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
{
	int i;
	if (dst_bytes > 4)
		dst_bytes = 4;
	for (i = 0; i < dst_bytes; i++)
		dst[i] = src >> ((3-i) * 8);
}

213 214 215 216 217 218 219
/* hrawclock is 1/4 the FSB frequency */
static int
intel_hrawclk(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t clkcfg;

220 221 222 223
	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
	if (IS_VALLEYVIEW(dev))
		return 200;

224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246
	clkcfg = I915_READ(CLKCFG);
	switch (clkcfg & CLKCFG_FSB_MASK) {
	case CLKCFG_FSB_400:
		return 100;
	case CLKCFG_FSB_533:
		return 133;
	case CLKCFG_FSB_667:
		return 166;
	case CLKCFG_FSB_800:
		return 200;
	case CLKCFG_FSB_1067:
		return 266;
	case CLKCFG_FSB_1333:
		return 333;
	/* these two are just a guess; one of them might be right */
	case CLKCFG_FSB_1600:
	case CLKCFG_FSB_1600_ALT:
		return 400;
	default:
		return 133;
	}
}

247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303
static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
				    struct intel_dp *intel_dp,
				    struct edp_power_seq *out);
static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
					      struct intel_dp *intel_dp,
					      struct edp_power_seq *out);

static enum pipe
vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;
	enum pipe pipe;

	/* modeset should have pipe */
	if (crtc)
		return to_intel_crtc(crtc)->pipe;

	/* init time, try to find a pipe with this port selected */
	for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
		u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
			PANEL_PORT_SELECT_MASK;
		if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
			return pipe;
		if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
			return pipe;
	}

	/* shrug */
	return PIPE_A;
}

static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

	if (HAS_PCH_SPLIT(dev))
		return PCH_PP_CONTROL;
	else
		return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
}

static u32 _pp_stat_reg(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

	if (HAS_PCH_SPLIT(dev))
		return PCH_PP_STATUS;
	else
		return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
}

304
static bool edp_have_panel_power(struct intel_dp *intel_dp)
305
{
306
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
307 308
	struct drm_i915_private *dev_priv = dev->dev_private;

309
	return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
310 311
}

312
static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
313
{
314
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
315 316
	struct drm_i915_private *dev_priv = dev->dev_private;

317 318
	return !dev_priv->pm.suspended &&
	       (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
319 320
}

321 322 323
static void
intel_dp_check_edp(struct intel_dp *intel_dp)
{
324
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
325
	struct drm_i915_private *dev_priv = dev->dev_private;
326

327 328
	if (!is_edp(intel_dp))
		return;
329

330
	if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
331 332
		WARN(1, "eDP powered off while attempting aux channel communication.\n");
		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
333 334
			      I915_READ(_pp_stat_reg(intel_dp)),
			      I915_READ(_pp_ctrl_reg(intel_dp)));
335 336 337
	}
}

338 339 340 341 342 343
static uint32_t
intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
344
	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
345 346 347
	uint32_t status;
	bool done;

348
#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
349
	if (has_aux_irq)
350
		done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
351
					  msecs_to_jiffies_timeout(10));
352 353 354 355 356 357 358 359 360 361
	else
		done = wait_for_atomic(C, 10) == 0;
	if (!done)
		DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
			  has_aux_irq);
#undef C

	return status;
}

362
static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
363
{
364 365
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
366

367 368 369
	/*
	 * The clock divider is based off the hrawclk, and would like to run at
	 * 2MHz.  So, take the hrawclk value and divide by 2 and use that
370
	 */
371 372 373 374 375 376 377 378 379 380 381 382 383
	return index ? 0 : intel_hrawclk(dev) / 2;
}

static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;

	if (index)
		return 0;

	if (intel_dig_port->port == PORT_A) {
		if (IS_GEN6(dev) || IS_GEN7(dev))
384
			return 200; /* SNB & IVB eDP input clock at 400Mhz */
385
		else
386
			return 225; /* eDP input clock at 450Mhz */
387 388 389 390 391 392 393 394 395 396 397 398 399 400 401
	} else {
		return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
	}
}

static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (intel_dig_port->port == PORT_A) {
		if (index)
			return 0;
		return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
402 403
	} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
		/* Workaround for non-ULT HSW */
404 405 406 407 408
		switch (index) {
		case 0: return 63;
		case 1: return 72;
		default: return 0;
		}
409
	} else  {
410
		return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
411
	}
412 413
}

414 415 416 417 418
static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	return index ? 0 : 100;
}

419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438
static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
				      bool has_aux_irq,
				      int send_bytes,
				      uint32_t aux_clock_divider)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	uint32_t precharge, timeout;

	if (IS_GEN6(dev))
		precharge = 3;
	else
		precharge = 5;

	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
		timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
	else
		timeout = DP_AUX_CH_CTL_TIME_OUT_400us;

	return DP_AUX_CH_CTL_SEND_BUSY |
439
	       DP_AUX_CH_CTL_DONE |
440
	       (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
441
	       DP_AUX_CH_CTL_TIME_OUT_ERROR |
442
	       timeout |
443
	       DP_AUX_CH_CTL_RECEIVE_ERROR |
444 445
	       (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
	       (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
446
	       (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
447 448
}

449 450 451 452 453 454 455 456 457 458
static int
intel_dp_aux_ch(struct intel_dp *intel_dp,
		uint8_t *send, int send_bytes,
		uint8_t *recv, int recv_size)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
	uint32_t ch_data = ch_ctl + 4;
459
	uint32_t aux_clock_divider;
460 461
	int i, ret, recv_bytes;
	uint32_t status;
462
	int try, clock = 0;
463
	bool has_aux_irq = HAS_AUX_IRQ(dev);
464 465 466
	bool vdd;

	vdd = _edp_panel_vdd_on(intel_dp);
467 468 469 470 471 472 473 474

	/* dp aux is extremely sensitive to irq latency, hence request the
	 * lowest possible wakeup latency and so prevent the cpu from going into
	 * deep sleep states.
	 */
	pm_qos_update_request(&dev_priv->pm_qos, 0);

	intel_dp_check_edp(intel_dp);
475

476 477
	intel_aux_display_runtime_get(dev_priv);

478 479
	/* Try to wait for any previous AUX channel activity */
	for (try = 0; try < 3; try++) {
480
		status = I915_READ_NOTRACE(ch_ctl);
481 482 483 484 485 486 487 488
		if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
			break;
		msleep(1);
	}

	if (try == 3) {
		WARN(1, "dp_aux_ch not started status 0x%08x\n",
		     I915_READ(ch_ctl));
489 490
		ret = -EBUSY;
		goto out;
491 492
	}

493 494 495 496 497 498
	/* Only 5 data registers! */
	if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
		ret = -E2BIG;
		goto out;
	}

499
	while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
500 501 502 503
		u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
							  has_aux_irq,
							  send_bytes,
							  aux_clock_divider);
504

505 506 507 508 509 510 511 512
		/* Must try at least 3 times according to DP spec */
		for (try = 0; try < 5; try++) {
			/* Load the send data into the aux channel data registers */
			for (i = 0; i < send_bytes; i += 4)
				I915_WRITE(ch_data + i,
					   pack_aux(send + i, send_bytes - i));

			/* Send the command and wait for it to complete */
513
			I915_WRITE(ch_ctl, send_ctl);
514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529

			status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);

			/* Clear done status and any errors */
			I915_WRITE(ch_ctl,
				   status |
				   DP_AUX_CH_CTL_DONE |
				   DP_AUX_CH_CTL_TIME_OUT_ERROR |
				   DP_AUX_CH_CTL_RECEIVE_ERROR);

			if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
				      DP_AUX_CH_CTL_RECEIVE_ERROR))
				continue;
			if (status & DP_AUX_CH_CTL_DONE)
				break;
		}
530
		if (status & DP_AUX_CH_CTL_DONE)
531 532 533 534
			break;
	}

	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
535
		DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
536 537
		ret = -EBUSY;
		goto out;
538 539 540 541 542
	}

	/* Check for timeout or receive error.
	 * Timeouts occur when the sink is not connected
	 */
543
	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
544
		DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
545 546
		ret = -EIO;
		goto out;
547
	}
548 549 550

	/* Timeouts occur when the device isn't connected, so they're
	 * "normal" -- don't fill the kernel log with these */
551
	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
552
		DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
553 554
		ret = -ETIMEDOUT;
		goto out;
555 556 557 558 559 560 561
	}

	/* Unload any bytes sent back from the other side */
	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
		      DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
	if (recv_bytes > recv_size)
		recv_bytes = recv_size;
562

563 564 565
	for (i = 0; i < recv_bytes; i += 4)
		unpack_aux(I915_READ(ch_data + i),
			   recv + i, recv_bytes - i);
566

567 568 569
	ret = recv_bytes;
out:
	pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
570
	intel_aux_display_runtime_put(dev_priv);
571

572 573 574
	if (vdd)
		edp_panel_vdd_off(intel_dp, false);

575
	return ret;
576 577
}

578 579
#define BARE_ADDRESS_SIZE	3
#define HEADER_SIZE		(BARE_ADDRESS_SIZE + 1)
580 581
static ssize_t
intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
582
{
583 584 585
	struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
	uint8_t txbuf[20], rxbuf[20];
	size_t txsize, rxsize;
586 587
	int ret;

588 589 590 591
	txbuf[0] = msg->request << 4;
	txbuf[1] = msg->address >> 8;
	txbuf[2] = msg->address & 0xff;
	txbuf[3] = msg->size - 1;
592

593 594 595
	switch (msg->request & ~DP_AUX_I2C_MOT) {
	case DP_AUX_NATIVE_WRITE:
	case DP_AUX_I2C_WRITE:
596
		txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
597
		rxsize = 1;
598

599 600
		if (WARN_ON(txsize > 20))
			return -E2BIG;
601

602
		memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
603

604 605 606
		ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
		if (ret > 0) {
			msg->reply = rxbuf[0] >> 4;
607

608 609 610 611
			/* Return payload size. */
			ret = msg->size;
		}
		break;
612

613 614
	case DP_AUX_NATIVE_READ:
	case DP_AUX_I2C_READ:
615
		txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
616
		rxsize = msg->size + 1;
617

618 619
		if (WARN_ON(rxsize > 20))
			return -E2BIG;
620

621 622 623 624 625 626 627 628 629 630 631
		ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
		if (ret > 0) {
			msg->reply = rxbuf[0] >> 4;
			/*
			 * Assume happy day, and copy the data. The caller is
			 * expected to check msg->reply before touching it.
			 *
			 * Return payload size.
			 */
			ret--;
			memcpy(msg->buffer, rxbuf + 1, ret);
632
		}
633 634 635 636 637
		break;

	default:
		ret = -EINVAL;
		break;
638
	}
639

640
	return ret;
641 642
}

643 644 645 646
static void
intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
647 648
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	enum port port = intel_dig_port->port;
649
	const char *name = NULL;
650 651
	int ret;

652 653 654
	switch (port) {
	case PORT_A:
		intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
655
		name = "DPDDC-A";
656
		break;
657 658
	case PORT_B:
		intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
659
		name = "DPDDC-B";
660
		break;
661 662
	case PORT_C:
		intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
663
		name = "DPDDC-C";
664
		break;
665 666
	case PORT_D:
		intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
667
		name = "DPDDC-D";
668 669 670
		break;
	default:
		BUG();
671 672
	}

673 674
	if (!HAS_DDI(dev))
		intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
675

676
	intel_dp->aux.name = name;
677 678
	intel_dp->aux.dev = dev->dev;
	intel_dp->aux.transfer = intel_dp_aux_transfer;
679

680 681
	DRM_DEBUG_KMS("registering %s bus for %s\n", name,
		      connector->base.kdev->kobj.name);
682

683 684 685 686 687
	ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux);
	if (ret < 0) {
		DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n",
			  name, ret);
		return;
688
	}
689

690 691 692 693 694 695
	ret = sysfs_create_link(&connector->base.kdev->kobj,
				&intel_dp->aux.ddc.dev.kobj,
				intel_dp->aux.ddc.dev.kobj.name);
	if (ret < 0) {
		DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
		drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
696
	}
697 698
}

699 700 701 702 703 704
static void
intel_dp_connector_unregister(struct intel_connector *intel_connector)
{
	struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);

	sysfs_remove_link(&intel_connector->base.kdev->kobj,
705
			  intel_dp->aux.ddc.dev.kobj.name);
706 707 708
	intel_connector_unregister(intel_connector);
}

709 710 711 712 713
static void
intel_dp_set_clock(struct intel_encoder *encoder,
		   struct intel_crtc_config *pipe_config, int link_bw)
{
	struct drm_device *dev = encoder->base.dev;
714 715
	const struct dp_link_dpll *divisor = NULL;
	int i, count = 0;
716 717

	if (IS_G4X(dev)) {
718 719
		divisor = gen4_dpll;
		count = ARRAY_SIZE(gen4_dpll);
720 721 722
	} else if (IS_HASWELL(dev)) {
		/* Haswell has special-purpose DP DDI clocks. */
	} else if (HAS_PCH_SPLIT(dev)) {
723 724
		divisor = pch_dpll;
		count = ARRAY_SIZE(pch_dpll);
725
	} else if (IS_VALLEYVIEW(dev)) {
726 727
		divisor = vlv_dpll;
		count = ARRAY_SIZE(vlv_dpll);
728
	}
729 730 731 732 733 734 735 736 737

	if (divisor && count) {
		for (i = 0; i < count; i++) {
			if (link_bw == divisor[i].link_bw) {
				pipe_config->dpll = divisor[i].dpll;
				pipe_config->clock_set = true;
				break;
			}
		}
738 739 740
	}
}

741 742 743 744 745 746 747 748 749 750 751 752 753 754
static void
intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n)
{
	struct drm_device *dev = crtc->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum transcoder transcoder = crtc->config.cpu_transcoder;

	I915_WRITE(PIPE_DATA_M2(transcoder),
		TU_SIZE(m_n->tu) | m_n->gmch_m);
	I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n);
	I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m);
	I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n);
}

P
Paulo Zanoni 已提交
755
bool
756 757
intel_dp_compute_config(struct intel_encoder *encoder,
			struct intel_crtc_config *pipe_config)
758
{
759
	struct drm_device *dev = encoder->base.dev;
760
	struct drm_i915_private *dev_priv = dev->dev_private;
761 762
	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
763
	enum port port = dp_to_dig_port(intel_dp)->port;
764
	struct intel_crtc *intel_crtc = encoder->new_crtc;
765
	struct intel_connector *intel_connector = intel_dp->attached_connector;
766
	int lane_count, clock;
767
	int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
768 769
	/* Conveniently, the link BW constants become indices with a shift...*/
	int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
770
	int bpp, mode_rate;
771
	static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
772
	int link_avail, link_clock;
773

774
	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
775 776
		pipe_config->has_pch_encoder = true;

777
	pipe_config->has_dp_encoder = true;
778

779 780 781
	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
		intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
				       adjusted_mode);
782 783 784 785
		if (!HAS_PCH_SPLIT(dev))
			intel_gmch_panel_fitting(intel_crtc, pipe_config,
						 intel_connector->panel.fitting_mode);
		else
786 787
			intel_pch_panel_fitting(intel_crtc, pipe_config,
						intel_connector->panel.fitting_mode);
788 789
	}

790
	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
791 792
		return false;

793 794
	DRM_DEBUG_KMS("DP link computation with max lane count %i "
		      "max bw %02x pixel clock %iKHz\n",
795 796
		      max_lane_count, bws[max_clock],
		      adjusted_mode->crtc_clock);
797

798 799
	/* Walk through all bpp values. Luckily they're all nicely spaced with 2
	 * bpc in between. */
800
	bpp = pipe_config->pipe_bpp;
801 802
	if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
	    dev_priv->vbt.edp_bpp < bpp) {
803 804
		DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
			      dev_priv->vbt.edp_bpp);
805
		bpp = dev_priv->vbt.edp_bpp;
806
	}
807

808
	for (; bpp >= 6*3; bpp -= 2*3) {
809 810
		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
						   bpp);
811

812 813
		for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
			for (clock = 0; clock <= max_clock; clock++) {
814 815 816 817 818 819 820 821 822 823
				link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
				link_avail = intel_dp_max_data_rate(link_clock,
								    lane_count);

				if (mode_rate <= link_avail) {
					goto found;
				}
			}
		}
	}
824

825
	return false;
826

827
found:
828 829 830 831 832 833
	if (intel_dp->color_range_auto) {
		/*
		 * See:
		 * CEA-861-E - 5.1 Default Encoding Parameters
		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
		 */
834
		if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
835 836 837 838 839
			intel_dp->color_range = DP_COLOR_RANGE_16_235;
		else
			intel_dp->color_range = 0;
	}

840
	if (intel_dp->color_range)
841
		pipe_config->limited_color_range = true;
842

843 844
	intel_dp->link_bw = bws[clock];
	intel_dp->lane_count = lane_count;
845
	pipe_config->pipe_bpp = bpp;
846
	pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
847

848 849
	DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
		      intel_dp->link_bw, intel_dp->lane_count,
850
		      pipe_config->port_clock, bpp);
851 852
	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
		      mode_rate, link_avail);
853

854
	intel_link_compute_m_n(bpp, lane_count,
855 856
			       adjusted_mode->crtc_clock,
			       pipe_config->port_clock,
857
			       &pipe_config->dp_m_n);
858

859 860 861 862 863 864 865 866
	if (intel_connector->panel.downclock_mode != NULL &&
		intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
			intel_link_compute_m_n(bpp, lane_count,
				intel_connector->panel.downclock_mode->clock,
				pipe_config->port_clock,
				&pipe_config->dp_m2_n2);
	}

867 868
	intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);

869
	return true;
870 871
}

872
static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
873
{
874 875 876
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
	struct drm_device *dev = crtc->base.dev;
877 878 879
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

880
	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
881 882 883
	dpa_ctl = I915_READ(DP_A);
	dpa_ctl &= ~DP_PLL_FREQ_MASK;

884
	if (crtc->config.port_clock == 162000) {
885 886 887 888
		/* For a long time we've carried around a ILK-DevA w/a for the
		 * 160MHz clock. If we're really unlucky, it's still required.
		 */
		DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
889
		dpa_ctl |= DP_PLL_FREQ_160MHZ;
890
		intel_dp->DP |= DP_PLL_FREQ_160MHZ;
891 892
	} else {
		dpa_ctl |= DP_PLL_FREQ_270MHZ;
893
		intel_dp->DP |= DP_PLL_FREQ_270MHZ;
894
	}
895

896 897 898 899 900 901
	I915_WRITE(DP_A, dpa_ctl);

	POSTING_READ(DP_A);
	udelay(500);
}

902
static void intel_dp_mode_set(struct intel_encoder *encoder)
903
{
904
	struct drm_device *dev = encoder->base.dev;
905
	struct drm_i915_private *dev_priv = dev->dev_private;
906
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
907
	enum port port = dp_to_dig_port(intel_dp)->port;
908 909
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
910

911
	/*
K
Keith Packard 已提交
912
	 * There are four kinds of DP registers:
913 914
	 *
	 * 	IBX PCH
K
Keith Packard 已提交
915 916
	 * 	SNB CPU
	 *	IVB CPU
917 918 919 920 921 922 923 924 925 926
	 * 	CPT PCH
	 *
	 * IBX PCH and CPU are the same for almost everything,
	 * except that the CPU DP PLL is configured in this
	 * register
	 *
	 * CPT PCH is quite different, having many bits moved
	 * to the TRANS_DP_CTL register instead. That
	 * configuration happens (oddly) in ironlake_pch_enable
	 */
927

928 929 930 931
	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
932

933 934
	/* Handle DP bits in common between all three register formats */
	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
935
	intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
936

937 938
	if (intel_dp->has_audio) {
		DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
939
				 pipe_name(crtc->pipe));
C
Chris Wilson 已提交
940
		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
941
		intel_write_eld(&encoder->base, adjusted_mode);
942
	}
943

944
	/* Split out the IBX/CPU vs CPT settings */
945

946
	if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
K
Keith Packard 已提交
947 948 949 950 951 952
		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

953
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
K
Keith Packard 已提交
954 955
			intel_dp->DP |= DP_ENHANCED_FRAMING;

956
		intel_dp->DP |= crtc->pipe << 29;
957
	} else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
958
		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
959
			intel_dp->DP |= intel_dp->color_range;
960 961 962 963 964 965 966

		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF;

967
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
968 969
			intel_dp->DP |= DP_ENHANCED_FRAMING;

970
		if (crtc->pipe == 1)
971 972 973
			intel_dp->DP |= DP_PIPEB_SELECT;
	} else {
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
974
	}
975

976
	if (port == PORT_A && !IS_VALLEYVIEW(dev))
977
		ironlake_set_pll_cpu_edp(intel_dp);
978 979
}

980 981
#define IDLE_ON_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
#define IDLE_ON_VALUE   	(PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
982

983 984
#define IDLE_OFF_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
#define IDLE_OFF_VALUE		(0     | PP_SEQUENCE_NONE | 0                     | 0)
985

986 987
#define IDLE_CYCLE_MASK		(PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
#define IDLE_CYCLE_VALUE	(0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
988

989
static void wait_panel_status(struct intel_dp *intel_dp,
990 991
				       u32 mask,
				       u32 value)
992
{
993
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
994
	struct drm_i915_private *dev_priv = dev->dev_private;
995 996
	u32 pp_stat_reg, pp_ctrl_reg;

997 998
	pp_stat_reg = _pp_stat_reg(intel_dp);
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
999

1000
	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1001 1002 1003
			mask, value,
			I915_READ(pp_stat_reg),
			I915_READ(pp_ctrl_reg));
1004

1005
	if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1006
		DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1007 1008
				I915_READ(pp_stat_reg),
				I915_READ(pp_ctrl_reg));
1009
	}
1010 1011

	DRM_DEBUG_KMS("Wait complete\n");
1012
}
1013

1014
static void wait_panel_on(struct intel_dp *intel_dp)
1015 1016
{
	DRM_DEBUG_KMS("Wait for panel power on\n");
1017
	wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1018 1019
}

1020
static void wait_panel_off(struct intel_dp *intel_dp)
1021 1022
{
	DRM_DEBUG_KMS("Wait for panel power off time\n");
1023
	wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1024 1025
}

1026
static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1027 1028
{
	DRM_DEBUG_KMS("Wait for panel power cycle\n");
1029 1030 1031 1032 1033 1034

	/* When we disable the VDD override bit last we have to do the manual
	 * wait. */
	wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
				       intel_dp->panel_power_cycle_delay);

1035
	wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1036 1037
}

1038
static void wait_backlight_on(struct intel_dp *intel_dp)
1039 1040 1041 1042 1043
{
	wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
				       intel_dp->backlight_on_delay);
}

1044
static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1045 1046 1047 1048
{
	wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
				       intel_dp->backlight_off_delay);
}
1049

1050 1051 1052 1053
/* Read the current pp_control value, unlocking the register if it
 * is locked
 */

1054
static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1055
{
1056 1057 1058
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 control;
1059

1060
	control = I915_READ(_pp_ctrl_reg(intel_dp));
1061 1062 1063
	control &= ~PANEL_UNLOCK_MASK;
	control |= PANEL_UNLOCK_REGS;
	return control;
1064 1065
}

1066
static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
1067
{
1068
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1069 1070
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
1071
	struct drm_i915_private *dev_priv = dev->dev_private;
1072
	enum intel_display_power_domain power_domain;
1073
	u32 pp;
1074
	u32 pp_stat_reg, pp_ctrl_reg;
1075
	bool need_to_disable = !intel_dp->want_panel_vdd;
1076

1077
	if (!is_edp(intel_dp))
1078
		return false;
1079 1080

	intel_dp->want_panel_vdd = true;
1081

1082
	if (edp_have_panel_vdd(intel_dp))
1083
		return need_to_disable;
1084

1085 1086
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);
1087

1088
	DRM_DEBUG_KMS("Turning eDP VDD on\n");
1089

1090 1091
	if (!edp_have_panel_power(intel_dp))
		wait_panel_power_cycle(intel_dp);
1092

1093
	pp = ironlake_get_pp_control(intel_dp);
1094
	pp |= EDP_FORCE_VDD;
1095

1096 1097
	pp_stat_reg = _pp_stat_reg(intel_dp);
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1098 1099 1100 1101 1102

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
			I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1103 1104 1105
	/*
	 * If the panel wasn't on, delay before accessing aux channel
	 */
1106
	if (!edp_have_panel_power(intel_dp)) {
1107
		DRM_DEBUG_KMS("eDP was not running\n");
1108 1109
		msleep(intel_dp->panel_power_up_delay);
	}
1110 1111 1112 1113

	return need_to_disable;
}

1114
void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1115 1116 1117 1118 1119 1120
{
	if (is_edp(intel_dp)) {
		bool vdd = _edp_panel_vdd_on(intel_dp);

		WARN(!vdd, "eDP VDD already requested on\n");
	}
1121 1122
}

1123
static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1124
{
1125
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1126 1127
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
1128
	u32 pp_stat_reg, pp_ctrl_reg;
1129

1130 1131
	WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));

1132
	if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1133 1134 1135 1136 1137
		struct intel_digital_port *intel_dig_port =
						dp_to_dig_port(intel_dp);
		struct intel_encoder *intel_encoder = &intel_dig_port->base;
		enum intel_display_power_domain power_domain;

1138 1139
		DRM_DEBUG_KMS("Turning eDP VDD off\n");

1140
		pp = ironlake_get_pp_control(intel_dp);
1141 1142
		pp &= ~EDP_FORCE_VDD;

1143 1144
		pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
		pp_stat_reg = _pp_stat_reg(intel_dp);
1145 1146 1147

		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1148

1149 1150 1151
		/* Make sure sequencer is idle before allowing subsequent activity */
		DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
		I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
P
Paulo Zanoni 已提交
1152 1153

		if ((pp & POWER_TARGET_ON) == 0)
1154
			intel_dp->last_power_cycle = jiffies;
1155

1156 1157
		power_domain = intel_display_port_power_domain(intel_encoder);
		intel_display_power_put(dev_priv, power_domain);
1158 1159
	}
}
1160

1161
static void edp_panel_vdd_work(struct work_struct *__work)
1162 1163 1164
{
	struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
						 struct intel_dp, panel_vdd_work);
1165
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1166

1167
	mutex_lock(&dev->mode_config.mutex);
1168
	edp_panel_vdd_off_sync(intel_dp);
1169
	mutex_unlock(&dev->mode_config.mutex);
1170 1171
}

1172
static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1173
{
1174 1175
	if (!is_edp(intel_dp))
		return;
1176

1177
	WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1178

1179 1180 1181
	intel_dp->want_panel_vdd = false;

	if (sync) {
1182
		edp_panel_vdd_off_sync(intel_dp);
1183 1184 1185 1186 1187 1188 1189 1190 1191
	} else {
		/*
		 * Queue the timer to fire a long
		 * time from now (relative to the power down delay)
		 * to keep the panel power up across a sequence of operations
		 */
		schedule_delayed_work(&intel_dp->panel_vdd_work,
				      msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
	}
1192 1193
}

1194
void intel_edp_panel_on(struct intel_dp *intel_dp)
1195
{
1196
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1197
	struct drm_i915_private *dev_priv = dev->dev_private;
1198
	u32 pp;
1199
	u32 pp_ctrl_reg;
1200

1201
	if (!is_edp(intel_dp))
1202
		return;
1203 1204 1205

	DRM_DEBUG_KMS("Turn eDP power on\n");

1206
	if (edp_have_panel_power(intel_dp)) {
1207
		DRM_DEBUG_KMS("eDP power already on\n");
1208
		return;
1209
	}
1210

1211
	wait_panel_power_cycle(intel_dp);
1212

1213
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1214
	pp = ironlake_get_pp_control(intel_dp);
1215 1216 1217
	if (IS_GEN5(dev)) {
		/* ILK workaround: disable reset around power sequence */
		pp &= ~PANEL_POWER_RESET;
1218 1219
		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1220
	}
1221

1222
	pp |= POWER_TARGET_ON;
1223 1224 1225
	if (!IS_GEN5(dev))
		pp |= PANEL_POWER_RESET;

1226 1227
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1228

1229
	wait_panel_on(intel_dp);
1230
	intel_dp->last_power_on = jiffies;
1231

1232 1233
	if (IS_GEN5(dev)) {
		pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1234 1235
		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1236
	}
1237 1238
}

1239
void intel_edp_panel_off(struct intel_dp *intel_dp)
1240
{
1241 1242
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
1243
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1244
	struct drm_i915_private *dev_priv = dev->dev_private;
1245
	enum intel_display_power_domain power_domain;
1246
	u32 pp;
1247
	u32 pp_ctrl_reg;
1248

1249 1250
	if (!is_edp(intel_dp))
		return;
1251

1252
	DRM_DEBUG_KMS("Turn eDP power off\n");
1253

1254
	edp_wait_backlight_off(intel_dp);
1255

1256 1257
	WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");

1258
	pp = ironlake_get_pp_control(intel_dp);
1259 1260
	/* We need to switch off panel power _and_ force vdd, for otherwise some
	 * panels get very unhappy and cease to work. */
1261 1262
	pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
		EDP_BLC_ENABLE);
1263

1264
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1265

1266 1267
	intel_dp->want_panel_vdd = false;

1268 1269
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1270

1271
	intel_dp->last_power_cycle = jiffies;
1272
	wait_panel_off(intel_dp);
1273 1274

	/* We got a reference when we enabled the VDD. */
1275 1276
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_put(dev_priv, power_domain);
1277 1278
}

1279
void intel_edp_backlight_on(struct intel_dp *intel_dp)
1280
{
1281 1282
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
1283 1284
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
1285
	u32 pp_ctrl_reg;
1286

1287 1288 1289
	if (!is_edp(intel_dp))
		return;

1290
	DRM_DEBUG_KMS("\n");
1291 1292 1293 1294 1295 1296
	/*
	 * If we enable the backlight right away following a panel power
	 * on, we may see slight flicker as the panel syncs with the eDP
	 * link.  So delay a bit to make sure the image is solid before
	 * allowing it to appear.
	 */
1297
	wait_backlight_on(intel_dp);
1298
	pp = ironlake_get_pp_control(intel_dp);
1299
	pp |= EDP_BLC_ENABLE;
1300

1301
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1302 1303 1304

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1305

1306
	intel_panel_enable_backlight(intel_dp->attached_connector);
1307 1308
}

1309
void intel_edp_backlight_off(struct intel_dp *intel_dp)
1310
{
1311
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1312 1313
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
1314
	u32 pp_ctrl_reg;
1315

1316 1317 1318
	if (!is_edp(intel_dp))
		return;

1319
	intel_panel_disable_backlight(intel_dp->attached_connector);
1320

1321
	DRM_DEBUG_KMS("\n");
1322
	pp = ironlake_get_pp_control(intel_dp);
1323
	pp &= ~EDP_BLC_ENABLE;
1324

1325
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1326 1327 1328

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1329
	intel_dp->last_backlight_off = jiffies;
1330
}
1331

1332
static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1333
{
1334 1335 1336
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = crtc->dev;
1337 1338 1339
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

1340 1341 1342
	assert_pipe_disabled(dev_priv,
			     to_intel_crtc(crtc)->pipe);

1343 1344
	DRM_DEBUG_KMS("\n");
	dpa_ctl = I915_READ(DP_A);
1345 1346 1347 1348 1349 1350 1351 1352 1353
	WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");

	/* We don't adjust intel_dp->DP while tearing down the link, to
	 * facilitate link retraining (e.g. after hotplug). Hence clear all
	 * enable bits here to ensure that we don't enable too much. */
	intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
	intel_dp->DP |= DP_PLL_ENABLE;
	I915_WRITE(DP_A, intel_dp->DP);
1354 1355
	POSTING_READ(DP_A);
	udelay(200);
1356 1357
}

1358
static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1359
{
1360 1361 1362
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = crtc->dev;
1363 1364 1365
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

1366 1367 1368
	assert_pipe_disabled(dev_priv,
			     to_intel_crtc(crtc)->pipe);

1369
	dpa_ctl = I915_READ(DP_A);
1370 1371 1372 1373 1374 1375 1376
	WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
	     "dp pll off, should be on\n");
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");

	/* We can't rely on the value tracked for the DP register in
	 * intel_dp->DP because link_down must not change that (otherwise link
	 * re-training will fail. */
1377
	dpa_ctl &= ~DP_PLL_ENABLE;
1378
	I915_WRITE(DP_A, dpa_ctl);
1379
	POSTING_READ(DP_A);
1380 1381 1382
	udelay(200);
}

1383
/* If the sink supports it, try to set the power state appropriately */
1384
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1385 1386 1387 1388 1389 1390 1391 1392
{
	int ret, i;

	/* Should have a valid DPCD by this point */
	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
		return;

	if (mode != DRM_MODE_DPMS_ON) {
1393 1394
		ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
					 DP_SET_POWER_D3);
1395 1396 1397 1398 1399 1400 1401 1402
		if (ret != 1)
			DRM_DEBUG_DRIVER("failed to write sink power state\n");
	} else {
		/*
		 * When turning on, we need to retry for 1ms to give the sink
		 * time to wake up.
		 */
		for (i = 0; i < 3; i++) {
1403 1404
			ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
						 DP_SET_POWER_D0);
1405 1406 1407 1408 1409 1410 1411
			if (ret == 1)
				break;
			msleep(1);
		}
	}
}

1412 1413
static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
				  enum pipe *pipe)
1414
{
1415
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1416
	enum port port = dp_to_dig_port(intel_dp)->port;
1417 1418
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1419 1420 1421 1422 1423 1424 1425 1426
	enum intel_display_power_domain power_domain;
	u32 tmp;

	power_domain = intel_display_port_power_domain(encoder);
	if (!intel_display_power_enabled(dev_priv, power_domain))
		return false;

	tmp = I915_READ(intel_dp->output_reg);
1427 1428 1429 1430

	if (!(tmp & DP_PORT_EN))
		return false;

1431
	if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1432
		*pipe = PORT_TO_PIPE_CPT(tmp);
1433
	} else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461
		*pipe = PORT_TO_PIPE(tmp);
	} else {
		u32 trans_sel;
		u32 trans_dp;
		int i;

		switch (intel_dp->output_reg) {
		case PCH_DP_B:
			trans_sel = TRANS_DP_PORT_SEL_B;
			break;
		case PCH_DP_C:
			trans_sel = TRANS_DP_PORT_SEL_C;
			break;
		case PCH_DP_D:
			trans_sel = TRANS_DP_PORT_SEL_D;
			break;
		default:
			return true;
		}

		for_each_pipe(i) {
			trans_dp = I915_READ(TRANS_DP_CTL(i));
			if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
				*pipe = i;
				return true;
			}
		}

1462 1463 1464
		DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
			      intel_dp->output_reg);
	}
1465

1466 1467
	return true;
}
1468

1469 1470 1471 1472 1473
static void intel_dp_get_config(struct intel_encoder *encoder,
				struct intel_crtc_config *pipe_config)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	u32 tmp, flags = 0;
1474 1475 1476 1477
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = dp_to_dig_port(intel_dp)->port;
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1478
	int dotclock;
1479

1480 1481 1482 1483 1484 1485
	if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
		tmp = I915_READ(intel_dp->output_reg);
		if (tmp & DP_SYNC_HS_HIGH)
			flags |= DRM_MODE_FLAG_PHSYNC;
		else
			flags |= DRM_MODE_FLAG_NHSYNC;
1486

1487 1488 1489 1490 1491 1492 1493 1494 1495 1496
		if (tmp & DP_SYNC_VS_HIGH)
			flags |= DRM_MODE_FLAG_PVSYNC;
		else
			flags |= DRM_MODE_FLAG_NVSYNC;
	} else {
		tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
		if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
			flags |= DRM_MODE_FLAG_PHSYNC;
		else
			flags |= DRM_MODE_FLAG_NHSYNC;
1497

1498 1499 1500 1501 1502
		if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
			flags |= DRM_MODE_FLAG_PVSYNC;
		else
			flags |= DRM_MODE_FLAG_NVSYNC;
	}
1503 1504

	pipe_config->adjusted_mode.flags |= flags;
1505

1506 1507 1508 1509
	pipe_config->has_dp_encoder = true;

	intel_dp_get_m_n(crtc, pipe_config);

1510
	if (port == PORT_A) {
1511 1512 1513 1514 1515
		if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
			pipe_config->port_clock = 162000;
		else
			pipe_config->port_clock = 270000;
	}
1516 1517 1518 1519 1520 1521 1522

	dotclock = intel_dotclock_calculate(pipe_config->port_clock,
					    &pipe_config->dp_m_n);

	if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
		ironlake_check_encoder_dotclock(pipe_config, dotclock);

1523
	pipe_config->adjusted_mode.crtc_clock = dotclock;
1524

1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543
	if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
	    pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
		/*
		 * This is a big fat ugly hack.
		 *
		 * Some machines in UEFI boot mode provide us a VBT that has 18
		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
		 * unknown we fail to light up. Yet the same BIOS boots up with
		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
		 * max, not what it tells us to use.
		 *
		 * Note: This will still be broken if the eDP panel is not lit
		 * up by the BIOS, and thus we can't get the mode at module
		 * load.
		 */
		DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
			      pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
		dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
	}
1544 1545
}

R
Rodrigo Vivi 已提交
1546
static bool is_edp_psr(struct drm_device *dev)
1547
{
R
Rodrigo Vivi 已提交
1548 1549 1550
	struct drm_i915_private *dev_priv = dev->dev_private;

	return dev_priv->psr.sink_support;
1551 1552
}

R
Rodrigo Vivi 已提交
1553 1554 1555 1556
static bool intel_edp_is_psr_enabled(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

1557
	if (!HAS_PSR(dev))
R
Rodrigo Vivi 已提交
1558 1559
		return false;

1560
	return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
R
Rodrigo Vivi 已提交
1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609
}

static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
				    struct edp_vsc_psr *vsc_psr)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
	u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
	uint32_t *data = (uint32_t *) vsc_psr;
	unsigned int i;

	/* As per BSPec (Pipe Video Data Island Packet), we need to disable
	   the video DIP being updated before program video DIP data buffer
	   registers for DIP being updated. */
	I915_WRITE(ctl_reg, 0);
	POSTING_READ(ctl_reg);

	for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
		if (i < sizeof(struct edp_vsc_psr))
			I915_WRITE(data_reg + i, *data++);
		else
			I915_WRITE(data_reg + i, 0);
	}

	I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
	POSTING_READ(ctl_reg);
}

static void intel_edp_psr_setup(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct edp_vsc_psr psr_vsc;

	if (intel_dp->psr_setup_done)
		return;

	/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
	memset(&psr_vsc, 0, sizeof(psr_vsc));
	psr_vsc.sdp_header.HB0 = 0;
	psr_vsc.sdp_header.HB1 = 0x7;
	psr_vsc.sdp_header.HB2 = 0x2;
	psr_vsc.sdp_header.HB3 = 0x8;
	intel_edp_psr_write_vsc(intel_dp, &psr_vsc);

	/* Avoid continuous PSR exit by masking memup and hpd */
1610
	I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1611
		   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
R
Rodrigo Vivi 已提交
1612 1613 1614 1615 1616 1617 1618 1619

	intel_dp->psr_setup_done = true;
}

static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
1620
	uint32_t aux_clock_divider;
R
Rodrigo Vivi 已提交
1621 1622 1623
	int precharge = 0x3;
	int msg_size = 5;       /* Header(4) + Message(1) */

1624 1625
	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);

R
Rodrigo Vivi 已提交
1626 1627
	/* Enable PSR in sink */
	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1628 1629
		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
				   DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
R
Rodrigo Vivi 已提交
1630
	else
1631 1632
		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
				   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
R
Rodrigo Vivi 已提交
1633 1634

	/* Setup AUX registers */
1635 1636 1637
	I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
	I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
	I915_WRITE(EDP_PSR_AUX_CTL(dev),
R
Rodrigo Vivi 已提交
1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650
		   DP_AUX_CH_CTL_TIME_OUT_400us |
		   (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
		   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
		   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
}

static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t max_sleep_time = 0x1f;
	uint32_t idle_frames = 1;
	uint32_t val = 0x0;
B
Ben Widawsky 已提交
1651
	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
R
Rodrigo Vivi 已提交
1652 1653 1654 1655 1656 1657 1658 1659 1660

	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
		val |= EDP_PSR_LINK_STANDBY;
		val |= EDP_PSR_TP2_TP3_TIME_0us;
		val |= EDP_PSR_TP1_TIME_0us;
		val |= EDP_PSR_SKIP_AUX_EXIT;
	} else
		val |= EDP_PSR_LINK_DISABLE;

1661
	I915_WRITE(EDP_PSR_CTL(dev), val |
B
Ben Widawsky 已提交
1662
		   (IS_BROADWELL(dev) ? 0 : link_entry_time) |
R
Rodrigo Vivi 已提交
1663 1664 1665 1666 1667
		   max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
		   idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
		   EDP_PSR_ENABLE);
}

1668 1669 1670 1671 1672 1673 1674
static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dig_port->base.base.crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1675
	struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
1676 1677
	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;

R
Rodrigo Vivi 已提交
1678 1679
	dev_priv->psr.source_ok = false;

1680
	if (!HAS_PSR(dev)) {
1681 1682 1683 1684 1685 1686 1687 1688 1689 1690
		DRM_DEBUG_KMS("PSR not supported on this platform\n");
		return false;
	}

	if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
	    (dig_port->port != PORT_A)) {
		DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
		return false;
	}

1691
	if (!i915.enable_psr) {
1692 1693 1694 1695
		DRM_DEBUG_KMS("PSR disable by flag\n");
		return false;
	}

1696 1697 1698 1699 1700 1701 1702
	crtc = dig_port->base.base.crtc;
	if (crtc == NULL) {
		DRM_DEBUG_KMS("crtc not active for PSR\n");
		return false;
	}

	intel_crtc = to_intel_crtc(crtc);
1703
	if (!intel_crtc_active(crtc)) {
1704 1705 1706 1707
		DRM_DEBUG_KMS("crtc not active for PSR\n");
		return false;
	}

1708
	obj = to_intel_framebuffer(crtc->primary->fb)->obj;
1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725
	if (obj->tiling_mode != I915_TILING_X ||
	    obj->fence_reg == I915_FENCE_REG_NONE) {
		DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
		return false;
	}

	if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
		DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
		return false;
	}

	if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
	    S3D_ENABLE) {
		DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
		return false;
	}

1726
	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1727 1728 1729 1730
		DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
		return false;
	}

R
Rodrigo Vivi 已提交
1731
	dev_priv->psr.source_ok = true;
1732 1733 1734
	return true;
}

1735
static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
R
Rodrigo Vivi 已提交
1736 1737 1738
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

1739 1740
	if (!intel_edp_psr_match_conditions(intel_dp) ||
	    intel_edp_is_psr_enabled(dev))
R
Rodrigo Vivi 已提交
1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752
		return;

	/* Setup PSR once */
	intel_edp_psr_setup(intel_dp);

	/* Enable PSR on the panel */
	intel_edp_psr_enable_sink(intel_dp);

	/* Enable PSR on the host */
	intel_edp_psr_enable_source(intel_dp);
}

1753 1754 1755 1756 1757 1758 1759 1760 1761
void intel_edp_psr_enable(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

	if (intel_edp_psr_match_conditions(intel_dp) &&
	    !intel_edp_is_psr_enabled(dev))
		intel_edp_psr_do_enable(intel_dp);
}

R
Rodrigo Vivi 已提交
1762 1763 1764 1765 1766 1767 1768 1769
void intel_edp_psr_disable(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!intel_edp_is_psr_enabled(dev))
		return;

1770 1771
	I915_WRITE(EDP_PSR_CTL(dev),
		   I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
R
Rodrigo Vivi 已提交
1772 1773

	/* Wait till PSR is idle */
1774
	if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
R
Rodrigo Vivi 已提交
1775 1776 1777 1778
		       EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
		DRM_ERROR("Timed out waiting for PSR Idle State\n");
}

1779 1780 1781 1782 1783 1784 1785 1786 1787
void intel_edp_psr_update(struct drm_device *dev)
{
	struct intel_encoder *encoder;
	struct intel_dp *intel_dp = NULL;

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
		if (encoder->type == INTEL_OUTPUT_EDP) {
			intel_dp = enc_to_intel_dp(&encoder->base);

R
Rodrigo Vivi 已提交
1788
			if (!is_edp_psr(dev))
1789 1790 1791 1792 1793 1794 1795 1796 1797 1798
				return;

			if (!intel_edp_psr_match_conditions(intel_dp))
				intel_edp_psr_disable(intel_dp);
			else
				if (!intel_edp_is_psr_enabled(dev))
					intel_edp_psr_do_enable(intel_dp);
		}
}

1799
static void intel_disable_dp(struct intel_encoder *encoder)
1800
{
1801
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1802 1803
	enum port port = dp_to_dig_port(intel_dp)->port;
	struct drm_device *dev = encoder->base.dev;
1804 1805 1806

	/* Make sure the panel is off before trying to change the mode. But also
	 * ensure that we have vdd while we switch off the panel. */
1807
	intel_edp_panel_vdd_on(intel_dp);
1808
	intel_edp_backlight_off(intel_dp);
1809
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1810
	intel_edp_panel_off(intel_dp);
1811 1812

	/* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1813
	if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1814
		intel_dp_link_down(intel_dp);
1815 1816
}

1817
static void g4x_post_disable_dp(struct intel_encoder *encoder)
1818
{
1819
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1820
	enum port port = dp_to_dig_port(intel_dp)->port;
1821

1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833
	if (port != PORT_A)
		return;

	intel_dp_link_down(intel_dp);
	ironlake_edp_pll_off(intel_dp);
}

static void vlv_post_disable_dp(struct intel_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

	intel_dp_link_down(intel_dp);
1834 1835
}

1836
static void intel_enable_dp(struct intel_encoder *encoder)
1837
{
1838 1839 1840 1841
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1842

1843 1844
	if (WARN_ON(dp_reg & DP_PORT_EN))
		return;
1845

1846
	intel_edp_panel_vdd_on(intel_dp);
1847
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1848
	intel_dp_start_link_train(intel_dp);
1849 1850
	intel_edp_panel_on(intel_dp);
	edp_panel_vdd_off(intel_dp, true);
1851
	intel_dp_complete_link_train(intel_dp);
1852
	intel_dp_stop_link_train(intel_dp);
1853
}
1854

1855 1856
static void g4x_enable_dp(struct intel_encoder *encoder)
{
1857 1858
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

1859
	intel_enable_dp(encoder);
1860
	intel_edp_backlight_on(intel_dp);
1861
}
1862

1863 1864
static void vlv_enable_dp(struct intel_encoder *encoder)
{
1865 1866
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

1867
	intel_edp_backlight_on(intel_dp);
1868 1869
}

1870
static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1871 1872 1873 1874 1875 1876 1877 1878 1879
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);

	if (dport->port == PORT_A)
		ironlake_edp_pll_on(intel_dp);
}

static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1880
{
1881
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1882
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1883
	struct drm_device *dev = encoder->base.dev;
1884
	struct drm_i915_private *dev_priv = dev->dev_private;
1885
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1886
	enum dpio_channel port = vlv_dport_to_channel(dport);
1887
	int pipe = intel_crtc->pipe;
1888
	struct edp_power_seq power_seq;
1889
	u32 val;
1890

1891
	mutex_lock(&dev_priv->dpio_lock);
1892

1893
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1894 1895 1896 1897 1898 1899
	val = 0;
	if (pipe)
		val |= (1<<21);
	else
		val &= ~(1<<21);
	val |= 0x001000c4;
1900 1901 1902
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1903

1904 1905
	mutex_unlock(&dev_priv->dpio_lock);

1906 1907 1908 1909 1910 1911
	if (is_edp(intel_dp)) {
		/* init power sequencer on this pipe and port */
		intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
		intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
							      &power_seq);
	}
1912

1913 1914
	intel_enable_dp(encoder);

1915
	vlv_wait_port_ready(dev_priv, dport);
1916 1917
}

1918
static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1919 1920 1921 1922
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1923 1924
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
1925
	enum dpio_channel port = vlv_dport_to_channel(dport);
1926
	int pipe = intel_crtc->pipe;
1927 1928

	/* Program Tx lane resets to default */
1929
	mutex_lock(&dev_priv->dpio_lock);
1930
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1931 1932
			 DPIO_PCS_TX_LANE2_RESET |
			 DPIO_PCS_TX_LANE1_RESET);
1933
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1934 1935 1936 1937 1938 1939
			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
				 DPIO_PCS_CLK_SOFT_RESET);

	/* Fix up inter-pair skew failure */
1940 1941 1942
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1943
	mutex_unlock(&dev_priv->dpio_lock);
1944 1945 1946
}

/*
1947 1948
 * Native read with retry for link status and receiver capability reads for
 * cases where the sink may still be asleep.
1949 1950 1951
 *
 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
 * supposed to retry 3 times per the spec.
1952
 */
1953 1954 1955
static ssize_t
intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
			void *buffer, size_t size)
1956
{
1957 1958
	ssize_t ret;
	int i;
1959 1960

	for (i = 0; i < 3; i++) {
1961 1962 1963
		ret = drm_dp_dpcd_read(aux, offset, buffer, size);
		if (ret == size)
			return ret;
1964 1965
		msleep(1);
	}
1966

1967
	return ret;
1968 1969 1970 1971 1972 1973 1974
}

/*
 * Fetch AUX CH registers 0x202 - 0x207 which contain
 * link status information
 */
static bool
1975
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1976
{
1977 1978 1979 1980
	return intel_dp_dpcd_read_wake(&intel_dp->aux,
				       DP_LANE0_1_STATUS,
				       link_status,
				       DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
1981 1982 1983 1984 1985 1986 1987 1988
}

/*
 * These are source-specific values; current Intel hardware supports
 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
 */

static uint8_t
K
Keith Packard 已提交
1989
intel_dp_voltage_max(struct intel_dp *intel_dp)
1990
{
1991
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1992
	enum port port = dp_to_dig_port(intel_dp)->port;
K
Keith Packard 已提交
1993

1994
	if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
1995
		return DP_TRAIN_VOLTAGE_SWING_1200;
1996
	else if (IS_GEN7(dev) && port == PORT_A)
K
Keith Packard 已提交
1997
		return DP_TRAIN_VOLTAGE_SWING_800;
1998
	else if (HAS_PCH_CPT(dev) && port != PORT_A)
K
Keith Packard 已提交
1999 2000 2001 2002 2003 2004 2005 2006
		return DP_TRAIN_VOLTAGE_SWING_1200;
	else
		return DP_TRAIN_VOLTAGE_SWING_800;
}

static uint8_t
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
{
2007
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2008
	enum port port = dp_to_dig_port(intel_dp)->port;
K
Keith Packard 已提交
2009

2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021
	if (IS_BROADWELL(dev)) {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
	} else if (IS_HASWELL(dev)) {
2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_9_5;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044
	} else if (IS_VALLEYVIEW(dev)) {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_9_5;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
2045
	} else if (IS_GEN7(dev) && port == PORT_A) {
K
Keith Packard 已提交
2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_600:
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
	} else {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
2067 2068 2069
	}
}

2070 2071 2072 2073 2074
static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2075 2076
	struct intel_crtc *intel_crtc =
		to_intel_crtc(dport->base.base.crtc);
2077 2078 2079
	unsigned long demph_reg_value, preemph_reg_value,
		uniqtranscale_reg_value;
	uint8_t train_set = intel_dp->train_set[0];
2080
	enum dpio_channel port = vlv_dport_to_channel(dport);
2081
	int pipe = intel_crtc->pipe;
2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155

	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
	case DP_TRAIN_PRE_EMPHASIS_0:
		preemph_reg_value = 0x0004000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x552AB83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5548B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_800:
			demph_reg_value = 0x2B245555;
			uniqtranscale_reg_value = 0x5560B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_1200:
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x5598DA3A;
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_3_5:
		preemph_reg_value = 0x0002000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5552B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			demph_reg_value = 0x2B404848;
			uniqtranscale_reg_value = 0x5580B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_800:
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_6:
		preemph_reg_value = 0x0000000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x2B305555;
			uniqtranscale_reg_value = 0x5570B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			demph_reg_value = 0x2B2B4040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_9_5:
		preemph_reg_value = 0x0006000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x1B405555;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	default:
		return 0;
	}

2156
	mutex_lock(&dev_priv->dpio_lock);
2157 2158 2159
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2160
			 uniqtranscale_reg_value);
2161 2162 2163 2164
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2165
	mutex_unlock(&dev_priv->dpio_lock);
2166 2167 2168 2169

	return 0;
}

2170
static void
J
Jani Nikula 已提交
2171 2172
intel_get_adjust_train(struct intel_dp *intel_dp,
		       const uint8_t link_status[DP_LINK_STATUS_SIZE])
2173 2174 2175 2176
{
	uint8_t v = 0;
	uint8_t p = 0;
	int lane;
K
Keith Packard 已提交
2177 2178
	uint8_t voltage_max;
	uint8_t preemph_max;
2179

2180
	for (lane = 0; lane < intel_dp->lane_count; lane++) {
2181 2182
		uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
		uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2183 2184 2185 2186 2187 2188 2189

		if (this_v > v)
			v = this_v;
		if (this_p > p)
			p = this_p;
	}

K
Keith Packard 已提交
2190
	voltage_max = intel_dp_voltage_max(intel_dp);
2191 2192
	if (v >= voltage_max)
		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2193

K
Keith Packard 已提交
2194 2195 2196
	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
	if (p >= preemph_max)
		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2197 2198

	for (lane = 0; lane < 4; lane++)
2199
		intel_dp->train_set[lane] = v | p;
2200 2201 2202
}

static uint32_t
2203
intel_gen4_signal_levels(uint8_t train_set)
2204
{
2205
	uint32_t	signal_levels = 0;
2206

2207
	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2208 2209 2210 2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221
	case DP_TRAIN_VOLTAGE_SWING_400:
	default:
		signal_levels |= DP_VOLTAGE_0_4;
		break;
	case DP_TRAIN_VOLTAGE_SWING_600:
		signal_levels |= DP_VOLTAGE_0_6;
		break;
	case DP_TRAIN_VOLTAGE_SWING_800:
		signal_levels |= DP_VOLTAGE_0_8;
		break;
	case DP_TRAIN_VOLTAGE_SWING_1200:
		signal_levels |= DP_VOLTAGE_1_2;
		break;
	}
2222
	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239
	case DP_TRAIN_PRE_EMPHASIS_0:
	default:
		signal_levels |= DP_PRE_EMPHASIS_0;
		break;
	case DP_TRAIN_PRE_EMPHASIS_3_5:
		signal_levels |= DP_PRE_EMPHASIS_3_5;
		break;
	case DP_TRAIN_PRE_EMPHASIS_6:
		signal_levels |= DP_PRE_EMPHASIS_6;
		break;
	case DP_TRAIN_PRE_EMPHASIS_9_5:
		signal_levels |= DP_PRE_EMPHASIS_9_5;
		break;
	}
	return signal_levels;
}

2240 2241 2242 2243
/* Gen6's DP voltage swing and pre-emphasis control */
static uint32_t
intel_gen6_edp_signal_levels(uint8_t train_set)
{
2244 2245 2246
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
2247
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2248 2249 2250 2251
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2252
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2253 2254
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
		return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2255
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2256 2257
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2258
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2259 2260
	case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2261
	default:
2262 2263 2264
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2265 2266 2267
	}
}

K
Keith Packard 已提交
2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298
/* Gen7's DP voltage swing and pre-emphasis control */
static uint32_t
intel_gen7_edp_signal_levels(uint8_t train_set)
{
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_400MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
		return EDP_LINK_TRAIN_400MV_6DB_IVB;

	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_600MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_600MV_3_5DB_IVB;

	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_800MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_800MV_3_5DB_IVB;

	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_500MV_0DB_IVB;
	}
}

2299 2300
/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
static uint32_t
2301
intel_hsw_signal_levels(uint8_t train_set)
2302
{
2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_400MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_400MV_3_5DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
		return DDI_BUF_EMP_400MV_6DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
		return DDI_BUF_EMP_400MV_9_5DB_HSW;
2314

2315 2316 2317 2318 2319 2320
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_600MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_600MV_3_5DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
		return DDI_BUF_EMP_600MV_6DB_HSW;
2321

2322 2323 2324 2325 2326 2327 2328 2329
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_800MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_800MV_3_5DB_HSW;
	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return DDI_BUF_EMP_400MV_0DB_HSW;
2330 2331 2332
	}
}

2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367
static uint32_t
intel_bdw_signal_levels(uint8_t train_set)
{
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_400MV_0DB_BDW;	/* Sel0 */
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_400MV_3_5DB_BDW;	/* Sel1 */
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
		return DDI_BUF_EMP_400MV_6DB_BDW;	/* Sel2 */

	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_600MV_0DB_BDW;	/* Sel3 */
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_600MV_3_5DB_BDW;	/* Sel4 */
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
		return DDI_BUF_EMP_600MV_6DB_BDW;	/* Sel5 */

	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_800MV_0DB_BDW;	/* Sel6 */
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_800MV_3_5DB_BDW;	/* Sel7 */

	case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_1200MV_0DB_BDW;	/* Sel8 */

	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return DDI_BUF_EMP_400MV_0DB_BDW;	/* Sel0 */
	}
}

2368 2369 2370 2371 2372
/* Properly updates "DP" with the correct signal levels. */
static void
intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2373
	enum port port = intel_dig_port->port;
2374 2375 2376 2377
	struct drm_device *dev = intel_dig_port->base.base.dev;
	uint32_t signal_levels, mask;
	uint8_t train_set = intel_dp->train_set[0];

2378 2379 2380 2381
	if (IS_BROADWELL(dev)) {
		signal_levels = intel_bdw_signal_levels(train_set);
		mask = DDI_BUF_EMP_MASK;
	} else if (IS_HASWELL(dev)) {
2382 2383
		signal_levels = intel_hsw_signal_levels(train_set);
		mask = DDI_BUF_EMP_MASK;
2384 2385 2386
	} else if (IS_VALLEYVIEW(dev)) {
		signal_levels = intel_vlv_signal_levels(intel_dp);
		mask = 0;
2387
	} else if (IS_GEN7(dev) && port == PORT_A) {
2388 2389
		signal_levels = intel_gen7_edp_signal_levels(train_set);
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2390
	} else if (IS_GEN6(dev) && port == PORT_A) {
2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402
		signal_levels = intel_gen6_edp_signal_levels(train_set);
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
	} else {
		signal_levels = intel_gen4_signal_levels(train_set);
		mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
	}

	DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);

	*DP = (*DP & ~mask) | signal_levels;
}

2403
static bool
C
Chris Wilson 已提交
2404
intel_dp_set_link_train(struct intel_dp *intel_dp,
2405
			uint32_t *DP,
2406
			uint8_t dp_train_pat)
2407
{
2408 2409
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
2410
	struct drm_i915_private *dev_priv = dev->dev_private;
2411
	enum port port = intel_dig_port->port;
2412 2413
	uint8_t buf[sizeof(intel_dp->train_set) + 1];
	int ret, len;
2414

2415
	if (HAS_DDI(dev)) {
2416
		uint32_t temp = I915_READ(DP_TP_CTL(port));
2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438

		if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
			temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
		else
			temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;

		temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;

			break;
		case DP_TRAINING_PATTERN_1:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
			break;
		case DP_TRAINING_PATTERN_2:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
			break;
		case DP_TRAINING_PATTERN_3:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
			break;
		}
2439
		I915_WRITE(DP_TP_CTL(port), temp);
2440

2441
	} else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2442
		*DP &= ~DP_LINK_TRAIN_MASK_CPT;
2443 2444 2445

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
2446
			*DP |= DP_LINK_TRAIN_OFF_CPT;
2447 2448
			break;
		case DP_TRAINING_PATTERN_1:
2449
			*DP |= DP_LINK_TRAIN_PAT_1_CPT;
2450 2451
			break;
		case DP_TRAINING_PATTERN_2:
2452
			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
2453 2454 2455
			break;
		case DP_TRAINING_PATTERN_3:
			DRM_ERROR("DP training pattern 3 not supported\n");
2456
			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
2457 2458 2459 2460
			break;
		}

	} else {
2461
		*DP &= ~DP_LINK_TRAIN_MASK;
2462 2463 2464

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
2465
			*DP |= DP_LINK_TRAIN_OFF;
2466 2467
			break;
		case DP_TRAINING_PATTERN_1:
2468
			*DP |= DP_LINK_TRAIN_PAT_1;
2469 2470
			break;
		case DP_TRAINING_PATTERN_2:
2471
			*DP |= DP_LINK_TRAIN_PAT_2;
2472 2473 2474
			break;
		case DP_TRAINING_PATTERN_3:
			DRM_ERROR("DP training pattern 3 not supported\n");
2475
			*DP |= DP_LINK_TRAIN_PAT_2;
2476 2477 2478 2479
			break;
		}
	}

2480
	I915_WRITE(intel_dp->output_reg, *DP);
C
Chris Wilson 已提交
2481
	POSTING_READ(intel_dp->output_reg);
2482

2483 2484
	buf[0] = dp_train_pat;
	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2485
	    DP_TRAINING_PATTERN_DISABLE) {
2486 2487 2488 2489 2490 2491
		/* don't write DP_TRAINING_LANEx_SET on disable */
		len = 1;
	} else {
		/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
		memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
		len = intel_dp->lane_count + 1;
2492
	}
2493

2494 2495
	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
				buf, len);
2496 2497

	return ret == len;
2498 2499
}

2500 2501 2502 2503
static bool
intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
			uint8_t dp_train_pat)
{
2504
	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2505 2506 2507 2508 2509 2510
	intel_dp_set_signal_levels(intel_dp, DP);
	return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
}

static bool
intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
J
Jani Nikula 已提交
2511
			   const uint8_t link_status[DP_LINK_STATUS_SIZE])
2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	intel_get_adjust_train(intel_dp, link_status);
	intel_dp_set_signal_levels(intel_dp, DP);

	I915_WRITE(intel_dp->output_reg, *DP);
	POSTING_READ(intel_dp->output_reg);

2524 2525
	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
				intel_dp->train_set, intel_dp->lane_count);
2526 2527 2528 2529

	return ret == intel_dp->lane_count;
}

2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560
static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;
	uint32_t val;

	if (!HAS_DDI(dev))
		return;

	val = I915_READ(DP_TP_CTL(port));
	val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
	val |= DP_TP_CTL_LINK_TRAIN_IDLE;
	I915_WRITE(DP_TP_CTL(port), val);

	/*
	 * On PORT_A we can have only eDP in SST mode. There the only reason
	 * we need to set idle transmission mode is to work around a HW issue
	 * where we enable the pipe while not in idle link-training mode.
	 * In this case there is requirement to wait for a minimum number of
	 * idle patterns to be sent.
	 */
	if (port == PORT_A)
		return;

	if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
		     1))
		DRM_ERROR("Timed out waiting for DP idle patterns\n");
}

2561
/* Enable corresponding port and start training pattern 1 */
2562
void
2563
intel_dp_start_link_train(struct intel_dp *intel_dp)
2564
{
2565
	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2566
	struct drm_device *dev = encoder->dev;
2567 2568
	int i;
	uint8_t voltage;
2569
	int voltage_tries, loop_tries;
C
Chris Wilson 已提交
2570
	uint32_t DP = intel_dp->DP;
2571
	uint8_t link_config[2];
2572

P
Paulo Zanoni 已提交
2573
	if (HAS_DDI(dev))
2574 2575
		intel_ddi_prepare_link_retrain(encoder);

2576
	/* Write the link configuration data */
2577 2578 2579 2580
	link_config[0] = intel_dp->link_bw;
	link_config[1] = intel_dp->lane_count;
	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2581
	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
2582 2583 2584

	link_config[0] = 0;
	link_config[1] = DP_SET_ANSI_8B10B;
2585
	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
2586 2587

	DP |= DP_PORT_EN;
K
Keith Packard 已提交
2588

2589 2590 2591 2592 2593 2594 2595 2596
	/* clock recovery */
	if (!intel_dp_reset_link_train(intel_dp, &DP,
				       DP_TRAINING_PATTERN_1 |
				       DP_LINK_SCRAMBLING_DISABLE)) {
		DRM_ERROR("failed to enable link training\n");
		return;
	}

2597
	voltage = 0xff;
2598 2599
	voltage_tries = 0;
	loop_tries = 0;
2600
	for (;;) {
2601
		uint8_t link_status[DP_LINK_STATUS_SIZE];
2602

2603
		drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2604 2605
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
2606
			break;
2607
		}
2608

2609
		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2610
			DRM_DEBUG_KMS("clock recovery OK\n");
2611 2612 2613 2614 2615 2616
			break;
		}

		/* Check to see if we've tried the max voltage */
		for (i = 0; i < intel_dp->lane_count; i++)
			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2617
				break;
2618
		if (i == intel_dp->lane_count) {
2619 2620
			++loop_tries;
			if (loop_tries == 5) {
2621
				DRM_ERROR("too many full retries, give up\n");
2622 2623
				break;
			}
2624 2625 2626
			intel_dp_reset_link_train(intel_dp, &DP,
						  DP_TRAINING_PATTERN_1 |
						  DP_LINK_SCRAMBLING_DISABLE);
2627 2628 2629
			voltage_tries = 0;
			continue;
		}
2630

2631
		/* Check to see if we've tried the same voltage 5 times */
2632
		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2633
			++voltage_tries;
2634
			if (voltage_tries == 5) {
2635
				DRM_ERROR("too many voltage retries, give up\n");
2636 2637 2638 2639 2640
				break;
			}
		} else
			voltage_tries = 0;
		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2641

2642 2643 2644 2645 2646
		/* Update training set as requested by target */
		if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
			DRM_ERROR("failed to update link training\n");
			break;
		}
2647 2648
	}

2649 2650 2651
	intel_dp->DP = DP;
}

2652
void
2653 2654 2655
intel_dp_complete_link_train(struct intel_dp *intel_dp)
{
	bool channel_eq = false;
2656
	int tries, cr_tries;
2657
	uint32_t DP = intel_dp->DP;
2658 2659 2660 2661 2662
	uint32_t training_pattern = DP_TRAINING_PATTERN_2;

	/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
	if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
		training_pattern = DP_TRAINING_PATTERN_3;
2663

2664
	/* channel equalization */
2665
	if (!intel_dp_set_link_train(intel_dp, &DP,
2666
				     training_pattern |
2667 2668 2669 2670 2671
				     DP_LINK_SCRAMBLING_DISABLE)) {
		DRM_ERROR("failed to start channel equalization\n");
		return;
	}

2672
	tries = 0;
2673
	cr_tries = 0;
2674 2675
	channel_eq = false;
	for (;;) {
2676
		uint8_t link_status[DP_LINK_STATUS_SIZE];
2677

2678 2679 2680 2681 2682
		if (cr_tries > 5) {
			DRM_ERROR("failed to train DP, aborting\n");
			break;
		}

2683
		drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2684 2685
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
2686
			break;
2687
		}
2688

2689
		/* Make sure clock is still ok */
2690
		if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2691
			intel_dp_start_link_train(intel_dp);
2692
			intel_dp_set_link_train(intel_dp, &DP,
2693
						training_pattern |
2694
						DP_LINK_SCRAMBLING_DISABLE);
2695 2696 2697 2698
			cr_tries++;
			continue;
		}

2699
		if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2700 2701 2702
			channel_eq = true;
			break;
		}
2703

2704 2705 2706 2707
		/* Try 5 times, then try clock recovery if that fails */
		if (tries > 5) {
			intel_dp_link_down(intel_dp);
			intel_dp_start_link_train(intel_dp);
2708
			intel_dp_set_link_train(intel_dp, &DP,
2709
						training_pattern |
2710
						DP_LINK_SCRAMBLING_DISABLE);
2711 2712 2713 2714
			tries = 0;
			cr_tries++;
			continue;
		}
2715

2716 2717 2718 2719 2720
		/* Update training set as requested by target */
		if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
			DRM_ERROR("failed to update link training\n");
			break;
		}
2721
		++tries;
2722
	}
2723

2724 2725 2726 2727
	intel_dp_set_idle_link_train(intel_dp);

	intel_dp->DP = DP;

2728
	if (channel_eq)
M
Masanari Iida 已提交
2729
		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2730

2731 2732 2733 2734
}

void intel_dp_stop_link_train(struct intel_dp *intel_dp)
{
2735
	intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2736
				DP_TRAINING_PATTERN_DISABLE);
2737 2738 2739
}

static void
C
Chris Wilson 已提交
2740
intel_dp_link_down(struct intel_dp *intel_dp)
2741
{
2742
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2743
	enum port port = intel_dig_port->port;
2744
	struct drm_device *dev = intel_dig_port->base.base.dev;
2745
	struct drm_i915_private *dev_priv = dev->dev_private;
2746 2747
	struct intel_crtc *intel_crtc =
		to_intel_crtc(intel_dig_port->base.base.crtc);
C
Chris Wilson 已提交
2748
	uint32_t DP = intel_dp->DP;
2749

2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764
	/*
	 * DDI code has a strict mode set sequence and we should try to respect
	 * it, otherwise we might hang the machine in many different ways. So we
	 * really should be disabling the port only on a complete crtc_disable
	 * sequence. This function is just called under two conditions on DDI
	 * code:
	 * - Link train failed while doing crtc_enable, and on this case we
	 *   really should respect the mode set sequence and wait for a
	 *   crtc_disable.
	 * - Someone turned the monitor off and intel_dp_check_link_status
	 *   called us. We don't need to disable the whole port on this case, so
	 *   when someone turns the monitor on again,
	 *   intel_ddi_prepare_link_retrain will take care of redoing the link
	 *   train.
	 */
P
Paulo Zanoni 已提交
2765
	if (HAS_DDI(dev))
2766 2767
		return;

2768
	if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2769 2770
		return;

2771
	DRM_DEBUG_KMS("\n");
2772

2773
	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2774
		DP &= ~DP_LINK_TRAIN_MASK_CPT;
C
Chris Wilson 已提交
2775
		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2776 2777
	} else {
		DP &= ~DP_LINK_TRAIN_MASK;
C
Chris Wilson 已提交
2778
		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2779
	}
2780
	POSTING_READ(intel_dp->output_reg);
2781

2782
	if (HAS_PCH_IBX(dev) &&
2783
	    I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2784
		struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2785

2786 2787 2788 2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799
		/* Hardware workaround: leaving our transcoder select
		 * set to transcoder B while it's off will prevent the
		 * corresponding HDMI output on transcoder A.
		 *
		 * Combine this with another hardware workaround:
		 * transcoder select bit can only be cleared while the
		 * port is enabled.
		 */
		DP &= ~DP_PIPEB_SELECT;
		I915_WRITE(intel_dp->output_reg, DP);

		/* Changes to enable or select take place the vblank
		 * after being written.
		 */
2800 2801 2802 2803
		if (WARN_ON(crtc == NULL)) {
			/* We should never try to disable a port without a crtc
			 * attached. For paranoia keep the code around for a
			 * bit. */
2804 2805 2806
			POSTING_READ(intel_dp->output_reg);
			msleep(50);
		} else
2807
			intel_wait_for_vblank(dev, intel_crtc->pipe);
2808 2809
	}

2810
	DP &= ~DP_AUDIO_OUTPUT_ENABLE;
C
Chris Wilson 已提交
2811 2812
	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);
2813
	msleep(intel_dp->panel_power_down_delay);
2814 2815
}

2816 2817
static bool
intel_dp_get_dpcd(struct intel_dp *intel_dp)
2818
{
R
Rodrigo Vivi 已提交
2819 2820 2821 2822
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

2823 2824
	char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];

2825 2826
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
				    sizeof(intel_dp->dpcd)) < 0)
2827
		return false; /* aux transfer failed */
2828

2829 2830 2831 2832
	hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
			   32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
	DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);

2833 2834 2835
	if (intel_dp->dpcd[DP_DPCD_REV] == 0)
		return false; /* DPCD not present */

2836 2837
	/* Check if the panel supports PSR */
	memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2838
	if (is_edp(intel_dp)) {
2839 2840 2841
		intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
					intel_dp->psr_dpcd,
					sizeof(intel_dp->psr_dpcd));
R
Rodrigo Vivi 已提交
2842 2843
		if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
			dev_priv->psr.sink_support = true;
2844
			DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
R
Rodrigo Vivi 已提交
2845
		}
2846 2847
	}

2848 2849 2850 2851 2852 2853 2854 2855
	/* Training Pattern 3 support */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
	    intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
		intel_dp->use_tps3 = true;
		DRM_DEBUG_KMS("Displayport TPS3 supported");
	} else
		intel_dp->use_tps3 = false;

2856 2857 2858 2859 2860 2861 2862
	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
	      DP_DWN_STRM_PORT_PRESENT))
		return true; /* native DP sink */

	if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
		return true; /* no per-port downstream info */

2863 2864 2865
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
				    intel_dp->downstream_ports,
				    DP_MAX_DOWNSTREAM_PORTS) < 0)
2866 2867 2868
		return false; /* downstream port status fetch failed */

	return true;
2869 2870
}

2871 2872 2873 2874 2875 2876 2877 2878
static void
intel_dp_probe_oui(struct intel_dp *intel_dp)
{
	u8 buf[3];

	if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
		return;

2879
	intel_edp_panel_vdd_on(intel_dp);
D
Daniel Vetter 已提交
2880

2881
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
2882 2883 2884
		DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);

2885
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
2886 2887
		DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);
D
Daniel Vetter 已提交
2888

2889
	edp_panel_vdd_off(intel_dp, false);
2890 2891
}

2892 2893 2894 2895 2896 2897 2898 2899
int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(intel_dig_port->base.base.crtc);
	u8 buf[1];

2900
	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
2901 2902 2903 2904 2905
		return -EAGAIN;

	if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
		return -ENOTTY;

2906 2907
	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
			       DP_TEST_SINK_START) < 0)
2908 2909 2910 2911 2912 2913
		return -EAGAIN;

	/* Wait 2 vblanks to be sure we will have the correct CRC value */
	intel_wait_for_vblank(dev, intel_crtc->pipe);
	intel_wait_for_vblank(dev, intel_crtc->pipe);

2914
	if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
2915 2916
		return -EAGAIN;

2917
	drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
2918 2919 2920
	return 0;
}

2921 2922 2923
static bool
intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
2924 2925 2926
	return intel_dp_dpcd_read_wake(&intel_dp->aux,
				       DP_DEVICE_SERVICE_IRQ_VECTOR,
				       sink_irq_vector, 1) == 1;
2927 2928 2929 2930 2931 2932
}

static void
intel_dp_handle_test_request(struct intel_dp *intel_dp)
{
	/* NAK by default */
2933
	drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
2934 2935
}

2936 2937 2938 2939 2940 2941 2942 2943 2944
/*
 * According to DP spec
 * 5.1.2:
 *  1. Read DPCD
 *  2. Configure link according to Receiver Capabilities
 *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
 *  4. Check link status on receipt of hot-plug interrupt
 */

P
Paulo Zanoni 已提交
2945
void
C
Chris Wilson 已提交
2946
intel_dp_check_link_status(struct intel_dp *intel_dp)
2947
{
2948
	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2949
	u8 sink_irq_vector;
2950
	u8 link_status[DP_LINK_STATUS_SIZE];
2951

2952
	if (!intel_encoder->connectors_active)
2953
		return;
2954

2955
	if (WARN_ON(!intel_encoder->base.crtc))
2956 2957
		return;

2958
	/* Try to read receiver status if the link appears to be up */
2959
	if (!intel_dp_get_link_status(intel_dp, link_status)) {
2960 2961 2962
		return;
	}

2963
	/* Now read the DPCD to see if it's actually running */
2964
	if (!intel_dp_get_dpcd(intel_dp)) {
2965 2966 2967
		return;
	}

2968 2969 2970 2971
	/* Try to read the source of the interrupt */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
		/* Clear interrupt source */
2972 2973 2974
		drm_dp_dpcd_writeb(&intel_dp->aux,
				   DP_DEVICE_SERVICE_IRQ_VECTOR,
				   sink_irq_vector);
2975 2976 2977 2978 2979 2980 2981

		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
			intel_dp_handle_test_request(intel_dp);
		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
	}

2982
	if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2983
		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2984
			      drm_get_encoder_name(&intel_encoder->base));
2985 2986
		intel_dp_start_link_train(intel_dp);
		intel_dp_complete_link_train(intel_dp);
2987
		intel_dp_stop_link_train(intel_dp);
2988
	}
2989 2990
}

2991
/* XXX this is probably wrong for multiple downstream ports */
2992
static enum drm_connector_status
2993
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2994
{
2995 2996 2997 2998 2999 3000 3001 3002
	uint8_t *dpcd = intel_dp->dpcd;
	uint8_t type;

	if (!intel_dp_get_dpcd(intel_dp))
		return connector_status_disconnected;

	/* if there's no downstream port, we're done */
	if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
3003
		return connector_status_connected;
3004 3005

	/* If we're HPD-aware, SINK_COUNT changes dynamically */
3006 3007
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
3008
		uint8_t reg;
3009 3010 3011

		if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
					    &reg, 1) < 0)
3012
			return connector_status_unknown;
3013

3014 3015
		return DP_GET_SINK_COUNT(reg) ? connector_status_connected
					      : connector_status_disconnected;
3016 3017 3018
	}

	/* If no HPD, poke DDC gently */
3019
	if (drm_probe_ddc(&intel_dp->aux.ddc))
3020
		return connector_status_connected;
3021 3022

	/* Well we tried, say unknown for unreliable port types */
3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033 3034
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
		type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
		if (type == DP_DS_PORT_TYPE_VGA ||
		    type == DP_DS_PORT_TYPE_NON_EDID)
			return connector_status_unknown;
	} else {
		type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
			DP_DWN_STRM_PORT_TYPE_MASK;
		if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
		    type == DP_DWN_STRM_PORT_TYPE_OTHER)
			return connector_status_unknown;
	}
3035 3036 3037

	/* Anything else is out of spec, warn and ignore */
	DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3038
	return connector_status_disconnected;
3039 3040
}

3041
static enum drm_connector_status
Z
Zhenyu Wang 已提交
3042
ironlake_dp_detect(struct intel_dp *intel_dp)
3043
{
3044
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3045 3046
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3047 3048
	enum drm_connector_status status;

3049 3050
	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp)) {
3051
		status = intel_panel_detect(dev);
3052 3053 3054 3055
		if (status == connector_status_unknown)
			status = connector_status_connected;
		return status;
	}
3056

3057 3058 3059
	if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
		return connector_status_disconnected;

3060
	return intel_dp_detect_dpcd(intel_dp);
3061 3062
}

3063
static enum drm_connector_status
Z
Zhenyu Wang 已提交
3064
g4x_dp_detect(struct intel_dp *intel_dp)
3065
{
3066
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3067
	struct drm_i915_private *dev_priv = dev->dev_private;
3068
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3069
	uint32_t bit;
3070

3071 3072 3073 3074 3075 3076 3077 3078 3079 3080
	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp)) {
		enum drm_connector_status status;

		status = intel_panel_detect(dev);
		if (status == connector_status_unknown)
			status = connector_status_connected;
		return status;
	}

3081 3082 3083 3084 3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108
	if (IS_VALLEYVIEW(dev)) {
		switch (intel_dig_port->port) {
		case PORT_B:
			bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
			break;
		case PORT_C:
			bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
			break;
		case PORT_D:
			bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
			break;
		default:
			return connector_status_unknown;
		}
	} else {
		switch (intel_dig_port->port) {
		case PORT_B:
			bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
			break;
		case PORT_C:
			bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
			break;
		case PORT_D:
			bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
			break;
		default:
			return connector_status_unknown;
		}
3109 3110
	}

3111
	if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3112 3113
		return connector_status_disconnected;

3114
	return intel_dp_detect_dpcd(intel_dp);
Z
Zhenyu Wang 已提交
3115 3116
}

3117 3118 3119
static struct edid *
intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
{
3120
	struct intel_connector *intel_connector = to_intel_connector(connector);
3121

3122 3123 3124 3125
	/* use cached edid if we have one */
	if (intel_connector->edid) {
		/* invalid edid */
		if (IS_ERR(intel_connector->edid))
3126 3127
			return NULL;

J
Jani Nikula 已提交
3128
		return drm_edid_duplicate(intel_connector->edid);
3129
	}
3130

3131
	return drm_get_edid(connector, adapter);
3132 3133 3134 3135 3136
}

static int
intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
{
3137
	struct intel_connector *intel_connector = to_intel_connector(connector);
3138

3139 3140 3141 3142 3143 3144 3145 3146
	/* use cached edid if we have one */
	if (intel_connector->edid) {
		/* invalid edid */
		if (IS_ERR(intel_connector->edid))
			return 0;

		return intel_connector_update_modes(connector,
						    intel_connector->edid);
3147 3148
	}

3149
	return intel_ddc_get_modes(connector, adapter);
3150 3151
}

Z
Zhenyu Wang 已提交
3152 3153 3154 3155
static enum drm_connector_status
intel_dp_detect(struct drm_connector *connector, bool force)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
3156 3157
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
3158
	struct drm_device *dev = connector->dev;
3159
	struct drm_i915_private *dev_priv = dev->dev_private;
Z
Zhenyu Wang 已提交
3160
	enum drm_connector_status status;
3161
	enum intel_display_power_domain power_domain;
Z
Zhenyu Wang 已提交
3162 3163
	struct edid *edid = NULL;

3164 3165
	intel_runtime_pm_get(dev_priv);

3166 3167 3168
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);

3169 3170 3171
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		      connector->base.id, drm_get_connector_name(connector));

Z
Zhenyu Wang 已提交
3172 3173 3174 3175 3176 3177
	intel_dp->has_audio = false;

	if (HAS_PCH_SPLIT(dev))
		status = ironlake_dp_detect(intel_dp);
	else
		status = g4x_dp_detect(intel_dp);
3178

Z
Zhenyu Wang 已提交
3179
	if (status != connector_status_connected)
3180
		goto out;
Z
Zhenyu Wang 已提交
3181

3182 3183
	intel_dp_probe_oui(intel_dp);

3184 3185
	if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
		intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3186
	} else {
3187
		edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3188 3189 3190 3191
		if (edid) {
			intel_dp->has_audio = drm_detect_monitor_audio(edid);
			kfree(edid);
		}
Z
Zhenyu Wang 已提交
3192 3193
	}

3194 3195
	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3196 3197 3198
	status = connector_status_connected;

out:
3199 3200
	intel_display_power_put(dev_priv, power_domain);

3201
	intel_runtime_pm_put(dev_priv);
3202

3203
	return status;
3204 3205 3206 3207
}

static int intel_dp_get_modes(struct drm_connector *connector)
{
3208
	struct intel_dp *intel_dp = intel_attached_dp(connector);
3209 3210
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
3211
	struct intel_connector *intel_connector = to_intel_connector(connector);
3212
	struct drm_device *dev = connector->dev;
3213 3214
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum intel_display_power_domain power_domain;
3215
	int ret;
3216 3217 3218 3219

	/* We should parse the EDID data and find out if it has an audio sink
	 */

3220 3221 3222
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);

3223
	ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
3224
	intel_display_power_put(dev_priv, power_domain);
3225
	if (ret)
3226 3227
		return ret;

3228
	/* if eDP has no EDID, fall back to fixed mode */
3229
	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3230
		struct drm_display_mode *mode;
3231 3232
		mode = drm_mode_duplicate(dev,
					  intel_connector->panel.fixed_mode);
3233
		if (mode) {
3234 3235 3236 3237 3238
			drm_mode_probed_add(connector, mode);
			return 1;
		}
	}
	return 0;
3239 3240
}

3241 3242 3243 3244
static bool
intel_dp_detect_audio(struct drm_connector *connector)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
3245 3246 3247 3248 3249
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = connector->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum intel_display_power_domain power_domain;
3250 3251 3252
	struct edid *edid;
	bool has_audio = false;

3253 3254 3255
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);

3256
	edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3257 3258 3259 3260 3261
	if (edid) {
		has_audio = drm_detect_monitor_audio(edid);
		kfree(edid);
	}

3262 3263
	intel_display_power_put(dev_priv, power_domain);

3264 3265 3266
	return has_audio;
}

3267 3268 3269 3270 3271
static int
intel_dp_set_property(struct drm_connector *connector,
		      struct drm_property *property,
		      uint64_t val)
{
3272
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
3273
	struct intel_connector *intel_connector = to_intel_connector(connector);
3274 3275
	struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3276 3277
	int ret;

3278
	ret = drm_object_property_set_value(&connector->base, property, val);
3279 3280 3281
	if (ret)
		return ret;

3282
	if (property == dev_priv->force_audio_property) {
3283 3284 3285 3286
		int i = val;
		bool has_audio;

		if (i == intel_dp->force_audio)
3287 3288
			return 0;

3289
		intel_dp->force_audio = i;
3290

3291
		if (i == HDMI_AUDIO_AUTO)
3292 3293
			has_audio = intel_dp_detect_audio(connector);
		else
3294
			has_audio = (i == HDMI_AUDIO_ON);
3295 3296

		if (has_audio == intel_dp->has_audio)
3297 3298
			return 0;

3299
		intel_dp->has_audio = has_audio;
3300 3301 3302
		goto done;
	}

3303
	if (property == dev_priv->broadcast_rgb_property) {
3304 3305 3306
		bool old_auto = intel_dp->color_range_auto;
		uint32_t old_range = intel_dp->color_range;

3307 3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321
		switch (val) {
		case INTEL_BROADCAST_RGB_AUTO:
			intel_dp->color_range_auto = true;
			break;
		case INTEL_BROADCAST_RGB_FULL:
			intel_dp->color_range_auto = false;
			intel_dp->color_range = 0;
			break;
		case INTEL_BROADCAST_RGB_LIMITED:
			intel_dp->color_range_auto = false;
			intel_dp->color_range = DP_COLOR_RANGE_16_235;
			break;
		default:
			return -EINVAL;
		}
3322 3323 3324 3325 3326

		if (old_auto == intel_dp->color_range_auto &&
		    old_range == intel_dp->color_range)
			return 0;

3327 3328 3329
		goto done;
	}

3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345
	if (is_edp(intel_dp) &&
	    property == connector->dev->mode_config.scaling_mode_property) {
		if (val == DRM_MODE_SCALE_NONE) {
			DRM_DEBUG_KMS("no scaling not supported\n");
			return -EINVAL;
		}

		if (intel_connector->panel.fitting_mode == val) {
			/* the eDP scaling property is not changed */
			return 0;
		}
		intel_connector->panel.fitting_mode = val;

		goto done;
	}

3346 3347 3348
	return -EINVAL;

done:
3349 3350
	if (intel_encoder->base.crtc)
		intel_crtc_restore_mode(intel_encoder->base.crtc);
3351 3352 3353 3354

	return 0;
}

3355
static void
3356
intel_dp_connector_destroy(struct drm_connector *connector)
3357
{
3358
	struct intel_connector *intel_connector = to_intel_connector(connector);
3359

3360 3361 3362
	if (!IS_ERR_OR_NULL(intel_connector->edid))
		kfree(intel_connector->edid);

3363 3364 3365
	/* Can't call is_edp() since the encoder may have been destroyed
	 * already. */
	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3366
		intel_panel_fini(&intel_connector->panel);
3367

3368
	drm_connector_cleanup(connector);
3369
	kfree(connector);
3370 3371
}

P
Paulo Zanoni 已提交
3372
void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3373
{
3374 3375
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_dp *intel_dp = &intel_dig_port->dp;
3376
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3377

3378
	drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
3379
	drm_encoder_cleanup(encoder);
3380 3381
	if (is_edp(intel_dp)) {
		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3382
		mutex_lock(&dev->mode_config.mutex);
3383
		edp_panel_vdd_off_sync(intel_dp);
3384
		mutex_unlock(&dev->mode_config.mutex);
3385
	}
3386
	kfree(intel_dig_port);
3387 3388
}

3389
static const struct drm_connector_funcs intel_dp_connector_funcs = {
3390
	.dpms = intel_connector_dpms,
3391 3392
	.detect = intel_dp_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
3393
	.set_property = intel_dp_set_property,
3394
	.destroy = intel_dp_connector_destroy,
3395 3396 3397 3398 3399
};

static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
	.get_modes = intel_dp_get_modes,
	.mode_valid = intel_dp_mode_valid,
3400
	.best_encoder = intel_best_encoder,
3401 3402 3403
};

static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3404
	.destroy = intel_dp_encoder_destroy,
3405 3406
};

3407
static void
3408
intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3409
{
3410
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3411

3412
	intel_dp_check_link_status(intel_dp);
3413
}
3414

3415 3416
/* Return which DP Port should be selected for Transcoder DP control */
int
3417
intel_trans_dp_port_sel(struct drm_crtc *crtc)
3418 3419
{
	struct drm_device *dev = crtc->dev;
3420 3421
	struct intel_encoder *intel_encoder;
	struct intel_dp *intel_dp;
3422

3423 3424
	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		intel_dp = enc_to_intel_dp(&intel_encoder->base);
3425

3426 3427
		if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
		    intel_encoder->type == INTEL_OUTPUT_EDP)
C
Chris Wilson 已提交
3428
			return intel_dp->output_reg;
3429
	}
C
Chris Wilson 已提交
3430

3431 3432 3433
	return -1;
}

3434
/* check the VBT to see whether the eDP is on DP-D port */
3435
bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3436 3437
{
	struct drm_i915_private *dev_priv = dev->dev_private;
3438
	union child_device_config *p_child;
3439
	int i;
3440 3441 3442 3443 3444
	static const short port_mapping[] = {
		[PORT_B] = PORT_IDPB,
		[PORT_C] = PORT_IDPC,
		[PORT_D] = PORT_IDPD,
	};
3445

3446 3447 3448
	if (port == PORT_A)
		return true;

3449
	if (!dev_priv->vbt.child_dev_num)
3450 3451
		return false;

3452 3453
	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
		p_child = dev_priv->vbt.child_dev + i;
3454

3455
		if (p_child->common.dvo_port == port_mapping[port] &&
3456 3457
		    (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
		    (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3458 3459 3460 3461 3462
			return true;
	}
	return false;
}

3463 3464 3465
static void
intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
{
3466 3467
	struct intel_connector *intel_connector = to_intel_connector(connector);

3468
	intel_attach_force_audio_property(connector);
3469
	intel_attach_broadcast_rgb_property(connector);
3470
	intel_dp->color_range_auto = true;
3471 3472 3473

	if (is_edp(intel_dp)) {
		drm_mode_create_scaling_mode_property(connector->dev);
3474 3475
		drm_object_attach_property(
			&connector->base,
3476
			connector->dev->mode_config.scaling_mode_property,
3477 3478
			DRM_MODE_SCALE_ASPECT);
		intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3479
	}
3480 3481
}

3482 3483 3484 3485 3486 3487 3488
static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
{
	intel_dp->last_power_cycle = jiffies;
	intel_dp->last_power_on = jiffies;
	intel_dp->last_backlight_off = jiffies;
}

3489 3490
static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3491 3492
				    struct intel_dp *intel_dp,
				    struct edp_power_seq *out)
3493 3494 3495 3496
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct edp_power_seq cur, vbt, spec, final;
	u32 pp_on, pp_off, pp_div, pp;
3497
	int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3498 3499

	if (HAS_PCH_SPLIT(dev)) {
3500
		pp_ctrl_reg = PCH_PP_CONTROL;
3501 3502 3503 3504
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
3505 3506 3507 3508 3509 3510
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3511
	}
3512 3513 3514

	/* Workaround: Need to write PP_CONTROL with the unlock key as
	 * the very first thing. */
3515
	pp = ironlake_get_pp_control(intel_dp);
3516
	I915_WRITE(pp_ctrl_reg, pp);
3517

3518 3519 3520
	pp_on = I915_READ(pp_on_reg);
	pp_off = I915_READ(pp_off_reg);
	pp_div = I915_READ(pp_div_reg);
3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540

	/* Pull timing values out of registers */
	cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
		PANEL_POWER_UP_DELAY_SHIFT;

	cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
		PANEL_LIGHT_ON_DELAY_SHIFT;

	cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
		PANEL_LIGHT_OFF_DELAY_SHIFT;

	cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
		PANEL_POWER_DOWN_DELAY_SHIFT;

	cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
		       PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;

	DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);

3541
	vbt = dev_priv->vbt.edp_pps;
3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572 3573 3574 3575 3576 3577

	/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
	 * our hw here, which are all in 100usec. */
	spec.t1_t3 = 210 * 10;
	spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
	spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
	spec.t10 = 500 * 10;
	/* This one is special and actually in units of 100ms, but zero
	 * based in the hw (so we need to add 100 ms). But the sw vbt
	 * table multiplies it with 1000 to make it in units of 100usec,
	 * too. */
	spec.t11_t12 = (510 + 100) * 10;

	DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);

	/* Use the max of the register settings and vbt. If both are
	 * unset, fall back to the spec limits. */
#define assign_final(field)	final.field = (max(cur.field, vbt.field) == 0 ? \
				       spec.field : \
				       max(cur.field, vbt.field))
	assign_final(t1_t3);
	assign_final(t8);
	assign_final(t9);
	assign_final(t10);
	assign_final(t11_t12);
#undef assign_final

#define get_delay(field)	(DIV_ROUND_UP(final.field, 10))
	intel_dp->panel_power_up_delay = get_delay(t1_t3);
	intel_dp->backlight_on_delay = get_delay(t8);
	intel_dp->backlight_off_delay = get_delay(t9);
	intel_dp->panel_power_down_delay = get_delay(t10);
	intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
#undef get_delay

3578 3579 3580 3581 3582 3583 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594
	DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
		      intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
		      intel_dp->panel_power_cycle_delay);

	DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
		      intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);

	if (out)
		*out = final;
}

static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
					      struct intel_dp *intel_dp,
					      struct edp_power_seq *seq)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
3595 3596 3597 3598 3599 3600 3601 3602 3603
	u32 pp_on, pp_off, pp_div, port_sel = 0;
	int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
	int pp_on_reg, pp_off_reg, pp_div_reg;

	if (HAS_PCH_SPLIT(dev)) {
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
3604 3605 3606 3607 3608
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3609 3610
	}

3611 3612 3613 3614 3615 3616 3617 3618
	/*
	 * And finally store the new values in the power sequencer. The
	 * backlight delays are set to 1 because we do manual waits on them. For
	 * T8, even BSpec recommends doing it. For T9, if we don't do this,
	 * we'll end up waiting for the backlight off delay twice: once when we
	 * do the manual sleep, and once when we disable the panel and wait for
	 * the PP_STATUS bit to become zero.
	 */
3619
	pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3620 3621
		(1 << PANEL_LIGHT_ON_DELAY_SHIFT);
	pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3622
		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3623 3624
	/* Compute the divisor for the pp clock, simply match the Bspec
	 * formula. */
3625
	pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3626
	pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3627 3628 3629 3630
			<< PANEL_POWER_CYCLE_DELAY_SHIFT);

	/* Haswell doesn't have any port selection bits for the panel
	 * power sequencer any more. */
3631
	if (IS_VALLEYVIEW(dev)) {
3632 3633 3634 3635
		if (dp_to_dig_port(intel_dp)->port == PORT_B)
			port_sel = PANEL_PORT_SELECT_DPB_VLV;
		else
			port_sel = PANEL_PORT_SELECT_DPC_VLV;
3636 3637
	} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
		if (dp_to_dig_port(intel_dp)->port == PORT_A)
3638
			port_sel = PANEL_PORT_SELECT_DPA;
3639
		else
3640
			port_sel = PANEL_PORT_SELECT_DPD;
3641 3642
	}

3643 3644 3645 3646 3647
	pp_on |= port_sel;

	I915_WRITE(pp_on_reg, pp_on);
	I915_WRITE(pp_off_reg, pp_off);
	I915_WRITE(pp_div_reg, pp_div);
3648 3649

	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3650 3651 3652
		      I915_READ(pp_on_reg),
		      I915_READ(pp_off_reg),
		      I915_READ(pp_div_reg));
3653 3654
}

3655 3656 3657 3658 3659 3660 3661 3662 3663 3664 3665 3666 3667 3668 3669 3670 3671 3672 3673 3674 3675 3676 3677 3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738
void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *encoder;
	struct intel_dp *intel_dp = NULL;
	struct intel_crtc_config *config = NULL;
	struct intel_crtc *intel_crtc = NULL;
	struct intel_connector *intel_connector = dev_priv->drrs.connector;
	u32 reg, val;
	enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;

	if (refresh_rate <= 0) {
		DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
		return;
	}

	if (intel_connector == NULL) {
		DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
		return;
	}

	if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
		DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
		return;
	}

	encoder = intel_attached_encoder(&intel_connector->base);
	intel_dp = enc_to_intel_dp(&encoder->base);
	intel_crtc = encoder->new_crtc;

	if (!intel_crtc) {
		DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
		return;
	}

	config = &intel_crtc->config;

	if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
		DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
		return;
	}

	if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
		index = DRRS_LOW_RR;

	if (index == intel_dp->drrs_state.refresh_rate_type) {
		DRM_DEBUG_KMS(
			"DRRS requested for previously set RR...ignoring\n");
		return;
	}

	if (!intel_crtc->active) {
		DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
		return;
	}

	if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
		reg = PIPECONF(intel_crtc->config.cpu_transcoder);
		val = I915_READ(reg);
		if (index > DRRS_HIGH_RR) {
			val |= PIPECONF_EDP_RR_MODE_SWITCH;
			intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2);
		} else {
			val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
		}
		I915_WRITE(reg, val);
	}

	/*
	 * mutex taken to ensure that there is no race between differnt
	 * drrs calls trying to update refresh rate. This scenario may occur
	 * in future when idleness detection based DRRS in kernel and
	 * possible calls from user space to set differnt RR are made.
	 */

	mutex_lock(&intel_dp->drrs_state.mutex);

	intel_dp->drrs_state.refresh_rate_type = index;

	mutex_unlock(&intel_dp->drrs_state.mutex);

	DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
}

3739 3740 3741 3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767
static struct drm_display_mode *
intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
			struct intel_connector *intel_connector,
			struct drm_display_mode *fixed_mode)
{
	struct drm_connector *connector = &intel_connector->base;
	struct intel_dp *intel_dp = &intel_dig_port->dp;
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_display_mode *downclock_mode = NULL;

	if (INTEL_INFO(dev)->gen <= 6) {
		DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
		return NULL;
	}

	if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
		DRM_INFO("VBT doesn't support DRRS\n");
		return NULL;
	}

	downclock_mode = intel_find_panel_downclock
					(dev, fixed_mode, connector);

	if (!downclock_mode) {
		DRM_INFO("DRRS not supported\n");
		return NULL;
	}

3768 3769 3770 3771
	dev_priv->drrs.connector = intel_connector;

	mutex_init(&intel_dp->drrs_state.mutex);

3772 3773 3774 3775 3776 3777 3778
	intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;

	intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
	DRM_INFO("seamless DRRS supported for eDP panel.\n");
	return downclock_mode;
}

3779
static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3780 3781
				     struct intel_connector *intel_connector,
				     struct edp_power_seq *power_seq)
3782 3783 3784
{
	struct drm_connector *connector = &intel_connector->base;
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3785 3786
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
3787 3788
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_display_mode *fixed_mode = NULL;
3789
	struct drm_display_mode *downclock_mode = NULL;
3790 3791 3792 3793
	bool has_dpcd;
	struct drm_display_mode *scan;
	struct edid *edid;

3794 3795
	intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;

3796 3797 3798
	if (!is_edp(intel_dp))
		return true;

3799 3800 3801 3802 3803 3804 3805 3806
	/* The VDD bit needs a power domain reference, so if the bit is already
	 * enabled when we boot, grab this reference. */
	if (edp_have_panel_vdd(intel_dp)) {
		enum intel_display_power_domain power_domain;
		power_domain = intel_display_port_power_domain(intel_encoder);
		intel_display_power_get(dev_priv, power_domain);
	}

3807
	/* Cache DPCD and EDID for edp. */
3808
	intel_edp_panel_vdd_on(intel_dp);
3809
	has_dpcd = intel_dp_get_dpcd(intel_dp);
3810
	edp_panel_vdd_off(intel_dp, false);
3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823

	if (has_dpcd) {
		if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
			dev_priv->no_aux_handshake =
				intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
				DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
	} else {
		/* if this fails, presume the device is a ghost */
		DRM_INFO("failed to retrieve link info, disabling eDP\n");
		return false;
	}

	/* We now know it's not a ghost, init power sequence regs. */
3824
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
3825

3826
	mutex_lock(&dev->mode_config.mutex);
3827
	edid = drm_get_edid(connector, &intel_dp->aux.ddc);
3828 3829 3830 3831 3832 3833 3834 3835 3836 3837 3838 3839 3840 3841 3842 3843 3844 3845
	if (edid) {
		if (drm_add_edid_modes(connector, edid)) {
			drm_mode_connector_update_edid_property(connector,
								edid);
			drm_edid_to_eld(connector, edid);
		} else {
			kfree(edid);
			edid = ERR_PTR(-EINVAL);
		}
	} else {
		edid = ERR_PTR(-ENOENT);
	}
	intel_connector->edid = edid;

	/* prefer fixed mode from EDID if available */
	list_for_each_entry(scan, &connector->probed_modes, head) {
		if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
			fixed_mode = drm_mode_duplicate(dev, scan);
3846 3847 3848
			downclock_mode = intel_dp_drrs_init(
						intel_dig_port,
						intel_connector, fixed_mode);
3849 3850 3851 3852 3853 3854 3855 3856 3857 3858 3859
			break;
		}
	}

	/* fallback to VBT if available for eDP */
	if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
		fixed_mode = drm_mode_duplicate(dev,
					dev_priv->vbt.lfp_lvds_vbt_mode);
		if (fixed_mode)
			fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
	}
3860
	mutex_unlock(&dev->mode_config.mutex);
3861

3862
	intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
3863 3864 3865 3866 3867
	intel_panel_setup_backlight(connector);

	return true;
}

3868
bool
3869 3870
intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
			struct intel_connector *intel_connector)
3871
{
3872 3873 3874 3875
	struct drm_connector *connector = &intel_connector->base;
	struct intel_dp *intel_dp = &intel_dig_port->dp;
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
3876
	struct drm_i915_private *dev_priv = dev->dev_private;
3877
	enum port port = intel_dig_port->port;
3878
	struct edp_power_seq power_seq = { 0 };
3879
	int type;
3880

3881 3882 3883 3884 3885 3886 3887 3888 3889 3890
	/* intel_dp vfuncs */
	if (IS_VALLEYVIEW(dev))
		intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
		intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
	else if (HAS_PCH_SPLIT(dev))
		intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
	else
		intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;

3891 3892
	intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;

3893 3894
	/* Preserve the current hw state. */
	intel_dp->DP = I915_READ(intel_dp->output_reg);
3895
	intel_dp->attached_connector = intel_connector;
3896

3897
	if (intel_dp_is_edp(dev, port))
3898
		type = DRM_MODE_CONNECTOR_eDP;
3899 3900
	else
		type = DRM_MODE_CONNECTOR_DisplayPort;
3901

3902 3903 3904 3905 3906 3907 3908 3909
	/*
	 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
	 * for DP the encoder type can be set by the caller to
	 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
	 */
	if (type == DRM_MODE_CONNECTOR_eDP)
		intel_encoder->type = INTEL_OUTPUT_EDP;

3910 3911 3912 3913
	DRM_DEBUG_KMS("Adding %s connector on port %c\n",
			type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
			port_name(port));

3914
	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3915 3916 3917 3918 3919
	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);

	connector->interlace_allowed = true;
	connector->doublescan_allowed = 0;

3920
	INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3921
			  edp_panel_vdd_work);
3922

3923
	intel_connector_attach_encoder(intel_connector, intel_encoder);
3924 3925
	drm_sysfs_connector_add(connector);

P
Paulo Zanoni 已提交
3926
	if (HAS_DDI(dev))
3927 3928 3929
		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
	else
		intel_connector->get_hw_state = intel_connector_get_hw_state;
3930
	intel_connector->unregister = intel_dp_connector_unregister;
3931

3932
	/* Set up the hotplug pin. */
3933 3934
	switch (port) {
	case PORT_A:
3935
		intel_encoder->hpd_pin = HPD_PORT_A;
3936 3937
		break;
	case PORT_B:
3938
		intel_encoder->hpd_pin = HPD_PORT_B;
3939 3940
		break;
	case PORT_C:
3941
		intel_encoder->hpd_pin = HPD_PORT_C;
3942 3943
		break;
	case PORT_D:
3944
		intel_encoder->hpd_pin = HPD_PORT_D;
3945 3946
		break;
	default:
3947
		BUG();
3948 3949
	}

3950 3951
	if (is_edp(intel_dp)) {
		intel_dp_init_panel_power_timestamps(intel_dp);
3952
		intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3953
	}
3954

3955
	intel_dp_aux_init(intel_dp, intel_connector);
3956

R
Rodrigo Vivi 已提交
3957 3958
	intel_dp->psr_setup_done = false;

3959
	if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
3960
		drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
3961 3962 3963
		if (is_edp(intel_dp)) {
			cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
			mutex_lock(&dev->mode_config.mutex);
3964
			edp_panel_vdd_off_sync(intel_dp);
3965 3966
			mutex_unlock(&dev->mode_config.mutex);
		}
3967 3968
		drm_sysfs_connector_remove(connector);
		drm_connector_cleanup(connector);
3969
		return false;
3970
	}
3971

3972 3973
	intel_dp_add_properties(intel_dp, connector);

3974 3975 3976 3977 3978 3979 3980 3981
	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
3982 3983

	return true;
3984
}
3985 3986 3987 3988 3989 3990 3991 3992 3993

void
intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
{
	struct intel_digital_port *intel_dig_port;
	struct intel_encoder *intel_encoder;
	struct drm_encoder *encoder;
	struct intel_connector *intel_connector;

3994
	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3995 3996 3997
	if (!intel_dig_port)
		return;

3998
	intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009
	if (!intel_connector) {
		kfree(intel_dig_port);
		return;
	}

	intel_encoder = &intel_dig_port->base;
	encoder = &intel_encoder->base;

	drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
			 DRM_MODE_ENCODER_TMDS);

4010
	intel_encoder->compute_config = intel_dp_compute_config;
4011
	intel_encoder->mode_set = intel_dp_mode_set;
P
Paulo Zanoni 已提交
4012 4013
	intel_encoder->disable = intel_disable_dp;
	intel_encoder->get_hw_state = intel_dp_get_hw_state;
4014
	intel_encoder->get_config = intel_dp_get_config;
4015
	if (IS_VALLEYVIEW(dev)) {
4016
		intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
4017 4018
		intel_encoder->pre_enable = vlv_pre_enable_dp;
		intel_encoder->enable = vlv_enable_dp;
4019
		intel_encoder->post_disable = vlv_post_disable_dp;
4020
	} else {
4021 4022
		intel_encoder->pre_enable = g4x_pre_enable_dp;
		intel_encoder->enable = g4x_enable_dp;
4023
		intel_encoder->post_disable = g4x_post_disable_dp;
4024
	}
4025

4026
	intel_dig_port->port = port;
4027 4028
	intel_dig_port->dp.output_reg = output_reg;

P
Paulo Zanoni 已提交
4029
	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4030
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
4031
	intel_encoder->cloneable = 0;
4032 4033
	intel_encoder->hot_plug = intel_dp_hot_plug;

4034 4035 4036
	if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
		drm_encoder_cleanup(encoder);
		kfree(intel_dig_port);
4037
		kfree(intel_connector);
4038
	}
4039
}