intel_dp.c 109.8 KB
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/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
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#include "intel_drv.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"

#define DP_LINK_CHECK_TIMEOUT	(10 * 1000)

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struct dp_link_dpll {
	int link_bw;
	struct dpll dpll;
};

static const struct dp_link_dpll gen4_dpll[] = {
	{ DP_LINK_BW_1_62,
		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
	{ DP_LINK_BW_2_7,
		{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
};

static const struct dp_link_dpll pch_dpll[] = {
	{ DP_LINK_BW_1_62,
		{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
	{ DP_LINK_BW_2_7,
		{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
};

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static const struct dp_link_dpll vlv_dpll[] = {
	{ DP_LINK_BW_1_62,
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		{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
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	{ DP_LINK_BW_2_7,
		{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
};

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/**
 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 * @intel_dp: DP struct
 *
 * If a CPU or PCH DP output is attached to an eDP panel, this function
 * will return true, and false otherwise.
 */
static bool is_edp(struct intel_dp *intel_dp)
{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
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}

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static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
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{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.base.dev;
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}

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static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
{
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	return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
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}

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static void intel_dp_link_down(struct intel_dp *intel_dp);
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static bool _edp_panel_vdd_on(struct intel_dp *intel_dp);
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static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
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static int
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intel_dp_max_link_bw(struct intel_dp *intel_dp)
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{
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	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
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	struct drm_device *dev = intel_dp->attached_connector->base.dev;
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	switch (max_link_bw) {
	case DP_LINK_BW_1_62:
	case DP_LINK_BW_2_7:
		break;
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	case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
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		if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
		     INTEL_INFO(dev)->gen >= 8) &&
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		    intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
			max_link_bw = DP_LINK_BW_5_4;
		else
			max_link_bw = DP_LINK_BW_2_7;
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		break;
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	default:
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		WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
		     max_link_bw);
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		max_link_bw = DP_LINK_BW_1_62;
		break;
	}
	return max_link_bw;
}

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static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	u8 source_max, sink_max;

	source_max = 4;
	if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
	    (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
		source_max = 2;

	sink_max = drm_dp_max_lane_count(intel_dp->dpcd);

	return min(source_max, sink_max);
}

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/*
 * The units on the numbers in the next two are... bizarre.  Examples will
 * make it clearer; this one parallels an example in the eDP spec.
 *
 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 *
 *     270000 * 1 * 8 / 10 == 216000
 *
 * The actual data capacity of that configuration is 2.16Gbit/s, so the
 * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 * 119000.  At 18bpp that's 2142000 kilobits per second.
 *
 * Thus the strange-looking division by 10 in intel_dp_link_required, to
 * get the result in decakilobits instead of kilobits.
 */

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static int
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intel_dp_link_required(int pixel_clock, int bpp)
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{
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	return (pixel_clock * bpp + 9) / 10;
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}

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static int
intel_dp_max_data_rate(int max_link_clock, int max_lanes)
{
	return (max_link_clock * max_lanes * 8) / 10;
}

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static enum drm_mode_status
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intel_dp_mode_valid(struct drm_connector *connector,
		    struct drm_display_mode *mode)
{
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	struct intel_dp *intel_dp = intel_attached_dp(connector);
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	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
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	int target_clock = mode->clock;
	int max_rate, mode_rate, max_lanes, max_link_clock;
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	if (is_edp(intel_dp) && fixed_mode) {
		if (mode->hdisplay > fixed_mode->hdisplay)
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			return MODE_PANEL;

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		if (mode->vdisplay > fixed_mode->vdisplay)
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			return MODE_PANEL;
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		target_clock = fixed_mode->clock;
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	}

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	max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
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	max_lanes = intel_dp_max_lane_count(intel_dp);
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	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
	mode_rate = intel_dp_link_required(target_clock, 18);

	if (mode_rate > max_rate)
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		return MODE_CLOCK_HIGH;
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	if (mode->clock < 10000)
		return MODE_CLOCK_LOW;

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	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		return MODE_H_ILLEGAL;

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	return MODE_OK;
}

static uint32_t
pack_aux(uint8_t *src, int src_bytes)
{
	int	i;
	uint32_t v = 0;

	if (src_bytes > 4)
		src_bytes = 4;
	for (i = 0; i < src_bytes; i++)
		v |= ((uint32_t) src[i]) << ((3-i) * 8);
	return v;
}

static void
unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
{
	int i;
	if (dst_bytes > 4)
		dst_bytes = 4;
	for (i = 0; i < dst_bytes; i++)
		dst[i] = src >> ((3-i) * 8);
}

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/* hrawclock is 1/4 the FSB frequency */
static int
intel_hrawclk(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t clkcfg;

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	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
	if (IS_VALLEYVIEW(dev))
		return 200;

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	clkcfg = I915_READ(CLKCFG);
	switch (clkcfg & CLKCFG_FSB_MASK) {
	case CLKCFG_FSB_400:
		return 100;
	case CLKCFG_FSB_533:
		return 133;
	case CLKCFG_FSB_667:
		return 166;
	case CLKCFG_FSB_800:
		return 200;
	case CLKCFG_FSB_1067:
		return 266;
	case CLKCFG_FSB_1333:
		return 333;
	/* these two are just a guess; one of them might be right */
	case CLKCFG_FSB_1600:
	case CLKCFG_FSB_1600_ALT:
		return 400;
	default:
		return 133;
	}
}

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static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
				    struct intel_dp *intel_dp,
				    struct edp_power_seq *out);
static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
					      struct intel_dp *intel_dp,
					      struct edp_power_seq *out);

static enum pipe
vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;
	enum pipe pipe;

	/* modeset should have pipe */
	if (crtc)
		return to_intel_crtc(crtc)->pipe;

	/* init time, try to find a pipe with this port selected */
	for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
		u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
			PANEL_PORT_SELECT_MASK;
		if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
			return pipe;
		if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
			return pipe;
	}

	/* shrug */
	return PIPE_A;
}

static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

	if (HAS_PCH_SPLIT(dev))
		return PCH_PP_CONTROL;
	else
		return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
}

static u32 _pp_stat_reg(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

	if (HAS_PCH_SPLIT(dev))
		return PCH_PP_STATUS;
	else
		return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
}

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static bool edp_have_panel_power(struct intel_dp *intel_dp)
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{
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	struct drm_device *dev = intel_dp_to_dev(intel_dp);
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	struct drm_i915_private *dev_priv = dev->dev_private;

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	return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
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}

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static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
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{
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	struct drm_device *dev = intel_dp_to_dev(intel_dp);
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	struct drm_i915_private *dev_priv = dev->dev_private;

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	return !dev_priv->pm.suspended &&
	       (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
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}

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static void
intel_dp_check_edp(struct intel_dp *intel_dp)
{
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	struct drm_device *dev = intel_dp_to_dev(intel_dp);
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	if (!is_edp(intel_dp))
		return;
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	if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
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		WARN(1, "eDP powered off while attempting aux channel communication.\n");
		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
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			      I915_READ(_pp_stat_reg(intel_dp)),
			      I915_READ(_pp_ctrl_reg(intel_dp)));
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	}
}

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static uint32_t
intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
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	uint32_t status;
	bool done;

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#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
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	if (has_aux_irq)
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		done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
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					  msecs_to_jiffies_timeout(10));
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	else
		done = wait_for_atomic(C, 10) == 0;
	if (!done)
		DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
			  has_aux_irq);
#undef C

	return status;
}

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static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
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{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
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	/*
	 * The clock divider is based off the hrawclk, and would like to run at
	 * 2MHz.  So, take the hrawclk value and divide by 2 and use that
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	 */
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	return index ? 0 : intel_hrawclk(dev) / 2;
}

static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;

	if (index)
		return 0;

	if (intel_dig_port->port == PORT_A) {
		if (IS_GEN6(dev) || IS_GEN7(dev))
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			return 200; /* SNB & IVB eDP input clock at 400Mhz */
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		else
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			return 225; /* eDP input clock at 450Mhz */
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	} else {
		return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
	}
}

static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (intel_dig_port->port == PORT_A) {
		if (index)
			return 0;
		return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
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	} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
		/* Workaround for non-ULT HSW */
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		switch (index) {
		case 0: return 63;
		case 1: return 72;
		default: return 0;
		}
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	} else  {
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		return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
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	}
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}

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static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	return index ? 0 : 100;
}

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static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
				      bool has_aux_irq,
				      int send_bytes,
				      uint32_t aux_clock_divider)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	uint32_t precharge, timeout;

	if (IS_GEN6(dev))
		precharge = 3;
	else
		precharge = 5;

	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
		timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
	else
		timeout = DP_AUX_CH_CTL_TIME_OUT_400us;

	return DP_AUX_CH_CTL_SEND_BUSY |
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	       DP_AUX_CH_CTL_DONE |
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	       (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
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	       DP_AUX_CH_CTL_TIME_OUT_ERROR |
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	       timeout |
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	       DP_AUX_CH_CTL_RECEIVE_ERROR |
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	       (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
	       (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
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	       (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
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}

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static int
intel_dp_aux_ch(struct intel_dp *intel_dp,
		uint8_t *send, int send_bytes,
		uint8_t *recv, int recv_size)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
	uint32_t ch_data = ch_ctl + 4;
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	uint32_t aux_clock_divider;
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	int i, ret, recv_bytes;
	uint32_t status;
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	int try, clock = 0;
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	bool has_aux_irq = HAS_AUX_IRQ(dev);
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	bool vdd;

	vdd = _edp_panel_vdd_on(intel_dp);
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	/* dp aux is extremely sensitive to irq latency, hence request the
	 * lowest possible wakeup latency and so prevent the cpu from going into
	 * deep sleep states.
	 */
	pm_qos_update_request(&dev_priv->pm_qos, 0);

	intel_dp_check_edp(intel_dp);
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	intel_aux_display_runtime_get(dev_priv);

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	/* Try to wait for any previous AUX channel activity */
	for (try = 0; try < 3; try++) {
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		status = I915_READ_NOTRACE(ch_ctl);
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		if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
			break;
		msleep(1);
	}

	if (try == 3) {
		WARN(1, "dp_aux_ch not started status 0x%08x\n",
		     I915_READ(ch_ctl));
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		ret = -EBUSY;
		goto out;
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	}

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	/* Only 5 data registers! */
	if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
		ret = -E2BIG;
		goto out;
	}

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	while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
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		u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
							  has_aux_irq,
							  send_bytes,
							  aux_clock_divider);
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		/* Must try at least 3 times according to DP spec */
		for (try = 0; try < 5; try++) {
			/* Load the send data into the aux channel data registers */
			for (i = 0; i < send_bytes; i += 4)
				I915_WRITE(ch_data + i,
					   pack_aux(send + i, send_bytes - i));

			/* Send the command and wait for it to complete */
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			I915_WRITE(ch_ctl, send_ctl);
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			status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);

			/* Clear done status and any errors */
			I915_WRITE(ch_ctl,
				   status |
				   DP_AUX_CH_CTL_DONE |
				   DP_AUX_CH_CTL_TIME_OUT_ERROR |
				   DP_AUX_CH_CTL_RECEIVE_ERROR);

			if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
				      DP_AUX_CH_CTL_RECEIVE_ERROR))
				continue;
			if (status & DP_AUX_CH_CTL_DONE)
				break;
		}
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		if (status & DP_AUX_CH_CTL_DONE)
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			break;
	}

	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
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		DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
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		ret = -EBUSY;
		goto out;
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	}

	/* Check for timeout or receive error.
	 * Timeouts occur when the sink is not connected
	 */
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	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
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		DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
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		ret = -EIO;
		goto out;
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	}
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	/* Timeouts occur when the device isn't connected, so they're
	 * "normal" -- don't fill the kernel log with these */
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	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
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		DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
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		ret = -ETIMEDOUT;
		goto out;
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	}

	/* Unload any bytes sent back from the other side */
	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
		      DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
	if (recv_bytes > recv_size)
		recv_bytes = recv_size;
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	for (i = 0; i < recv_bytes; i += 4)
		unpack_aux(I915_READ(ch_data + i),
			   recv + i, recv_bytes - i);
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	ret = recv_bytes;
out:
	pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
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	intel_aux_display_runtime_put(dev_priv);
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589 590 591
	if (vdd)
		edp_panel_vdd_off(intel_dp, false);

592
	return ret;
593 594
}

595 596
#define BARE_ADDRESS_SIZE	3
#define HEADER_SIZE		(BARE_ADDRESS_SIZE + 1)
597 598
static ssize_t
intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
599
{
600 601 602
	struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
	uint8_t txbuf[20], rxbuf[20];
	size_t txsize, rxsize;
603 604
	int ret;

605 606 607 608
	txbuf[0] = msg->request << 4;
	txbuf[1] = msg->address >> 8;
	txbuf[2] = msg->address & 0xff;
	txbuf[3] = msg->size - 1;
609

610 611 612
	switch (msg->request & ~DP_AUX_I2C_MOT) {
	case DP_AUX_NATIVE_WRITE:
	case DP_AUX_I2C_WRITE:
613
		txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
614
		rxsize = 1;
615

616 617
		if (WARN_ON(txsize > 20))
			return -E2BIG;
618

619
		memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
620

621 622 623
		ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
		if (ret > 0) {
			msg->reply = rxbuf[0] >> 4;
624

625 626 627 628
			/* Return payload size. */
			ret = msg->size;
		}
		break;
629

630 631
	case DP_AUX_NATIVE_READ:
	case DP_AUX_I2C_READ:
632
		txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
633
		rxsize = msg->size + 1;
634

635 636
		if (WARN_ON(rxsize > 20))
			return -E2BIG;
637

638 639 640 641 642 643 644 645 646 647 648
		ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
		if (ret > 0) {
			msg->reply = rxbuf[0] >> 4;
			/*
			 * Assume happy day, and copy the data. The caller is
			 * expected to check msg->reply before touching it.
			 *
			 * Return payload size.
			 */
			ret--;
			memcpy(msg->buffer, rxbuf + 1, ret);
649
		}
650 651 652 653 654
		break;

	default:
		ret = -EINVAL;
		break;
655
	}
656

657
	return ret;
658 659
}

660 661 662 663
static void
intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
664 665
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	enum port port = intel_dig_port->port;
666
	const char *name = NULL;
667 668
	int ret;

669 670 671
	switch (port) {
	case PORT_A:
		intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
672
		name = "DPDDC-A";
673
		break;
674 675
	case PORT_B:
		intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
676
		name = "DPDDC-B";
677
		break;
678 679
	case PORT_C:
		intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
680
		name = "DPDDC-C";
681
		break;
682 683
	case PORT_D:
		intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
684
		name = "DPDDC-D";
685 686 687
		break;
	default:
		BUG();
688 689
	}

690 691
	if (!HAS_DDI(dev))
		intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
692

693
	intel_dp->aux.name = name;
694 695
	intel_dp->aux.dev = dev->dev;
	intel_dp->aux.transfer = intel_dp_aux_transfer;
696

697 698
	DRM_DEBUG_KMS("registering %s bus for %s\n", name,
		      connector->base.kdev->kobj.name);
699

700 701 702 703 704
	ret = drm_dp_aux_register_i2c_bus(&intel_dp->aux);
	if (ret < 0) {
		DRM_ERROR("drm_dp_aux_register_i2c_bus() for %s failed (%d)\n",
			  name, ret);
		return;
705
	}
706

707 708 709 710 711 712
	ret = sysfs_create_link(&connector->base.kdev->kobj,
				&intel_dp->aux.ddc.dev.kobj,
				intel_dp->aux.ddc.dev.kobj.name);
	if (ret < 0) {
		DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
		drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
713
	}
714 715
}

716 717 718 719 720 721
static void
intel_dp_connector_unregister(struct intel_connector *intel_connector)
{
	struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);

	sysfs_remove_link(&intel_connector->base.kdev->kobj,
722
			  intel_dp->aux.ddc.dev.kobj.name);
723 724 725
	intel_connector_unregister(intel_connector);
}

726 727 728 729 730
static void
intel_dp_set_clock(struct intel_encoder *encoder,
		   struct intel_crtc_config *pipe_config, int link_bw)
{
	struct drm_device *dev = encoder->base.dev;
731 732
	const struct dp_link_dpll *divisor = NULL;
	int i, count = 0;
733 734

	if (IS_G4X(dev)) {
735 736
		divisor = gen4_dpll;
		count = ARRAY_SIZE(gen4_dpll);
737 738 739
	} else if (IS_HASWELL(dev)) {
		/* Haswell has special-purpose DP DDI clocks. */
	} else if (HAS_PCH_SPLIT(dev)) {
740 741
		divisor = pch_dpll;
		count = ARRAY_SIZE(pch_dpll);
742
	} else if (IS_VALLEYVIEW(dev)) {
743 744
		divisor = vlv_dpll;
		count = ARRAY_SIZE(vlv_dpll);
745
	}
746 747 748 749 750 751 752 753 754

	if (divisor && count) {
		for (i = 0; i < count; i++) {
			if (link_bw == divisor[i].link_bw) {
				pipe_config->dpll = divisor[i].dpll;
				pipe_config->clock_set = true;
				break;
			}
		}
755 756 757
	}
}

P
Paulo Zanoni 已提交
758
bool
759 760
intel_dp_compute_config(struct intel_encoder *encoder,
			struct intel_crtc_config *pipe_config)
761
{
762
	struct drm_device *dev = encoder->base.dev;
763
	struct drm_i915_private *dev_priv = dev->dev_private;
764 765
	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
766
	enum port port = dp_to_dig_port(intel_dp)->port;
767
	struct intel_crtc *intel_crtc = encoder->new_crtc;
768
	struct intel_connector *intel_connector = intel_dp->attached_connector;
769
	int lane_count, clock;
770
	int max_lane_count = intel_dp_max_lane_count(intel_dp);
771 772
	/* Conveniently, the link BW constants become indices with a shift...*/
	int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
773
	int bpp, mode_rate;
774
	static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
775
	int link_avail, link_clock;
776

777
	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
778 779
		pipe_config->has_pch_encoder = true;

780
	pipe_config->has_dp_encoder = true;
781

782 783 784
	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
		intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
				       adjusted_mode);
785 786 787 788
		if (!HAS_PCH_SPLIT(dev))
			intel_gmch_panel_fitting(intel_crtc, pipe_config,
						 intel_connector->panel.fitting_mode);
		else
789 790
			intel_pch_panel_fitting(intel_crtc, pipe_config,
						intel_connector->panel.fitting_mode);
791 792
	}

793
	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
794 795
		return false;

796 797
	DRM_DEBUG_KMS("DP link computation with max lane count %i "
		      "max bw %02x pixel clock %iKHz\n",
798 799
		      max_lane_count, bws[max_clock],
		      adjusted_mode->crtc_clock);
800

801 802
	/* Walk through all bpp values. Luckily they're all nicely spaced with 2
	 * bpc in between. */
803
	bpp = pipe_config->pipe_bpp;
804 805
	if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
	    dev_priv->vbt.edp_bpp < bpp) {
806 807
		DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
			      dev_priv->vbt.edp_bpp);
808
		bpp = dev_priv->vbt.edp_bpp;
809
	}
810

811
	for (; bpp >= 6*3; bpp -= 2*3) {
812 813
		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
						   bpp);
814

815 816
		for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
			for (clock = 0; clock <= max_clock; clock++) {
817 818 819 820 821 822 823 824 825 826
				link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
				link_avail = intel_dp_max_data_rate(link_clock,
								    lane_count);

				if (mode_rate <= link_avail) {
					goto found;
				}
			}
		}
	}
827

828
	return false;
829

830
found:
831 832 833 834 835 836
	if (intel_dp->color_range_auto) {
		/*
		 * See:
		 * CEA-861-E - 5.1 Default Encoding Parameters
		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
		 */
837
		if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
838 839 840 841 842
			intel_dp->color_range = DP_COLOR_RANGE_16_235;
		else
			intel_dp->color_range = 0;
	}

843
	if (intel_dp->color_range)
844
		pipe_config->limited_color_range = true;
845

846 847
	intel_dp->link_bw = bws[clock];
	intel_dp->lane_count = lane_count;
848
	pipe_config->pipe_bpp = bpp;
849
	pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
850

851 852
	DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
		      intel_dp->link_bw, intel_dp->lane_count,
853
		      pipe_config->port_clock, bpp);
854 855
	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
		      mode_rate, link_avail);
856

857
	intel_link_compute_m_n(bpp, lane_count,
858 859
			       adjusted_mode->crtc_clock,
			       pipe_config->port_clock,
860
			       &pipe_config->dp_m_n);
861

862 863
	intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);

864
	return true;
865 866
}

867
static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
868
{
869 870 871
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
	struct drm_device *dev = crtc->base.dev;
872 873 874
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

875
	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
876 877 878
	dpa_ctl = I915_READ(DP_A);
	dpa_ctl &= ~DP_PLL_FREQ_MASK;

879
	if (crtc->config.port_clock == 162000) {
880 881 882 883
		/* For a long time we've carried around a ILK-DevA w/a for the
		 * 160MHz clock. If we're really unlucky, it's still required.
		 */
		DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
884
		dpa_ctl |= DP_PLL_FREQ_160MHZ;
885
		intel_dp->DP |= DP_PLL_FREQ_160MHZ;
886 887
	} else {
		dpa_ctl |= DP_PLL_FREQ_270MHZ;
888
		intel_dp->DP |= DP_PLL_FREQ_270MHZ;
889
	}
890

891 892 893 894 895 896
	I915_WRITE(DP_A, dpa_ctl);

	POSTING_READ(DP_A);
	udelay(500);
}

897
static void intel_dp_mode_set(struct intel_encoder *encoder)
898
{
899
	struct drm_device *dev = encoder->base.dev;
900
	struct drm_i915_private *dev_priv = dev->dev_private;
901
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
902
	enum port port = dp_to_dig_port(intel_dp)->port;
903 904
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
905

906
	/*
K
Keith Packard 已提交
907
	 * There are four kinds of DP registers:
908 909
	 *
	 * 	IBX PCH
K
Keith Packard 已提交
910 911
	 * 	SNB CPU
	 *	IVB CPU
912 913 914 915 916 917 918 919 920 921
	 * 	CPT PCH
	 *
	 * IBX PCH and CPU are the same for almost everything,
	 * except that the CPU DP PLL is configured in this
	 * register
	 *
	 * CPT PCH is quite different, having many bits moved
	 * to the TRANS_DP_CTL register instead. That
	 * configuration happens (oddly) in ironlake_pch_enable
	 */
922

923 924 925 926
	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
927

928 929
	/* Handle DP bits in common between all three register formats */
	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
930
	intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
931

932 933
	if (intel_dp->has_audio) {
		DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
934
				 pipe_name(crtc->pipe));
C
Chris Wilson 已提交
935
		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
936
		intel_write_eld(&encoder->base, adjusted_mode);
937
	}
938

939
	/* Split out the IBX/CPU vs CPT settings */
940

941
	if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
K
Keith Packard 已提交
942 943 944 945 946 947
		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

948
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
K
Keith Packard 已提交
949 950
			intel_dp->DP |= DP_ENHANCED_FRAMING;

951
		intel_dp->DP |= crtc->pipe << 29;
952
	} else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
953
		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
954
			intel_dp->DP |= intel_dp->color_range;
955 956 957 958 959 960 961

		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF;

962
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
963 964
			intel_dp->DP |= DP_ENHANCED_FRAMING;

965
		if (crtc->pipe == 1)
966 967 968
			intel_dp->DP |= DP_PIPEB_SELECT;
	} else {
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
969
	}
970

971
	if (port == PORT_A && !IS_VALLEYVIEW(dev))
972
		ironlake_set_pll_cpu_edp(intel_dp);
973 974
}

975 976
#define IDLE_ON_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
#define IDLE_ON_VALUE   	(PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
977

978 979
#define IDLE_OFF_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
#define IDLE_OFF_VALUE		(0     | PP_SEQUENCE_NONE | 0                     | 0)
980

981 982
#define IDLE_CYCLE_MASK		(PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
#define IDLE_CYCLE_VALUE	(0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
983

984
static void wait_panel_status(struct intel_dp *intel_dp,
985 986
				       u32 mask,
				       u32 value)
987
{
988
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
989
	struct drm_i915_private *dev_priv = dev->dev_private;
990 991
	u32 pp_stat_reg, pp_ctrl_reg;

992 993
	pp_stat_reg = _pp_stat_reg(intel_dp);
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
994

995
	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
996 997 998
			mask, value,
			I915_READ(pp_stat_reg),
			I915_READ(pp_ctrl_reg));
999

1000
	if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1001
		DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1002 1003
				I915_READ(pp_stat_reg),
				I915_READ(pp_ctrl_reg));
1004
	}
1005 1006

	DRM_DEBUG_KMS("Wait complete\n");
1007
}
1008

1009
static void wait_panel_on(struct intel_dp *intel_dp)
1010 1011
{
	DRM_DEBUG_KMS("Wait for panel power on\n");
1012
	wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1013 1014
}

1015
static void wait_panel_off(struct intel_dp *intel_dp)
1016 1017
{
	DRM_DEBUG_KMS("Wait for panel power off time\n");
1018
	wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1019 1020
}

1021
static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1022 1023
{
	DRM_DEBUG_KMS("Wait for panel power cycle\n");
1024 1025 1026 1027 1028 1029

	/* When we disable the VDD override bit last we have to do the manual
	 * wait. */
	wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
				       intel_dp->panel_power_cycle_delay);

1030
	wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1031 1032
}

1033
static void wait_backlight_on(struct intel_dp *intel_dp)
1034 1035 1036 1037 1038
{
	wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
				       intel_dp->backlight_on_delay);
}

1039
static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1040 1041 1042 1043
{
	wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
				       intel_dp->backlight_off_delay);
}
1044

1045 1046 1047 1048
/* Read the current pp_control value, unlocking the register if it
 * is locked
 */

1049
static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1050
{
1051 1052 1053
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 control;
1054

1055
	control = I915_READ(_pp_ctrl_reg(intel_dp));
1056 1057 1058
	control &= ~PANEL_UNLOCK_MASK;
	control |= PANEL_UNLOCK_REGS;
	return control;
1059 1060
}

1061
static bool _edp_panel_vdd_on(struct intel_dp *intel_dp)
1062
{
1063
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1064 1065
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
1066
	u32 pp_stat_reg, pp_ctrl_reg;
1067
	bool need_to_disable = !intel_dp->want_panel_vdd;
1068

1069
	if (!is_edp(intel_dp))
1070
		return false;
1071 1072

	intel_dp->want_panel_vdd = true;
1073

1074
	if (edp_have_panel_vdd(intel_dp))
1075
		return need_to_disable;
1076

1077 1078
	intel_runtime_pm_get(dev_priv);

1079
	DRM_DEBUG_KMS("Turning eDP VDD on\n");
1080

1081 1082
	if (!edp_have_panel_power(intel_dp))
		wait_panel_power_cycle(intel_dp);
1083

1084
	pp = ironlake_get_pp_control(intel_dp);
1085
	pp |= EDP_FORCE_VDD;
1086

1087 1088
	pp_stat_reg = _pp_stat_reg(intel_dp);
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1089 1090 1091 1092 1093

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
			I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1094 1095 1096
	/*
	 * If the panel wasn't on, delay before accessing aux channel
	 */
1097
	if (!edp_have_panel_power(intel_dp)) {
1098
		DRM_DEBUG_KMS("eDP was not running\n");
1099 1100
		msleep(intel_dp->panel_power_up_delay);
	}
1101 1102 1103 1104

	return need_to_disable;
}

1105
void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1106 1107 1108 1109 1110 1111
{
	if (is_edp(intel_dp)) {
		bool vdd = _edp_panel_vdd_on(intel_dp);

		WARN(!vdd, "eDP VDD already requested on\n");
	}
1112 1113
}

1114
static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1115
{
1116
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1117 1118
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
1119
	u32 pp_stat_reg, pp_ctrl_reg;
1120

1121 1122
	WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));

1123
	if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1124 1125
		DRM_DEBUG_KMS("Turning eDP VDD off\n");

1126
		pp = ironlake_get_pp_control(intel_dp);
1127 1128
		pp &= ~EDP_FORCE_VDD;

1129 1130
		pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
		pp_stat_reg = _pp_stat_reg(intel_dp);
1131 1132 1133

		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1134

1135 1136 1137
		/* Make sure sequencer is idle before allowing subsequent activity */
		DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
		I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
P
Paulo Zanoni 已提交
1138 1139

		if ((pp & POWER_TARGET_ON) == 0)
1140
			intel_dp->last_power_cycle = jiffies;
1141 1142

		intel_runtime_pm_put(dev_priv);
1143 1144
	}
}
1145

1146
static void edp_panel_vdd_work(struct work_struct *__work)
1147 1148 1149
{
	struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
						 struct intel_dp, panel_vdd_work);
1150
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1151

1152
	mutex_lock(&dev->mode_config.mutex);
1153
	edp_panel_vdd_off_sync(intel_dp);
1154
	mutex_unlock(&dev->mode_config.mutex);
1155 1156
}

1157
static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1158
{
1159 1160
	if (!is_edp(intel_dp))
		return;
1161

1162
	WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1163

1164 1165 1166
	intel_dp->want_panel_vdd = false;

	if (sync) {
1167
		edp_panel_vdd_off_sync(intel_dp);
1168 1169 1170 1171 1172 1173 1174 1175 1176
	} else {
		/*
		 * Queue the timer to fire a long
		 * time from now (relative to the power down delay)
		 * to keep the panel power up across a sequence of operations
		 */
		schedule_delayed_work(&intel_dp->panel_vdd_work,
				      msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
	}
1177 1178
}

1179
void intel_edp_panel_on(struct intel_dp *intel_dp)
1180
{
1181
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1182
	struct drm_i915_private *dev_priv = dev->dev_private;
1183
	u32 pp;
1184
	u32 pp_ctrl_reg;
1185

1186
	if (!is_edp(intel_dp))
1187
		return;
1188 1189 1190

	DRM_DEBUG_KMS("Turn eDP power on\n");

1191
	if (edp_have_panel_power(intel_dp)) {
1192
		DRM_DEBUG_KMS("eDP power already on\n");
1193
		return;
1194
	}
1195

1196
	wait_panel_power_cycle(intel_dp);
1197

1198
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1199
	pp = ironlake_get_pp_control(intel_dp);
1200 1201 1202
	if (IS_GEN5(dev)) {
		/* ILK workaround: disable reset around power sequence */
		pp &= ~PANEL_POWER_RESET;
1203 1204
		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1205
	}
1206

1207
	pp |= POWER_TARGET_ON;
1208 1209 1210
	if (!IS_GEN5(dev))
		pp |= PANEL_POWER_RESET;

1211 1212
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1213

1214
	wait_panel_on(intel_dp);
1215
	intel_dp->last_power_on = jiffies;
1216

1217 1218
	if (IS_GEN5(dev)) {
		pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1219 1220
		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1221
	}
1222 1223
}

1224
void intel_edp_panel_off(struct intel_dp *intel_dp)
1225
{
1226
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1227
	struct drm_i915_private *dev_priv = dev->dev_private;
1228
	u32 pp;
1229
	u32 pp_ctrl_reg;
1230

1231 1232
	if (!is_edp(intel_dp))
		return;
1233

1234
	DRM_DEBUG_KMS("Turn eDP power off\n");
1235

1236
	edp_wait_backlight_off(intel_dp);
1237

1238 1239
	WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");

1240
	pp = ironlake_get_pp_control(intel_dp);
1241 1242
	/* We need to switch off panel power _and_ force vdd, for otherwise some
	 * panels get very unhappy and cease to work. */
1243 1244
	pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
		EDP_BLC_ENABLE);
1245

1246
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1247

1248 1249
	intel_dp->want_panel_vdd = false;

1250 1251
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1252

1253
	intel_dp->last_power_cycle = jiffies;
1254
	wait_panel_off(intel_dp);
1255 1256 1257

	/* We got a reference when we enabled the VDD. */
	intel_runtime_pm_put(dev_priv);
1258 1259
}

1260
void intel_edp_backlight_on(struct intel_dp *intel_dp)
1261
{
1262 1263
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
1264 1265
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
1266
	u32 pp_ctrl_reg;
1267

1268 1269 1270
	if (!is_edp(intel_dp))
		return;

1271
	DRM_DEBUG_KMS("\n");
1272 1273 1274 1275 1276 1277
	/*
	 * If we enable the backlight right away following a panel power
	 * on, we may see slight flicker as the panel syncs with the eDP
	 * link.  So delay a bit to make sure the image is solid before
	 * allowing it to appear.
	 */
1278
	wait_backlight_on(intel_dp);
1279
	pp = ironlake_get_pp_control(intel_dp);
1280
	pp |= EDP_BLC_ENABLE;
1281

1282
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1283 1284 1285

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1286

1287
	intel_panel_enable_backlight(intel_dp->attached_connector);
1288 1289
}

1290
void intel_edp_backlight_off(struct intel_dp *intel_dp)
1291
{
1292
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1293 1294
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
1295
	u32 pp_ctrl_reg;
1296

1297 1298 1299
	if (!is_edp(intel_dp))
		return;

1300
	intel_panel_disable_backlight(intel_dp->attached_connector);
1301

1302
	DRM_DEBUG_KMS("\n");
1303
	pp = ironlake_get_pp_control(intel_dp);
1304
	pp &= ~EDP_BLC_ENABLE;
1305

1306
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1307 1308 1309

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1310
	intel_dp->last_backlight_off = jiffies;
1311
}
1312

1313
static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1314
{
1315 1316 1317
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = crtc->dev;
1318 1319 1320
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

1321 1322 1323
	assert_pipe_disabled(dev_priv,
			     to_intel_crtc(crtc)->pipe);

1324 1325
	DRM_DEBUG_KMS("\n");
	dpa_ctl = I915_READ(DP_A);
1326 1327 1328 1329 1330 1331 1332 1333 1334
	WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");

	/* We don't adjust intel_dp->DP while tearing down the link, to
	 * facilitate link retraining (e.g. after hotplug). Hence clear all
	 * enable bits here to ensure that we don't enable too much. */
	intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
	intel_dp->DP |= DP_PLL_ENABLE;
	I915_WRITE(DP_A, intel_dp->DP);
1335 1336
	POSTING_READ(DP_A);
	udelay(200);
1337 1338
}

1339
static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1340
{
1341 1342 1343
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = crtc->dev;
1344 1345 1346
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

1347 1348 1349
	assert_pipe_disabled(dev_priv,
			     to_intel_crtc(crtc)->pipe);

1350
	dpa_ctl = I915_READ(DP_A);
1351 1352 1353 1354 1355 1356 1357
	WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
	     "dp pll off, should be on\n");
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");

	/* We can't rely on the value tracked for the DP register in
	 * intel_dp->DP because link_down must not change that (otherwise link
	 * re-training will fail. */
1358
	dpa_ctl &= ~DP_PLL_ENABLE;
1359
	I915_WRITE(DP_A, dpa_ctl);
1360
	POSTING_READ(DP_A);
1361 1362 1363
	udelay(200);
}

1364
/* If the sink supports it, try to set the power state appropriately */
1365
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1366 1367 1368 1369 1370 1371 1372 1373
{
	int ret, i;

	/* Should have a valid DPCD by this point */
	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
		return;

	if (mode != DRM_MODE_DPMS_ON) {
1374 1375
		ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
					 DP_SET_POWER_D3);
1376 1377 1378 1379 1380 1381 1382 1383
		if (ret != 1)
			DRM_DEBUG_DRIVER("failed to write sink power state\n");
	} else {
		/*
		 * When turning on, we need to retry for 1ms to give the sink
		 * time to wake up.
		 */
		for (i = 0; i < 3; i++) {
1384 1385
			ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
						 DP_SET_POWER_D0);
1386 1387 1388 1389 1390 1391 1392
			if (ret == 1)
				break;
			msleep(1);
		}
	}
}

1393 1394
static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
				  enum pipe *pipe)
1395
{
1396
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1397
	enum port port = dp_to_dig_port(intel_dp)->port;
1398 1399
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1400 1401 1402 1403 1404 1405 1406 1407
	enum intel_display_power_domain power_domain;
	u32 tmp;

	power_domain = intel_display_port_power_domain(encoder);
	if (!intel_display_power_enabled(dev_priv, power_domain))
		return false;

	tmp = I915_READ(intel_dp->output_reg);
1408 1409 1410 1411

	if (!(tmp & DP_PORT_EN))
		return false;

1412
	if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1413
		*pipe = PORT_TO_PIPE_CPT(tmp);
1414
	} else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1415 1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426 1427 1428 1429 1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442
		*pipe = PORT_TO_PIPE(tmp);
	} else {
		u32 trans_sel;
		u32 trans_dp;
		int i;

		switch (intel_dp->output_reg) {
		case PCH_DP_B:
			trans_sel = TRANS_DP_PORT_SEL_B;
			break;
		case PCH_DP_C:
			trans_sel = TRANS_DP_PORT_SEL_C;
			break;
		case PCH_DP_D:
			trans_sel = TRANS_DP_PORT_SEL_D;
			break;
		default:
			return true;
		}

		for_each_pipe(i) {
			trans_dp = I915_READ(TRANS_DP_CTL(i));
			if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
				*pipe = i;
				return true;
			}
		}

1443 1444 1445
		DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
			      intel_dp->output_reg);
	}
1446

1447 1448
	return true;
}
1449

1450 1451 1452 1453 1454
static void intel_dp_get_config(struct intel_encoder *encoder,
				struct intel_crtc_config *pipe_config)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	u32 tmp, flags = 0;
1455 1456 1457 1458
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = dp_to_dig_port(intel_dp)->port;
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1459
	int dotclock;
1460

1461 1462 1463 1464 1465 1466
	if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
		tmp = I915_READ(intel_dp->output_reg);
		if (tmp & DP_SYNC_HS_HIGH)
			flags |= DRM_MODE_FLAG_PHSYNC;
		else
			flags |= DRM_MODE_FLAG_NHSYNC;
1467

1468 1469 1470 1471 1472 1473 1474 1475 1476 1477
		if (tmp & DP_SYNC_VS_HIGH)
			flags |= DRM_MODE_FLAG_PVSYNC;
		else
			flags |= DRM_MODE_FLAG_NVSYNC;
	} else {
		tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
		if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
			flags |= DRM_MODE_FLAG_PHSYNC;
		else
			flags |= DRM_MODE_FLAG_NHSYNC;
1478

1479 1480 1481 1482 1483
		if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
			flags |= DRM_MODE_FLAG_PVSYNC;
		else
			flags |= DRM_MODE_FLAG_NVSYNC;
	}
1484 1485

	pipe_config->adjusted_mode.flags |= flags;
1486

1487 1488 1489 1490
	pipe_config->has_dp_encoder = true;

	intel_dp_get_m_n(crtc, pipe_config);

1491
	if (port == PORT_A) {
1492 1493 1494 1495 1496
		if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
			pipe_config->port_clock = 162000;
		else
			pipe_config->port_clock = 270000;
	}
1497 1498 1499 1500 1501 1502 1503

	dotclock = intel_dotclock_calculate(pipe_config->port_clock,
					    &pipe_config->dp_m_n);

	if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
		ironlake_check_encoder_dotclock(pipe_config, dotclock);

1504
	pipe_config->adjusted_mode.crtc_clock = dotclock;
1505

1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522 1523 1524
	if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
	    pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
		/*
		 * This is a big fat ugly hack.
		 *
		 * Some machines in UEFI boot mode provide us a VBT that has 18
		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
		 * unknown we fail to light up. Yet the same BIOS boots up with
		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
		 * max, not what it tells us to use.
		 *
		 * Note: This will still be broken if the eDP panel is not lit
		 * up by the BIOS, and thus we can't get the mode at module
		 * load.
		 */
		DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
			      pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
		dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
	}
1525 1526
}

R
Rodrigo Vivi 已提交
1527
static bool is_edp_psr(struct drm_device *dev)
1528
{
R
Rodrigo Vivi 已提交
1529 1530 1531
	struct drm_i915_private *dev_priv = dev->dev_private;

	return dev_priv->psr.sink_support;
1532 1533
}

R
Rodrigo Vivi 已提交
1534 1535 1536 1537
static bool intel_edp_is_psr_enabled(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

1538
	if (!HAS_PSR(dev))
R
Rodrigo Vivi 已提交
1539 1540
		return false;

1541
	return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
R
Rodrigo Vivi 已提交
1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590
}

static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
				    struct edp_vsc_psr *vsc_psr)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
	u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
	uint32_t *data = (uint32_t *) vsc_psr;
	unsigned int i;

	/* As per BSPec (Pipe Video Data Island Packet), we need to disable
	   the video DIP being updated before program video DIP data buffer
	   registers for DIP being updated. */
	I915_WRITE(ctl_reg, 0);
	POSTING_READ(ctl_reg);

	for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
		if (i < sizeof(struct edp_vsc_psr))
			I915_WRITE(data_reg + i, *data++);
		else
			I915_WRITE(data_reg + i, 0);
	}

	I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
	POSTING_READ(ctl_reg);
}

static void intel_edp_psr_setup(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct edp_vsc_psr psr_vsc;

	if (intel_dp->psr_setup_done)
		return;

	/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
	memset(&psr_vsc, 0, sizeof(psr_vsc));
	psr_vsc.sdp_header.HB0 = 0;
	psr_vsc.sdp_header.HB1 = 0x7;
	psr_vsc.sdp_header.HB2 = 0x2;
	psr_vsc.sdp_header.HB3 = 0x8;
	intel_edp_psr_write_vsc(intel_dp, &psr_vsc);

	/* Avoid continuous PSR exit by masking memup and hpd */
1591
	I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1592
		   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
R
Rodrigo Vivi 已提交
1593 1594 1595 1596 1597 1598 1599 1600

	intel_dp->psr_setup_done = true;
}

static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
1601
	uint32_t aux_clock_divider;
R
Rodrigo Vivi 已提交
1602 1603 1604
	int precharge = 0x3;
	int msg_size = 5;       /* Header(4) + Message(1) */

1605 1606
	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);

R
Rodrigo Vivi 已提交
1607 1608
	/* Enable PSR in sink */
	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
1609 1610
		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
				   DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
R
Rodrigo Vivi 已提交
1611
	else
1612 1613
		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
				   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
R
Rodrigo Vivi 已提交
1614 1615

	/* Setup AUX registers */
1616 1617 1618
	I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
	I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
	I915_WRITE(EDP_PSR_AUX_CTL(dev),
R
Rodrigo Vivi 已提交
1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631
		   DP_AUX_CH_CTL_TIME_OUT_400us |
		   (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
		   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
		   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
}

static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t max_sleep_time = 0x1f;
	uint32_t idle_frames = 1;
	uint32_t val = 0x0;
B
Ben Widawsky 已提交
1632
	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
R
Rodrigo Vivi 已提交
1633 1634 1635 1636 1637 1638 1639 1640 1641

	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
		val |= EDP_PSR_LINK_STANDBY;
		val |= EDP_PSR_TP2_TP3_TIME_0us;
		val |= EDP_PSR_TP1_TIME_0us;
		val |= EDP_PSR_SKIP_AUX_EXIT;
	} else
		val |= EDP_PSR_LINK_DISABLE;

1642
	I915_WRITE(EDP_PSR_CTL(dev), val |
B
Ben Widawsky 已提交
1643
		   (IS_BROADWELL(dev) ? 0 : link_entry_time) |
R
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1644 1645 1646 1647 1648
		   max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
		   idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
		   EDP_PSR_ENABLE);
}

1649 1650 1651 1652 1653 1654 1655
static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dig_port->base.base.crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1656
	struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->primary->fb)->obj;
1657 1658
	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;

R
Rodrigo Vivi 已提交
1659 1660
	dev_priv->psr.source_ok = false;

1661
	if (!HAS_PSR(dev)) {
1662 1663 1664 1665 1666 1667 1668 1669 1670 1671
		DRM_DEBUG_KMS("PSR not supported on this platform\n");
		return false;
	}

	if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
	    (dig_port->port != PORT_A)) {
		DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
		return false;
	}

1672
	if (!i915.enable_psr) {
1673 1674 1675 1676
		DRM_DEBUG_KMS("PSR disable by flag\n");
		return false;
	}

1677 1678 1679 1680 1681 1682 1683
	crtc = dig_port->base.base.crtc;
	if (crtc == NULL) {
		DRM_DEBUG_KMS("crtc not active for PSR\n");
		return false;
	}

	intel_crtc = to_intel_crtc(crtc);
1684
	if (!intel_crtc_active(crtc)) {
1685 1686 1687 1688
		DRM_DEBUG_KMS("crtc not active for PSR\n");
		return false;
	}

1689
	obj = to_intel_framebuffer(crtc->primary->fb)->obj;
1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706
	if (obj->tiling_mode != I915_TILING_X ||
	    obj->fence_reg == I915_FENCE_REG_NONE) {
		DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
		return false;
	}

	if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
		DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
		return false;
	}

	if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
	    S3D_ENABLE) {
		DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
		return false;
	}

1707
	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1708 1709 1710 1711
		DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
		return false;
	}

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Rodrigo Vivi 已提交
1712
	dev_priv->psr.source_ok = true;
1713 1714 1715
	return true;
}

1716
static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
R
Rodrigo Vivi 已提交
1717 1718 1719
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

1720 1721
	if (!intel_edp_psr_match_conditions(intel_dp) ||
	    intel_edp_is_psr_enabled(dev))
R
Rodrigo Vivi 已提交
1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732 1733
		return;

	/* Setup PSR once */
	intel_edp_psr_setup(intel_dp);

	/* Enable PSR on the panel */
	intel_edp_psr_enable_sink(intel_dp);

	/* Enable PSR on the host */
	intel_edp_psr_enable_source(intel_dp);
}

1734 1735 1736 1737 1738 1739 1740 1741 1742
void intel_edp_psr_enable(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

	if (intel_edp_psr_match_conditions(intel_dp) &&
	    !intel_edp_is_psr_enabled(dev))
		intel_edp_psr_do_enable(intel_dp);
}

R
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1743 1744 1745 1746 1747 1748 1749 1750
void intel_edp_psr_disable(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!intel_edp_is_psr_enabled(dev))
		return;

1751 1752
	I915_WRITE(EDP_PSR_CTL(dev),
		   I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
R
Rodrigo Vivi 已提交
1753 1754

	/* Wait till PSR is idle */
1755
	if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
R
Rodrigo Vivi 已提交
1756 1757 1758 1759
		       EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
		DRM_ERROR("Timed out waiting for PSR Idle State\n");
}

1760 1761 1762 1763 1764 1765 1766 1767 1768
void intel_edp_psr_update(struct drm_device *dev)
{
	struct intel_encoder *encoder;
	struct intel_dp *intel_dp = NULL;

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
		if (encoder->type == INTEL_OUTPUT_EDP) {
			intel_dp = enc_to_intel_dp(&encoder->base);

R
Rodrigo Vivi 已提交
1769
			if (!is_edp_psr(dev))
1770 1771 1772 1773 1774 1775 1776 1777 1778 1779
				return;

			if (!intel_edp_psr_match_conditions(intel_dp))
				intel_edp_psr_disable(intel_dp);
			else
				if (!intel_edp_is_psr_enabled(dev))
					intel_edp_psr_do_enable(intel_dp);
		}
}

1780
static void intel_disable_dp(struct intel_encoder *encoder)
1781
{
1782
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1783 1784
	enum port port = dp_to_dig_port(intel_dp)->port;
	struct drm_device *dev = encoder->base.dev;
1785 1786 1787

	/* Make sure the panel is off before trying to change the mode. But also
	 * ensure that we have vdd while we switch off the panel. */
1788
	intel_edp_panel_vdd_on(intel_dp);
1789
	intel_edp_backlight_off(intel_dp);
1790
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1791
	intel_edp_panel_off(intel_dp);
1792 1793

	/* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1794
	if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1795
		intel_dp_link_down(intel_dp);
1796 1797
}

1798
static void intel_post_disable_dp(struct intel_encoder *encoder)
1799
{
1800
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1801
	enum port port = dp_to_dig_port(intel_dp)->port;
1802
	struct drm_device *dev = encoder->base.dev;
1803

1804
	if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1805
		intel_dp_link_down(intel_dp);
1806 1807
		if (!IS_VALLEYVIEW(dev))
			ironlake_edp_pll_off(intel_dp);
1808
	}
1809 1810
}

1811
static void intel_enable_dp(struct intel_encoder *encoder)
1812
{
1813 1814 1815 1816
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1817

1818 1819
	if (WARN_ON(dp_reg & DP_PORT_EN))
		return;
1820

1821
	intel_edp_panel_vdd_on(intel_dp);
1822
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1823
	intel_dp_start_link_train(intel_dp);
1824 1825
	intel_edp_panel_on(intel_dp);
	edp_panel_vdd_off(intel_dp, true);
1826
	intel_dp_complete_link_train(intel_dp);
1827
	intel_dp_stop_link_train(intel_dp);
1828
}
1829

1830 1831
static void g4x_enable_dp(struct intel_encoder *encoder)
{
1832 1833
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

1834
	intel_enable_dp(encoder);
1835
	intel_edp_backlight_on(intel_dp);
1836
}
1837

1838 1839
static void vlv_enable_dp(struct intel_encoder *encoder)
{
1840 1841
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

1842
	intel_edp_backlight_on(intel_dp);
1843 1844
}

1845
static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1846 1847 1848 1849 1850 1851 1852 1853 1854
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);

	if (dport->port == PORT_A)
		ironlake_edp_pll_on(intel_dp);
}

static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1855
{
1856
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1857
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1858
	struct drm_device *dev = encoder->base.dev;
1859
	struct drm_i915_private *dev_priv = dev->dev_private;
1860
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1861
	enum dpio_channel port = vlv_dport_to_channel(dport);
1862
	int pipe = intel_crtc->pipe;
1863
	struct edp_power_seq power_seq;
1864
	u32 val;
1865

1866
	mutex_lock(&dev_priv->dpio_lock);
1867

1868
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1869 1870 1871 1872 1873 1874
	val = 0;
	if (pipe)
		val |= (1<<21);
	else
		val &= ~(1<<21);
	val |= 0x001000c4;
1875 1876 1877
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1878

1879 1880
	mutex_unlock(&dev_priv->dpio_lock);

1881 1882 1883 1884 1885 1886
	if (is_edp(intel_dp)) {
		/* init power sequencer on this pipe and port */
		intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
		intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
							      &power_seq);
	}
1887

1888 1889
	intel_enable_dp(encoder);

1890
	vlv_wait_port_ready(dev_priv, dport);
1891 1892
}

1893
static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1894 1895 1896 1897
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1898 1899
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
1900
	enum dpio_channel port = vlv_dport_to_channel(dport);
1901
	int pipe = intel_crtc->pipe;
1902 1903

	/* Program Tx lane resets to default */
1904
	mutex_lock(&dev_priv->dpio_lock);
1905
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1906 1907
			 DPIO_PCS_TX_LANE2_RESET |
			 DPIO_PCS_TX_LANE1_RESET);
1908
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1909 1910 1911 1912 1913 1914
			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
				 DPIO_PCS_CLK_SOFT_RESET);

	/* Fix up inter-pair skew failure */
1915 1916 1917
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1918
	mutex_unlock(&dev_priv->dpio_lock);
1919 1920 1921
}

/*
1922 1923
 * Native read with retry for link status and receiver capability reads for
 * cases where the sink may still be asleep.
1924 1925 1926
 *
 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
 * supposed to retry 3 times per the spec.
1927
 */
1928 1929 1930
static ssize_t
intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
			void *buffer, size_t size)
1931
{
1932 1933
	ssize_t ret;
	int i;
1934 1935

	for (i = 0; i < 3; i++) {
1936 1937 1938
		ret = drm_dp_dpcd_read(aux, offset, buffer, size);
		if (ret == size)
			return ret;
1939 1940
		msleep(1);
	}
1941

1942
	return ret;
1943 1944 1945 1946 1947 1948 1949
}

/*
 * Fetch AUX CH registers 0x202 - 0x207 which contain
 * link status information
 */
static bool
1950
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1951
{
1952 1953 1954 1955
	return intel_dp_dpcd_read_wake(&intel_dp->aux,
				       DP_LANE0_1_STATUS,
				       link_status,
				       DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
1956 1957 1958 1959 1960 1961 1962 1963
}

/*
 * These are source-specific values; current Intel hardware supports
 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
 */

static uint8_t
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Keith Packard 已提交
1964
intel_dp_voltage_max(struct intel_dp *intel_dp)
1965
{
1966
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1967
	enum port port = dp_to_dig_port(intel_dp)->port;
K
Keith Packard 已提交
1968

1969
	if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
1970
		return DP_TRAIN_VOLTAGE_SWING_1200;
1971
	else if (IS_GEN7(dev) && port == PORT_A)
K
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1972
		return DP_TRAIN_VOLTAGE_SWING_800;
1973
	else if (HAS_PCH_CPT(dev) && port != PORT_A)
K
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1974 1975 1976 1977 1978 1979 1980 1981
		return DP_TRAIN_VOLTAGE_SWING_1200;
	else
		return DP_TRAIN_VOLTAGE_SWING_800;
}

static uint8_t
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
{
1982
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1983
	enum port port = dp_to_dig_port(intel_dp)->port;
K
Keith Packard 已提交
1984

1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996
	if (IS_BROADWELL(dev)) {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
	} else if (IS_HASWELL(dev)) {
1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_9_5;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019
	} else if (IS_VALLEYVIEW(dev)) {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_9_5;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
2020
	} else if (IS_GEN7(dev) && port == PORT_A) {
K
Keith Packard 已提交
2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_600:
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
	} else {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
2042 2043 2044
	}
}

2045 2046 2047 2048 2049
static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2050 2051
	struct intel_crtc *intel_crtc =
		to_intel_crtc(dport->base.base.crtc);
2052 2053 2054
	unsigned long demph_reg_value, preemph_reg_value,
		uniqtranscale_reg_value;
	uint8_t train_set = intel_dp->train_set[0];
2055
	enum dpio_channel port = vlv_dport_to_channel(dport);
2056
	int pipe = intel_crtc->pipe;
2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130

	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
	case DP_TRAIN_PRE_EMPHASIS_0:
		preemph_reg_value = 0x0004000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x552AB83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5548B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_800:
			demph_reg_value = 0x2B245555;
			uniqtranscale_reg_value = 0x5560B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_1200:
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x5598DA3A;
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_3_5:
		preemph_reg_value = 0x0002000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5552B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			demph_reg_value = 0x2B404848;
			uniqtranscale_reg_value = 0x5580B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_800:
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_6:
		preemph_reg_value = 0x0000000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x2B305555;
			uniqtranscale_reg_value = 0x5570B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			demph_reg_value = 0x2B2B4040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_9_5:
		preemph_reg_value = 0x0006000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x1B405555;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	default:
		return 0;
	}

2131
	mutex_lock(&dev_priv->dpio_lock);
2132 2133 2134
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2135
			 uniqtranscale_reg_value);
2136 2137 2138 2139
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2140
	mutex_unlock(&dev_priv->dpio_lock);
2141 2142 2143 2144

	return 0;
}

2145
static void
J
Jani Nikula 已提交
2146 2147
intel_get_adjust_train(struct intel_dp *intel_dp,
		       const uint8_t link_status[DP_LINK_STATUS_SIZE])
2148 2149 2150 2151
{
	uint8_t v = 0;
	uint8_t p = 0;
	int lane;
K
Keith Packard 已提交
2152 2153
	uint8_t voltage_max;
	uint8_t preemph_max;
2154

2155
	for (lane = 0; lane < intel_dp->lane_count; lane++) {
2156 2157
		uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
		uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2158 2159 2160 2161 2162 2163 2164

		if (this_v > v)
			v = this_v;
		if (this_p > p)
			p = this_p;
	}

K
Keith Packard 已提交
2165
	voltage_max = intel_dp_voltage_max(intel_dp);
2166 2167
	if (v >= voltage_max)
		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2168

K
Keith Packard 已提交
2169 2170 2171
	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
	if (p >= preemph_max)
		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2172 2173

	for (lane = 0; lane < 4; lane++)
2174
		intel_dp->train_set[lane] = v | p;
2175 2176 2177
}

static uint32_t
2178
intel_gen4_signal_levels(uint8_t train_set)
2179
{
2180
	uint32_t	signal_levels = 0;
2181

2182
	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196
	case DP_TRAIN_VOLTAGE_SWING_400:
	default:
		signal_levels |= DP_VOLTAGE_0_4;
		break;
	case DP_TRAIN_VOLTAGE_SWING_600:
		signal_levels |= DP_VOLTAGE_0_6;
		break;
	case DP_TRAIN_VOLTAGE_SWING_800:
		signal_levels |= DP_VOLTAGE_0_8;
		break;
	case DP_TRAIN_VOLTAGE_SWING_1200:
		signal_levels |= DP_VOLTAGE_1_2;
		break;
	}
2197
	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209 2210 2211 2212 2213 2214
	case DP_TRAIN_PRE_EMPHASIS_0:
	default:
		signal_levels |= DP_PRE_EMPHASIS_0;
		break;
	case DP_TRAIN_PRE_EMPHASIS_3_5:
		signal_levels |= DP_PRE_EMPHASIS_3_5;
		break;
	case DP_TRAIN_PRE_EMPHASIS_6:
		signal_levels |= DP_PRE_EMPHASIS_6;
		break;
	case DP_TRAIN_PRE_EMPHASIS_9_5:
		signal_levels |= DP_PRE_EMPHASIS_9_5;
		break;
	}
	return signal_levels;
}

2215 2216 2217 2218
/* Gen6's DP voltage swing and pre-emphasis control */
static uint32_t
intel_gen6_edp_signal_levels(uint8_t train_set)
{
2219 2220 2221
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
2222
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2223 2224 2225 2226
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2227
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2228 2229
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
		return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2230
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2231 2232
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2233
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2234 2235
	case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2236
	default:
2237 2238 2239
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2240 2241 2242
	}
}

K
Keith Packard 已提交
2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273
/* Gen7's DP voltage swing and pre-emphasis control */
static uint32_t
intel_gen7_edp_signal_levels(uint8_t train_set)
{
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_400MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
		return EDP_LINK_TRAIN_400MV_6DB_IVB;

	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_600MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_600MV_3_5DB_IVB;

	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_800MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_800MV_3_5DB_IVB;

	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_500MV_0DB_IVB;
	}
}

2274 2275
/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
static uint32_t
2276
intel_hsw_signal_levels(uint8_t train_set)
2277
{
2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_400MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_400MV_3_5DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
		return DDI_BUF_EMP_400MV_6DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
		return DDI_BUF_EMP_400MV_9_5DB_HSW;
2289

2290 2291 2292 2293 2294 2295
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_600MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_600MV_3_5DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
		return DDI_BUF_EMP_600MV_6DB_HSW;
2296

2297 2298 2299 2300 2301 2302 2303 2304
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_800MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_800MV_3_5DB_HSW;
	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return DDI_BUF_EMP_400MV_0DB_HSW;
2305 2306 2307
	}
}

2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342
static uint32_t
intel_bdw_signal_levels(uint8_t train_set)
{
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_400MV_0DB_BDW;	/* Sel0 */
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_400MV_3_5DB_BDW;	/* Sel1 */
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
		return DDI_BUF_EMP_400MV_6DB_BDW;	/* Sel2 */

	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_600MV_0DB_BDW;	/* Sel3 */
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_600MV_3_5DB_BDW;	/* Sel4 */
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
		return DDI_BUF_EMP_600MV_6DB_BDW;	/* Sel5 */

	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_800MV_0DB_BDW;	/* Sel6 */
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_800MV_3_5DB_BDW;	/* Sel7 */

	case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_1200MV_0DB_BDW;	/* Sel8 */

	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return DDI_BUF_EMP_400MV_0DB_BDW;	/* Sel0 */
	}
}

2343 2344 2345 2346 2347
/* Properly updates "DP" with the correct signal levels. */
static void
intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2348
	enum port port = intel_dig_port->port;
2349 2350 2351 2352
	struct drm_device *dev = intel_dig_port->base.base.dev;
	uint32_t signal_levels, mask;
	uint8_t train_set = intel_dp->train_set[0];

2353 2354 2355 2356
	if (IS_BROADWELL(dev)) {
		signal_levels = intel_bdw_signal_levels(train_set);
		mask = DDI_BUF_EMP_MASK;
	} else if (IS_HASWELL(dev)) {
2357 2358
		signal_levels = intel_hsw_signal_levels(train_set);
		mask = DDI_BUF_EMP_MASK;
2359 2360 2361
	} else if (IS_VALLEYVIEW(dev)) {
		signal_levels = intel_vlv_signal_levels(intel_dp);
		mask = 0;
2362
	} else if (IS_GEN7(dev) && port == PORT_A) {
2363 2364
		signal_levels = intel_gen7_edp_signal_levels(train_set);
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2365
	} else if (IS_GEN6(dev) && port == PORT_A) {
2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377
		signal_levels = intel_gen6_edp_signal_levels(train_set);
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
	} else {
		signal_levels = intel_gen4_signal_levels(train_set);
		mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
	}

	DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);

	*DP = (*DP & ~mask) | signal_levels;
}

2378
static bool
C
Chris Wilson 已提交
2379
intel_dp_set_link_train(struct intel_dp *intel_dp,
2380
			uint32_t *DP,
2381
			uint8_t dp_train_pat)
2382
{
2383 2384
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
2385
	struct drm_i915_private *dev_priv = dev->dev_private;
2386
	enum port port = intel_dig_port->port;
2387 2388
	uint8_t buf[sizeof(intel_dp->train_set) + 1];
	int ret, len;
2389

2390
	if (HAS_DDI(dev)) {
2391
		uint32_t temp = I915_READ(DP_TP_CTL(port));
2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413

		if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
			temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
		else
			temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;

		temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;

			break;
		case DP_TRAINING_PATTERN_1:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
			break;
		case DP_TRAINING_PATTERN_2:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
			break;
		case DP_TRAINING_PATTERN_3:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
			break;
		}
2414
		I915_WRITE(DP_TP_CTL(port), temp);
2415

2416
	} else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2417
		*DP &= ~DP_LINK_TRAIN_MASK_CPT;
2418 2419 2420

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
2421
			*DP |= DP_LINK_TRAIN_OFF_CPT;
2422 2423
			break;
		case DP_TRAINING_PATTERN_1:
2424
			*DP |= DP_LINK_TRAIN_PAT_1_CPT;
2425 2426
			break;
		case DP_TRAINING_PATTERN_2:
2427
			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
2428 2429 2430
			break;
		case DP_TRAINING_PATTERN_3:
			DRM_ERROR("DP training pattern 3 not supported\n");
2431
			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
2432 2433 2434 2435
			break;
		}

	} else {
2436
		*DP &= ~DP_LINK_TRAIN_MASK;
2437 2438 2439

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
2440
			*DP |= DP_LINK_TRAIN_OFF;
2441 2442
			break;
		case DP_TRAINING_PATTERN_1:
2443
			*DP |= DP_LINK_TRAIN_PAT_1;
2444 2445
			break;
		case DP_TRAINING_PATTERN_2:
2446
			*DP |= DP_LINK_TRAIN_PAT_2;
2447 2448 2449
			break;
		case DP_TRAINING_PATTERN_3:
			DRM_ERROR("DP training pattern 3 not supported\n");
2450
			*DP |= DP_LINK_TRAIN_PAT_2;
2451 2452 2453 2454
			break;
		}
	}

2455
	I915_WRITE(intel_dp->output_reg, *DP);
C
Chris Wilson 已提交
2456
	POSTING_READ(intel_dp->output_reg);
2457

2458 2459
	buf[0] = dp_train_pat;
	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2460
	    DP_TRAINING_PATTERN_DISABLE) {
2461 2462 2463 2464 2465 2466
		/* don't write DP_TRAINING_LANEx_SET on disable */
		len = 1;
	} else {
		/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
		memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
		len = intel_dp->lane_count + 1;
2467
	}
2468

2469 2470
	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
				buf, len);
2471 2472

	return ret == len;
2473 2474
}

2475 2476 2477 2478
static bool
intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
			uint8_t dp_train_pat)
{
2479
	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2480 2481 2482 2483 2484 2485
	intel_dp_set_signal_levels(intel_dp, DP);
	return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
}

static bool
intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
J
Jani Nikula 已提交
2486
			   const uint8_t link_status[DP_LINK_STATUS_SIZE])
2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	intel_get_adjust_train(intel_dp, link_status);
	intel_dp_set_signal_levels(intel_dp, DP);

	I915_WRITE(intel_dp->output_reg, *DP);
	POSTING_READ(intel_dp->output_reg);

2499 2500
	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
				intel_dp->train_set, intel_dp->lane_count);
2501 2502 2503 2504

	return ret == intel_dp->lane_count;
}

2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535
static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;
	uint32_t val;

	if (!HAS_DDI(dev))
		return;

	val = I915_READ(DP_TP_CTL(port));
	val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
	val |= DP_TP_CTL_LINK_TRAIN_IDLE;
	I915_WRITE(DP_TP_CTL(port), val);

	/*
	 * On PORT_A we can have only eDP in SST mode. There the only reason
	 * we need to set idle transmission mode is to work around a HW issue
	 * where we enable the pipe while not in idle link-training mode.
	 * In this case there is requirement to wait for a minimum number of
	 * idle patterns to be sent.
	 */
	if (port == PORT_A)
		return;

	if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
		     1))
		DRM_ERROR("Timed out waiting for DP idle patterns\n");
}

2536
/* Enable corresponding port and start training pattern 1 */
2537
void
2538
intel_dp_start_link_train(struct intel_dp *intel_dp)
2539
{
2540
	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2541
	struct drm_device *dev = encoder->dev;
2542 2543
	int i;
	uint8_t voltage;
2544
	int voltage_tries, loop_tries;
C
Chris Wilson 已提交
2545
	uint32_t DP = intel_dp->DP;
2546
	uint8_t link_config[2];
2547

P
Paulo Zanoni 已提交
2548
	if (HAS_DDI(dev))
2549 2550
		intel_ddi_prepare_link_retrain(encoder);

2551
	/* Write the link configuration data */
2552 2553 2554 2555
	link_config[0] = intel_dp->link_bw;
	link_config[1] = intel_dp->lane_count;
	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2556
	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
2557 2558 2559

	link_config[0] = 0;
	link_config[1] = DP_SET_ANSI_8B10B;
2560
	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
2561 2562

	DP |= DP_PORT_EN;
K
Keith Packard 已提交
2563

2564 2565 2566 2567 2568 2569 2570 2571
	/* clock recovery */
	if (!intel_dp_reset_link_train(intel_dp, &DP,
				       DP_TRAINING_PATTERN_1 |
				       DP_LINK_SCRAMBLING_DISABLE)) {
		DRM_ERROR("failed to enable link training\n");
		return;
	}

2572
	voltage = 0xff;
2573 2574
	voltage_tries = 0;
	loop_tries = 0;
2575
	for (;;) {
2576
		uint8_t link_status[DP_LINK_STATUS_SIZE];
2577

2578
		drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2579 2580
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
2581
			break;
2582
		}
2583

2584
		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2585
			DRM_DEBUG_KMS("clock recovery OK\n");
2586 2587 2588 2589 2590 2591
			break;
		}

		/* Check to see if we've tried the max voltage */
		for (i = 0; i < intel_dp->lane_count; i++)
			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2592
				break;
2593
		if (i == intel_dp->lane_count) {
2594 2595
			++loop_tries;
			if (loop_tries == 5) {
2596
				DRM_ERROR("too many full retries, give up\n");
2597 2598
				break;
			}
2599 2600 2601
			intel_dp_reset_link_train(intel_dp, &DP,
						  DP_TRAINING_PATTERN_1 |
						  DP_LINK_SCRAMBLING_DISABLE);
2602 2603 2604
			voltage_tries = 0;
			continue;
		}
2605

2606
		/* Check to see if we've tried the same voltage 5 times */
2607
		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2608
			++voltage_tries;
2609
			if (voltage_tries == 5) {
2610
				DRM_ERROR("too many voltage retries, give up\n");
2611 2612 2613 2614 2615
				break;
			}
		} else
			voltage_tries = 0;
		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2616

2617 2618 2619 2620 2621
		/* Update training set as requested by target */
		if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
			DRM_ERROR("failed to update link training\n");
			break;
		}
2622 2623
	}

2624 2625 2626
	intel_dp->DP = DP;
}

2627
void
2628 2629 2630
intel_dp_complete_link_train(struct intel_dp *intel_dp)
{
	bool channel_eq = false;
2631
	int tries, cr_tries;
2632
	uint32_t DP = intel_dp->DP;
2633 2634 2635 2636 2637
	uint32_t training_pattern = DP_TRAINING_PATTERN_2;

	/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
	if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
		training_pattern = DP_TRAINING_PATTERN_3;
2638

2639
	/* channel equalization */
2640
	if (!intel_dp_set_link_train(intel_dp, &DP,
2641
				     training_pattern |
2642 2643 2644 2645 2646
				     DP_LINK_SCRAMBLING_DISABLE)) {
		DRM_ERROR("failed to start channel equalization\n");
		return;
	}

2647
	tries = 0;
2648
	cr_tries = 0;
2649 2650
	channel_eq = false;
	for (;;) {
2651
		uint8_t link_status[DP_LINK_STATUS_SIZE];
2652

2653 2654 2655 2656 2657
		if (cr_tries > 5) {
			DRM_ERROR("failed to train DP, aborting\n");
			break;
		}

2658
		drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2659 2660
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
2661
			break;
2662
		}
2663

2664
		/* Make sure clock is still ok */
2665
		if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2666
			intel_dp_start_link_train(intel_dp);
2667
			intel_dp_set_link_train(intel_dp, &DP,
2668
						training_pattern |
2669
						DP_LINK_SCRAMBLING_DISABLE);
2670 2671 2672 2673
			cr_tries++;
			continue;
		}

2674
		if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2675 2676 2677
			channel_eq = true;
			break;
		}
2678

2679 2680 2681 2682
		/* Try 5 times, then try clock recovery if that fails */
		if (tries > 5) {
			intel_dp_link_down(intel_dp);
			intel_dp_start_link_train(intel_dp);
2683
			intel_dp_set_link_train(intel_dp, &DP,
2684
						training_pattern |
2685
						DP_LINK_SCRAMBLING_DISABLE);
2686 2687 2688 2689
			tries = 0;
			cr_tries++;
			continue;
		}
2690

2691 2692 2693 2694 2695
		/* Update training set as requested by target */
		if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
			DRM_ERROR("failed to update link training\n");
			break;
		}
2696
		++tries;
2697
	}
2698

2699 2700 2701 2702
	intel_dp_set_idle_link_train(intel_dp);

	intel_dp->DP = DP;

2703
	if (channel_eq)
M
Masanari Iida 已提交
2704
		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2705

2706 2707 2708 2709
}

void intel_dp_stop_link_train(struct intel_dp *intel_dp)
{
2710
	intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2711
				DP_TRAINING_PATTERN_DISABLE);
2712 2713 2714
}

static void
C
Chris Wilson 已提交
2715
intel_dp_link_down(struct intel_dp *intel_dp)
2716
{
2717
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2718
	enum port port = intel_dig_port->port;
2719
	struct drm_device *dev = intel_dig_port->base.base.dev;
2720
	struct drm_i915_private *dev_priv = dev->dev_private;
2721 2722
	struct intel_crtc *intel_crtc =
		to_intel_crtc(intel_dig_port->base.base.crtc);
C
Chris Wilson 已提交
2723
	uint32_t DP = intel_dp->DP;
2724

2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739
	/*
	 * DDI code has a strict mode set sequence and we should try to respect
	 * it, otherwise we might hang the machine in many different ways. So we
	 * really should be disabling the port only on a complete crtc_disable
	 * sequence. This function is just called under two conditions on DDI
	 * code:
	 * - Link train failed while doing crtc_enable, and on this case we
	 *   really should respect the mode set sequence and wait for a
	 *   crtc_disable.
	 * - Someone turned the monitor off and intel_dp_check_link_status
	 *   called us. We don't need to disable the whole port on this case, so
	 *   when someone turns the monitor on again,
	 *   intel_ddi_prepare_link_retrain will take care of redoing the link
	 *   train.
	 */
P
Paulo Zanoni 已提交
2740
	if (HAS_DDI(dev))
2741 2742
		return;

2743
	if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2744 2745
		return;

2746
	DRM_DEBUG_KMS("\n");
2747

2748
	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2749
		DP &= ~DP_LINK_TRAIN_MASK_CPT;
C
Chris Wilson 已提交
2750
		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2751 2752
	} else {
		DP &= ~DP_LINK_TRAIN_MASK;
C
Chris Wilson 已提交
2753
		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2754
	}
2755
	POSTING_READ(intel_dp->output_reg);
2756

2757 2758
	/* We don't really know why we're doing this */
	intel_wait_for_vblank(dev, intel_crtc->pipe);
2759

2760
	if (HAS_PCH_IBX(dev) &&
2761
	    I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2762
		struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2763

2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777
		/* Hardware workaround: leaving our transcoder select
		 * set to transcoder B while it's off will prevent the
		 * corresponding HDMI output on transcoder A.
		 *
		 * Combine this with another hardware workaround:
		 * transcoder select bit can only be cleared while the
		 * port is enabled.
		 */
		DP &= ~DP_PIPEB_SELECT;
		I915_WRITE(intel_dp->output_reg, DP);

		/* Changes to enable or select take place the vblank
		 * after being written.
		 */
2778 2779 2780 2781
		if (WARN_ON(crtc == NULL)) {
			/* We should never try to disable a port without a crtc
			 * attached. For paranoia keep the code around for a
			 * bit. */
2782 2783 2784
			POSTING_READ(intel_dp->output_reg);
			msleep(50);
		} else
2785
			intel_wait_for_vblank(dev, intel_crtc->pipe);
2786 2787
	}

2788
	DP &= ~DP_AUDIO_OUTPUT_ENABLE;
C
Chris Wilson 已提交
2789 2790
	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);
2791
	msleep(intel_dp->panel_power_down_delay);
2792 2793
}

2794 2795
static bool
intel_dp_get_dpcd(struct intel_dp *intel_dp)
2796
{
R
Rodrigo Vivi 已提交
2797 2798 2799 2800
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

2801 2802
	char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];

2803 2804
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
				    sizeof(intel_dp->dpcd)) < 0)
2805
		return false; /* aux transfer failed */
2806

2807 2808 2809 2810
	hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
			   32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
	DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);

2811 2812 2813
	if (intel_dp->dpcd[DP_DPCD_REV] == 0)
		return false; /* DPCD not present */

2814 2815
	/* Check if the panel supports PSR */
	memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2816
	if (is_edp(intel_dp)) {
2817 2818 2819
		intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
					intel_dp->psr_dpcd,
					sizeof(intel_dp->psr_dpcd));
R
Rodrigo Vivi 已提交
2820 2821
		if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
			dev_priv->psr.sink_support = true;
2822
			DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
R
Rodrigo Vivi 已提交
2823
		}
2824 2825
	}

2826 2827 2828 2829 2830 2831 2832 2833
	/* Training Pattern 3 support */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
	    intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
		intel_dp->use_tps3 = true;
		DRM_DEBUG_KMS("Displayport TPS3 supported");
	} else
		intel_dp->use_tps3 = false;

2834 2835 2836 2837 2838 2839 2840
	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
	      DP_DWN_STRM_PORT_PRESENT))
		return true; /* native DP sink */

	if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
		return true; /* no per-port downstream info */

2841 2842 2843
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
				    intel_dp->downstream_ports,
				    DP_MAX_DOWNSTREAM_PORTS) < 0)
2844 2845 2846
		return false; /* downstream port status fetch failed */

	return true;
2847 2848
}

2849 2850 2851 2852 2853 2854 2855 2856
static void
intel_dp_probe_oui(struct intel_dp *intel_dp)
{
	u8 buf[3];

	if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
		return;

2857
	intel_edp_panel_vdd_on(intel_dp);
D
Daniel Vetter 已提交
2858

2859
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
2860 2861 2862
		DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);

2863
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
2864 2865
		DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);
D
Daniel Vetter 已提交
2866

2867
	edp_panel_vdd_off(intel_dp, false);
2868 2869
}

2870 2871 2872 2873 2874 2875 2876 2877
int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(intel_dig_port->base.base.crtc);
	u8 buf[1];

2878
	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, buf) < 0)
2879 2880 2881 2882 2883
		return -EAGAIN;

	if (!(buf[0] & DP_TEST_CRC_SUPPORTED))
		return -ENOTTY;

2884 2885
	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
			       DP_TEST_SINK_START) < 0)
2886 2887 2888 2889 2890 2891
		return -EAGAIN;

	/* Wait 2 vblanks to be sure we will have the correct CRC value */
	intel_wait_for_vblank(dev, intel_crtc->pipe);
	intel_wait_for_vblank(dev, intel_crtc->pipe);

2892
	if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
2893 2894
		return -EAGAIN;

2895
	drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK, 0);
2896 2897 2898
	return 0;
}

2899 2900 2901
static bool
intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
2902 2903 2904
	return intel_dp_dpcd_read_wake(&intel_dp->aux,
				       DP_DEVICE_SERVICE_IRQ_VECTOR,
				       sink_irq_vector, 1) == 1;
2905 2906 2907 2908 2909 2910
}

static void
intel_dp_handle_test_request(struct intel_dp *intel_dp)
{
	/* NAK by default */
2911
	drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
2912 2913
}

2914 2915 2916 2917 2918 2919 2920 2921 2922
/*
 * According to DP spec
 * 5.1.2:
 *  1. Read DPCD
 *  2. Configure link according to Receiver Capabilities
 *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
 *  4. Check link status on receipt of hot-plug interrupt
 */

P
Paulo Zanoni 已提交
2923
void
C
Chris Wilson 已提交
2924
intel_dp_check_link_status(struct intel_dp *intel_dp)
2925
{
2926
	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2927
	u8 sink_irq_vector;
2928
	u8 link_status[DP_LINK_STATUS_SIZE];
2929

2930
	if (!intel_encoder->connectors_active)
2931
		return;
2932

2933
	if (WARN_ON(!intel_encoder->base.crtc))
2934 2935
		return;

2936
	/* Try to read receiver status if the link appears to be up */
2937
	if (!intel_dp_get_link_status(intel_dp, link_status)) {
2938 2939 2940
		return;
	}

2941
	/* Now read the DPCD to see if it's actually running */
2942
	if (!intel_dp_get_dpcd(intel_dp)) {
2943 2944 2945
		return;
	}

2946 2947 2948 2949
	/* Try to read the source of the interrupt */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
		/* Clear interrupt source */
2950 2951 2952
		drm_dp_dpcd_writeb(&intel_dp->aux,
				   DP_DEVICE_SERVICE_IRQ_VECTOR,
				   sink_irq_vector);
2953 2954 2955 2956 2957 2958 2959

		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
			intel_dp_handle_test_request(intel_dp);
		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
	}

2960
	if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2961
		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2962
			      drm_get_encoder_name(&intel_encoder->base));
2963 2964
		intel_dp_start_link_train(intel_dp);
		intel_dp_complete_link_train(intel_dp);
2965
		intel_dp_stop_link_train(intel_dp);
2966
	}
2967 2968
}

2969
/* XXX this is probably wrong for multiple downstream ports */
2970
static enum drm_connector_status
2971
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2972
{
2973 2974 2975 2976 2977 2978 2979 2980
	uint8_t *dpcd = intel_dp->dpcd;
	uint8_t type;

	if (!intel_dp_get_dpcd(intel_dp))
		return connector_status_disconnected;

	/* if there's no downstream port, we're done */
	if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2981
		return connector_status_connected;
2982 2983

	/* If we're HPD-aware, SINK_COUNT changes dynamically */
2984 2985
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
2986
		uint8_t reg;
2987 2988 2989

		if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
					    &reg, 1) < 0)
2990
			return connector_status_unknown;
2991

2992 2993
		return DP_GET_SINK_COUNT(reg) ? connector_status_connected
					      : connector_status_disconnected;
2994 2995 2996
	}

	/* If no HPD, poke DDC gently */
2997
	if (drm_probe_ddc(&intel_dp->aux.ddc))
2998
		return connector_status_connected;
2999 3000

	/* Well we tried, say unknown for unreliable port types */
3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
		type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
		if (type == DP_DS_PORT_TYPE_VGA ||
		    type == DP_DS_PORT_TYPE_NON_EDID)
			return connector_status_unknown;
	} else {
		type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
			DP_DWN_STRM_PORT_TYPE_MASK;
		if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
		    type == DP_DWN_STRM_PORT_TYPE_OTHER)
			return connector_status_unknown;
	}
3013 3014 3015

	/* Anything else is out of spec, warn and ignore */
	DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
3016
	return connector_status_disconnected;
3017 3018
}

3019
static enum drm_connector_status
Z
Zhenyu Wang 已提交
3020
ironlake_dp_detect(struct intel_dp *intel_dp)
3021
{
3022
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3023 3024
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3025 3026
	enum drm_connector_status status;

3027 3028
	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp)) {
3029
		status = intel_panel_detect(dev);
3030 3031 3032 3033
		if (status == connector_status_unknown)
			status = connector_status_connected;
		return status;
	}
3034

3035 3036 3037
	if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
		return connector_status_disconnected;

3038
	return intel_dp_detect_dpcd(intel_dp);
3039 3040
}

3041
static enum drm_connector_status
Z
Zhenyu Wang 已提交
3042
g4x_dp_detect(struct intel_dp *intel_dp)
3043
{
3044
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3045
	struct drm_i915_private *dev_priv = dev->dev_private;
3046
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3047
	uint32_t bit;
3048

3049 3050 3051 3052 3053 3054 3055 3056 3057 3058
	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp)) {
		enum drm_connector_status status;

		status = intel_panel_detect(dev);
		if (status == connector_status_unknown)
			status = connector_status_connected;
		return status;
	}

3059 3060 3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086
	if (IS_VALLEYVIEW(dev)) {
		switch (intel_dig_port->port) {
		case PORT_B:
			bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
			break;
		case PORT_C:
			bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
			break;
		case PORT_D:
			bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
			break;
		default:
			return connector_status_unknown;
		}
	} else {
		switch (intel_dig_port->port) {
		case PORT_B:
			bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
			break;
		case PORT_C:
			bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
			break;
		case PORT_D:
			bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
			break;
		default:
			return connector_status_unknown;
		}
3087 3088
	}

3089
	if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3090 3091
		return connector_status_disconnected;

3092
	return intel_dp_detect_dpcd(intel_dp);
Z
Zhenyu Wang 已提交
3093 3094
}

3095 3096 3097
static struct edid *
intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
{
3098
	struct intel_connector *intel_connector = to_intel_connector(connector);
3099

3100 3101 3102 3103
	/* use cached edid if we have one */
	if (intel_connector->edid) {
		/* invalid edid */
		if (IS_ERR(intel_connector->edid))
3104 3105
			return NULL;

J
Jani Nikula 已提交
3106
		return drm_edid_duplicate(intel_connector->edid);
3107
	}
3108

3109
	return drm_get_edid(connector, adapter);
3110 3111 3112 3113 3114
}

static int
intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
{
3115
	struct intel_connector *intel_connector = to_intel_connector(connector);
3116

3117 3118 3119 3120 3121 3122 3123 3124
	/* use cached edid if we have one */
	if (intel_connector->edid) {
		/* invalid edid */
		if (IS_ERR(intel_connector->edid))
			return 0;

		return intel_connector_update_modes(connector,
						    intel_connector->edid);
3125 3126
	}

3127
	return intel_ddc_get_modes(connector, adapter);
3128 3129
}

Z
Zhenyu Wang 已提交
3130 3131 3132 3133
static enum drm_connector_status
intel_dp_detect(struct drm_connector *connector, bool force)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
3134 3135
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
3136
	struct drm_device *dev = connector->dev;
3137
	struct drm_i915_private *dev_priv = dev->dev_private;
Z
Zhenyu Wang 已提交
3138
	enum drm_connector_status status;
3139
	enum intel_display_power_domain power_domain;
Z
Zhenyu Wang 已提交
3140 3141
	struct edid *edid = NULL;

3142 3143
	intel_runtime_pm_get(dev_priv);

3144 3145 3146
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);

3147 3148 3149
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		      connector->base.id, drm_get_connector_name(connector));

Z
Zhenyu Wang 已提交
3150 3151 3152 3153 3154 3155
	intel_dp->has_audio = false;

	if (HAS_PCH_SPLIT(dev))
		status = ironlake_dp_detect(intel_dp);
	else
		status = g4x_dp_detect(intel_dp);
3156

Z
Zhenyu Wang 已提交
3157
	if (status != connector_status_connected)
3158
		goto out;
Z
Zhenyu Wang 已提交
3159

3160 3161
	intel_dp_probe_oui(intel_dp);

3162 3163
	if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
		intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3164
	} else {
3165
		edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3166 3167 3168 3169
		if (edid) {
			intel_dp->has_audio = drm_detect_monitor_audio(edid);
			kfree(edid);
		}
Z
Zhenyu Wang 已提交
3170 3171
	}

3172 3173
	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3174 3175 3176
	status = connector_status_connected;

out:
3177 3178
	intel_display_power_put(dev_priv, power_domain);

3179
	intel_runtime_pm_put(dev_priv);
3180

3181
	return status;
3182 3183 3184 3185
}

static int intel_dp_get_modes(struct drm_connector *connector)
{
3186
	struct intel_dp *intel_dp = intel_attached_dp(connector);
3187 3188
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
3189
	struct intel_connector *intel_connector = to_intel_connector(connector);
3190
	struct drm_device *dev = connector->dev;
3191 3192
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum intel_display_power_domain power_domain;
3193
	int ret;
3194 3195 3196 3197

	/* We should parse the EDID data and find out if it has an audio sink
	 */

3198 3199 3200
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);

3201
	ret = intel_dp_get_edid_modes(connector, &intel_dp->aux.ddc);
3202
	intel_display_power_put(dev_priv, power_domain);
3203
	if (ret)
3204 3205
		return ret;

3206
	/* if eDP has no EDID, fall back to fixed mode */
3207
	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3208
		struct drm_display_mode *mode;
3209 3210
		mode = drm_mode_duplicate(dev,
					  intel_connector->panel.fixed_mode);
3211
		if (mode) {
3212 3213 3214 3215 3216
			drm_mode_probed_add(connector, mode);
			return 1;
		}
	}
	return 0;
3217 3218
}

3219 3220 3221 3222
static bool
intel_dp_detect_audio(struct drm_connector *connector)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
3223 3224 3225 3226 3227
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = connector->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum intel_display_power_domain power_domain;
3228 3229 3230
	struct edid *edid;
	bool has_audio = false;

3231 3232 3233
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);

3234
	edid = intel_dp_get_edid(connector, &intel_dp->aux.ddc);
3235 3236 3237 3238 3239
	if (edid) {
		has_audio = drm_detect_monitor_audio(edid);
		kfree(edid);
	}

3240 3241
	intel_display_power_put(dev_priv, power_domain);

3242 3243 3244
	return has_audio;
}

3245 3246 3247 3248 3249
static int
intel_dp_set_property(struct drm_connector *connector,
		      struct drm_property *property,
		      uint64_t val)
{
3250
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
3251
	struct intel_connector *intel_connector = to_intel_connector(connector);
3252 3253
	struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3254 3255
	int ret;

3256
	ret = drm_object_property_set_value(&connector->base, property, val);
3257 3258 3259
	if (ret)
		return ret;

3260
	if (property == dev_priv->force_audio_property) {
3261 3262 3263 3264
		int i = val;
		bool has_audio;

		if (i == intel_dp->force_audio)
3265 3266
			return 0;

3267
		intel_dp->force_audio = i;
3268

3269
		if (i == HDMI_AUDIO_AUTO)
3270 3271
			has_audio = intel_dp_detect_audio(connector);
		else
3272
			has_audio = (i == HDMI_AUDIO_ON);
3273 3274

		if (has_audio == intel_dp->has_audio)
3275 3276
			return 0;

3277
		intel_dp->has_audio = has_audio;
3278 3279 3280
		goto done;
	}

3281
	if (property == dev_priv->broadcast_rgb_property) {
3282 3283 3284
		bool old_auto = intel_dp->color_range_auto;
		uint32_t old_range = intel_dp->color_range;

3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299
		switch (val) {
		case INTEL_BROADCAST_RGB_AUTO:
			intel_dp->color_range_auto = true;
			break;
		case INTEL_BROADCAST_RGB_FULL:
			intel_dp->color_range_auto = false;
			intel_dp->color_range = 0;
			break;
		case INTEL_BROADCAST_RGB_LIMITED:
			intel_dp->color_range_auto = false;
			intel_dp->color_range = DP_COLOR_RANGE_16_235;
			break;
		default:
			return -EINVAL;
		}
3300 3301 3302 3303 3304

		if (old_auto == intel_dp->color_range_auto &&
		    old_range == intel_dp->color_range)
			return 0;

3305 3306 3307
		goto done;
	}

3308 3309 3310 3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323
	if (is_edp(intel_dp) &&
	    property == connector->dev->mode_config.scaling_mode_property) {
		if (val == DRM_MODE_SCALE_NONE) {
			DRM_DEBUG_KMS("no scaling not supported\n");
			return -EINVAL;
		}

		if (intel_connector->panel.fitting_mode == val) {
			/* the eDP scaling property is not changed */
			return 0;
		}
		intel_connector->panel.fitting_mode = val;

		goto done;
	}

3324 3325 3326
	return -EINVAL;

done:
3327 3328
	if (intel_encoder->base.crtc)
		intel_crtc_restore_mode(intel_encoder->base.crtc);
3329 3330 3331 3332

	return 0;
}

3333
static void
3334
intel_dp_connector_destroy(struct drm_connector *connector)
3335
{
3336
	struct intel_connector *intel_connector = to_intel_connector(connector);
3337

3338 3339 3340
	if (!IS_ERR_OR_NULL(intel_connector->edid))
		kfree(intel_connector->edid);

3341 3342 3343
	/* Can't call is_edp() since the encoder may have been destroyed
	 * already. */
	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3344
		intel_panel_fini(&intel_connector->panel);
3345

3346
	drm_connector_cleanup(connector);
3347
	kfree(connector);
3348 3349
}

P
Paulo Zanoni 已提交
3350
void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3351
{
3352 3353
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_dp *intel_dp = &intel_dig_port->dp;
3354
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3355

3356
	drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
3357
	drm_encoder_cleanup(encoder);
3358 3359
	if (is_edp(intel_dp)) {
		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3360
		mutex_lock(&dev->mode_config.mutex);
3361
		edp_panel_vdd_off_sync(intel_dp);
3362
		mutex_unlock(&dev->mode_config.mutex);
3363
	}
3364
	kfree(intel_dig_port);
3365 3366
}

3367
static const struct drm_connector_funcs intel_dp_connector_funcs = {
3368
	.dpms = intel_connector_dpms,
3369 3370
	.detect = intel_dp_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
3371
	.set_property = intel_dp_set_property,
3372
	.destroy = intel_dp_connector_destroy,
3373 3374 3375 3376 3377
};

static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
	.get_modes = intel_dp_get_modes,
	.mode_valid = intel_dp_mode_valid,
3378
	.best_encoder = intel_best_encoder,
3379 3380 3381
};

static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3382
	.destroy = intel_dp_encoder_destroy,
3383 3384
};

3385
static void
3386
intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3387
{
3388
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3389

3390
	intel_dp_check_link_status(intel_dp);
3391
}
3392

3393 3394
/* Return which DP Port should be selected for Transcoder DP control */
int
3395
intel_trans_dp_port_sel(struct drm_crtc *crtc)
3396 3397
{
	struct drm_device *dev = crtc->dev;
3398 3399
	struct intel_encoder *intel_encoder;
	struct intel_dp *intel_dp;
3400

3401 3402
	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		intel_dp = enc_to_intel_dp(&intel_encoder->base);
3403

3404 3405
		if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
		    intel_encoder->type == INTEL_OUTPUT_EDP)
C
Chris Wilson 已提交
3406
			return intel_dp->output_reg;
3407
	}
C
Chris Wilson 已提交
3408

3409 3410 3411
	return -1;
}

3412
/* check the VBT to see whether the eDP is on DP-D port */
3413
bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3414 3415
{
	struct drm_i915_private *dev_priv = dev->dev_private;
3416
	union child_device_config *p_child;
3417
	int i;
3418 3419 3420 3421 3422
	static const short port_mapping[] = {
		[PORT_B] = PORT_IDPB,
		[PORT_C] = PORT_IDPC,
		[PORT_D] = PORT_IDPD,
	};
3423

3424 3425 3426
	if (port == PORT_A)
		return true;

3427
	if (!dev_priv->vbt.child_dev_num)
3428 3429
		return false;

3430 3431
	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
		p_child = dev_priv->vbt.child_dev + i;
3432

3433
		if (p_child->common.dvo_port == port_mapping[port] &&
3434 3435
		    (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
		    (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3436 3437 3438 3439 3440
			return true;
	}
	return false;
}

3441 3442 3443
static void
intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
{
3444 3445
	struct intel_connector *intel_connector = to_intel_connector(connector);

3446
	intel_attach_force_audio_property(connector);
3447
	intel_attach_broadcast_rgb_property(connector);
3448
	intel_dp->color_range_auto = true;
3449 3450 3451

	if (is_edp(intel_dp)) {
		drm_mode_create_scaling_mode_property(connector->dev);
3452 3453
		drm_object_attach_property(
			&connector->base,
3454
			connector->dev->mode_config.scaling_mode_property,
3455 3456
			DRM_MODE_SCALE_ASPECT);
		intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3457
	}
3458 3459
}

3460 3461 3462 3463 3464 3465 3466
static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
{
	intel_dp->last_power_cycle = jiffies;
	intel_dp->last_power_on = jiffies;
	intel_dp->last_backlight_off = jiffies;
}

3467 3468
static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3469 3470
				    struct intel_dp *intel_dp,
				    struct edp_power_seq *out)
3471 3472 3473 3474
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct edp_power_seq cur, vbt, spec, final;
	u32 pp_on, pp_off, pp_div, pp;
3475
	int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3476 3477

	if (HAS_PCH_SPLIT(dev)) {
3478
		pp_ctrl_reg = PCH_PP_CONTROL;
3479 3480 3481 3482
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
3483 3484 3485 3486 3487 3488
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3489
	}
3490 3491 3492

	/* Workaround: Need to write PP_CONTROL with the unlock key as
	 * the very first thing. */
3493
	pp = ironlake_get_pp_control(intel_dp);
3494
	I915_WRITE(pp_ctrl_reg, pp);
3495

3496 3497 3498
	pp_on = I915_READ(pp_on_reg);
	pp_off = I915_READ(pp_off_reg);
	pp_div = I915_READ(pp_div_reg);
3499 3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518

	/* Pull timing values out of registers */
	cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
		PANEL_POWER_UP_DELAY_SHIFT;

	cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
		PANEL_LIGHT_ON_DELAY_SHIFT;

	cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
		PANEL_LIGHT_OFF_DELAY_SHIFT;

	cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
		PANEL_POWER_DOWN_DELAY_SHIFT;

	cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
		       PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;

	DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);

3519
	vbt = dev_priv->vbt.edp_pps;
3520 3521 3522 3523 3524 3525 3526 3527 3528 3529 3530 3531 3532 3533 3534 3535 3536 3537 3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549 3550 3551 3552 3553 3554 3555

	/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
	 * our hw here, which are all in 100usec. */
	spec.t1_t3 = 210 * 10;
	spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
	spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
	spec.t10 = 500 * 10;
	/* This one is special and actually in units of 100ms, but zero
	 * based in the hw (so we need to add 100 ms). But the sw vbt
	 * table multiplies it with 1000 to make it in units of 100usec,
	 * too. */
	spec.t11_t12 = (510 + 100) * 10;

	DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);

	/* Use the max of the register settings and vbt. If both are
	 * unset, fall back to the spec limits. */
#define assign_final(field)	final.field = (max(cur.field, vbt.field) == 0 ? \
				       spec.field : \
				       max(cur.field, vbt.field))
	assign_final(t1_t3);
	assign_final(t8);
	assign_final(t9);
	assign_final(t10);
	assign_final(t11_t12);
#undef assign_final

#define get_delay(field)	(DIV_ROUND_UP(final.field, 10))
	intel_dp->panel_power_up_delay = get_delay(t1_t3);
	intel_dp->backlight_on_delay = get_delay(t8);
	intel_dp->backlight_off_delay = get_delay(t9);
	intel_dp->panel_power_down_delay = get_delay(t10);
	intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
#undef get_delay

3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568 3569 3570 3571 3572
	DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
		      intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
		      intel_dp->panel_power_cycle_delay);

	DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
		      intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);

	if (out)
		*out = final;
}

static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
					      struct intel_dp *intel_dp,
					      struct edp_power_seq *seq)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
3573 3574 3575 3576 3577 3578 3579 3580 3581
	u32 pp_on, pp_off, pp_div, port_sel = 0;
	int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
	int pp_on_reg, pp_off_reg, pp_div_reg;

	if (HAS_PCH_SPLIT(dev)) {
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
3582 3583 3584 3585 3586
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3587 3588
	}

3589 3590 3591 3592 3593 3594 3595 3596
	/*
	 * And finally store the new values in the power sequencer. The
	 * backlight delays are set to 1 because we do manual waits on them. For
	 * T8, even BSpec recommends doing it. For T9, if we don't do this,
	 * we'll end up waiting for the backlight off delay twice: once when we
	 * do the manual sleep, and once when we disable the panel and wait for
	 * the PP_STATUS bit to become zero.
	 */
3597
	pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
3598 3599
		(1 << PANEL_LIGHT_ON_DELAY_SHIFT);
	pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
3600
		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3601 3602
	/* Compute the divisor for the pp clock, simply match the Bspec
	 * formula. */
3603
	pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3604
	pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3605 3606 3607 3608
			<< PANEL_POWER_CYCLE_DELAY_SHIFT);

	/* Haswell doesn't have any port selection bits for the panel
	 * power sequencer any more. */
3609
	if (IS_VALLEYVIEW(dev)) {
3610 3611 3612 3613
		if (dp_to_dig_port(intel_dp)->port == PORT_B)
			port_sel = PANEL_PORT_SELECT_DPB_VLV;
		else
			port_sel = PANEL_PORT_SELECT_DPC_VLV;
3614 3615
	} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
		if (dp_to_dig_port(intel_dp)->port == PORT_A)
3616
			port_sel = PANEL_PORT_SELECT_DPA;
3617
		else
3618
			port_sel = PANEL_PORT_SELECT_DPD;
3619 3620
	}

3621 3622 3623 3624 3625
	pp_on |= port_sel;

	I915_WRITE(pp_on_reg, pp_on);
	I915_WRITE(pp_off_reg, pp_off);
	I915_WRITE(pp_div_reg, pp_div);
3626 3627

	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3628 3629 3630
		      I915_READ(pp_on_reg),
		      I915_READ(pp_off_reg),
		      I915_READ(pp_div_reg));
3631 3632
}

3633
static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3634 3635
				     struct intel_connector *intel_connector,
				     struct edp_power_seq *power_seq)
3636 3637 3638
{
	struct drm_connector *connector = &intel_connector->base;
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3639 3640
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
3641 3642 3643 3644 3645 3646 3647 3648 3649
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_display_mode *fixed_mode = NULL;
	bool has_dpcd;
	struct drm_display_mode *scan;
	struct edid *edid;

	if (!is_edp(intel_dp))
		return true;

3650 3651 3652 3653 3654 3655 3656 3657
	/* The VDD bit needs a power domain reference, so if the bit is already
	 * enabled when we boot, grab this reference. */
	if (edp_have_panel_vdd(intel_dp)) {
		enum intel_display_power_domain power_domain;
		power_domain = intel_display_port_power_domain(intel_encoder);
		intel_display_power_get(dev_priv, power_domain);
	}

3658
	/* Cache DPCD and EDID for edp. */
3659
	intel_edp_panel_vdd_on(intel_dp);
3660
	has_dpcd = intel_dp_get_dpcd(intel_dp);
3661
	edp_panel_vdd_off(intel_dp, false);
3662 3663 3664 3665 3666 3667 3668 3669 3670 3671 3672 3673 3674

	if (has_dpcd) {
		if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
			dev_priv->no_aux_handshake =
				intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
				DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
	} else {
		/* if this fails, presume the device is a ghost */
		DRM_INFO("failed to retrieve link info, disabling eDP\n");
		return false;
	}

	/* We now know it's not a ghost, init power sequence regs. */
3675
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
3676

3677
	mutex_lock(&dev->mode_config.mutex);
3678
	edid = drm_get_edid(connector, &intel_dp->aux.ddc);
3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690 3691 3692 3693 3694 3695 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707
	if (edid) {
		if (drm_add_edid_modes(connector, edid)) {
			drm_mode_connector_update_edid_property(connector,
								edid);
			drm_edid_to_eld(connector, edid);
		} else {
			kfree(edid);
			edid = ERR_PTR(-EINVAL);
		}
	} else {
		edid = ERR_PTR(-ENOENT);
	}
	intel_connector->edid = edid;

	/* prefer fixed mode from EDID if available */
	list_for_each_entry(scan, &connector->probed_modes, head) {
		if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
			fixed_mode = drm_mode_duplicate(dev, scan);
			break;
		}
	}

	/* fallback to VBT if available for eDP */
	if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
		fixed_mode = drm_mode_duplicate(dev,
					dev_priv->vbt.lfp_lvds_vbt_mode);
		if (fixed_mode)
			fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
	}
3708
	mutex_unlock(&dev->mode_config.mutex);
3709

3710
	intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
3711 3712 3713 3714 3715
	intel_panel_setup_backlight(connector);

	return true;
}

3716
bool
3717 3718
intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
			struct intel_connector *intel_connector)
3719
{
3720 3721 3722 3723
	struct drm_connector *connector = &intel_connector->base;
	struct intel_dp *intel_dp = &intel_dig_port->dp;
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
3724
	struct drm_i915_private *dev_priv = dev->dev_private;
3725
	enum port port = intel_dig_port->port;
3726
	struct edp_power_seq power_seq = { 0 };
3727
	int type;
3728

3729 3730 3731 3732 3733 3734 3735 3736 3737 3738
	/* intel_dp vfuncs */
	if (IS_VALLEYVIEW(dev))
		intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
		intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
	else if (HAS_PCH_SPLIT(dev))
		intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
	else
		intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;

3739 3740
	intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;

3741 3742
	/* Preserve the current hw state. */
	intel_dp->DP = I915_READ(intel_dp->output_reg);
3743
	intel_dp->attached_connector = intel_connector;
3744

3745
	if (intel_dp_is_edp(dev, port))
3746
		type = DRM_MODE_CONNECTOR_eDP;
3747 3748
	else
		type = DRM_MODE_CONNECTOR_DisplayPort;
3749

3750 3751 3752 3753 3754 3755 3756 3757
	/*
	 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
	 * for DP the encoder type can be set by the caller to
	 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
	 */
	if (type == DRM_MODE_CONNECTOR_eDP)
		intel_encoder->type = INTEL_OUTPUT_EDP;

3758 3759 3760 3761
	DRM_DEBUG_KMS("Adding %s connector on port %c\n",
			type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
			port_name(port));

3762
	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3763 3764 3765 3766 3767
	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);

	connector->interlace_allowed = true;
	connector->doublescan_allowed = 0;

3768
	INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3769
			  edp_panel_vdd_work);
3770

3771
	intel_connector_attach_encoder(intel_connector, intel_encoder);
3772 3773
	drm_sysfs_connector_add(connector);

P
Paulo Zanoni 已提交
3774
	if (HAS_DDI(dev))
3775 3776 3777
		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
	else
		intel_connector->get_hw_state = intel_connector_get_hw_state;
3778
	intel_connector->unregister = intel_dp_connector_unregister;
3779

3780
	/* Set up the hotplug pin. */
3781 3782
	switch (port) {
	case PORT_A:
3783
		intel_encoder->hpd_pin = HPD_PORT_A;
3784 3785
		break;
	case PORT_B:
3786
		intel_encoder->hpd_pin = HPD_PORT_B;
3787 3788
		break;
	case PORT_C:
3789
		intel_encoder->hpd_pin = HPD_PORT_C;
3790 3791
		break;
	case PORT_D:
3792
		intel_encoder->hpd_pin = HPD_PORT_D;
3793 3794
		break;
	default:
3795
		BUG();
3796 3797
	}

3798 3799
	if (is_edp(intel_dp)) {
		intel_dp_init_panel_power_timestamps(intel_dp);
3800
		intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
3801
	}
3802

3803
	intel_dp_aux_init(intel_dp, intel_connector);
3804

R
Rodrigo Vivi 已提交
3805 3806
	intel_dp->psr_setup_done = false;

3807
	if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
3808
		drm_dp_aux_unregister_i2c_bus(&intel_dp->aux);
3809 3810 3811
		if (is_edp(intel_dp)) {
			cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
			mutex_lock(&dev->mode_config.mutex);
3812
			edp_panel_vdd_off_sync(intel_dp);
3813 3814
			mutex_unlock(&dev->mode_config.mutex);
		}
3815 3816
		drm_sysfs_connector_remove(connector);
		drm_connector_cleanup(connector);
3817
		return false;
3818
	}
3819

3820 3821
	intel_dp_add_properties(intel_dp, connector);

3822 3823 3824 3825 3826 3827 3828 3829
	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
3830 3831

	return true;
3832
}
3833 3834 3835 3836 3837 3838 3839 3840 3841

void
intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
{
	struct intel_digital_port *intel_dig_port;
	struct intel_encoder *intel_encoder;
	struct drm_encoder *encoder;
	struct intel_connector *intel_connector;

3842
	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3843 3844 3845
	if (!intel_dig_port)
		return;

3846
	intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
3847 3848 3849 3850 3851 3852 3853 3854 3855 3856 3857
	if (!intel_connector) {
		kfree(intel_dig_port);
		return;
	}

	intel_encoder = &intel_dig_port->base;
	encoder = &intel_encoder->base;

	drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
			 DRM_MODE_ENCODER_TMDS);

3858
	intel_encoder->compute_config = intel_dp_compute_config;
3859
	intel_encoder->mode_set = intel_dp_mode_set;
P
Paulo Zanoni 已提交
3860 3861 3862
	intel_encoder->disable = intel_disable_dp;
	intel_encoder->post_disable = intel_post_disable_dp;
	intel_encoder->get_hw_state = intel_dp_get_hw_state;
3863
	intel_encoder->get_config = intel_dp_get_config;
3864
	if (IS_VALLEYVIEW(dev)) {
3865
		intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
3866 3867 3868
		intel_encoder->pre_enable = vlv_pre_enable_dp;
		intel_encoder->enable = vlv_enable_dp;
	} else {
3869 3870
		intel_encoder->pre_enable = g4x_pre_enable_dp;
		intel_encoder->enable = g4x_enable_dp;
3871
	}
3872

3873
	intel_dig_port->port = port;
3874 3875
	intel_dig_port->dp.output_reg = output_reg;

P
Paulo Zanoni 已提交
3876
	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3877
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
3878
	intel_encoder->cloneable = 0;
3879 3880
	intel_encoder->hot_plug = intel_dp_hot_plug;

3881 3882 3883
	if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
		drm_encoder_cleanup(encoder);
		kfree(intel_dig_port);
3884
		kfree(intel_connector);
3885
	}
3886
}