intel_dp.c 106.7 KB
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/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
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#include "intel_drv.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"

#define DP_LINK_CHECK_TIMEOUT	(10 * 1000)

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struct dp_link_dpll {
	int link_bw;
	struct dpll dpll;
};

static const struct dp_link_dpll gen4_dpll[] = {
	{ DP_LINK_BW_1_62,
		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
	{ DP_LINK_BW_2_7,
		{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
};

static const struct dp_link_dpll pch_dpll[] = {
	{ DP_LINK_BW_1_62,
		{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
	{ DP_LINK_BW_2_7,
		{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
};

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static const struct dp_link_dpll vlv_dpll[] = {
	{ DP_LINK_BW_1_62,
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		{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
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	{ DP_LINK_BW_2_7,
		{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
};

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/**
 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 * @intel_dp: DP struct
 *
 * If a CPU or PCH DP output is attached to an eDP panel, this function
 * will return true, and false otherwise.
 */
static bool is_edp(struct intel_dp *intel_dp)
{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
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}

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static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
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{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.base.dev;
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}

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static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
{
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	return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
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}

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static void intel_dp_link_down(struct intel_dp *intel_dp);
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static void edp_panel_vdd_on(struct intel_dp *intel_dp);
static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
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static int
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intel_dp_max_link_bw(struct intel_dp *intel_dp)
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{
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	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
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	switch (max_link_bw) {
	case DP_LINK_BW_1_62:
	case DP_LINK_BW_2_7:
		break;
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	case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
		max_link_bw = DP_LINK_BW_2_7;
		break;
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	default:
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		WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
		     max_link_bw);
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		max_link_bw = DP_LINK_BW_1_62;
		break;
	}
	return max_link_bw;
}

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/*
 * The units on the numbers in the next two are... bizarre.  Examples will
 * make it clearer; this one parallels an example in the eDP spec.
 *
 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 *
 *     270000 * 1 * 8 / 10 == 216000
 *
 * The actual data capacity of that configuration is 2.16Gbit/s, so the
 * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 * 119000.  At 18bpp that's 2142000 kilobits per second.
 *
 * Thus the strange-looking division by 10 in intel_dp_link_required, to
 * get the result in decakilobits instead of kilobits.
 */

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static int
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intel_dp_link_required(int pixel_clock, int bpp)
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{
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	return (pixel_clock * bpp + 9) / 10;
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}

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static int
intel_dp_max_data_rate(int max_link_clock, int max_lanes)
{
	return (max_link_clock * max_lanes * 8) / 10;
}

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static enum drm_mode_status
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intel_dp_mode_valid(struct drm_connector *connector,
		    struct drm_display_mode *mode)
{
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	struct intel_dp *intel_dp = intel_attached_dp(connector);
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	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
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	int target_clock = mode->clock;
	int max_rate, mode_rate, max_lanes, max_link_clock;
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	if (is_edp(intel_dp) && fixed_mode) {
		if (mode->hdisplay > fixed_mode->hdisplay)
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			return MODE_PANEL;

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		if (mode->vdisplay > fixed_mode->vdisplay)
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			return MODE_PANEL;
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		target_clock = fixed_mode->clock;
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	}

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	max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
	max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);

	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
	mode_rate = intel_dp_link_required(target_clock, 18);

	if (mode_rate > max_rate)
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		return MODE_CLOCK_HIGH;
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	if (mode->clock < 10000)
		return MODE_CLOCK_LOW;

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	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		return MODE_H_ILLEGAL;

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	return MODE_OK;
}

static uint32_t
pack_aux(uint8_t *src, int src_bytes)
{
	int	i;
	uint32_t v = 0;

	if (src_bytes > 4)
		src_bytes = 4;
	for (i = 0; i < src_bytes; i++)
		v |= ((uint32_t) src[i]) << ((3-i) * 8);
	return v;
}

static void
unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
{
	int i;
	if (dst_bytes > 4)
		dst_bytes = 4;
	for (i = 0; i < dst_bytes; i++)
		dst[i] = src >> ((3-i) * 8);
}

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/* hrawclock is 1/4 the FSB frequency */
static int
intel_hrawclk(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t clkcfg;

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	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
	if (IS_VALLEYVIEW(dev))
		return 200;

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	clkcfg = I915_READ(CLKCFG);
	switch (clkcfg & CLKCFG_FSB_MASK) {
	case CLKCFG_FSB_400:
		return 100;
	case CLKCFG_FSB_533:
		return 133;
	case CLKCFG_FSB_667:
		return 166;
	case CLKCFG_FSB_800:
		return 200;
	case CLKCFG_FSB_1067:
		return 266;
	case CLKCFG_FSB_1333:
		return 333;
	/* these two are just a guess; one of them might be right */
	case CLKCFG_FSB_1600:
	case CLKCFG_FSB_1600_ALT:
		return 400;
	default:
		return 133;
	}
}

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static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
				    struct intel_dp *intel_dp,
				    struct edp_power_seq *out);
static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
					      struct intel_dp *intel_dp,
					      struct edp_power_seq *out);

static enum pipe
vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;
	enum pipe pipe;

	/* modeset should have pipe */
	if (crtc)
		return to_intel_crtc(crtc)->pipe;

	/* init time, try to find a pipe with this port selected */
	for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
		u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
			PANEL_PORT_SELECT_MASK;
		if (port_sel == PANEL_PORT_SELECT_DPB_VLV && port == PORT_B)
			return pipe;
		if (port_sel == PANEL_PORT_SELECT_DPC_VLV && port == PORT_C)
			return pipe;
	}

	/* shrug */
	return PIPE_A;
}

static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

	if (HAS_PCH_SPLIT(dev))
		return PCH_PP_CONTROL;
	else
		return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
}

static u32 _pp_stat_reg(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

	if (HAS_PCH_SPLIT(dev))
		return PCH_PP_STATUS;
	else
		return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
}

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static bool edp_have_panel_power(struct intel_dp *intel_dp)
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{
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	struct drm_device *dev = intel_dp_to_dev(intel_dp);
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	struct drm_i915_private *dev_priv = dev->dev_private;

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	return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
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}

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static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
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{
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	struct drm_device *dev = intel_dp_to_dev(intel_dp);
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	struct drm_i915_private *dev_priv = dev->dev_private;

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	return (I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD) != 0;
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}

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static void
intel_dp_check_edp(struct intel_dp *intel_dp)
{
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	struct drm_device *dev = intel_dp_to_dev(intel_dp);
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	if (!is_edp(intel_dp))
		return;
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	if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
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		WARN(1, "eDP powered off while attempting aux channel communication.\n");
		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
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			      I915_READ(_pp_stat_reg(intel_dp)),
			      I915_READ(_pp_ctrl_reg(intel_dp)));
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	}
}

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static uint32_t
intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
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	uint32_t status;
	bool done;

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#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
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	if (has_aux_irq)
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		done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
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					  msecs_to_jiffies_timeout(10));
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	else
		done = wait_for_atomic(C, 10) == 0;
	if (!done)
		DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
			  has_aux_irq);
#undef C

	return status;
}

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static uint32_t get_aux_clock_divider(struct intel_dp *intel_dp,
				      int index)
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{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	/* The clock divider is based off the hrawclk,
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	 * and would like to run at 2MHz. So, take the
	 * hrawclk value and divide by 2 and use that
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	 *
	 * Note that PCH attached eDP panels should use a 125MHz input
	 * clock divider.
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	 */
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	if (IS_VALLEYVIEW(dev)) {
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		return index ? 0 : 100;
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	} else if (intel_dig_port->port == PORT_A) {
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		if (index)
			return 0;
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		if (HAS_DDI(dev))
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			return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
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		else if (IS_GEN6(dev) || IS_GEN7(dev))
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			return 200; /* SNB & IVB eDP input clock at 400Mhz */
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		else
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			return 225; /* eDP input clock at 450Mhz */
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	} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
		/* Workaround for non-ULT HSW */
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		switch (index) {
		case 0: return 63;
		case 1: return 72;
		default: return 0;
		}
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	} else if (HAS_PCH_SPLIT(dev)) {
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		return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
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	} else {
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		return index ? 0 :intel_hrawclk(dev) / 2;
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	}
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}

static int
intel_dp_aux_ch(struct intel_dp *intel_dp,
		uint8_t *send, int send_bytes,
		uint8_t *recv, int recv_size)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
	uint32_t ch_data = ch_ctl + 4;
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	uint32_t aux_clock_divider;
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	int i, ret, recv_bytes;
	uint32_t status;
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	int try, precharge, clock = 0;
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	bool has_aux_irq = true;
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	uint32_t timeout;
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	/* dp aux is extremely sensitive to irq latency, hence request the
	 * lowest possible wakeup latency and so prevent the cpu from going into
	 * deep sleep states.
	 */
	pm_qos_update_request(&dev_priv->pm_qos, 0);

	intel_dp_check_edp(intel_dp);
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	if (IS_GEN6(dev))
		precharge = 3;
	else
		precharge = 5;

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	if (IS_BROADWELL(dev) && ch_ctl == DPA_AUX_CH_CTL)
		timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
	else
		timeout = DP_AUX_CH_CTL_TIME_OUT_400us;

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	intel_aux_display_runtime_get(dev_priv);

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	/* Try to wait for any previous AUX channel activity */
	for (try = 0; try < 3; try++) {
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		status = I915_READ_NOTRACE(ch_ctl);
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		if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
			break;
		msleep(1);
	}

	if (try == 3) {
		WARN(1, "dp_aux_ch not started status 0x%08x\n",
		     I915_READ(ch_ctl));
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		ret = -EBUSY;
		goto out;
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	}

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	/* Only 5 data registers! */
	if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
		ret = -E2BIG;
		goto out;
	}

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	while ((aux_clock_divider = get_aux_clock_divider(intel_dp, clock++))) {
		/* Must try at least 3 times according to DP spec */
		for (try = 0; try < 5; try++) {
			/* Load the send data into the aux channel data registers */
			for (i = 0; i < send_bytes; i += 4)
				I915_WRITE(ch_data + i,
					   pack_aux(send + i, send_bytes - i));

			/* Send the command and wait for it to complete */
			I915_WRITE(ch_ctl,
				   DP_AUX_CH_CTL_SEND_BUSY |
				   (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
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				   timeout |
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				   (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
				   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
				   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
				   DP_AUX_CH_CTL_DONE |
				   DP_AUX_CH_CTL_TIME_OUT_ERROR |
				   DP_AUX_CH_CTL_RECEIVE_ERROR);

			status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);

			/* Clear done status and any errors */
			I915_WRITE(ch_ctl,
				   status |
				   DP_AUX_CH_CTL_DONE |
				   DP_AUX_CH_CTL_TIME_OUT_ERROR |
				   DP_AUX_CH_CTL_RECEIVE_ERROR);

			if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
				      DP_AUX_CH_CTL_RECEIVE_ERROR))
				continue;
			if (status & DP_AUX_CH_CTL_DONE)
				break;
		}
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		if (status & DP_AUX_CH_CTL_DONE)
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			break;
	}

	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
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		DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
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		ret = -EBUSY;
		goto out;
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	}

	/* Check for timeout or receive error.
	 * Timeouts occur when the sink is not connected
	 */
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	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
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		DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
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		ret = -EIO;
		goto out;
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	}
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	/* Timeouts occur when the device isn't connected, so they're
	 * "normal" -- don't fill the kernel log with these */
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	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
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		DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
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		ret = -ETIMEDOUT;
		goto out;
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	}

	/* Unload any bytes sent back from the other side */
	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
		      DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
	if (recv_bytes > recv_size)
		recv_bytes = recv_size;
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	for (i = 0; i < recv_bytes; i += 4)
		unpack_aux(I915_READ(ch_data + i),
			   recv + i, recv_bytes - i);
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	ret = recv_bytes;
out:
	pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
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	intel_aux_display_runtime_put(dev_priv);
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	return ret;
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}

/* Write data to the aux channel in native mode */
static int
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intel_dp_aux_native_write(struct intel_dp *intel_dp,
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			  uint16_t address, uint8_t *send, int send_bytes)
{
	int ret;
	uint8_t	msg[20];
	int msg_bytes;
	uint8_t	ack;

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	if (WARN_ON(send_bytes > 16))
		return -E2BIG;

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	intel_dp_check_edp(intel_dp);
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	msg[0] = DP_AUX_NATIVE_WRITE << 4;
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	msg[1] = address >> 8;
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	msg[2] = address & 0xff;
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	msg[3] = send_bytes - 1;
	memcpy(&msg[4], send, send_bytes);
	msg_bytes = send_bytes + 4;
	for (;;) {
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		ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
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		if (ret < 0)
			return ret;
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		ack >>= 4;
		if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK)
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			break;
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		else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
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			udelay(100);
		else
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			return -EIO;
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	}
	return send_bytes;
}

/* Write a single byte to the aux channel in native mode */
static int
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intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
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			    uint16_t address, uint8_t byte)
{
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	return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
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}

/* read bytes from a native aux channel */
static int
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intel_dp_aux_native_read(struct intel_dp *intel_dp,
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			 uint16_t address, uint8_t *recv, int recv_bytes)
{
	uint8_t msg[4];
	int msg_bytes;
	uint8_t reply[20];
	int reply_bytes;
	uint8_t ack;
	int ret;

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	if (WARN_ON(recv_bytes > 19))
		return -E2BIG;

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	intel_dp_check_edp(intel_dp);
592
	msg[0] = DP_AUX_NATIVE_READ << 4;
593 594 595 596 597 598 599 600
	msg[1] = address >> 8;
	msg[2] = address & 0xff;
	msg[3] = recv_bytes - 1;

	msg_bytes = 4;
	reply_bytes = recv_bytes + 1;

	for (;;) {
C
Chris Wilson 已提交
601
		ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
602
				      reply, reply_bytes);
603 604 605
		if (ret == 0)
			return -EPROTO;
		if (ret < 0)
606
			return ret;
607 608
		ack = reply[0] >> 4;
		if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_ACK) {
609 610 611
			memcpy(recv, reply + 1, ret - 1);
			return ret - 1;
		}
612
		else if ((ack & DP_AUX_NATIVE_REPLY_MASK) == DP_AUX_NATIVE_REPLY_DEFER)
613 614
			udelay(100);
		else
615
			return -EIO;
616 617 618 619
	}
}

static int
620 621
intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
		    uint8_t write_byte, uint8_t *read_byte)
622
{
623
	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
C
Chris Wilson 已提交
624 625 626
	struct intel_dp *intel_dp = container_of(adapter,
						struct intel_dp,
						adapter);
627 628 629
	uint16_t address = algo_data->address;
	uint8_t msg[5];
	uint8_t reply[2];
630
	unsigned retry;
631 632 633 634
	int msg_bytes;
	int reply_bytes;
	int ret;

635
	edp_panel_vdd_on(intel_dp);
636
	intel_dp_check_edp(intel_dp);
637 638
	/* Set up the command byte */
	if (mode & MODE_I2C_READ)
639
		msg[0] = DP_AUX_I2C_READ << 4;
640
	else
641
		msg[0] = DP_AUX_I2C_WRITE << 4;
642 643

	if (!(mode & MODE_I2C_STOP))
644
		msg[0] |= DP_AUX_I2C_MOT << 4;
645

646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666
	msg[1] = address >> 8;
	msg[2] = address;

	switch (mode) {
	case MODE_I2C_WRITE:
		msg[3] = 0;
		msg[4] = write_byte;
		msg_bytes = 5;
		reply_bytes = 1;
		break;
	case MODE_I2C_READ:
		msg[3] = 0;
		msg_bytes = 4;
		reply_bytes = 2;
		break;
	default:
		msg_bytes = 3;
		reply_bytes = 1;
		break;
	}

667 668 669 670 671 672
	/*
	 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device is
	 * required to retry at least seven times upon receiving AUX_DEFER
	 * before giving up the AUX transaction.
	 */
	for (retry = 0; retry < 7; retry++) {
673 674 675
		ret = intel_dp_aux_ch(intel_dp,
				      msg, msg_bytes,
				      reply, reply_bytes);
676
		if (ret < 0) {
677
			DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
678
			goto out;
679
		}
680

681 682
		switch ((reply[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK) {
		case DP_AUX_NATIVE_REPLY_ACK:
683 684 685 686
			/* I2C-over-AUX Reply field is only valid
			 * when paired with AUX ACK.
			 */
			break;
687
		case DP_AUX_NATIVE_REPLY_NACK:
688
			DRM_DEBUG_KMS("aux_ch native nack\n");
689 690
			ret = -EREMOTEIO;
			goto out;
691
		case DP_AUX_NATIVE_REPLY_DEFER:
692 693 694 695 696 697 698 699 700 701 702 703
			/*
			 * For now, just give more slack to branch devices. We
			 * could check the DPCD for I2C bit rate capabilities,
			 * and if available, adjust the interval. We could also
			 * be more careful with DP-to-Legacy adapters where a
			 * long legacy cable may force very low I2C bit rates.
			 */
			if (intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
			    DP_DWN_STRM_PORT_PRESENT)
				usleep_range(500, 600);
			else
				usleep_range(300, 400);
704 705 706 707
			continue;
		default:
			DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
				  reply[0]);
708 709
			ret = -EREMOTEIO;
			goto out;
710 711
		}

712 713
		switch ((reply[0] >> 4) & DP_AUX_I2C_REPLY_MASK) {
		case DP_AUX_I2C_REPLY_ACK:
714 715 716
			if (mode == MODE_I2C_READ) {
				*read_byte = reply[1];
			}
717 718
			ret = reply_bytes - 1;
			goto out;
719
		case DP_AUX_I2C_REPLY_NACK:
720
			DRM_DEBUG_KMS("aux_i2c nack\n");
721 722
			ret = -EREMOTEIO;
			goto out;
723
		case DP_AUX_I2C_REPLY_DEFER:
724
			DRM_DEBUG_KMS("aux_i2c defer\n");
725 726 727
			udelay(100);
			break;
		default:
728
			DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
729 730
			ret = -EREMOTEIO;
			goto out;
731 732
		}
	}
733 734

	DRM_ERROR("too many retries, giving up\n");
735 736 737
	ret = -EREMOTEIO;

out:
738
	edp_panel_vdd_off(intel_dp, false);
739
	return ret;
740 741 742
}

static int
C
Chris Wilson 已提交
743
intel_dp_i2c_init(struct intel_dp *intel_dp,
744
		  struct intel_connector *intel_connector, const char *name)
745
{
746 747
	int	ret;

Z
Zhenyu Wang 已提交
748
	DRM_DEBUG_KMS("i2c_init %s\n", name);
C
Chris Wilson 已提交
749 750 751 752
	intel_dp->algo.running = false;
	intel_dp->algo.address = 0;
	intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;

753
	memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
C
Chris Wilson 已提交
754 755
	intel_dp->adapter.owner = THIS_MODULE;
	intel_dp->adapter.class = I2C_CLASS_DDC;
756
	strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
C
Chris Wilson 已提交
757 758
	intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
	intel_dp->adapter.algo_data = &intel_dp->algo;
759
	intel_dp->adapter.dev.parent = intel_connector->base.kdev;
C
Chris Wilson 已提交
760

761 762
	ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
	return ret;
763 764
}

765 766 767 768 769
static void
intel_dp_set_clock(struct intel_encoder *encoder,
		   struct intel_crtc_config *pipe_config, int link_bw)
{
	struct drm_device *dev = encoder->base.dev;
770 771
	const struct dp_link_dpll *divisor = NULL;
	int i, count = 0;
772 773

	if (IS_G4X(dev)) {
774 775
		divisor = gen4_dpll;
		count = ARRAY_SIZE(gen4_dpll);
776 777 778
	} else if (IS_HASWELL(dev)) {
		/* Haswell has special-purpose DP DDI clocks. */
	} else if (HAS_PCH_SPLIT(dev)) {
779 780
		divisor = pch_dpll;
		count = ARRAY_SIZE(pch_dpll);
781
	} else if (IS_VALLEYVIEW(dev)) {
782 783
		divisor = vlv_dpll;
		count = ARRAY_SIZE(vlv_dpll);
784
	}
785 786 787 788 789 790 791 792 793

	if (divisor && count) {
		for (i = 0; i < count; i++) {
			if (link_bw == divisor[i].link_bw) {
				pipe_config->dpll = divisor[i].dpll;
				pipe_config->clock_set = true;
				break;
			}
		}
794 795 796
	}
}

P
Paulo Zanoni 已提交
797
bool
798 799
intel_dp_compute_config(struct intel_encoder *encoder,
			struct intel_crtc_config *pipe_config)
800
{
801
	struct drm_device *dev = encoder->base.dev;
802
	struct drm_i915_private *dev_priv = dev->dev_private;
803 804
	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
805
	enum port port = dp_to_dig_port(intel_dp)->port;
806
	struct intel_crtc *intel_crtc = encoder->new_crtc;
807
	struct intel_connector *intel_connector = intel_dp->attached_connector;
808
	int lane_count, clock;
809
	int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
C
Chris Wilson 已提交
810
	int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
811
	int bpp, mode_rate;
812
	static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
813
	int link_avail, link_clock;
814

815
	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
816 817
		pipe_config->has_pch_encoder = true;

818
	pipe_config->has_dp_encoder = true;
819

820 821 822
	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
		intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
				       adjusted_mode);
823 824 825 826
		if (!HAS_PCH_SPLIT(dev))
			intel_gmch_panel_fitting(intel_crtc, pipe_config,
						 intel_connector->panel.fitting_mode);
		else
827 828
			intel_pch_panel_fitting(intel_crtc, pipe_config,
						intel_connector->panel.fitting_mode);
829 830
	}

831
	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
832 833
		return false;

834 835
	DRM_DEBUG_KMS("DP link computation with max lane count %i "
		      "max bw %02x pixel clock %iKHz\n",
836 837
		      max_lane_count, bws[max_clock],
		      adjusted_mode->crtc_clock);
838

839 840
	/* Walk through all bpp values. Luckily they're all nicely spaced with 2
	 * bpc in between. */
841
	bpp = pipe_config->pipe_bpp;
842 843
	if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
	    dev_priv->vbt.edp_bpp < bpp) {
844 845
		DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
			      dev_priv->vbt.edp_bpp);
846
		bpp = dev_priv->vbt.edp_bpp;
847
	}
848

849
	for (; bpp >= 6*3; bpp -= 2*3) {
850 851
		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
						   bpp);
852 853 854 855 856 857 858 859 860 861 862 863 864

		for (clock = 0; clock <= max_clock; clock++) {
			for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
				link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
				link_avail = intel_dp_max_data_rate(link_clock,
								    lane_count);

				if (mode_rate <= link_avail) {
					goto found;
				}
			}
		}
	}
865

866
	return false;
867

868
found:
869 870 871 872 873 874
	if (intel_dp->color_range_auto) {
		/*
		 * See:
		 * CEA-861-E - 5.1 Default Encoding Parameters
		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
		 */
875
		if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
876 877 878 879 880
			intel_dp->color_range = DP_COLOR_RANGE_16_235;
		else
			intel_dp->color_range = 0;
	}

881
	if (intel_dp->color_range)
882
		pipe_config->limited_color_range = true;
883

884 885
	intel_dp->link_bw = bws[clock];
	intel_dp->lane_count = lane_count;
886
	pipe_config->pipe_bpp = bpp;
887
	pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
888

889 890
	DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
		      intel_dp->link_bw, intel_dp->lane_count,
891
		      pipe_config->port_clock, bpp);
892 893
	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
		      mode_rate, link_avail);
894

895
	intel_link_compute_m_n(bpp, lane_count,
896 897
			       adjusted_mode->crtc_clock,
			       pipe_config->port_clock,
898
			       &pipe_config->dp_m_n);
899

900 901
	intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);

902
	return true;
903 904
}

905
static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
906
{
907 908 909
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
	struct drm_device *dev = crtc->base.dev;
910 911 912
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

913
	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
914 915 916
	dpa_ctl = I915_READ(DP_A);
	dpa_ctl &= ~DP_PLL_FREQ_MASK;

917
	if (crtc->config.port_clock == 162000) {
918 919 920 921
		/* For a long time we've carried around a ILK-DevA w/a for the
		 * 160MHz clock. If we're really unlucky, it's still required.
		 */
		DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
922
		dpa_ctl |= DP_PLL_FREQ_160MHZ;
923
		intel_dp->DP |= DP_PLL_FREQ_160MHZ;
924 925
	} else {
		dpa_ctl |= DP_PLL_FREQ_270MHZ;
926
		intel_dp->DP |= DP_PLL_FREQ_270MHZ;
927
	}
928

929 930 931 932 933 934
	I915_WRITE(DP_A, dpa_ctl);

	POSTING_READ(DP_A);
	udelay(500);
}

935
static void intel_dp_mode_set(struct intel_encoder *encoder)
936
{
937
	struct drm_device *dev = encoder->base.dev;
938
	struct drm_i915_private *dev_priv = dev->dev_private;
939
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
940
	enum port port = dp_to_dig_port(intel_dp)->port;
941 942
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
943

944
	/*
K
Keith Packard 已提交
945
	 * There are four kinds of DP registers:
946 947
	 *
	 * 	IBX PCH
K
Keith Packard 已提交
948 949
	 * 	SNB CPU
	 *	IVB CPU
950 951 952 953 954 955 956 957 958 959
	 * 	CPT PCH
	 *
	 * IBX PCH and CPU are the same for almost everything,
	 * except that the CPU DP PLL is configured in this
	 * register
	 *
	 * CPT PCH is quite different, having many bits moved
	 * to the TRANS_DP_CTL register instead. That
	 * configuration happens (oddly) in ironlake_pch_enable
	 */
960

961 962 963 964
	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
965

966 967
	/* Handle DP bits in common between all three register formats */
	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
968
	intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
969

970 971
	if (intel_dp->has_audio) {
		DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
972
				 pipe_name(crtc->pipe));
C
Chris Wilson 已提交
973
		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
974
		intel_write_eld(&encoder->base, adjusted_mode);
975
	}
976

977
	/* Split out the IBX/CPU vs CPT settings */
978

979
	if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
K
Keith Packard 已提交
980 981 982 983 984 985
		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

986
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
K
Keith Packard 已提交
987 988
			intel_dp->DP |= DP_ENHANCED_FRAMING;

989
		intel_dp->DP |= crtc->pipe << 29;
990
	} else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
991
		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
992
			intel_dp->DP |= intel_dp->color_range;
993 994 995 996 997 998 999

		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF;

1000
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1001 1002
			intel_dp->DP |= DP_ENHANCED_FRAMING;

1003
		if (crtc->pipe == 1)
1004 1005 1006
			intel_dp->DP |= DP_PIPEB_SELECT;
	} else {
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1007
	}
1008

1009
	if (port == PORT_A && !IS_VALLEYVIEW(dev))
1010
		ironlake_set_pll_cpu_edp(intel_dp);
1011 1012
}

1013 1014
#define IDLE_ON_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
#define IDLE_ON_VALUE   	(PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1015

1016 1017
#define IDLE_OFF_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
#define IDLE_OFF_VALUE		(0     | PP_SEQUENCE_NONE | 0                     | 0)
1018

1019 1020
#define IDLE_CYCLE_MASK		(PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
#define IDLE_CYCLE_VALUE	(0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1021

1022
static void wait_panel_status(struct intel_dp *intel_dp,
1023 1024
				       u32 mask,
				       u32 value)
1025
{
1026
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1027
	struct drm_i915_private *dev_priv = dev->dev_private;
1028 1029
	u32 pp_stat_reg, pp_ctrl_reg;

1030 1031
	pp_stat_reg = _pp_stat_reg(intel_dp);
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1032

1033
	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1034 1035 1036
			mask, value,
			I915_READ(pp_stat_reg),
			I915_READ(pp_ctrl_reg));
1037

1038
	if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1039
		DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1040 1041
				I915_READ(pp_stat_reg),
				I915_READ(pp_ctrl_reg));
1042
	}
1043 1044

	DRM_DEBUG_KMS("Wait complete\n");
1045
}
1046

1047
static void wait_panel_on(struct intel_dp *intel_dp)
1048 1049
{
	DRM_DEBUG_KMS("Wait for panel power on\n");
1050
	wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1051 1052
}

1053
static void wait_panel_off(struct intel_dp *intel_dp)
1054 1055
{
	DRM_DEBUG_KMS("Wait for panel power off time\n");
1056
	wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1057 1058
}

1059
static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1060 1061
{
	DRM_DEBUG_KMS("Wait for panel power cycle\n");
1062 1063 1064 1065 1066 1067

	/* When we disable the VDD override bit last we have to do the manual
	 * wait. */
	wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
				       intel_dp->panel_power_cycle_delay);

1068
	wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1069 1070
}

1071
static void wait_backlight_on(struct intel_dp *intel_dp)
1072 1073 1074 1075 1076
{
	wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
				       intel_dp->backlight_on_delay);
}

1077
static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1078 1079 1080 1081
{
	wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
				       intel_dp->backlight_off_delay);
}
1082

1083 1084 1085 1086
/* Read the current pp_control value, unlocking the register if it
 * is locked
 */

1087
static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1088
{
1089 1090 1091
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 control;
1092

1093
	control = I915_READ(_pp_ctrl_reg(intel_dp));
1094 1095 1096
	control &= ~PANEL_UNLOCK_MASK;
	control |= PANEL_UNLOCK_REGS;
	return control;
1097 1098
}

1099
static void edp_panel_vdd_on(struct intel_dp *intel_dp)
1100
{
1101
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1102 1103
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
1104
	u32 pp_stat_reg, pp_ctrl_reg;
1105

1106 1107
	if (!is_edp(intel_dp))
		return;
1108

1109 1110 1111 1112
	WARN(intel_dp->want_panel_vdd,
	     "eDP VDD already requested on\n");

	intel_dp->want_panel_vdd = true;
1113

1114
	if (edp_have_panel_vdd(intel_dp))
1115
		return;
1116

1117 1118
	intel_runtime_pm_get(dev_priv);

1119
	DRM_DEBUG_KMS("Turning eDP VDD on\n");
1120

1121 1122
	if (!edp_have_panel_power(intel_dp))
		wait_panel_power_cycle(intel_dp);
1123

1124
	pp = ironlake_get_pp_control(intel_dp);
1125
	pp |= EDP_FORCE_VDD;
1126

1127 1128
	pp_stat_reg = _pp_stat_reg(intel_dp);
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1129 1130 1131 1132 1133

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
			I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1134 1135 1136
	/*
	 * If the panel wasn't on, delay before accessing aux channel
	 */
1137
	if (!edp_have_panel_power(intel_dp)) {
1138
		DRM_DEBUG_KMS("eDP was not running\n");
1139 1140
		msleep(intel_dp->panel_power_up_delay);
	}
1141 1142
}

1143
static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1144
{
1145
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1146 1147
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
1148
	u32 pp_stat_reg, pp_ctrl_reg;
1149

1150 1151
	WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));

1152
	if (!intel_dp->want_panel_vdd && edp_have_panel_vdd(intel_dp)) {
1153 1154
		DRM_DEBUG_KMS("Turning eDP VDD off\n");

1155
		pp = ironlake_get_pp_control(intel_dp);
1156 1157
		pp &= ~EDP_FORCE_VDD;

1158 1159
		pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
		pp_stat_reg = _pp_stat_reg(intel_dp);
1160 1161 1162

		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1163

1164 1165 1166
		/* Make sure sequencer is idle before allowing subsequent activity */
		DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
		I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
P
Paulo Zanoni 已提交
1167 1168

		if ((pp & POWER_TARGET_ON) == 0)
1169
			intel_dp->last_power_cycle = jiffies;
1170 1171

		intel_runtime_pm_put(dev_priv);
1172 1173
	}
}
1174

1175
static void edp_panel_vdd_work(struct work_struct *__work)
1176 1177 1178
{
	struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
						 struct intel_dp, panel_vdd_work);
1179
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1180

1181
	mutex_lock(&dev->mode_config.mutex);
1182
	edp_panel_vdd_off_sync(intel_dp);
1183
	mutex_unlock(&dev->mode_config.mutex);
1184 1185
}

1186
static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1187
{
1188 1189
	if (!is_edp(intel_dp))
		return;
1190

1191
	WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1192

1193 1194 1195
	intel_dp->want_panel_vdd = false;

	if (sync) {
1196
		edp_panel_vdd_off_sync(intel_dp);
1197 1198 1199 1200 1201 1202 1203 1204 1205
	} else {
		/*
		 * Queue the timer to fire a long
		 * time from now (relative to the power down delay)
		 * to keep the panel power up across a sequence of operations
		 */
		schedule_delayed_work(&intel_dp->panel_vdd_work,
				      msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
	}
1206 1207
}

1208
void intel_edp_panel_on(struct intel_dp *intel_dp)
1209
{
1210
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1211
	struct drm_i915_private *dev_priv = dev->dev_private;
1212
	u32 pp;
1213
	u32 pp_ctrl_reg;
1214

1215
	if (!is_edp(intel_dp))
1216
		return;
1217 1218 1219

	DRM_DEBUG_KMS("Turn eDP power on\n");

1220
	if (edp_have_panel_power(intel_dp)) {
1221
		DRM_DEBUG_KMS("eDP power already on\n");
1222
		return;
1223
	}
1224

1225
	wait_panel_power_cycle(intel_dp);
1226

1227
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1228
	pp = ironlake_get_pp_control(intel_dp);
1229 1230 1231
	if (IS_GEN5(dev)) {
		/* ILK workaround: disable reset around power sequence */
		pp &= ~PANEL_POWER_RESET;
1232 1233
		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1234
	}
1235

1236
	pp |= POWER_TARGET_ON;
1237 1238 1239
	if (!IS_GEN5(dev))
		pp |= PANEL_POWER_RESET;

1240 1241
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1242

1243
	wait_panel_on(intel_dp);
1244
	intel_dp->last_power_on = jiffies;
1245

1246 1247
	if (IS_GEN5(dev)) {
		pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1248 1249
		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1250
	}
1251 1252
}

1253
void intel_edp_panel_off(struct intel_dp *intel_dp)
1254
{
1255
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1256
	struct drm_i915_private *dev_priv = dev->dev_private;
1257
	u32 pp;
1258
	u32 pp_ctrl_reg;
1259

1260 1261
	if (!is_edp(intel_dp))
		return;
1262

1263
	DRM_DEBUG_KMS("Turn eDP power off\n");
1264

1265
	edp_wait_backlight_off(intel_dp);
1266

1267
	pp = ironlake_get_pp_control(intel_dp);
1268 1269
	/* We need to switch off panel power _and_ force vdd, for otherwise some
	 * panels get very unhappy and cease to work. */
1270
	pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1271

1272
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1273 1274 1275

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1276

1277
	intel_dp->last_power_cycle = jiffies;
1278
	wait_panel_off(intel_dp);
1279 1280
}

1281
void intel_edp_backlight_on(struct intel_dp *intel_dp)
1282
{
1283 1284
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
1285 1286
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
1287
	u32 pp_ctrl_reg;
1288

1289 1290 1291
	if (!is_edp(intel_dp))
		return;

1292
	DRM_DEBUG_KMS("\n");
1293 1294 1295 1296 1297 1298
	/*
	 * If we enable the backlight right away following a panel power
	 * on, we may see slight flicker as the panel syncs with the eDP
	 * link.  So delay a bit to make sure the image is solid before
	 * allowing it to appear.
	 */
1299
	wait_backlight_on(intel_dp);
1300
	pp = ironlake_get_pp_control(intel_dp);
1301
	pp |= EDP_BLC_ENABLE;
1302

1303
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1304 1305 1306

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1307

1308
	intel_panel_enable_backlight(intel_dp->attached_connector);
1309 1310
}

1311
void intel_edp_backlight_off(struct intel_dp *intel_dp)
1312
{
1313
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1314 1315
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
1316
	u32 pp_ctrl_reg;
1317

1318 1319 1320
	if (!is_edp(intel_dp))
		return;

1321
	intel_panel_disable_backlight(intel_dp->attached_connector);
1322

1323
	DRM_DEBUG_KMS("\n");
1324
	pp = ironlake_get_pp_control(intel_dp);
1325
	pp &= ~EDP_BLC_ENABLE;
1326

1327
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1328 1329 1330

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1331
	intel_dp->last_backlight_off = jiffies;
1332
}
1333

1334
static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1335
{
1336 1337 1338
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = crtc->dev;
1339 1340 1341
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

1342 1343 1344
	assert_pipe_disabled(dev_priv,
			     to_intel_crtc(crtc)->pipe);

1345 1346
	DRM_DEBUG_KMS("\n");
	dpa_ctl = I915_READ(DP_A);
1347 1348 1349 1350 1351 1352 1353 1354 1355
	WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");

	/* We don't adjust intel_dp->DP while tearing down the link, to
	 * facilitate link retraining (e.g. after hotplug). Hence clear all
	 * enable bits here to ensure that we don't enable too much. */
	intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
	intel_dp->DP |= DP_PLL_ENABLE;
	I915_WRITE(DP_A, intel_dp->DP);
1356 1357
	POSTING_READ(DP_A);
	udelay(200);
1358 1359
}

1360
static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1361
{
1362 1363 1364
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = crtc->dev;
1365 1366 1367
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

1368 1369 1370
	assert_pipe_disabled(dev_priv,
			     to_intel_crtc(crtc)->pipe);

1371
	dpa_ctl = I915_READ(DP_A);
1372 1373 1374 1375 1376 1377 1378
	WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
	     "dp pll off, should be on\n");
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");

	/* We can't rely on the value tracked for the DP register in
	 * intel_dp->DP because link_down must not change that (otherwise link
	 * re-training will fail. */
1379
	dpa_ctl &= ~DP_PLL_ENABLE;
1380
	I915_WRITE(DP_A, dpa_ctl);
1381
	POSTING_READ(DP_A);
1382 1383 1384
	udelay(200);
}

1385
/* If the sink supports it, try to set the power state appropriately */
1386
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414
{
	int ret, i;

	/* Should have a valid DPCD by this point */
	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
		return;

	if (mode != DRM_MODE_DPMS_ON) {
		ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
						  DP_SET_POWER_D3);
		if (ret != 1)
			DRM_DEBUG_DRIVER("failed to write sink power state\n");
	} else {
		/*
		 * When turning on, we need to retry for 1ms to give the sink
		 * time to wake up.
		 */
		for (i = 0; i < 3; i++) {
			ret = intel_dp_aux_native_write_1(intel_dp,
							  DP_SET_POWER,
							  DP_SET_POWER_D0);
			if (ret == 1)
				break;
			msleep(1);
		}
	}
}

1415 1416
static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
				  enum pipe *pipe)
1417
{
1418
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1419
	enum port port = dp_to_dig_port(intel_dp)->port;
1420 1421 1422 1423 1424 1425 1426
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 tmp = I915_READ(intel_dp->output_reg);

	if (!(tmp & DP_PORT_EN))
		return false;

1427
	if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1428
		*pipe = PORT_TO_PIPE_CPT(tmp);
1429
	} else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1430 1431 1432 1433 1434 1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457
		*pipe = PORT_TO_PIPE(tmp);
	} else {
		u32 trans_sel;
		u32 trans_dp;
		int i;

		switch (intel_dp->output_reg) {
		case PCH_DP_B:
			trans_sel = TRANS_DP_PORT_SEL_B;
			break;
		case PCH_DP_C:
			trans_sel = TRANS_DP_PORT_SEL_C;
			break;
		case PCH_DP_D:
			trans_sel = TRANS_DP_PORT_SEL_D;
			break;
		default:
			return true;
		}

		for_each_pipe(i) {
			trans_dp = I915_READ(TRANS_DP_CTL(i));
			if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
				*pipe = i;
				return true;
			}
		}

1458 1459 1460
		DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
			      intel_dp->output_reg);
	}
1461

1462 1463
	return true;
}
1464

1465 1466 1467 1468 1469
static void intel_dp_get_config(struct intel_encoder *encoder,
				struct intel_crtc_config *pipe_config)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	u32 tmp, flags = 0;
1470 1471 1472 1473
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = dp_to_dig_port(intel_dp)->port;
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1474
	int dotclock;
1475

1476 1477 1478 1479 1480 1481
	if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
		tmp = I915_READ(intel_dp->output_reg);
		if (tmp & DP_SYNC_HS_HIGH)
			flags |= DRM_MODE_FLAG_PHSYNC;
		else
			flags |= DRM_MODE_FLAG_NHSYNC;
1482

1483 1484 1485 1486 1487 1488 1489 1490 1491 1492
		if (tmp & DP_SYNC_VS_HIGH)
			flags |= DRM_MODE_FLAG_PVSYNC;
		else
			flags |= DRM_MODE_FLAG_NVSYNC;
	} else {
		tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
		if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
			flags |= DRM_MODE_FLAG_PHSYNC;
		else
			flags |= DRM_MODE_FLAG_NHSYNC;
1493

1494 1495 1496 1497 1498
		if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
			flags |= DRM_MODE_FLAG_PVSYNC;
		else
			flags |= DRM_MODE_FLAG_NVSYNC;
	}
1499 1500

	pipe_config->adjusted_mode.flags |= flags;
1501

1502 1503 1504 1505
	pipe_config->has_dp_encoder = true;

	intel_dp_get_m_n(crtc, pipe_config);

1506
	if (port == PORT_A) {
1507 1508 1509 1510 1511
		if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
			pipe_config->port_clock = 162000;
		else
			pipe_config->port_clock = 270000;
	}
1512 1513 1514 1515 1516 1517 1518

	dotclock = intel_dotclock_calculate(pipe_config->port_clock,
					    &pipe_config->dp_m_n);

	if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
		ironlake_check_encoder_dotclock(pipe_config, dotclock);

1519
	pipe_config->adjusted_mode.crtc_clock = dotclock;
1520

1521 1522 1523 1524 1525 1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539
	if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
	    pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
		/*
		 * This is a big fat ugly hack.
		 *
		 * Some machines in UEFI boot mode provide us a VBT that has 18
		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
		 * unknown we fail to light up. Yet the same BIOS boots up with
		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
		 * max, not what it tells us to use.
		 *
		 * Note: This will still be broken if the eDP panel is not lit
		 * up by the BIOS, and thus we can't get the mode at module
		 * load.
		 */
		DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
			      pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
		dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
	}
1540 1541
}

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Rodrigo Vivi 已提交
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static bool is_edp_psr(struct drm_device *dev)
1543
{
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Rodrigo Vivi 已提交
1544 1545 1546
	struct drm_i915_private *dev_priv = dev->dev_private;

	return dev_priv->psr.sink_support;
1547 1548
}

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1549 1550 1551 1552
static bool intel_edp_is_psr_enabled(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

1553
	if (!HAS_PSR(dev))
R
Rodrigo Vivi 已提交
1554 1555
		return false;

1556
	return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
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1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605
}

static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
				    struct edp_vsc_psr *vsc_psr)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
	u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
	uint32_t *data = (uint32_t *) vsc_psr;
	unsigned int i;

	/* As per BSPec (Pipe Video Data Island Packet), we need to disable
	   the video DIP being updated before program video DIP data buffer
	   registers for DIP being updated. */
	I915_WRITE(ctl_reg, 0);
	POSTING_READ(ctl_reg);

	for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
		if (i < sizeof(struct edp_vsc_psr))
			I915_WRITE(data_reg + i, *data++);
		else
			I915_WRITE(data_reg + i, 0);
	}

	I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
	POSTING_READ(ctl_reg);
}

static void intel_edp_psr_setup(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct edp_vsc_psr psr_vsc;

	if (intel_dp->psr_setup_done)
		return;

	/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
	memset(&psr_vsc, 0, sizeof(psr_vsc));
	psr_vsc.sdp_header.HB0 = 0;
	psr_vsc.sdp_header.HB1 = 0x7;
	psr_vsc.sdp_header.HB2 = 0x2;
	psr_vsc.sdp_header.HB3 = 0x8;
	intel_edp_psr_write_vsc(intel_dp, &psr_vsc);

	/* Avoid continuous PSR exit by masking memup and hpd */
1606
	I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
1607
		   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
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1608 1609 1610 1611 1612 1613 1614 1615

	intel_dp->psr_setup_done = true;
}

static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
1616
	uint32_t aux_clock_divider = get_aux_clock_divider(intel_dp, 0);
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Rodrigo Vivi 已提交
1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630
	int precharge = 0x3;
	int msg_size = 5;       /* Header(4) + Message(1) */

	/* Enable PSR in sink */
	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT)
		intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
					    DP_PSR_ENABLE &
					    ~DP_PSR_MAIN_LINK_ACTIVE);
	else
		intel_dp_aux_native_write_1(intel_dp, DP_PSR_EN_CFG,
					    DP_PSR_ENABLE |
					    DP_PSR_MAIN_LINK_ACTIVE);

	/* Setup AUX registers */
1631 1632 1633
	I915_WRITE(EDP_PSR_AUX_DATA1(dev), EDP_PSR_DPCD_COMMAND);
	I915_WRITE(EDP_PSR_AUX_DATA2(dev), EDP_PSR_DPCD_NORMAL_OPERATION);
	I915_WRITE(EDP_PSR_AUX_CTL(dev),
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		   DP_AUX_CH_CTL_TIME_OUT_400us |
		   (msg_size << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
		   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
		   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
}

static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t max_sleep_time = 0x1f;
	uint32_t idle_frames = 1;
	uint32_t val = 0x0;
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	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
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	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
		val |= EDP_PSR_LINK_STANDBY;
		val |= EDP_PSR_TP2_TP3_TIME_0us;
		val |= EDP_PSR_TP1_TIME_0us;
		val |= EDP_PSR_SKIP_AUX_EXIT;
	} else
		val |= EDP_PSR_LINK_DISABLE;

1657
	I915_WRITE(EDP_PSR_CTL(dev), val |
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		   IS_BROADWELL(dev) ? 0 : link_entry_time |
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		   max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
		   idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
		   EDP_PSR_ENABLE);
}

1664 1665 1666 1667 1668 1669 1670 1671 1672 1673
static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dig_port->base.base.crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
	struct drm_i915_gem_object *obj = to_intel_framebuffer(crtc->fb)->obj;
	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;

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	dev_priv->psr.source_ok = false;

1676
	if (!HAS_PSR(dev)) {
1677 1678 1679 1680 1681 1682 1683 1684 1685 1686
		DRM_DEBUG_KMS("PSR not supported on this platform\n");
		return false;
	}

	if ((intel_encoder->type != INTEL_OUTPUT_EDP) ||
	    (dig_port->port != PORT_A)) {
		DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
		return false;
	}

1687 1688 1689 1690 1691
	if (!i915_enable_psr) {
		DRM_DEBUG_KMS("PSR disable by flag\n");
		return false;
	}

1692 1693 1694 1695 1696 1697 1698
	crtc = dig_port->base.base.crtc;
	if (crtc == NULL) {
		DRM_DEBUG_KMS("crtc not active for PSR\n");
		return false;
	}

	intel_crtc = to_intel_crtc(crtc);
1699
	if (!intel_crtc_active(crtc)) {
1700 1701 1702 1703
		DRM_DEBUG_KMS("crtc not active for PSR\n");
		return false;
	}

1704
	obj = to_intel_framebuffer(crtc->fb)->obj;
1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721
	if (obj->tiling_mode != I915_TILING_X ||
	    obj->fence_reg == I915_FENCE_REG_NONE) {
		DRM_DEBUG_KMS("PSR condition failed: fb not tiled or fenced\n");
		return false;
	}

	if (I915_READ(SPRCTL(intel_crtc->pipe)) & SPRITE_ENABLE) {
		DRM_DEBUG_KMS("PSR condition failed: Sprite is Enabled\n");
		return false;
	}

	if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
	    S3D_ENABLE) {
		DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
		return false;
	}

1722
	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
1723 1724 1725 1726
		DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
		return false;
	}

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	dev_priv->psr.source_ok = true;
1728 1729 1730
	return true;
}

1731
static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
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{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

1735 1736
	if (!intel_edp_psr_match_conditions(intel_dp) ||
	    intel_edp_is_psr_enabled(dev))
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		return;

	/* Setup PSR once */
	intel_edp_psr_setup(intel_dp);

	/* Enable PSR on the panel */
	intel_edp_psr_enable_sink(intel_dp);

	/* Enable PSR on the host */
	intel_edp_psr_enable_source(intel_dp);
}

1749 1750 1751 1752 1753 1754 1755 1756 1757
void intel_edp_psr_enable(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

	if (intel_edp_psr_match_conditions(intel_dp) &&
	    !intel_edp_is_psr_enabled(dev))
		intel_edp_psr_do_enable(intel_dp);
}

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void intel_edp_psr_disable(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (!intel_edp_is_psr_enabled(dev))
		return;

1766 1767
	I915_WRITE(EDP_PSR_CTL(dev),
		   I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
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	/* Wait till PSR is idle */
1770
	if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
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		       EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
		DRM_ERROR("Timed out waiting for PSR Idle State\n");
}

1775 1776 1777 1778 1779 1780 1781 1782 1783
void intel_edp_psr_update(struct drm_device *dev)
{
	struct intel_encoder *encoder;
	struct intel_dp *intel_dp = NULL;

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head)
		if (encoder->type == INTEL_OUTPUT_EDP) {
			intel_dp = enc_to_intel_dp(&encoder->base);

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			if (!is_edp_psr(dev))
1785 1786 1787 1788 1789 1790 1791 1792 1793 1794
				return;

			if (!intel_edp_psr_match_conditions(intel_dp))
				intel_edp_psr_disable(intel_dp);
			else
				if (!intel_edp_is_psr_enabled(dev))
					intel_edp_psr_do_enable(intel_dp);
		}
}

1795
static void intel_disable_dp(struct intel_encoder *encoder)
1796
{
1797
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1798 1799
	enum port port = dp_to_dig_port(intel_dp)->port;
	struct drm_device *dev = encoder->base.dev;
1800 1801 1802

	/* Make sure the panel is off before trying to change the mode. But also
	 * ensure that we have vdd while we switch off the panel. */
1803
	intel_edp_backlight_off(intel_dp);
1804
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
1805
	intel_edp_panel_off(intel_dp);
1806 1807

	/* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1808
	if (!(port == PORT_A || IS_VALLEYVIEW(dev)))
1809
		intel_dp_link_down(intel_dp);
1810 1811
}

1812
static void intel_post_disable_dp(struct intel_encoder *encoder)
1813
{
1814
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1815
	enum port port = dp_to_dig_port(intel_dp)->port;
1816
	struct drm_device *dev = encoder->base.dev;
1817

1818
	if (port == PORT_A || IS_VALLEYVIEW(dev)) {
1819
		intel_dp_link_down(intel_dp);
1820 1821
		if (!IS_VALLEYVIEW(dev))
			ironlake_edp_pll_off(intel_dp);
1822
	}
1823 1824
}

1825
static void intel_enable_dp(struct intel_encoder *encoder)
1826
{
1827 1828 1829 1830
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1831

1832 1833
	if (WARN_ON(dp_reg & DP_PORT_EN))
		return;
1834

1835
	edp_panel_vdd_on(intel_dp);
1836
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1837
	intel_dp_start_link_train(intel_dp);
1838 1839
	intel_edp_panel_on(intel_dp);
	edp_panel_vdd_off(intel_dp, true);
1840
	intel_dp_complete_link_train(intel_dp);
1841
	intel_dp_stop_link_train(intel_dp);
1842
}
1843

1844 1845
static void g4x_enable_dp(struct intel_encoder *encoder)
{
1846 1847
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

1848
	intel_enable_dp(encoder);
1849
	intel_edp_backlight_on(intel_dp);
1850
}
1851

1852 1853
static void vlv_enable_dp(struct intel_encoder *encoder)
{
1854 1855
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

1856
	intel_edp_backlight_on(intel_dp);
1857 1858
}

1859
static void g4x_pre_enable_dp(struct intel_encoder *encoder)
1860 1861 1862 1863 1864 1865 1866 1867 1868
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);

	if (dport->port == PORT_A)
		ironlake_edp_pll_on(intel_dp);
}

static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1869
{
1870
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1871
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1872
	struct drm_device *dev = encoder->base.dev;
1873
	struct drm_i915_private *dev_priv = dev->dev_private;
1874
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1875
	enum dpio_channel port = vlv_dport_to_channel(dport);
1876
	int pipe = intel_crtc->pipe;
1877
	struct edp_power_seq power_seq;
1878
	u32 val;
1879

1880
	mutex_lock(&dev_priv->dpio_lock);
1881

1882
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1883 1884 1885 1886 1887 1888
	val = 0;
	if (pipe)
		val |= (1<<21);
	else
		val &= ~(1<<21);
	val |= 0x001000c4;
1889 1890 1891
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1892

1893 1894
	mutex_unlock(&dev_priv->dpio_lock);

1895 1896 1897 1898 1899
	/* init power sequencer on this pipe and port */
	intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
						      &power_seq);

1900 1901
	intel_enable_dp(encoder);

1902
	vlv_wait_port_ready(dev_priv, dport);
1903 1904
}

1905
static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1906 1907 1908 1909
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1910 1911
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
1912
	enum dpio_channel port = vlv_dport_to_channel(dport);
1913
	int pipe = intel_crtc->pipe;
1914 1915

	/* Program Tx lane resets to default */
1916
	mutex_lock(&dev_priv->dpio_lock);
1917
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1918 1919
			 DPIO_PCS_TX_LANE2_RESET |
			 DPIO_PCS_TX_LANE1_RESET);
1920
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1921 1922 1923 1924 1925 1926
			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
				 DPIO_PCS_CLK_SOFT_RESET);

	/* Fix up inter-pair skew failure */
1927 1928 1929
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1930
	mutex_unlock(&dev_priv->dpio_lock);
1931 1932 1933
}

/*
1934 1935
 * Native read with retry for link status and receiver capability reads for
 * cases where the sink may still be asleep.
1936 1937
 */
static bool
1938 1939
intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
			       uint8_t *recv, int recv_bytes)
1940
{
1941 1942
	int ret, i;

1943 1944 1945 1946
	/*
	 * Sinks are *supposed* to come up within 1ms from an off state,
	 * but we're also supposed to retry 3 times per the spec.
	 */
1947
	for (i = 0; i < 3; i++) {
1948 1949 1950
		ret = intel_dp_aux_native_read(intel_dp, address, recv,
					       recv_bytes);
		if (ret == recv_bytes)
1951 1952 1953
			return true;
		msleep(1);
	}
1954

1955
	return false;
1956 1957 1958 1959 1960 1961 1962
}

/*
 * Fetch AUX CH registers 0x202 - 0x207 which contain
 * link status information
 */
static bool
1963
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1964
{
1965 1966
	return intel_dp_aux_native_read_retry(intel_dp,
					      DP_LANE0_1_STATUS,
1967
					      link_status,
1968
					      DP_LINK_STATUS_SIZE);
1969 1970 1971 1972 1973 1974 1975 1976
}

/*
 * These are source-specific values; current Intel hardware supports
 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
 */

static uint8_t
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intel_dp_voltage_max(struct intel_dp *intel_dp)
1978
{
1979
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1980
	enum port port = dp_to_dig_port(intel_dp)->port;
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1982
	if (IS_VALLEYVIEW(dev) || IS_BROADWELL(dev))
1983
		return DP_TRAIN_VOLTAGE_SWING_1200;
1984
	else if (IS_GEN7(dev) && port == PORT_A)
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		return DP_TRAIN_VOLTAGE_SWING_800;
1986
	else if (HAS_PCH_CPT(dev) && port != PORT_A)
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		return DP_TRAIN_VOLTAGE_SWING_1200;
	else
		return DP_TRAIN_VOLTAGE_SWING_800;
}

static uint8_t
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
{
1995
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1996
	enum port port = dp_to_dig_port(intel_dp)->port;
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1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009
	if (IS_BROADWELL(dev)) {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
	} else if (IS_HASWELL(dev)) {
2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_9_5;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032
	} else if (IS_VALLEYVIEW(dev)) {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_9_5;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
2033
	} else if (IS_GEN7(dev) && port == PORT_A) {
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		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_600:
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
	} else {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
2055 2056 2057
	}
}

2058 2059 2060 2061 2062
static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2063 2064
	struct intel_crtc *intel_crtc =
		to_intel_crtc(dport->base.base.crtc);
2065 2066 2067
	unsigned long demph_reg_value, preemph_reg_value,
		uniqtranscale_reg_value;
	uint8_t train_set = intel_dp->train_set[0];
2068
	enum dpio_channel port = vlv_dport_to_channel(dport);
2069
	int pipe = intel_crtc->pipe;
2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143

	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
	case DP_TRAIN_PRE_EMPHASIS_0:
		preemph_reg_value = 0x0004000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x552AB83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5548B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_800:
			demph_reg_value = 0x2B245555;
			uniqtranscale_reg_value = 0x5560B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_1200:
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x5598DA3A;
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_3_5:
		preemph_reg_value = 0x0002000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5552B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			demph_reg_value = 0x2B404848;
			uniqtranscale_reg_value = 0x5580B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_800:
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_6:
		preemph_reg_value = 0x0000000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x2B305555;
			uniqtranscale_reg_value = 0x5570B83A;
			break;
		case DP_TRAIN_VOLTAGE_SWING_600:
			demph_reg_value = 0x2B2B4040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	case DP_TRAIN_PRE_EMPHASIS_9_5:
		preemph_reg_value = 0x0006000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			demph_reg_value = 0x1B405555;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	default:
		return 0;
	}

2144
	mutex_lock(&dev_priv->dpio_lock);
2145 2146 2147
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2148
			 uniqtranscale_reg_value);
2149 2150 2151 2152
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2153
	mutex_unlock(&dev_priv->dpio_lock);
2154 2155 2156 2157

	return 0;
}

2158
static void
J
Jani Nikula 已提交
2159 2160
intel_get_adjust_train(struct intel_dp *intel_dp,
		       const uint8_t link_status[DP_LINK_STATUS_SIZE])
2161 2162 2163 2164
{
	uint8_t v = 0;
	uint8_t p = 0;
	int lane;
K
Keith Packard 已提交
2165 2166
	uint8_t voltage_max;
	uint8_t preemph_max;
2167

2168
	for (lane = 0; lane < intel_dp->lane_count; lane++) {
2169 2170
		uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
		uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
2171 2172 2173 2174 2175 2176 2177

		if (this_v > v)
			v = this_v;
		if (this_p > p)
			p = this_p;
	}

K
Keith Packard 已提交
2178
	voltage_max = intel_dp_voltage_max(intel_dp);
2179 2180
	if (v >= voltage_max)
		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
2181

K
Keith Packard 已提交
2182 2183 2184
	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
	if (p >= preemph_max)
		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
2185 2186

	for (lane = 0; lane < 4; lane++)
2187
		intel_dp->train_set[lane] = v | p;
2188 2189 2190
}

static uint32_t
2191
intel_gen4_signal_levels(uint8_t train_set)
2192
{
2193
	uint32_t	signal_levels = 0;
2194

2195
	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206 2207 2208 2209
	case DP_TRAIN_VOLTAGE_SWING_400:
	default:
		signal_levels |= DP_VOLTAGE_0_4;
		break;
	case DP_TRAIN_VOLTAGE_SWING_600:
		signal_levels |= DP_VOLTAGE_0_6;
		break;
	case DP_TRAIN_VOLTAGE_SWING_800:
		signal_levels |= DP_VOLTAGE_0_8;
		break;
	case DP_TRAIN_VOLTAGE_SWING_1200:
		signal_levels |= DP_VOLTAGE_1_2;
		break;
	}
2210
	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227
	case DP_TRAIN_PRE_EMPHASIS_0:
	default:
		signal_levels |= DP_PRE_EMPHASIS_0;
		break;
	case DP_TRAIN_PRE_EMPHASIS_3_5:
		signal_levels |= DP_PRE_EMPHASIS_3_5;
		break;
	case DP_TRAIN_PRE_EMPHASIS_6:
		signal_levels |= DP_PRE_EMPHASIS_6;
		break;
	case DP_TRAIN_PRE_EMPHASIS_9_5:
		signal_levels |= DP_PRE_EMPHASIS_9_5;
		break;
	}
	return signal_levels;
}

2228 2229 2230 2231
/* Gen6's DP voltage swing and pre-emphasis control */
static uint32_t
intel_gen6_edp_signal_levels(uint8_t train_set)
{
2232 2233 2234
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
2235
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
2236 2237 2238 2239
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
2240
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
2241 2242
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
		return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
2243
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
2244 2245
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
2246
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
2247 2248
	case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
2249
	default:
2250 2251 2252
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
2253 2254 2255
	}
}

K
Keith Packard 已提交
2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271 2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286
/* Gen7's DP voltage swing and pre-emphasis control */
static uint32_t
intel_gen7_edp_signal_levels(uint8_t train_set)
{
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_400MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
		return EDP_LINK_TRAIN_400MV_6DB_IVB;

	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_600MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_600MV_3_5DB_IVB;

	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_800MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_800MV_3_5DB_IVB;

	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_500MV_0DB_IVB;
	}
}

2287 2288
/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
static uint32_t
2289
intel_hsw_signal_levels(uint8_t train_set)
2290
{
2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_400MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_400MV_3_5DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
		return DDI_BUF_EMP_400MV_6DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
		return DDI_BUF_EMP_400MV_9_5DB_HSW;
2302

2303 2304 2305 2306 2307 2308
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_600MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_600MV_3_5DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
		return DDI_BUF_EMP_600MV_6DB_HSW;
2309

2310 2311 2312 2313 2314 2315 2316 2317
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_800MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_800MV_3_5DB_HSW;
	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return DDI_BUF_EMP_400MV_0DB_HSW;
2318 2319 2320
	}
}

2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355
static uint32_t
intel_bdw_signal_levels(uint8_t train_set)
{
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_400MV_0DB_BDW;	/* Sel0 */
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_400MV_3_5DB_BDW;	/* Sel1 */
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
		return DDI_BUF_EMP_400MV_6DB_BDW;	/* Sel2 */

	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_600MV_0DB_BDW;	/* Sel3 */
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_600MV_3_5DB_BDW;	/* Sel4 */
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
		return DDI_BUF_EMP_600MV_6DB_BDW;	/* Sel5 */

	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_800MV_0DB_BDW;	/* Sel6 */
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_800MV_3_5DB_BDW;	/* Sel7 */

	case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_1200MV_0DB_BDW;	/* Sel8 */

	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return DDI_BUF_EMP_400MV_0DB_BDW;	/* Sel0 */
	}
}

2356 2357 2358 2359 2360
/* Properly updates "DP" with the correct signal levels. */
static void
intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2361
	enum port port = intel_dig_port->port;
2362 2363 2364 2365
	struct drm_device *dev = intel_dig_port->base.base.dev;
	uint32_t signal_levels, mask;
	uint8_t train_set = intel_dp->train_set[0];

2366 2367 2368 2369
	if (IS_BROADWELL(dev)) {
		signal_levels = intel_bdw_signal_levels(train_set);
		mask = DDI_BUF_EMP_MASK;
	} else if (IS_HASWELL(dev)) {
2370 2371
		signal_levels = intel_hsw_signal_levels(train_set);
		mask = DDI_BUF_EMP_MASK;
2372 2373 2374
	} else if (IS_VALLEYVIEW(dev)) {
		signal_levels = intel_vlv_signal_levels(intel_dp);
		mask = 0;
2375
	} else if (IS_GEN7(dev) && port == PORT_A) {
2376 2377
		signal_levels = intel_gen7_edp_signal_levels(train_set);
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
2378
	} else if (IS_GEN6(dev) && port == PORT_A) {
2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390
		signal_levels = intel_gen6_edp_signal_levels(train_set);
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
	} else {
		signal_levels = intel_gen4_signal_levels(train_set);
		mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
	}

	DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);

	*DP = (*DP & ~mask) | signal_levels;
}

2391
static bool
C
Chris Wilson 已提交
2392
intel_dp_set_link_train(struct intel_dp *intel_dp,
2393
			uint32_t *DP,
2394
			uint8_t dp_train_pat)
2395
{
2396 2397
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
2398
	struct drm_i915_private *dev_priv = dev->dev_private;
2399
	enum port port = intel_dig_port->port;
2400 2401
	uint8_t buf[sizeof(intel_dp->train_set) + 1];
	int ret, len;
2402

2403
	if (HAS_DDI(dev)) {
2404
		uint32_t temp = I915_READ(DP_TP_CTL(port));
2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426

		if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
			temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
		else
			temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;

		temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;

			break;
		case DP_TRAINING_PATTERN_1:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
			break;
		case DP_TRAINING_PATTERN_2:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
			break;
		case DP_TRAINING_PATTERN_3:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
			break;
		}
2427
		I915_WRITE(DP_TP_CTL(port), temp);
2428

2429
	} else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2430
		*DP &= ~DP_LINK_TRAIN_MASK_CPT;
2431 2432 2433

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
2434
			*DP |= DP_LINK_TRAIN_OFF_CPT;
2435 2436
			break;
		case DP_TRAINING_PATTERN_1:
2437
			*DP |= DP_LINK_TRAIN_PAT_1_CPT;
2438 2439
			break;
		case DP_TRAINING_PATTERN_2:
2440
			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
2441 2442 2443
			break;
		case DP_TRAINING_PATTERN_3:
			DRM_ERROR("DP training pattern 3 not supported\n");
2444
			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
2445 2446 2447 2448
			break;
		}

	} else {
2449
		*DP &= ~DP_LINK_TRAIN_MASK;
2450 2451 2452

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
2453
			*DP |= DP_LINK_TRAIN_OFF;
2454 2455
			break;
		case DP_TRAINING_PATTERN_1:
2456
			*DP |= DP_LINK_TRAIN_PAT_1;
2457 2458
			break;
		case DP_TRAINING_PATTERN_2:
2459
			*DP |= DP_LINK_TRAIN_PAT_2;
2460 2461 2462
			break;
		case DP_TRAINING_PATTERN_3:
			DRM_ERROR("DP training pattern 3 not supported\n");
2463
			*DP |= DP_LINK_TRAIN_PAT_2;
2464 2465 2466 2467
			break;
		}
	}

2468
	I915_WRITE(intel_dp->output_reg, *DP);
C
Chris Wilson 已提交
2469
	POSTING_READ(intel_dp->output_reg);
2470

2471 2472
	buf[0] = dp_train_pat;
	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
2473
	    DP_TRAINING_PATTERN_DISABLE) {
2474 2475 2476 2477 2478 2479
		/* don't write DP_TRAINING_LANEx_SET on disable */
		len = 1;
	} else {
		/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
		memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
		len = intel_dp->lane_count + 1;
2480
	}
2481

2482 2483 2484 2485
	ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_PATTERN_SET,
					buf, len);

	return ret == len;
2486 2487
}

2488 2489 2490 2491
static bool
intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
			uint8_t dp_train_pat)
{
2492
	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
2493 2494 2495 2496 2497 2498
	intel_dp_set_signal_levels(intel_dp, DP);
	return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
}

static bool
intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
J
Jani Nikula 已提交
2499
			   const uint8_t link_status[DP_LINK_STATUS_SIZE])
2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	intel_get_adjust_train(intel_dp, link_status);
	intel_dp_set_signal_levels(intel_dp, DP);

	I915_WRITE(intel_dp->output_reg, *DP);
	POSTING_READ(intel_dp->output_reg);

	ret = intel_dp_aux_native_write(intel_dp, DP_TRAINING_LANE0_SET,
					intel_dp->train_set,
					intel_dp->lane_count);

	return ret == intel_dp->lane_count;
}

2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549
static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;
	uint32_t val;

	if (!HAS_DDI(dev))
		return;

	val = I915_READ(DP_TP_CTL(port));
	val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
	val |= DP_TP_CTL_LINK_TRAIN_IDLE;
	I915_WRITE(DP_TP_CTL(port), val);

	/*
	 * On PORT_A we can have only eDP in SST mode. There the only reason
	 * we need to set idle transmission mode is to work around a HW issue
	 * where we enable the pipe while not in idle link-training mode.
	 * In this case there is requirement to wait for a minimum number of
	 * idle patterns to be sent.
	 */
	if (port == PORT_A)
		return;

	if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
		     1))
		DRM_ERROR("Timed out waiting for DP idle patterns\n");
}

2550
/* Enable corresponding port and start training pattern 1 */
2551
void
2552
intel_dp_start_link_train(struct intel_dp *intel_dp)
2553
{
2554
	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
2555
	struct drm_device *dev = encoder->dev;
2556 2557
	int i;
	uint8_t voltage;
2558
	int voltage_tries, loop_tries;
C
Chris Wilson 已提交
2559
	uint32_t DP = intel_dp->DP;
2560
	uint8_t link_config[2];
2561

P
Paulo Zanoni 已提交
2562
	if (HAS_DDI(dev))
2563 2564
		intel_ddi_prepare_link_retrain(encoder);

2565
	/* Write the link configuration data */
2566 2567 2568 2569 2570 2571 2572 2573 2574
	link_config[0] = intel_dp->link_bw;
	link_config[1] = intel_dp->lane_count;
	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
	intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, link_config, 2);

	link_config[0] = 0;
	link_config[1] = DP_SET_ANSI_8B10B;
	intel_dp_aux_native_write(intel_dp, DP_DOWNSPREAD_CTRL, link_config, 2);
2575 2576

	DP |= DP_PORT_EN;
K
Keith Packard 已提交
2577

2578 2579 2580 2581 2582 2583 2584 2585
	/* clock recovery */
	if (!intel_dp_reset_link_train(intel_dp, &DP,
				       DP_TRAINING_PATTERN_1 |
				       DP_LINK_SCRAMBLING_DISABLE)) {
		DRM_ERROR("failed to enable link training\n");
		return;
	}

2586
	voltage = 0xff;
2587 2588
	voltage_tries = 0;
	loop_tries = 0;
2589
	for (;;) {
2590
		uint8_t link_status[DP_LINK_STATUS_SIZE];
2591

2592
		drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
2593 2594
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
2595
			break;
2596
		}
2597

2598
		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2599
			DRM_DEBUG_KMS("clock recovery OK\n");
2600 2601 2602 2603 2604 2605
			break;
		}

		/* Check to see if we've tried the max voltage */
		for (i = 0; i < intel_dp->lane_count; i++)
			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
2606
				break;
2607
		if (i == intel_dp->lane_count) {
2608 2609
			++loop_tries;
			if (loop_tries == 5) {
2610
				DRM_ERROR("too many full retries, give up\n");
2611 2612
				break;
			}
2613 2614 2615
			intel_dp_reset_link_train(intel_dp, &DP,
						  DP_TRAINING_PATTERN_1 |
						  DP_LINK_SCRAMBLING_DISABLE);
2616 2617 2618
			voltage_tries = 0;
			continue;
		}
2619

2620
		/* Check to see if we've tried the same voltage 5 times */
2621
		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
2622
			++voltage_tries;
2623
			if (voltage_tries == 5) {
2624
				DRM_ERROR("too many voltage retries, give up\n");
2625 2626 2627 2628 2629
				break;
			}
		} else
			voltage_tries = 0;
		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
2630

2631 2632 2633 2634 2635
		/* Update training set as requested by target */
		if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
			DRM_ERROR("failed to update link training\n");
			break;
		}
2636 2637
	}

2638 2639 2640
	intel_dp->DP = DP;
}

2641
void
2642 2643 2644
intel_dp_complete_link_train(struct intel_dp *intel_dp)
{
	bool channel_eq = false;
2645
	int tries, cr_tries;
2646 2647
	uint32_t DP = intel_dp->DP;

2648
	/* channel equalization */
2649 2650 2651 2652 2653 2654 2655
	if (!intel_dp_set_link_train(intel_dp, &DP,
				     DP_TRAINING_PATTERN_2 |
				     DP_LINK_SCRAMBLING_DISABLE)) {
		DRM_ERROR("failed to start channel equalization\n");
		return;
	}

2656
	tries = 0;
2657
	cr_tries = 0;
2658 2659
	channel_eq = false;
	for (;;) {
2660
		uint8_t link_status[DP_LINK_STATUS_SIZE];
2661

2662 2663 2664 2665 2666
		if (cr_tries > 5) {
			DRM_ERROR("failed to train DP, aborting\n");
			break;
		}

2667
		drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
2668 2669
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
2670
			break;
2671
		}
2672

2673
		/* Make sure clock is still ok */
2674
		if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
2675
			intel_dp_start_link_train(intel_dp);
2676 2677 2678
			intel_dp_set_link_train(intel_dp, &DP,
						DP_TRAINING_PATTERN_2 |
						DP_LINK_SCRAMBLING_DISABLE);
2679 2680 2681 2682
			cr_tries++;
			continue;
		}

2683
		if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2684 2685 2686
			channel_eq = true;
			break;
		}
2687

2688 2689 2690 2691
		/* Try 5 times, then try clock recovery if that fails */
		if (tries > 5) {
			intel_dp_link_down(intel_dp);
			intel_dp_start_link_train(intel_dp);
2692 2693 2694
			intel_dp_set_link_train(intel_dp, &DP,
						DP_TRAINING_PATTERN_2 |
						DP_LINK_SCRAMBLING_DISABLE);
2695 2696 2697 2698
			tries = 0;
			cr_tries++;
			continue;
		}
2699

2700 2701 2702 2703 2704
		/* Update training set as requested by target */
		if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
			DRM_ERROR("failed to update link training\n");
			break;
		}
2705
		++tries;
2706
	}
2707

2708 2709 2710 2711
	intel_dp_set_idle_link_train(intel_dp);

	intel_dp->DP = DP;

2712
	if (channel_eq)
M
Masanari Iida 已提交
2713
		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
2714

2715 2716 2717 2718
}

void intel_dp_stop_link_train(struct intel_dp *intel_dp)
{
2719
	intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2720
				DP_TRAINING_PATTERN_DISABLE);
2721 2722 2723
}

static void
C
Chris Wilson 已提交
2724
intel_dp_link_down(struct intel_dp *intel_dp)
2725
{
2726
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2727
	enum port port = intel_dig_port->port;
2728
	struct drm_device *dev = intel_dig_port->base.base.dev;
2729
	struct drm_i915_private *dev_priv = dev->dev_private;
2730 2731
	struct intel_crtc *intel_crtc =
		to_intel_crtc(intel_dig_port->base.base.crtc);
C
Chris Wilson 已提交
2732
	uint32_t DP = intel_dp->DP;
2733

2734 2735 2736 2737 2738 2739 2740 2741 2742 2743 2744 2745 2746 2747 2748
	/*
	 * DDI code has a strict mode set sequence and we should try to respect
	 * it, otherwise we might hang the machine in many different ways. So we
	 * really should be disabling the port only on a complete crtc_disable
	 * sequence. This function is just called under two conditions on DDI
	 * code:
	 * - Link train failed while doing crtc_enable, and on this case we
	 *   really should respect the mode set sequence and wait for a
	 *   crtc_disable.
	 * - Someone turned the monitor off and intel_dp_check_link_status
	 *   called us. We don't need to disable the whole port on this case, so
	 *   when someone turns the monitor on again,
	 *   intel_ddi_prepare_link_retrain will take care of redoing the link
	 *   train.
	 */
P
Paulo Zanoni 已提交
2749
	if (HAS_DDI(dev))
2750 2751
		return;

2752
	if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2753 2754
		return;

2755
	DRM_DEBUG_KMS("\n");
2756

2757
	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
2758
		DP &= ~DP_LINK_TRAIN_MASK_CPT;
C
Chris Wilson 已提交
2759
		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2760 2761
	} else {
		DP &= ~DP_LINK_TRAIN_MASK;
C
Chris Wilson 已提交
2762
		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2763
	}
2764
	POSTING_READ(intel_dp->output_reg);
2765

2766 2767
	/* We don't really know why we're doing this */
	intel_wait_for_vblank(dev, intel_crtc->pipe);
2768

2769
	if (HAS_PCH_IBX(dev) &&
2770
	    I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2771
		struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2772

2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786
		/* Hardware workaround: leaving our transcoder select
		 * set to transcoder B while it's off will prevent the
		 * corresponding HDMI output on transcoder A.
		 *
		 * Combine this with another hardware workaround:
		 * transcoder select bit can only be cleared while the
		 * port is enabled.
		 */
		DP &= ~DP_PIPEB_SELECT;
		I915_WRITE(intel_dp->output_reg, DP);

		/* Changes to enable or select take place the vblank
		 * after being written.
		 */
2787 2788 2789 2790
		if (WARN_ON(crtc == NULL)) {
			/* We should never try to disable a port without a crtc
			 * attached. For paranoia keep the code around for a
			 * bit. */
2791 2792 2793
			POSTING_READ(intel_dp->output_reg);
			msleep(50);
		} else
2794
			intel_wait_for_vblank(dev, intel_crtc->pipe);
2795 2796
	}

2797
	DP &= ~DP_AUDIO_OUTPUT_ENABLE;
C
Chris Wilson 已提交
2798 2799
	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);
2800
	msleep(intel_dp->panel_power_down_delay);
2801 2802
}

2803 2804
static bool
intel_dp_get_dpcd(struct intel_dp *intel_dp)
2805
{
R
Rodrigo Vivi 已提交
2806 2807 2808 2809
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

2810 2811
	char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];

2812
	if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2813 2814
					   sizeof(intel_dp->dpcd)) == 0)
		return false; /* aux transfer failed */
2815

2816 2817 2818 2819
	hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
			   32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
	DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);

2820 2821 2822
	if (intel_dp->dpcd[DP_DPCD_REV] == 0)
		return false; /* DPCD not present */

2823 2824
	/* Check if the panel supports PSR */
	memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
2825 2826 2827 2828
	if (is_edp(intel_dp)) {
		intel_dp_aux_native_read_retry(intel_dp, DP_PSR_SUPPORT,
					       intel_dp->psr_dpcd,
					       sizeof(intel_dp->psr_dpcd));
R
Rodrigo Vivi 已提交
2829 2830
		if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
			dev_priv->psr.sink_support = true;
2831
			DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
R
Rodrigo Vivi 已提交
2832
		}
2833 2834
	}

2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846 2847
	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
	      DP_DWN_STRM_PORT_PRESENT))
		return true; /* native DP sink */

	if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
		return true; /* no per-port downstream info */

	if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
					   intel_dp->downstream_ports,
					   DP_MAX_DOWNSTREAM_PORTS) == 0)
		return false; /* downstream port status fetch failed */

	return true;
2848 2849
}

2850 2851 2852 2853 2854 2855 2856 2857
static void
intel_dp_probe_oui(struct intel_dp *intel_dp)
{
	u8 buf[3];

	if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
		return;

2858
	edp_panel_vdd_on(intel_dp);
D
Daniel Vetter 已提交
2859

2860 2861 2862 2863 2864 2865 2866
	if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
		DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);

	if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
		DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);
D
Daniel Vetter 已提交
2867

2868
	edp_panel_vdd_off(intel_dp, false);
2869 2870
}

2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888
static bool
intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
	int ret;

	ret = intel_dp_aux_native_read_retry(intel_dp,
					     DP_DEVICE_SERVICE_IRQ_VECTOR,
					     sink_irq_vector, 1);
	if (!ret)
		return false;

	return true;
}

static void
intel_dp_handle_test_request(struct intel_dp *intel_dp)
{
	/* NAK by default */
2889
	intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2890 2891
}

2892 2893 2894 2895 2896 2897 2898 2899 2900
/*
 * According to DP spec
 * 5.1.2:
 *  1. Read DPCD
 *  2. Configure link according to Receiver Capabilities
 *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
 *  4. Check link status on receipt of hot-plug interrupt
 */

P
Paulo Zanoni 已提交
2901
void
C
Chris Wilson 已提交
2902
intel_dp_check_link_status(struct intel_dp *intel_dp)
2903
{
2904
	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2905
	u8 sink_irq_vector;
2906
	u8 link_status[DP_LINK_STATUS_SIZE];
2907

2908
	if (!intel_encoder->connectors_active)
2909
		return;
2910

2911
	if (WARN_ON(!intel_encoder->base.crtc))
2912 2913
		return;

2914
	/* Try to read receiver status if the link appears to be up */
2915
	if (!intel_dp_get_link_status(intel_dp, link_status)) {
2916 2917 2918
		return;
	}

2919
	/* Now read the DPCD to see if it's actually running */
2920
	if (!intel_dp_get_dpcd(intel_dp)) {
2921 2922 2923
		return;
	}

2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937
	/* Try to read the source of the interrupt */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
		/* Clear interrupt source */
		intel_dp_aux_native_write_1(intel_dp,
					    DP_DEVICE_SERVICE_IRQ_VECTOR,
					    sink_irq_vector);

		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
			intel_dp_handle_test_request(intel_dp);
		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
	}

2938
	if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2939
		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2940
			      drm_get_encoder_name(&intel_encoder->base));
2941 2942
		intel_dp_start_link_train(intel_dp);
		intel_dp_complete_link_train(intel_dp);
2943
		intel_dp_stop_link_train(intel_dp);
2944
	}
2945 2946
}

2947
/* XXX this is probably wrong for multiple downstream ports */
2948
static enum drm_connector_status
2949
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2950
{
2951 2952 2953 2954 2955 2956 2957 2958
	uint8_t *dpcd = intel_dp->dpcd;
	uint8_t type;

	if (!intel_dp_get_dpcd(intel_dp))
		return connector_status_disconnected;

	/* if there's no downstream port, we're done */
	if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2959
		return connector_status_connected;
2960 2961

	/* If we're HPD-aware, SINK_COUNT changes dynamically */
2962 2963
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
2964
		uint8_t reg;
2965
		if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2966
						    &reg, 1))
2967
			return connector_status_unknown;
2968 2969
		return DP_GET_SINK_COUNT(reg) ? connector_status_connected
					      : connector_status_disconnected;
2970 2971 2972 2973
	}

	/* If no HPD, poke DDC gently */
	if (drm_probe_ddc(&intel_dp->adapter))
2974
		return connector_status_connected;
2975 2976

	/* Well we tried, say unknown for unreliable port types */
2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
		type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
		if (type == DP_DS_PORT_TYPE_VGA ||
		    type == DP_DS_PORT_TYPE_NON_EDID)
			return connector_status_unknown;
	} else {
		type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
			DP_DWN_STRM_PORT_TYPE_MASK;
		if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
		    type == DP_DWN_STRM_PORT_TYPE_OTHER)
			return connector_status_unknown;
	}
2989 2990 2991

	/* Anything else is out of spec, warn and ignore */
	DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2992
	return connector_status_disconnected;
2993 2994
}

2995
static enum drm_connector_status
Z
Zhenyu Wang 已提交
2996
ironlake_dp_detect(struct intel_dp *intel_dp)
2997
{
2998
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2999 3000
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3001 3002
	enum drm_connector_status status;

3003 3004
	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp)) {
3005
		status = intel_panel_detect(dev);
3006 3007 3008 3009
		if (status == connector_status_unknown)
			status = connector_status_connected;
		return status;
	}
3010

3011 3012 3013
	if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
		return connector_status_disconnected;

3014
	return intel_dp_detect_dpcd(intel_dp);
3015 3016
}

3017
static enum drm_connector_status
Z
Zhenyu Wang 已提交
3018
g4x_dp_detect(struct intel_dp *intel_dp)
3019
{
3020
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3021
	struct drm_i915_private *dev_priv = dev->dev_private;
3022
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3023
	uint32_t bit;
3024

3025 3026 3027 3028 3029 3030 3031 3032 3033 3034
	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp)) {
		enum drm_connector_status status;

		status = intel_panel_detect(dev);
		if (status == connector_status_unknown)
			status = connector_status_connected;
		return status;
	}

3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061 3062
	if (IS_VALLEYVIEW(dev)) {
		switch (intel_dig_port->port) {
		case PORT_B:
			bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
			break;
		case PORT_C:
			bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
			break;
		case PORT_D:
			bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
			break;
		default:
			return connector_status_unknown;
		}
	} else {
		switch (intel_dig_port->port) {
		case PORT_B:
			bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
			break;
		case PORT_C:
			bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
			break;
		case PORT_D:
			bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
			break;
		default:
			return connector_status_unknown;
		}
3063 3064
	}

3065
	if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
3066 3067
		return connector_status_disconnected;

3068
	return intel_dp_detect_dpcd(intel_dp);
Z
Zhenyu Wang 已提交
3069 3070
}

3071 3072 3073
static struct edid *
intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
{
3074
	struct intel_connector *intel_connector = to_intel_connector(connector);
3075

3076 3077 3078 3079
	/* use cached edid if we have one */
	if (intel_connector->edid) {
		/* invalid edid */
		if (IS_ERR(intel_connector->edid))
3080 3081
			return NULL;

J
Jani Nikula 已提交
3082
		return drm_edid_duplicate(intel_connector->edid);
3083
	}
3084

3085
	return drm_get_edid(connector, adapter);
3086 3087 3088 3089 3090
}

static int
intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
{
3091
	struct intel_connector *intel_connector = to_intel_connector(connector);
3092

3093 3094 3095 3096 3097 3098 3099 3100
	/* use cached edid if we have one */
	if (intel_connector->edid) {
		/* invalid edid */
		if (IS_ERR(intel_connector->edid))
			return 0;

		return intel_connector_update_modes(connector,
						    intel_connector->edid);
3101 3102
	}

3103
	return intel_ddc_get_modes(connector, adapter);
3104 3105
}

Z
Zhenyu Wang 已提交
3106 3107 3108 3109
static enum drm_connector_status
intel_dp_detect(struct drm_connector *connector, bool force)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
3110 3111
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
3112
	struct drm_device *dev = connector->dev;
3113
	struct drm_i915_private *dev_priv = dev->dev_private;
Z
Zhenyu Wang 已提交
3114 3115 3116
	enum drm_connector_status status;
	struct edid *edid = NULL;

3117 3118
	intel_runtime_pm_get(dev_priv);

3119 3120 3121
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		      connector->base.id, drm_get_connector_name(connector));

Z
Zhenyu Wang 已提交
3122 3123 3124 3125 3126 3127
	intel_dp->has_audio = false;

	if (HAS_PCH_SPLIT(dev))
		status = ironlake_dp_detect(intel_dp);
	else
		status = g4x_dp_detect(intel_dp);
3128

Z
Zhenyu Wang 已提交
3129
	if (status != connector_status_connected)
3130
		goto out;
Z
Zhenyu Wang 已提交
3131

3132 3133
	intel_dp_probe_oui(intel_dp);

3134 3135
	if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
		intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
3136
	} else {
3137
		edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3138 3139 3140 3141
		if (edid) {
			intel_dp->has_audio = drm_detect_monitor_audio(edid);
			kfree(edid);
		}
Z
Zhenyu Wang 已提交
3142 3143
	}

3144 3145
	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3146 3147 3148 3149 3150
	status = connector_status_connected;

out:
	intel_runtime_pm_put(dev_priv);
	return status;
3151 3152 3153 3154
}

static int intel_dp_get_modes(struct drm_connector *connector)
{
3155
	struct intel_dp *intel_dp = intel_attached_dp(connector);
3156
	struct intel_connector *intel_connector = to_intel_connector(connector);
3157
	struct drm_device *dev = connector->dev;
3158
	int ret;
3159 3160 3161 3162

	/* We should parse the EDID data and find out if it has an audio sink
	 */

3163
	ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
3164
	if (ret)
3165 3166
		return ret;

3167
	/* if eDP has no EDID, fall back to fixed mode */
3168
	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
3169
		struct drm_display_mode *mode;
3170 3171
		mode = drm_mode_duplicate(dev,
					  intel_connector->panel.fixed_mode);
3172
		if (mode) {
3173 3174 3175 3176 3177
			drm_mode_probed_add(connector, mode);
			return 1;
		}
	}
	return 0;
3178 3179
}

3180 3181 3182 3183 3184 3185 3186
static bool
intel_dp_detect_audio(struct drm_connector *connector)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
	struct edid *edid;
	bool has_audio = false;

3187
	edid = intel_dp_get_edid(connector, &intel_dp->adapter);
3188 3189 3190 3191 3192 3193 3194 3195
	if (edid) {
		has_audio = drm_detect_monitor_audio(edid);
		kfree(edid);
	}

	return has_audio;
}

3196 3197 3198 3199 3200
static int
intel_dp_set_property(struct drm_connector *connector,
		      struct drm_property *property,
		      uint64_t val)
{
3201
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
3202
	struct intel_connector *intel_connector = to_intel_connector(connector);
3203 3204
	struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3205 3206
	int ret;

3207
	ret = drm_object_property_set_value(&connector->base, property, val);
3208 3209 3210
	if (ret)
		return ret;

3211
	if (property == dev_priv->force_audio_property) {
3212 3213 3214 3215
		int i = val;
		bool has_audio;

		if (i == intel_dp->force_audio)
3216 3217
			return 0;

3218
		intel_dp->force_audio = i;
3219

3220
		if (i == HDMI_AUDIO_AUTO)
3221 3222
			has_audio = intel_dp_detect_audio(connector);
		else
3223
			has_audio = (i == HDMI_AUDIO_ON);
3224 3225

		if (has_audio == intel_dp->has_audio)
3226 3227
			return 0;

3228
		intel_dp->has_audio = has_audio;
3229 3230 3231
		goto done;
	}

3232
	if (property == dev_priv->broadcast_rgb_property) {
3233 3234 3235
		bool old_auto = intel_dp->color_range_auto;
		uint32_t old_range = intel_dp->color_range;

3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250
		switch (val) {
		case INTEL_BROADCAST_RGB_AUTO:
			intel_dp->color_range_auto = true;
			break;
		case INTEL_BROADCAST_RGB_FULL:
			intel_dp->color_range_auto = false;
			intel_dp->color_range = 0;
			break;
		case INTEL_BROADCAST_RGB_LIMITED:
			intel_dp->color_range_auto = false;
			intel_dp->color_range = DP_COLOR_RANGE_16_235;
			break;
		default:
			return -EINVAL;
		}
3251 3252 3253 3254 3255

		if (old_auto == intel_dp->color_range_auto &&
		    old_range == intel_dp->color_range)
			return 0;

3256 3257 3258
		goto done;
	}

3259 3260 3261 3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274
	if (is_edp(intel_dp) &&
	    property == connector->dev->mode_config.scaling_mode_property) {
		if (val == DRM_MODE_SCALE_NONE) {
			DRM_DEBUG_KMS("no scaling not supported\n");
			return -EINVAL;
		}

		if (intel_connector->panel.fitting_mode == val) {
			/* the eDP scaling property is not changed */
			return 0;
		}
		intel_connector->panel.fitting_mode = val;

		goto done;
	}

3275 3276 3277
	return -EINVAL;

done:
3278 3279
	if (intel_encoder->base.crtc)
		intel_crtc_restore_mode(intel_encoder->base.crtc);
3280 3281 3282 3283

	return 0;
}

3284
static void
3285
intel_dp_connector_destroy(struct drm_connector *connector)
3286
{
3287
	struct intel_connector *intel_connector = to_intel_connector(connector);
3288

3289 3290 3291
	if (!IS_ERR_OR_NULL(intel_connector->edid))
		kfree(intel_connector->edid);

3292 3293 3294
	/* Can't call is_edp() since the encoder may have been destroyed
	 * already. */
	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3295
		intel_panel_fini(&intel_connector->panel);
3296

3297
	drm_connector_cleanup(connector);
3298
	kfree(connector);
3299 3300
}

P
Paulo Zanoni 已提交
3301
void intel_dp_encoder_destroy(struct drm_encoder *encoder)
3302
{
3303 3304
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_dp *intel_dp = &intel_dig_port->dp;
3305
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3306 3307 3308

	i2c_del_adapter(&intel_dp->adapter);
	drm_encoder_cleanup(encoder);
3309 3310
	if (is_edp(intel_dp)) {
		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
3311
		mutex_lock(&dev->mode_config.mutex);
3312
		edp_panel_vdd_off_sync(intel_dp);
3313
		mutex_unlock(&dev->mode_config.mutex);
3314
	}
3315
	kfree(intel_dig_port);
3316 3317
}

3318
static const struct drm_connector_funcs intel_dp_connector_funcs = {
3319
	.dpms = intel_connector_dpms,
3320 3321
	.detect = intel_dp_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
3322
	.set_property = intel_dp_set_property,
3323
	.destroy = intel_dp_connector_destroy,
3324 3325 3326 3327 3328
};

static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
	.get_modes = intel_dp_get_modes,
	.mode_valid = intel_dp_mode_valid,
3329
	.best_encoder = intel_best_encoder,
3330 3331 3332
};

static const struct drm_encoder_funcs intel_dp_enc_funcs = {
3333
	.destroy = intel_dp_encoder_destroy,
3334 3335
};

3336
static void
3337
intel_dp_hot_plug(struct intel_encoder *intel_encoder)
3338
{
3339
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
3340

3341
	intel_dp_check_link_status(intel_dp);
3342
}
3343

3344 3345
/* Return which DP Port should be selected for Transcoder DP control */
int
3346
intel_trans_dp_port_sel(struct drm_crtc *crtc)
3347 3348
{
	struct drm_device *dev = crtc->dev;
3349 3350
	struct intel_encoder *intel_encoder;
	struct intel_dp *intel_dp;
3351

3352 3353
	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		intel_dp = enc_to_intel_dp(&intel_encoder->base);
3354

3355 3356
		if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
		    intel_encoder->type == INTEL_OUTPUT_EDP)
C
Chris Wilson 已提交
3357
			return intel_dp->output_reg;
3358
	}
C
Chris Wilson 已提交
3359

3360 3361 3362
	return -1;
}

3363
/* check the VBT to see whether the eDP is on DP-D port */
3364
bool intel_dp_is_edp(struct drm_device *dev, enum port port)
3365 3366
{
	struct drm_i915_private *dev_priv = dev->dev_private;
3367
	union child_device_config *p_child;
3368
	int i;
3369 3370 3371 3372 3373
	static const short port_mapping[] = {
		[PORT_B] = PORT_IDPB,
		[PORT_C] = PORT_IDPC,
		[PORT_D] = PORT_IDPD,
	};
3374

3375 3376 3377
	if (port == PORT_A)
		return true;

3378
	if (!dev_priv->vbt.child_dev_num)
3379 3380
		return false;

3381 3382
	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
		p_child = dev_priv->vbt.child_dev + i;
3383

3384
		if (p_child->common.dvo_port == port_mapping[port] &&
3385 3386
		    (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
		    (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
3387 3388 3389 3390 3391
			return true;
	}
	return false;
}

3392 3393 3394
static void
intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
{
3395 3396
	struct intel_connector *intel_connector = to_intel_connector(connector);

3397
	intel_attach_force_audio_property(connector);
3398
	intel_attach_broadcast_rgb_property(connector);
3399
	intel_dp->color_range_auto = true;
3400 3401 3402

	if (is_edp(intel_dp)) {
		drm_mode_create_scaling_mode_property(connector->dev);
3403 3404
		drm_object_attach_property(
			&connector->base,
3405
			connector->dev->mode_config.scaling_mode_property,
3406 3407
			DRM_MODE_SCALE_ASPECT);
		intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
3408
	}
3409 3410
}

3411 3412
static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
3413 3414
				    struct intel_dp *intel_dp,
				    struct edp_power_seq *out)
3415 3416 3417 3418
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct edp_power_seq cur, vbt, spec, final;
	u32 pp_on, pp_off, pp_div, pp;
3419
	int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
3420 3421

	if (HAS_PCH_SPLIT(dev)) {
3422
		pp_ctrl_reg = PCH_PP_CONTROL;
3423 3424 3425 3426
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
3427 3428 3429 3430 3431 3432
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3433
	}
3434 3435 3436

	/* Workaround: Need to write PP_CONTROL with the unlock key as
	 * the very first thing. */
3437
	pp = ironlake_get_pp_control(intel_dp);
3438
	I915_WRITE(pp_ctrl_reg, pp);
3439

3440 3441 3442
	pp_on = I915_READ(pp_on_reg);
	pp_off = I915_READ(pp_off_reg);
	pp_div = I915_READ(pp_div_reg);
3443 3444 3445 3446 3447 3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459 3460 3461 3462

	/* Pull timing values out of registers */
	cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
		PANEL_POWER_UP_DELAY_SHIFT;

	cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
		PANEL_LIGHT_ON_DELAY_SHIFT;

	cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
		PANEL_LIGHT_OFF_DELAY_SHIFT;

	cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
		PANEL_POWER_DOWN_DELAY_SHIFT;

	cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
		       PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;

	DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);

3463
	vbt = dev_priv->vbt.edp_pps;
3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499

	/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
	 * our hw here, which are all in 100usec. */
	spec.t1_t3 = 210 * 10;
	spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
	spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
	spec.t10 = 500 * 10;
	/* This one is special and actually in units of 100ms, but zero
	 * based in the hw (so we need to add 100 ms). But the sw vbt
	 * table multiplies it with 1000 to make it in units of 100usec,
	 * too. */
	spec.t11_t12 = (510 + 100) * 10;

	DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);

	/* Use the max of the register settings and vbt. If both are
	 * unset, fall back to the spec limits. */
#define assign_final(field)	final.field = (max(cur.field, vbt.field) == 0 ? \
				       spec.field : \
				       max(cur.field, vbt.field))
	assign_final(t1_t3);
	assign_final(t8);
	assign_final(t9);
	assign_final(t10);
	assign_final(t11_t12);
#undef assign_final

#define get_delay(field)	(DIV_ROUND_UP(final.field, 10))
	intel_dp->panel_power_up_delay = get_delay(t1_t3);
	intel_dp->backlight_on_delay = get_delay(t8);
	intel_dp->backlight_off_delay = get_delay(t9);
	intel_dp->panel_power_down_delay = get_delay(t10);
	intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
#undef get_delay

3500 3501 3502 3503 3504 3505 3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516
	DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
		      intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
		      intel_dp->panel_power_cycle_delay);

	DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
		      intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);

	if (out)
		*out = final;
}

static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
					      struct intel_dp *intel_dp,
					      struct edp_power_seq *seq)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
3517 3518 3519 3520 3521 3522 3523 3524 3525
	u32 pp_on, pp_off, pp_div, port_sel = 0;
	int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
	int pp_on_reg, pp_off_reg, pp_div_reg;

	if (HAS_PCH_SPLIT(dev)) {
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
3526 3527 3528 3529 3530
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
3531 3532
	}

3533
	/* And finally store the new values in the power sequencer. */
3534 3535 3536 3537
	pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
		(seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
	pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
3538 3539
	/* Compute the divisor for the pp clock, simply match the Bspec
	 * formula. */
3540
	pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
3541
	pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
3542 3543 3544 3545
			<< PANEL_POWER_CYCLE_DELAY_SHIFT);

	/* Haswell doesn't have any port selection bits for the panel
	 * power sequencer any more. */
3546
	if (IS_VALLEYVIEW(dev)) {
3547 3548 3549 3550
		if (dp_to_dig_port(intel_dp)->port == PORT_B)
			port_sel = PANEL_PORT_SELECT_DPB_VLV;
		else
			port_sel = PANEL_PORT_SELECT_DPC_VLV;
3551 3552
	} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
		if (dp_to_dig_port(intel_dp)->port == PORT_A)
3553
			port_sel = PANEL_PORT_SELECT_DPA;
3554
		else
3555
			port_sel = PANEL_PORT_SELECT_DPD;
3556 3557
	}

3558 3559 3560 3561 3562
	pp_on |= port_sel;

	I915_WRITE(pp_on_reg, pp_on);
	I915_WRITE(pp_off_reg, pp_off);
	I915_WRITE(pp_div_reg, pp_div);
3563 3564

	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
3565 3566 3567
		      I915_READ(pp_on_reg),
		      I915_READ(pp_off_reg),
		      I915_READ(pp_div_reg));
3568 3569
}

3570
static bool intel_edp_init_connector(struct intel_dp *intel_dp,
3571 3572
				     struct intel_connector *intel_connector,
				     struct edp_power_seq *power_seq)
3573 3574 3575 3576 3577 3578 3579 3580 3581 3582 3583 3584 3585 3586
{
	struct drm_connector *connector = &intel_connector->base;
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_display_mode *fixed_mode = NULL;
	bool has_dpcd;
	struct drm_display_mode *scan;
	struct edid *edid;

	if (!is_edp(intel_dp))
		return true;

	/* Cache DPCD and EDID for edp. */
3587
	edp_panel_vdd_on(intel_dp);
3588
	has_dpcd = intel_dp_get_dpcd(intel_dp);
3589
	edp_panel_vdd_off(intel_dp, false);
3590 3591 3592 3593 3594 3595 3596 3597 3598 3599 3600 3601 3602

	if (has_dpcd) {
		if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
			dev_priv->no_aux_handshake =
				intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
				DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
	} else {
		/* if this fails, presume the device is a ghost */
		DRM_INFO("failed to retrieve link info, disabling eDP\n");
		return false;
	}

	/* We now know it's not a ghost, init power sequence regs. */
3603
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, power_seq);
3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641

	edid = drm_get_edid(connector, &intel_dp->adapter);
	if (edid) {
		if (drm_add_edid_modes(connector, edid)) {
			drm_mode_connector_update_edid_property(connector,
								edid);
			drm_edid_to_eld(connector, edid);
		} else {
			kfree(edid);
			edid = ERR_PTR(-EINVAL);
		}
	} else {
		edid = ERR_PTR(-ENOENT);
	}
	intel_connector->edid = edid;

	/* prefer fixed mode from EDID if available */
	list_for_each_entry(scan, &connector->probed_modes, head) {
		if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
			fixed_mode = drm_mode_duplicate(dev, scan);
			break;
		}
	}

	/* fallback to VBT if available for eDP */
	if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
		fixed_mode = drm_mode_duplicate(dev,
					dev_priv->vbt.lfp_lvds_vbt_mode);
		if (fixed_mode)
			fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
	}

	intel_panel_init(&intel_connector->panel, fixed_mode);
	intel_panel_setup_backlight(connector);

	return true;
}

3642
bool
3643 3644
intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
			struct intel_connector *intel_connector)
3645
{
3646 3647 3648 3649
	struct drm_connector *connector = &intel_connector->base;
	struct intel_dp *intel_dp = &intel_dig_port->dp;
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
3650
	struct drm_i915_private *dev_priv = dev->dev_private;
3651
	enum port port = intel_dig_port->port;
3652
	struct edp_power_seq power_seq = { 0 };
3653
	const char *name = NULL;
3654
	int type, error;
3655

3656 3657
	/* Preserve the current hw state. */
	intel_dp->DP = I915_READ(intel_dp->output_reg);
3658
	intel_dp->attached_connector = intel_connector;
3659

3660
	if (intel_dp_is_edp(dev, port))
3661
		type = DRM_MODE_CONNECTOR_eDP;
3662 3663
	else
		type = DRM_MODE_CONNECTOR_DisplayPort;
3664

3665 3666 3667 3668 3669 3670 3671 3672
	/*
	 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
	 * for DP the encoder type can be set by the caller to
	 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
	 */
	if (type == DRM_MODE_CONNECTOR_eDP)
		intel_encoder->type = INTEL_OUTPUT_EDP;

3673 3674 3675 3676
	DRM_DEBUG_KMS("Adding %s connector on port %c\n",
			type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
			port_name(port));

3677
	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
3678 3679 3680 3681 3682
	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);

	connector->interlace_allowed = true;
	connector->doublescan_allowed = 0;

3683
	INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
3684
			  edp_panel_vdd_work);
3685

3686
	intel_connector_attach_encoder(intel_connector, intel_encoder);
3687 3688
	drm_sysfs_connector_add(connector);

P
Paulo Zanoni 已提交
3689
	if (HAS_DDI(dev))
3690 3691 3692 3693
		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
	else
		intel_connector->get_hw_state = intel_connector_get_hw_state;

3694 3695 3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712
	intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
	if (HAS_DDI(dev)) {
		switch (intel_dig_port->port) {
		case PORT_A:
			intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
			break;
		case PORT_B:
			intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
			break;
		case PORT_C:
			intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
			break;
		case PORT_D:
			intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
			break;
		default:
			BUG();
		}
	}
3713

3714
	/* Set up the DDC bus. */
3715 3716
	switch (port) {
	case PORT_A:
3717
		intel_encoder->hpd_pin = HPD_PORT_A;
3718 3719 3720
		name = "DPDDC-A";
		break;
	case PORT_B:
3721
		intel_encoder->hpd_pin = HPD_PORT_B;
3722 3723 3724
		name = "DPDDC-B";
		break;
	case PORT_C:
3725
		intel_encoder->hpd_pin = HPD_PORT_C;
3726 3727 3728
		name = "DPDDC-C";
		break;
	case PORT_D:
3729
		intel_encoder->hpd_pin = HPD_PORT_D;
3730 3731 3732
		name = "DPDDC-D";
		break;
	default:
3733
		BUG();
3734 3735
	}

3736 3737 3738
	if (is_edp(intel_dp))
		intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);

3739 3740 3741
	error = intel_dp_i2c_init(intel_dp, intel_connector, name);
	WARN(error, "intel_dp_i2c_init failed with error %d for port %c\n",
	     error, port_name(port));
3742

R
Rodrigo Vivi 已提交
3743 3744
	intel_dp->psr_setup_done = false;

3745
	if (!intel_edp_init_connector(intel_dp, intel_connector, &power_seq)) {
3746 3747 3748 3749
		i2c_del_adapter(&intel_dp->adapter);
		if (is_edp(intel_dp)) {
			cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
			mutex_lock(&dev->mode_config.mutex);
3750
			edp_panel_vdd_off_sync(intel_dp);
3751 3752
			mutex_unlock(&dev->mode_config.mutex);
		}
3753 3754
		drm_sysfs_connector_remove(connector);
		drm_connector_cleanup(connector);
3755
		return false;
3756
	}
3757

3758 3759
	intel_dp_add_properties(intel_dp, connector);

3760 3761 3762 3763 3764 3765 3766 3767
	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
3768 3769

	return true;
3770
}
3771 3772 3773 3774 3775 3776 3777 3778 3779

void
intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
{
	struct intel_digital_port *intel_dig_port;
	struct intel_encoder *intel_encoder;
	struct drm_encoder *encoder;
	struct intel_connector *intel_connector;

3780
	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
3781 3782 3783
	if (!intel_dig_port)
		return;

3784
	intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
3785 3786 3787 3788 3789 3790 3791 3792 3793 3794 3795
	if (!intel_connector) {
		kfree(intel_dig_port);
		return;
	}

	intel_encoder = &intel_dig_port->base;
	encoder = &intel_encoder->base;

	drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
			 DRM_MODE_ENCODER_TMDS);

3796
	intel_encoder->compute_config = intel_dp_compute_config;
3797
	intel_encoder->mode_set = intel_dp_mode_set;
P
Paulo Zanoni 已提交
3798 3799 3800
	intel_encoder->disable = intel_disable_dp;
	intel_encoder->post_disable = intel_post_disable_dp;
	intel_encoder->get_hw_state = intel_dp_get_hw_state;
3801
	intel_encoder->get_config = intel_dp_get_config;
3802
	if (IS_VALLEYVIEW(dev)) {
3803
		intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
3804 3805 3806
		intel_encoder->pre_enable = vlv_pre_enable_dp;
		intel_encoder->enable = vlv_enable_dp;
	} else {
3807 3808
		intel_encoder->pre_enable = g4x_pre_enable_dp;
		intel_encoder->enable = g4x_enable_dp;
3809
	}
3810

3811
	intel_dig_port->port = port;
3812 3813
	intel_dig_port->dp.output_reg = output_reg;

P
Paulo Zanoni 已提交
3814
	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
3815 3816 3817 3818
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
	intel_encoder->cloneable = false;
	intel_encoder->hot_plug = intel_dp_hot_plug;

3819 3820 3821
	if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
		drm_encoder_cleanup(encoder);
		kfree(intel_dig_port);
3822
		kfree(intel_connector);
3823
	}
3824
}