intel_dp.c 82.1 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/i2c.h>
29
#include <linux/slab.h>
30
#include <linux/export.h>
31 32 33 34
#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
35
#include "intel_drv.h"
36
#include <drm/i915_drm.h>
37 38 39 40
#include "i915_drv.h"

#define DP_LINK_CHECK_TIMEOUT	(10 * 1000)

41 42 43 44 45 46 47 48 49
/**
 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 * @intel_dp: DP struct
 *
 * If a CPU or PCH DP output is attached to an eDP panel, this function
 * will return true, and false otherwise.
 */
static bool is_edp(struct intel_dp *intel_dp)
{
50 51 52
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67
}

/**
 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
 * @intel_dp: DP struct
 *
 * Returns true if the given DP struct corresponds to a PCH DP port attached
 * to an eDP panel, false otherwise.  Helpful for determining whether we
 * may need FDI resources for a given DP output or not.
 */
static bool is_pch_edp(struct intel_dp *intel_dp)
{
	return intel_dp->is_pch_edp;
}

A
Adam Jackson 已提交
68 69 70 71 72 73 74 75 76 77 78
/**
 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
 * @intel_dp: DP struct
 *
 * Returns true if the given DP struct corresponds to a CPU eDP port.
 */
static bool is_cpu_edp(struct intel_dp *intel_dp)
{
	return is_edp(intel_dp) && !is_pch_edp(intel_dp);
}

79
static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
C
Chris Wilson 已提交
80
{
81 82 83
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.base.dev;
C
Chris Wilson 已提交
84
}
85

86 87
static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
{
88
	return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
89 90
}

91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109
/**
 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
 * @encoder: DRM encoder
 *
 * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
 * by intel_display.c.
 */
bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
{
	struct intel_dp *intel_dp;

	if (!encoder)
		return false;

	intel_dp = enc_to_intel_dp(encoder);

	return is_pch_edp(intel_dp);
}

C
Chris Wilson 已提交
110
static void intel_dp_link_down(struct intel_dp *intel_dp);
111 112

static int
C
Chris Wilson 已提交
113
intel_dp_max_link_bw(struct intel_dp *intel_dp)
114
{
115
	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
116 117 118 119 120 121 122 123 124 125 126 127

	switch (max_link_bw) {
	case DP_LINK_BW_1_62:
	case DP_LINK_BW_2_7:
		break;
	default:
		max_link_bw = DP_LINK_BW_1_62;
		break;
	}
	return max_link_bw;
}

128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
/*
 * The units on the numbers in the next two are... bizarre.  Examples will
 * make it clearer; this one parallels an example in the eDP spec.
 *
 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 *
 *     270000 * 1 * 8 / 10 == 216000
 *
 * The actual data capacity of that configuration is 2.16Gbit/s, so the
 * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 * 119000.  At 18bpp that's 2142000 kilobits per second.
 *
 * Thus the strange-looking division by 10 in intel_dp_link_required, to
 * get the result in decakilobits instead of kilobits.
 */

145
static int
146
intel_dp_link_required(int pixel_clock, int bpp)
147
{
148
	return (pixel_clock * bpp + 9) / 10;
149 150
}

151 152 153 154 155 156
static int
intel_dp_max_data_rate(int max_link_clock, int max_lanes)
{
	return (max_link_clock * max_lanes * 8) / 10;
}

157 158 159 160
static int
intel_dp_mode_valid(struct drm_connector *connector,
		    struct drm_display_mode *mode)
{
161
	struct intel_dp *intel_dp = intel_attached_dp(connector);
162 163
	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
164 165
	int target_clock = mode->clock;
	int max_rate, mode_rate, max_lanes, max_link_clock;
166

167 168
	if (is_edp(intel_dp) && fixed_mode) {
		if (mode->hdisplay > fixed_mode->hdisplay)
169 170
			return MODE_PANEL;

171
		if (mode->vdisplay > fixed_mode->vdisplay)
172
			return MODE_PANEL;
173 174

		target_clock = fixed_mode->clock;
175 176
	}

177 178 179 180 181 182 183
	max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
	max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);

	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
	mode_rate = intel_dp_link_required(target_clock, 18);

	if (mode_rate > max_rate)
184
		return MODE_CLOCK_HIGH;
185 186 187 188

	if (mode->clock < 10000)
		return MODE_CLOCK_LOW;

189 190 191
	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		return MODE_H_ILLEGAL;

192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217
	return MODE_OK;
}

static uint32_t
pack_aux(uint8_t *src, int src_bytes)
{
	int	i;
	uint32_t v = 0;

	if (src_bytes > 4)
		src_bytes = 4;
	for (i = 0; i < src_bytes; i++)
		v |= ((uint32_t) src[i]) << ((3-i) * 8);
	return v;
}

static void
unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
{
	int i;
	if (dst_bytes > 4)
		dst_bytes = 4;
	for (i = 0; i < dst_bytes; i++)
		dst[i] = src >> ((3-i) * 8);
}

218 219 220 221 222 223 224
/* hrawclock is 1/4 the FSB frequency */
static int
intel_hrawclk(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t clkcfg;

225 226 227 228
	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
	if (IS_VALLEYVIEW(dev))
		return 200;

229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251
	clkcfg = I915_READ(CLKCFG);
	switch (clkcfg & CLKCFG_FSB_MASK) {
	case CLKCFG_FSB_400:
		return 100;
	case CLKCFG_FSB_533:
		return 133;
	case CLKCFG_FSB_667:
		return 166;
	case CLKCFG_FSB_800:
		return 200;
	case CLKCFG_FSB_1067:
		return 266;
	case CLKCFG_FSB_1333:
		return 333;
	/* these two are just a guess; one of them might be right */
	case CLKCFG_FSB_1600:
	case CLKCFG_FSB_1600_ALT:
		return 400;
	default:
		return 133;
	}
}

252 253
static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
{
254
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
255
	struct drm_i915_private *dev_priv = dev->dev_private;
256
	u32 pp_stat_reg;
257

258 259
	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
	return (I915_READ(pp_stat_reg) & PP_ON) != 0;
260 261 262 263
}

static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
{
264
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
265
	struct drm_i915_private *dev_priv = dev->dev_private;
266
	u32 pp_ctrl_reg;
267

268 269
	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
	return (I915_READ(pp_ctrl_reg) & EDP_FORCE_VDD) != 0;
270 271
}

272 273 274
static void
intel_dp_check_edp(struct intel_dp *intel_dp)
{
275
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
276
	struct drm_i915_private *dev_priv = dev->dev_private;
277
	u32 pp_stat_reg, pp_ctrl_reg;
278

279 280
	if (!is_edp(intel_dp))
		return;
281 282 283 284

	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;

285
	if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
286 287
		WARN(1, "eDP powered off while attempting aux channel communication.\n");
		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
288 289
				I915_READ(pp_stat_reg),
				I915_READ(pp_ctrl_reg));
290 291 292
	}
}

293 294 295 296 297 298
static uint32_t
intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
299
	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
300 301 302
	uint32_t status;
	bool done;

303
#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
304
	if (has_aux_irq)
305 306
		done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
					  msecs_to_jiffies(10));
307 308 309 310 311 312 313 314 315 316
	else
		done = wait_for_atomic(C, 10) == 0;
	if (!done)
		DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
			  has_aux_irq);
#undef C

	return status;
}

317
static int
C
Chris Wilson 已提交
318
intel_dp_aux_ch(struct intel_dp *intel_dp,
319 320 321
		uint8_t *send, int send_bytes,
		uint8_t *recv, int recv_size)
{
322 323
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
324
	struct drm_i915_private *dev_priv = dev->dev_private;
325
	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
326
	uint32_t ch_data = ch_ctl + 4;
327
	int i, ret, recv_bytes;
328
	uint32_t status;
329
	uint32_t aux_clock_divider;
330
	int try, precharge;
331 332 333 334 335 336 337
	bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);

	/* dp aux is extremely sensitive to irq latency, hence request the
	 * lowest possible wakeup latency and so prevent the cpu from going into
	 * deep sleep states.
	 */
	pm_qos_update_request(&dev_priv->pm_qos, 0);
338

339
	intel_dp_check_edp(intel_dp);
340
	/* The clock divider is based off the hrawclk,
341 342
	 * and would like to run at 2MHz. So, take the
	 * hrawclk value and divide by 2 and use that
343 344 345
	 *
	 * Note that PCH attached eDP panels should use a 125MHz input
	 * clock divider.
346
	 */
A
Adam Jackson 已提交
347
	if (is_cpu_edp(intel_dp)) {
P
Paulo Zanoni 已提交
348
		if (HAS_DDI(dev))
349 350
			aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
		else if (IS_VALLEYVIEW(dev))
351 352
			aux_clock_divider = 100;
		else if (IS_GEN6(dev) || IS_GEN7(dev))
K
Keith Packard 已提交
353
			aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
354 355
		else
			aux_clock_divider = 225; /* eDP input clock at 450Mhz */
356 357 358 359
	} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
		/* Workaround for non-ULT HSW */
		aux_clock_divider = 74;
	} else if (HAS_PCH_SPLIT(dev)) {
360
		aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
361
	} else {
362
		aux_clock_divider = intel_hrawclk(dev) / 2;
363
	}
364

365 366 367 368 369
	if (IS_GEN6(dev))
		precharge = 3;
	else
		precharge = 5;

370 371
	/* Try to wait for any previous AUX channel activity */
	for (try = 0; try < 3; try++) {
372
		status = I915_READ_NOTRACE(ch_ctl);
373 374 375 376 377 378 379 380
		if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
			break;
		msleep(1);
	}

	if (try == 3) {
		WARN(1, "dp_aux_ch not started status 0x%08x\n",
		     I915_READ(ch_ctl));
381 382
		ret = -EBUSY;
		goto out;
383 384
	}

385 386 387
	/* Must try at least 3 times according to DP spec */
	for (try = 0; try < 5; try++) {
		/* Load the send data into the aux channel data registers */
388 389 390
		for (i = 0; i < send_bytes; i += 4)
			I915_WRITE(ch_data + i,
				   pack_aux(send + i, send_bytes - i));
391

392
		/* Send the command and wait for it to complete */
393 394
		I915_WRITE(ch_ctl,
			   DP_AUX_CH_CTL_SEND_BUSY |
395
			   (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
396 397 398 399 400 401 402
			   DP_AUX_CH_CTL_TIME_OUT_400us |
			   (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
			   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
			   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
			   DP_AUX_CH_CTL_DONE |
			   DP_AUX_CH_CTL_TIME_OUT_ERROR |
			   DP_AUX_CH_CTL_RECEIVE_ERROR);
403 404

		status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
405

406
		/* Clear done status and any errors */
407 408 409 410 411
		I915_WRITE(ch_ctl,
			   status |
			   DP_AUX_CH_CTL_DONE |
			   DP_AUX_CH_CTL_TIME_OUT_ERROR |
			   DP_AUX_CH_CTL_RECEIVE_ERROR);
412 413 414 415

		if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
			      DP_AUX_CH_CTL_RECEIVE_ERROR))
			continue;
416
		if (status & DP_AUX_CH_CTL_DONE)
417 418 419 420
			break;
	}

	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
421
		DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
422 423
		ret = -EBUSY;
		goto out;
424 425 426 427 428
	}

	/* Check for timeout or receive error.
	 * Timeouts occur when the sink is not connected
	 */
429
	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
430
		DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
431 432
		ret = -EIO;
		goto out;
433
	}
434 435 436

	/* Timeouts occur when the device isn't connected, so they're
	 * "normal" -- don't fill the kernel log with these */
437
	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
438
		DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
439 440
		ret = -ETIMEDOUT;
		goto out;
441 442 443 444 445 446 447
	}

	/* Unload any bytes sent back from the other side */
	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
		      DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
	if (recv_bytes > recv_size)
		recv_bytes = recv_size;
448

449 450 451
	for (i = 0; i < recv_bytes; i += 4)
		unpack_aux(I915_READ(ch_data + i),
			   recv + i, recv_bytes - i);
452

453 454 455 456 457
	ret = recv_bytes;
out:
	pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);

	return ret;
458 459 460 461
}

/* Write data to the aux channel in native mode */
static int
C
Chris Wilson 已提交
462
intel_dp_aux_native_write(struct intel_dp *intel_dp,
463 464 465 466 467 468 469
			  uint16_t address, uint8_t *send, int send_bytes)
{
	int ret;
	uint8_t	msg[20];
	int msg_bytes;
	uint8_t	ack;

470
	intel_dp_check_edp(intel_dp);
471 472 473 474
	if (send_bytes > 16)
		return -1;
	msg[0] = AUX_NATIVE_WRITE << 4;
	msg[1] = address >> 8;
475
	msg[2] = address & 0xff;
476 477 478 479
	msg[3] = send_bytes - 1;
	memcpy(&msg[4], send, send_bytes);
	msg_bytes = send_bytes + 4;
	for (;;) {
C
Chris Wilson 已提交
480
		ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
481 482 483 484 485 486 487
		if (ret < 0)
			return ret;
		if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
			break;
		else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
			udelay(100);
		else
488
			return -EIO;
489 490 491 492 493 494
	}
	return send_bytes;
}

/* Write a single byte to the aux channel in native mode */
static int
C
Chris Wilson 已提交
495
intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
496 497
			    uint16_t address, uint8_t byte)
{
C
Chris Wilson 已提交
498
	return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
499 500 501 502
}

/* read bytes from a native aux channel */
static int
C
Chris Wilson 已提交
503
intel_dp_aux_native_read(struct intel_dp *intel_dp,
504 505 506 507 508 509 510 511 512
			 uint16_t address, uint8_t *recv, int recv_bytes)
{
	uint8_t msg[4];
	int msg_bytes;
	uint8_t reply[20];
	int reply_bytes;
	uint8_t ack;
	int ret;

513
	intel_dp_check_edp(intel_dp);
514 515 516 517 518 519 520 521 522
	msg[0] = AUX_NATIVE_READ << 4;
	msg[1] = address >> 8;
	msg[2] = address & 0xff;
	msg[3] = recv_bytes - 1;

	msg_bytes = 4;
	reply_bytes = recv_bytes + 1;

	for (;;) {
C
Chris Wilson 已提交
523
		ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
524
				      reply, reply_bytes);
525 526 527
		if (ret == 0)
			return -EPROTO;
		if (ret < 0)
528 529 530 531 532 533 534 535 536
			return ret;
		ack = reply[0];
		if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
			memcpy(recv, reply + 1, ret - 1);
			return ret - 1;
		}
		else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
			udelay(100);
		else
537
			return -EIO;
538 539 540 541
	}
}

static int
542 543
intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
		    uint8_t write_byte, uint8_t *read_byte)
544
{
545
	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
C
Chris Wilson 已提交
546 547 548
	struct intel_dp *intel_dp = container_of(adapter,
						struct intel_dp,
						adapter);
549 550 551
	uint16_t address = algo_data->address;
	uint8_t msg[5];
	uint8_t reply[2];
552
	unsigned retry;
553 554 555 556
	int msg_bytes;
	int reply_bytes;
	int ret;

557
	intel_dp_check_edp(intel_dp);
558 559 560 561 562 563 564 565
	/* Set up the command byte */
	if (mode & MODE_I2C_READ)
		msg[0] = AUX_I2C_READ << 4;
	else
		msg[0] = AUX_I2C_WRITE << 4;

	if (!(mode & MODE_I2C_STOP))
		msg[0] |= AUX_I2C_MOT << 4;
566

567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587
	msg[1] = address >> 8;
	msg[2] = address;

	switch (mode) {
	case MODE_I2C_WRITE:
		msg[3] = 0;
		msg[4] = write_byte;
		msg_bytes = 5;
		reply_bytes = 1;
		break;
	case MODE_I2C_READ:
		msg[3] = 0;
		msg_bytes = 4;
		reply_bytes = 2;
		break;
	default:
		msg_bytes = 3;
		reply_bytes = 1;
		break;
	}

588 589 590 591
	for (retry = 0; retry < 5; retry++) {
		ret = intel_dp_aux_ch(intel_dp,
				      msg, msg_bytes,
				      reply, reply_bytes);
592
		if (ret < 0) {
593
			DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
594 595
			return ret;
		}
596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614

		switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
		case AUX_NATIVE_REPLY_ACK:
			/* I2C-over-AUX Reply field is only valid
			 * when paired with AUX ACK.
			 */
			break;
		case AUX_NATIVE_REPLY_NACK:
			DRM_DEBUG_KMS("aux_ch native nack\n");
			return -EREMOTEIO;
		case AUX_NATIVE_REPLY_DEFER:
			udelay(100);
			continue;
		default:
			DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
				  reply[0]);
			return -EREMOTEIO;
		}

615 616 617 618 619 620 621
		switch (reply[0] & AUX_I2C_REPLY_MASK) {
		case AUX_I2C_REPLY_ACK:
			if (mode == MODE_I2C_READ) {
				*read_byte = reply[1];
			}
			return reply_bytes - 1;
		case AUX_I2C_REPLY_NACK:
622
			DRM_DEBUG_KMS("aux_i2c nack\n");
623 624
			return -EREMOTEIO;
		case AUX_I2C_REPLY_DEFER:
625
			DRM_DEBUG_KMS("aux_i2c defer\n");
626 627 628
			udelay(100);
			break;
		default:
629
			DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
630 631 632
			return -EREMOTEIO;
		}
	}
633 634 635

	DRM_ERROR("too many retries, giving up\n");
	return -EREMOTEIO;
636 637 638
}

static int
C
Chris Wilson 已提交
639
intel_dp_i2c_init(struct intel_dp *intel_dp,
640
		  struct intel_connector *intel_connector, const char *name)
641
{
642 643
	int	ret;

Z
Zhenyu Wang 已提交
644
	DRM_DEBUG_KMS("i2c_init %s\n", name);
C
Chris Wilson 已提交
645 646 647 648
	intel_dp->algo.running = false;
	intel_dp->algo.address = 0;
	intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;

649
	memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
C
Chris Wilson 已提交
650 651
	intel_dp->adapter.owner = THIS_MODULE;
	intel_dp->adapter.class = I2C_CLASS_DDC;
652
	strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
C
Chris Wilson 已提交
653 654 655 656
	intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
	intel_dp->adapter.algo_data = &intel_dp->algo;
	intel_dp->adapter.dev.parent = &intel_connector->base.kdev;

657 658
	ironlake_edp_panel_vdd_on(intel_dp);
	ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
659
	ironlake_edp_panel_vdd_off(intel_dp, false);
660
	return ret;
661 662
}

P
Paulo Zanoni 已提交
663
bool
664 665
intel_dp_compute_config(struct intel_encoder *encoder,
			struct intel_crtc_config *pipe_config)
666
{
667
	struct drm_device *dev = encoder->base.dev;
668
	struct drm_i915_private *dev_priv = dev->dev_private;
669 670 671
	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
	struct drm_display_mode *mode = &pipe_config->requested_mode;
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
672
	struct intel_connector *intel_connector = intel_dp->attached_connector;
673
	int lane_count, clock;
674
	int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
C
Chris Wilson 已提交
675
	int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
676
	int bpp, mode_rate;
677
	static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
678
	int target_clock, link_avail, link_clock;
679

680 681 682
	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && !is_cpu_edp(intel_dp))
		pipe_config->has_pch_encoder = true;

683 684
	pipe_config->has_dp_encoder = true;

685 686 687
	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
		intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
				       adjusted_mode);
688 689
		intel_pch_panel_fitting(dev,
					intel_connector->panel.fitting_mode,
690
					mode, adjusted_mode);
691
	}
692 693
	/* We need to take the panel's fixed mode into account. */
	target_clock = adjusted_mode->clock;
694

695
	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
696 697
		return false;

698 699
	DRM_DEBUG_KMS("DP link computation with max lane count %i "
		      "max bw %02x pixel clock %iKHz\n",
700
		      max_lane_count, bws[max_clock], adjusted_mode->clock);
701

702 703
	/* Walk through all bpp values. Luckily they're all nicely spaced with 2
	 * bpc in between. */
704
	bpp = min_t(int, 8*3, pipe_config->pipe_bpp);
705 706 707 708 709 710 711 712 713 714 715 716 717 718 719
	for (; bpp >= 6*3; bpp -= 2*3) {
		mode_rate = intel_dp_link_required(target_clock, bpp);

		for (clock = 0; clock <= max_clock; clock++) {
			for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
				link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
				link_avail = intel_dp_max_data_rate(link_clock,
								    lane_count);

				if (mode_rate <= link_avail) {
					goto found;
				}
			}
		}
	}
720

721
	return false;
722

723
found:
724 725 726 727 728 729
	if (intel_dp->color_range_auto) {
		/*
		 * See:
		 * CEA-861-E - 5.1 Default Encoding Parameters
		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
		 */
730
		if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
731 732 733 734 735
			intel_dp->color_range = DP_COLOR_RANGE_16_235;
		else
			intel_dp->color_range = 0;
	}

736
	if (intel_dp->color_range)
737
		pipe_config->limited_color_range = true;
738

739 740 741
	intel_dp->link_bw = bws[clock];
	intel_dp->lane_count = lane_count;
	adjusted_mode->clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
742
	pipe_config->pixel_target_clock = target_clock;
743

744 745 746 747 748 749
	DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
		      intel_dp->link_bw, intel_dp->lane_count,
		      adjusted_mode->clock, bpp);
	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
		      mode_rate, link_avail);

750 751 752
	intel_link_compute_m_n(bpp, lane_count,
			       target_clock, adjusted_mode->clock,
			       &pipe_config->dp_m_n);
753

754 755 756 757 758 759 760 761 762 763 764 765 766 767
	/*
	 * XXX: We have a strange regression where using the vbt edp bpp value
	 * for the link bw computation results in black screens, the panel only
	 * works when we do the computation at the usual 24bpp (but still
	 * requires us to use 18bpp). Until that's fully debugged, stay
	 * bug-for-bug compatible with the old code.
	 */
	if (is_edp(intel_dp) && dev_priv->edp.bpp) {
		DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n",
			      bpp, dev_priv->edp.bpp);
		bpp = min_t(int, bpp, dev_priv->edp.bpp);
	}
	pipe_config->pipe_bpp = bpp;

768
	return true;
769 770
}

771 772 773 774 775 776 777 778 779 780 781 782 783 784 785
void intel_dp_init_link_config(struct intel_dp *intel_dp)
{
	memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
	intel_dp->link_configuration[0] = intel_dp->link_bw;
	intel_dp->link_configuration[1] = intel_dp->lane_count;
	intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
	/*
	 * Check for DPCD version > 1.1 and enhanced framing support
	 */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
		intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
	}
}

786 787 788 789 790 791 792 793 794 795 796
static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
	dpa_ctl = I915_READ(DP_A);
	dpa_ctl &= ~DP_PLL_FREQ_MASK;

	if (clock < 200000) {
797 798 799 800
		/* For a long time we've carried around a ILK-DevA w/a for the
		 * 160MHz clock. If we're really unlucky, it's still required.
		 */
		DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
801 802 803 804
		dpa_ctl |= DP_PLL_FREQ_160MHZ;
	} else {
		dpa_ctl |= DP_PLL_FREQ_270MHZ;
	}
805

806 807 808 809 810 811
	I915_WRITE(DP_A, dpa_ctl);

	POSTING_READ(DP_A);
	udelay(500);
}

812 813 814 815
static void
intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
		  struct drm_display_mode *adjusted_mode)
{
816
	struct drm_device *dev = encoder->dev;
817
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
818
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
819
	struct drm_crtc *crtc = encoder->crtc;
820 821
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

822
	/*
K
Keith Packard 已提交
823
	 * There are four kinds of DP registers:
824 825
	 *
	 * 	IBX PCH
K
Keith Packard 已提交
826 827
	 * 	SNB CPU
	 *	IVB CPU
828 829 830 831 832 833 834 835 836 837
	 * 	CPT PCH
	 *
	 * IBX PCH and CPU are the same for almost everything,
	 * except that the CPU DP PLL is configured in this
	 * register
	 *
	 * CPT PCH is quite different, having many bits moved
	 * to the TRANS_DP_CTL register instead. That
	 * configuration happens (oddly) in ironlake_pch_enable
	 */
838

839 840 841 842
	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
843

844 845
	/* Handle DP bits in common between all three register formats */
	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
846

C
Chris Wilson 已提交
847
	switch (intel_dp->lane_count) {
848
	case 1:
C
Chris Wilson 已提交
849
		intel_dp->DP |= DP_PORT_WIDTH_1;
850 851
		break;
	case 2:
C
Chris Wilson 已提交
852
		intel_dp->DP |= DP_PORT_WIDTH_2;
853 854
		break;
	case 4:
C
Chris Wilson 已提交
855
		intel_dp->DP |= DP_PORT_WIDTH_4;
856 857
		break;
	}
858 859 860
	if (intel_dp->has_audio) {
		DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
				 pipe_name(intel_crtc->pipe));
C
Chris Wilson 已提交
861
		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
862 863
		intel_write_eld(encoder, adjusted_mode);
	}
864 865

	intel_dp_init_link_config(intel_dp);
866

867
	/* Split out the IBX/CPU vs CPT settings */
868

869
	if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
K
Keith Packard 已提交
870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886
		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

		if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
			intel_dp->DP |= DP_ENHANCED_FRAMING;

		intel_dp->DP |= intel_crtc->pipe << 29;

		/* don't miss out required setting for eDP */
		if (adjusted_mode->clock < 200000)
			intel_dp->DP |= DP_PLL_FREQ_160MHZ;
		else
			intel_dp->DP |= DP_PLL_FREQ_270MHZ;
	} else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
887
		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
888
			intel_dp->DP |= intel_dp->color_range;
889 890 891 892 893 894 895 896 897 898 899 900 901

		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF;

		if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
			intel_dp->DP |= DP_ENHANCED_FRAMING;

		if (intel_crtc->pipe == 1)
			intel_dp->DP |= DP_PIPEB_SELECT;

902
		if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
903 904 905 906 907 908 909 910
			/* don't miss out required setting for eDP */
			if (adjusted_mode->clock < 200000)
				intel_dp->DP |= DP_PLL_FREQ_160MHZ;
			else
				intel_dp->DP |= DP_PLL_FREQ_270MHZ;
		}
	} else {
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
911
	}
912

913
	if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
914
		ironlake_set_pll_edp(crtc, adjusted_mode->clock);
915 916
}

917 918 919 920 921 922 923 924 925 926 927 928
#define IDLE_ON_MASK		(PP_ON | 0 	  | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
#define IDLE_ON_VALUE   	(PP_ON | 0 	  | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)

#define IDLE_OFF_MASK		(PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
#define IDLE_OFF_VALUE		(0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)

#define IDLE_CYCLE_MASK		(PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
#define IDLE_CYCLE_VALUE	(0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)

static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
				       u32 mask,
				       u32 value)
929
{
930
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
931
	struct drm_i915_private *dev_priv = dev->dev_private;
932 933 934 935
	u32 pp_stat_reg, pp_ctrl_reg;

	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
936

937
	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
938 939 940
			mask, value,
			I915_READ(pp_stat_reg),
			I915_READ(pp_ctrl_reg));
941

942
	if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
943
		DRM_ERROR("Panel status timeout: status %08x control %08x\n",
944 945
				I915_READ(pp_stat_reg),
				I915_READ(pp_ctrl_reg));
946
	}
947
}
948

949 950 951 952
static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
{
	DRM_DEBUG_KMS("Wait for panel power on\n");
	ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
953 954
}

955 956 957 958 959 960 961 962 963 964 965 966 967
static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
{
	DRM_DEBUG_KMS("Wait for panel power off time\n");
	ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
}

static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
{
	DRM_DEBUG_KMS("Wait for panel power cycle\n");
	ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
}


968 969 970 971
/* Read the current pp_control value, unlocking the register if it
 * is locked
 */

972
static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
973
{
974 975 976 977 978 979 980
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 control;
	u32 pp_ctrl_reg;

	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;
	control = I915_READ(pp_ctrl_reg);
981 982 983 984

	control &= ~PANEL_UNLOCK_MASK;
	control |= PANEL_UNLOCK_REGS;
	return control;
985 986
}

987
void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
988
{
989
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
990 991
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
992
	u32 pp_stat_reg, pp_ctrl_reg;
993

994 995
	if (!is_edp(intel_dp))
		return;
996
	DRM_DEBUG_KMS("Turn eDP VDD on\n");
997

998 999 1000 1001
	WARN(intel_dp->want_panel_vdd,
	     "eDP VDD already requested on\n");

	intel_dp->want_panel_vdd = true;
1002

1003 1004 1005 1006 1007
	if (ironlake_edp_have_panel_vdd(intel_dp)) {
		DRM_DEBUG_KMS("eDP VDD already on\n");
		return;
	}

1008 1009 1010
	if (!ironlake_edp_have_panel_power(intel_dp))
		ironlake_wait_panel_power_cycle(intel_dp);

1011
	pp = ironlake_get_pp_control(intel_dp);
1012
	pp |= EDP_FORCE_VDD;
1013

1014 1015 1016 1017 1018 1019 1020
	pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
			I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1021 1022 1023 1024
	/*
	 * If the panel wasn't on, delay before accessing aux channel
	 */
	if (!ironlake_edp_have_panel_power(intel_dp)) {
1025
		DRM_DEBUG_KMS("eDP was not running\n");
1026 1027
		msleep(intel_dp->panel_power_up_delay);
	}
1028 1029
}

1030
static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1031
{
1032
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1033 1034
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
1035
	u32 pp_stat_reg, pp_ctrl_reg;
1036

1037 1038
	WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));

1039
	if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1040
		pp = ironlake_get_pp_control(intel_dp);
1041 1042
		pp &= ~EDP_FORCE_VDD;

1043 1044 1045 1046 1047
		pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS;
		pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;

		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1048

1049 1050 1051
		/* Make sure sequencer is idle before allowing subsequent activity */
		DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
		I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1052
		msleep(intel_dp->panel_power_down_delay);
1053 1054
	}
}
1055

1056 1057 1058 1059
static void ironlake_panel_vdd_work(struct work_struct *__work)
{
	struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
						 struct intel_dp, panel_vdd_work);
1060
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1061

1062
	mutex_lock(&dev->mode_config.mutex);
1063
	ironlake_panel_vdd_off_sync(intel_dp);
1064
	mutex_unlock(&dev->mode_config.mutex);
1065 1066
}

1067
void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1068
{
1069 1070
	if (!is_edp(intel_dp))
		return;
1071

1072 1073
	DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
	WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1074

1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087
	intel_dp->want_panel_vdd = false;

	if (sync) {
		ironlake_panel_vdd_off_sync(intel_dp);
	} else {
		/*
		 * Queue the timer to fire a long
		 * time from now (relative to the power down delay)
		 * to keep the panel power up across a sequence of operations
		 */
		schedule_delayed_work(&intel_dp->panel_vdd_work,
				      msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
	}
1088 1089
}

1090
void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1091
{
1092
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1093
	struct drm_i915_private *dev_priv = dev->dev_private;
1094
	u32 pp;
1095
	u32 pp_ctrl_reg;
1096

1097
	if (!is_edp(intel_dp))
1098
		return;
1099 1100 1101 1102 1103

	DRM_DEBUG_KMS("Turn eDP power on\n");

	if (ironlake_edp_have_panel_power(intel_dp)) {
		DRM_DEBUG_KMS("eDP power already on\n");
1104
		return;
1105
	}
1106

1107
	ironlake_wait_panel_power_cycle(intel_dp);
1108

1109
	pp = ironlake_get_pp_control(intel_dp);
1110 1111 1112 1113 1114 1115
	if (IS_GEN5(dev)) {
		/* ILK workaround: disable reset around power sequence */
		pp &= ~PANEL_POWER_RESET;
		I915_WRITE(PCH_PP_CONTROL, pp);
		POSTING_READ(PCH_PP_CONTROL);
	}
1116

1117
	pp |= POWER_TARGET_ON;
1118 1119 1120
	if (!IS_GEN5(dev))
		pp |= PANEL_POWER_RESET;

1121 1122 1123 1124
	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1125

1126
	ironlake_wait_panel_on(intel_dp);
1127

1128 1129 1130 1131 1132
	if (IS_GEN5(dev)) {
		pp |= PANEL_POWER_RESET; /* restore panel reset bit */
		I915_WRITE(PCH_PP_CONTROL, pp);
		POSTING_READ(PCH_PP_CONTROL);
	}
1133 1134
}

1135
void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1136
{
1137
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1138
	struct drm_i915_private *dev_priv = dev->dev_private;
1139
	u32 pp;
1140
	u32 pp_ctrl_reg;
1141

1142 1143
	if (!is_edp(intel_dp))
		return;
1144

1145
	DRM_DEBUG_KMS("Turn eDP power off\n");
1146

1147
	WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1148

1149
	pp = ironlake_get_pp_control(intel_dp);
1150 1151 1152
	/* We need to switch off panel power _and_ force vdd, for otherwise some
	 * panels get very unhappy and cease to work. */
	pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1153 1154 1155 1156 1157

	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1158

1159 1160
	intel_dp->want_panel_vdd = false;

1161
	ironlake_wait_panel_off(intel_dp);
1162 1163
}

1164
void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1165
{
1166 1167
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
1168
	struct drm_i915_private *dev_priv = dev->dev_private;
1169
	int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1170
	u32 pp;
1171
	u32 pp_ctrl_reg;
1172

1173 1174 1175
	if (!is_edp(intel_dp))
		return;

1176
	DRM_DEBUG_KMS("\n");
1177 1178 1179 1180 1181 1182
	/*
	 * If we enable the backlight right away following a panel power
	 * on, we may see slight flicker as the panel syncs with the eDP
	 * link.  So delay a bit to make sure the image is solid before
	 * allowing it to appear.
	 */
1183
	msleep(intel_dp->backlight_on_delay);
1184
	pp = ironlake_get_pp_control(intel_dp);
1185
	pp |= EDP_BLC_ENABLE;
1186 1187 1188 1189 1190

	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1191 1192

	intel_panel_enable_backlight(dev, pipe);
1193 1194
}

1195
void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1196
{
1197
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1198 1199
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
1200
	u32 pp_ctrl_reg;
1201

1202 1203 1204
	if (!is_edp(intel_dp))
		return;

1205 1206
	intel_panel_disable_backlight(dev);

1207
	DRM_DEBUG_KMS("\n");
1208
	pp = ironlake_get_pp_control(intel_dp);
1209
	pp &= ~EDP_BLC_ENABLE;
1210 1211 1212 1213 1214

	pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL;

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1215
	msleep(intel_dp->backlight_off_delay);
1216
}
1217

1218
static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1219
{
1220 1221 1222
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = crtc->dev;
1223 1224 1225
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

1226 1227 1228
	assert_pipe_disabled(dev_priv,
			     to_intel_crtc(crtc)->pipe);

1229 1230
	DRM_DEBUG_KMS("\n");
	dpa_ctl = I915_READ(DP_A);
1231 1232 1233 1234 1235 1236 1237 1238 1239
	WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");

	/* We don't adjust intel_dp->DP while tearing down the link, to
	 * facilitate link retraining (e.g. after hotplug). Hence clear all
	 * enable bits here to ensure that we don't enable too much. */
	intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
	intel_dp->DP |= DP_PLL_ENABLE;
	I915_WRITE(DP_A, intel_dp->DP);
1240 1241
	POSTING_READ(DP_A);
	udelay(200);
1242 1243
}

1244
static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1245
{
1246 1247 1248
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = crtc->dev;
1249 1250 1251
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

1252 1253 1254
	assert_pipe_disabled(dev_priv,
			     to_intel_crtc(crtc)->pipe);

1255
	dpa_ctl = I915_READ(DP_A);
1256 1257 1258 1259 1260 1261 1262
	WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
	     "dp pll off, should be on\n");
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");

	/* We can't rely on the value tracked for the DP register in
	 * intel_dp->DP because link_down must not change that (otherwise link
	 * re-training will fail. */
1263
	dpa_ctl &= ~DP_PLL_ENABLE;
1264
	I915_WRITE(DP_A, dpa_ctl);
1265
	POSTING_READ(DP_A);
1266 1267 1268
	udelay(200);
}

1269
/* If the sink supports it, try to set the power state appropriately */
1270
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298
{
	int ret, i;

	/* Should have a valid DPCD by this point */
	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
		return;

	if (mode != DRM_MODE_DPMS_ON) {
		ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
						  DP_SET_POWER_D3);
		if (ret != 1)
			DRM_DEBUG_DRIVER("failed to write sink power state\n");
	} else {
		/*
		 * When turning on, we need to retry for 1ms to give the sink
		 * time to wake up.
		 */
		for (i = 0; i < 3; i++) {
			ret = intel_dp_aux_native_write_1(intel_dp,
							  DP_SET_POWER,
							  DP_SET_POWER_D0);
			if (ret == 1)
				break;
			msleep(1);
		}
	}
}

1299 1300
static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
				  enum pipe *pipe)
1301
{
1302 1303 1304 1305 1306 1307 1308 1309
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 tmp = I915_READ(intel_dp->output_reg);

	if (!(tmp & DP_PORT_EN))
		return false;

1310
	if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340
		*pipe = PORT_TO_PIPE_CPT(tmp);
	} else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
		*pipe = PORT_TO_PIPE(tmp);
	} else {
		u32 trans_sel;
		u32 trans_dp;
		int i;

		switch (intel_dp->output_reg) {
		case PCH_DP_B:
			trans_sel = TRANS_DP_PORT_SEL_B;
			break;
		case PCH_DP_C:
			trans_sel = TRANS_DP_PORT_SEL_C;
			break;
		case PCH_DP_D:
			trans_sel = TRANS_DP_PORT_SEL_D;
			break;
		default:
			return true;
		}

		for_each_pipe(i) {
			trans_dp = I915_READ(TRANS_DP_CTL(i));
			if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
				*pipe = i;
				return true;
			}
		}

1341 1342 1343
		DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
			      intel_dp->output_reg);
	}
1344

1345
	return true;
1346
}
1347

1348
static void intel_disable_dp(struct intel_encoder *encoder)
1349
{
1350
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1351 1352 1353 1354

	/* Make sure the panel is off before trying to change the mode. But also
	 * ensure that we have vdd while we switch off the panel. */
	ironlake_edp_panel_vdd_on(intel_dp);
1355
	ironlake_edp_backlight_off(intel_dp);
1356
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1357
	ironlake_edp_panel_off(intel_dp);
1358 1359 1360 1361

	/* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
	if (!is_cpu_edp(intel_dp))
		intel_dp_link_down(intel_dp);
1362 1363
}

1364
static void intel_post_disable_dp(struct intel_encoder *encoder)
1365
{
1366
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1367
	struct drm_device *dev = encoder->base.dev;
1368

1369 1370
	if (is_cpu_edp(intel_dp)) {
		intel_dp_link_down(intel_dp);
1371 1372
		if (!IS_VALLEYVIEW(dev))
			ironlake_edp_pll_off(intel_dp);
1373
	}
1374 1375
}

1376
static void intel_enable_dp(struct intel_encoder *encoder)
1377
{
1378 1379 1380 1381
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1382

1383 1384
	if (WARN_ON(dp_reg & DP_PORT_EN))
		return;
1385

1386
	ironlake_edp_panel_vdd_on(intel_dp);
1387
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1388
	intel_dp_start_link_train(intel_dp);
1389
	ironlake_edp_panel_on(intel_dp);
1390
	ironlake_edp_panel_vdd_off(intel_dp, true);
1391
	intel_dp_complete_link_train(intel_dp);
1392
	ironlake_edp_backlight_on(intel_dp);
1393 1394
}

1395
static void intel_pre_enable_dp(struct intel_encoder *encoder)
1396
{
1397
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1398
	struct drm_device *dev = encoder->base.dev;
1399

1400
	if (is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev))
1401
		ironlake_edp_pll_on(intel_dp);
1402 1403 1404
}

/*
1405 1406
 * Native read with retry for link status and receiver capability reads for
 * cases where the sink may still be asleep.
1407 1408
 */
static bool
1409 1410
intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
			       uint8_t *recv, int recv_bytes)
1411
{
1412 1413
	int ret, i;

1414 1415 1416 1417
	/*
	 * Sinks are *supposed* to come up within 1ms from an off state,
	 * but we're also supposed to retry 3 times per the spec.
	 */
1418
	for (i = 0; i < 3; i++) {
1419 1420 1421
		ret = intel_dp_aux_native_read(intel_dp, address, recv,
					       recv_bytes);
		if (ret == recv_bytes)
1422 1423 1424
			return true;
		msleep(1);
	}
1425

1426
	return false;
1427 1428 1429 1430 1431 1432 1433
}

/*
 * Fetch AUX CH registers 0x202 - 0x207 which contain
 * link status information
 */
static bool
1434
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1435
{
1436 1437
	return intel_dp_aux_native_read_retry(intel_dp,
					      DP_LANE0_1_STATUS,
1438
					      link_status,
1439
					      DP_LINK_STATUS_SIZE);
1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459
}

#if 0
static char	*voltage_names[] = {
	"0.4V", "0.6V", "0.8V", "1.2V"
};
static char	*pre_emph_names[] = {
	"0dB", "3.5dB", "6dB", "9.5dB"
};
static char	*link_train_names[] = {
	"pattern 1", "pattern 2", "idle", "off"
};
#endif

/*
 * These are source-specific values; current Intel hardware supports
 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
 */

static uint8_t
K
Keith Packard 已提交
1460
intel_dp_voltage_max(struct intel_dp *intel_dp)
1461
{
1462
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
K
Keith Packard 已提交
1463 1464 1465 1466 1467 1468 1469 1470 1471 1472 1473 1474

	if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
		return DP_TRAIN_VOLTAGE_SWING_800;
	else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
		return DP_TRAIN_VOLTAGE_SWING_1200;
	else
		return DP_TRAIN_VOLTAGE_SWING_800;
}

static uint8_t
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
{
1475
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
K
Keith Packard 已提交
1476

1477
	if (HAS_DDI(dev)) {
1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_9_5;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
	} else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
K
Keith Packard 已提交
1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_600:
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
	} else {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
1511 1512 1513 1514
	}
}

static void
1515
intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1516 1517 1518 1519
{
	uint8_t v = 0;
	uint8_t p = 0;
	int lane;
K
Keith Packard 已提交
1520 1521
	uint8_t voltage_max;
	uint8_t preemph_max;
1522

1523
	for (lane = 0; lane < intel_dp->lane_count; lane++) {
1524 1525
		uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
		uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1526 1527 1528 1529 1530 1531 1532

		if (this_v > v)
			v = this_v;
		if (this_p > p)
			p = this_p;
	}

K
Keith Packard 已提交
1533
	voltage_max = intel_dp_voltage_max(intel_dp);
1534 1535
	if (v >= voltage_max)
		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1536

K
Keith Packard 已提交
1537 1538 1539
	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
	if (p >= preemph_max)
		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1540 1541

	for (lane = 0; lane < 4; lane++)
1542
		intel_dp->train_set[lane] = v | p;
1543 1544 1545
}

static uint32_t
1546
intel_gen4_signal_levels(uint8_t train_set)
1547
{
1548
	uint32_t	signal_levels = 0;
1549

1550
	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564
	case DP_TRAIN_VOLTAGE_SWING_400:
	default:
		signal_levels |= DP_VOLTAGE_0_4;
		break;
	case DP_TRAIN_VOLTAGE_SWING_600:
		signal_levels |= DP_VOLTAGE_0_6;
		break;
	case DP_TRAIN_VOLTAGE_SWING_800:
		signal_levels |= DP_VOLTAGE_0_8;
		break;
	case DP_TRAIN_VOLTAGE_SWING_1200:
		signal_levels |= DP_VOLTAGE_1_2;
		break;
	}
1565
	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582
	case DP_TRAIN_PRE_EMPHASIS_0:
	default:
		signal_levels |= DP_PRE_EMPHASIS_0;
		break;
	case DP_TRAIN_PRE_EMPHASIS_3_5:
		signal_levels |= DP_PRE_EMPHASIS_3_5;
		break;
	case DP_TRAIN_PRE_EMPHASIS_6:
		signal_levels |= DP_PRE_EMPHASIS_6;
		break;
	case DP_TRAIN_PRE_EMPHASIS_9_5:
		signal_levels |= DP_PRE_EMPHASIS_9_5;
		break;
	}
	return signal_levels;
}

1583 1584 1585 1586
/* Gen6's DP voltage swing and pre-emphasis control */
static uint32_t
intel_gen6_edp_signal_levels(uint8_t train_set)
{
1587 1588 1589
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
1590
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1591 1592 1593 1594
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1595
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1596 1597
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
		return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1598
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1599 1600
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1601
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1602 1603
	case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1604
	default:
1605 1606 1607
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1608 1609 1610
	}
}

K
Keith Packard 已提交
1611 1612 1613 1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641
/* Gen7's DP voltage swing and pre-emphasis control */
static uint32_t
intel_gen7_edp_signal_levels(uint8_t train_set)
{
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_400MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
		return EDP_LINK_TRAIN_400MV_6DB_IVB;

	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_600MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_600MV_3_5DB_IVB;

	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_800MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_800MV_3_5DB_IVB;

	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_500MV_0DB_IVB;
	}
}

1642 1643
/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
static uint32_t
1644
intel_hsw_signal_levels(uint8_t train_set)
1645
{
1646 1647 1648 1649 1650 1651 1652 1653 1654 1655 1656
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_400MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_400MV_3_5DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
		return DDI_BUF_EMP_400MV_6DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
		return DDI_BUF_EMP_400MV_9_5DB_HSW;
1657

1658 1659 1660 1661 1662 1663
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_600MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_600MV_3_5DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
		return DDI_BUF_EMP_600MV_6DB_HSW;
1664

1665 1666 1667 1668 1669 1670 1671 1672
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_800MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_800MV_3_5DB_HSW;
	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return DDI_BUF_EMP_400MV_0DB_HSW;
1673 1674 1675
	}
}

1676 1677 1678 1679 1680 1681 1682 1683 1684
/* Properly updates "DP" with the correct signal levels. */
static void
intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	uint32_t signal_levels, mask;
	uint8_t train_set = intel_dp->train_set[0];

1685
	if (HAS_DDI(dev)) {
1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703
		signal_levels = intel_hsw_signal_levels(train_set);
		mask = DDI_BUF_EMP_MASK;
	} else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
		signal_levels = intel_gen7_edp_signal_levels(train_set);
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
	} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
		signal_levels = intel_gen6_edp_signal_levels(train_set);
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
	} else {
		signal_levels = intel_gen4_signal_levels(train_set);
		mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
	}

	DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);

	*DP = (*DP & ~mask) | signal_levels;
}

1704
static bool
C
Chris Wilson 已提交
1705
intel_dp_set_link_train(struct intel_dp *intel_dp,
1706
			uint32_t dp_reg_value,
1707
			uint8_t dp_train_pat)
1708
{
1709 1710
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
1711
	struct drm_i915_private *dev_priv = dev->dev_private;
1712
	enum port port = intel_dig_port->port;
1713
	int ret;
1714
	uint32_t temp;
1715

1716
	if (HAS_DDI(dev)) {
1717
		temp = I915_READ(DP_TP_CTL(port));
1718 1719 1720 1721 1722 1723 1724 1725 1726 1727

		if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
			temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
		else
			temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;

		temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:

1728 1729 1730 1731 1732 1733 1734 1735 1736 1737
			if (port != PORT_A) {
				temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
				I915_WRITE(DP_TP_CTL(port), temp);

				if (wait_for((I915_READ(DP_TP_STATUS(port)) &
					      DP_TP_STATUS_IDLE_DONE), 1))
					DRM_ERROR("Timed out waiting for DP idle patterns\n");

				temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
			}
1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751

			temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;

			break;
		case DP_TRAINING_PATTERN_1:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
			break;
		case DP_TRAINING_PATTERN_2:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
			break;
		case DP_TRAINING_PATTERN_3:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
			break;
		}
1752
		I915_WRITE(DP_TP_CTL(port), temp);
1753 1754 1755

	} else if (HAS_PCH_CPT(dev) &&
		   (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793
		dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
			break;
		case DP_TRAINING_PATTERN_1:
			dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
			break;
		case DP_TRAINING_PATTERN_2:
			dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
			break;
		case DP_TRAINING_PATTERN_3:
			DRM_ERROR("DP training pattern 3 not supported\n");
			dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
			break;
		}

	} else {
		dp_reg_value &= ~DP_LINK_TRAIN_MASK;

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			dp_reg_value |= DP_LINK_TRAIN_OFF;
			break;
		case DP_TRAINING_PATTERN_1:
			dp_reg_value |= DP_LINK_TRAIN_PAT_1;
			break;
		case DP_TRAINING_PATTERN_2:
			dp_reg_value |= DP_LINK_TRAIN_PAT_2;
			break;
		case DP_TRAINING_PATTERN_3:
			DRM_ERROR("DP training pattern 3 not supported\n");
			dp_reg_value |= DP_LINK_TRAIN_PAT_2;
			break;
		}
	}

C
Chris Wilson 已提交
1794 1795
	I915_WRITE(intel_dp->output_reg, dp_reg_value);
	POSTING_READ(intel_dp->output_reg);
1796

C
Chris Wilson 已提交
1797
	intel_dp_aux_native_write_1(intel_dp,
1798 1799 1800
				    DP_TRAINING_PATTERN_SET,
				    dp_train_pat);

1801 1802 1803 1804 1805 1806 1807 1808 1809
	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
	    DP_TRAINING_PATTERN_DISABLE) {
		ret = intel_dp_aux_native_write(intel_dp,
						DP_TRAINING_LANE0_SET,
						intel_dp->train_set,
						intel_dp->lane_count);
		if (ret != intel_dp->lane_count)
			return false;
	}
1810 1811 1812 1813

	return true;
}

1814
/* Enable corresponding port and start training pattern 1 */
1815
void
1816
intel_dp_start_link_train(struct intel_dp *intel_dp)
1817
{
1818
	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
1819
	struct drm_device *dev = encoder->dev;
1820 1821 1822
	int i;
	uint8_t voltage;
	bool clock_recovery = false;
1823
	int voltage_tries, loop_tries;
C
Chris Wilson 已提交
1824
	uint32_t DP = intel_dp->DP;
1825

P
Paulo Zanoni 已提交
1826
	if (HAS_DDI(dev))
1827 1828
		intel_ddi_prepare_link_retrain(encoder);

1829 1830 1831 1832
	/* Write the link configuration data */
	intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
				  intel_dp->link_configuration,
				  DP_LINK_CONFIGURATION_SIZE);
1833 1834

	DP |= DP_PORT_EN;
K
Keith Packard 已提交
1835

1836
	memset(intel_dp->train_set, 0, 4);
1837
	voltage = 0xff;
1838 1839
	voltage_tries = 0;
	loop_tries = 0;
1840 1841
	clock_recovery = false;
	for (;;) {
1842
		/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1843
		uint8_t	    link_status[DP_LINK_STATUS_SIZE];
1844 1845

		intel_dp_set_signal_levels(intel_dp, &DP);
1846

1847
		/* Set training pattern 1 */
1848
		if (!intel_dp_set_link_train(intel_dp, DP,
1849 1850
					     DP_TRAINING_PATTERN_1 |
					     DP_LINK_SCRAMBLING_DISABLE))
1851 1852
			break;

1853
		drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
1854 1855
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
1856
			break;
1857
		}
1858

1859
		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1860
			DRM_DEBUG_KMS("clock recovery OK\n");
1861 1862 1863 1864 1865 1866 1867
			clock_recovery = true;
			break;
		}

		/* Check to see if we've tried the max voltage */
		for (i = 0; i < intel_dp->lane_count; i++)
			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1868
				break;
1869
		if (i == intel_dp->lane_count) {
1870 1871
			++loop_tries;
			if (loop_tries == 5) {
1872 1873 1874 1875 1876 1877 1878
				DRM_DEBUG_KMS("too many full retries, give up\n");
				break;
			}
			memset(intel_dp->train_set, 0, 4);
			voltage_tries = 0;
			continue;
		}
1879

1880
		/* Check to see if we've tried the same voltage 5 times */
1881
		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1882
			++voltage_tries;
1883 1884 1885 1886 1887 1888 1889
			if (voltage_tries == 5) {
				DRM_DEBUG_KMS("too many voltage retries, give up\n");
				break;
			}
		} else
			voltage_tries = 0;
		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1890

1891
		/* Compute new intel_dp->train_set as requested by target */
1892
		intel_get_adjust_train(intel_dp, link_status);
1893 1894
	}

1895 1896 1897
	intel_dp->DP = DP;
}

1898
void
1899 1900 1901
intel_dp_complete_link_train(struct intel_dp *intel_dp)
{
	bool channel_eq = false;
1902
	int tries, cr_tries;
1903 1904
	uint32_t DP = intel_dp->DP;

1905 1906
	/* channel equalization */
	tries = 0;
1907
	cr_tries = 0;
1908 1909
	channel_eq = false;
	for (;;) {
1910
		uint8_t	    link_status[DP_LINK_STATUS_SIZE];
1911

1912 1913 1914 1915 1916 1917
		if (cr_tries > 5) {
			DRM_ERROR("failed to train DP, aborting\n");
			intel_dp_link_down(intel_dp);
			break;
		}

1918
		intel_dp_set_signal_levels(intel_dp, &DP);
1919

1920
		/* channel eq pattern */
1921
		if (!intel_dp_set_link_train(intel_dp, DP,
1922 1923
					     DP_TRAINING_PATTERN_2 |
					     DP_LINK_SCRAMBLING_DISABLE))
1924 1925
			break;

1926
		drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
1927
		if (!intel_dp_get_link_status(intel_dp, link_status))
1928 1929
			break;

1930
		/* Make sure clock is still ok */
1931
		if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1932 1933 1934 1935 1936
			intel_dp_start_link_train(intel_dp);
			cr_tries++;
			continue;
		}

1937
		if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
1938 1939 1940
			channel_eq = true;
			break;
		}
1941

1942 1943 1944 1945 1946 1947 1948 1949
		/* Try 5 times, then try clock recovery if that fails */
		if (tries > 5) {
			intel_dp_link_down(intel_dp);
			intel_dp_start_link_train(intel_dp);
			tries = 0;
			cr_tries++;
			continue;
		}
1950

1951
		/* Compute new intel_dp->train_set as requested by target */
1952
		intel_get_adjust_train(intel_dp, link_status);
1953
		++tries;
1954
	}
1955

1956 1957 1958
	if (channel_eq)
		DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");

1959
	intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
1960 1961 1962
}

static void
C
Chris Wilson 已提交
1963
intel_dp_link_down(struct intel_dp *intel_dp)
1964
{
1965 1966
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
1967
	struct drm_i915_private *dev_priv = dev->dev_private;
1968 1969
	struct intel_crtc *intel_crtc =
		to_intel_crtc(intel_dig_port->base.base.crtc);
C
Chris Wilson 已提交
1970
	uint32_t DP = intel_dp->DP;
1971

1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982 1983 1984 1985 1986
	/*
	 * DDI code has a strict mode set sequence and we should try to respect
	 * it, otherwise we might hang the machine in many different ways. So we
	 * really should be disabling the port only on a complete crtc_disable
	 * sequence. This function is just called under two conditions on DDI
	 * code:
	 * - Link train failed while doing crtc_enable, and on this case we
	 *   really should respect the mode set sequence and wait for a
	 *   crtc_disable.
	 * - Someone turned the monitor off and intel_dp_check_link_status
	 *   called us. We don't need to disable the whole port on this case, so
	 *   when someone turns the monitor on again,
	 *   intel_ddi_prepare_link_retrain will take care of redoing the link
	 *   train.
	 */
P
Paulo Zanoni 已提交
1987
	if (HAS_DDI(dev))
1988 1989
		return;

1990
	if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1991 1992
		return;

1993
	DRM_DEBUG_KMS("\n");
1994

K
Keith Packard 已提交
1995
	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1996
		DP &= ~DP_LINK_TRAIN_MASK_CPT;
C
Chris Wilson 已提交
1997
		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1998 1999
	} else {
		DP &= ~DP_LINK_TRAIN_MASK;
C
Chris Wilson 已提交
2000
		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2001
	}
2002
	POSTING_READ(intel_dp->output_reg);
2003

2004 2005
	/* We don't really know why we're doing this */
	intel_wait_for_vblank(dev, intel_crtc->pipe);
2006

2007
	if (HAS_PCH_IBX(dev) &&
2008
	    I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2009
		struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2010

2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024
		/* Hardware workaround: leaving our transcoder select
		 * set to transcoder B while it's off will prevent the
		 * corresponding HDMI output on transcoder A.
		 *
		 * Combine this with another hardware workaround:
		 * transcoder select bit can only be cleared while the
		 * port is enabled.
		 */
		DP &= ~DP_PIPEB_SELECT;
		I915_WRITE(intel_dp->output_reg, DP);

		/* Changes to enable or select take place the vblank
		 * after being written.
		 */
2025 2026 2027 2028
		if (WARN_ON(crtc == NULL)) {
			/* We should never try to disable a port without a crtc
			 * attached. For paranoia keep the code around for a
			 * bit. */
2029 2030 2031
			POSTING_READ(intel_dp->output_reg);
			msleep(50);
		} else
2032
			intel_wait_for_vblank(dev, intel_crtc->pipe);
2033 2034
	}

2035
	DP &= ~DP_AUDIO_OUTPUT_ENABLE;
C
Chris Wilson 已提交
2036 2037
	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);
2038
	msleep(intel_dp->panel_power_down_delay);
2039 2040
}

2041 2042
static bool
intel_dp_get_dpcd(struct intel_dp *intel_dp)
2043
{
2044 2045
	char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];

2046
	if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2047 2048
					   sizeof(intel_dp->dpcd)) == 0)
		return false; /* aux transfer failed */
2049

2050 2051 2052 2053
	hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
			   32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
	DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);

2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069
	if (intel_dp->dpcd[DP_DPCD_REV] == 0)
		return false; /* DPCD not present */

	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
	      DP_DWN_STRM_PORT_PRESENT))
		return true; /* native DP sink */

	if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
		return true; /* no per-port downstream info */

	if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
					   intel_dp->downstream_ports,
					   DP_MAX_DOWNSTREAM_PORTS) == 0)
		return false; /* downstream port status fetch failed */

	return true;
2070 2071
}

2072 2073 2074 2075 2076 2077 2078 2079
static void
intel_dp_probe_oui(struct intel_dp *intel_dp)
{
	u8 buf[3];

	if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
		return;

D
Daniel Vetter 已提交
2080 2081
	ironlake_edp_panel_vdd_on(intel_dp);

2082 2083 2084 2085 2086 2087 2088
	if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
		DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);

	if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
		DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);
D
Daniel Vetter 已提交
2089 2090

	ironlake_edp_panel_vdd_off(intel_dp, false);
2091 2092
}

2093 2094 2095 2096 2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110
static bool
intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
	int ret;

	ret = intel_dp_aux_native_read_retry(intel_dp,
					     DP_DEVICE_SERVICE_IRQ_VECTOR,
					     sink_irq_vector, 1);
	if (!ret)
		return false;

	return true;
}

static void
intel_dp_handle_test_request(struct intel_dp *intel_dp)
{
	/* NAK by default */
2111
	intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2112 2113
}

2114 2115 2116 2117 2118 2119 2120 2121 2122
/*
 * According to DP spec
 * 5.1.2:
 *  1. Read DPCD
 *  2. Configure link according to Receiver Capabilities
 *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
 *  4. Check link status on receipt of hot-plug interrupt
 */

P
Paulo Zanoni 已提交
2123
void
C
Chris Wilson 已提交
2124
intel_dp_check_link_status(struct intel_dp *intel_dp)
2125
{
2126
	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2127
	u8 sink_irq_vector;
2128
	u8 link_status[DP_LINK_STATUS_SIZE];
2129

2130
	if (!intel_encoder->connectors_active)
2131
		return;
2132

2133
	if (WARN_ON(!intel_encoder->base.crtc))
2134 2135
		return;

2136
	/* Try to read receiver status if the link appears to be up */
2137
	if (!intel_dp_get_link_status(intel_dp, link_status)) {
C
Chris Wilson 已提交
2138
		intel_dp_link_down(intel_dp);
2139 2140 2141
		return;
	}

2142
	/* Now read the DPCD to see if it's actually running */
2143
	if (!intel_dp_get_dpcd(intel_dp)) {
2144 2145 2146 2147
		intel_dp_link_down(intel_dp);
		return;
	}

2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161
	/* Try to read the source of the interrupt */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
		/* Clear interrupt source */
		intel_dp_aux_native_write_1(intel_dp,
					    DP_DEVICE_SERVICE_IRQ_VECTOR,
					    sink_irq_vector);

		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
			intel_dp_handle_test_request(intel_dp);
		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
	}

2162
	if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2163
		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2164
			      drm_get_encoder_name(&intel_encoder->base));
2165 2166 2167
		intel_dp_start_link_train(intel_dp);
		intel_dp_complete_link_train(intel_dp);
	}
2168 2169
}

2170
/* XXX this is probably wrong for multiple downstream ports */
2171
static enum drm_connector_status
2172
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2173
{
2174 2175 2176 2177 2178 2179 2180 2181 2182
	uint8_t *dpcd = intel_dp->dpcd;
	bool hpd;
	uint8_t type;

	if (!intel_dp_get_dpcd(intel_dp))
		return connector_status_disconnected;

	/* if there's no downstream port, we're done */
	if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2183
		return connector_status_connected;
2184 2185 2186 2187

	/* If we're HPD-aware, SINK_COUNT changes dynamically */
	hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
	if (hpd) {
2188
		uint8_t reg;
2189
		if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2190
						    &reg, 1))
2191
			return connector_status_unknown;
2192 2193
		return DP_GET_SINK_COUNT(reg) ? connector_status_connected
					      : connector_status_disconnected;
2194 2195 2196 2197
	}

	/* If no HPD, poke DDC gently */
	if (drm_probe_ddc(&intel_dp->adapter))
2198
		return connector_status_connected;
2199 2200 2201 2202 2203 2204 2205 2206

	/* Well we tried, say unknown for unreliable port types */
	type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
	if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
		return connector_status_unknown;

	/* Anything else is out of spec, warn and ignore */
	DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2207
	return connector_status_disconnected;
2208 2209
}

2210
static enum drm_connector_status
Z
Zhenyu Wang 已提交
2211
ironlake_dp_detect(struct intel_dp *intel_dp)
2212
{
2213
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2214 2215
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2216 2217
	enum drm_connector_status status;

2218 2219
	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp)) {
2220
		status = intel_panel_detect(dev);
2221 2222 2223 2224
		if (status == connector_status_unknown)
			status = connector_status_connected;
		return status;
	}
2225

2226 2227 2228
	if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
		return connector_status_disconnected;

2229
	return intel_dp_detect_dpcd(intel_dp);
2230 2231
}

2232
static enum drm_connector_status
Z
Zhenyu Wang 已提交
2233
g4x_dp_detect(struct intel_dp *intel_dp)
2234
{
2235
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2236
	struct drm_i915_private *dev_priv = dev->dev_private;
2237
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2238
	uint32_t bit;
2239

2240 2241 2242 2243 2244 2245 2246 2247 2248 2249
	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp)) {
		enum drm_connector_status status;

		status = intel_panel_detect(dev);
		if (status == connector_status_unknown)
			status = connector_status_connected;
		return status;
	}

2250 2251
	switch (intel_dig_port->port) {
	case PORT_B:
2252
		bit = PORTB_HOTPLUG_LIVE_STATUS;
2253
		break;
2254
	case PORT_C:
2255
		bit = PORTC_HOTPLUG_LIVE_STATUS;
2256
		break;
2257
	case PORT_D:
2258
		bit = PORTD_HOTPLUG_LIVE_STATUS;
2259 2260 2261 2262 2263
		break;
	default:
		return connector_status_unknown;
	}

2264
	if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2265 2266
		return connector_status_disconnected;

2267
	return intel_dp_detect_dpcd(intel_dp);
Z
Zhenyu Wang 已提交
2268 2269
}

2270 2271 2272
static struct edid *
intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
{
2273
	struct intel_connector *intel_connector = to_intel_connector(connector);
2274

2275 2276 2277 2278 2279 2280 2281
	/* use cached edid if we have one */
	if (intel_connector->edid) {
		struct edid *edid;
		int size;

		/* invalid edid */
		if (IS_ERR(intel_connector->edid))
2282 2283
			return NULL;

2284
		size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2285 2286 2287 2288
		edid = kmalloc(size, GFP_KERNEL);
		if (!edid)
			return NULL;

2289
		memcpy(edid, intel_connector->edid, size);
2290 2291
		return edid;
	}
2292

2293
	return drm_get_edid(connector, adapter);
2294 2295 2296 2297 2298
}

static int
intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
{
2299
	struct intel_connector *intel_connector = to_intel_connector(connector);
2300

2301 2302 2303 2304 2305 2306 2307 2308
	/* use cached edid if we have one */
	if (intel_connector->edid) {
		/* invalid edid */
		if (IS_ERR(intel_connector->edid))
			return 0;

		return intel_connector_update_modes(connector,
						    intel_connector->edid);
2309 2310
	}

2311
	return intel_ddc_get_modes(connector, adapter);
2312 2313
}

Z
Zhenyu Wang 已提交
2314 2315 2316 2317
static enum drm_connector_status
intel_dp_detect(struct drm_connector *connector, bool force)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
2318 2319
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
2320
	struct drm_device *dev = connector->dev;
Z
Zhenyu Wang 已提交
2321 2322 2323 2324 2325 2326 2327 2328 2329
	enum drm_connector_status status;
	struct edid *edid = NULL;

	intel_dp->has_audio = false;

	if (HAS_PCH_SPLIT(dev))
		status = ironlake_dp_detect(intel_dp);
	else
		status = g4x_dp_detect(intel_dp);
2330

Z
Zhenyu Wang 已提交
2331 2332 2333
	if (status != connector_status_connected)
		return status;

2334 2335
	intel_dp_probe_oui(intel_dp);

2336 2337
	if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
		intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2338
	} else {
2339
		edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2340 2341 2342 2343
		if (edid) {
			intel_dp->has_audio = drm_detect_monitor_audio(edid);
			kfree(edid);
		}
Z
Zhenyu Wang 已提交
2344 2345
	}

2346 2347
	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
Z
Zhenyu Wang 已提交
2348
	return connector_status_connected;
2349 2350 2351 2352
}

static int intel_dp_get_modes(struct drm_connector *connector)
{
2353
	struct intel_dp *intel_dp = intel_attached_dp(connector);
2354
	struct intel_connector *intel_connector = to_intel_connector(connector);
2355
	struct drm_device *dev = connector->dev;
2356
	int ret;
2357 2358 2359 2360

	/* We should parse the EDID data and find out if it has an audio sink
	 */

2361
	ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2362
	if (ret)
2363 2364
		return ret;

2365
	/* if eDP has no EDID, fall back to fixed mode */
2366
	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2367
		struct drm_display_mode *mode;
2368 2369
		mode = drm_mode_duplicate(dev,
					  intel_connector->panel.fixed_mode);
2370
		if (mode) {
2371 2372 2373 2374 2375
			drm_mode_probed_add(connector, mode);
			return 1;
		}
	}
	return 0;
2376 2377
}

2378 2379 2380 2381 2382 2383 2384
static bool
intel_dp_detect_audio(struct drm_connector *connector)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
	struct edid *edid;
	bool has_audio = false;

2385
	edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2386 2387 2388 2389 2390 2391 2392 2393
	if (edid) {
		has_audio = drm_detect_monitor_audio(edid);
		kfree(edid);
	}

	return has_audio;
}

2394 2395 2396 2397 2398
static int
intel_dp_set_property(struct drm_connector *connector,
		      struct drm_property *property,
		      uint64_t val)
{
2399
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
2400
	struct intel_connector *intel_connector = to_intel_connector(connector);
2401 2402
	struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2403 2404
	int ret;

2405
	ret = drm_object_property_set_value(&connector->base, property, val);
2406 2407 2408
	if (ret)
		return ret;

2409
	if (property == dev_priv->force_audio_property) {
2410 2411 2412 2413
		int i = val;
		bool has_audio;

		if (i == intel_dp->force_audio)
2414 2415
			return 0;

2416
		intel_dp->force_audio = i;
2417

2418
		if (i == HDMI_AUDIO_AUTO)
2419 2420
			has_audio = intel_dp_detect_audio(connector);
		else
2421
			has_audio = (i == HDMI_AUDIO_ON);
2422 2423

		if (has_audio == intel_dp->has_audio)
2424 2425
			return 0;

2426
		intel_dp->has_audio = has_audio;
2427 2428 2429
		goto done;
	}

2430
	if (property == dev_priv->broadcast_rgb_property) {
2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445
		switch (val) {
		case INTEL_BROADCAST_RGB_AUTO:
			intel_dp->color_range_auto = true;
			break;
		case INTEL_BROADCAST_RGB_FULL:
			intel_dp->color_range_auto = false;
			intel_dp->color_range = 0;
			break;
		case INTEL_BROADCAST_RGB_LIMITED:
			intel_dp->color_range_auto = false;
			intel_dp->color_range = DP_COLOR_RANGE_16_235;
			break;
		default:
			return -EINVAL;
		}
2446 2447 2448
		goto done;
	}

2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464
	if (is_edp(intel_dp) &&
	    property == connector->dev->mode_config.scaling_mode_property) {
		if (val == DRM_MODE_SCALE_NONE) {
			DRM_DEBUG_KMS("no scaling not supported\n");
			return -EINVAL;
		}

		if (intel_connector->panel.fitting_mode == val) {
			/* the eDP scaling property is not changed */
			return 0;
		}
		intel_connector->panel.fitting_mode = val;

		goto done;
	}

2465 2466 2467
	return -EINVAL;

done:
2468 2469
	if (intel_encoder->base.crtc)
		intel_crtc_restore_mode(intel_encoder->base.crtc);
2470 2471 2472 2473

	return 0;
}

2474
static void
2475
intel_dp_destroy(struct drm_connector *connector)
2476
{
2477
	struct intel_dp *intel_dp = intel_attached_dp(connector);
2478
	struct intel_connector *intel_connector = to_intel_connector(connector);
2479

2480 2481 2482
	if (!IS_ERR_OR_NULL(intel_connector->edid))
		kfree(intel_connector->edid);

2483
	if (is_edp(intel_dp))
2484
		intel_panel_fini(&intel_connector->panel);
2485

2486 2487
	drm_sysfs_connector_remove(connector);
	drm_connector_cleanup(connector);
2488
	kfree(connector);
2489 2490
}

P
Paulo Zanoni 已提交
2491
void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2492
{
2493 2494
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_dp *intel_dp = &intel_dig_port->dp;
2495 2496 2497

	i2c_del_adapter(&intel_dp->adapter);
	drm_encoder_cleanup(encoder);
2498 2499 2500 2501
	if (is_edp(intel_dp)) {
		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
		ironlake_panel_vdd_off_sync(intel_dp);
	}
2502
	kfree(intel_dig_port);
2503 2504
}

2505 2506 2507 2508 2509
static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
	.mode_set = intel_dp_mode_set,
};

static const struct drm_connector_funcs intel_dp_connector_funcs = {
2510
	.dpms = intel_connector_dpms,
2511 2512
	.detect = intel_dp_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
2513
	.set_property = intel_dp_set_property,
2514 2515 2516 2517 2518 2519
	.destroy = intel_dp_destroy,
};

static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
	.get_modes = intel_dp_get_modes,
	.mode_valid = intel_dp_mode_valid,
2520
	.best_encoder = intel_best_encoder,
2521 2522 2523
};

static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2524
	.destroy = intel_dp_encoder_destroy,
2525 2526
};

2527
static void
2528
intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2529
{
2530
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2531

2532
	intel_dp_check_link_status(intel_dp);
2533
}
2534

2535 2536
/* Return which DP Port should be selected for Transcoder DP control */
int
2537
intel_trans_dp_port_sel(struct drm_crtc *crtc)
2538 2539
{
	struct drm_device *dev = crtc->dev;
2540 2541
	struct intel_encoder *intel_encoder;
	struct intel_dp *intel_dp;
2542

2543 2544
	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		intel_dp = enc_to_intel_dp(&intel_encoder->base);
2545

2546 2547
		if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
		    intel_encoder->type == INTEL_OUTPUT_EDP)
C
Chris Wilson 已提交
2548
			return intel_dp->output_reg;
2549
	}
C
Chris Wilson 已提交
2550

2551 2552 2553
	return -1;
}

2554
/* check the VBT to see whether the eDP is on DP-D port */
2555
bool intel_dpd_is_edp(struct drm_device *dev)
2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct child_device_config *p_child;
	int i;

	if (!dev_priv->child_dev_num)
		return false;

	for (i = 0; i < dev_priv->child_dev_num; i++) {
		p_child = dev_priv->child_dev + i;

		if (p_child->dvo_port == PORT_IDPD &&
		    p_child->device_type == DEVICE_TYPE_eDP)
			return true;
	}
	return false;
}

2574 2575 2576
static void
intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
{
2577 2578
	struct intel_connector *intel_connector = to_intel_connector(connector);

2579
	intel_attach_force_audio_property(connector);
2580
	intel_attach_broadcast_rgb_property(connector);
2581
	intel_dp->color_range_auto = true;
2582 2583 2584

	if (is_edp(intel_dp)) {
		drm_mode_create_scaling_mode_property(connector->dev);
2585 2586
		drm_object_attach_property(
			&connector->base,
2587
			connector->dev->mode_config.scaling_mode_property,
2588 2589
			DRM_MODE_SCALE_ASPECT);
		intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2590
	}
2591 2592
}

2593 2594
static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2595 2596
				    struct intel_dp *intel_dp,
				    struct edp_power_seq *out)
2597 2598 2599 2600
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct edp_power_seq cur, vbt, spec, final;
	u32 pp_on, pp_off, pp_div, pp;
2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613
	int pp_control_reg, pp_on_reg, pp_off_reg, pp_div_reg;

	if (HAS_PCH_SPLIT(dev)) {
		pp_control_reg = PCH_PP_CONTROL;
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
		pp_control_reg = PIPEA_PP_CONTROL;
		pp_on_reg = PIPEA_PP_ON_DELAYS;
		pp_off_reg = PIPEA_PP_OFF_DELAYS;
		pp_div_reg = PIPEA_PP_DIVISOR;
	}
2614 2615 2616

	/* Workaround: Need to write PP_CONTROL with the unlock key as
	 * the very first thing. */
2617 2618
	pp = ironlake_get_pp_control(intel_dp);
	I915_WRITE(pp_control_reg, pp);
2619

2620 2621 2622
	pp_on = I915_READ(pp_on_reg);
	pp_off = I915_READ(pp_off_reg);
	pp_div = I915_READ(pp_div_reg);
2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679

	/* Pull timing values out of registers */
	cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
		PANEL_POWER_UP_DELAY_SHIFT;

	cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
		PANEL_LIGHT_ON_DELAY_SHIFT;

	cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
		PANEL_LIGHT_OFF_DELAY_SHIFT;

	cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
		PANEL_POWER_DOWN_DELAY_SHIFT;

	cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
		       PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;

	DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);

	vbt = dev_priv->edp.pps;

	/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
	 * our hw here, which are all in 100usec. */
	spec.t1_t3 = 210 * 10;
	spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
	spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
	spec.t10 = 500 * 10;
	/* This one is special and actually in units of 100ms, but zero
	 * based in the hw (so we need to add 100 ms). But the sw vbt
	 * table multiplies it with 1000 to make it in units of 100usec,
	 * too. */
	spec.t11_t12 = (510 + 100) * 10;

	DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);

	/* Use the max of the register settings and vbt. If both are
	 * unset, fall back to the spec limits. */
#define assign_final(field)	final.field = (max(cur.field, vbt.field) == 0 ? \
				       spec.field : \
				       max(cur.field, vbt.field))
	assign_final(t1_t3);
	assign_final(t8);
	assign_final(t9);
	assign_final(t10);
	assign_final(t11_t12);
#undef assign_final

#define get_delay(field)	(DIV_ROUND_UP(final.field, 10))
	intel_dp->panel_power_up_delay = get_delay(t1_t3);
	intel_dp->backlight_on_delay = get_delay(t8);
	intel_dp->backlight_off_delay = get_delay(t9);
	intel_dp->panel_power_down_delay = get_delay(t10);
	intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
#undef get_delay

2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696
	DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
		      intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
		      intel_dp->panel_power_cycle_delay);

	DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
		      intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);

	if (out)
		*out = final;
}

static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
					      struct intel_dp *intel_dp,
					      struct edp_power_seq *seq)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712
	u32 pp_on, pp_off, pp_div, port_sel = 0;
	int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
	int pp_on_reg, pp_off_reg, pp_div_reg;

	if (HAS_PCH_SPLIT(dev)) {
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
		pp_on_reg = PIPEA_PP_ON_DELAYS;
		pp_off_reg = PIPEA_PP_OFF_DELAYS;
		pp_div_reg = PIPEA_PP_DIVISOR;
	}

	if (IS_VALLEYVIEW(dev))
		port_sel = I915_READ(pp_on_reg) & 0xc0000000;
2713

2714
	/* And finally store the new values in the power sequencer. */
2715 2716 2717 2718
	pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
		(seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
	pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2719 2720
	/* Compute the divisor for the pp clock, simply match the Bspec
	 * formula. */
2721
	pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
2722
	pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2723 2724 2725 2726 2727 2728
			<< PANEL_POWER_CYCLE_DELAY_SHIFT);

	/* Haswell doesn't have any port selection bits for the panel
	 * power sequencer any more. */
	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
		if (is_cpu_edp(intel_dp))
2729
			port_sel = PANEL_POWER_PORT_DP_A;
2730
		else
2731
			port_sel = PANEL_POWER_PORT_DP_D;
2732 2733
	}

2734 2735 2736 2737 2738
	pp_on |= port_sel;

	I915_WRITE(pp_on_reg, pp_on);
	I915_WRITE(pp_off_reg, pp_off);
	I915_WRITE(pp_div_reg, pp_div);
2739 2740

	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2741 2742 2743
		      I915_READ(pp_on_reg),
		      I915_READ(pp_off_reg),
		      I915_READ(pp_div_reg));
2744 2745
}

2746
void
2747 2748
intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
			struct intel_connector *intel_connector)
2749
{
2750 2751 2752 2753
	struct drm_connector *connector = &intel_connector->base;
	struct intel_dp *intel_dp = &intel_dig_port->dp;
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
2754
	struct drm_i915_private *dev_priv = dev->dev_private;
2755
	struct drm_display_mode *fixed_mode = NULL;
2756
	struct edp_power_seq power_seq = { 0 };
2757
	enum port port = intel_dig_port->port;
2758
	const char *name = NULL;
2759
	int type;
2760

2761 2762
	/* Preserve the current hw state. */
	intel_dp->DP = I915_READ(intel_dp->output_reg);
2763
	intel_dp->attached_connector = intel_connector;
2764

2765
	if (HAS_PCH_SPLIT(dev) && port == PORT_D)
2766
		if (intel_dpd_is_edp(dev))
C
Chris Wilson 已提交
2767
			intel_dp->is_pch_edp = true;
2768

2769 2770 2771 2772
	/*
	 * FIXME : We need to initialize built-in panels before external panels.
	 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
	 */
2773
	if (IS_VALLEYVIEW(dev) && port == PORT_C) {
2774 2775
		type = DRM_MODE_CONNECTOR_eDP;
		intel_encoder->type = INTEL_OUTPUT_EDP;
2776
	} else if (port == PORT_A || is_pch_edp(intel_dp)) {
2777 2778 2779
		type = DRM_MODE_CONNECTOR_eDP;
		intel_encoder->type = INTEL_OUTPUT_EDP;
	} else {
P
Paulo Zanoni 已提交
2780 2781 2782 2783
		/* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
		 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
		 * rewrite it.
		 */
2784 2785 2786 2787
		type = DRM_MODE_CONNECTOR_DisplayPort;
	}

	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2788 2789 2790 2791 2792
	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);

	connector->interlace_allowed = true;
	connector->doublescan_allowed = 0;

2793 2794
	INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
			  ironlake_panel_vdd_work);
2795

2796
	intel_connector_attach_encoder(intel_connector, intel_encoder);
2797 2798
	drm_sysfs_connector_add(connector);

P
Paulo Zanoni 已提交
2799
	if (HAS_DDI(dev))
2800 2801 2802 2803
		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
	else
		intel_connector->get_hw_state = intel_connector_get_hw_state;

2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822
	intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
	if (HAS_DDI(dev)) {
		switch (intel_dig_port->port) {
		case PORT_A:
			intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
			break;
		case PORT_B:
			intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
			break;
		case PORT_C:
			intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
			break;
		case PORT_D:
			intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
			break;
		default:
			BUG();
		}
	}
2823

2824
	/* Set up the DDC bus. */
2825 2826
	switch (port) {
	case PORT_A:
2827
		intel_encoder->hpd_pin = HPD_PORT_A;
2828 2829 2830
		name = "DPDDC-A";
		break;
	case PORT_B:
2831
		intel_encoder->hpd_pin = HPD_PORT_B;
2832 2833 2834
		name = "DPDDC-B";
		break;
	case PORT_C:
2835
		intel_encoder->hpd_pin = HPD_PORT_C;
2836 2837 2838
		name = "DPDDC-C";
		break;
	case PORT_D:
2839
		intel_encoder->hpd_pin = HPD_PORT_D;
2840 2841 2842
		name = "DPDDC-D";
		break;
	default:
2843
		BUG();
2844 2845
	}

2846
	if (is_edp(intel_dp))
2847
		intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2848 2849 2850

	intel_dp_i2c_init(intel_dp, intel_connector, name);

2851
	/* Cache DPCD and EDID for edp. */
2852 2853
	if (is_edp(intel_dp)) {
		bool ret;
2854
		struct drm_display_mode *scan;
2855
		struct edid *edid;
2856 2857

		ironlake_edp_panel_vdd_on(intel_dp);
2858
		ret = intel_dp_get_dpcd(intel_dp);
2859
		ironlake_edp_panel_vdd_off(intel_dp, false);
2860

2861
		if (ret) {
2862 2863 2864
			if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
				dev_priv->no_aux_handshake =
					intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
J
Jesse Barnes 已提交
2865 2866
					DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
		} else {
2867
			/* if this fails, presume the device is a ghost */
2868
			DRM_INFO("failed to retrieve link info, disabling eDP\n");
2869 2870
			intel_dp_encoder_destroy(&intel_encoder->base);
			intel_dp_destroy(connector);
2871
			return;
J
Jesse Barnes 已提交
2872 2873
		}

2874 2875 2876 2877
		/* We now know it's not a ghost, init power sequence regs. */
		intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
							      &power_seq);

2878 2879 2880
		ironlake_edp_panel_vdd_on(intel_dp);
		edid = drm_get_edid(connector, &intel_dp->adapter);
		if (edid) {
2881 2882 2883 2884 2885 2886 2887 2888 2889
			if (drm_add_edid_modes(connector, edid)) {
				drm_mode_connector_update_edid_property(connector, edid);
				drm_edid_to_eld(connector, edid);
			} else {
				kfree(edid);
				edid = ERR_PTR(-EINVAL);
			}
		} else {
			edid = ERR_PTR(-ENOENT);
2890
		}
2891
		intel_connector->edid = edid;
2892 2893 2894 2895 2896 2897 2898

		/* prefer fixed mode from EDID if available */
		list_for_each_entry(scan, &connector->probed_modes, head) {
			if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
				fixed_mode = drm_mode_duplicate(dev, scan);
				break;
			}
2899
		}
2900 2901 2902 2903 2904 2905 2906 2907

		/* fallback to VBT if available for eDP */
		if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
			fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
			if (fixed_mode)
				fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
		}

2908 2909
		ironlake_edp_panel_vdd_off(intel_dp, false);
	}
2910

2911
	if (is_edp(intel_dp)) {
2912
		intel_panel_init(&intel_connector->panel, fixed_mode);
2913
		intel_panel_setup_backlight(connector);
2914 2915
	}

2916 2917
	intel_dp_add_properties(intel_dp, connector);

2918 2919 2920 2921 2922 2923 2924 2925 2926
	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
}
2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950

void
intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
{
	struct intel_digital_port *intel_dig_port;
	struct intel_encoder *intel_encoder;
	struct drm_encoder *encoder;
	struct intel_connector *intel_connector;

	intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
	if (!intel_dig_port)
		return;

	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
	if (!intel_connector) {
		kfree(intel_dig_port);
		return;
	}

	intel_encoder = &intel_dig_port->base;
	encoder = &intel_encoder->base;

	drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
			 DRM_MODE_ENCODER_TMDS);
P
Paulo Zanoni 已提交
2951
	drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2952

2953
	intel_encoder->compute_config = intel_dp_compute_config;
P
Paulo Zanoni 已提交
2954 2955 2956 2957 2958
	intel_encoder->enable = intel_enable_dp;
	intel_encoder->pre_enable = intel_pre_enable_dp;
	intel_encoder->disable = intel_disable_dp;
	intel_encoder->post_disable = intel_post_disable_dp;
	intel_encoder->get_hw_state = intel_dp_get_hw_state;
2959

2960
	intel_dig_port->port = port;
2961 2962
	intel_dig_port->dp.output_reg = output_reg;

P
Paulo Zanoni 已提交
2963
	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2964 2965 2966 2967 2968 2969
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
	intel_encoder->cloneable = false;
	intel_encoder->hot_plug = intel_dp_hot_plug;

	intel_dp_init_connector(intel_dig_port, intel_connector);
}