intel_dp.c 81.9 KB
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/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
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#include "intel_drv.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"

#define DP_LINK_CHECK_TIMEOUT	(10 * 1000)

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/**
 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 * @intel_dp: DP struct
 *
 * If a CPU or PCH DP output is attached to an eDP panel, this function
 * will return true, and false otherwise.
 */
static bool is_edp(struct intel_dp *intel_dp)
{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
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}

/**
 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
 * @intel_dp: DP struct
 *
 * Returns true if the given DP struct corresponds to a PCH DP port attached
 * to an eDP panel, false otherwise.  Helpful for determining whether we
 * may need FDI resources for a given DP output or not.
 */
static bool is_pch_edp(struct intel_dp *intel_dp)
{
	return intel_dp->is_pch_edp;
}

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/**
 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
 * @intel_dp: DP struct
 *
 * Returns true if the given DP struct corresponds to a CPU eDP port.
 */
static bool is_cpu_edp(struct intel_dp *intel_dp)
{
	return is_edp(intel_dp) && !is_pch_edp(intel_dp);
}

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static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
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{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.base.dev;
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}
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static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
{
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	return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
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}

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/**
 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
 * @encoder: DRM encoder
 *
 * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
 * by intel_display.c.
 */
bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
{
	struct intel_dp *intel_dp;

	if (!encoder)
		return false;

	intel_dp = enc_to_intel_dp(encoder);

	return is_pch_edp(intel_dp);
}

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static void intel_dp_link_down(struct intel_dp *intel_dp);
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void
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intel_edp_link_config(struct intel_encoder *intel_encoder,
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		       int *lane_num, int *link_bw)
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{
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	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
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	*lane_num = intel_dp->lane_count;
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	*link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
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}

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int
intel_edp_target_clock(struct intel_encoder *intel_encoder,
		       struct drm_display_mode *mode)
{
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	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
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	struct intel_connector *intel_connector = intel_dp->attached_connector;
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	if (intel_connector->panel.fixed_mode)
		return intel_connector->panel.fixed_mode->clock;
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	else
		return mode->clock;
}

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static int
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intel_dp_max_link_bw(struct intel_dp *intel_dp)
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{
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	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
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	switch (max_link_bw) {
	case DP_LINK_BW_1_62:
	case DP_LINK_BW_2_7:
		break;
	default:
		max_link_bw = DP_LINK_BW_1_62;
		break;
	}
	return max_link_bw;
}

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/*
 * The units on the numbers in the next two are... bizarre.  Examples will
 * make it clearer; this one parallels an example in the eDP spec.
 *
 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 *
 *     270000 * 1 * 8 / 10 == 216000
 *
 * The actual data capacity of that configuration is 2.16Gbit/s, so the
 * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 * 119000.  At 18bpp that's 2142000 kilobits per second.
 *
 * Thus the strange-looking division by 10 in intel_dp_link_required, to
 * get the result in decakilobits instead of kilobits.
 */

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static int
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intel_dp_link_required(int pixel_clock, int bpp)
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{
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	return (pixel_clock * bpp + 9) / 10;
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}

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static int
intel_dp_max_data_rate(int max_link_clock, int max_lanes)
{
	return (max_link_clock * max_lanes * 8) / 10;
}

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static bool
intel_dp_adjust_dithering(struct intel_dp *intel_dp,
			  struct drm_display_mode *mode,
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			  bool adjust_mode)
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{
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	int max_link_clock =
		drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
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	int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
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	int max_rate, mode_rate;

	mode_rate = intel_dp_link_required(mode->clock, 24);
	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);

	if (mode_rate > max_rate) {
		mode_rate = intel_dp_link_required(mode->clock, 18);
		if (mode_rate > max_rate)
			return false;

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		if (adjust_mode)
			mode->private_flags
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				|= INTEL_MODE_DP_FORCE_6BPC;

		return true;
	}

	return true;
}

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static int
intel_dp_mode_valid(struct drm_connector *connector,
		    struct drm_display_mode *mode)
{
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	struct intel_dp *intel_dp = intel_attached_dp(connector);
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	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
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	if (is_edp(intel_dp) && fixed_mode) {
		if (mode->hdisplay > fixed_mode->hdisplay)
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			return MODE_PANEL;

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		if (mode->vdisplay > fixed_mode->vdisplay)
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			return MODE_PANEL;
	}

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	if (!intel_dp_adjust_dithering(intel_dp, mode, false))
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		return MODE_CLOCK_HIGH;
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	if (mode->clock < 10000)
		return MODE_CLOCK_LOW;

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	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		return MODE_H_ILLEGAL;

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	return MODE_OK;
}

static uint32_t
pack_aux(uint8_t *src, int src_bytes)
{
	int	i;
	uint32_t v = 0;

	if (src_bytes > 4)
		src_bytes = 4;
	for (i = 0; i < src_bytes; i++)
		v |= ((uint32_t) src[i]) << ((3-i) * 8);
	return v;
}

static void
unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
{
	int i;
	if (dst_bytes > 4)
		dst_bytes = 4;
	for (i = 0; i < dst_bytes; i++)
		dst[i] = src >> ((3-i) * 8);
}

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/* hrawclock is 1/4 the FSB frequency */
static int
intel_hrawclk(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t clkcfg;

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	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
	if (IS_VALLEYVIEW(dev))
		return 200;

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	clkcfg = I915_READ(CLKCFG);
	switch (clkcfg & CLKCFG_FSB_MASK) {
	case CLKCFG_FSB_400:
		return 100;
	case CLKCFG_FSB_533:
		return 133;
	case CLKCFG_FSB_667:
		return 166;
	case CLKCFG_FSB_800:
		return 200;
	case CLKCFG_FSB_1067:
		return 266;
	case CLKCFG_FSB_1333:
		return 333;
	/* these two are just a guess; one of them might be right */
	case CLKCFG_FSB_1600:
	case CLKCFG_FSB_1600_ALT:
		return 400;
	default:
		return 133;
	}
}

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static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
{
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	struct drm_device *dev = intel_dp_to_dev(intel_dp);
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	struct drm_i915_private *dev_priv = dev->dev_private;

	return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
}

static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
{
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	struct drm_device *dev = intel_dp_to_dev(intel_dp);
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	struct drm_i915_private *dev_priv = dev->dev_private;

	return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
}

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static void
intel_dp_check_edp(struct intel_dp *intel_dp)
{
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	struct drm_device *dev = intel_dp_to_dev(intel_dp);
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	struct drm_i915_private *dev_priv = dev->dev_private;
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	if (!is_edp(intel_dp))
		return;
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	if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
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		WARN(1, "eDP powered off while attempting aux channel communication.\n");
		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
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			      I915_READ(PCH_PP_STATUS),
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			      I915_READ(PCH_PP_CONTROL));
	}
}

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static uint32_t
intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t ch_ctl = intel_dp->output_reg + 0x10;
	uint32_t status;
	bool done;

	if (IS_HASWELL(dev)) {
		switch (intel_dig_port->port) {
		case PORT_A:
			ch_ctl = DPA_AUX_CH_CTL;
			break;
		case PORT_B:
			ch_ctl = PCH_DPB_AUX_CH_CTL;
			break;
		case PORT_C:
			ch_ctl = PCH_DPC_AUX_CH_CTL;
			break;
		case PORT_D:
			ch_ctl = PCH_DPD_AUX_CH_CTL;
			break;
		default:
			BUG();
		}
	}

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#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
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	if (has_aux_irq)
		done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 10);
	else
		done = wait_for_atomic(C, 10) == 0;
	if (!done)
		DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
			  has_aux_irq);
#undef C

	return status;
}

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static int
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intel_dp_aux_ch(struct intel_dp *intel_dp,
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		uint8_t *send, int send_bytes,
		uint8_t *recv, int recv_size)
{
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	uint32_t output_reg = intel_dp->output_reg;
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
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	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t ch_ctl = output_reg + 0x10;
	uint32_t ch_data = ch_ctl + 4;
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	int i, ret, recv_bytes;
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	uint32_t status;
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	uint32_t aux_clock_divider;
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	int try, precharge;
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	bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);

	/* dp aux is extremely sensitive to irq latency, hence request the
	 * lowest possible wakeup latency and so prevent the cpu from going into
	 * deep sleep states.
	 */
	pm_qos_update_request(&dev_priv->pm_qos, 0);
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	if (IS_HASWELL(dev)) {
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		switch (intel_dig_port->port) {
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		case PORT_A:
			ch_ctl = DPA_AUX_CH_CTL;
			ch_data = DPA_AUX_CH_DATA1;
			break;
		case PORT_B:
			ch_ctl = PCH_DPB_AUX_CH_CTL;
			ch_data = PCH_DPB_AUX_CH_DATA1;
			break;
		case PORT_C:
			ch_ctl = PCH_DPC_AUX_CH_CTL;
			ch_data = PCH_DPC_AUX_CH_DATA1;
			break;
		case PORT_D:
			ch_ctl = PCH_DPD_AUX_CH_CTL;
			ch_data = PCH_DPD_AUX_CH_DATA1;
			break;
		default:
			BUG();
		}
	}

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	intel_dp_check_edp(intel_dp);
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	/* The clock divider is based off the hrawclk,
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	 * and would like to run at 2MHz. So, take the
	 * hrawclk value and divide by 2 and use that
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	 *
	 * Note that PCH attached eDP panels should use a 125MHz input
	 * clock divider.
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	 */
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	if (is_cpu_edp(intel_dp)) {
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		if (HAS_DDI(dev))
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			aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
		else if (IS_VALLEYVIEW(dev))
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			aux_clock_divider = 100;
		else if (IS_GEN6(dev) || IS_GEN7(dev))
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			aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
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		else
			aux_clock_divider = 225; /* eDP input clock at 450Mhz */
	} else if (HAS_PCH_SPLIT(dev))
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		aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
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	else
		aux_clock_divider = intel_hrawclk(dev) / 2;

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	if (IS_GEN6(dev))
		precharge = 3;
	else
		precharge = 5;

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	/* Try to wait for any previous AUX channel activity */
	for (try = 0; try < 3; try++) {
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		status = I915_READ_NOTRACE(ch_ctl);
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		if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
			break;
		msleep(1);
	}

	if (try == 3) {
		WARN(1, "dp_aux_ch not started status 0x%08x\n",
		     I915_READ(ch_ctl));
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		ret = -EBUSY;
		goto out;
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	}

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	/* Must try at least 3 times according to DP spec */
	for (try = 0; try < 5; try++) {
		/* Load the send data into the aux channel data registers */
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		for (i = 0; i < send_bytes; i += 4)
			I915_WRITE(ch_data + i,
				   pack_aux(send + i, send_bytes - i));
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		/* Send the command and wait for it to complete */
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		I915_WRITE(ch_ctl,
			   DP_AUX_CH_CTL_SEND_BUSY |
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			   (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
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			   DP_AUX_CH_CTL_TIME_OUT_400us |
			   (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
			   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
			   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
			   DP_AUX_CH_CTL_DONE |
			   DP_AUX_CH_CTL_TIME_OUT_ERROR |
			   DP_AUX_CH_CTL_RECEIVE_ERROR);
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		status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
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		/* Clear done status and any errors */
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		I915_WRITE(ch_ctl,
			   status |
			   DP_AUX_CH_CTL_DONE |
			   DP_AUX_CH_CTL_TIME_OUT_ERROR |
			   DP_AUX_CH_CTL_RECEIVE_ERROR);
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		if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
			      DP_AUX_CH_CTL_RECEIVE_ERROR))
			continue;
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		if (status & DP_AUX_CH_CTL_DONE)
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			break;
	}

	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
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		DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
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		ret = -EBUSY;
		goto out;
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	}

	/* Check for timeout or receive error.
	 * Timeouts occur when the sink is not connected
	 */
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	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
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		DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
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		ret = -EIO;
		goto out;
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	}
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	/* Timeouts occur when the device isn't connected, so they're
	 * "normal" -- don't fill the kernel log with these */
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	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
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		DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
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		ret = -ETIMEDOUT;
		goto out;
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	}

	/* Unload any bytes sent back from the other side */
	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
		      DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
	if (recv_bytes > recv_size)
		recv_bytes = recv_size;
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	for (i = 0; i < recv_bytes; i += 4)
		unpack_aux(I915_READ(ch_data + i),
			   recv + i, recv_bytes - i);
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	ret = recv_bytes;
out:
	pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);

	return ret;
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}

/* Write data to the aux channel in native mode */
static int
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intel_dp_aux_native_write(struct intel_dp *intel_dp,
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			  uint16_t address, uint8_t *send, int send_bytes)
{
	int ret;
	uint8_t	msg[20];
	int msg_bytes;
	uint8_t	ack;

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	intel_dp_check_edp(intel_dp);
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	if (send_bytes > 16)
		return -1;
	msg[0] = AUX_NATIVE_WRITE << 4;
	msg[1] = address >> 8;
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	msg[2] = address & 0xff;
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	msg[3] = send_bytes - 1;
	memcpy(&msg[4], send, send_bytes);
	msg_bytes = send_bytes + 4;
	for (;;) {
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		ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
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		if (ret < 0)
			return ret;
		if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
			break;
		else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
			udelay(100);
		else
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			return -EIO;
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	}
	return send_bytes;
}

/* Write a single byte to the aux channel in native mode */
static int
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intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
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			    uint16_t address, uint8_t byte)
{
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	return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
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}

/* read bytes from a native aux channel */
static int
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intel_dp_aux_native_read(struct intel_dp *intel_dp,
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			 uint16_t address, uint8_t *recv, int recv_bytes)
{
	uint8_t msg[4];
	int msg_bytes;
	uint8_t reply[20];
	int reply_bytes;
	uint8_t ack;
	int ret;

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	intel_dp_check_edp(intel_dp);
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	msg[0] = AUX_NATIVE_READ << 4;
	msg[1] = address >> 8;
	msg[2] = address & 0xff;
	msg[3] = recv_bytes - 1;

	msg_bytes = 4;
	reply_bytes = recv_bytes + 1;

	for (;;) {
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		ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
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				      reply, reply_bytes);
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		if (ret == 0)
			return -EPROTO;
		if (ret < 0)
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			return ret;
		ack = reply[0];
		if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
			memcpy(recv, reply + 1, ret - 1);
			return ret - 1;
		}
		else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
			udelay(100);
		else
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			return -EIO;
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	}
}

static int
612 613
intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
		    uint8_t write_byte, uint8_t *read_byte)
614
{
615
	struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
C
Chris Wilson 已提交
616 617 618
	struct intel_dp *intel_dp = container_of(adapter,
						struct intel_dp,
						adapter);
619 620 621
	uint16_t address = algo_data->address;
	uint8_t msg[5];
	uint8_t reply[2];
622
	unsigned retry;
623 624 625 626
	int msg_bytes;
	int reply_bytes;
	int ret;

627
	intel_dp_check_edp(intel_dp);
628 629 630 631 632 633 634 635
	/* Set up the command byte */
	if (mode & MODE_I2C_READ)
		msg[0] = AUX_I2C_READ << 4;
	else
		msg[0] = AUX_I2C_WRITE << 4;

	if (!(mode & MODE_I2C_STOP))
		msg[0] |= AUX_I2C_MOT << 4;
636

637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657
	msg[1] = address >> 8;
	msg[2] = address;

	switch (mode) {
	case MODE_I2C_WRITE:
		msg[3] = 0;
		msg[4] = write_byte;
		msg_bytes = 5;
		reply_bytes = 1;
		break;
	case MODE_I2C_READ:
		msg[3] = 0;
		msg_bytes = 4;
		reply_bytes = 2;
		break;
	default:
		msg_bytes = 3;
		reply_bytes = 1;
		break;
	}

658 659 660 661
	for (retry = 0; retry < 5; retry++) {
		ret = intel_dp_aux_ch(intel_dp,
				      msg, msg_bytes,
				      reply, reply_bytes);
662
		if (ret < 0) {
663
			DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
664 665
			return ret;
		}
666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684

		switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
		case AUX_NATIVE_REPLY_ACK:
			/* I2C-over-AUX Reply field is only valid
			 * when paired with AUX ACK.
			 */
			break;
		case AUX_NATIVE_REPLY_NACK:
			DRM_DEBUG_KMS("aux_ch native nack\n");
			return -EREMOTEIO;
		case AUX_NATIVE_REPLY_DEFER:
			udelay(100);
			continue;
		default:
			DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
				  reply[0]);
			return -EREMOTEIO;
		}

685 686 687 688 689 690 691
		switch (reply[0] & AUX_I2C_REPLY_MASK) {
		case AUX_I2C_REPLY_ACK:
			if (mode == MODE_I2C_READ) {
				*read_byte = reply[1];
			}
			return reply_bytes - 1;
		case AUX_I2C_REPLY_NACK:
692
			DRM_DEBUG_KMS("aux_i2c nack\n");
693 694
			return -EREMOTEIO;
		case AUX_I2C_REPLY_DEFER:
695
			DRM_DEBUG_KMS("aux_i2c defer\n");
696 697 698
			udelay(100);
			break;
		default:
699
			DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
700 701 702
			return -EREMOTEIO;
		}
	}
703 704 705

	DRM_ERROR("too many retries, giving up\n");
	return -EREMOTEIO;
706 707 708
}

static int
C
Chris Wilson 已提交
709
intel_dp_i2c_init(struct intel_dp *intel_dp,
710
		  struct intel_connector *intel_connector, const char *name)
711
{
712 713
	int	ret;

Z
Zhenyu Wang 已提交
714
	DRM_DEBUG_KMS("i2c_init %s\n", name);
C
Chris Wilson 已提交
715 716 717 718
	intel_dp->algo.running = false;
	intel_dp->algo.address = 0;
	intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;

719
	memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
C
Chris Wilson 已提交
720 721
	intel_dp->adapter.owner = THIS_MODULE;
	intel_dp->adapter.class = I2C_CLASS_DDC;
722
	strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
C
Chris Wilson 已提交
723 724 725 726
	intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
	intel_dp->adapter.algo_data = &intel_dp->algo;
	intel_dp->adapter.dev.parent = &intel_connector->base.kdev;

727 728
	ironlake_edp_panel_vdd_on(intel_dp);
	ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
729
	ironlake_edp_panel_vdd_off(intel_dp, false);
730
	return ret;
731 732
}

P
Paulo Zanoni 已提交
733
bool
734 735
intel_dp_mode_fixup(struct drm_encoder *encoder,
		    const struct drm_display_mode *mode,
736 737
		    struct drm_display_mode *adjusted_mode)
{
738
	struct drm_device *dev = encoder->dev;
C
Chris Wilson 已提交
739
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
740
	struct intel_connector *intel_connector = intel_dp->attached_connector;
741
	int lane_count, clock;
742
	int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
C
Chris Wilson 已提交
743
	int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
744
	int bpp, mode_rate;
745 746
	static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };

747 748 749
	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
		intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
				       adjusted_mode);
750 751
		intel_pch_panel_fitting(dev,
					intel_connector->panel.fitting_mode,
752
					mode, adjusted_mode);
753 754
	}

755
	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
756 757
		return false;

758 759
	DRM_DEBUG_KMS("DP link computation with max lane count %i "
		      "max bw %02x pixel clock %iKHz\n",
760
		      max_lane_count, bws[max_clock], adjusted_mode->clock);
761

762
	if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
763 764 765
		return false;

	bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
766

767 768 769 770 771 772 773 774 775 776 777 778
	if (intel_dp->color_range_auto) {
		/*
		 * See:
		 * CEA-861-E - 5.1 Default Encoding Parameters
		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
		 */
		if (bpp != 18 && drm_mode_cea_vic(adjusted_mode) > 1)
			intel_dp->color_range = DP_COLOR_RANGE_16_235;
		else
			intel_dp->color_range = 0;
	}

779 780 781
	if (intel_dp->color_range)
		adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE;

782
	mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
783

784 785
	for (clock = 0; clock <= max_clock; clock++) {
		for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
786 787 788 789
			int link_bw_clock =
				drm_dp_bw_code_to_link_rate(bws[clock]);
			int link_avail = intel_dp_max_data_rate(link_bw_clock,
								lane_count);
790

791
			if (mode_rate <= link_avail) {
C
Chris Wilson 已提交
792 793
				intel_dp->link_bw = bws[clock];
				intel_dp->lane_count = lane_count;
794
				adjusted_mode->clock = link_bw_clock;
795 796
				DRM_DEBUG_KMS("DP link bw %02x lane "
						"count %d clock %d bpp %d\n",
C
Chris Wilson 已提交
797
				       intel_dp->link_bw, intel_dp->lane_count,
798 799 800
				       adjusted_mode->clock, bpp);
				DRM_DEBUG_KMS("DP link bw required %i available %i\n",
					      mode_rate, link_avail);
801 802 803 804
				return true;
			}
		}
	}
805

806 807 808 809 810 811 812 813
	return false;
}

void
intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
		 struct drm_display_mode *adjusted_mode)
{
	struct drm_device *dev = crtc->dev;
814 815
	struct intel_encoder *intel_encoder;
	struct intel_dp *intel_dp;
816 817
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
818
	int lane_count = 4;
819
	struct intel_link_m_n m_n;
820
	int pipe = intel_crtc->pipe;
821
	enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
822 823

	/*
824
	 * Find the lane count in the intel_encoder private
825
	 */
826 827
	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		intel_dp = enc_to_intel_dp(&intel_encoder->base);
828

829 830
		if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
		    intel_encoder->type == INTEL_OUTPUT_EDP)
831
		{
C
Chris Wilson 已提交
832
			lane_count = intel_dp->lane_count;
833
			break;
834 835 836 837 838 839 840 841
		}
	}

	/*
	 * Compute the GMCH and Link ratios. The '3' here is
	 * the number of bytes_per_pixel post-LUT, which we always
	 * set up for 8-bits of R/G/B, or 3 bytes total.
	 */
842 843
	intel_link_compute_m_n(intel_crtc->bpp, lane_count,
			       mode->clock, adjusted_mode->clock, &m_n);
844

845
	if (IS_HASWELL(dev)) {
846 847 848 849 850
		I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
			   TU_SIZE(m_n.tu) | m_n.gmch_m);
		I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
		I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
		I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
851
	} else if (HAS_PCH_SPLIT(dev)) {
852
		I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
853 854 855
		I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
		I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
		I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
856 857 858 859 860
	} else if (IS_VALLEYVIEW(dev)) {
		I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
		I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
		I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
		I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
861
	} else {
862
		I915_WRITE(PIPE_GMCH_DATA_M(pipe),
863
			   TU_SIZE(m_n.tu) | m_n.gmch_m);
864 865 866
		I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
		I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
		I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
867 868 869
	}
}

870 871 872 873 874 875 876 877 878 879 880 881 882 883 884
void intel_dp_init_link_config(struct intel_dp *intel_dp)
{
	memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
	intel_dp->link_configuration[0] = intel_dp->link_bw;
	intel_dp->link_configuration[1] = intel_dp->lane_count;
	intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
	/*
	 * Check for DPCD version > 1.1 and enhanced framing support
	 */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
		intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
	}
}

885 886 887 888 889 890 891 892 893 894 895
static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
{
	struct drm_device *dev = crtc->dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
	dpa_ctl = I915_READ(DP_A);
	dpa_ctl &= ~DP_PLL_FREQ_MASK;

	if (clock < 200000) {
896 897 898 899
		/* For a long time we've carried around a ILK-DevA w/a for the
		 * 160MHz clock. If we're really unlucky, it's still required.
		 */
		DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
900 901 902 903
		dpa_ctl |= DP_PLL_FREQ_160MHZ;
	} else {
		dpa_ctl |= DP_PLL_FREQ_270MHZ;
	}
904

905 906 907 908 909 910
	I915_WRITE(DP_A, dpa_ctl);

	POSTING_READ(DP_A);
	udelay(500);
}

911 912 913 914
static void
intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
		  struct drm_display_mode *adjusted_mode)
{
915
	struct drm_device *dev = encoder->dev;
916
	struct drm_i915_private *dev_priv = dev->dev_private;
C
Chris Wilson 已提交
917
	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
918
	struct drm_crtc *crtc = encoder->crtc;
919 920
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

921
	/*
K
Keith Packard 已提交
922
	 * There are four kinds of DP registers:
923 924
	 *
	 * 	IBX PCH
K
Keith Packard 已提交
925 926
	 * 	SNB CPU
	 *	IVB CPU
927 928 929 930 931 932 933 934 935 936
	 * 	CPT PCH
	 *
	 * IBX PCH and CPU are the same for almost everything,
	 * except that the CPU DP PLL is configured in this
	 * register
	 *
	 * CPT PCH is quite different, having many bits moved
	 * to the TRANS_DP_CTL register instead. That
	 * configuration happens (oddly) in ironlake_pch_enable
	 */
937

938 939 940 941
	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
942

943 944
	/* Handle DP bits in common between all three register formats */
	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
945

C
Chris Wilson 已提交
946
	switch (intel_dp->lane_count) {
947
	case 1:
C
Chris Wilson 已提交
948
		intel_dp->DP |= DP_PORT_WIDTH_1;
949 950
		break;
	case 2:
C
Chris Wilson 已提交
951
		intel_dp->DP |= DP_PORT_WIDTH_2;
952 953
		break;
	case 4:
C
Chris Wilson 已提交
954
		intel_dp->DP |= DP_PORT_WIDTH_4;
955 956
		break;
	}
957 958 959
	if (intel_dp->has_audio) {
		DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
				 pipe_name(intel_crtc->pipe));
C
Chris Wilson 已提交
960
		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
961 962
		intel_write_eld(encoder, adjusted_mode);
	}
963 964

	intel_dp_init_link_config(intel_dp);
965

966
	/* Split out the IBX/CPU vs CPT settings */
967

968
	if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
K
Keith Packard 已提交
969 970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985
		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

		if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
			intel_dp->DP |= DP_ENHANCED_FRAMING;

		intel_dp->DP |= intel_crtc->pipe << 29;

		/* don't miss out required setting for eDP */
		if (adjusted_mode->clock < 200000)
			intel_dp->DP |= DP_PLL_FREQ_160MHZ;
		else
			intel_dp->DP |= DP_PLL_FREQ_270MHZ;
	} else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
986 987
		if (!HAS_PCH_SPLIT(dev))
			intel_dp->DP |= intel_dp->color_range;
988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009

		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF;

		if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
			intel_dp->DP |= DP_ENHANCED_FRAMING;

		if (intel_crtc->pipe == 1)
			intel_dp->DP |= DP_PIPEB_SELECT;

		if (is_cpu_edp(intel_dp)) {
			/* don't miss out required setting for eDP */
			if (adjusted_mode->clock < 200000)
				intel_dp->DP |= DP_PLL_FREQ_160MHZ;
			else
				intel_dp->DP |= DP_PLL_FREQ_270MHZ;
		}
	} else {
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1010
	}
1011 1012 1013

	if (is_cpu_edp(intel_dp))
		ironlake_set_pll_edp(crtc, adjusted_mode->clock);
1014 1015
}

1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027
#define IDLE_ON_MASK		(PP_ON | 0 	  | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
#define IDLE_ON_VALUE   	(PP_ON | 0 	  | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)

#define IDLE_OFF_MASK		(PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
#define IDLE_OFF_VALUE		(0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)

#define IDLE_CYCLE_MASK		(PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
#define IDLE_CYCLE_VALUE	(0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)

static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
				       u32 mask,
				       u32 value)
1028
{
1029
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1030
	struct drm_i915_private *dev_priv = dev->dev_private;
1031

1032 1033 1034 1035
	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
		      mask, value,
		      I915_READ(PCH_PP_STATUS),
		      I915_READ(PCH_PP_CONTROL));
1036

1037 1038 1039 1040
	if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
		DRM_ERROR("Panel status timeout: status %08x control %08x\n",
			  I915_READ(PCH_PP_STATUS),
			  I915_READ(PCH_PP_CONTROL));
1041
	}
1042
}
1043

1044 1045 1046 1047
static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
{
	DRM_DEBUG_KMS("Wait for panel power on\n");
	ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1048 1049
}

1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062
static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
{
	DRM_DEBUG_KMS("Wait for panel power off time\n");
	ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
}

static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
{
	DRM_DEBUG_KMS("Wait for panel power cycle\n");
	ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
}


1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073
/* Read the current pp_control value, unlocking the register if it
 * is locked
 */

static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
{
	u32	control = I915_READ(PCH_PP_CONTROL);

	control &= ~PANEL_UNLOCK_MASK;
	control |= PANEL_UNLOCK_REGS;
	return control;
1074 1075
}

1076
void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1077
{
1078
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1079 1080 1081
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;

1082 1083
	if (!is_edp(intel_dp))
		return;
1084
	DRM_DEBUG_KMS("Turn eDP VDD on\n");
1085

1086 1087 1088 1089
	WARN(intel_dp->want_panel_vdd,
	     "eDP VDD already requested on\n");

	intel_dp->want_panel_vdd = true;
1090

1091 1092 1093 1094 1095
	if (ironlake_edp_have_panel_vdd(intel_dp)) {
		DRM_DEBUG_KMS("eDP VDD already on\n");
		return;
	}

1096 1097 1098
	if (!ironlake_edp_have_panel_power(intel_dp))
		ironlake_wait_panel_power_cycle(intel_dp);

1099
	pp = ironlake_get_pp_control(dev_priv);
1100 1101 1102
	pp |= EDP_FORCE_VDD;
	I915_WRITE(PCH_PP_CONTROL, pp);
	POSTING_READ(PCH_PP_CONTROL);
1103 1104
	DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
		      I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1105 1106 1107 1108 1109

	/*
	 * If the panel wasn't on, delay before accessing aux channel
	 */
	if (!ironlake_edp_have_panel_power(intel_dp)) {
1110
		DRM_DEBUG_KMS("eDP was not running\n");
1111 1112
		msleep(intel_dp->panel_power_up_delay);
	}
1113 1114
}

1115
static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1116
{
1117
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1118 1119 1120
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;

1121 1122
	WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));

1123
	if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1124
		pp = ironlake_get_pp_control(dev_priv);
1125 1126 1127 1128 1129 1130 1131
		pp &= ~EDP_FORCE_VDD;
		I915_WRITE(PCH_PP_CONTROL, pp);
		POSTING_READ(PCH_PP_CONTROL);

		/* Make sure sequencer is idle before allowing subsequent activity */
		DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
			      I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1132 1133

		msleep(intel_dp->panel_power_down_delay);
1134 1135
	}
}
1136

1137 1138 1139 1140
static void ironlake_panel_vdd_work(struct work_struct *__work)
{
	struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
						 struct intel_dp, panel_vdd_work);
1141
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1142

1143
	mutex_lock(&dev->mode_config.mutex);
1144
	ironlake_panel_vdd_off_sync(intel_dp);
1145
	mutex_unlock(&dev->mode_config.mutex);
1146 1147
}

1148
void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1149
{
1150 1151
	if (!is_edp(intel_dp))
		return;
1152

1153 1154
	DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
	WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1155

1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168
	intel_dp->want_panel_vdd = false;

	if (sync) {
		ironlake_panel_vdd_off_sync(intel_dp);
	} else {
		/*
		 * Queue the timer to fire a long
		 * time from now (relative to the power down delay)
		 * to keep the panel power up across a sequence of operations
		 */
		schedule_delayed_work(&intel_dp->panel_vdd_work,
				      msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
	}
1169 1170
}

1171
void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1172
{
1173
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1174
	struct drm_i915_private *dev_priv = dev->dev_private;
1175
	u32 pp;
1176

1177
	if (!is_edp(intel_dp))
1178
		return;
1179 1180 1181 1182 1183

	DRM_DEBUG_KMS("Turn eDP power on\n");

	if (ironlake_edp_have_panel_power(intel_dp)) {
		DRM_DEBUG_KMS("eDP power already on\n");
1184
		return;
1185
	}
1186

1187
	ironlake_wait_panel_power_cycle(intel_dp);
1188

1189
	pp = ironlake_get_pp_control(dev_priv);
1190 1191 1192 1193 1194 1195
	if (IS_GEN5(dev)) {
		/* ILK workaround: disable reset around power sequence */
		pp &= ~PANEL_POWER_RESET;
		I915_WRITE(PCH_PP_CONTROL, pp);
		POSTING_READ(PCH_PP_CONTROL);
	}
1196

1197
	pp |= POWER_TARGET_ON;
1198 1199 1200
	if (!IS_GEN5(dev))
		pp |= PANEL_POWER_RESET;

1201
	I915_WRITE(PCH_PP_CONTROL, pp);
1202
	POSTING_READ(PCH_PP_CONTROL);
1203

1204
	ironlake_wait_panel_on(intel_dp);
1205

1206 1207 1208 1209 1210
	if (IS_GEN5(dev)) {
		pp |= PANEL_POWER_RESET; /* restore panel reset bit */
		I915_WRITE(PCH_PP_CONTROL, pp);
		POSTING_READ(PCH_PP_CONTROL);
	}
1211 1212
}

1213
void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1214
{
1215
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1216
	struct drm_i915_private *dev_priv = dev->dev_private;
1217
	u32 pp;
1218

1219 1220
	if (!is_edp(intel_dp))
		return;
1221

1222
	DRM_DEBUG_KMS("Turn eDP power off\n");
1223

1224
	WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1225

1226
	pp = ironlake_get_pp_control(dev_priv);
1227 1228 1229
	/* We need to switch off panel power _and_ force vdd, for otherwise some
	 * panels get very unhappy and cease to work. */
	pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1230 1231
	I915_WRITE(PCH_PP_CONTROL, pp);
	POSTING_READ(PCH_PP_CONTROL);
1232

1233 1234
	intel_dp->want_panel_vdd = false;

1235
	ironlake_wait_panel_off(intel_dp);
1236 1237
}

1238
void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1239
{
1240 1241
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
1242
	struct drm_i915_private *dev_priv = dev->dev_private;
1243
	int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1244 1245
	u32 pp;

1246 1247 1248
	if (!is_edp(intel_dp))
		return;

1249
	DRM_DEBUG_KMS("\n");
1250 1251 1252 1253 1254 1255
	/*
	 * If we enable the backlight right away following a panel power
	 * on, we may see slight flicker as the panel syncs with the eDP
	 * link.  So delay a bit to make sure the image is solid before
	 * allowing it to appear.
	 */
1256
	msleep(intel_dp->backlight_on_delay);
1257
	pp = ironlake_get_pp_control(dev_priv);
1258 1259
	pp |= EDP_BLC_ENABLE;
	I915_WRITE(PCH_PP_CONTROL, pp);
1260
	POSTING_READ(PCH_PP_CONTROL);
1261 1262

	intel_panel_enable_backlight(dev, pipe);
1263 1264
}

1265
void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1266
{
1267
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1268 1269 1270
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;

1271 1272 1273
	if (!is_edp(intel_dp))
		return;

1274 1275
	intel_panel_disable_backlight(dev);

1276
	DRM_DEBUG_KMS("\n");
1277
	pp = ironlake_get_pp_control(dev_priv);
1278 1279
	pp &= ~EDP_BLC_ENABLE;
	I915_WRITE(PCH_PP_CONTROL, pp);
1280 1281
	POSTING_READ(PCH_PP_CONTROL);
	msleep(intel_dp->backlight_off_delay);
1282
}
1283

1284
static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1285
{
1286 1287 1288
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = crtc->dev;
1289 1290 1291
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

1292 1293 1294
	assert_pipe_disabled(dev_priv,
			     to_intel_crtc(crtc)->pipe);

1295 1296
	DRM_DEBUG_KMS("\n");
	dpa_ctl = I915_READ(DP_A);
1297 1298 1299 1300 1301 1302 1303 1304 1305
	WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");

	/* We don't adjust intel_dp->DP while tearing down the link, to
	 * facilitate link retraining (e.g. after hotplug). Hence clear all
	 * enable bits here to ensure that we don't enable too much. */
	intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
	intel_dp->DP |= DP_PLL_ENABLE;
	I915_WRITE(DP_A, intel_dp->DP);
1306 1307
	POSTING_READ(DP_A);
	udelay(200);
1308 1309
}

1310
static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1311
{
1312 1313 1314
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = crtc->dev;
1315 1316 1317
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

1318 1319 1320
	assert_pipe_disabled(dev_priv,
			     to_intel_crtc(crtc)->pipe);

1321
	dpa_ctl = I915_READ(DP_A);
1322 1323 1324 1325 1326 1327 1328
	WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
	     "dp pll off, should be on\n");
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");

	/* We can't rely on the value tracked for the DP register in
	 * intel_dp->DP because link_down must not change that (otherwise link
	 * re-training will fail. */
1329
	dpa_ctl &= ~DP_PLL_ENABLE;
1330
	I915_WRITE(DP_A, dpa_ctl);
1331
	POSTING_READ(DP_A);
1332 1333 1334
	udelay(200);
}

1335
/* If the sink supports it, try to set the power state appropriately */
1336
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364
{
	int ret, i;

	/* Should have a valid DPCD by this point */
	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
		return;

	if (mode != DRM_MODE_DPMS_ON) {
		ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
						  DP_SET_POWER_D3);
		if (ret != 1)
			DRM_DEBUG_DRIVER("failed to write sink power state\n");
	} else {
		/*
		 * When turning on, we need to retry for 1ms to give the sink
		 * time to wake up.
		 */
		for (i = 0; i < 3; i++) {
			ret = intel_dp_aux_native_write_1(intel_dp,
							  DP_SET_POWER,
							  DP_SET_POWER_D0);
			if (ret == 1)
				break;
			msleep(1);
		}
	}
}

1365 1366
static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
				  enum pipe *pipe)
1367
{
1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 tmp = I915_READ(intel_dp->output_reg);

	if (!(tmp & DP_PORT_EN))
		return false;

	if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
		*pipe = PORT_TO_PIPE_CPT(tmp);
	} else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
		*pipe = PORT_TO_PIPE(tmp);
	} else {
		u32 trans_sel;
		u32 trans_dp;
		int i;

		switch (intel_dp->output_reg) {
		case PCH_DP_B:
			trans_sel = TRANS_DP_PORT_SEL_B;
			break;
		case PCH_DP_C:
			trans_sel = TRANS_DP_PORT_SEL_C;
			break;
		case PCH_DP_D:
			trans_sel = TRANS_DP_PORT_SEL_D;
			break;
		default:
			return true;
		}

		for_each_pipe(i) {
			trans_dp = I915_READ(TRANS_DP_CTL(i));
			if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
				*pipe = i;
				return true;
			}
		}

1407 1408 1409
		DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
			      intel_dp->output_reg);
	}
1410

1411 1412
	return true;
}
1413

1414
static void intel_disable_dp(struct intel_encoder *encoder)
1415
{
1416
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1417 1418 1419 1420

	/* Make sure the panel is off before trying to change the mode. But also
	 * ensure that we have vdd while we switch off the panel. */
	ironlake_edp_panel_vdd_on(intel_dp);
1421
	ironlake_edp_backlight_off(intel_dp);
1422
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1423
	ironlake_edp_panel_off(intel_dp);
1424 1425 1426 1427

	/* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
	if (!is_cpu_edp(intel_dp))
		intel_dp_link_down(intel_dp);
1428 1429
}

1430
static void intel_post_disable_dp(struct intel_encoder *encoder)
1431
{
1432 1433
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

1434 1435
	if (is_cpu_edp(intel_dp)) {
		intel_dp_link_down(intel_dp);
1436
		ironlake_edp_pll_off(intel_dp);
1437
	}
1438 1439
}

1440
static void intel_enable_dp(struct intel_encoder *encoder)
1441
{
1442 1443 1444 1445
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1446

1447 1448
	if (WARN_ON(dp_reg & DP_PORT_EN))
		return;
1449

1450
	ironlake_edp_panel_vdd_on(intel_dp);
1451
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1452
	intel_dp_start_link_train(intel_dp);
1453
	ironlake_edp_panel_on(intel_dp);
1454
	ironlake_edp_panel_vdd_off(intel_dp, true);
1455
	intel_dp_complete_link_train(intel_dp);
1456
	ironlake_edp_backlight_on(intel_dp);
1457 1458
}

1459
static void intel_pre_enable_dp(struct intel_encoder *encoder)
1460
{
1461
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1462

1463 1464
	if (is_cpu_edp(intel_dp))
		ironlake_edp_pll_on(intel_dp);
1465 1466 1467
}

/*
1468 1469
 * Native read with retry for link status and receiver capability reads for
 * cases where the sink may still be asleep.
1470 1471
 */
static bool
1472 1473
intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
			       uint8_t *recv, int recv_bytes)
1474
{
1475 1476
	int ret, i;

1477 1478 1479 1480
	/*
	 * Sinks are *supposed* to come up within 1ms from an off state,
	 * but we're also supposed to retry 3 times per the spec.
	 */
1481
	for (i = 0; i < 3; i++) {
1482 1483 1484
		ret = intel_dp_aux_native_read(intel_dp, address, recv,
					       recv_bytes);
		if (ret == recv_bytes)
1485 1486 1487
			return true;
		msleep(1);
	}
1488

1489
	return false;
1490 1491 1492 1493 1494 1495 1496
}

/*
 * Fetch AUX CH registers 0x202 - 0x207 which contain
 * link status information
 */
static bool
1497
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1498
{
1499 1500
	return intel_dp_aux_native_read_retry(intel_dp,
					      DP_LANE0_1_STATUS,
1501
					      link_status,
1502
					      DP_LINK_STATUS_SIZE);
1503 1504 1505 1506 1507 1508 1509 1510 1511 1512 1513 1514 1515 1516 1517 1518 1519 1520 1521 1522
}

#if 0
static char	*voltage_names[] = {
	"0.4V", "0.6V", "0.8V", "1.2V"
};
static char	*pre_emph_names[] = {
	"0dB", "3.5dB", "6dB", "9.5dB"
};
static char	*link_train_names[] = {
	"pattern 1", "pattern 2", "idle", "off"
};
#endif

/*
 * These are source-specific values; current Intel hardware supports
 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
 */

static uint8_t
K
Keith Packard 已提交
1523
intel_dp_voltage_max(struct intel_dp *intel_dp)
1524
{
1525
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
K
Keith Packard 已提交
1526 1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537

	if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
		return DP_TRAIN_VOLTAGE_SWING_800;
	else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
		return DP_TRAIN_VOLTAGE_SWING_1200;
	else
		return DP_TRAIN_VOLTAGE_SWING_800;
}

static uint8_t
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
{
1538
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
K
Keith Packard 已提交
1539

1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552
	if (IS_HASWELL(dev)) {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_9_5;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
	} else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
K
Keith Packard 已提交
1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_600:
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
	} else {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_400:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_600:
			return DP_TRAIN_PRE_EMPHASIS_6;
		case DP_TRAIN_VOLTAGE_SWING_800:
			return DP_TRAIN_PRE_EMPHASIS_3_5;
		case DP_TRAIN_VOLTAGE_SWING_1200:
		default:
			return DP_TRAIN_PRE_EMPHASIS_0;
		}
1574 1575 1576 1577
	}
}

static void
1578
intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1579 1580 1581 1582
{
	uint8_t v = 0;
	uint8_t p = 0;
	int lane;
K
Keith Packard 已提交
1583 1584
	uint8_t voltage_max;
	uint8_t preemph_max;
1585

1586
	for (lane = 0; lane < intel_dp->lane_count; lane++) {
1587 1588
		uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
		uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1589 1590 1591 1592 1593 1594 1595

		if (this_v > v)
			v = this_v;
		if (this_p > p)
			p = this_p;
	}

K
Keith Packard 已提交
1596
	voltage_max = intel_dp_voltage_max(intel_dp);
1597 1598
	if (v >= voltage_max)
		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1599

K
Keith Packard 已提交
1600 1601 1602
	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
	if (p >= preemph_max)
		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1603 1604

	for (lane = 0; lane < 4; lane++)
1605
		intel_dp->train_set[lane] = v | p;
1606 1607 1608
}

static uint32_t
1609
intel_gen4_signal_levels(uint8_t train_set)
1610
{
1611
	uint32_t	signal_levels = 0;
1612

1613
	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1614 1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627
	case DP_TRAIN_VOLTAGE_SWING_400:
	default:
		signal_levels |= DP_VOLTAGE_0_4;
		break;
	case DP_TRAIN_VOLTAGE_SWING_600:
		signal_levels |= DP_VOLTAGE_0_6;
		break;
	case DP_TRAIN_VOLTAGE_SWING_800:
		signal_levels |= DP_VOLTAGE_0_8;
		break;
	case DP_TRAIN_VOLTAGE_SWING_1200:
		signal_levels |= DP_VOLTAGE_1_2;
		break;
	}
1628
	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645
	case DP_TRAIN_PRE_EMPHASIS_0:
	default:
		signal_levels |= DP_PRE_EMPHASIS_0;
		break;
	case DP_TRAIN_PRE_EMPHASIS_3_5:
		signal_levels |= DP_PRE_EMPHASIS_3_5;
		break;
	case DP_TRAIN_PRE_EMPHASIS_6:
		signal_levels |= DP_PRE_EMPHASIS_6;
		break;
	case DP_TRAIN_PRE_EMPHASIS_9_5:
		signal_levels |= DP_PRE_EMPHASIS_9_5;
		break;
	}
	return signal_levels;
}

1646 1647 1648 1649
/* Gen6's DP voltage swing and pre-emphasis control */
static uint32_t
intel_gen6_edp_signal_levels(uint8_t train_set)
{
1650 1651 1652
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
1653
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1654 1655 1656 1657
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1658
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1659 1660
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
		return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1661
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1662 1663
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1664
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1665 1666
	case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1667
	default:
1668 1669 1670
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1671 1672 1673
	}
}

K
Keith Packard 已提交
1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704
/* Gen7's DP voltage swing and pre-emphasis control */
static uint32_t
intel_gen7_edp_signal_levels(uint8_t train_set)
{
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_400MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
		return EDP_LINK_TRAIN_400MV_6DB_IVB;

	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_600MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_600MV_3_5DB_IVB;

	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
		return EDP_LINK_TRAIN_800MV_0DB_IVB;
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return EDP_LINK_TRAIN_800MV_3_5DB_IVB;

	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_500MV_0DB_IVB;
	}
}

1705 1706
/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
static uint32_t
1707
intel_hsw_signal_levels(uint8_t train_set)
1708
{
1709 1710 1711 1712 1713 1714 1715 1716 1717 1718 1719
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_400MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_400MV_3_5DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
		return DDI_BUF_EMP_400MV_6DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
		return DDI_BUF_EMP_400MV_9_5DB_HSW;
1720

1721 1722 1723 1724 1725 1726
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_600MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_600MV_3_5DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
		return DDI_BUF_EMP_600MV_6DB_HSW;
1727

1728 1729 1730 1731 1732 1733 1734 1735
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
		return DDI_BUF_EMP_800MV_0DB_HSW;
	case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
		return DDI_BUF_EMP_800MV_3_5DB_HSW;
	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return DDI_BUF_EMP_400MV_0DB_HSW;
1736 1737 1738
	}
}

1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763 1764 1765 1766
/* Properly updates "DP" with the correct signal levels. */
static void
intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	uint32_t signal_levels, mask;
	uint8_t train_set = intel_dp->train_set[0];

	if (IS_HASWELL(dev)) {
		signal_levels = intel_hsw_signal_levels(train_set);
		mask = DDI_BUF_EMP_MASK;
	} else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
		signal_levels = intel_gen7_edp_signal_levels(train_set);
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
	} else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
		signal_levels = intel_gen6_edp_signal_levels(train_set);
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
	} else {
		signal_levels = intel_gen4_signal_levels(train_set);
		mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
	}

	DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);

	*DP = (*DP & ~mask) | signal_levels;
}

1767
static bool
C
Chris Wilson 已提交
1768
intel_dp_set_link_train(struct intel_dp *intel_dp,
1769
			uint32_t dp_reg_value,
1770
			uint8_t dp_train_pat)
1771
{
1772 1773
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
1774
	struct drm_i915_private *dev_priv = dev->dev_private;
1775
	enum port port = intel_dig_port->port;
1776
	int ret;
1777
	uint32_t temp;
1778

1779
	if (IS_HASWELL(dev)) {
1780
		temp = I915_READ(DP_TP_CTL(port));
1781 1782 1783 1784 1785 1786 1787 1788 1789 1790

		if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
			temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
		else
			temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;

		temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:

1791 1792 1793 1794 1795 1796 1797 1798 1799 1800
			if (port != PORT_A) {
				temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
				I915_WRITE(DP_TP_CTL(port), temp);

				if (wait_for((I915_READ(DP_TP_STATUS(port)) &
					      DP_TP_STATUS_IDLE_DONE), 1))
					DRM_ERROR("Timed out waiting for DP idle patterns\n");

				temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
			}
1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814

			temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;

			break;
		case DP_TRAINING_PATTERN_1:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
			break;
		case DP_TRAINING_PATTERN_2:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
			break;
		case DP_TRAINING_PATTERN_3:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
			break;
		}
1815
		I915_WRITE(DP_TP_CTL(port), temp);
1816 1817 1818

	} else if (HAS_PCH_CPT(dev) &&
		   (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856
		dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
			break;
		case DP_TRAINING_PATTERN_1:
			dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
			break;
		case DP_TRAINING_PATTERN_2:
			dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
			break;
		case DP_TRAINING_PATTERN_3:
			DRM_ERROR("DP training pattern 3 not supported\n");
			dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
			break;
		}

	} else {
		dp_reg_value &= ~DP_LINK_TRAIN_MASK;

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			dp_reg_value |= DP_LINK_TRAIN_OFF;
			break;
		case DP_TRAINING_PATTERN_1:
			dp_reg_value |= DP_LINK_TRAIN_PAT_1;
			break;
		case DP_TRAINING_PATTERN_2:
			dp_reg_value |= DP_LINK_TRAIN_PAT_2;
			break;
		case DP_TRAINING_PATTERN_3:
			DRM_ERROR("DP training pattern 3 not supported\n");
			dp_reg_value |= DP_LINK_TRAIN_PAT_2;
			break;
		}
	}

C
Chris Wilson 已提交
1857 1858
	I915_WRITE(intel_dp->output_reg, dp_reg_value);
	POSTING_READ(intel_dp->output_reg);
1859

C
Chris Wilson 已提交
1860
	intel_dp_aux_native_write_1(intel_dp,
1861 1862 1863
				    DP_TRAINING_PATTERN_SET,
				    dp_train_pat);

1864 1865 1866 1867 1868 1869 1870 1871 1872
	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
	    DP_TRAINING_PATTERN_DISABLE) {
		ret = intel_dp_aux_native_write(intel_dp,
						DP_TRAINING_LANE0_SET,
						intel_dp->train_set,
						intel_dp->lane_count);
		if (ret != intel_dp->lane_count)
			return false;
	}
1873 1874 1875 1876

	return true;
}

1877
/* Enable corresponding port and start training pattern 1 */
1878
void
1879
intel_dp_start_link_train(struct intel_dp *intel_dp)
1880
{
1881
	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
1882
	struct drm_device *dev = encoder->dev;
1883 1884 1885
	int i;
	uint8_t voltage;
	bool clock_recovery = false;
1886
	int voltage_tries, loop_tries;
C
Chris Wilson 已提交
1887
	uint32_t DP = intel_dp->DP;
1888

P
Paulo Zanoni 已提交
1889
	if (HAS_DDI(dev))
1890 1891
		intel_ddi_prepare_link_retrain(encoder);

1892 1893 1894 1895
	/* Write the link configuration data */
	intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
				  intel_dp->link_configuration,
				  DP_LINK_CONFIGURATION_SIZE);
1896 1897

	DP |= DP_PORT_EN;
K
Keith Packard 已提交
1898

1899
	memset(intel_dp->train_set, 0, 4);
1900
	voltage = 0xff;
1901 1902
	voltage_tries = 0;
	loop_tries = 0;
1903 1904
	clock_recovery = false;
	for (;;) {
1905
		/* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1906
		uint8_t	    link_status[DP_LINK_STATUS_SIZE];
1907 1908

		intel_dp_set_signal_levels(intel_dp, &DP);
1909

1910
		/* Set training pattern 1 */
1911
		if (!intel_dp_set_link_train(intel_dp, DP,
1912 1913
					     DP_TRAINING_PATTERN_1 |
					     DP_LINK_SCRAMBLING_DISABLE))
1914 1915
			break;

1916
		drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
1917 1918
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
1919
			break;
1920
		}
1921

1922
		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1923
			DRM_DEBUG_KMS("clock recovery OK\n");
1924 1925 1926 1927 1928 1929 1930
			clock_recovery = true;
			break;
		}

		/* Check to see if we've tried the max voltage */
		for (i = 0; i < intel_dp->lane_count; i++)
			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1931
				break;
1932
		if (i == intel_dp->lane_count && voltage_tries == 5) {
1933 1934
			++loop_tries;
			if (loop_tries == 5) {
1935 1936 1937 1938 1939 1940 1941
				DRM_DEBUG_KMS("too many full retries, give up\n");
				break;
			}
			memset(intel_dp->train_set, 0, 4);
			voltage_tries = 0;
			continue;
		}
1942

1943
		/* Check to see if we've tried the same voltage 5 times */
1944
		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1945
			++voltage_tries;
1946 1947 1948 1949 1950 1951 1952
			if (voltage_tries == 5) {
				DRM_DEBUG_KMS("too many voltage retries, give up\n");
				break;
			}
		} else
			voltage_tries = 0;
		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1953

1954
		/* Compute new intel_dp->train_set as requested by target */
1955
		intel_get_adjust_train(intel_dp, link_status);
1956 1957
	}

1958 1959 1960
	intel_dp->DP = DP;
}

1961
void
1962 1963 1964
intel_dp_complete_link_train(struct intel_dp *intel_dp)
{
	bool channel_eq = false;
1965
	int tries, cr_tries;
1966 1967
	uint32_t DP = intel_dp->DP;

1968 1969
	/* channel equalization */
	tries = 0;
1970
	cr_tries = 0;
1971 1972
	channel_eq = false;
	for (;;) {
1973
		uint8_t	    link_status[DP_LINK_STATUS_SIZE];
1974

1975 1976 1977 1978 1979 1980
		if (cr_tries > 5) {
			DRM_ERROR("failed to train DP, aborting\n");
			intel_dp_link_down(intel_dp);
			break;
		}

1981
		intel_dp_set_signal_levels(intel_dp, &DP);
1982

1983
		/* channel eq pattern */
1984
		if (!intel_dp_set_link_train(intel_dp, DP,
1985 1986
					     DP_TRAINING_PATTERN_2 |
					     DP_LINK_SCRAMBLING_DISABLE))
1987 1988
			break;

1989
		drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
1990
		if (!intel_dp_get_link_status(intel_dp, link_status))
1991 1992
			break;

1993
		/* Make sure clock is still ok */
1994
		if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1995 1996 1997 1998 1999
			intel_dp_start_link_train(intel_dp);
			cr_tries++;
			continue;
		}

2000
		if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2001 2002 2003
			channel_eq = true;
			break;
		}
2004

2005 2006 2007 2008 2009 2010 2011 2012
		/* Try 5 times, then try clock recovery if that fails */
		if (tries > 5) {
			intel_dp_link_down(intel_dp);
			intel_dp_start_link_train(intel_dp);
			tries = 0;
			cr_tries++;
			continue;
		}
2013

2014
		/* Compute new intel_dp->train_set as requested by target */
2015
		intel_get_adjust_train(intel_dp, link_status);
2016
		++tries;
2017
	}
2018

2019 2020 2021
	if (channel_eq)
		DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");

2022
	intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
2023 2024 2025
}

static void
C
Chris Wilson 已提交
2026
intel_dp_link_down(struct intel_dp *intel_dp)
2027
{
2028 2029
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
2030
	struct drm_i915_private *dev_priv = dev->dev_private;
2031 2032
	struct intel_crtc *intel_crtc =
		to_intel_crtc(intel_dig_port->base.base.crtc);
C
Chris Wilson 已提交
2033
	uint32_t DP = intel_dp->DP;
2034

2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049
	/*
	 * DDI code has a strict mode set sequence and we should try to respect
	 * it, otherwise we might hang the machine in many different ways. So we
	 * really should be disabling the port only on a complete crtc_disable
	 * sequence. This function is just called under two conditions on DDI
	 * code:
	 * - Link train failed while doing crtc_enable, and on this case we
	 *   really should respect the mode set sequence and wait for a
	 *   crtc_disable.
	 * - Someone turned the monitor off and intel_dp_check_link_status
	 *   called us. We don't need to disable the whole port on this case, so
	 *   when someone turns the monitor on again,
	 *   intel_ddi_prepare_link_retrain will take care of redoing the link
	 *   train.
	 */
P
Paulo Zanoni 已提交
2050
	if (HAS_DDI(dev))
2051 2052
		return;

2053
	if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2054 2055
		return;

2056
	DRM_DEBUG_KMS("\n");
2057

K
Keith Packard 已提交
2058
	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
2059
		DP &= ~DP_LINK_TRAIN_MASK_CPT;
C
Chris Wilson 已提交
2060
		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2061 2062
	} else {
		DP &= ~DP_LINK_TRAIN_MASK;
C
Chris Wilson 已提交
2063
		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2064
	}
2065
	POSTING_READ(intel_dp->output_reg);
2066

2067 2068
	/* We don't really know why we're doing this */
	intel_wait_for_vblank(dev, intel_crtc->pipe);
2069

2070
	if (HAS_PCH_IBX(dev) &&
2071
	    I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2072
		struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2073

2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087
		/* Hardware workaround: leaving our transcoder select
		 * set to transcoder B while it's off will prevent the
		 * corresponding HDMI output on transcoder A.
		 *
		 * Combine this with another hardware workaround:
		 * transcoder select bit can only be cleared while the
		 * port is enabled.
		 */
		DP &= ~DP_PIPEB_SELECT;
		I915_WRITE(intel_dp->output_reg, DP);

		/* Changes to enable or select take place the vblank
		 * after being written.
		 */
2088 2089 2090 2091
		if (WARN_ON(crtc == NULL)) {
			/* We should never try to disable a port without a crtc
			 * attached. For paranoia keep the code around for a
			 * bit. */
2092 2093 2094
			POSTING_READ(intel_dp->output_reg);
			msleep(50);
		} else
2095
			intel_wait_for_vblank(dev, intel_crtc->pipe);
2096 2097
	}

2098
	DP &= ~DP_AUDIO_OUTPUT_ENABLE;
C
Chris Wilson 已提交
2099 2100
	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);
2101
	msleep(intel_dp->panel_power_down_delay);
2102 2103
}

2104 2105
static bool
intel_dp_get_dpcd(struct intel_dp *intel_dp)
2106
{
2107 2108
	char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];

2109
	if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2110 2111
					   sizeof(intel_dp->dpcd)) == 0)
		return false; /* aux transfer failed */
2112

2113 2114 2115 2116
	hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
			   32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
	DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);

2117 2118 2119 2120 2121 2122 2123 2124 2125 2126 2127 2128 2129 2130 2131 2132
	if (intel_dp->dpcd[DP_DPCD_REV] == 0)
		return false; /* DPCD not present */

	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
	      DP_DWN_STRM_PORT_PRESENT))
		return true; /* native DP sink */

	if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
		return true; /* no per-port downstream info */

	if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
					   intel_dp->downstream_ports,
					   DP_MAX_DOWNSTREAM_PORTS) == 0)
		return false; /* downstream port status fetch failed */

	return true;
2133 2134
}

2135 2136 2137 2138 2139 2140 2141 2142
static void
intel_dp_probe_oui(struct intel_dp *intel_dp)
{
	u8 buf[3];

	if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
		return;

D
Daniel Vetter 已提交
2143 2144
	ironlake_edp_panel_vdd_on(intel_dp);

2145 2146 2147 2148 2149 2150 2151
	if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
		DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);

	if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
		DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);
D
Daniel Vetter 已提交
2152 2153

	ironlake_edp_panel_vdd_off(intel_dp, false);
2154 2155
}

2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2172 2173
static bool
intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
	int ret;

	ret = intel_dp_aux_native_read_retry(intel_dp,
					     DP_DEVICE_SERVICE_IRQ_VECTOR,
					     sink_irq_vector, 1);
	if (!ret)
		return false;

	return true;
}

static void
intel_dp_handle_test_request(struct intel_dp *intel_dp)
{
	/* NAK by default */
2174
	intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2175 2176
}

2177 2178 2179 2180 2181 2182 2183 2184 2185
/*
 * According to DP spec
 * 5.1.2:
 *  1. Read DPCD
 *  2. Configure link according to Receiver Capabilities
 *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
 *  4. Check link status on receipt of hot-plug interrupt
 */

P
Paulo Zanoni 已提交
2186
void
C
Chris Wilson 已提交
2187
intel_dp_check_link_status(struct intel_dp *intel_dp)
2188
{
2189
	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2190
	u8 sink_irq_vector;
2191
	u8 link_status[DP_LINK_STATUS_SIZE];
2192

2193
	if (!intel_encoder->connectors_active)
2194
		return;
2195

2196
	if (WARN_ON(!intel_encoder->base.crtc))
2197 2198
		return;

2199
	/* Try to read receiver status if the link appears to be up */
2200
	if (!intel_dp_get_link_status(intel_dp, link_status)) {
C
Chris Wilson 已提交
2201
		intel_dp_link_down(intel_dp);
2202 2203 2204
		return;
	}

2205
	/* Now read the DPCD to see if it's actually running */
2206
	if (!intel_dp_get_dpcd(intel_dp)) {
2207 2208 2209 2210
		intel_dp_link_down(intel_dp);
		return;
	}

2211 2212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 2223 2224
	/* Try to read the source of the interrupt */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
		/* Clear interrupt source */
		intel_dp_aux_native_write_1(intel_dp,
					    DP_DEVICE_SERVICE_IRQ_VECTOR,
					    sink_irq_vector);

		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
			intel_dp_handle_test_request(intel_dp);
		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
	}

2225
	if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2226
		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2227
			      drm_get_encoder_name(&intel_encoder->base));
2228 2229 2230
		intel_dp_start_link_train(intel_dp);
		intel_dp_complete_link_train(intel_dp);
	}
2231 2232
}

2233
/* XXX this is probably wrong for multiple downstream ports */
2234
static enum drm_connector_status
2235
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2236
{
2237 2238 2239 2240 2241 2242 2243 2244 2245
	uint8_t *dpcd = intel_dp->dpcd;
	bool hpd;
	uint8_t type;

	if (!intel_dp_get_dpcd(intel_dp))
		return connector_status_disconnected;

	/* if there's no downstream port, we're done */
	if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2246
		return connector_status_connected;
2247 2248 2249 2250

	/* If we're HPD-aware, SINK_COUNT changes dynamically */
	hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
	if (hpd) {
2251
		uint8_t reg;
2252
		if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2253
						    &reg, 1))
2254
			return connector_status_unknown;
2255 2256
		return DP_GET_SINK_COUNT(reg) ? connector_status_connected
					      : connector_status_disconnected;
2257 2258 2259 2260
	}

	/* If no HPD, poke DDC gently */
	if (drm_probe_ddc(&intel_dp->adapter))
2261
		return connector_status_connected;
2262 2263 2264 2265 2266 2267 2268 2269

	/* Well we tried, say unknown for unreliable port types */
	type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
	if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
		return connector_status_unknown;

	/* Anything else is out of spec, warn and ignore */
	DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2270
	return connector_status_disconnected;
2271 2272
}

2273
static enum drm_connector_status
Z
Zhenyu Wang 已提交
2274
ironlake_dp_detect(struct intel_dp *intel_dp)
2275
{
2276
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2277 2278
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2279 2280
	enum drm_connector_status status;

2281 2282
	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp)) {
2283
		status = intel_panel_detect(dev);
2284 2285 2286 2287
		if (status == connector_status_unknown)
			status = connector_status_connected;
		return status;
	}
2288

2289 2290 2291
	if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
		return connector_status_disconnected;

2292
	return intel_dp_detect_dpcd(intel_dp);
2293 2294
}

2295
static enum drm_connector_status
Z
Zhenyu Wang 已提交
2296
g4x_dp_detect(struct intel_dp *intel_dp)
2297
{
2298
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2299
	struct drm_i915_private *dev_priv = dev->dev_private;
2300
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2301
	uint32_t bit;
2302

2303 2304
	switch (intel_dig_port->port) {
	case PORT_B:
2305
		bit = PORTB_HOTPLUG_LIVE_STATUS;
2306
		break;
2307
	case PORT_C:
2308
		bit = PORTC_HOTPLUG_LIVE_STATUS;
2309
		break;
2310
	case PORT_D:
2311
		bit = PORTD_HOTPLUG_LIVE_STATUS;
2312 2313 2314 2315 2316
		break;
	default:
		return connector_status_unknown;
	}

2317
	if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2318 2319
		return connector_status_disconnected;

2320
	return intel_dp_detect_dpcd(intel_dp);
Z
Zhenyu Wang 已提交
2321 2322
}

2323 2324 2325
static struct edid *
intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
{
2326
	struct intel_connector *intel_connector = to_intel_connector(connector);
2327

2328 2329 2330 2331 2332 2333 2334
	/* use cached edid if we have one */
	if (intel_connector->edid) {
		struct edid *edid;
		int size;

		/* invalid edid */
		if (IS_ERR(intel_connector->edid))
2335 2336
			return NULL;

2337
		size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2338 2339 2340 2341
		edid = kmalloc(size, GFP_KERNEL);
		if (!edid)
			return NULL;

2342
		memcpy(edid, intel_connector->edid, size);
2343 2344
		return edid;
	}
2345

2346
	return drm_get_edid(connector, adapter);
2347 2348 2349 2350 2351
}

static int
intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
{
2352
	struct intel_connector *intel_connector = to_intel_connector(connector);
2353

2354 2355 2356 2357 2358 2359 2360 2361
	/* use cached edid if we have one */
	if (intel_connector->edid) {
		/* invalid edid */
		if (IS_ERR(intel_connector->edid))
			return 0;

		return intel_connector_update_modes(connector,
						    intel_connector->edid);
2362 2363
	}

2364
	return intel_ddc_get_modes(connector, adapter);
2365 2366
}

Z
Zhenyu Wang 已提交
2367 2368 2369 2370
static enum drm_connector_status
intel_dp_detect(struct drm_connector *connector, bool force)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
2371 2372
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
2373
	struct drm_device *dev = connector->dev;
Z
Zhenyu Wang 已提交
2374 2375 2376 2377 2378 2379 2380 2381 2382
	enum drm_connector_status status;
	struct edid *edid = NULL;

	intel_dp->has_audio = false;

	if (HAS_PCH_SPLIT(dev))
		status = ironlake_dp_detect(intel_dp);
	else
		status = g4x_dp_detect(intel_dp);
2383

Z
Zhenyu Wang 已提交
2384 2385 2386
	if (status != connector_status_connected)
		return status;

2387 2388
	intel_dp_probe_oui(intel_dp);

2389 2390
	if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
		intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2391
	} else {
2392
		edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2393 2394 2395 2396
		if (edid) {
			intel_dp->has_audio = drm_detect_monitor_audio(edid);
			kfree(edid);
		}
Z
Zhenyu Wang 已提交
2397 2398
	}

2399 2400
	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
Z
Zhenyu Wang 已提交
2401
	return connector_status_connected;
2402 2403 2404 2405
}

static int intel_dp_get_modes(struct drm_connector *connector)
{
2406
	struct intel_dp *intel_dp = intel_attached_dp(connector);
2407
	struct intel_connector *intel_connector = to_intel_connector(connector);
2408
	struct drm_device *dev = connector->dev;
2409
	int ret;
2410 2411 2412 2413

	/* We should parse the EDID data and find out if it has an audio sink
	 */

2414
	ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2415
	if (ret)
2416 2417
		return ret;

2418
	/* if eDP has no EDID, fall back to fixed mode */
2419
	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2420
		struct drm_display_mode *mode;
2421 2422
		mode = drm_mode_duplicate(dev,
					  intel_connector->panel.fixed_mode);
2423
		if (mode) {
2424 2425 2426 2427 2428
			drm_mode_probed_add(connector, mode);
			return 1;
		}
	}
	return 0;
2429 2430
}

2431 2432 2433 2434 2435 2436 2437
static bool
intel_dp_detect_audio(struct drm_connector *connector)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
	struct edid *edid;
	bool has_audio = false;

2438
	edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2439 2440 2441 2442 2443 2444 2445 2446
	if (edid) {
		has_audio = drm_detect_monitor_audio(edid);
		kfree(edid);
	}

	return has_audio;
}

2447 2448 2449 2450 2451
static int
intel_dp_set_property(struct drm_connector *connector,
		      struct drm_property *property,
		      uint64_t val)
{
2452
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
2453
	struct intel_connector *intel_connector = to_intel_connector(connector);
2454 2455
	struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2456 2457
	int ret;

2458
	ret = drm_object_property_set_value(&connector->base, property, val);
2459 2460 2461
	if (ret)
		return ret;

2462
	if (property == dev_priv->force_audio_property) {
2463 2464 2465 2466
		int i = val;
		bool has_audio;

		if (i == intel_dp->force_audio)
2467 2468
			return 0;

2469
		intel_dp->force_audio = i;
2470

2471
		if (i == HDMI_AUDIO_AUTO)
2472 2473
			has_audio = intel_dp_detect_audio(connector);
		else
2474
			has_audio = (i == HDMI_AUDIO_ON);
2475 2476

		if (has_audio == intel_dp->has_audio)
2477 2478
			return 0;

2479
		intel_dp->has_audio = has_audio;
2480 2481 2482
		goto done;
	}

2483
	if (property == dev_priv->broadcast_rgb_property) {
2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498
		switch (val) {
		case INTEL_BROADCAST_RGB_AUTO:
			intel_dp->color_range_auto = true;
			break;
		case INTEL_BROADCAST_RGB_FULL:
			intel_dp->color_range_auto = false;
			intel_dp->color_range = 0;
			break;
		case INTEL_BROADCAST_RGB_LIMITED:
			intel_dp->color_range_auto = false;
			intel_dp->color_range = DP_COLOR_RANGE_16_235;
			break;
		default:
			return -EINVAL;
		}
2499 2500 2501
		goto done;
	}

2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517
	if (is_edp(intel_dp) &&
	    property == connector->dev->mode_config.scaling_mode_property) {
		if (val == DRM_MODE_SCALE_NONE) {
			DRM_DEBUG_KMS("no scaling not supported\n");
			return -EINVAL;
		}

		if (intel_connector->panel.fitting_mode == val) {
			/* the eDP scaling property is not changed */
			return 0;
		}
		intel_connector->panel.fitting_mode = val;

		goto done;
	}

2518 2519 2520
	return -EINVAL;

done:
2521 2522
	if (intel_encoder->base.crtc)
		intel_crtc_restore_mode(intel_encoder->base.crtc);
2523 2524 2525 2526

	return 0;
}

2527
static void
2528
intel_dp_destroy(struct drm_connector *connector)
2529
{
2530
	struct drm_device *dev = connector->dev;
2531
	struct intel_dp *intel_dp = intel_attached_dp(connector);
2532
	struct intel_connector *intel_connector = to_intel_connector(connector);
2533

2534 2535 2536
	if (!IS_ERR_OR_NULL(intel_connector->edid))
		kfree(intel_connector->edid);

2537
	if (is_edp(intel_dp)) {
2538
		intel_panel_destroy_backlight(dev);
2539 2540
		intel_panel_fini(&intel_connector->panel);
	}
2541

2542 2543
	drm_sysfs_connector_remove(connector);
	drm_connector_cleanup(connector);
2544
	kfree(connector);
2545 2546
}

P
Paulo Zanoni 已提交
2547
void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2548
{
2549 2550
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_dp *intel_dp = &intel_dig_port->dp;
2551 2552 2553

	i2c_del_adapter(&intel_dp->adapter);
	drm_encoder_cleanup(encoder);
2554 2555 2556 2557
	if (is_edp(intel_dp)) {
		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
		ironlake_panel_vdd_off_sync(intel_dp);
	}
2558
	kfree(intel_dig_port);
2559 2560
}

2561 2562 2563
static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
	.mode_fixup = intel_dp_mode_fixup,
	.mode_set = intel_dp_mode_set,
2564
	.disable = intel_encoder_noop,
2565 2566 2567
};

static const struct drm_connector_funcs intel_dp_connector_funcs = {
2568
	.dpms = intel_connector_dpms,
2569 2570
	.detect = intel_dp_detect,
	.fill_modes = drm_helper_probe_single_connector_modes,
2571
	.set_property = intel_dp_set_property,
2572 2573 2574 2575 2576 2577
	.destroy = intel_dp_destroy,
};

static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
	.get_modes = intel_dp_get_modes,
	.mode_valid = intel_dp_mode_valid,
2578
	.best_encoder = intel_best_encoder,
2579 2580 2581
};

static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2582
	.destroy = intel_dp_encoder_destroy,
2583 2584
};

2585
static void
2586
intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2587
{
2588
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2589

2590
	intel_dp_check_link_status(intel_dp);
2591
}
2592

2593 2594
/* Return which DP Port should be selected for Transcoder DP control */
int
2595
intel_trans_dp_port_sel(struct drm_crtc *crtc)
2596 2597
{
	struct drm_device *dev = crtc->dev;
2598 2599
	struct intel_encoder *intel_encoder;
	struct intel_dp *intel_dp;
2600

2601 2602
	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		intel_dp = enc_to_intel_dp(&intel_encoder->base);
2603

2604 2605
		if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
		    intel_encoder->type == INTEL_OUTPUT_EDP)
C
Chris Wilson 已提交
2606
			return intel_dp->output_reg;
2607
	}
C
Chris Wilson 已提交
2608

2609 2610 2611
	return -1;
}

2612
/* check the VBT to see whether the eDP is on DP-D port */
2613
bool intel_dpd_is_edp(struct drm_device *dev)
2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct child_device_config *p_child;
	int i;

	if (!dev_priv->child_dev_num)
		return false;

	for (i = 0; i < dev_priv->child_dev_num; i++) {
		p_child = dev_priv->child_dev + i;

		if (p_child->dvo_port == PORT_IDPD &&
		    p_child->device_type == DEVICE_TYPE_eDP)
			return true;
	}
	return false;
}

2632 2633 2634
static void
intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
{
2635 2636
	struct intel_connector *intel_connector = to_intel_connector(connector);

2637
	intel_attach_force_audio_property(connector);
2638
	intel_attach_broadcast_rgb_property(connector);
2639
	intel_dp->color_range_auto = true;
2640 2641 2642

	if (is_edp(intel_dp)) {
		drm_mode_create_scaling_mode_property(connector->dev);
2643 2644
		drm_object_attach_property(
			&connector->base,
2645
			connector->dev->mode_config.scaling_mode_property,
2646 2647
			DRM_MODE_SCALE_ASPECT);
		intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2648
	}
2649 2650
}

2651 2652
static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2653 2654
				    struct intel_dp *intel_dp,
				    struct edp_power_seq *out)
2655 2656 2657 2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct edp_power_seq cur, vbt, spec, final;
	u32 pp_on, pp_off, pp_div, pp;

	/* Workaround: Need to write PP_CONTROL with the unlock key as
	 * the very first thing. */
	pp = ironlake_get_pp_control(dev_priv);
	I915_WRITE(PCH_PP_CONTROL, pp);

	pp_on = I915_READ(PCH_PP_ON_DELAYS);
	pp_off = I915_READ(PCH_PP_OFF_DELAYS);
	pp_div = I915_READ(PCH_PP_DIVISOR);

	/* Pull timing values out of registers */
	cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
		PANEL_POWER_UP_DELAY_SHIFT;

	cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
		PANEL_LIGHT_ON_DELAY_SHIFT;

	cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
		PANEL_LIGHT_OFF_DELAY_SHIFT;

	cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
		PANEL_POWER_DOWN_DELAY_SHIFT;

	cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
		       PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;

	DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);

	vbt = dev_priv->edp.pps;

	/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
	 * our hw here, which are all in 100usec. */
	spec.t1_t3 = 210 * 10;
	spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
	spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
	spec.t10 = 500 * 10;
	/* This one is special and actually in units of 100ms, but zero
	 * based in the hw (so we need to add 100 ms). But the sw vbt
	 * table multiplies it with 1000 to make it in units of 100usec,
	 * too. */
	spec.t11_t12 = (510 + 100) * 10;

	DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);

	/* Use the max of the register settings and vbt. If both are
	 * unset, fall back to the spec limits. */
#define assign_final(field)	final.field = (max(cur.field, vbt.field) == 0 ? \
				       spec.field : \
				       max(cur.field, vbt.field))
	assign_final(t1_t3);
	assign_final(t8);
	assign_final(t9);
	assign_final(t10);
	assign_final(t11_t12);
#undef assign_final

#define get_delay(field)	(DIV_ROUND_UP(final.field, 10))
	intel_dp->panel_power_up_delay = get_delay(t1_t3);
	intel_dp->backlight_on_delay = get_delay(t8);
	intel_dp->backlight_off_delay = get_delay(t9);
	intel_dp->panel_power_down_delay = get_delay(t10);
	intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
#undef get_delay

2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737 2738 2739 2740 2741 2742 2743
	DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
		      intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
		      intel_dp->panel_power_cycle_delay);

	DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
		      intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);

	if (out)
		*out = final;
}

static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
					      struct intel_dp *intel_dp,
					      struct edp_power_seq *seq)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp_on, pp_off, pp_div;

2744
	/* And finally store the new values in the power sequencer. */
2745 2746 2747 2748
	pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
		(seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
	pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2749 2750 2751 2752
	/* Compute the divisor for the pp clock, simply match the Bspec
	 * formula. */
	pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
			<< PP_REFERENCE_DIVIDER_SHIFT;
2753
	pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772
			<< PANEL_POWER_CYCLE_DELAY_SHIFT);

	/* Haswell doesn't have any port selection bits for the panel
	 * power sequencer any more. */
	if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
		if (is_cpu_edp(intel_dp))
			pp_on |= PANEL_POWER_PORT_DP_A;
		else
			pp_on |= PANEL_POWER_PORT_DP_D;
	}

	I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
	I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
	I915_WRITE(PCH_PP_DIVISOR, pp_div);

	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
		      I915_READ(PCH_PP_ON_DELAYS),
		      I915_READ(PCH_PP_OFF_DELAYS),
		      I915_READ(PCH_PP_DIVISOR));
2773 2774
}

2775
void
2776 2777
intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
			struct intel_connector *intel_connector)
2778
{
2779 2780 2781 2782
	struct drm_connector *connector = &intel_connector->base;
	struct intel_dp *intel_dp = &intel_dig_port->dp;
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
2783
	struct drm_i915_private *dev_priv = dev->dev_private;
2784
	struct drm_display_mode *fixed_mode = NULL;
2785
	struct edp_power_seq power_seq = { 0 };
2786
	enum port port = intel_dig_port->port;
2787
	const char *name = NULL;
2788
	int type;
2789

2790 2791
	/* Preserve the current hw state. */
	intel_dp->DP = I915_READ(intel_dp->output_reg);
2792
	intel_dp->attached_connector = intel_connector;
2793

2794
	if (HAS_PCH_SPLIT(dev) && port == PORT_D)
2795
		if (intel_dpd_is_edp(dev))
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Chris Wilson 已提交
2796
			intel_dp->is_pch_edp = true;
2797

2798 2799 2800 2801
	/*
	 * FIXME : We need to initialize built-in panels before external panels.
	 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
	 */
2802
	if (IS_VALLEYVIEW(dev) && port == PORT_C) {
2803 2804
		type = DRM_MODE_CONNECTOR_eDP;
		intel_encoder->type = INTEL_OUTPUT_EDP;
2805
	} else if (port == PORT_A || is_pch_edp(intel_dp)) {
2806 2807 2808
		type = DRM_MODE_CONNECTOR_eDP;
		intel_encoder->type = INTEL_OUTPUT_EDP;
	} else {
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Paulo Zanoni 已提交
2809 2810 2811 2812
		/* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
		 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
		 * rewrite it.
		 */
2813 2814 2815 2816
		type = DRM_MODE_CONNECTOR_DisplayPort;
	}

	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2817 2818
	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);

2819
	connector->polled = DRM_CONNECTOR_POLL_HPD;
2820 2821 2822
	connector->interlace_allowed = true;
	connector->doublescan_allowed = 0;

2823 2824
	INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
			  ironlake_panel_vdd_work);
2825

2826
	intel_connector_attach_encoder(intel_connector, intel_encoder);
2827 2828
	drm_sysfs_connector_add(connector);

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Paulo Zanoni 已提交
2829
	if (HAS_DDI(dev))
2830 2831 2832 2833
		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
	else
		intel_connector->get_hw_state = intel_connector_get_hw_state;

2834

2835
	/* Set up the DDC bus. */
2836 2837 2838 2839 2840
	switch (port) {
	case PORT_A:
		name = "DPDDC-A";
		break;
	case PORT_B:
2841
		dev_priv->hotplug_supported_mask |= PORTB_HOTPLUG_INT_STATUS;
2842 2843 2844
		name = "DPDDC-B";
		break;
	case PORT_C:
2845
		dev_priv->hotplug_supported_mask |= PORTC_HOTPLUG_INT_STATUS;
2846 2847 2848
		name = "DPDDC-C";
		break;
	case PORT_D:
2849
		dev_priv->hotplug_supported_mask |= PORTD_HOTPLUG_INT_STATUS;
2850 2851 2852 2853 2854
		name = "DPDDC-D";
		break;
	default:
		WARN(1, "Invalid port %c\n", port_name(port));
		break;
2855 2856
	}

2857
	if (is_edp(intel_dp))
2858
		intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2859 2860 2861

	intel_dp_i2c_init(intel_dp, intel_connector, name);

2862
	/* Cache DPCD and EDID for edp. */
2863 2864
	if (is_edp(intel_dp)) {
		bool ret;
2865
		struct drm_display_mode *scan;
2866
		struct edid *edid;
2867 2868

		ironlake_edp_panel_vdd_on(intel_dp);
2869
		ret = intel_dp_get_dpcd(intel_dp);
2870
		ironlake_edp_panel_vdd_off(intel_dp, false);
2871

2872
		if (ret) {
2873 2874 2875
			if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
				dev_priv->no_aux_handshake =
					intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
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Jesse Barnes 已提交
2876 2877
					DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
		} else {
2878
			/* if this fails, presume the device is a ghost */
2879
			DRM_INFO("failed to retrieve link info, disabling eDP\n");
2880 2881
			intel_dp_encoder_destroy(&intel_encoder->base);
			intel_dp_destroy(connector);
2882
			return;
J
Jesse Barnes 已提交
2883 2884
		}

2885 2886 2887 2888
		/* We now know it's not a ghost, init power sequence regs. */
		intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
							      &power_seq);

2889 2890 2891
		ironlake_edp_panel_vdd_on(intel_dp);
		edid = drm_get_edid(connector, &intel_dp->adapter);
		if (edid) {
2892 2893 2894 2895 2896 2897 2898 2899 2900
			if (drm_add_edid_modes(connector, edid)) {
				drm_mode_connector_update_edid_property(connector, edid);
				drm_edid_to_eld(connector, edid);
			} else {
				kfree(edid);
				edid = ERR_PTR(-EINVAL);
			}
		} else {
			edid = ERR_PTR(-ENOENT);
2901
		}
2902
		intel_connector->edid = edid;
2903 2904 2905 2906 2907 2908 2909

		/* prefer fixed mode from EDID if available */
		list_for_each_entry(scan, &connector->probed_modes, head) {
			if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
				fixed_mode = drm_mode_duplicate(dev, scan);
				break;
			}
2910
		}
2911 2912 2913 2914 2915 2916 2917 2918

		/* fallback to VBT if available for eDP */
		if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
			fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
			if (fixed_mode)
				fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
		}

2919 2920
		ironlake_edp_panel_vdd_off(intel_dp, false);
	}
2921

2922
	if (is_edp(intel_dp)) {
2923
		intel_panel_init(&intel_connector->panel, fixed_mode);
2924
		intel_panel_setup_backlight(connector);
2925 2926
	}

2927 2928
	intel_dp_add_properties(intel_dp, connector);

2929 2930 2931 2932 2933 2934 2935 2936 2937
	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
}
2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961

void
intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
{
	struct intel_digital_port *intel_dig_port;
	struct intel_encoder *intel_encoder;
	struct drm_encoder *encoder;
	struct intel_connector *intel_connector;

	intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
	if (!intel_dig_port)
		return;

	intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
	if (!intel_connector) {
		kfree(intel_dig_port);
		return;
	}

	intel_encoder = &intel_dig_port->base;
	encoder = &intel_encoder->base;

	drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
			 DRM_MODE_ENCODER_TMDS);
P
Paulo Zanoni 已提交
2962
	drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2963

P
Paulo Zanoni 已提交
2964 2965 2966 2967 2968
	intel_encoder->enable = intel_enable_dp;
	intel_encoder->pre_enable = intel_pre_enable_dp;
	intel_encoder->disable = intel_disable_dp;
	intel_encoder->post_disable = intel_post_disable_dp;
	intel_encoder->get_hw_state = intel_dp_get_hw_state;
2969

2970
	intel_dig_port->port = port;
2971 2972
	intel_dig_port->dp.output_reg = output_reg;

P
Paulo Zanoni 已提交
2973
	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2974 2975 2976 2977 2978 2979
	intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
	intel_encoder->cloneable = false;
	intel_encoder->hot_plug = intel_dp_hot_plug;

	intel_dp_init_connector(intel_dig_port, intel_connector);
}