emulate.c 149.9 KB
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/******************************************************************************
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 * emulate.c
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 *
 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
 *
 * Copyright (c) 2005 Keir Fraser
 *
 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
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 * privileged instructions:
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 *
 * Copyright (C) 2006 Qumranet
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 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
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 *
 *   Avi Kivity <avi@qumranet.com>
 *   Yaniv Kamay <yaniv@qumranet.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
 */

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#include <linux/kvm_host.h>
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#include "kvm_cache_regs.h"
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#include <asm/kvm_emulate.h>
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#include <linux/stringify.h>
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#include <asm/debugreg.h>
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#include <asm/nospec-branch.h>
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#include "x86.h"
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#include "tss.h"
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#include "mmu.h"
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#include "pmu.h"
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/*
 * Operand types
 */
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#define OpNone             0ull
#define OpImplicit         1ull  /* No generic decode */
#define OpReg              2ull  /* Register */
#define OpMem              3ull  /* Memory */
#define OpAcc              4ull  /* Accumulator: AL/AX/EAX/RAX */
#define OpDI               5ull  /* ES:DI/EDI/RDI */
#define OpMem64            6ull  /* Memory, 64-bit */
#define OpImmUByte         7ull  /* Zero-extended 8-bit immediate */
#define OpDX               8ull  /* DX register */
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#define OpCL               9ull  /* CL register (for shifts) */
#define OpImmByte         10ull  /* 8-bit sign extended immediate */
#define OpOne             11ull  /* Implied 1 */
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#define OpImm             12ull  /* Sign extended up to 32-bit immediate */
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#define OpMem16           13ull  /* Memory operand (16-bit). */
#define OpMem32           14ull  /* Memory operand (32-bit). */
#define OpImmU            15ull  /* Immediate operand, zero extended */
#define OpSI              16ull  /* SI/ESI/RSI */
#define OpImmFAddr        17ull  /* Immediate far address */
#define OpMemFAddr        18ull  /* Far address in memory */
#define OpImmU16          19ull  /* Immediate operand, 16 bits, zero extended */
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#define OpES              20ull  /* ES */
#define OpCS              21ull  /* CS */
#define OpSS              22ull  /* SS */
#define OpDS              23ull  /* DS */
#define OpFS              24ull  /* FS */
#define OpGS              25ull  /* GS */
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#define OpMem8            26ull  /* 8-bit zero extended memory operand */
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#define OpImm64           27ull  /* Sign extended 16/32/64-bit immediate */
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#define OpXLat            28ull  /* memory at BX/EBX/RBX + zero-extended AL */
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#define OpAccLo           29ull  /* Low part of extended acc (AX/AX/EAX/RAX) */
#define OpAccHi           30ull  /* High part of extended acc (-/DX/EDX/RDX) */
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#define OpBits             5  /* Width of operand field */
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#define OpMask             ((1ull << OpBits) - 1)
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/*
 * Opcode effective-address decode tables.
 * Note that we only emulate instructions that have at least one memory
 * operand (excluding implicit stack references). We assume that stack
 * references and instruction fetches will never occur in special memory
 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
 * not be handled.
 */

/* Operand sizes: 8-bit operands or specified/overridden size. */
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#define ByteOp      (1<<0)	/* 8-bit operands. */
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/* Destination operand type. */
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#define DstShift    1
#define ImplicitOps (OpImplicit << DstShift)
#define DstReg      (OpReg << DstShift)
#define DstMem      (OpMem << DstShift)
#define DstAcc      (OpAcc << DstShift)
#define DstDI       (OpDI << DstShift)
#define DstMem64    (OpMem64 << DstShift)
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#define DstMem16    (OpMem16 << DstShift)
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#define DstImmUByte (OpImmUByte << DstShift)
#define DstDX       (OpDX << DstShift)
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#define DstAccLo    (OpAccLo << DstShift)
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#define DstMask     (OpMask << DstShift)
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/* Source operand type. */
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#define SrcShift    6
#define SrcNone     (OpNone << SrcShift)
#define SrcReg      (OpReg << SrcShift)
#define SrcMem      (OpMem << SrcShift)
#define SrcMem16    (OpMem16 << SrcShift)
#define SrcMem32    (OpMem32 << SrcShift)
#define SrcImm      (OpImm << SrcShift)
#define SrcImmByte  (OpImmByte << SrcShift)
#define SrcOne      (OpOne << SrcShift)
#define SrcImmUByte (OpImmUByte << SrcShift)
#define SrcImmU     (OpImmU << SrcShift)
#define SrcSI       (OpSI << SrcShift)
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#define SrcXLat     (OpXLat << SrcShift)
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#define SrcImmFAddr (OpImmFAddr << SrcShift)
#define SrcMemFAddr (OpMemFAddr << SrcShift)
#define SrcAcc      (OpAcc << SrcShift)
#define SrcImmU16   (OpImmU16 << SrcShift)
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#define SrcImm64    (OpImm64 << SrcShift)
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#define SrcDX       (OpDX << SrcShift)
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#define SrcMem8     (OpMem8 << SrcShift)
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#define SrcAccHi    (OpAccHi << SrcShift)
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#define SrcMask     (OpMask << SrcShift)
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#define BitOp       (1<<11)
#define MemAbs      (1<<12)      /* Memory operand is absolute displacement */
#define String      (1<<13)     /* String instruction (rep capable) */
#define Stack       (1<<14)     /* Stack instruction (push/pop) */
#define GroupMask   (7<<15)     /* Opcode uses one of the group mechanisms */
#define Group       (1<<15)     /* Bits 3:5 of modrm byte extend opcode */
#define GroupDual   (2<<15)     /* Alternate decoding of mod == 3 */
#define Prefix      (3<<15)     /* Instruction varies with 66/f2/f3 prefix */
#define RMExt       (4<<15)     /* Opcode extension in ModRM r/m if mod == 3 */
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#define Escape      (5<<15)     /* Escape to coprocessor instruction */
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#define InstrDual   (6<<15)     /* Alternate instruction decoding of mod == 3 */
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#define ModeDual    (7<<15)     /* Different instruction for 32/64 bit */
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#define Sse         (1<<18)     /* SSE Vector instruction */
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/* Generic ModRM decode. */
#define ModRM       (1<<19)
/* Destination is only written; never read. */
#define Mov         (1<<20)
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/* Misc flags */
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#define Prot        (1<<21) /* instruction generates #UD if not in prot-mode */
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#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
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#define NoAccess    (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
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#define Op3264      (1<<24) /* Operand is 64b in long mode, 32b otherwise */
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#define Undefined   (1<<25) /* No Such Instruction */
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#define Lock        (1<<26) /* lock prefix is allowed for the instruction */
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#define Priv        (1<<27) /* instruction generates #GP if current CPL != 0 */
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#define No64	    (1<<28)
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#define PageTable   (1 << 29)   /* instruction used to write page table */
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#define NotImpl     (1 << 30)   /* instruction is not implemented */
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/* Source 2 operand type */
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#define Src2Shift   (31)
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#define Src2None    (OpNone << Src2Shift)
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#define Src2Mem     (OpMem << Src2Shift)
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#define Src2CL      (OpCL << Src2Shift)
#define Src2ImmByte (OpImmByte << Src2Shift)
#define Src2One     (OpOne << Src2Shift)
#define Src2Imm     (OpImm << Src2Shift)
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#define Src2ES      (OpES << Src2Shift)
#define Src2CS      (OpCS << Src2Shift)
#define Src2SS      (OpSS << Src2Shift)
#define Src2DS      (OpDS << Src2Shift)
#define Src2FS      (OpFS << Src2Shift)
#define Src2GS      (OpGS << Src2Shift)
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#define Src2Mask    (OpMask << Src2Shift)
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#define Mmx         ((u64)1 << 40)  /* MMX Vector instruction */
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#define AlignMask   ((u64)7 << 41)
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#define Aligned     ((u64)1 << 41)  /* Explicitly aligned (e.g. MOVDQA) */
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#define Unaligned   ((u64)2 << 41)  /* Explicitly unaligned (e.g. MOVDQU) */
#define Avx         ((u64)3 << 41)  /* Advanced Vector Extensions */
#define Aligned16   ((u64)4 << 41)  /* Aligned to 16 byte boundary (e.g. FXSAVE) */
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#define Fastop      ((u64)1 << 44)  /* Use opcode::u.fastop */
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#define NoWrite     ((u64)1 << 45)  /* No writeback */
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#define SrcWrite    ((u64)1 << 46)  /* Write back src operand */
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#define NoMod	    ((u64)1 << 47)  /* Mod field is ignored */
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#define Intercept   ((u64)1 << 48)  /* Has valid intercept field */
#define CheckPerm   ((u64)1 << 49)  /* Has valid check_perm field */
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#define PrivUD      ((u64)1 << 51)  /* #UD instead of #GP on CPL > 0 */
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#define NearBranch  ((u64)1 << 52)  /* Near branches */
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#define No16	    ((u64)1 << 53)  /* No 16 bit operand */
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#define IncSP       ((u64)1 << 54)  /* SP is incremented before ModRM calc */
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#define TwoMemOp    ((u64)1 << 55)  /* Instruction has two memory operand */
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#define DstXacc     (DstAccLo | SrcAccHi | SrcWrite)
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#define X2(x...) x, x
#define X3(x...) X2(x), x
#define X4(x...) X2(x), X2(x)
#define X5(x...) X4(x), x
#define X6(x...) X4(x), X2(x)
#define X7(x...) X4(x), X3(x)
#define X8(x...) X4(x), X4(x)
#define X16(x...) X8(x), X8(x)
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#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
#define FASTOP_SIZE 8

/*
 * fastop functions have a special calling convention:
 *
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 * dst:    rax        (in/out)
 * src:    rdx        (in/out)
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 * src2:   rcx        (in)
 * flags:  rflags     (in/out)
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 * ex:     rsi        (in:fastop pointer, out:zero if exception)
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 *
 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
 * different operand sizes can be reached by calculation, rather than a jump
 * table (which would be bigger than the code).
 *
 * fastop functions are declared as taking a never-defined fastop parameter,
 * so they can't be called from C directly.
 */

struct fastop;

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struct opcode {
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	u64 flags : 56;
	u64 intercept : 8;
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	union {
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		int (*execute)(struct x86_emulate_ctxt *ctxt);
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		const struct opcode *group;
		const struct group_dual *gdual;
		const struct gprefix *gprefix;
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		const struct escape *esc;
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		const struct instr_dual *idual;
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		const struct mode_dual *mdual;
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		void (*fastop)(struct fastop *fake);
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	} u;
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	int (*check_perm)(struct x86_emulate_ctxt *ctxt);
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};

struct group_dual {
	struct opcode mod012[8];
	struct opcode mod3[8];
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};

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struct gprefix {
	struct opcode pfx_no;
	struct opcode pfx_66;
	struct opcode pfx_f2;
	struct opcode pfx_f3;
};

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struct escape {
	struct opcode op[8];
	struct opcode high[64];
};

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struct instr_dual {
	struct opcode mod012;
	struct opcode mod3;
};

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struct mode_dual {
	struct opcode mode32;
	struct opcode mode64;
};

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#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a

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enum x86_transfer_type {
	X86_TRANSFER_NONE,
	X86_TRANSFER_CALL_JMP,
	X86_TRANSFER_RET,
	X86_TRANSFER_TASK_SWITCH,
};

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static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
{
	if (!(ctxt->regs_valid & (1 << nr))) {
		ctxt->regs_valid |= 1 << nr;
		ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
	}
	return ctxt->_regs[nr];
}

static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
{
	ctxt->regs_valid |= 1 << nr;
	ctxt->regs_dirty |= 1 << nr;
	return &ctxt->_regs[nr];
}

static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
{
	reg_read(ctxt, nr);
	return reg_write(ctxt, nr);
}

static void writeback_registers(struct x86_emulate_ctxt *ctxt)
{
	unsigned reg;

	for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
		ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
}

static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
{
	ctxt->regs_dirty = 0;
	ctxt->regs_valid = 0;
}

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/*
 * These EFLAGS bits are restored from saved value during emulation, and
 * any changes are written back to the saved value after emulation.
 */
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#define EFLAGS_MASK (X86_EFLAGS_OF|X86_EFLAGS_SF|X86_EFLAGS_ZF|X86_EFLAGS_AF|\
		     X86_EFLAGS_PF|X86_EFLAGS_CF)
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#ifdef CONFIG_X86_64
#define ON64(x) x
#else
#define ON64(x)
#endif

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static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));

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#define FOP_FUNC(name) \
	".align " __stringify(FASTOP_SIZE) " \n\t" \
	".type " name ", @function \n\t" \
	name ":\n\t"

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#define FOP_RET   "ret \n\t"

#define FOP_START(op) \
	extern void em_##op(struct fastop *fake); \
	asm(".pushsection .text, \"ax\" \n\t" \
	    ".global em_" #op " \n\t" \
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	    FOP_FUNC("em_" #op)
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#define FOP_END \
	    ".popsection")

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#define FOPNOP() \
	FOP_FUNC(__stringify(__UNIQUE_ID(nop))) \
	FOP_RET
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#define FOP1E(op,  dst) \
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	FOP_FUNC(#op "_" #dst) \
	"10: " #op " %" #dst " \n\t" FOP_RET
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#define FOP1EEX(op,  dst) \
	FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
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#define FASTOP1(op) \
	FOP_START(op) \
	FOP1E(op##b, al) \
	FOP1E(op##w, ax) \
	FOP1E(op##l, eax) \
	ON64(FOP1E(op##q, rax))	\
	FOP_END

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/* 1-operand, using src2 (for MUL/DIV r/m) */
#define FASTOP1SRC2(op, name) \
	FOP_START(name) \
	FOP1E(op, cl) \
	FOP1E(op, cx) \
	FOP1E(op, ecx) \
	ON64(FOP1E(op, rcx)) \
	FOP_END

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/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
#define FASTOP1SRC2EX(op, name) \
	FOP_START(name) \
	FOP1EEX(op, cl) \
	FOP1EEX(op, cx) \
	FOP1EEX(op, ecx) \
	ON64(FOP1EEX(op, rcx)) \
	FOP_END

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#define FOP2E(op,  dst, src)	   \
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	FOP_FUNC(#op "_" #dst "_" #src) \
	#op " %" #src ", %" #dst " \n\t" FOP_RET
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#define FASTOP2(op) \
	FOP_START(op) \
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	FOP2E(op##b, al, dl) \
	FOP2E(op##w, ax, dx) \
	FOP2E(op##l, eax, edx) \
	ON64(FOP2E(op##q, rax, rdx)) \
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	FOP_END

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/* 2 operand, word only */
#define FASTOP2W(op) \
	FOP_START(op) \
	FOPNOP() \
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	FOP2E(op##w, ax, dx) \
	FOP2E(op##l, eax, edx) \
	ON64(FOP2E(op##q, rax, rdx)) \
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	FOP_END

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/* 2 operand, src is CL */
#define FASTOP2CL(op) \
	FOP_START(op) \
	FOP2E(op##b, al, cl) \
	FOP2E(op##w, ax, cl) \
	FOP2E(op##l, eax, cl) \
	ON64(FOP2E(op##q, rax, cl)) \
	FOP_END

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/* 2 operand, src and dest are reversed */
#define FASTOP2R(op, name) \
	FOP_START(name) \
	FOP2E(op##b, dl, al) \
	FOP2E(op##w, dx, ax) \
	FOP2E(op##l, edx, eax) \
	ON64(FOP2E(op##q, rdx, rax)) \
	FOP_END

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#define FOP3E(op,  dst, src, src2) \
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	FOP_FUNC(#op "_" #dst "_" #src "_" #src2) \
	#op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
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/* 3-operand, word-only, src2=cl */
#define FASTOP3WCL(op) \
	FOP_START(op) \
	FOPNOP() \
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	FOP3E(op##w, ax, dx, cl) \
	FOP3E(op##l, eax, edx, cl) \
	ON64(FOP3E(op##q, rax, rdx, cl)) \
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	FOP_END

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/* Special case for SETcc - 1 instruction per cc */
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#define FOP_SETCC(op) \
	".align 4 \n\t" \
	".type " #op ", @function \n\t" \
	#op ": \n\t" \
	#op " %al \n\t" \
	FOP_RET
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asm(".pushsection .fixup, \"ax\"\n"
    ".global kvm_fastop_exception \n"
    "kvm_fastop_exception: xor %esi, %esi; ret\n"
    ".popsection");
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FOP_START(setcc)
FOP_SETCC(seto)
FOP_SETCC(setno)
FOP_SETCC(setc)
FOP_SETCC(setnc)
FOP_SETCC(setz)
FOP_SETCC(setnz)
FOP_SETCC(setbe)
FOP_SETCC(setnbe)
FOP_SETCC(sets)
FOP_SETCC(setns)
FOP_SETCC(setp)
FOP_SETCC(setnp)
FOP_SETCC(setl)
FOP_SETCC(setnl)
FOP_SETCC(setle)
FOP_SETCC(setnle)
FOP_END;

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FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
FOP_END;

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/*
 * XXX: inoutclob user must know where the argument is being expanded.
 *      Relying on CC_HAVE_ASM_GOTO would allow us to remove _fault.
 */
#define asm_safe(insn, inoutclob...) \
({ \
	int _fault = 0; \
 \
	asm volatile("1:" insn "\n" \
	             "2:\n" \
	             ".pushsection .fixup, \"ax\"\n" \
	             "3: movl $1, %[_fault]\n" \
	             "   jmp  2b\n" \
	             ".popsection\n" \
	             _ASM_EXTABLE(1b, 3b) \
	             : [_fault] "+qm"(_fault) inoutclob ); \
 \
	_fault ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; \
})

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static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
				    enum x86_intercept intercept,
				    enum x86_intercept_stage stage)
{
	struct x86_instruction_info info = {
		.intercept  = intercept,
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		.rep_prefix = ctxt->rep_prefix,
		.modrm_mod  = ctxt->modrm_mod,
		.modrm_reg  = ctxt->modrm_reg,
		.modrm_rm   = ctxt->modrm_rm,
		.src_val    = ctxt->src.val64,
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		.dst_val    = ctxt->dst.val64,
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		.src_bytes  = ctxt->src.bytes,
		.dst_bytes  = ctxt->dst.bytes,
		.ad_bytes   = ctxt->ad_bytes,
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		.next_rip   = ctxt->eip,
	};

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	return ctxt->ops->intercept(ctxt, &info, stage);
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}

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static void assign_masked(ulong *dest, ulong src, ulong mask)
{
	*dest = (*dest & ~mask) | (src & mask);
}

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static void assign_register(unsigned long *reg, u64 val, int bytes)
{
	/* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
	switch (bytes) {
	case 1:
		*(u8 *)reg = (u8)val;
		break;
	case 2:
		*(u16 *)reg = (u16)val;
		break;
	case 4:
		*reg = (u32)val;
		break;	/* 64b: zero-extend */
	case 8:
		*reg = val;
		break;
	}
}

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static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
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{
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	return (1UL << (ctxt->ad_bytes << 3)) - 1;
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}

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static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
{
	u16 sel;
	struct desc_struct ss;

	if (ctxt->mode == X86EMUL_MODE_PROT64)
		return ~0UL;
	ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
	return ~0U >> ((ss.d ^ 1) * 16);  /* d=0: 0xffff; d=1: 0xffffffff */
}

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static int stack_size(struct x86_emulate_ctxt *ctxt)
{
	return (__fls(stack_mask(ctxt)) + 1) >> 3;
}

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/* Access/update address held in a register, based on addressing mode. */
544
static inline unsigned long
545
address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
546
{
547
	if (ctxt->ad_bytes == sizeof(unsigned long))
548 549
		return reg;
	else
550
		return reg & ad_mask(ctxt);
551 552 553
}

static inline unsigned long
554
register_address(struct x86_emulate_ctxt *ctxt, int reg)
555
{
556
	return address_mask(ctxt, reg_read(ctxt, reg));
557 558
}

559 560 561 562 563
static void masked_increment(ulong *reg, ulong mask, int inc)
{
	assign_masked(reg, *reg + inc, mask);
}

564
static inline void
565
register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
566
{
567
	ulong *preg = reg_rmw(ctxt, reg);
568

569
	assign_register(preg, *preg + inc, ctxt->ad_bytes);
570 571 572 573
}

static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
{
574
	masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
575
}
A
Avi Kivity 已提交
576

577 578 579 580 581 582 583
static u32 desc_limit_scaled(struct desc_struct *desc)
{
	u32 limit = get_desc_limit(desc);

	return desc->g ? (limit << 12) | 0xfff : limit;
}

584
static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
585 586 587 588
{
	if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
		return 0;

589
	return ctxt->ops->get_cached_segment_base(ctxt, seg);
590 591
}

592 593
static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
			     u32 error, bool valid)
594
{
595
	WARN_ON(vec > 0x1f);
596 597 598
	ctxt->exception.vector = vec;
	ctxt->exception.error_code = error;
	ctxt->exception.error_code_valid = valid;
599
	return X86EMUL_PROPAGATE_FAULT;
600 601
}

602 603 604 605 606
static int emulate_db(struct x86_emulate_ctxt *ctxt)
{
	return emulate_exception(ctxt, DB_VECTOR, 0, false);
}

607
static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
608
{
609
	return emulate_exception(ctxt, GP_VECTOR, err, true);
610 611
}

612 613 614 615 616
static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
{
	return emulate_exception(ctxt, SS_VECTOR, err, true);
}

617
static int emulate_ud(struct x86_emulate_ctxt *ctxt)
618
{
619
	return emulate_exception(ctxt, UD_VECTOR, 0, false);
620 621
}

622
static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
623
{
624
	return emulate_exception(ctxt, TS_VECTOR, err, true);
625 626
}

627 628
static int emulate_de(struct x86_emulate_ctxt *ctxt)
{
629
	return emulate_exception(ctxt, DE_VECTOR, 0, false);
630 631
}

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632 633 634 635 636
static int emulate_nm(struct x86_emulate_ctxt *ctxt)
{
	return emulate_exception(ctxt, NM_VECTOR, 0, false);
}

637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656
static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
{
	u16 selector;
	struct desc_struct desc;

	ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
	return selector;
}

static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
				 unsigned seg)
{
	u16 dummy;
	u32 base3;
	struct desc_struct desc;

	ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
	ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
}

657 658 659 660 661 662
/*
 * x86 defines three classes of vector instructions: explicitly
 * aligned, explicitly unaligned, and the rest, which change behaviour
 * depending on whether they're AVX encoded or not.
 *
 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
663 664
 * subject to the same check.  FXSAVE and FXRSTOR are checked here too as their
 * 512 bytes of data must be aligned to a 16 byte boundary.
665
 */
666
static unsigned insn_alignment(struct x86_emulate_ctxt *ctxt, unsigned size)
667
{
668
	u64 alignment = ctxt->d & AlignMask;
669 670

	if (likely(size < 16))
671
		return 1;
672

673 674 675
	switch (alignment) {
	case Unaligned:
	case Avx:
676
		return 1;
677
	case Aligned16:
678
		return 16;
679 680
	case Aligned:
	default:
681
		return size;
682
	}
683 684
}

685 686 687 688
static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
				       struct segmented_address addr,
				       unsigned *max_size, unsigned size,
				       bool write, bool fetch,
689
				       enum x86emul_mode mode, ulong *linear)
690
{
691 692
	struct desc_struct desc;
	bool usable;
693
	ulong la;
694
	u32 lim;
695
	u16 sel;
696
	u8  va_bits;
697

698
	la = seg_base(ctxt, addr.seg) + addr.ea;
699
	*max_size = 0;
700
	switch (mode) {
701
	case X86EMUL_MODE_PROT64:
702
		*linear = la;
703 704
		va_bits = ctxt_virt_addr_bits(ctxt);
		if (get_canonical(la, va_bits) != la)
705
			goto bad;
706

707
		*max_size = min_t(u64, ~0u, (1ull << va_bits) - la);
708 709
		if (size > *max_size)
			goto bad;
710 711
		break;
	default:
712
		*linear = la = (u32)la;
713 714
		usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
						addr.seg);
715 716
		if (!usable)
			goto bad;
717 718 719
		/* code segment in protected mode or read-only data segment */
		if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
					|| !(desc.type & 2)) && write)
720 721
			goto bad;
		/* unreadable code segment */
722
		if (!fetch && (desc.type & 8) && !(desc.type & 2))
723 724
			goto bad;
		lim = desc_limit_scaled(&desc);
725
		if (!(desc.type & 8) && (desc.type & 4)) {
G
Guo Chao 已提交
726
			/* expand-down segment */
727
			if (addr.ea <= lim)
728 729 730
				goto bad;
			lim = desc.d ? 0xffffffff : 0xffff;
		}
731 732
		if (addr.ea > lim)
			goto bad;
733 734 735 736 737 738 739
		if (lim == 0xffffffff)
			*max_size = ~0u;
		else {
			*max_size = (u64)lim + 1 - addr.ea;
			if (size > *max_size)
				goto bad;
		}
740 741
		break;
	}
742
	if (la & (insn_alignment(ctxt, size) - 1))
743
		return emulate_gp(ctxt, 0);
744
	return X86EMUL_CONTINUE;
745 746
bad:
	if (addr.seg == VCPU_SREG_SS)
747
		return emulate_ss(ctxt, 0);
748
	else
749
		return emulate_gp(ctxt, 0);
750 751
}

752 753 754 755 756
static int linearize(struct x86_emulate_ctxt *ctxt,
		     struct segmented_address addr,
		     unsigned size, bool write,
		     ulong *linear)
{
757
	unsigned max_size;
758 759
	return __linearize(ctxt, addr, &max_size, size, write, false,
			   ctxt->mode, linear);
760 761
}

762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781
static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
			     enum x86emul_mode mode)
{
	ulong linear;
	int rc;
	unsigned max_size;
	struct segmented_address addr = { .seg = VCPU_SREG_CS,
					   .ea = dst };

	if (ctxt->op_bytes != sizeof(unsigned long))
		addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
	rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear);
	if (rc == X86EMUL_CONTINUE)
		ctxt->_eip = addr.ea;
	return rc;
}

static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
{
	return assign_eip(ctxt, dst, ctxt->mode);
782 783
}

784 785 786 787
static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
			  const struct desc_struct *cs_desc)
{
	enum x86emul_mode mode = ctxt->mode;
788
	int rc;
789 790

#ifdef CONFIG_X86_64
791 792 793
	if (ctxt->mode >= X86EMUL_MODE_PROT16) {
		if (cs_desc->l) {
			u64 efer = 0;
794

795 796 797 798 799
			ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
			if (efer & EFER_LMA)
				mode = X86EMUL_MODE_PROT64;
		} else
			mode = X86EMUL_MODE_PROT32; /* temporary value */
800 801 802 803
	}
#endif
	if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32)
		mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
804 805 806 807
	rc = assign_eip(ctxt, dst, mode);
	if (rc == X86EMUL_CONTINUE)
		ctxt->mode = mode;
	return rc;
808 809 810 811 812 813
}

static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
{
	return assign_eip_near(ctxt, ctxt->_eip + rel);
}
814

815 816 817 818 819 820 821 822 823 824 825 826 827
static int linear_read_system(struct x86_emulate_ctxt *ctxt, ulong linear,
			      void *data, unsigned size)
{
	return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
}

static int linear_write_system(struct x86_emulate_ctxt *ctxt,
			       ulong linear, void *data,
			       unsigned int size)
{
	return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception);
}

828 829 830 831 832
static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
			      struct segmented_address addr,
			      void *data,
			      unsigned size)
{
833 834 835
	int rc;
	ulong linear;

836
	rc = linearize(ctxt, addr, size, false, &linear);
837 838
	if (rc != X86EMUL_CONTINUE)
		return rc;
839
	return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
840 841
}

842 843 844 845 846 847 848 849 850 851 852 853 854 855
static int segmented_write_std(struct x86_emulate_ctxt *ctxt,
			       struct segmented_address addr,
			       void *data,
			       unsigned int size)
{
	int rc;
	ulong linear;

	rc = linearize(ctxt, addr, size, true, &linear);
	if (rc != X86EMUL_CONTINUE)
		return rc;
	return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception);
}

856
/*
857
 * Prefetch the remaining bytes of the instruction without crossing page
858 859
 * boundary if they are not in fetch_cache yet.
 */
860
static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
861 862
{
	int rc;
863
	unsigned size, max_size;
864
	unsigned long linear;
865
	int cur_size = ctxt->fetch.end - ctxt->fetch.data;
866
	struct segmented_address addr = { .seg = VCPU_SREG_CS,
867 868
					   .ea = ctxt->eip + cur_size };

869 870 871 872 873 874 875 876 877 878
	/*
	 * We do not know exactly how many bytes will be needed, and
	 * __linearize is expensive, so fetch as much as possible.  We
	 * just have to avoid going beyond the 15 byte limit, the end
	 * of the segment, or the end of the page.
	 *
	 * __linearize is called with size 0 so that it does not do any
	 * boundary check itself.  Instead, we use max_size to check
	 * against op_size.
	 */
879 880
	rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode,
			 &linear);
881 882 883
	if (unlikely(rc != X86EMUL_CONTINUE))
		return rc;

884
	size = min_t(unsigned, 15UL ^ cur_size, max_size);
885
	size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
886 887 888 889 890 891 892 893

	/*
	 * One instruction can only straddle two pages,
	 * and one has been loaded at the beginning of
	 * x86_decode_insn.  So, if not enough bytes
	 * still, we must have hit the 15-byte boundary.
	 */
	if (unlikely(size < op_size))
894 895
		return emulate_gp(ctxt, 0);

896
	rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
897 898 899
			      size, &ctxt->exception);
	if (unlikely(rc != X86EMUL_CONTINUE))
		return rc;
900
	ctxt->fetch.end += size;
901
	return X86EMUL_CONTINUE;
902 903
}

904 905
static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
					       unsigned size)
906
{
907 908 909 910
	unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;

	if (unlikely(done_size < size))
		return __do_insn_fetch_bytes(ctxt, size - done_size);
911 912
	else
		return X86EMUL_CONTINUE;
913 914
}

915
/* Fetch next part of the instruction being emulated. */
916
#define insn_fetch(_type, _ctxt)					\
917 918 919
({	_type _x;							\
									\
	rc = do_insn_fetch_bytes(_ctxt, sizeof(_type));			\
920 921
	if (rc != X86EMUL_CONTINUE)					\
		goto done;						\
922
	ctxt->_eip += sizeof(_type);					\
923
	memcpy(&_x, ctxt->fetch.ptr, sizeof(_type));			\
924
	ctxt->fetch.ptr += sizeof(_type);				\
925
	_x;								\
926 927
})

928
#define insn_fetch_arr(_arr, _size, _ctxt)				\
929 930
({									\
	rc = do_insn_fetch_bytes(_ctxt, _size);				\
931 932
	if (rc != X86EMUL_CONTINUE)					\
		goto done;						\
933
	ctxt->_eip += (_size);						\
934 935
	memcpy(_arr, ctxt->fetch.ptr, _size);				\
	ctxt->fetch.ptr += (_size);					\
936 937
})

938 939 940 941 942
/*
 * Given the 'reg' portion of a ModRM byte, and a register block, return a
 * pointer into the block that addresses the relevant register.
 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
 */
943
static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
944
			     int byteop)
A
Avi Kivity 已提交
945 946
{
	void *p;
947
	int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
A
Avi Kivity 已提交
948 949

	if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
950 951 952
		p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
	else
		p = reg_rmw(ctxt, modrm_reg);
A
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953 954 955 956
	return p;
}

static int read_descriptor(struct x86_emulate_ctxt *ctxt,
957
			   struct segmented_address addr,
A
Avi Kivity 已提交
958 959 960 961 962 963 964
			   u16 *size, unsigned long *address, int op_bytes)
{
	int rc;

	if (op_bytes == 2)
		op_bytes = 3;
	*address = 0;
965
	rc = segmented_read_std(ctxt, addr, size, 2);
966
	if (rc != X86EMUL_CONTINUE)
A
Avi Kivity 已提交
967
		return rc;
968
	addr.ea += 2;
969
	rc = segmented_read_std(ctxt, addr, address, op_bytes);
A
Avi Kivity 已提交
970 971 972
	return rc;
}

973 974 975 976 977 978 979 980 981 982
FASTOP2(add);
FASTOP2(or);
FASTOP2(adc);
FASTOP2(sbb);
FASTOP2(and);
FASTOP2(sub);
FASTOP2(xor);
FASTOP2(cmp);
FASTOP2(test);

983 984
FASTOP1SRC2(mul, mul_ex);
FASTOP1SRC2(imul, imul_ex);
985 986
FASTOP1SRC2EX(div, div_ex);
FASTOP1SRC2EX(idiv, idiv_ex);
987

988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012
FASTOP3WCL(shld);
FASTOP3WCL(shrd);

FASTOP2W(imul);

FASTOP1(not);
FASTOP1(neg);
FASTOP1(inc);
FASTOP1(dec);

FASTOP2CL(rol);
FASTOP2CL(ror);
FASTOP2CL(rcl);
FASTOP2CL(rcr);
FASTOP2CL(shl);
FASTOP2CL(shr);
FASTOP2CL(sar);

FASTOP2W(bsf);
FASTOP2W(bsr);
FASTOP2W(bt);
FASTOP2W(bts);
FASTOP2W(btr);
FASTOP2W(btc);

1013 1014
FASTOP2(xadd);

1015 1016
FASTOP2R(cmp, cmp_r);

1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032
static int em_bsf_c(struct x86_emulate_ctxt *ctxt)
{
	/* If src is zero, do not writeback, but update flags */
	if (ctxt->src.val == 0)
		ctxt->dst.type = OP_NONE;
	return fastop(ctxt, em_bsf);
}

static int em_bsr_c(struct x86_emulate_ctxt *ctxt)
{
	/* If src is zero, do not writeback, but update flags */
	if (ctxt->src.val == 0)
		ctxt->dst.type = OP_NONE;
	return fastop(ctxt, em_bsr);
}

1033
static __always_inline u8 test_cc(unsigned int condition, unsigned long flags)
1034
{
1035 1036
	u8 rc;
	void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
1037

1038
	flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
1039 1040
	asm("push %[flags]; popf; " CALL_NOSPEC
	    : "=a"(rc) : [thunk_target]"r"(fop), [flags]"r"(flags));
1041
	return rc;
1042 1043
}

1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061
static void fetch_register_operand(struct operand *op)
{
	switch (op->bytes) {
	case 1:
		op->val = *(u8 *)op->addr.reg;
		break;
	case 2:
		op->val = *(u16 *)op->addr.reg;
		break;
	case 4:
		op->val = *(u32 *)op->addr.reg;
		break;
	case 8:
		op->val = *(u64 *)op->addr.reg;
		break;
	}
}

A
Avi Kivity 已提交
1062 1063 1064
static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
{
	switch (reg) {
1065 1066 1067 1068 1069 1070 1071 1072
	case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
	case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
	case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
	case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
	case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
	case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
	case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
	case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
A
Avi Kivity 已提交
1073
#ifdef CONFIG_X86_64
1074 1075 1076 1077 1078 1079 1080 1081
	case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
	case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
	case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
	case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
	case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
	case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
	case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
	case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
A
Avi Kivity 已提交
1082 1083 1084 1085 1086 1087 1088 1089 1090
#endif
	default: BUG();
	}
}

static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
			  int reg)
{
	switch (reg) {
1091 1092 1093 1094 1095 1096 1097 1098
	case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
	case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
	case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
	case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
	case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
	case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
	case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
	case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
A
Avi Kivity 已提交
1099
#ifdef CONFIG_X86_64
1100 1101 1102 1103 1104 1105 1106 1107
	case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
	case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
	case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
	case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
	case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
	case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
	case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
	case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
A
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1108 1109 1110 1111 1112
#endif
	default: BUG();
	}
}

A
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1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142
static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
{
	switch (reg) {
	case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
	case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
	case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
	case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
	case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
	case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
	case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
	case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
	default: BUG();
	}
}

static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
{
	switch (reg) {
	case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
	case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
	case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
	case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
	case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
	case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
	case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
	case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
	default: BUG();
	}
}

1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1179
static int em_fninit(struct x86_emulate_ctxt *ctxt)
{
	if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
		return emulate_nm(ctxt);

	asm volatile("fninit");
	return X86EMUL_CONTINUE;
}

static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
{
	u16 fcw;

	if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
		return emulate_nm(ctxt);

	asm volatile("fnstcw %0": "+m"(fcw));

	ctxt->dst.val = fcw;

	return X86EMUL_CONTINUE;
}

static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
{
	u16 fsw;

	if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
		return emulate_nm(ctxt);

	asm volatile("fnstsw %0": "+m"(fsw));

	ctxt->dst.val = fsw;

	return X86EMUL_CONTINUE;
}

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1180
static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
1181
				    struct operand *op)
1182
{
1183
	unsigned reg = ctxt->modrm_reg;
1184

1185 1186
	if (!(ctxt->d & ModRM))
		reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
A
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1187

1188
	if (ctxt->d & Sse) {
A
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1189 1190 1191 1192 1193 1194
		op->type = OP_XMM;
		op->bytes = 16;
		op->addr.xmm = reg;
		read_sse_reg(ctxt, &op->vec_val, reg);
		return;
	}
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1195 1196 1197 1198 1199 1200 1201
	if (ctxt->d & Mmx) {
		reg &= 7;
		op->type = OP_MM;
		op->bytes = 8;
		op->addr.mm = reg;
		return;
	}
A
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1202

1203
	op->type = OP_REG;
1204 1205 1206
	op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
	op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);

1207
	fetch_register_operand(op);
1208 1209 1210
	op->orig_val = op->val;
}

1211 1212 1213 1214 1215 1216
static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
{
	if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
		ctxt->modrm_seg = VCPU_SREG_SS;
}

1217
static int decode_modrm(struct x86_emulate_ctxt *ctxt,
1218
			struct operand *op)
1219 1220
{
	u8 sib;
B
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1221
	int index_reg, base_reg, scale;
1222
	int rc = X86EMUL_CONTINUE;
1223
	ulong modrm_ea = 0;
1224

B
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1225 1226 1227
	ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
	index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
	base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1228

B
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1229
	ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
1230
	ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
B
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1231
	ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
1232
	ctxt->modrm_seg = VCPU_SREG_DS;
1233

1234
	if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
1235
		op->type = OP_REG;
1236
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1237
		op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
1238
				ctxt->d & ByteOp);
1239
		if (ctxt->d & Sse) {
A
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1240 1241
			op->type = OP_XMM;
			op->bytes = 16;
1242 1243
			op->addr.xmm = ctxt->modrm_rm;
			read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
A
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1244 1245
			return rc;
		}
A
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1246 1247 1248
		if (ctxt->d & Mmx) {
			op->type = OP_MM;
			op->bytes = 8;
1249
			op->addr.mm = ctxt->modrm_rm & 7;
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1250 1251
			return rc;
		}
1252
		fetch_register_operand(op);
1253 1254 1255
		return rc;
	}

1256 1257
	op->type = OP_MEM;

1258
	if (ctxt->ad_bytes == 2) {
1259 1260 1261 1262
		unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
		unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
		unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
		unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1263 1264

		/* 16-bit ModR/M decode. */
1265
		switch (ctxt->modrm_mod) {
1266
		case 0:
1267
			if (ctxt->modrm_rm == 6)
1268
				modrm_ea += insn_fetch(u16, ctxt);
1269 1270
			break;
		case 1:
1271
			modrm_ea += insn_fetch(s8, ctxt);
1272 1273
			break;
		case 2:
1274
			modrm_ea += insn_fetch(u16, ctxt);
1275 1276
			break;
		}
1277
		switch (ctxt->modrm_rm) {
1278
		case 0:
1279
			modrm_ea += bx + si;
1280 1281
			break;
		case 1:
1282
			modrm_ea += bx + di;
1283 1284
			break;
		case 2:
1285
			modrm_ea += bp + si;
1286 1287
			break;
		case 3:
1288
			modrm_ea += bp + di;
1289 1290
			break;
		case 4:
1291
			modrm_ea += si;
1292 1293
			break;
		case 5:
1294
			modrm_ea += di;
1295 1296
			break;
		case 6:
1297
			if (ctxt->modrm_mod != 0)
1298
				modrm_ea += bp;
1299 1300
			break;
		case 7:
1301
			modrm_ea += bx;
1302 1303
			break;
		}
1304 1305 1306
		if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
		    (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
			ctxt->modrm_seg = VCPU_SREG_SS;
1307
		modrm_ea = (u16)modrm_ea;
1308 1309
	} else {
		/* 32/64-bit ModR/M decode. */
1310
		if ((ctxt->modrm_rm & 7) == 4) {
1311
			sib = insn_fetch(u8, ctxt);
1312 1313 1314 1315
			index_reg |= (sib >> 3) & 7;
			base_reg |= sib & 7;
			scale = sib >> 6;

1316
			if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
1317
				modrm_ea += insn_fetch(s32, ctxt);
1318
			else {
1319
				modrm_ea += reg_read(ctxt, base_reg);
1320
				adjust_modrm_seg(ctxt, base_reg);
1321 1322 1323 1324
				/* Increment ESP on POP [ESP] */
				if ((ctxt->d & IncSP) &&
				    base_reg == VCPU_REGS_RSP)
					modrm_ea += ctxt->op_bytes;
1325
			}
1326
			if (index_reg != 4)
1327
				modrm_ea += reg_read(ctxt, index_reg) << scale;
1328
		} else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
1329
			modrm_ea += insn_fetch(s32, ctxt);
1330
			if (ctxt->mode == X86EMUL_MODE_PROT64)
1331
				ctxt->rip_relative = 1;
1332 1333
		} else {
			base_reg = ctxt->modrm_rm;
1334
			modrm_ea += reg_read(ctxt, base_reg);
1335 1336
			adjust_modrm_seg(ctxt, base_reg);
		}
1337
		switch (ctxt->modrm_mod) {
1338
		case 1:
1339
			modrm_ea += insn_fetch(s8, ctxt);
1340 1341
			break;
		case 2:
1342
			modrm_ea += insn_fetch(s32, ctxt);
1343 1344 1345
			break;
		}
	}
1346
	op->addr.mem.ea = modrm_ea;
1347 1348 1349
	if (ctxt->ad_bytes != 8)
		ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;

1350 1351 1352 1353 1354
done:
	return rc;
}

static int decode_abs(struct x86_emulate_ctxt *ctxt,
1355
		      struct operand *op)
1356
{
1357
	int rc = X86EMUL_CONTINUE;
1358

1359
	op->type = OP_MEM;
1360
	switch (ctxt->ad_bytes) {
1361
	case 2:
1362
		op->addr.mem.ea = insn_fetch(u16, ctxt);
1363 1364
		break;
	case 4:
1365
		op->addr.mem.ea = insn_fetch(u32, ctxt);
1366 1367
		break;
	case 8:
1368
		op->addr.mem.ea = insn_fetch(u64, ctxt);
1369 1370 1371 1372 1373 1374
		break;
	}
done:
	return rc;
}

1375
static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
1376
{
1377
	long sv = 0, mask;
1378

1379
	if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1380
		mask = ~((long)ctxt->dst.bytes * 8 - 1);
1381

1382 1383 1384 1385
		if (ctxt->src.bytes == 2)
			sv = (s16)ctxt->src.val & (s16)mask;
		else if (ctxt->src.bytes == 4)
			sv = (s32)ctxt->src.val & (s32)mask;
1386 1387
		else
			sv = (s64)ctxt->src.val & (s64)mask;
1388

1389 1390
		ctxt->dst.addr.mem.ea = address_mask(ctxt,
					   ctxt->dst.addr.mem.ea + (sv >> 3));
1391
	}
1392 1393

	/* only subword offset */
1394
	ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
1395 1396
}

1397 1398
static int read_emulated(struct x86_emulate_ctxt *ctxt,
			 unsigned long addr, void *dest, unsigned size)
A
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1399
{
1400
	int rc;
1401
	struct read_cache *mc = &ctxt->mem_read;
A
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1402

1403 1404
	if (mc->pos < mc->end)
		goto read_cached;
A
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1405

1406 1407 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417
	WARN_ON((mc->end + size) >= sizeof(mc->data));

	rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
				      &ctxt->exception);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	mc->end += size;

read_cached:
	memcpy(dest, mc->data + mc->pos, size);
	mc->pos += size;
1418 1419
	return X86EMUL_CONTINUE;
}
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1421 1422 1423 1424 1425
static int segmented_read(struct x86_emulate_ctxt *ctxt,
			  struct segmented_address addr,
			  void *data,
			  unsigned size)
{
1426 1427 1428
	int rc;
	ulong linear;

1429
	rc = linearize(ctxt, addr, size, false, &linear);
1430 1431
	if (rc != X86EMUL_CONTINUE)
		return rc;
1432
	return read_emulated(ctxt, linear, data, size);
1433 1434 1435 1436 1437 1438 1439
}

static int segmented_write(struct x86_emulate_ctxt *ctxt,
			   struct segmented_address addr,
			   const void *data,
			   unsigned size)
{
1440 1441 1442
	int rc;
	ulong linear;

1443
	rc = linearize(ctxt, addr, size, true, &linear);
1444 1445
	if (rc != X86EMUL_CONTINUE)
		return rc;
1446 1447
	return ctxt->ops->write_emulated(ctxt, linear, data, size,
					 &ctxt->exception);
1448 1449 1450 1451 1452 1453 1454
}

static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
			     struct segmented_address addr,
			     const void *orig_data, const void *data,
			     unsigned size)
{
1455 1456 1457
	int rc;
	ulong linear;

1458
	rc = linearize(ctxt, addr, size, true, &linear);
1459 1460
	if (rc != X86EMUL_CONTINUE)
		return rc;
1461 1462
	return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
					   size, &ctxt->exception);
1463 1464
}

1465 1466 1467 1468
static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
			   unsigned int size, unsigned short port,
			   void *dest)
{
1469
	struct read_cache *rc = &ctxt->io_read;
1470

1471 1472
	if (rc->pos == rc->end) { /* refill pio read ahead */
		unsigned int in_page, n;
1473
		unsigned int count = ctxt->rep_prefix ?
1474
			address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
1475
		in_page = (ctxt->eflags & X86_EFLAGS_DF) ?
1476 1477
			offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
			PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
1478
		n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
1479 1480 1481
		if (n == 0)
			n = 1;
		rc->pos = rc->end = 0;
1482
		if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
1483 1484
			return 0;
		rc->end = n * size;
A
Avi Kivity 已提交
1485 1486
	}

1487
	if (ctxt->rep_prefix && (ctxt->d & String) &&
1488
	    !(ctxt->eflags & X86_EFLAGS_DF)) {
1489 1490 1491 1492 1493 1494 1495 1496
		ctxt->dst.data = rc->data + rc->pos;
		ctxt->dst.type = OP_MEM_STR;
		ctxt->dst.count = (rc->end - rc->pos) / size;
		rc->pos = rc->end;
	} else {
		memcpy(dest, rc->data + rc->pos, size);
		rc->pos += size;
	}
1497 1498
	return 1;
}
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1499

1500 1501 1502 1503 1504 1505 1506 1507 1508 1509 1510 1511
static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
				     u16 index, struct desc_struct *desc)
{
	struct desc_ptr dt;
	ulong addr;

	ctxt->ops->get_idt(ctxt, &dt);

	if (dt.size < index * 8 + 7)
		return emulate_gp(ctxt, index << 3 | 0x2);

	addr = dt.address + index * 8;
1512
	return linear_read_system(ctxt, addr, desc, sizeof *desc);
1513 1514
}

1515 1516 1517
static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
				     u16 selector, struct desc_ptr *dt)
{
1518
	const struct x86_emulate_ops *ops = ctxt->ops;
1519
	u32 base3 = 0;
1520

1521 1522
	if (selector & 1 << 2) {
		struct desc_struct desc;
1523 1524
		u16 sel;

1525
		memset (dt, 0, sizeof *dt);
1526 1527
		if (!ops->get_segment(ctxt, &sel, &desc, &base3,
				      VCPU_SREG_LDTR))
1528
			return;
1529

1530
		dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1531
		dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
1532
	} else
1533
		ops->get_gdt(ctxt, dt);
1534
}
1535

1536 1537
static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt,
			      u16 selector, ulong *desc_addr_p)
1538 1539 1540 1541
{
	struct desc_ptr dt;
	u16 index = selector >> 3;
	ulong addr;
1542

1543
	get_descriptor_table_ptr(ctxt, selector, &dt);
1544

1545 1546
	if (dt.size < index * 8 + 7)
		return emulate_gp(ctxt, selector & 0xfffc);
1547

1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563 1564 1565 1566 1567 1568 1569 1570 1571 1572 1573 1574
	addr = dt.address + index * 8;

#ifdef CONFIG_X86_64
	if (addr >> 32 != 0) {
		u64 efer = 0;

		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
		if (!(efer & EFER_LMA))
			addr &= (u32)-1;
	}
#endif

	*desc_addr_p = addr;
	return X86EMUL_CONTINUE;
}

/* allowed just for 8 bytes segments */
static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				   u16 selector, struct desc_struct *desc,
				   ulong *desc_addr_p)
{
	int rc;

	rc = get_descriptor_ptr(ctxt, selector, desc_addr_p);
	if (rc != X86EMUL_CONTINUE)
		return rc;

1575
	return linear_read_system(ctxt, *desc_addr_p, desc, sizeof(*desc));
1576
}
1577

1578 1579 1580 1581
/* allowed just for 8 bytes segments */
static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				    u16 selector, struct desc_struct *desc)
{
1582
	int rc;
1583
	ulong addr;
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Avi Kivity 已提交
1584

1585 1586 1587
	rc = get_descriptor_ptr(ctxt, selector, &addr);
	if (rc != X86EMUL_CONTINUE)
		return rc;
A
Avi Kivity 已提交
1588

1589
	return linear_write_system(ctxt, addr, desc, sizeof *desc);
1590
}
1591

1592
static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1593
				     u16 selector, int seg, u8 cpl,
1594
				     enum x86_transfer_type transfer,
1595
				     struct desc_struct *desc)
1596
{
1597
	struct desc_struct seg_desc, old_desc;
1598
	u8 dpl, rpl;
1599 1600 1601
	unsigned err_vec = GP_VECTOR;
	u32 err_code = 0;
	bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1602
	ulong desc_addr;
1603
	int ret;
1604
	u16 dummy;
1605
	u32 base3 = 0;
1606

1607
	memset(&seg_desc, 0, sizeof seg_desc);
1608

1609 1610 1611
	if (ctxt->mode == X86EMUL_MODE_REAL) {
		/* set real mode segment descriptor (keep limit etc. for
		 * unreal mode) */
1612
		ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
1613 1614
		set_desc_base(&seg_desc, selector << 4);
		goto load;
1615 1616 1617 1618 1619 1620 1621 1622 1623
	} else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
		/* VM86 needs a clean new segment descriptor */
		set_desc_base(&seg_desc, selector << 4);
		set_desc_limit(&seg_desc, 0xffff);
		seg_desc.type = 3;
		seg_desc.p = 1;
		seg_desc.s = 1;
		seg_desc.dpl = 3;
		goto load;
1624 1625
	}

1626 1627
	rpl = selector & 3;

1628 1629 1630 1631
	/* TR should be in GDT only */
	if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
		goto exception;

1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653
	/* NULL selector is not valid for TR, CS and (except for long mode) SS */
	if (null_selector) {
		if (seg == VCPU_SREG_CS || seg == VCPU_SREG_TR)
			goto exception;

		if (seg == VCPU_SREG_SS) {
			if (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl)
				goto exception;

			/*
			 * ctxt->ops->set_segment expects the CPL to be in
			 * SS.DPL, so fake an expand-up 32-bit data segment.
			 */
			seg_desc.type = 3;
			seg_desc.p = 1;
			seg_desc.s = 1;
			seg_desc.dpl = cpl;
			seg_desc.d = 1;
			seg_desc.g = 1;
		}

		/* Skip all following checks */
1654
		goto load;
1655
	}
1656

1657
	ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
1658 1659 1660 1661
	if (ret != X86EMUL_CONTINUE)
		return ret;

	err_code = selector & 0xfffc;
1662 1663
	err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR :
							   GP_VECTOR;
1664

G
Guo Chao 已提交
1665
	/* can't load system descriptor into segment selector */
1666 1667 1668
	if (seg <= VCPU_SREG_GS && !seg_desc.s) {
		if (transfer == X86_TRANSFER_CALL_JMP)
			return X86EMUL_UNHANDLEABLE;
1669
		goto exception;
1670
	}
1671 1672 1673 1674 1675 1676 1677 1678 1679 1680 1681 1682 1683 1684 1685 1686

	if (!seg_desc.p) {
		err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
		goto exception;
	}

	dpl = seg_desc.dpl;

	switch (seg) {
	case VCPU_SREG_SS:
		/*
		 * segment is not a writable data segment or segment
		 * selector's RPL != CPL or segment selector's RPL != CPL
		 */
		if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
			goto exception;
A
Avi Kivity 已提交
1687
		break;
1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700
	case VCPU_SREG_CS:
		if (!(seg_desc.type & 8))
			goto exception;

		if (seg_desc.type & 4) {
			/* conforming */
			if (dpl > cpl)
				goto exception;
		} else {
			/* nonconforming */
			if (rpl > cpl || dpl != cpl)
				goto exception;
		}
1701 1702 1703 1704 1705 1706 1707 1708 1709
		/* in long-mode d/b must be clear if l is set */
		if (seg_desc.d && seg_desc.l) {
			u64 efer = 0;

			ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
			if (efer & EFER_LMA)
				goto exception;
		}

1710 1711
		/* CS(RPL) <- CPL */
		selector = (selector & 0xfffc) | cpl;
A
Avi Kivity 已提交
1712
		break;
1713 1714 1715
	case VCPU_SREG_TR:
		if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
			goto exception;
1716 1717 1718 1719 1720 1721
		old_desc = seg_desc;
		seg_desc.type |= 2; /* busy */
		ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
						  sizeof(seg_desc), &ctxt->exception);
		if (ret != X86EMUL_CONTINUE)
			return ret;
1722 1723 1724 1725 1726 1727
		break;
	case VCPU_SREG_LDTR:
		if (seg_desc.s || seg_desc.type != 2)
			goto exception;
		break;
	default: /*  DS, ES, FS, or GS */
1728
		/*
1729 1730 1731
		 * segment is not a data or readable code segment or
		 * ((segment is a data or nonconforming code segment)
		 * and (both RPL and CPL > DPL))
1732
		 */
1733 1734 1735 1736
		if ((seg_desc.type & 0xa) == 0x8 ||
		    (((seg_desc.type & 0xc) != 0xc) &&
		     (rpl > dpl && cpl > dpl)))
			goto exception;
A
Avi Kivity 已提交
1737
		break;
1738 1739 1740 1741
	}

	if (seg_desc.s) {
		/* mark segment as accessed */
1742 1743 1744 1745 1746 1747 1748
		if (!(seg_desc.type & 1)) {
			seg_desc.type |= 1;
			ret = write_segment_descriptor(ctxt, selector,
						       &seg_desc);
			if (ret != X86EMUL_CONTINUE)
				return ret;
		}
1749
	} else if (ctxt->mode == X86EMUL_MODE_PROT64) {
1750
		ret = linear_read_system(ctxt, desc_addr+8, &base3, sizeof(base3));
1751 1752
		if (ret != X86EMUL_CONTINUE)
			return ret;
1753 1754
		if (emul_is_noncanonical_address(get_desc_base(&seg_desc) |
				((u64)base3 << 32), ctxt))
1755
			return emulate_gp(ctxt, 0);
1756 1757
	}
load:
1758
	ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
1759 1760
	if (desc)
		*desc = seg_desc;
1761 1762
	return X86EMUL_CONTINUE;
exception:
1763
	return emulate_exception(ctxt, err_vec, err_code, true);
1764 1765
}

1766 1767 1768 1769
static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				   u16 selector, int seg)
{
	u8 cpl = ctxt->ops->cpl(ctxt);
1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784

	/*
	 * None of MOV, POP and LSS can load a NULL selector in CPL=3, but
	 * they can load it at CPL<3 (Intel's manual says only LSS can,
	 * but it's wrong).
	 *
	 * However, the Intel manual says that putting IST=1/DPL=3 in
	 * an interrupt gate will result in SS=3 (the AMD manual instead
	 * says it doesn't), so allow SS=3 in __load_segment_descriptor
	 * and only forbid it here.
	 */
	if (seg == VCPU_SREG_SS && selector == 3 &&
	    ctxt->mode == X86EMUL_MODE_PROT64)
		return emulate_exception(ctxt, GP_VECTOR, 0, true);

1785 1786
	return __load_segment_descriptor(ctxt, selector, seg, cpl,
					 X86_TRANSFER_NONE, NULL);
1787 1788
}

1789 1790
static void write_register_operand(struct operand *op)
{
1791
	return assign_register(op->addr.reg, op->val, op->bytes);
1792 1793
}

1794
static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
1795
{
1796
	switch (op->type) {
1797
	case OP_REG:
1798
		write_register_operand(op);
A
Avi Kivity 已提交
1799
		break;
1800
	case OP_MEM:
1801
		if (ctxt->lock_prefix)
P
Paolo Bonzini 已提交
1802 1803 1804 1805 1806 1807 1808
			return segmented_cmpxchg(ctxt,
						 op->addr.mem,
						 &op->orig_val,
						 &op->val,
						 op->bytes);
		else
			return segmented_write(ctxt,
1809 1810 1811
					       op->addr.mem,
					       &op->val,
					       op->bytes);
1812
		break;
1813
	case OP_MEM_STR:
P
Paolo Bonzini 已提交
1814 1815 1816 1817
		return segmented_write(ctxt,
				       op->addr.mem,
				       op->data,
				       op->bytes * op->count);
1818
		break;
A
Avi Kivity 已提交
1819
	case OP_XMM:
1820
		write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
A
Avi Kivity 已提交
1821
		break;
A
Avi Kivity 已提交
1822
	case OP_MM:
1823
		write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
A
Avi Kivity 已提交
1824
		break;
1825 1826
	case OP_NONE:
		/* no writeback */
1827
		break;
1828
	default:
1829
		break;
A
Avi Kivity 已提交
1830
	}
1831 1832
	return X86EMUL_CONTINUE;
}
A
Avi Kivity 已提交
1833

1834
static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
1835
{
1836
	struct segmented_address addr;
1837

1838
	rsp_increment(ctxt, -bytes);
1839
	addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1840 1841
	addr.seg = VCPU_SREG_SS;

1842 1843 1844 1845 1846
	return segmented_write(ctxt, addr, data, bytes);
}

static int em_push(struct x86_emulate_ctxt *ctxt)
{
1847
	/* Disable writeback. */
1848
	ctxt->dst.type = OP_NONE;
1849
	return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
1850
}
1851

1852 1853 1854 1855
static int emulate_pop(struct x86_emulate_ctxt *ctxt,
		       void *dest, int len)
{
	int rc;
1856
	struct segmented_address addr;
1857

1858
	addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1859
	addr.seg = VCPU_SREG_SS;
1860
	rc = segmented_read(ctxt, addr, dest, len);
1861 1862 1863
	if (rc != X86EMUL_CONTINUE)
		return rc;

1864
	rsp_increment(ctxt, len);
1865
	return rc;
1866 1867
}

1868 1869
static int em_pop(struct x86_emulate_ctxt *ctxt)
{
1870
	return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1871 1872
}

1873
static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1874
			void *dest, int len)
1875 1876
{
	int rc;
1877
	unsigned long val, change_mask;
1878
	int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
1879
	int cpl = ctxt->ops->cpl(ctxt);
1880

1881
	rc = emulate_pop(ctxt, &val, len);
1882 1883
	if (rc != X86EMUL_CONTINUE)
		return rc;
1884

1885 1886 1887 1888
	change_mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
		      X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF |
		      X86_EFLAGS_TF | X86_EFLAGS_DF | X86_EFLAGS_NT |
		      X86_EFLAGS_AC | X86_EFLAGS_ID;
1889

1890 1891 1892 1893 1894
	switch(ctxt->mode) {
	case X86EMUL_MODE_PROT64:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT16:
		if (cpl == 0)
1895
			change_mask |= X86_EFLAGS_IOPL;
1896
		if (cpl <= iopl)
1897
			change_mask |= X86_EFLAGS_IF;
1898 1899
		break;
	case X86EMUL_MODE_VM86:
1900 1901
		if (iopl < 3)
			return emulate_gp(ctxt, 0);
1902
		change_mask |= X86_EFLAGS_IF;
1903 1904
		break;
	default: /* real mode */
1905
		change_mask |= (X86_EFLAGS_IOPL | X86_EFLAGS_IF);
1906
		break;
1907
	}
1908 1909 1910 1911 1912

	*(unsigned long *)dest =
		(ctxt->eflags & ~change_mask) | (val & change_mask);

	return rc;
1913 1914
}

1915 1916
static int em_popf(struct x86_emulate_ctxt *ctxt)
{
1917 1918 1919 1920
	ctxt->dst.type = OP_REG;
	ctxt->dst.addr.reg = &ctxt->eflags;
	ctxt->dst.bytes = ctxt->op_bytes;
	return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1921 1922
}

A
Avi Kivity 已提交
1923 1924 1925 1926 1927
static int em_enter(struct x86_emulate_ctxt *ctxt)
{
	int rc;
	unsigned frame_size = ctxt->src.val;
	unsigned nesting_level = ctxt->src2.val & 31;
1928
	ulong rbp;
A
Avi Kivity 已提交
1929 1930 1931 1932

	if (nesting_level)
		return X86EMUL_UNHANDLEABLE;

1933 1934
	rbp = reg_read(ctxt, VCPU_REGS_RBP);
	rc = push(ctxt, &rbp, stack_size(ctxt));
A
Avi Kivity 已提交
1935 1936
	if (rc != X86EMUL_CONTINUE)
		return rc;
1937
	assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
A
Avi Kivity 已提交
1938
		      stack_mask(ctxt));
1939 1940
	assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
		      reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
A
Avi Kivity 已提交
1941 1942 1943 1944
		      stack_mask(ctxt));
	return X86EMUL_CONTINUE;
}

A
Avi Kivity 已提交
1945 1946
static int em_leave(struct x86_emulate_ctxt *ctxt)
{
1947
	assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
A
Avi Kivity 已提交
1948
		      stack_mask(ctxt));
1949
	return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
A
Avi Kivity 已提交
1950 1951
}

1952
static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
1953
{
1954 1955
	int seg = ctxt->src2.val;

1956
	ctxt->src.val = get_segment_selector(ctxt, seg);
1957 1958 1959 1960
	if (ctxt->op_bytes == 4) {
		rsp_increment(ctxt, -2);
		ctxt->op_bytes = 2;
	}
1961

1962
	return em_push(ctxt);
1963 1964
}

1965
static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
1966
{
1967
	int seg = ctxt->src2.val;
1968 1969
	unsigned long selector;
	int rc;
1970

1971
	rc = emulate_pop(ctxt, &selector, 2);
1972 1973 1974
	if (rc != X86EMUL_CONTINUE)
		return rc;

1975 1976
	if (ctxt->modrm_reg == VCPU_SREG_SS)
		ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
1977 1978
	if (ctxt->op_bytes > 2)
		rsp_increment(ctxt, ctxt->op_bytes - 2);
1979

1980
	rc = load_segment_descriptor(ctxt, (u16)selector, seg);
1981
	return rc;
1982 1983
}

1984
static int em_pusha(struct x86_emulate_ctxt *ctxt)
1985
{
1986
	unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
1987 1988
	int rc = X86EMUL_CONTINUE;
	int reg = VCPU_REGS_RAX;
1989

1990 1991
	while (reg <= VCPU_REGS_RDI) {
		(reg == VCPU_REGS_RSP) ?
1992
		(ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
1993

1994
		rc = em_push(ctxt);
1995 1996
		if (rc != X86EMUL_CONTINUE)
			return rc;
1997

1998
		++reg;
1999 2000
	}

2001
	return rc;
2002 2003
}

2004 2005
static int em_pushf(struct x86_emulate_ctxt *ctxt)
{
2006
	ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM;
2007 2008 2009
	return em_push(ctxt);
}

2010
static int em_popa(struct x86_emulate_ctxt *ctxt)
2011
{
2012 2013
	int rc = X86EMUL_CONTINUE;
	int reg = VCPU_REGS_RDI;
2014
	u32 val;
2015

2016 2017
	while (reg >= VCPU_REGS_RAX) {
		if (reg == VCPU_REGS_RSP) {
2018
			rsp_increment(ctxt, ctxt->op_bytes);
2019 2020
			--reg;
		}
2021

2022
		rc = emulate_pop(ctxt, &val, ctxt->op_bytes);
2023 2024
		if (rc != X86EMUL_CONTINUE)
			break;
2025
		assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes);
2026
		--reg;
2027
	}
2028
	return rc;
2029 2030
}

2031
static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
2032
{
2033
	const struct x86_emulate_ops *ops = ctxt->ops;
2034
	int rc;
2035 2036 2037 2038 2039 2040
	struct desc_ptr dt;
	gva_t cs_addr;
	gva_t eip_addr;
	u16 cs, eip;

	/* TODO: Add limit checks */
2041
	ctxt->src.val = ctxt->eflags;
2042
	rc = em_push(ctxt);
2043 2044
	if (rc != X86EMUL_CONTINUE)
		return rc;
2045

2046
	ctxt->eflags &= ~(X86_EFLAGS_IF | X86_EFLAGS_TF | X86_EFLAGS_AC);
2047

2048
	ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
2049
	rc = em_push(ctxt);
2050 2051
	if (rc != X86EMUL_CONTINUE)
		return rc;
2052

2053
	ctxt->src.val = ctxt->_eip;
2054
	rc = em_push(ctxt);
2055 2056 2057
	if (rc != X86EMUL_CONTINUE)
		return rc;

2058
	ops->get_idt(ctxt, &dt);
2059 2060 2061 2062

	eip_addr = dt.address + (irq << 2);
	cs_addr = dt.address + (irq << 2) + 2;

2063
	rc = linear_read_system(ctxt, cs_addr, &cs, 2);
2064 2065 2066
	if (rc != X86EMUL_CONTINUE)
		return rc;

2067
	rc = linear_read_system(ctxt, eip_addr, &eip, 2);
2068 2069 2070
	if (rc != X86EMUL_CONTINUE)
		return rc;

2071
	rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
2072 2073 2074
	if (rc != X86EMUL_CONTINUE)
		return rc;

2075
	ctxt->_eip = eip;
2076 2077 2078 2079

	return rc;
}

2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090
int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
{
	int rc;

	invalidate_registers(ctxt);
	rc = __emulate_int_real(ctxt, irq);
	if (rc == X86EMUL_CONTINUE)
		writeback_registers(ctxt);
	return rc;
}

2091
static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
2092 2093 2094
{
	switch(ctxt->mode) {
	case X86EMUL_MODE_REAL:
2095
		return __emulate_int_real(ctxt, irq);
2096 2097 2098 2099 2100 2101 2102 2103 2104 2105
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT64:
	default:
		/* Protected mode interrupts unimplemented yet */
		return X86EMUL_UNHANDLEABLE;
	}
}

2106
static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
2107
{
2108 2109 2110 2111
	int rc = X86EMUL_CONTINUE;
	unsigned long temp_eip = 0;
	unsigned long temp_eflags = 0;
	unsigned long cs = 0;
2112 2113 2114 2115 2116
	unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
			     X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_TF |
			     X86_EFLAGS_IF | X86_EFLAGS_DF | X86_EFLAGS_OF |
			     X86_EFLAGS_IOPL | X86_EFLAGS_NT | X86_EFLAGS_RF |
			     X86_EFLAGS_AC | X86_EFLAGS_ID |
W
Wanpeng Li 已提交
2117
			     X86_EFLAGS_FIXED;
2118 2119
	unsigned long vm86_mask = X86_EFLAGS_VM | X86_EFLAGS_VIF |
				  X86_EFLAGS_VIP;
2120

2121
	/* TODO: Add stack limit check */
2122

2123
	rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
2124

2125 2126
	if (rc != X86EMUL_CONTINUE)
		return rc;
2127

2128 2129
	if (temp_eip & ~0xffff)
		return emulate_gp(ctxt, 0);
2130

2131
	rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
2132

2133 2134
	if (rc != X86EMUL_CONTINUE)
		return rc;
2135

2136
	rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
2137

2138 2139
	if (rc != X86EMUL_CONTINUE)
		return rc;
2140

2141
	rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
2142

2143 2144
	if (rc != X86EMUL_CONTINUE)
		return rc;
2145

2146
	ctxt->_eip = temp_eip;
2147

2148
	if (ctxt->op_bytes == 4)
2149
		ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
2150
	else if (ctxt->op_bytes == 2) {
2151 2152
		ctxt->eflags &= ~0xffff;
		ctxt->eflags |= temp_eflags;
2153
	}
2154 2155

	ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
W
Wanpeng Li 已提交
2156
	ctxt->eflags |= X86_EFLAGS_FIXED;
2157
	ctxt->ops->set_nmi_mask(ctxt, false);
2158 2159

	return rc;
2160 2161
}

2162
static int em_iret(struct x86_emulate_ctxt *ctxt)
2163
{
2164 2165
	switch(ctxt->mode) {
	case X86EMUL_MODE_REAL:
2166
		return emulate_iret_real(ctxt);
2167 2168 2169 2170
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT64:
2171
	default:
2172 2173
		/* iret from protected mode unimplemented yet */
		return X86EMUL_UNHANDLEABLE;
2174 2175 2176
	}
}

2177 2178 2179
static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
{
	int rc;
2180 2181
	unsigned short sel;
	struct desc_struct new_desc;
2182 2183
	u8 cpl = ctxt->ops->cpl(ctxt);

2184
	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2185

2186 2187
	rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
				       X86_TRANSFER_CALL_JMP,
2188
				       &new_desc);
2189 2190 2191
	if (rc != X86EMUL_CONTINUE)
		return rc;

2192
	rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
2193 2194 2195 2196
	/* Error handling is not implemented. */
	if (rc != X86EMUL_CONTINUE)
		return X86EMUL_UNHANDLEABLE;

2197
	return rc;
2198 2199
}

2200
static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
2201
{
2202 2203
	return assign_eip_near(ctxt, ctxt->src.val);
}
2204

2205 2206 2207 2208 2209 2210 2211 2212 2213 2214 2215
static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
{
	int rc;
	long int old_eip;

	old_eip = ctxt->_eip;
	rc = assign_eip_near(ctxt, ctxt->src.val);
	if (rc != X86EMUL_CONTINUE)
		return rc;
	ctxt->src.val = old_eip;
	rc = em_push(ctxt);
2216
	return rc;
2217 2218
}

2219
static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
2220
{
2221
	u64 old = ctxt->dst.orig_val64;
2222

2223 2224 2225
	if (ctxt->dst.bytes == 16)
		return X86EMUL_UNHANDLEABLE;

2226 2227 2228 2229
	if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
	    ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
		*reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
		*reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
2230
		ctxt->eflags &= ~X86_EFLAGS_ZF;
2231
	} else {
2232 2233
		ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
			(u32) reg_read(ctxt, VCPU_REGS_RBX);
2234

2235
		ctxt->eflags |= X86_EFLAGS_ZF;
2236
	}
2237
	return X86EMUL_CONTINUE;
2238 2239
}

2240 2241
static int em_ret(struct x86_emulate_ctxt *ctxt)
{
2242 2243 2244 2245 2246 2247 2248 2249
	int rc;
	unsigned long eip;

	rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	return assign_eip_near(ctxt, eip);
2250 2251
}

2252
static int em_ret_far(struct x86_emulate_ctxt *ctxt)
2253 2254
{
	int rc;
2255
	unsigned long eip, cs;
2256
	int cpl = ctxt->ops->cpl(ctxt);
2257
	struct desc_struct new_desc;
2258

2259
	rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2260
	if (rc != X86EMUL_CONTINUE)
2261
		return rc;
2262
	rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
2263
	if (rc != X86EMUL_CONTINUE)
2264
		return rc;
2265 2266 2267
	/* Outer-privilege level return is not implemented */
	if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
		return X86EMUL_UNHANDLEABLE;
2268 2269
	rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl,
				       X86_TRANSFER_RET,
2270 2271 2272
				       &new_desc);
	if (rc != X86EMUL_CONTINUE)
		return rc;
2273
	rc = assign_eip_far(ctxt, eip, &new_desc);
2274 2275 2276 2277
	/* Error handling is not implemented. */
	if (rc != X86EMUL_CONTINUE)
		return X86EMUL_UNHANDLEABLE;

2278 2279 2280
	return rc;
}

2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291
static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
{
        int rc;

        rc = em_ret_far(ctxt);
        if (rc != X86EMUL_CONTINUE)
                return rc;
        rsp_increment(ctxt, ctxt->src.val);
        return X86EMUL_CONTINUE;
}

2292 2293 2294
static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
{
	/* Save real source value, then compare EAX against destination. */
2295 2296
	ctxt->dst.orig_val = ctxt->dst.val;
	ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
2297
	ctxt->src.orig_val = ctxt->src.val;
2298
	ctxt->src.val = ctxt->dst.orig_val;
2299
	fastop(ctxt, em_cmp);
2300

2301
	if (ctxt->eflags & X86_EFLAGS_ZF) {
2302 2303
		/* Success: write back to memory; no update of EAX */
		ctxt->src.type = OP_NONE;
2304 2305 2306
		ctxt->dst.val = ctxt->src.orig_val;
	} else {
		/* Failure: write the value we saw to EAX. */
2307 2308 2309 2310
		ctxt->src.type = OP_REG;
		ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
		ctxt->src.val = ctxt->dst.orig_val;
		/* Create write-cycle to dest by writing the same value */
2311
		ctxt->dst.val = ctxt->dst.orig_val;
2312 2313 2314 2315
	}
	return X86EMUL_CONTINUE;
}

2316
static int em_lseg(struct x86_emulate_ctxt *ctxt)
2317
{
2318
	int seg = ctxt->src2.val;
2319 2320 2321
	unsigned short sel;
	int rc;

2322
	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2323

2324
	rc = load_segment_descriptor(ctxt, sel, seg);
2325 2326 2327
	if (rc != X86EMUL_CONTINUE)
		return rc;

2328
	ctxt->dst.val = ctxt->src.val;
2329 2330 2331
	return rc;
}

2332 2333 2334 2335 2336 2337
static int emulator_has_longmode(struct x86_emulate_ctxt *ctxt)
{
	u32 eax, ebx, ecx, edx;

	eax = 0x80000001;
	ecx = 0;
2338
	ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
2339 2340 2341 2342 2343 2344
	return edx & bit(X86_FEATURE_LM);
}

#define GET_SMSTATE(type, smbase, offset)				  \
	({								  \
	 type __val;							  \
2345 2346
	 int r = ctxt->ops->read_phys(ctxt, smbase + offset, &__val,      \
				      sizeof(__val));			  \
2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403
	 if (r != X86EMUL_CONTINUE)					  \
		 return X86EMUL_UNHANDLEABLE;				  \
	 __val;								  \
	})

static void rsm_set_desc_flags(struct desc_struct *desc, u32 flags)
{
	desc->g    = (flags >> 23) & 1;
	desc->d    = (flags >> 22) & 1;
	desc->l    = (flags >> 21) & 1;
	desc->avl  = (flags >> 20) & 1;
	desc->p    = (flags >> 15) & 1;
	desc->dpl  = (flags >> 13) & 3;
	desc->s    = (flags >> 12) & 1;
	desc->type = (flags >>  8) & 15;
}

static int rsm_load_seg_32(struct x86_emulate_ctxt *ctxt, u64 smbase, int n)
{
	struct desc_struct desc;
	int offset;
	u16 selector;

	selector = GET_SMSTATE(u32, smbase, 0x7fa8 + n * 4);

	if (n < 3)
		offset = 0x7f84 + n * 12;
	else
		offset = 0x7f2c + (n - 3) * 12;

	set_desc_base(&desc,      GET_SMSTATE(u32, smbase, offset + 8));
	set_desc_limit(&desc,     GET_SMSTATE(u32, smbase, offset + 4));
	rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, offset));
	ctxt->ops->set_segment(ctxt, selector, &desc, 0, n);
	return X86EMUL_CONTINUE;
}

static int rsm_load_seg_64(struct x86_emulate_ctxt *ctxt, u64 smbase, int n)
{
	struct desc_struct desc;
	int offset;
	u16 selector;
	u32 base3;

	offset = 0x7e00 + n * 16;

	selector =                GET_SMSTATE(u16, smbase, offset);
	rsm_set_desc_flags(&desc, GET_SMSTATE(u16, smbase, offset + 2) << 8);
	set_desc_limit(&desc,     GET_SMSTATE(u32, smbase, offset + 4));
	set_desc_base(&desc,      GET_SMSTATE(u32, smbase, offset + 8));
	base3 =                   GET_SMSTATE(u32, smbase, offset + 12);

	ctxt->ops->set_segment(ctxt, selector, &desc, base3, n);
	return X86EMUL_CONTINUE;
}

static int rsm_enter_protected_mode(struct x86_emulate_ctxt *ctxt,
2404
				    u64 cr0, u64 cr3, u64 cr4)
2405 2406
{
	int bad;
2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418
	u64 pcid;

	/* In order to later set CR4.PCIDE, CR3[11:0] must be zero.  */
	pcid = 0;
	if (cr4 & X86_CR4_PCIDE) {
		pcid = cr3 & 0xfff;
		cr3 &= ~0xfff;
	}

	bad = ctxt->ops->set_cr(ctxt, 3, cr3);
	if (bad)
		return X86EMUL_UNHANDLEABLE;
2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436

	/*
	 * First enable PAE, long mode needs it before CR0.PG = 1 is set.
	 * Then enable protected mode.	However, PCID cannot be enabled
	 * if EFER.LMA=0, so set it separately.
	 */
	bad = ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE);
	if (bad)
		return X86EMUL_UNHANDLEABLE;

	bad = ctxt->ops->set_cr(ctxt, 0, cr0);
	if (bad)
		return X86EMUL_UNHANDLEABLE;

	if (cr4 & X86_CR4_PCIDE) {
		bad = ctxt->ops->set_cr(ctxt, 4, cr4);
		if (bad)
			return X86EMUL_UNHANDLEABLE;
2437 2438 2439 2440 2441 2442
		if (pcid) {
			bad = ctxt->ops->set_cr(ctxt, 3, cr3 | pcid);
			if (bad)
				return X86EMUL_UNHANDLEABLE;
		}

2443 2444 2445 2446 2447 2448 2449 2450 2451 2452
	}

	return X86EMUL_CONTINUE;
}

static int rsm_load_state_32(struct x86_emulate_ctxt *ctxt, u64 smbase)
{
	struct desc_struct desc;
	struct desc_ptr dt;
	u16 selector;
2453
	u32 val, cr0, cr3, cr4;
2454 2455 2456
	int i;

	cr0 =                      GET_SMSTATE(u32, smbase, 0x7ffc);
2457
	cr3 =                      GET_SMSTATE(u32, smbase, 0x7ff8);
2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498
	ctxt->eflags =             GET_SMSTATE(u32, smbase, 0x7ff4) | X86_EFLAGS_FIXED;
	ctxt->_eip =               GET_SMSTATE(u32, smbase, 0x7ff0);

	for (i = 0; i < 8; i++)
		*reg_write(ctxt, i) = GET_SMSTATE(u32, smbase, 0x7fd0 + i * 4);

	val = GET_SMSTATE(u32, smbase, 0x7fcc);
	ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1);
	val = GET_SMSTATE(u32, smbase, 0x7fc8);
	ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1);

	selector =                 GET_SMSTATE(u32, smbase, 0x7fc4);
	set_desc_base(&desc,       GET_SMSTATE(u32, smbase, 0x7f64));
	set_desc_limit(&desc,      GET_SMSTATE(u32, smbase, 0x7f60));
	rsm_set_desc_flags(&desc,  GET_SMSTATE(u32, smbase, 0x7f5c));
	ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_TR);

	selector =                 GET_SMSTATE(u32, smbase, 0x7fc0);
	set_desc_base(&desc,       GET_SMSTATE(u32, smbase, 0x7f80));
	set_desc_limit(&desc,      GET_SMSTATE(u32, smbase, 0x7f7c));
	rsm_set_desc_flags(&desc,  GET_SMSTATE(u32, smbase, 0x7f78));
	ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_LDTR);

	dt.address =               GET_SMSTATE(u32, smbase, 0x7f74);
	dt.size =                  GET_SMSTATE(u32, smbase, 0x7f70);
	ctxt->ops->set_gdt(ctxt, &dt);

	dt.address =               GET_SMSTATE(u32, smbase, 0x7f58);
	dt.size =                  GET_SMSTATE(u32, smbase, 0x7f54);
	ctxt->ops->set_idt(ctxt, &dt);

	for (i = 0; i < 6; i++) {
		int r = rsm_load_seg_32(ctxt, smbase, i);
		if (r != X86EMUL_CONTINUE)
			return r;
	}

	cr4 = GET_SMSTATE(u32, smbase, 0x7f14);

	ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smbase, 0x7ef8));

2499
	return rsm_enter_protected_mode(ctxt, cr0, cr3, cr4);
2500 2501 2502 2503 2504 2505
}

static int rsm_load_state_64(struct x86_emulate_ctxt *ctxt, u64 smbase)
{
	struct desc_struct desc;
	struct desc_ptr dt;
2506
	u64 val, cr0, cr3, cr4;
2507 2508
	u32 base3;
	u16 selector;
2509
	int i, r;
2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522

	for (i = 0; i < 16; i++)
		*reg_write(ctxt, i) = GET_SMSTATE(u64, smbase, 0x7ff8 - i * 8);

	ctxt->_eip   = GET_SMSTATE(u64, smbase, 0x7f78);
	ctxt->eflags = GET_SMSTATE(u32, smbase, 0x7f70) | X86_EFLAGS_FIXED;

	val = GET_SMSTATE(u32, smbase, 0x7f68);
	ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1);
	val = GET_SMSTATE(u32, smbase, 0x7f60);
	ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1);

	cr0 =                       GET_SMSTATE(u64, smbase, 0x7f58);
2523
	cr3 =                       GET_SMSTATE(u64, smbase, 0x7f50);
2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550
	cr4 =                       GET_SMSTATE(u64, smbase, 0x7f48);
	ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smbase, 0x7f00));
	val =                       GET_SMSTATE(u64, smbase, 0x7ed0);
	ctxt->ops->set_msr(ctxt, MSR_EFER, val & ~EFER_LMA);

	selector =                  GET_SMSTATE(u32, smbase, 0x7e90);
	rsm_set_desc_flags(&desc,   GET_SMSTATE(u32, smbase, 0x7e92) << 8);
	set_desc_limit(&desc,       GET_SMSTATE(u32, smbase, 0x7e94));
	set_desc_base(&desc,        GET_SMSTATE(u32, smbase, 0x7e98));
	base3 =                     GET_SMSTATE(u32, smbase, 0x7e9c);
	ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_TR);

	dt.size =                   GET_SMSTATE(u32, smbase, 0x7e84);
	dt.address =                GET_SMSTATE(u64, smbase, 0x7e88);
	ctxt->ops->set_idt(ctxt, &dt);

	selector =                  GET_SMSTATE(u32, smbase, 0x7e70);
	rsm_set_desc_flags(&desc,   GET_SMSTATE(u32, smbase, 0x7e72) << 8);
	set_desc_limit(&desc,       GET_SMSTATE(u32, smbase, 0x7e74));
	set_desc_base(&desc,        GET_SMSTATE(u32, smbase, 0x7e78));
	base3 =                     GET_SMSTATE(u32, smbase, 0x7e7c);
	ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_LDTR);

	dt.size =                   GET_SMSTATE(u32, smbase, 0x7e64);
	dt.address =                GET_SMSTATE(u64, smbase, 0x7e68);
	ctxt->ops->set_gdt(ctxt, &dt);

2551
	r = rsm_enter_protected_mode(ctxt, cr0, cr3, cr4);
2552 2553 2554
	if (r != X86EMUL_CONTINUE)
		return r;

2555
	for (i = 0; i < 6; i++) {
2556
		r = rsm_load_seg_64(ctxt, smbase, i);
2557 2558 2559 2560
		if (r != X86EMUL_CONTINUE)
			return r;
	}

2561
	return X86EMUL_CONTINUE;
2562 2563
}

P
Paolo Bonzini 已提交
2564 2565
static int em_rsm(struct x86_emulate_ctxt *ctxt)
{
2566 2567 2568 2569
	unsigned long cr0, cr4, efer;
	u64 smbase;
	int ret;

2570
	if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_MASK) == 0)
P
Paolo Bonzini 已提交
2571 2572
		return emulate_ud(ctxt);

2573 2574
	/*
	 * Get back to real mode, to prepare a safe state in which to load
2575 2576
	 * CR0/CR3/CR4/EFER.  It's all a bit more complicated if the vCPU
	 * supports long mode.
2577
	 */
2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595
	cr4 = ctxt->ops->get_cr(ctxt, 4);
	if (emulator_has_longmode(ctxt)) {
		struct desc_struct cs_desc;

		/* Zero CR4.PCIDE before CR0.PG.  */
		if (cr4 & X86_CR4_PCIDE) {
			ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE);
			cr4 &= ~X86_CR4_PCIDE;
		}

		/* A 32-bit code segment is required to clear EFER.LMA.  */
		memset(&cs_desc, 0, sizeof(cs_desc));
		cs_desc.type = 0xb;
		cs_desc.s = cs_desc.g = cs_desc.p = 1;
		ctxt->ops->set_segment(ctxt, 0, &cs_desc, 0, VCPU_SREG_CS);
	}

	/* For the 64-bit case, this will clear EFER.LMA.  */
2596 2597 2598
	cr0 = ctxt->ops->get_cr(ctxt, 0);
	if (cr0 & X86_CR0_PE)
		ctxt->ops->set_cr(ctxt, 0, cr0 & ~(X86_CR0_PG | X86_CR0_PE));
2599 2600

	/* Now clear CR4.PAE (which must be done before clearing EFER.LME).  */
2601 2602
	if (cr4 & X86_CR4_PAE)
		ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PAE);
2603 2604

	/* And finally go back to 32-bit mode.  */
2605 2606 2607 2608
	efer = 0;
	ctxt->ops->set_msr(ctxt, MSR_EFER, efer);

	smbase = ctxt->ops->get_smbase(ctxt);
2609 2610 2611 2612 2613 2614 2615 2616 2617

	/*
	 * Give pre_leave_smm() a chance to make ISA-specific changes to the
	 * vCPU state (e.g. enter guest mode) before loading state from the SMM
	 * state-save area.
	 */
	if (ctxt->ops->pre_leave_smm(ctxt, smbase))
		return X86EMUL_UNHANDLEABLE;

2618 2619 2620 2621 2622 2623 2624 2625 2626 2627
	if (emulator_has_longmode(ctxt))
		ret = rsm_load_state_64(ctxt, smbase + 0x8000);
	else
		ret = rsm_load_state_32(ctxt, smbase + 0x8000);

	if (ret != X86EMUL_CONTINUE) {
		/* FIXME: should triple fault */
		return X86EMUL_UNHANDLEABLE;
	}

2628
	if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_INSIDE_NMI_MASK) == 0)
2629 2630
		ctxt->ops->set_nmi_mask(ctxt, false);

2631 2632
	ctxt->ops->set_hflags(ctxt, ctxt->ops->get_hflags(ctxt) &
		~(X86EMUL_SMM_INSIDE_NMI_MASK | X86EMUL_SMM_MASK));
2633
	return X86EMUL_CONTINUE;
P
Paolo Bonzini 已提交
2634 2635
}

2636
static void
2637
setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
2638
			struct desc_struct *cs, struct desc_struct *ss)
2639 2640
{
	cs->l = 0;		/* will be adjusted later */
2641
	set_desc_base(cs, 0);	/* flat segment */
2642
	cs->g = 1;		/* 4kb granularity */
2643
	set_desc_limit(cs, 0xfffff);	/* 4GB limit */
2644 2645 2646
	cs->type = 0x0b;	/* Read, Execute, Accessed */
	cs->s = 1;
	cs->dpl = 0;		/* will be adjusted later */
2647 2648
	cs->p = 1;
	cs->d = 1;
2649
	cs->avl = 0;
2650

2651 2652
	set_desc_base(ss, 0);	/* flat segment */
	set_desc_limit(ss, 0xfffff);	/* 4GB limit */
2653 2654 2655
	ss->g = 1;		/* 4kb granularity */
	ss->s = 1;
	ss->type = 0x03;	/* Read/Write, Accessed */
2656
	ss->d = 1;		/* 32bit stack segment */
2657
	ss->dpl = 0;
2658
	ss->p = 1;
2659 2660
	ss->l = 0;
	ss->avl = 0;
2661 2662
}

2663 2664 2665 2666 2667
static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
{
	u32 eax, ebx, ecx, edx;

	eax = ecx = 0;
2668
	ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
2669
	return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
2670 2671 2672 2673
		&& ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
		&& edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
}

2674 2675
static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
{
2676
	const struct x86_emulate_ops *ops = ctxt->ops;
2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687
	u32 eax, ebx, ecx, edx;

	/*
	 * syscall should always be enabled in longmode - so only become
	 * vendor specific (cpuid) if other modes are active...
	 */
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		return true;

	eax = 0x00000000;
	ecx = 0x00000000;
2688
	ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712
	/*
	 * Intel ("GenuineIntel")
	 * remark: Intel CPUs only support "syscall" in 64bit
	 * longmode. Also an 64bit guest with a
	 * 32bit compat-app running will #UD !! While this
	 * behaviour can be fixed (by emulating) into AMD
	 * response - CPUs of AMD can't behave like Intel.
	 */
	if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
	    ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
	    edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
		return false;

	/* AMD ("AuthenticAMD") */
	if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
	    ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
	    edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
		return true;

	/* AMD ("AMDisbetter!") */
	if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
	    ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
	    edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
		return true;
2713 2714 2715 2716 2717

	/* default: (not Intel, not AMD), apply Intel's stricter rules... */
	return false;
}

2718
static int em_syscall(struct x86_emulate_ctxt *ctxt)
2719
{
2720
	const struct x86_emulate_ops *ops = ctxt->ops;
2721
	struct desc_struct cs, ss;
2722
	u64 msr_data;
2723
	u16 cs_sel, ss_sel;
2724
	u64 efer = 0;
2725 2726

	/* syscall is not available in real mode */
2727
	if (ctxt->mode == X86EMUL_MODE_REAL ||
2728 2729
	    ctxt->mode == X86EMUL_MODE_VM86)
		return emulate_ud(ctxt);
2730

2731 2732 2733
	if (!(em_syscall_is_enabled(ctxt)))
		return emulate_ud(ctxt);

2734
	ops->get_msr(ctxt, MSR_EFER, &efer);
2735
	setup_syscalls_segments(ctxt, &cs, &ss);
2736

2737 2738 2739
	if (!(efer & EFER_SCE))
		return emulate_ud(ctxt);

2740
	ops->get_msr(ctxt, MSR_STAR, &msr_data);
2741
	msr_data >>= 32;
2742 2743
	cs_sel = (u16)(msr_data & 0xfffc);
	ss_sel = (u16)(msr_data + 8);
2744

2745
	if (efer & EFER_LMA) {
2746
		cs.d = 0;
2747 2748
		cs.l = 1;
	}
2749 2750
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2751

2752
	*reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
2753
	if (efer & EFER_LMA) {
2754
#ifdef CONFIG_X86_64
2755
		*reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
2756

2757
		ops->get_msr(ctxt,
2758 2759
			     ctxt->mode == X86EMUL_MODE_PROT64 ?
			     MSR_LSTAR : MSR_CSTAR, &msr_data);
2760
		ctxt->_eip = msr_data;
2761

2762
		ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
2763
		ctxt->eflags &= ~msr_data;
W
Wanpeng Li 已提交
2764
		ctxt->eflags |= X86_EFLAGS_FIXED;
2765 2766 2767
#endif
	} else {
		/* legacy mode */
2768
		ops->get_msr(ctxt, MSR_STAR, &msr_data);
2769
		ctxt->_eip = (u32)msr_data;
2770

2771
		ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
2772 2773
	}

2774
	ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
2775
	return X86EMUL_CONTINUE;
2776 2777
}

2778
static int em_sysenter(struct x86_emulate_ctxt *ctxt)
2779
{
2780
	const struct x86_emulate_ops *ops = ctxt->ops;
2781
	struct desc_struct cs, ss;
2782
	u64 msr_data;
2783
	u16 cs_sel, ss_sel;
2784
	u64 efer = 0;
2785

2786
	ops->get_msr(ctxt, MSR_EFER, &efer);
2787
	/* inject #GP if in real mode */
2788 2789
	if (ctxt->mode == X86EMUL_MODE_REAL)
		return emulate_gp(ctxt, 0);
2790

2791 2792 2793 2794
	/*
	 * Not recognized on AMD in compat mode (but is recognized in legacy
	 * mode).
	 */
2795
	if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA)
2796 2797 2798
	    && !vendor_intel(ctxt))
		return emulate_ud(ctxt);

2799
	/* sysenter/sysexit have not been tested in 64bit mode. */
2800
	if (ctxt->mode == X86EMUL_MODE_PROT64)
2801
		return X86EMUL_UNHANDLEABLE;
2802

2803
	setup_syscalls_segments(ctxt, &cs, &ss);
2804

2805
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2806 2807
	if ((msr_data & 0xfffc) == 0x0)
		return emulate_gp(ctxt, 0);
2808

2809
	ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
2810
	cs_sel = (u16)msr_data & ~SEGMENT_RPL_MASK;
2811
	ss_sel = cs_sel + 8;
2812
	if (efer & EFER_LMA) {
2813
		cs.d = 0;
2814 2815 2816
		cs.l = 1;
	}

2817 2818
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2819

2820
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
2821
	ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data;
2822

2823
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
2824 2825
	*reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data :
							      (u32)msr_data;
2826

2827
	return X86EMUL_CONTINUE;
2828 2829
}

2830
static int em_sysexit(struct x86_emulate_ctxt *ctxt)
2831
{
2832
	const struct x86_emulate_ops *ops = ctxt->ops;
2833
	struct desc_struct cs, ss;
2834
	u64 msr_data, rcx, rdx;
2835
	int usermode;
X
Xiao Guangrong 已提交
2836
	u16 cs_sel = 0, ss_sel = 0;
2837

2838 2839
	/* inject #GP if in real mode or Virtual 8086 mode */
	if (ctxt->mode == X86EMUL_MODE_REAL ||
2840 2841
	    ctxt->mode == X86EMUL_MODE_VM86)
		return emulate_gp(ctxt, 0);
2842

2843
	setup_syscalls_segments(ctxt, &cs, &ss);
2844

2845
	if ((ctxt->rex_prefix & 0x8) != 0x0)
2846 2847 2848 2849
		usermode = X86EMUL_MODE_PROT64;
	else
		usermode = X86EMUL_MODE_PROT32;

2850 2851 2852
	rcx = reg_read(ctxt, VCPU_REGS_RCX);
	rdx = reg_read(ctxt, VCPU_REGS_RDX);

2853 2854
	cs.dpl = 3;
	ss.dpl = 3;
2855
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2856 2857
	switch (usermode) {
	case X86EMUL_MODE_PROT32:
2858
		cs_sel = (u16)(msr_data + 16);
2859 2860
		if ((msr_data & 0xfffc) == 0x0)
			return emulate_gp(ctxt, 0);
2861
		ss_sel = (u16)(msr_data + 24);
2862 2863
		rcx = (u32)rcx;
		rdx = (u32)rdx;
2864 2865
		break;
	case X86EMUL_MODE_PROT64:
2866
		cs_sel = (u16)(msr_data + 32);
2867 2868
		if (msr_data == 0x0)
			return emulate_gp(ctxt, 0);
2869 2870
		ss_sel = cs_sel + 8;
		cs.d = 0;
2871
		cs.l = 1;
2872 2873
		if (emul_is_noncanonical_address(rcx, ctxt) ||
		    emul_is_noncanonical_address(rdx, ctxt))
2874
			return emulate_gp(ctxt, 0);
2875 2876
		break;
	}
2877 2878
	cs_sel |= SEGMENT_RPL_MASK;
	ss_sel |= SEGMENT_RPL_MASK;
2879

2880 2881
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2882

2883 2884
	ctxt->_eip = rdx;
	*reg_write(ctxt, VCPU_REGS_RSP) = rcx;
2885

2886
	return X86EMUL_CONTINUE;
2887 2888
}

2889
static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
2890 2891 2892 2893 2894 2895
{
	int iopl;
	if (ctxt->mode == X86EMUL_MODE_REAL)
		return false;
	if (ctxt->mode == X86EMUL_MODE_VM86)
		return true;
2896
	iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
2897
	return ctxt->ops->cpl(ctxt) > iopl;
2898 2899
}

2900 2901 2902
#define VMWARE_PORT_VMPORT	(0x5658)
#define VMWARE_PORT_VMRPC	(0x5659)

2903 2904 2905
static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
					    u16 port, u16 len)
{
2906
	const struct x86_emulate_ops *ops = ctxt->ops;
2907
	struct desc_struct tr_seg;
2908
	u32 base3;
2909
	int r;
2910
	u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
2911
	unsigned mask = (1 << len) - 1;
2912
	unsigned long base;
2913

2914 2915 2916 2917 2918 2919 2920 2921
	/*
	 * VMware allows access to these ports even if denied
	 * by TSS I/O permission bitmap. Mimic behavior.
	 */
	if (enable_vmware_backdoor &&
	    ((port == VMWARE_PORT_VMPORT) || (port == VMWARE_PORT_VMRPC)))
		return true;

2922
	ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
2923
	if (!tr_seg.p)
2924
		return false;
2925
	if (desc_limit_scaled(&tr_seg) < 103)
2926
		return false;
2927 2928 2929 2930
	base = get_desc_base(&tr_seg);
#ifdef CONFIG_X86_64
	base |= ((u64)base3) << 32;
#endif
2931
	r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
2932 2933
	if (r != X86EMUL_CONTINUE)
		return false;
2934
	if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
2935
		return false;
2936
	r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
2937 2938 2939 2940 2941 2942 2943 2944 2945 2946
	if (r != X86EMUL_CONTINUE)
		return false;
	if ((perm >> bit_idx) & mask)
		return false;
	return true;
}

static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
				 u16 port, u16 len)
{
2947 2948 2949
	if (ctxt->perm_ok)
		return true;

2950 2951
	if (emulator_bad_iopl(ctxt))
		if (!emulator_io_port_access_allowed(ctxt, port, len))
2952
			return false;
2953 2954 2955

	ctxt->perm_ok = true;

2956 2957 2958
	return true;
}

2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982
static void string_registers_quirk(struct x86_emulate_ctxt *ctxt)
{
	/*
	 * Intel CPUs mask the counter and pointers in quite strange
	 * manner when ECX is zero due to REP-string optimizations.
	 */
#ifdef CONFIG_X86_64
	if (ctxt->ad_bytes != 4 || !vendor_intel(ctxt))
		return;

	*reg_write(ctxt, VCPU_REGS_RCX) = 0;

	switch (ctxt->b) {
	case 0xa4:	/* movsb */
	case 0xa5:	/* movsd/w */
		*reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1;
		/* fall through */
	case 0xaa:	/* stosb */
	case 0xab:	/* stosd/w */
		*reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1;
	}
#endif
}

2983 2984 2985
static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
				struct tss_segment_16 *tss)
{
2986
	tss->ip = ctxt->_eip;
2987
	tss->flag = ctxt->eflags;
2988 2989 2990 2991 2992 2993 2994 2995
	tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
	tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
	tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
	tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
	tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
	tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
	tss->si = reg_read(ctxt, VCPU_REGS_RSI);
	tss->di = reg_read(ctxt, VCPU_REGS_RDI);
2996

2997 2998 2999 3000 3001
	tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
	tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
	tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
	tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
	tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
3002 3003 3004 3005 3006 3007
}

static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
				 struct tss_segment_16 *tss)
{
	int ret;
3008
	u8 cpl;
3009

3010
	ctxt->_eip = tss->ip;
3011
	ctxt->eflags = tss->flag | 2;
3012 3013 3014 3015 3016 3017 3018 3019
	*reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
	*reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
	*reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
	*reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
	*reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
	*reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
	*reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
	*reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
3020 3021 3022 3023 3024

	/*
	 * SDM says that segment selectors are loaded before segment
	 * descriptors
	 */
3025 3026 3027 3028 3029
	set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
	set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
	set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
	set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
	set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
3030

3031 3032
	cpl = tss->cs & 3;

3033
	/*
G
Guo Chao 已提交
3034
	 * Now load segment descriptors. If fault happens at this stage
3035 3036
	 * it is handled in a context of new task
	 */
3037
	ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
3038
					X86_TRANSFER_TASK_SWITCH, NULL);
3039 3040
	if (ret != X86EMUL_CONTINUE)
		return ret;
3041
	ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3042
					X86_TRANSFER_TASK_SWITCH, NULL);
3043 3044
	if (ret != X86EMUL_CONTINUE)
		return ret;
3045
	ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3046
					X86_TRANSFER_TASK_SWITCH, NULL);
3047 3048
	if (ret != X86EMUL_CONTINUE)
		return ret;
3049
	ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3050
					X86_TRANSFER_TASK_SWITCH, NULL);
3051 3052
	if (ret != X86EMUL_CONTINUE)
		return ret;
3053
	ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3054
					X86_TRANSFER_TASK_SWITCH, NULL);
3055 3056 3057 3058 3059 3060 3061 3062 3063 3064 3065 3066
	if (ret != X86EMUL_CONTINUE)
		return ret;

	return X86EMUL_CONTINUE;
}

static int task_switch_16(struct x86_emulate_ctxt *ctxt,
			  u16 tss_selector, u16 old_tss_sel,
			  ulong old_tss_base, struct desc_struct *new_desc)
{
	struct tss_segment_16 tss_seg;
	int ret;
3067
	u32 new_tss_base = get_desc_base(new_desc);
3068

3069
	ret = linear_read_system(ctxt, old_tss_base, &tss_seg, sizeof tss_seg);
3070
	if (ret != X86EMUL_CONTINUE)
3071 3072
		return ret;

3073
	save_state_to_tss16(ctxt, &tss_seg);
3074

3075
	ret = linear_write_system(ctxt, old_tss_base, &tss_seg, sizeof tss_seg);
3076
	if (ret != X86EMUL_CONTINUE)
3077 3078
		return ret;

3079
	ret = linear_read_system(ctxt, new_tss_base, &tss_seg, sizeof tss_seg);
3080
	if (ret != X86EMUL_CONTINUE)
3081 3082 3083 3084 3085
		return ret;

	if (old_tss_sel != 0xffff) {
		tss_seg.prev_task_link = old_tss_sel;

3086 3087 3088
		ret = linear_write_system(ctxt, new_tss_base,
					  &tss_seg.prev_task_link,
					  sizeof tss_seg.prev_task_link);
3089
		if (ret != X86EMUL_CONTINUE)
3090 3091 3092
			return ret;
	}

3093
	return load_state_from_tss16(ctxt, &tss_seg);
3094 3095 3096 3097 3098
}

static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
				struct tss_segment_32 *tss)
{
3099
	/* CR3 and ldt selector are not saved intentionally */
3100
	tss->eip = ctxt->_eip;
3101
	tss->eflags = ctxt->eflags;
3102 3103 3104 3105 3106 3107 3108 3109
	tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
	tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
	tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
	tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
	tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
	tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
	tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
	tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
3110

3111 3112 3113 3114 3115 3116
	tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
	tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
	tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
	tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
	tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
	tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
3117 3118 3119 3120 3121 3122
}

static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
				 struct tss_segment_32 *tss)
{
	int ret;
3123
	u8 cpl;
3124

3125
	if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
3126
		return emulate_gp(ctxt, 0);
3127
	ctxt->_eip = tss->eip;
3128
	ctxt->eflags = tss->eflags | 2;
3129 3130

	/* General purpose registers */
3131 3132 3133 3134 3135 3136 3137 3138
	*reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
	*reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
	*reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
	*reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
	*reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
	*reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
	*reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
	*reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
3139 3140 3141

	/*
	 * SDM says that segment selectors are loaded before segment
3142 3143
	 * descriptors.  This is important because CPL checks will
	 * use CS.RPL.
3144
	 */
3145 3146 3147 3148 3149 3150 3151
	set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
	set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
	set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
	set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
	set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
	set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
	set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
3152

3153 3154 3155 3156 3157
	/*
	 * If we're switching between Protected Mode and VM86, we need to make
	 * sure to update the mode before loading the segment descriptors so
	 * that the selectors are interpreted correctly.
	 */
3158
	if (ctxt->eflags & X86_EFLAGS_VM) {
3159
		ctxt->mode = X86EMUL_MODE_VM86;
3160 3161
		cpl = 3;
	} else {
3162
		ctxt->mode = X86EMUL_MODE_PROT32;
3163 3164
		cpl = tss->cs & 3;
	}
3165

3166 3167 3168 3169
	/*
	 * Now load segment descriptors. If fault happenes at this stage
	 * it is handled in a context of new task
	 */
3170
	ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
3171
					cpl, X86_TRANSFER_TASK_SWITCH, NULL);
3172 3173
	if (ret != X86EMUL_CONTINUE)
		return ret;
3174
	ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3175
					X86_TRANSFER_TASK_SWITCH, NULL);
3176 3177
	if (ret != X86EMUL_CONTINUE)
		return ret;
3178
	ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3179
					X86_TRANSFER_TASK_SWITCH, NULL);
3180 3181
	if (ret != X86EMUL_CONTINUE)
		return ret;
3182
	ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3183
					X86_TRANSFER_TASK_SWITCH, NULL);
3184 3185
	if (ret != X86EMUL_CONTINUE)
		return ret;
3186
	ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3187
					X86_TRANSFER_TASK_SWITCH, NULL);
3188 3189
	if (ret != X86EMUL_CONTINUE)
		return ret;
3190
	ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
3191
					X86_TRANSFER_TASK_SWITCH, NULL);
3192 3193
	if (ret != X86EMUL_CONTINUE)
		return ret;
3194
	ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
3195
					X86_TRANSFER_TASK_SWITCH, NULL);
3196

3197
	return ret;
3198 3199 3200 3201 3202 3203 3204 3205
}

static int task_switch_32(struct x86_emulate_ctxt *ctxt,
			  u16 tss_selector, u16 old_tss_sel,
			  ulong old_tss_base, struct desc_struct *new_desc)
{
	struct tss_segment_32 tss_seg;
	int ret;
3206
	u32 new_tss_base = get_desc_base(new_desc);
3207 3208
	u32 eip_offset = offsetof(struct tss_segment_32, eip);
	u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
3209

3210
	ret = linear_read_system(ctxt, old_tss_base, &tss_seg, sizeof tss_seg);
3211
	if (ret != X86EMUL_CONTINUE)
3212 3213
		return ret;

3214
	save_state_to_tss32(ctxt, &tss_seg);
3215

3216
	/* Only GP registers and segment selectors are saved */
3217 3218
	ret = linear_write_system(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
				  ldt_sel_offset - eip_offset);
3219
	if (ret != X86EMUL_CONTINUE)
3220 3221
		return ret;

3222
	ret = linear_read_system(ctxt, new_tss_base, &tss_seg, sizeof tss_seg);
3223
	if (ret != X86EMUL_CONTINUE)
3224 3225 3226 3227 3228
		return ret;

	if (old_tss_sel != 0xffff) {
		tss_seg.prev_task_link = old_tss_sel;

3229 3230 3231
		ret = linear_write_system(ctxt, new_tss_base,
					  &tss_seg.prev_task_link,
					  sizeof tss_seg.prev_task_link);
3232
		if (ret != X86EMUL_CONTINUE)
3233 3234 3235
			return ret;
	}

3236
	return load_state_from_tss32(ctxt, &tss_seg);
3237 3238 3239
}

static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
3240
				   u16 tss_selector, int idt_index, int reason,
3241
				   bool has_error_code, u32 error_code)
3242
{
3243
	const struct x86_emulate_ops *ops = ctxt->ops;
3244 3245
	struct desc_struct curr_tss_desc, next_tss_desc;
	int ret;
3246
	u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
3247
	ulong old_tss_base =
3248
		ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
3249
	u32 desc_limit;
3250
	ulong desc_addr, dr7;
3251 3252 3253

	/* FIXME: old_tss_base == ~0 ? */

3254
	ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
3255 3256
	if (ret != X86EMUL_CONTINUE)
		return ret;
3257
	ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
3258 3259 3260 3261 3262
	if (ret != X86EMUL_CONTINUE)
		return ret;

	/* FIXME: check that next_tss_desc is tss */

3263 3264 3265 3266 3267
	/*
	 * Check privileges. The three cases are task switch caused by...
	 *
	 * 1. jmp/call/int to task gate: Check against DPL of the task gate
	 * 2. Exception/IRQ/iret: No check is performed
3268 3269
	 * 3. jmp/call to TSS/task-gate: No check is performed since the
	 *    hardware checks it before exiting.
3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285
	 */
	if (reason == TASK_SWITCH_GATE) {
		if (idt_index != -1) {
			/* Software interrupts */
			struct desc_struct task_gate_desc;
			int dpl;

			ret = read_interrupt_descriptor(ctxt, idt_index,
							&task_gate_desc);
			if (ret != X86EMUL_CONTINUE)
				return ret;

			dpl = task_gate_desc.dpl;
			if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
				return emulate_gp(ctxt, (idt_index << 3) | 0x2);
		}
3286 3287
	}

3288 3289 3290 3291
	desc_limit = desc_limit_scaled(&next_tss_desc);
	if (!next_tss_desc.p ||
	    ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
	     desc_limit < 0x2b)) {
3292
		return emulate_ts(ctxt, tss_selector & 0xfffc);
3293 3294 3295 3296
	}

	if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
		curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
3297
		write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
3298 3299 3300 3301 3302 3303
	}

	if (reason == TASK_SWITCH_IRET)
		ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;

	/* set back link to prev task only if NT bit is set in eflags
G
Guo Chao 已提交
3304
	   note that old_tss_sel is not used after this point */
3305 3306 3307 3308
	if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
		old_tss_sel = 0xffff;

	if (next_tss_desc.type & 8)
3309
		ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
3310 3311
				     old_tss_base, &next_tss_desc);
	else
3312
		ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
3313
				     old_tss_base, &next_tss_desc);
3314 3315
	if (ret != X86EMUL_CONTINUE)
		return ret;
3316 3317 3318 3319 3320 3321

	if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
		ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;

	if (reason != TASK_SWITCH_IRET) {
		next_tss_desc.type |= (1 << 1); /* set busy flag */
3322
		write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
3323 3324
	}

3325
	ops->set_cr(ctxt, 0,  ops->get_cr(ctxt, 0) | X86_CR0_TS);
3326
	ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
3327

3328
	if (has_error_code) {
3329 3330 3331
		ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
		ctxt->lock_prefix = 0;
		ctxt->src.val = (unsigned long) error_code;
3332
		ret = em_push(ctxt);
3333 3334
	}

3335 3336 3337
	ops->get_dr(ctxt, 7, &dr7);
	ops->set_dr(ctxt, 7, dr7 & ~(DR_LOCAL_ENABLE_MASK | DR_LOCAL_SLOWDOWN));

3338 3339 3340 3341
	return ret;
}

int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
3342
			 u16 tss_selector, int idt_index, int reason,
3343
			 bool has_error_code, u32 error_code)
3344 3345 3346
{
	int rc;

3347
	invalidate_registers(ctxt);
3348 3349
	ctxt->_eip = ctxt->eip;
	ctxt->dst.type = OP_NONE;
3350

3351
	rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
3352
				     has_error_code, error_code);
3353

3354
	if (rc == X86EMUL_CONTINUE) {
3355
		ctxt->eip = ctxt->_eip;
3356 3357
		writeback_registers(ctxt);
	}
3358

3359
	return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
3360 3361
}

3362 3363
static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
		struct operand *op)
3364
{
3365
	int df = (ctxt->eflags & X86_EFLAGS_DF) ? -op->count : op->count;
3366

3367 3368
	register_address_increment(ctxt, reg, df * op->bytes);
	op->addr.mem.ea = register_address(ctxt, reg);
3369 3370
}

3371 3372 3373 3374 3375 3376
static int em_das(struct x86_emulate_ctxt *ctxt)
{
	u8 al, old_al;
	bool af, cf, old_cf;

	cf = ctxt->eflags & X86_EFLAGS_CF;
3377
	al = ctxt->dst.val;
3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394

	old_al = al;
	old_cf = cf;
	cf = false;
	af = ctxt->eflags & X86_EFLAGS_AF;
	if ((al & 0x0f) > 9 || af) {
		al -= 6;
		cf = old_cf | (al >= 250);
		af = true;
	} else {
		af = false;
	}
	if (old_al > 0x99 || old_cf) {
		al -= 0x60;
		cf = true;
	}

3395
	ctxt->dst.val = al;
3396
	/* Set PF, ZF, SF */
3397 3398 3399
	ctxt->src.type = OP_IMM;
	ctxt->src.val = 0;
	ctxt->src.bytes = 1;
3400
	fastop(ctxt, em_or);
3401 3402 3403 3404 3405 3406 3407 3408
	ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
	if (cf)
		ctxt->eflags |= X86_EFLAGS_CF;
	if (af)
		ctxt->eflags |= X86_EFLAGS_AF;
	return X86EMUL_CONTINUE;
}

P
Paolo Bonzini 已提交
3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430
static int em_aam(struct x86_emulate_ctxt *ctxt)
{
	u8 al, ah;

	if (ctxt->src.val == 0)
		return emulate_de(ctxt);

	al = ctxt->dst.val & 0xff;
	ah = al / ctxt->src.val;
	al %= ctxt->src.val;

	ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);

	/* Set PF, ZF, SF */
	ctxt->src.type = OP_IMM;
	ctxt->src.val = 0;
	ctxt->src.bytes = 1;
	fastop(ctxt, em_or);

	return X86EMUL_CONTINUE;
}

3431 3432 3433 3434 3435 3436 3437 3438 3439
static int em_aad(struct x86_emulate_ctxt *ctxt)
{
	u8 al = ctxt->dst.val & 0xff;
	u8 ah = (ctxt->dst.val >> 8) & 0xff;

	al = (al + (ah * ctxt->src.val)) & 0xff;

	ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;

3440 3441 3442 3443 3444
	/* Set PF, ZF, SF */
	ctxt->src.type = OP_IMM;
	ctxt->src.val = 0;
	ctxt->src.bytes = 1;
	fastop(ctxt, em_or);
3445 3446 3447 3448

	return X86EMUL_CONTINUE;
}

3449 3450
static int em_call(struct x86_emulate_ctxt *ctxt)
{
3451
	int rc;
3452 3453 3454
	long rel = ctxt->src.val;

	ctxt->src.val = (unsigned long)ctxt->_eip;
3455 3456 3457
	rc = jmp_rel(ctxt, rel);
	if (rc != X86EMUL_CONTINUE)
		return rc;
3458 3459 3460
	return em_push(ctxt);
}

3461 3462 3463 3464 3465
static int em_call_far(struct x86_emulate_ctxt *ctxt)
{
	u16 sel, old_cs;
	ulong old_eip;
	int rc;
3466 3467 3468
	struct desc_struct old_desc, new_desc;
	const struct x86_emulate_ops *ops = ctxt->ops;
	int cpl = ctxt->ops->cpl(ctxt);
3469
	enum x86emul_mode prev_mode = ctxt->mode;
3470

3471
	old_eip = ctxt->_eip;
3472
	ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
3473

3474
	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
3475 3476
	rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
				       X86_TRANSFER_CALL_JMP, &new_desc);
3477
	if (rc != X86EMUL_CONTINUE)
3478
		return rc;
3479

3480
	rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
3481 3482
	if (rc != X86EMUL_CONTINUE)
		goto fail;
3483

3484
	ctxt->src.val = old_cs;
3485
	rc = em_push(ctxt);
3486
	if (rc != X86EMUL_CONTINUE)
3487
		goto fail;
3488

3489
	ctxt->src.val = old_eip;
3490 3491 3492
	rc = em_push(ctxt);
	/* If we failed, we tainted the memory, but the very least we should
	   restore cs */
3493 3494
	if (rc != X86EMUL_CONTINUE) {
		pr_warn_once("faulting far call emulation tainted memory\n");
3495
		goto fail;
3496
	}
3497 3498 3499
	return rc;
fail:
	ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
3500
	ctxt->mode = prev_mode;
3501 3502
	return rc;

3503 3504
}

3505 3506 3507
static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
{
	int rc;
3508
	unsigned long eip;
3509

3510 3511 3512 3513
	rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
	if (rc != X86EMUL_CONTINUE)
		return rc;
	rc = assign_eip_near(ctxt, eip);
3514 3515
	if (rc != X86EMUL_CONTINUE)
		return rc;
3516
	rsp_increment(ctxt, ctxt->src.val);
3517 3518 3519
	return X86EMUL_CONTINUE;
}

3520 3521 3522
static int em_xchg(struct x86_emulate_ctxt *ctxt)
{
	/* Write back the register source. */
3523 3524
	ctxt->src.val = ctxt->dst.val;
	write_register_operand(&ctxt->src);
3525 3526

	/* Write back the memory destination with implicit LOCK prefix. */
3527 3528
	ctxt->dst.val = ctxt->src.orig_val;
	ctxt->lock_prefix = 1;
3529 3530 3531
	return X86EMUL_CONTINUE;
}

3532 3533
static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
{
3534
	ctxt->dst.val = ctxt->src2.val;
3535
	return fastop(ctxt, em_imul);
3536 3537
}

3538 3539
static int em_cwd(struct x86_emulate_ctxt *ctxt)
{
3540 3541
	ctxt->dst.type = OP_REG;
	ctxt->dst.bytes = ctxt->src.bytes;
3542
	ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
3543
	ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
3544 3545 3546 3547

	return X86EMUL_CONTINUE;
}

P
Paolo Bonzini 已提交
3548 3549 3550 3551 3552 3553 3554 3555 3556 3557
static int em_rdpid(struct x86_emulate_ctxt *ctxt)
{
	u64 tsc_aux = 0;

	if (ctxt->ops->get_msr(ctxt, MSR_TSC_AUX, &tsc_aux))
		return emulate_gp(ctxt, 0);
	ctxt->dst.val = tsc_aux;
	return X86EMUL_CONTINUE;
}

3558 3559 3560 3561
static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
{
	u64 tsc = 0;

3562
	ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
3563 3564
	*reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
	*reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
3565 3566 3567
	return X86EMUL_CONTINUE;
}

3568 3569 3570 3571
static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
{
	u64 pmc;

3572
	if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
3573
		return emulate_gp(ctxt, 0);
3574 3575
	*reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
	*reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
3576 3577 3578
	return X86EMUL_CONTINUE;
}

3579 3580
static int em_mov(struct x86_emulate_ctxt *ctxt)
{
3581
	memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
3582 3583 3584
	return X86EMUL_CONTINUE;
}

B
Borislav Petkov 已提交
3585 3586 3587 3588 3589 3590 3591 3592 3593 3594
#define FFL(x) bit(X86_FEATURE_##x)

static int em_movbe(struct x86_emulate_ctxt *ctxt)
{
	u32 ebx, ecx, edx, eax = 1;
	u16 tmp;

	/*
	 * Check MOVBE is set in the guest-visible CPUID leaf.
	 */
3595
	ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
B
Borislav Petkov 已提交
3596 3597 3598 3599 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619
	if (!(ecx & FFL(MOVBE)))
		return emulate_ud(ctxt);

	switch (ctxt->op_bytes) {
	case 2:
		/*
		 * From MOVBE definition: "...When the operand size is 16 bits,
		 * the upper word of the destination register remains unchanged
		 * ..."
		 *
		 * Both casting ->valptr and ->val to u16 breaks strict aliasing
		 * rules so we have to do the operation almost per hand.
		 */
		tmp = (u16)ctxt->src.val;
		ctxt->dst.val &= ~0xffffUL;
		ctxt->dst.val |= (unsigned long)swab16(tmp);
		break;
	case 4:
		ctxt->dst.val = swab32((u32)ctxt->src.val);
		break;
	case 8:
		ctxt->dst.val = swab64(ctxt->src.val);
		break;
	default:
3620
		BUG();
B
Borislav Petkov 已提交
3621 3622 3623 3624
	}
	return X86EMUL_CONTINUE;
}

3625 3626 3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643 3644 3645 3646 3647 3648 3649 3650 3651 3652
static int em_cr_write(struct x86_emulate_ctxt *ctxt)
{
	if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
		return emulate_gp(ctxt, 0);

	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

static int em_dr_write(struct x86_emulate_ctxt *ctxt)
{
	unsigned long val;

	if (ctxt->mode == X86EMUL_MODE_PROT64)
		val = ctxt->src.val & ~0ULL;
	else
		val = ctxt->src.val & ~0U;

	/* #UD condition is already handled. */
	if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
		return emulate_gp(ctxt, 0);

	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

3653 3654 3655 3656
static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
{
	u64 msr_data;

3657 3658 3659
	msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
		| ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
	if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
3660 3661 3662 3663 3664 3665 3666 3667 3668
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
{
	u64 msr_data;

3669
	if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
3670 3671
		return emulate_gp(ctxt, 0);

3672 3673
	*reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
	*reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
3674 3675 3676
	return X86EMUL_CONTINUE;
}

P
Paolo Bonzini 已提交
3677
static int em_store_sreg(struct x86_emulate_ctxt *ctxt, int segment)
3678
{
P
Paolo Bonzini 已提交
3679 3680 3681 3682
	if (segment > VCPU_SREG_GS &&
	    (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) &&
	    ctxt->ops->cpl(ctxt) > 0)
		return emulate_gp(ctxt, 0);
3683

P
Paolo Bonzini 已提交
3684
	ctxt->dst.val = get_segment_selector(ctxt, segment);
3685 3686
	if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
		ctxt->dst.bytes = 2;
3687 3688 3689
	return X86EMUL_CONTINUE;
}

P
Paolo Bonzini 已提交
3690 3691 3692 3693 3694 3695 3696 3697
static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
{
	if (ctxt->modrm_reg > VCPU_SREG_GS)
		return emulate_ud(ctxt);

	return em_store_sreg(ctxt, ctxt->modrm_reg);
}

3698 3699
static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
{
3700
	u16 sel = ctxt->src.val;
3701

3702
	if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
3703 3704
		return emulate_ud(ctxt);

3705
	if (ctxt->modrm_reg == VCPU_SREG_SS)
3706 3707 3708
		ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;

	/* Disable writeback. */
3709 3710
	ctxt->dst.type = OP_NONE;
	return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
3711 3712
}

P
Paolo Bonzini 已提交
3713 3714 3715 3716 3717
static int em_sldt(struct x86_emulate_ctxt *ctxt)
{
	return em_store_sreg(ctxt, VCPU_SREG_LDTR);
}

A
Avi Kivity 已提交
3718 3719 3720 3721 3722 3723 3724 3725 3726
static int em_lldt(struct x86_emulate_ctxt *ctxt)
{
	u16 sel = ctxt->src.val;

	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
}

P
Paolo Bonzini 已提交
3727 3728 3729 3730 3731
static int em_str(struct x86_emulate_ctxt *ctxt)
{
	return em_store_sreg(ctxt, VCPU_SREG_TR);
}

A
Avi Kivity 已提交
3732 3733 3734 3735 3736 3737 3738 3739 3740
static int em_ltr(struct x86_emulate_ctxt *ctxt)
{
	u16 sel = ctxt->src.val;

	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
}

3741 3742
static int em_invlpg(struct x86_emulate_ctxt *ctxt)
{
3743 3744 3745
	int rc;
	ulong linear;

3746
	rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
3747
	if (rc == X86EMUL_CONTINUE)
3748
		ctxt->ops->invlpg(ctxt, linear);
3749
	/* Disable writeback. */
3750
	ctxt->dst.type = OP_NONE;
3751 3752 3753
	return X86EMUL_CONTINUE;
}

3754 3755 3756 3757 3758 3759 3760 3761 3762 3763
static int em_clts(struct x86_emulate_ctxt *ctxt)
{
	ulong cr0;

	cr0 = ctxt->ops->get_cr(ctxt, 0);
	cr0 &= ~X86_CR0_TS;
	ctxt->ops->set_cr(ctxt, 0, cr0);
	return X86EMUL_CONTINUE;
}

3764
static int em_hypercall(struct x86_emulate_ctxt *ctxt)
3765
{
3766
	int rc = ctxt->ops->fix_hypercall(ctxt);
3767 3768 3769 3770 3771

	if (rc != X86EMUL_CONTINUE)
		return rc;

	/* Let the processor re-execute the fixed hypercall */
3772
	ctxt->_eip = ctxt->eip;
3773
	/* Disable writeback. */
3774
	ctxt->dst.type = OP_NONE;
3775 3776 3777
	return X86EMUL_CONTINUE;
}

3778 3779 3780 3781 3782 3783
static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
				  void (*get)(struct x86_emulate_ctxt *ctxt,
					      struct desc_ptr *ptr))
{
	struct desc_ptr desc_ptr;

P
Paolo Bonzini 已提交
3784 3785 3786 3787
	if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) &&
	    ctxt->ops->cpl(ctxt) > 0)
		return emulate_gp(ctxt, 0);

3788 3789 3790 3791 3792 3793 3794 3795 3796
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		ctxt->op_bytes = 8;
	get(ctxt, &desc_ptr);
	if (ctxt->op_bytes == 2) {
		ctxt->op_bytes = 4;
		desc_ptr.address &= 0x00ffffff;
	}
	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
3797 3798
	return segmented_write_std(ctxt, ctxt->dst.addr.mem,
				   &desc_ptr, 2 + ctxt->op_bytes);
3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810
}

static int em_sgdt(struct x86_emulate_ctxt *ctxt)
{
	return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
}

static int em_sidt(struct x86_emulate_ctxt *ctxt)
{
	return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
}

3811
static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
3812 3813 3814 3815
{
	struct desc_ptr desc_ptr;
	int rc;

3816 3817
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		ctxt->op_bytes = 8;
3818
	rc = read_descriptor(ctxt, ctxt->src.addr.mem,
3819
			     &desc_ptr.size, &desc_ptr.address,
3820
			     ctxt->op_bytes);
3821 3822
	if (rc != X86EMUL_CONTINUE)
		return rc;
3823
	if (ctxt->mode == X86EMUL_MODE_PROT64 &&
3824
	    emul_is_noncanonical_address(desc_ptr.address, ctxt))
3825
		return emulate_gp(ctxt, 0);
3826 3827 3828 3829
	if (lgdt)
		ctxt->ops->set_gdt(ctxt, &desc_ptr);
	else
		ctxt->ops->set_idt(ctxt, &desc_ptr);
3830
	/* Disable writeback. */
3831
	ctxt->dst.type = OP_NONE;
3832 3833 3834
	return X86EMUL_CONTINUE;
}

3835 3836 3837 3838 3839
static int em_lgdt(struct x86_emulate_ctxt *ctxt)
{
	return em_lgdt_lidt(ctxt, true);
}

3840 3841
static int em_lidt(struct x86_emulate_ctxt *ctxt)
{
3842
	return em_lgdt_lidt(ctxt, false);
3843 3844 3845 3846
}

static int em_smsw(struct x86_emulate_ctxt *ctxt)
{
P
Paolo Bonzini 已提交
3847 3848 3849 3850
	if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) &&
	    ctxt->ops->cpl(ctxt) > 0)
		return emulate_gp(ctxt, 0);

3851 3852
	if (ctxt->dst.type == OP_MEM)
		ctxt->dst.bytes = 2;
3853
	ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
3854 3855 3856 3857 3858 3859
	return X86EMUL_CONTINUE;
}

static int em_lmsw(struct x86_emulate_ctxt *ctxt)
{
	ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
3860 3861
			  | (ctxt->src.val & 0x0f));
	ctxt->dst.type = OP_NONE;
3862 3863 3864
	return X86EMUL_CONTINUE;
}

3865 3866
static int em_loop(struct x86_emulate_ctxt *ctxt)
{
3867 3868
	int rc = X86EMUL_CONTINUE;

3869
	register_address_increment(ctxt, VCPU_REGS_RCX, -1);
3870
	if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
3871
	    (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3872
		rc = jmp_rel(ctxt, ctxt->src.val);
3873

3874
	return rc;
3875 3876 3877 3878
}

static int em_jcxz(struct x86_emulate_ctxt *ctxt)
{
3879 3880
	int rc = X86EMUL_CONTINUE;

3881
	if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
3882
		rc = jmp_rel(ctxt, ctxt->src.val);
3883

3884
	return rc;
3885 3886
}

3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904
static int em_in(struct x86_emulate_ctxt *ctxt)
{
	if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
			     &ctxt->dst.val))
		return X86EMUL_IO_NEEDED;

	return X86EMUL_CONTINUE;
}

static int em_out(struct x86_emulate_ctxt *ctxt)
{
	ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
				    &ctxt->src.val, 1);
	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923
static int em_cli(struct x86_emulate_ctxt *ctxt)
{
	if (emulator_bad_iopl(ctxt))
		return emulate_gp(ctxt, 0);

	ctxt->eflags &= ~X86_EFLAGS_IF;
	return X86EMUL_CONTINUE;
}

static int em_sti(struct x86_emulate_ctxt *ctxt)
{
	if (emulator_bad_iopl(ctxt))
		return emulate_gp(ctxt, 0);

	ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
	ctxt->eflags |= X86_EFLAGS_IF;
	return X86EMUL_CONTINUE;
}

A
Avi Kivity 已提交
3924 3925 3926
static int em_cpuid(struct x86_emulate_ctxt *ctxt)
{
	u32 eax, ebx, ecx, edx;
K
Kyle Huey 已提交
3927 3928 3929 3930 3931 3932 3933
	u64 msr = 0;

	ctxt->ops->get_msr(ctxt, MSR_MISC_FEATURES_ENABLES, &msr);
	if (msr & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
	    ctxt->ops->cpl(ctxt)) {
		return emulate_gp(ctxt, 0);
	}
A
Avi Kivity 已提交
3934

3935 3936
	eax = reg_read(ctxt, VCPU_REGS_RAX);
	ecx = reg_read(ctxt, VCPU_REGS_RCX);
3937
	ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, true);
3938 3939 3940 3941
	*reg_write(ctxt, VCPU_REGS_RAX) = eax;
	*reg_write(ctxt, VCPU_REGS_RBX) = ebx;
	*reg_write(ctxt, VCPU_REGS_RCX) = ecx;
	*reg_write(ctxt, VCPU_REGS_RDX) = edx;
A
Avi Kivity 已提交
3942 3943 3944
	return X86EMUL_CONTINUE;
}

P
Paolo Bonzini 已提交
3945 3946 3947 3948
static int em_sahf(struct x86_emulate_ctxt *ctxt)
{
	u32 flags;

3949 3950
	flags = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
		X86_EFLAGS_SF;
P
Paolo Bonzini 已提交
3951 3952 3953 3954 3955 3956 3957
	flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;

	ctxt->eflags &= ~0xffUL;
	ctxt->eflags |= flags | X86_EFLAGS_FIXED;
	return X86EMUL_CONTINUE;
}

A
Avi Kivity 已提交
3958 3959
static int em_lahf(struct x86_emulate_ctxt *ctxt)
{
3960 3961
	*reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
	*reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
A
Avi Kivity 已提交
3962 3963 3964
	return X86EMUL_CONTINUE;
}

A
Avi Kivity 已提交
3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979
static int em_bswap(struct x86_emulate_ctxt *ctxt)
{
	switch (ctxt->op_bytes) {
#ifdef CONFIG_X86_64
	case 8:
		asm("bswap %0" : "+r"(ctxt->dst.val));
		break;
#endif
	default:
		asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
		break;
	}
	return X86EMUL_CONTINUE;
}

3980 3981 3982 3983 3984 3985
static int em_clflush(struct x86_emulate_ctxt *ctxt)
{
	/* emulating clflush regardless of cpuid */
	return X86EMUL_CONTINUE;
}

3986 3987 3988 3989 3990 3991
static int em_movsxd(struct x86_emulate_ctxt *ctxt)
{
	ctxt->dst.val = (s32) ctxt->src.val;
	return X86EMUL_CONTINUE;
}

3992 3993 3994 3995
static int check_fxsr(struct x86_emulate_ctxt *ctxt)
{
	u32 eax = 1, ebx, ecx = 0, edx;

3996
	ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012
	if (!(edx & FFL(FXSR)))
		return emulate_ud(ctxt);

	if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
		return emulate_nm(ctxt);

	/*
	 * Don't emulate a case that should never be hit, instead of working
	 * around a lack of fxsave64/fxrstor64 on old compilers.
	 */
	if (ctxt->mode >= X86EMUL_MODE_PROT64)
		return X86EMUL_UNHANDLEABLE;

	return X86EMUL_CONTINUE;
}

4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031
/*
 * Hardware doesn't save and restore XMM 0-7 without CR4.OSFXSR, but does save
 * and restore MXCSR.
 */
static size_t __fxstate_size(int nregs)
{
	return offsetof(struct fxregs_state, xmm_space[0]) + nregs * 16;
}

static inline size_t fxstate_size(struct x86_emulate_ctxt *ctxt)
{
	bool cr4_osfxsr;
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		return __fxstate_size(16);

	cr4_osfxsr = ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR;
	return __fxstate_size(cr4_osfxsr ? 8 : 0);
}

4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045 4046 4047 4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063
/*
 * FXSAVE and FXRSTOR have 4 different formats depending on execution mode,
 *  1) 16 bit mode
 *  2) 32 bit mode
 *     - like (1), but FIP and FDP (foo) are only 16 bit.  At least Intel CPUs
 *       preserve whole 32 bit values, though, so (1) and (2) are the same wrt.
 *       save and restore
 *  3) 64-bit mode with REX.W prefix
 *     - like (2), but XMM 8-15 are being saved and restored
 *  4) 64-bit mode without REX.W prefix
 *     - like (3), but FIP and FDP are 64 bit
 *
 * Emulation uses (3) for (1) and (2) and preserves XMM 8-15 to reach the
 * desired result.  (4) is not emulated.
 *
 * Note: Guest and host CPUID.(EAX=07H,ECX=0H):EBX[bit 13] (deprecate FPU CS
 * and FPU DS) should match.
 */
static int em_fxsave(struct x86_emulate_ctxt *ctxt)
{
	struct fxregs_state fx_state;
	int rc;

	rc = check_fxsr(ctxt);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_state));

	if (rc != X86EMUL_CONTINUE)
		return rc;

4064 4065
	return segmented_write_std(ctxt, ctxt->memop.addr.mem, &fx_state,
		                   fxstate_size(ctxt));
4066 4067
}

4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085 4086 4087
/*
 * FXRSTOR might restore XMM registers not provided by the guest. Fill
 * in the host registers (via FXSAVE) instead, so they won't be modified.
 * (preemption has to stay disabled until FXRSTOR).
 *
 * Use noinline to keep the stack for other functions called by callers small.
 */
static noinline int fxregs_fixup(struct fxregs_state *fx_state,
				 const size_t used_size)
{
	struct fxregs_state fx_tmp;
	int rc;

	rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_tmp));
	memcpy((void *)fx_state + used_size, (void *)&fx_tmp + used_size,
	       __fxstate_size(16) - used_size);

	return rc;
}

4088 4089 4090 4091
static int em_fxrstor(struct x86_emulate_ctxt *ctxt)
{
	struct fxregs_state fx_state;
	int rc;
4092
	size_t size;
4093 4094 4095 4096 4097

	rc = check_fxsr(ctxt);
	if (rc != X86EMUL_CONTINUE)
		return rc;

4098 4099 4100 4101 4102
	size = fxstate_size(ctxt);
	rc = segmented_read_std(ctxt, ctxt->memop.addr.mem, &fx_state, size);
	if (rc != X86EMUL_CONTINUE)
		return rc;

4103
	if (size < __fxstate_size(16)) {
4104
		rc = fxregs_fixup(&fx_state, size);
4105 4106 4107
		if (rc != X86EMUL_CONTINUE)
			goto out;
	}
4108

4109 4110 4111 4112
	if (fx_state.mxcsr >> 16) {
		rc = emulate_gp(ctxt, 0);
		goto out;
	}
4113 4114 4115 4116

	if (rc == X86EMUL_CONTINUE)
		rc = asm_safe("fxrstor %[fx]", : [fx] "m"(fx_state));

4117
out:
4118 4119 4120
	return rc;
}

4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131 4132 4133 4134
static bool valid_cr(int nr)
{
	switch (nr) {
	case 0:
	case 2 ... 4:
	case 8:
		return true;
	default:
		return false;
	}
}

static int check_cr_read(struct x86_emulate_ctxt *ctxt)
{
4135
	if (!valid_cr(ctxt->modrm_reg))
4136 4137 4138 4139 4140 4141 4142
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_cr_write(struct x86_emulate_ctxt *ctxt)
{
4143 4144
	u64 new_val = ctxt->src.val64;
	int cr = ctxt->modrm_reg;
4145
	u64 efer = 0;
4146 4147 4148 4149 4150 4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162

	static u64 cr_reserved_bits[] = {
		0xffffffff00000000ULL,
		0, 0, 0, /* CR3 checked later */
		CR4_RESERVED_BITS,
		0, 0, 0,
		CR8_RESERVED_BITS,
	};

	if (!valid_cr(cr))
		return emulate_ud(ctxt);

	if (new_val & cr_reserved_bits[cr])
		return emulate_gp(ctxt, 0);

	switch (cr) {
	case 0: {
4163
		u64 cr4;
4164 4165 4166 4167
		if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
		    ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
			return emulate_gp(ctxt, 0);

4168 4169
		cr4 = ctxt->ops->get_cr(ctxt, 4);
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
4170 4171 4172 4173 4174 4175 4176 4177 4178 4179

		if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
		    !(cr4 & X86_CR4_PAE))
			return emulate_gp(ctxt, 0);

		break;
		}
	case 3: {
		u64 rsvd = 0;

4180
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
4181 4182
		if (efer & EFER_LMA) {
			u64 maxphyaddr;
4183
			u32 eax, ebx, ecx, edx;
4184

4185 4186 4187 4188
			eax = 0x80000008;
			ecx = 0;
			if (ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx,
						 &edx, false))
4189 4190 4191
				maxphyaddr = eax & 0xff;
			else
				maxphyaddr = 36;
4192 4193 4194
			rsvd = rsvd_bits(maxphyaddr, 63);
			if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PCIDE)
				rsvd &= ~CR3_PCID_INVD;
4195
		}
4196 4197 4198 4199 4200 4201 4202

		if (new_val & rsvd)
			return emulate_gp(ctxt, 0);

		break;
		}
	case 4: {
4203
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214

		if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
			return emulate_gp(ctxt, 0);

		break;
		}
	}

	return X86EMUL_CONTINUE;
}

4215 4216 4217 4218
static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
{
	unsigned long dr7;

4219
	ctxt->ops->get_dr(ctxt, 7, &dr7);
4220 4221 4222 4223 4224 4225 4226

	/* Check if DR7.Global_Enable is set */
	return dr7 & (1 << 13);
}

static int check_dr_read(struct x86_emulate_ctxt *ctxt)
{
4227
	int dr = ctxt->modrm_reg;
4228 4229 4230 4231 4232
	u64 cr4;

	if (dr > 7)
		return emulate_ud(ctxt);

4233
	cr4 = ctxt->ops->get_cr(ctxt, 4);
4234 4235 4236
	if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
		return emulate_ud(ctxt);

4237 4238 4239 4240 4241 4242 4243
	if (check_dr7_gd(ctxt)) {
		ulong dr6;

		ctxt->ops->get_dr(ctxt, 6, &dr6);
		dr6 &= ~15;
		dr6 |= DR6_BD | DR6_RTM;
		ctxt->ops->set_dr(ctxt, 6, dr6);
4244
		return emulate_db(ctxt);
4245
	}
4246 4247 4248 4249 4250 4251

	return X86EMUL_CONTINUE;
}

static int check_dr_write(struct x86_emulate_ctxt *ctxt)
{
4252 4253
	u64 new_val = ctxt->src.val64;
	int dr = ctxt->modrm_reg;
4254 4255 4256 4257 4258 4259 4260

	if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
		return emulate_gp(ctxt, 0);

	return check_dr_read(ctxt);
}

4261 4262
static int check_svme(struct x86_emulate_ctxt *ctxt)
{
4263
	u64 efer = 0;
4264

4265
	ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
4266 4267 4268 4269 4270 4271 4272 4273 4274

	if (!(efer & EFER_SVME))
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
{
4275
	u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
4276 4277

	/* Valid physical address? */
4278
	if (rax & 0xffff000000000000ULL)
4279 4280 4281 4282 4283
		return emulate_gp(ctxt, 0);

	return check_svme(ctxt);
}

4284 4285
static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
{
4286
	u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
4287

4288
	if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
4289 4290 4291 4292 4293
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

4294 4295
static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
{
4296
	u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
4297
	u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
4298

4299 4300 4301 4302 4303 4304 4305
	/*
	 * VMware allows access to these Pseduo-PMCs even when read via RDPMC
	 * in Ring3 when CR4.PCE=0.
	 */
	if (enable_vmware_backdoor && is_vmware_backdoor_pmc(rcx))
		return X86EMUL_CONTINUE;

4306
	if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
4307
	    ctxt->ops->check_pmc(ctxt, rcx))
4308 4309 4310 4311 4312
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

4313 4314
static int check_perm_in(struct x86_emulate_ctxt *ctxt)
{
4315 4316
	ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
	if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
4317 4318 4319 4320 4321 4322 4323
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

static int check_perm_out(struct x86_emulate_ctxt *ctxt)
{
4324 4325
	ctxt->src.bytes = min(ctxt->src.bytes, 4u);
	if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
4326 4327 4328 4329 4330
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

4331
#define D(_y) { .flags = (_y) }
4332 4333 4334
#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
		      .intercept = x86_intercept_##_i, .check_perm = (_p) }
4335
#define N    D(NotImpl)
4336
#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
4337 4338
#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
4339
#define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) }
4340
#define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) }
4341
#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
4342
#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
4343
#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
4344
#define II(_f, _e, _i) \
4345
	{ .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
4346
#define IIP(_f, _e, _i, _p) \
4347 4348
	{ .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
	  .intercept = x86_intercept_##_i, .check_perm = (_p) }
4349
#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
4350

4351
#define D2bv(_f)      D((_f) | ByteOp), D(_f)
4352
#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
4353
#define I2bv(_f, _e)  I((_f) | ByteOp, _e), I(_f, _e)
4354
#define F2bv(_f, _e)  F((_f) | ByteOp, _e), F(_f, _e)
4355 4356
#define I2bvIP(_f, _e, _i, _p) \
	IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
4357

4358 4359 4360
#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e),		\
		F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e),	\
		F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
4361

4362 4363
static const struct opcode group7_rm0[] = {
	N,
4364
	I(SrcNone | Priv | EmulateOnUD,	em_hypercall),
4365 4366 4367
	N, N, N, N, N, N,
};

4368
static const struct opcode group7_rm1[] = {
4369 4370
	DI(SrcNone | Priv, monitor),
	DI(SrcNone | Priv, mwait),
4371 4372 4373
	N, N, N, N, N, N,
};

4374
static const struct opcode group7_rm3[] = {
4375
	DIP(SrcNone | Prot | Priv,		vmrun,		check_svme_pa),
4376
	II(SrcNone  | Prot | EmulateOnUD,	em_hypercall,	vmmcall),
4377 4378 4379 4380 4381 4382
	DIP(SrcNone | Prot | Priv,		vmload,		check_svme_pa),
	DIP(SrcNone | Prot | Priv,		vmsave,		check_svme_pa),
	DIP(SrcNone | Prot | Priv,		stgi,		check_svme),
	DIP(SrcNone | Prot | Priv,		clgi,		check_svme),
	DIP(SrcNone | Prot | Priv,		skinit,		check_svme),
	DIP(SrcNone | Prot | Priv,		invlpga,	check_svme),
4383
};
4384

4385
static const struct opcode group7_rm7[] = {
4386
	N,
4387
	DIP(SrcNone, rdtscp, check_rdtsc),
4388 4389
	N, N, N, N, N, N,
};
4390

4391
static const struct opcode group1[] = {
4392 4393 4394 4395 4396 4397 4398 4399
	F(Lock, em_add),
	F(Lock | PageTable, em_or),
	F(Lock, em_adc),
	F(Lock, em_sbb),
	F(Lock | PageTable, em_and),
	F(Lock, em_sub),
	F(Lock, em_xor),
	F(NoWrite, em_cmp),
4400 4401
};

4402
static const struct opcode group1A[] = {
4403
	I(DstMem | SrcNone | Mov | Stack | IncSP | TwoMemOp, em_pop), N, N, N, N, N, N, N,
4404 4405
};

4406 4407 4408 4409 4410 4411 4412 4413 4414 4415 4416
static const struct opcode group2[] = {
	F(DstMem | ModRM, em_rol),
	F(DstMem | ModRM, em_ror),
	F(DstMem | ModRM, em_rcl),
	F(DstMem | ModRM, em_rcr),
	F(DstMem | ModRM, em_shl),
	F(DstMem | ModRM, em_shr),
	F(DstMem | ModRM, em_shl),
	F(DstMem | ModRM, em_sar),
};

4417
static const struct opcode group3[] = {
4418 4419
	F(DstMem | SrcImm | NoWrite, em_test),
	F(DstMem | SrcImm | NoWrite, em_test),
4420 4421
	F(DstMem | SrcNone | Lock, em_not),
	F(DstMem | SrcNone | Lock, em_neg),
4422 4423
	F(DstXacc | Src2Mem, em_mul_ex),
	F(DstXacc | Src2Mem, em_imul_ex),
4424 4425
	F(DstXacc | Src2Mem, em_div_ex),
	F(DstXacc | Src2Mem, em_idiv_ex),
4426 4427
};

4428
static const struct opcode group4[] = {
4429 4430
	F(ByteOp | DstMem | SrcNone | Lock, em_inc),
	F(ByteOp | DstMem | SrcNone | Lock, em_dec),
4431 4432 4433
	N, N, N, N, N, N,
};

4434
static const struct opcode group5[] = {
4435 4436
	F(DstMem | SrcNone | Lock,		em_inc),
	F(DstMem | SrcNone | Lock,		em_dec),
4437
	I(SrcMem | NearBranch,			em_call_near_abs),
4438
	I(SrcMemFAddr | ImplicitOps,		em_call_far),
4439
	I(SrcMem | NearBranch,			em_jmp_abs),
4440
	I(SrcMemFAddr | ImplicitOps,		em_jmp_far),
4441
	I(SrcMem | Stack | TwoMemOp,		em_push), D(Undefined),
4442 4443
};

4444
static const struct opcode group6[] = {
P
Paolo Bonzini 已提交
4445 4446
	II(Prot | DstMem,	   em_sldt, sldt),
	II(Prot | DstMem,	   em_str, str),
A
Avi Kivity 已提交
4447
	II(Prot | Priv | SrcMem16, em_lldt, lldt),
A
Avi Kivity 已提交
4448
	II(Prot | Priv | SrcMem16, em_ltr, ltr),
4449 4450 4451
	N, N, N, N,
};

4452
static const struct group_dual group7 = { {
4453 4454
	II(Mov | DstMem,			em_sgdt, sgdt),
	II(Mov | DstMem,			em_sidt, sidt),
4455 4456 4457 4458 4459
	II(SrcMem | Priv,			em_lgdt, lgdt),
	II(SrcMem | Priv,			em_lidt, lidt),
	II(SrcNone | DstMem | Mov,		em_smsw, smsw), N,
	II(SrcMem16 | Mov | Priv,		em_lmsw, lmsw),
	II(SrcMem | ByteOp | Priv | NoAccess,	em_invlpg, invlpg),
4460
}, {
4461
	EXT(0, group7_rm0),
4462
	EXT(0, group7_rm1),
4463
	N, EXT(0, group7_rm3),
4464 4465 4466
	II(SrcNone | DstMem | Mov,		em_smsw, smsw), N,
	II(SrcMem16 | Mov | Priv,		em_lmsw, lmsw),
	EXT(0, group7_rm7),
4467 4468
} };

4469
static const struct opcode group8[] = {
4470
	N, N, N, N,
4471 4472 4473 4474
	F(DstMem | SrcImmByte | NoWrite,		em_bt),
	F(DstMem | SrcImmByte | Lock | PageTable,	em_bts),
	F(DstMem | SrcImmByte | Lock,			em_btr),
	F(DstMem | SrcImmByte | Lock | PageTable,	em_btc),
4475 4476
};

P
Paolo Bonzini 已提交
4477 4478 4479 4480 4481 4482 4483 4484 4485
/*
 * The "memory" destination is actually always a register, since we come
 * from the register case of group9.
 */
static const struct gprefix pfx_0f_c7_7 = {
	N, N, N, II(DstMem | ModRM | Op3264 | EmulateOnUD, em_rdpid, rdtscp),
};


4486
static const struct group_dual group9 = { {
4487
	N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
4488
}, {
P
Paolo Bonzini 已提交
4489 4490
	N, N, N, N, N, N, N,
	GP(0, &pfx_0f_c7_7),
4491 4492
} };

4493
static const struct opcode group11[] = {
4494
	I(DstMem | SrcImm | Mov | PageTable, em_mov),
4495
	X7(D(Undefined)),
4496 4497
};

4498
static const struct gprefix pfx_0f_ae_7 = {
4499
	I(SrcMem | ByteOp, em_clflush), N, N, N,
4500 4501 4502
};

static const struct group_dual group15 = { {
4503 4504 4505
	I(ModRM | Aligned16, em_fxsave),
	I(ModRM | Aligned16, em_fxrstor),
	N, N, N, N, N, GP(0, &pfx_0f_ae_7),
4506 4507 4508 4509
}, {
	N, N, N, N, N, N, N, N,
} };

4510
static const struct gprefix pfx_0f_6f_0f_7f = {
4511
	I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
4512 4513
};

4514 4515 4516 4517
static const struct instr_dual instr_dual_0f_2b = {
	I(0, em_mov), N
};

4518
static const struct gprefix pfx_0f_2b = {
4519
	ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N,
4520 4521
};

4522 4523 4524 4525
static const struct gprefix pfx_0f_10_0f_11 = {
	I(Unaligned, em_mov), I(Unaligned, em_mov), N, N,
};

4526
static const struct gprefix pfx_0f_28_0f_29 = {
4527
	I(Aligned, em_mov), I(Aligned, em_mov), N, N,
4528 4529
};

4530 4531 4532 4533
static const struct gprefix pfx_0f_e7 = {
	N, I(Sse, em_mov), N, N,
};

4534
static const struct escape escape_d9 = { {
4535
	N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw),
4536 4537 4538 4539 4540 4541 4542 4543 4544 4545 4546 4547 4548 4549 4550 4551 4552 4553 4554 4555 4556 4557 4558 4559 4560 4561 4562 4563 4564 4565 4566 4567 4568 4569 4570 4571 4572 4573 4574 4575 4576
}, {
	/* 0xC0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xC8 - 0xCF */
	N, N, N, N, N, N, N, N,
	/* 0xD0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xD8 - 0xDF */
	N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xE7 */
	N, N, N, N, N, N, N, N,
	/* 0xE8 - 0xEF */
	N, N, N, N, N, N, N, N,
	/* 0xF0 - 0xF7 */
	N, N, N, N, N, N, N, N,
	/* 0xF8 - 0xFF */
	N, N, N, N, N, N, N, N,
} };

static const struct escape escape_db = { {
	N, N, N, N, N, N, N, N,
}, {
	/* 0xC0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xC8 - 0xCF */
	N, N, N, N, N, N, N, N,
	/* 0xD0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xD8 - 0xDF */
	N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xE7 */
	N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
	/* 0xE8 - 0xEF */
	N, N, N, N, N, N, N, N,
	/* 0xF0 - 0xF7 */
	N, N, N, N, N, N, N, N,
	/* 0xF8 - 0xFF */
	N, N, N, N, N, N, N, N,
} };

static const struct escape escape_dd = { {
4577
	N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw),
4578 4579 4580 4581 4582 4583 4584 4585 4586 4587 4588 4589 4590 4591 4592 4593 4594 4595 4596
}, {
	/* 0xC0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xC8 - 0xCF */
	N, N, N, N, N, N, N, N,
	/* 0xD0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xD8 - 0xDF */
	N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xE7 */
	N, N, N, N, N, N, N, N,
	/* 0xE8 - 0xEF */
	N, N, N, N, N, N, N, N,
	/* 0xF0 - 0xF7 */
	N, N, N, N, N, N, N, N,
	/* 0xF8 - 0xFF */
	N, N, N, N, N, N, N, N,
} };

4597 4598 4599 4600
static const struct instr_dual instr_dual_0f_c3 = {
	I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N
};

4601 4602 4603 4604
static const struct mode_dual mode_dual_63 = {
	N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd)
};

4605
static const struct opcode opcode_table[256] = {
4606
	/* 0x00 - 0x07 */
4607
	F6ALU(Lock, em_add),
4608 4609
	I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
	I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
4610
	/* 0x08 - 0x0F */
4611
	F6ALU(Lock | PageTable, em_or),
4612 4613
	I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
	N,
4614
	/* 0x10 - 0x17 */
4615
	F6ALU(Lock, em_adc),
4616 4617
	I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
	I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
4618
	/* 0x18 - 0x1F */
4619
	F6ALU(Lock, em_sbb),
4620 4621
	I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
	I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
4622
	/* 0x20 - 0x27 */
4623
	F6ALU(Lock | PageTable, em_and), N, N,
4624
	/* 0x28 - 0x2F */
4625
	F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
4626
	/* 0x30 - 0x37 */
4627
	F6ALU(Lock, em_xor), N, N,
4628
	/* 0x38 - 0x3F */
4629
	F6ALU(NoWrite, em_cmp), N, N,
4630
	/* 0x40 - 0x4F */
4631
	X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
4632
	/* 0x50 - 0x57 */
4633
	X8(I(SrcReg | Stack, em_push)),
4634
	/* 0x58 - 0x5F */
4635
	X8(I(DstReg | Stack, em_pop)),
4636
	/* 0x60 - 0x67 */
4637 4638
	I(ImplicitOps | Stack | No64, em_pusha),
	I(ImplicitOps | Stack | No64, em_popa),
4639
	N, MD(ModRM, &mode_dual_63),
4640 4641
	N, N, N, N,
	/* 0x68 - 0x6F */
4642 4643
	I(SrcImm | Mov | Stack, em_push),
	I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
4644 4645
	I(SrcImmByte | Mov | Stack, em_push),
	I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
4646
	I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
4647
	I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
4648
	/* 0x70 - 0x7F */
4649
	X16(D(SrcImmByte | NearBranch)),
4650
	/* 0x80 - 0x87 */
4651 4652 4653 4654
	G(ByteOp | DstMem | SrcImm, group1),
	G(DstMem | SrcImm, group1),
	G(ByteOp | DstMem | SrcImm | No64, group1),
	G(DstMem | SrcImmByte, group1),
4655
	F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
4656
	I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
4657
	/* 0x88 - 0x8F */
4658
	I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
4659
	I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
4660
	I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
4661 4662 4663
	D(ModRM | SrcMem | NoAccess | DstReg),
	I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
	G(0, group1A),
4664
	/* 0x90 - 0x97 */
4665
	DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
4666
	/* 0x98 - 0x9F */
4667
	D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
4668
	I(SrcImmFAddr | No64, em_call_far), N,
4669
	II(ImplicitOps | Stack, em_pushf, pushf),
P
Paolo Bonzini 已提交
4670 4671
	II(ImplicitOps | Stack, em_popf, popf),
	I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
4672
	/* 0xA0 - 0xA7 */
4673
	I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
4674
	I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
4675 4676
	I2bv(SrcSI | DstDI | Mov | String | TwoMemOp, em_mov),
	F2bv(SrcSI | DstDI | String | NoWrite | TwoMemOp, em_cmp_r),
4677
	/* 0xA8 - 0xAF */
4678
	F2bv(DstAcc | SrcImm | NoWrite, em_test),
4679 4680
	I2bv(SrcAcc | DstDI | Mov | String, em_mov),
	I2bv(SrcSI | DstAcc | Mov | String, em_mov),
4681
	F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
4682
	/* 0xB0 - 0xB7 */
4683
	X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
4684
	/* 0xB8 - 0xBF */
4685
	X8(I(DstReg | SrcImm64 | Mov, em_mov)),
4686
	/* 0xC0 - 0xC7 */
4687
	G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
4688 4689
	I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
	I(ImplicitOps | NearBranch, em_ret),
4690 4691
	I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
	I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
4692
	G(ByteOp, group11), G(0, group11),
4693
	/* 0xC8 - 0xCF */
A
Avi Kivity 已提交
4694
	I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
4695 4696
	I(ImplicitOps | SrcImmU16, em_ret_far_imm),
	I(ImplicitOps, em_ret_far),
4697
	D(ImplicitOps), DI(SrcImmByte, intn),
4698
	D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
4699
	/* 0xD0 - 0xD7 */
4700 4701
	G(Src2One | ByteOp, group2), G(Src2One, group2),
	G(Src2CL | ByteOp, group2), G(Src2CL, group2),
P
Paolo Bonzini 已提交
4702
	I(DstAcc | SrcImmUByte | No64, em_aam),
P
Paolo Bonzini 已提交
4703 4704
	I(DstAcc | SrcImmUByte | No64, em_aad),
	F(DstAcc | ByteOp | No64, em_salc),
P
Paolo Bonzini 已提交
4705
	I(DstAcc | SrcXLat | ByteOp, em_mov),
4706
	/* 0xD8 - 0xDF */
4707
	N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
4708
	/* 0xE0 - 0xE7 */
4709 4710
	X3(I(SrcImmByte | NearBranch, em_loop)),
	I(SrcImmByte | NearBranch, em_jcxz),
4711 4712
	I2bvIP(SrcImmUByte | DstAcc, em_in,  in,  check_perm_in),
	I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
4713
	/* 0xE8 - 0xEF */
4714 4715 4716
	I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
	I(SrcImmFAddr | No64, em_jmp_far),
	D(SrcImmByte | ImplicitOps | NearBranch),
4717 4718
	I2bvIP(SrcDX | DstAcc, em_in,  in,  check_perm_in),
	I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
4719
	/* 0xF0 - 0xF7 */
4720
	N, DI(ImplicitOps, icebp), N, N,
4721 4722
	DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
	G(ByteOp, group3), G(0, group3),
4723
	/* 0xF8 - 0xFF */
4724 4725
	D(ImplicitOps), D(ImplicitOps),
	I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
4726 4727 4728
	D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
};

4729
static const struct opcode twobyte_table[256] = {
4730
	/* 0x00 - 0x0F */
4731
	G(0, group6), GD(0, &group7), N, N,
4732
	N, I(ImplicitOps | EmulateOnUD, em_syscall),
4733
	II(ImplicitOps | Priv, em_clts, clts), N,
4734
	DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
4735
	N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
4736
	/* 0x10 - 0x1F */
4737 4738 4739
	GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_10_0f_11),
	GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_10_0f_11),
	N, N, N, N, N, N,
4740 4741
	D(ImplicitOps | ModRM | SrcMem | NoAccess),
	N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
4742
	/* 0x20 - 0x2F */
4743 4744 4745 4746 4747 4748
	DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
	DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
	IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
						check_cr_write),
	IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
						check_dr_write),
4749
	N, N, N, N,
4750 4751
	GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
	GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
4752
	N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
4753
	N, N, N, N,
4754
	/* 0x30 - 0x3F */
4755
	II(ImplicitOps | Priv, em_wrmsr, wrmsr),
4756
	IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
4757
	II(ImplicitOps | Priv, em_rdmsr, rdmsr),
4758
	IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
4759 4760
	I(ImplicitOps | EmulateOnUD, em_sysenter),
	I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
4761
	N, N,
4762 4763
	N, N, N, N, N, N, N, N,
	/* 0x40 - 0x4F */
4764
	X16(D(DstReg | SrcMem | ModRM)),
4765 4766 4767
	/* 0x50 - 0x5F */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0x60 - 0x6F */
4768 4769 4770 4771
	N, N, N, N,
	N, N, N, N,
	N, N, N, N,
	N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
4772
	/* 0x70 - 0x7F */
4773 4774 4775 4776
	N, N, N, N,
	N, N, N, N,
	N, N, N, N,
	N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
4777
	/* 0x80 - 0x8F */
4778
	X16(D(SrcImm | NearBranch)),
4779
	/* 0x90 - 0x9F */
4780
	X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
4781
	/* 0xA0 - 0xA7 */
4782
	I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
4783 4784
	II(ImplicitOps, em_cpuid, cpuid),
	F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
4785 4786
	F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
	F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
4787
	/* 0xA8 - 0xAF */
4788
	I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
4789
	II(EmulateOnUD | ImplicitOps, em_rsm, rsm),
4790
	F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
4791 4792
	F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
	F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4793
	GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
4794
	/* 0xB0 - 0xB7 */
4795
	I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg),
4796
	I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
4797
	F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
4798 4799
	I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
	I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
4800
	D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
4801 4802
	/* 0xB8 - 0xBF */
	N, N,
4803
	G(BitOp, group8),
4804
	F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4805 4806
	I(DstReg | SrcMem | ModRM, em_bsf_c),
	I(DstReg | SrcMem | ModRM, em_bsr_c),
4807
	D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
A
Avi Kivity 已提交
4808
	/* 0xC0 - 0xC7 */
4809
	F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
4810
	N, ID(0, &instr_dual_0f_c3),
4811
	N, N, N, GD(0, &group9),
A
Avi Kivity 已提交
4812 4813
	/* 0xC8 - 0xCF */
	X8(I(DstReg, em_bswap)),
4814 4815 4816
	/* 0xD0 - 0xDF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xEF */
4817 4818
	N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
	N, N, N, N, N, N, N, N,
4819 4820 4821 4822
	/* 0xF0 - 0xFF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
};

4823 4824 4825 4826 4827 4828 4829 4830
static const struct instr_dual instr_dual_0f_38_f0 = {
	I(DstReg | SrcMem | Mov, em_movbe), N
};

static const struct instr_dual instr_dual_0f_38_f1 = {
	I(DstMem | SrcReg | Mov, em_movbe), N
};

4831
static const struct gprefix three_byte_0f_38_f0 = {
4832
	ID(0, &instr_dual_0f_38_f0), N, N, N
4833 4834 4835
};

static const struct gprefix three_byte_0f_38_f1 = {
4836
	ID(0, &instr_dual_0f_38_f1), N, N, N
4837 4838 4839 4840 4841 4842 4843 4844 4845
};

/*
 * Insns below are selected by the prefix which indexed by the third opcode
 * byte.
 */
static const struct opcode opcode_map_0f_38[256] = {
	/* 0x00 - 0x7f */
	X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
B
Borislav Petkov 已提交
4846 4847 4848
	/* 0x80 - 0xef */
	X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
	/* 0xf0 - 0xf1 */
4849 4850
	GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0),
	GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1),
B
Borislav Petkov 已提交
4851 4852
	/* 0xf2 - 0xff */
	N, N, X4(N), X8(N)
4853 4854
};

4855 4856 4857 4858 4859
#undef D
#undef N
#undef G
#undef GD
#undef I
4860
#undef GP
4861
#undef EXT
4862
#undef MD
N
Nadav Amit 已提交
4863
#undef ID
4864

4865
#undef D2bv
4866
#undef D2bvIP
4867
#undef I2bv
4868
#undef I2bvIP
4869
#undef I6ALU
4870

4871
static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
4872 4873 4874
{
	unsigned size;

4875
	size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4876 4877 4878 4879 4880 4881 4882 4883 4884 4885 4886 4887
	if (size == 8)
		size = 4;
	return size;
}

static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
		      unsigned size, bool sign_extension)
{
	int rc = X86EMUL_CONTINUE;

	op->type = OP_IMM;
	op->bytes = size;
4888
	op->addr.mem.ea = ctxt->_eip;
4889 4890 4891
	/* NB. Immediates are sign-extended as necessary. */
	switch (op->bytes) {
	case 1:
4892
		op->val = insn_fetch(s8, ctxt);
4893 4894
		break;
	case 2:
4895
		op->val = insn_fetch(s16, ctxt);
4896 4897
		break;
	case 4:
4898
		op->val = insn_fetch(s32, ctxt);
4899
		break;
4900 4901 4902
	case 8:
		op->val = insn_fetch(s64, ctxt);
		break;
4903 4904 4905 4906 4907 4908 4909 4910 4911 4912 4913 4914 4915 4916 4917 4918 4919 4920
	}
	if (!sign_extension) {
		switch (op->bytes) {
		case 1:
			op->val &= 0xff;
			break;
		case 2:
			op->val &= 0xffff;
			break;
		case 4:
			op->val &= 0xffffffff;
			break;
		}
	}
done:
	return rc;
}

4921 4922 4923 4924 4925 4926 4927
static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
			  unsigned d)
{
	int rc = X86EMUL_CONTINUE;

	switch (d) {
	case OpReg:
4928
		decode_register_operand(ctxt, op);
4929 4930
		break;
	case OpImmUByte:
4931
		rc = decode_imm(ctxt, op, 1, false);
4932 4933
		break;
	case OpMem:
4934
		ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4935 4936 4937
	mem_common:
		*op = ctxt->memop;
		ctxt->memopp = op;
4938
		if (ctxt->d & BitOp)
4939 4940 4941
			fetch_bit_operand(ctxt);
		op->orig_val = op->val;
		break;
4942
	case OpMem64:
4943
		ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
4944
		goto mem_common;
4945 4946 4947
	case OpAcc:
		op->type = OP_REG;
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4948
		op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4949 4950 4951
		fetch_register_operand(op);
		op->orig_val = op->val;
		break;
4952 4953 4954 4955 4956 4957 4958 4959 4960 4961 4962 4963 4964 4965 4966 4967 4968 4969
	case OpAccLo:
		op->type = OP_REG;
		op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
		op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
		fetch_register_operand(op);
		op->orig_val = op->val;
		break;
	case OpAccHi:
		if (ctxt->d & ByteOp) {
			op->type = OP_NONE;
			break;
		}
		op->type = OP_REG;
		op->bytes = ctxt->op_bytes;
		op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
		fetch_register_operand(op);
		op->orig_val = op->val;
		break;
4970 4971 4972 4973
	case OpDI:
		op->type = OP_MEM;
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		op->addr.mem.ea =
4974
			register_address(ctxt, VCPU_REGS_RDI);
4975 4976
		op->addr.mem.seg = VCPU_SREG_ES;
		op->val = 0;
4977
		op->count = 1;
4978 4979 4980 4981
		break;
	case OpDX:
		op->type = OP_REG;
		op->bytes = 2;
4982
		op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4983 4984
		fetch_register_operand(op);
		break;
4985
	case OpCL:
4986
		op->type = OP_IMM;
4987
		op->bytes = 1;
4988
		op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4989 4990 4991 4992 4993
		break;
	case OpImmByte:
		rc = decode_imm(ctxt, op, 1, true);
		break;
	case OpOne:
4994
		op->type = OP_IMM;
4995 4996 4997 4998 4999 5000
		op->bytes = 1;
		op->val = 1;
		break;
	case OpImm:
		rc = decode_imm(ctxt, op, imm_size(ctxt), true);
		break;
5001 5002 5003
	case OpImm64:
		rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
		break;
5004 5005
	case OpMem8:
		ctxt->memop.bytes = 1;
5006
		if (ctxt->memop.type == OP_REG) {
5007 5008
			ctxt->memop.addr.reg = decode_register(ctxt,
					ctxt->modrm_rm, true);
5009 5010
			fetch_register_operand(&ctxt->memop);
		}
5011
		goto mem_common;
5012 5013 5014 5015 5016 5017 5018 5019 5020 5021 5022 5023 5024 5025 5026 5027
	case OpMem16:
		ctxt->memop.bytes = 2;
		goto mem_common;
	case OpMem32:
		ctxt->memop.bytes = 4;
		goto mem_common;
	case OpImmU16:
		rc = decode_imm(ctxt, op, 2, false);
		break;
	case OpImmU:
		rc = decode_imm(ctxt, op, imm_size(ctxt), false);
		break;
	case OpSI:
		op->type = OP_MEM;
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		op->addr.mem.ea =
5028
			register_address(ctxt, VCPU_REGS_RSI);
B
Bandan Das 已提交
5029
		op->addr.mem.seg = ctxt->seg_override;
5030
		op->val = 0;
5031
		op->count = 1;
5032
		break;
P
Paolo Bonzini 已提交
5033 5034 5035 5036
	case OpXLat:
		op->type = OP_MEM;
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		op->addr.mem.ea =
5037
			address_mask(ctxt,
P
Paolo Bonzini 已提交
5038 5039
				reg_read(ctxt, VCPU_REGS_RBX) +
				(reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
B
Bandan Das 已提交
5040
		op->addr.mem.seg = ctxt->seg_override;
P
Paolo Bonzini 已提交
5041 5042
		op->val = 0;
		break;
5043 5044 5045 5046 5047 5048 5049 5050 5051
	case OpImmFAddr:
		op->type = OP_IMM;
		op->addr.mem.ea = ctxt->_eip;
		op->bytes = ctxt->op_bytes + 2;
		insn_fetch_arr(op->valptr, op->bytes, ctxt);
		break;
	case OpMemFAddr:
		ctxt->memop.bytes = ctxt->op_bytes + 2;
		goto mem_common;
5052
	case OpES:
5053
		op->type = OP_IMM;
5054 5055 5056
		op->val = VCPU_SREG_ES;
		break;
	case OpCS:
5057
		op->type = OP_IMM;
5058 5059 5060
		op->val = VCPU_SREG_CS;
		break;
	case OpSS:
5061
		op->type = OP_IMM;
5062 5063 5064
		op->val = VCPU_SREG_SS;
		break;
	case OpDS:
5065
		op->type = OP_IMM;
5066 5067 5068
		op->val = VCPU_SREG_DS;
		break;
	case OpFS:
5069
		op->type = OP_IMM;
5070 5071 5072
		op->val = VCPU_SREG_FS;
		break;
	case OpGS:
5073
		op->type = OP_IMM;
5074 5075
		op->val = VCPU_SREG_GS;
		break;
5076 5077 5078 5079 5080 5081 5082 5083 5084 5085 5086
	case OpImplicit:
		/* Special instructions do their own operand decoding. */
	default:
		op->type = OP_NONE; /* Disable writeback. */
		break;
	}

done:
	return rc;
}

5087
int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
5088 5089 5090
{
	int rc = X86EMUL_CONTINUE;
	int mode = ctxt->mode;
5091
	int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
5092
	bool op_prefix = false;
B
Bandan Das 已提交
5093
	bool has_seg_override = false;
5094
	struct opcode opcode;
5095 5096
	u16 dummy;
	struct desc_struct desc;
5097

5098 5099
	ctxt->memop.type = OP_NONE;
	ctxt->memopp = NULL;
5100
	ctxt->_eip = ctxt->eip;
5101 5102
	ctxt->fetch.ptr = ctxt->fetch.data;
	ctxt->fetch.end = ctxt->fetch.data + insn_len;
B
Borislav Petkov 已提交
5103
	ctxt->opcode_len = 1;
5104
	if (insn_len > 0)
5105
		memcpy(ctxt->fetch.data, insn, insn_len);
5106
	else {
5107
		rc = __do_insn_fetch_bytes(ctxt, 1);
5108 5109 5110
		if (rc != X86EMUL_CONTINUE)
			return rc;
	}
5111 5112 5113 5114

	switch (mode) {
	case X86EMUL_MODE_REAL:
	case X86EMUL_MODE_VM86:
5115 5116 5117 5118 5119
		def_op_bytes = def_ad_bytes = 2;
		ctxt->ops->get_segment(ctxt, &dummy, &desc, NULL, VCPU_SREG_CS);
		if (desc.d)
			def_op_bytes = def_ad_bytes = 4;
		break;
5120 5121 5122 5123 5124 5125 5126 5127 5128 5129 5130 5131 5132
	case X86EMUL_MODE_PROT16:
		def_op_bytes = def_ad_bytes = 2;
		break;
	case X86EMUL_MODE_PROT32:
		def_op_bytes = def_ad_bytes = 4;
		break;
#ifdef CONFIG_X86_64
	case X86EMUL_MODE_PROT64:
		def_op_bytes = 4;
		def_ad_bytes = 8;
		break;
#endif
	default:
5133
		return EMULATION_FAILED;
5134 5135
	}

5136 5137
	ctxt->op_bytes = def_op_bytes;
	ctxt->ad_bytes = def_ad_bytes;
5138 5139 5140

	/* Legacy prefixes. */
	for (;;) {
5141
		switch (ctxt->b = insn_fetch(u8, ctxt)) {
5142
		case 0x66:	/* operand-size override */
5143
			op_prefix = true;
5144
			/* switch between 2/4 bytes */
5145
			ctxt->op_bytes = def_op_bytes ^ 6;
5146 5147 5148 5149
			break;
		case 0x67:	/* address-size override */
			if (mode == X86EMUL_MODE_PROT64)
				/* switch between 4/8 bytes */
5150
				ctxt->ad_bytes = def_ad_bytes ^ 12;
5151 5152
			else
				/* switch between 2/4 bytes */
5153
				ctxt->ad_bytes = def_ad_bytes ^ 6;
5154 5155 5156 5157 5158
			break;
		case 0x26:	/* ES override */
		case 0x2e:	/* CS override */
		case 0x36:	/* SS override */
		case 0x3e:	/* DS override */
B
Bandan Das 已提交
5159 5160
			has_seg_override = true;
			ctxt->seg_override = (ctxt->b >> 3) & 3;
5161 5162 5163
			break;
		case 0x64:	/* FS override */
		case 0x65:	/* GS override */
B
Bandan Das 已提交
5164 5165
			has_seg_override = true;
			ctxt->seg_override = ctxt->b & 7;
5166 5167 5168 5169
			break;
		case 0x40 ... 0x4f: /* REX */
			if (mode != X86EMUL_MODE_PROT64)
				goto done_prefixes;
5170
			ctxt->rex_prefix = ctxt->b;
5171 5172
			continue;
		case 0xf0:	/* LOCK */
5173
			ctxt->lock_prefix = 1;
5174 5175 5176
			break;
		case 0xf2:	/* REPNE/REPNZ */
		case 0xf3:	/* REP/REPE/REPZ */
5177
			ctxt->rep_prefix = ctxt->b;
5178 5179 5180 5181 5182 5183 5184
			break;
		default:
			goto done_prefixes;
		}

		/* Any legacy prefix after a REX prefix nullifies its effect. */

5185
		ctxt->rex_prefix = 0;
5186 5187 5188 5189 5190
	}

done_prefixes:

	/* REX prefix. */
5191 5192
	if (ctxt->rex_prefix & 8)
		ctxt->op_bytes = 8;	/* REX.W */
5193 5194

	/* Opcode byte(s). */
5195
	opcode = opcode_table[ctxt->b];
5196
	/* Two-byte opcode? */
5197
	if (ctxt->b == 0x0f) {
B
Borislav Petkov 已提交
5198
		ctxt->opcode_len = 2;
5199
		ctxt->b = insn_fetch(u8, ctxt);
5200
		opcode = twobyte_table[ctxt->b];
5201 5202 5203 5204 5205 5206 5207

		/* 0F_38 opcode map */
		if (ctxt->b == 0x38) {
			ctxt->opcode_len = 3;
			ctxt->b = insn_fetch(u8, ctxt);
			opcode = opcode_map_0f_38[ctxt->b];
		}
5208
	}
5209
	ctxt->d = opcode.flags;
5210

5211 5212 5213
	if (ctxt->d & ModRM)
		ctxt->modrm = insn_fetch(u8, ctxt);

5214 5215
	/* vex-prefix instructions are not implemented */
	if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
5216
	    (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
5217 5218 5219
		ctxt->d = NotImpl;
	}

5220 5221
	while (ctxt->d & GroupMask) {
		switch (ctxt->d & GroupMask) {
5222
		case Group:
5223
			goffset = (ctxt->modrm >> 3) & 7;
5224 5225 5226
			opcode = opcode.u.group[goffset];
			break;
		case GroupDual:
5227 5228
			goffset = (ctxt->modrm >> 3) & 7;
			if ((ctxt->modrm >> 6) == 3)
5229 5230 5231 5232 5233
				opcode = opcode.u.gdual->mod3[goffset];
			else
				opcode = opcode.u.gdual->mod012[goffset];
			break;
		case RMExt:
5234
			goffset = ctxt->modrm & 7;
5235
			opcode = opcode.u.group[goffset];
5236 5237
			break;
		case Prefix:
5238
			if (ctxt->rep_prefix && op_prefix)
5239
				return EMULATION_FAILED;
5240
			simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
5241 5242 5243 5244 5245 5246 5247
			switch (simd_prefix) {
			case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
			case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
			case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
			case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
			}
			break;
5248 5249 5250 5251 5252 5253
		case Escape:
			if (ctxt->modrm > 0xbf)
				opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
			else
				opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
			break;
5254 5255 5256 5257 5258 5259
		case InstrDual:
			if ((ctxt->modrm >> 6) == 3)
				opcode = opcode.u.idual->mod3;
			else
				opcode = opcode.u.idual->mod012;
			break;
5260 5261 5262 5263 5264 5265
		case ModeDual:
			if (ctxt->mode == X86EMUL_MODE_PROT64)
				opcode = opcode.u.mdual->mode64;
			else
				opcode = opcode.u.mdual->mode32;
			break;
5266
		default:
5267
			return EMULATION_FAILED;
5268
		}
5269

5270
		ctxt->d &= ~(u64)GroupMask;
5271
		ctxt->d |= opcode.flags;
5272 5273
	}

5274 5275 5276 5277
	/* Unrecognised? */
	if (ctxt->d == 0)
		return EMULATION_FAILED;

5278
	ctxt->execute = opcode.u.execute;
5279

5280 5281 5282
	if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
		return EMULATION_FAILED;

5283
	if (unlikely(ctxt->d &
5284 5285
	    (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
	     No16))) {
5286 5287 5288 5289 5290 5291
		/*
		 * These are copied unconditionally here, and checked unconditionally
		 * in x86_emulate_insn.
		 */
		ctxt->check_perm = opcode.check_perm;
		ctxt->intercept = opcode.intercept;
5292

5293 5294
		if (ctxt->d & NotImpl)
			return EMULATION_FAILED;
5295

5296 5297 5298 5299 5300 5301
		if (mode == X86EMUL_MODE_PROT64) {
			if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
				ctxt->op_bytes = 8;
			else if (ctxt->d & NearBranch)
				ctxt->op_bytes = 8;
		}
5302

5303 5304 5305 5306 5307 5308 5309
		if (ctxt->d & Op3264) {
			if (mode == X86EMUL_MODE_PROT64)
				ctxt->op_bytes = 8;
			else
				ctxt->op_bytes = 4;
		}

5310 5311 5312
		if ((ctxt->d & No16) && ctxt->op_bytes == 2)
			ctxt->op_bytes = 4;

5313 5314 5315 5316 5317
		if (ctxt->d & Sse)
			ctxt->op_bytes = 16;
		else if (ctxt->d & Mmx)
			ctxt->op_bytes = 8;
	}
A
Avi Kivity 已提交
5318

5319
	/* ModRM and SIB bytes. */
5320
	if (ctxt->d & ModRM) {
5321
		rc = decode_modrm(ctxt, &ctxt->memop);
B
Bandan Das 已提交
5322 5323 5324 5325
		if (!has_seg_override) {
			has_seg_override = true;
			ctxt->seg_override = ctxt->modrm_seg;
		}
5326
	} else if (ctxt->d & MemAbs)
5327
		rc = decode_abs(ctxt, &ctxt->memop);
5328 5329 5330
	if (rc != X86EMUL_CONTINUE)
		goto done;

B
Bandan Das 已提交
5331 5332
	if (!has_seg_override)
		ctxt->seg_override = VCPU_SREG_DS;
5333

B
Bandan Das 已提交
5334
	ctxt->memop.addr.mem.seg = ctxt->seg_override;
5335 5336 5337 5338 5339

	/*
	 * Decode and fetch the source operand: register, memory
	 * or immediate.
	 */
5340
	rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
5341 5342 5343
	if (rc != X86EMUL_CONTINUE)
		goto done;

5344 5345 5346 5347
	/*
	 * Decode and fetch the second source operand: register, memory
	 * or immediate.
	 */
5348
	rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
5349 5350 5351
	if (rc != X86EMUL_CONTINUE)
		goto done;

5352
	/* Decode and fetch the destination operand: register or memory. */
5353
	rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
5354

5355
	if (ctxt->rip_relative && likely(ctxt->memopp))
5356 5357
		ctxt->memopp->addr.mem.ea = address_mask(ctxt,
					ctxt->memopp->addr.mem.ea + ctxt->_eip);
5358

5359
done:
5360
	return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
5361 5362
}

5363 5364 5365 5366 5367
bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
{
	return ctxt->d & PageTable;
}

5368 5369 5370 5371 5372 5373 5374 5375 5376
static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
{
	/* The second termination condition only applies for REPE
	 * and REPNE. Test if the repeat string operation prefix is
	 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
	 * corresponding termination condition according to:
	 * 	- if REPE/REPZ and ZF = 0 then done
	 * 	- if REPNE/REPNZ and ZF = 1 then done
	 */
5377 5378 5379
	if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
	     (ctxt->b == 0xae) || (ctxt->b == 0xaf))
	    && (((ctxt->rep_prefix == REPE_PREFIX) &&
5380
		 ((ctxt->eflags & X86_EFLAGS_ZF) == 0))
5381
		|| ((ctxt->rep_prefix == REPNE_PREFIX) &&
5382
		    ((ctxt->eflags & X86_EFLAGS_ZF) == X86_EFLAGS_ZF))))
5383 5384 5385 5386 5387
		return true;

	return false;
}

A
Avi Kivity 已提交
5388 5389
static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
{
R
Radim Krčmář 已提交
5390
	int rc;
A
Avi Kivity 已提交
5391

R
Radim Krčmář 已提交
5392
	rc = asm_safe("fwait");
A
Avi Kivity 已提交
5393

R
Radim Krčmář 已提交
5394
	if (unlikely(rc != X86EMUL_CONTINUE))
A
Avi Kivity 已提交
5395 5396 5397 5398 5399 5400 5401 5402 5403 5404 5405 5406
		return emulate_exception(ctxt, MF_VECTOR, 0, false);

	return X86EMUL_CONTINUE;
}

static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
				       struct operand *op)
{
	if (op->type == OP_MM)
		read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
}

5407 5408 5409
static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
{
	ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
5410

5411 5412
	if (!(ctxt->d & ByteOp))
		fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
5413

5414
	asm("push %[flags]; popf; " CALL_NOSPEC " ; pushf; pop %[flags]\n"
5415
	    : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
5416
	      [thunk_target]"+S"(fop), ASM_CALL_CONSTRAINT
5417
	    : "c"(ctxt->src2.val));
5418

5419
	ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
5420 5421
	if (!fop) /* exception is returned in fop variable */
		return emulate_de(ctxt);
5422 5423
	return X86EMUL_CONTINUE;
}
5424

5425 5426
void init_decode_cache(struct x86_emulate_ctxt *ctxt)
{
B
Bandan Das 已提交
5427 5428
	memset(&ctxt->rip_relative, 0,
	       (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
5429 5430 5431 5432 5433 5434

	ctxt->io_read.pos = 0;
	ctxt->io_read.end = 0;
	ctxt->mem_read.end = 0;
}

5435
int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
5436
{
5437
	const struct x86_emulate_ops *ops = ctxt->ops;
5438
	int rc = X86EMUL_CONTINUE;
5439
	int saved_dst_type = ctxt->dst.type;
5440
	unsigned emul_flags;
5441

5442
	ctxt->mem_read.pos = 0;
5443

5444 5445
	/* LOCK prefix is allowed only with some instructions */
	if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
5446
		rc = emulate_ud(ctxt);
5447 5448 5449
		goto done;
	}

5450
	if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
5451
		rc = emulate_ud(ctxt);
5452 5453 5454
		goto done;
	}

5455
	emul_flags = ctxt->ops->get_hflags(ctxt);
5456 5457 5458 5459 5460 5461 5462
	if (unlikely(ctxt->d &
		     (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
		if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
				(ctxt->d & Undefined)) {
			rc = emulate_ud(ctxt);
			goto done;
		}
A
Avi Kivity 已提交
5463

5464 5465 5466
		if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
		    || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
			rc = emulate_ud(ctxt);
A
Avi Kivity 已提交
5467
			goto done;
5468
		}
A
Avi Kivity 已提交
5469

5470 5471
		if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
			rc = emulate_nm(ctxt);
5472
			goto done;
5473
		}
5474

5475 5476 5477 5478 5479 5480 5481 5482 5483 5484 5485 5486 5487
		if (ctxt->d & Mmx) {
			rc = flush_pending_x87_faults(ctxt);
			if (rc != X86EMUL_CONTINUE)
				goto done;
			/*
			 * Now that we know the fpu is exception safe, we can fetch
			 * operands from it.
			 */
			fetch_possible_mmx_operand(ctxt, &ctxt->src);
			fetch_possible_mmx_operand(ctxt, &ctxt->src2);
			if (!(ctxt->d & Mov))
				fetch_possible_mmx_operand(ctxt, &ctxt->dst);
		}
5488

5489
		if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && ctxt->intercept) {
5490 5491 5492 5493 5494
			rc = emulator_check_intercept(ctxt, ctxt->intercept,
						      X86_ICPT_PRE_EXCEPT);
			if (rc != X86EMUL_CONTINUE)
				goto done;
		}
5495

5496 5497 5498 5499 5500 5501
		/* Instruction can only be executed in protected mode */
		if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
			rc = emulate_ud(ctxt);
			goto done;
		}

5502 5503
		/* Privileged instruction can be executed only in CPL=0 */
		if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
5504 5505 5506 5507
			if (ctxt->d & PrivUD)
				rc = emulate_ud(ctxt);
			else
				rc = emulate_gp(ctxt, 0);
5508
			goto done;
5509
		}
5510

5511
		/* Do instruction specific permission checks */
5512
		if (ctxt->d & CheckPerm) {
5513 5514 5515 5516 5517
			rc = ctxt->check_perm(ctxt);
			if (rc != X86EMUL_CONTINUE)
				goto done;
		}

5518
		if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) {
5519 5520 5521 5522 5523 5524 5525 5526 5527
			rc = emulator_check_intercept(ctxt, ctxt->intercept,
						      X86_ICPT_POST_EXCEPT);
			if (rc != X86EMUL_CONTINUE)
				goto done;
		}

		if (ctxt->rep_prefix && (ctxt->d & String)) {
			/* All REP prefixes have the same first termination condition */
			if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
5528
				string_registers_quirk(ctxt);
5529
				ctxt->eip = ctxt->_eip;
5530
				ctxt->eflags &= ~X86_EFLAGS_RF;
5531 5532
				goto done;
			}
5533 5534 5535
		}
	}

5536 5537 5538
	if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
		rc = segmented_read(ctxt, ctxt->src.addr.mem,
				    ctxt->src.valptr, ctxt->src.bytes);
5539
		if (rc != X86EMUL_CONTINUE)
5540
			goto done;
5541
		ctxt->src.orig_val64 = ctxt->src.val64;
5542 5543
	}

5544 5545 5546
	if (ctxt->src2.type == OP_MEM) {
		rc = segmented_read(ctxt, ctxt->src2.addr.mem,
				    &ctxt->src2.val, ctxt->src2.bytes);
5547 5548 5549 5550
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

5551
	if ((ctxt->d & DstMask) == ImplicitOps)
5552 5553 5554
		goto special_insn;


5555
	if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
5556
		/* optimisation - avoid slow emulated read if Mov */
5557 5558
		rc = segmented_read(ctxt, ctxt->dst.addr.mem,
				   &ctxt->dst.val, ctxt->dst.bytes);
5559
		if (rc != X86EMUL_CONTINUE) {
5560 5561
			if (!(ctxt->d & NoWrite) &&
			    rc == X86EMUL_PROPAGATE_FAULT &&
5562 5563
			    ctxt->exception.vector == PF_VECTOR)
				ctxt->exception.error_code |= PFERR_WRITE_MASK;
5564
			goto done;
5565
		}
5566
	}
5567 5568
	/* Copy full 64-bit value for CMPXCHG8B.  */
	ctxt->dst.orig_val64 = ctxt->dst.val64;
5569

5570 5571
special_insn:

5572
	if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) {
5573
		rc = emulator_check_intercept(ctxt, ctxt->intercept,
5574
					      X86_ICPT_POST_MEMACCESS);
5575 5576 5577 5578
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

5579
	if (ctxt->rep_prefix && (ctxt->d & String))
5580
		ctxt->eflags |= X86_EFLAGS_RF;
5581
	else
5582
		ctxt->eflags &= ~X86_EFLAGS_RF;
5583

5584
	if (ctxt->execute) {
5585 5586 5587 5588 5589 5590 5591
		if (ctxt->d & Fastop) {
			void (*fop)(struct fastop *) = (void *)ctxt->execute;
			rc = fastop(ctxt, fop);
			if (rc != X86EMUL_CONTINUE)
				goto done;
			goto writeback;
		}
5592
		rc = ctxt->execute(ctxt);
5593 5594 5595 5596 5597
		if (rc != X86EMUL_CONTINUE)
			goto done;
		goto writeback;
	}

B
Borislav Petkov 已提交
5598
	if (ctxt->opcode_len == 2)
A
Avi Kivity 已提交
5599
		goto twobyte_insn;
5600 5601
	else if (ctxt->opcode_len == 3)
		goto threebyte_insn;
A
Avi Kivity 已提交
5602

5603
	switch (ctxt->b) {
5604
	case 0x70 ... 0x7f: /* jcc (short) */
5605
		if (test_cc(ctxt->b, ctxt->eflags))
5606
			rc = jmp_rel(ctxt, ctxt->src.val);
5607
		break;
N
Nitin A Kamble 已提交
5608
	case 0x8d: /* lea r16/r32, m */
5609
		ctxt->dst.val = ctxt->src.addr.mem.ea;
N
Nitin A Kamble 已提交
5610
		break;
5611
	case 0x90 ... 0x97: /* nop / xchg reg, rax */
5612
		if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
5613 5614 5615
			ctxt->dst.type = OP_NONE;
		else
			rc = em_xchg(ctxt);
5616
		break;
5617
	case 0x98: /* cbw/cwde/cdqe */
5618 5619 5620 5621
		switch (ctxt->op_bytes) {
		case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
		case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
		case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
5622 5623
		}
		break;
5624
	case 0xcc:		/* int3 */
5625 5626
		rc = emulate_int(ctxt, 3);
		break;
5627
	case 0xcd:		/* int n */
5628
		rc = emulate_int(ctxt, ctxt->src.val);
5629 5630
		break;
	case 0xce:		/* into */
5631
		if (ctxt->eflags & X86_EFLAGS_OF)
5632
			rc = emulate_int(ctxt, 4);
5633
		break;
5634
	case 0xe9: /* jmp rel */
5635
	case 0xeb: /* jmp rel short */
5636
		rc = jmp_rel(ctxt, ctxt->src.val);
5637
		ctxt->dst.type = OP_NONE; /* Disable writeback. */
5638
		break;
5639
	case 0xf4:              /* hlt */
5640
		ctxt->ops->halt(ctxt);
5641
		break;
5642 5643
	case 0xf5:	/* cmc */
		/* complement carry flag from eflags reg */
5644
		ctxt->eflags ^= X86_EFLAGS_CF;
5645 5646
		break;
	case 0xf8: /* clc */
5647
		ctxt->eflags &= ~X86_EFLAGS_CF;
5648
		break;
5649
	case 0xf9: /* stc */
5650
		ctxt->eflags |= X86_EFLAGS_CF;
5651
		break;
5652
	case 0xfc: /* cld */
5653
		ctxt->eflags &= ~X86_EFLAGS_DF;
5654 5655
		break;
	case 0xfd: /* std */
5656
		ctxt->eflags |= X86_EFLAGS_DF;
5657
		break;
5658 5659
	default:
		goto cannot_emulate;
A
Avi Kivity 已提交
5660
	}
5661

5662 5663 5664
	if (rc != X86EMUL_CONTINUE)
		goto done;

5665
writeback:
5666 5667 5668 5669 5670 5671
	if (ctxt->d & SrcWrite) {
		BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
		rc = writeback(ctxt, &ctxt->src);
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}
5672 5673 5674 5675 5676
	if (!(ctxt->d & NoWrite)) {
		rc = writeback(ctxt, &ctxt->dst);
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}
5677

5678 5679 5680 5681
	/*
	 * restore dst type in case the decoding will be reused
	 * (happens for string instruction )
	 */
5682
	ctxt->dst.type = saved_dst_type;
5683

5684
	if ((ctxt->d & SrcMask) == SrcSI)
5685
		string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
5686

5687
	if ((ctxt->d & DstMask) == DstDI)
5688
		string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
5689

5690
	if (ctxt->rep_prefix && (ctxt->d & String)) {
5691
		unsigned int count;
5692
		struct read_cache *r = &ctxt->io_read;
5693 5694 5695 5696
		if ((ctxt->d & SrcMask) == SrcSI)
			count = ctxt->src.count;
		else
			count = ctxt->dst.count;
5697
		register_address_increment(ctxt, VCPU_REGS_RCX, -count);
5698

5699 5700 5701 5702 5703
		if (!string_insn_completed(ctxt)) {
			/*
			 * Re-enter guest when pio read ahead buffer is empty
			 * or, if it is not used, after each 1024 iteration.
			 */
5704
			if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
5705 5706 5707 5708 5709 5710
			    (r->end == 0 || r->end != r->pos)) {
				/*
				 * Reset read cache. Usually happens before
				 * decode, but since instruction is restarted
				 * we have to do it here.
				 */
5711
				ctxt->mem_read.end = 0;
5712
				writeback_registers(ctxt);
5713 5714 5715
				return EMULATION_RESTART;
			}
			goto done; /* skip rip writeback */
5716
		}
5717
		ctxt->eflags &= ~X86_EFLAGS_RF;
5718
	}
5719

5720
	ctxt->eip = ctxt->_eip;
5721 5722

done:
5723 5724
	if (rc == X86EMUL_PROPAGATE_FAULT) {
		WARN_ON(ctxt->exception.vector > 0x1f);
5725
		ctxt->have_exception = true;
5726
	}
5727 5728 5729
	if (rc == X86EMUL_INTERCEPTED)
		return EMULATION_INTERCEPTED;

5730 5731 5732
	if (rc == X86EMUL_CONTINUE)
		writeback_registers(ctxt);

5733
	return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
A
Avi Kivity 已提交
5734 5735

twobyte_insn:
5736
	switch (ctxt->b) {
5737
	case 0x09:		/* wbinvd */
5738
		(ctxt->ops->wbinvd)(ctxt);
5739 5740
		break;
	case 0x08:		/* invd */
5741 5742
	case 0x0d:		/* GrpP (prefetch) */
	case 0x18:		/* Grp16 (prefetch/nop) */
P
Paolo Bonzini 已提交
5743
	case 0x1f:		/* nop */
5744 5745
		break;
	case 0x20: /* mov cr, reg */
5746
		ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
5747
		break;
A
Avi Kivity 已提交
5748
	case 0x21: /* mov from dr to reg */
5749
		ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
A
Avi Kivity 已提交
5750 5751
		break;
	case 0x40 ... 0x4f:	/* cmov */
5752 5753
		if (test_cc(ctxt->b, ctxt->eflags))
			ctxt->dst.val = ctxt->src.val;
5754
		else if (ctxt->op_bytes != 4)
5755
			ctxt->dst.type = OP_NONE; /* no writeback */
A
Avi Kivity 已提交
5756
		break;
5757
	case 0x80 ... 0x8f: /* jnz rel, etc*/
5758
		if (test_cc(ctxt->b, ctxt->eflags))
5759
			rc = jmp_rel(ctxt, ctxt->src.val);
5760
		break;
5761
	case 0x90 ... 0x9f:     /* setcc r/m8 */
5762
		ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
5763
		break;
A
Avi Kivity 已提交
5764
	case 0xb6 ... 0xb7:	/* movzx */
5765
		ctxt->dst.bytes = ctxt->op_bytes;
5766
		ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
5767
						       : (u16) ctxt->src.val;
A
Avi Kivity 已提交
5768 5769
		break;
	case 0xbe ... 0xbf:	/* movsx */
5770
		ctxt->dst.bytes = ctxt->op_bytes;
5771
		ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
5772
							(s16) ctxt->src.val;
A
Avi Kivity 已提交
5773
		break;
5774 5775
	default:
		goto cannot_emulate;
A
Avi Kivity 已提交
5776
	}
5777

5778 5779
threebyte_insn:

5780 5781 5782
	if (rc != X86EMUL_CONTINUE)
		goto done;

A
Avi Kivity 已提交
5783 5784 5785
	goto writeback;

cannot_emulate:
5786
	return EMULATION_FAILED;
A
Avi Kivity 已提交
5787
}
5788 5789 5790 5791 5792 5793 5794 5795 5796 5797

void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
{
	invalidate_registers(ctxt);
}

void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
{
	writeback_registers(ctxt);
}
5798 5799 5800 5801 5802 5803 5804 5805 5806 5807 5808

bool emulator_can_use_gpa(struct x86_emulate_ctxt *ctxt)
{
	if (ctxt->rep_prefix && (ctxt->d & String))
		return false;

	if (ctxt->d & TwoMemOp)
		return false;

	return true;
}