emulate.c 116.5 KB
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/******************************************************************************
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 * emulate.c
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 *
 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
 *
 * Copyright (c) 2005 Keir Fraser
 *
 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
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 * privileged instructions:
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 *
 * Copyright (C) 2006 Qumranet
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 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
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 *
 *   Avi Kivity <avi@qumranet.com>
 *   Yaniv Kamay <yaniv@qumranet.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
 */

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#include <linux/kvm_host.h>
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#include "kvm_cache_regs.h"
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#include <linux/module.h>
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#include <asm/kvm_emulate.h>
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#include "x86.h"
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#include "tss.h"
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/*
 * Operand types
 */
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#define OpNone             0ull
#define OpImplicit         1ull  /* No generic decode */
#define OpReg              2ull  /* Register */
#define OpMem              3ull  /* Memory */
#define OpAcc              4ull  /* Accumulator: AL/AX/EAX/RAX */
#define OpDI               5ull  /* ES:DI/EDI/RDI */
#define OpMem64            6ull  /* Memory, 64-bit */
#define OpImmUByte         7ull  /* Zero-extended 8-bit immediate */
#define OpDX               8ull  /* DX register */
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#define OpCL               9ull  /* CL register (for shifts) */
#define OpImmByte         10ull  /* 8-bit sign extended immediate */
#define OpOne             11ull  /* Implied 1 */
#define OpImm             12ull  /* Sign extended immediate */
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#define OpMem16           13ull  /* Memory operand (16-bit). */
#define OpMem32           14ull  /* Memory operand (32-bit). */
#define OpImmU            15ull  /* Immediate operand, zero extended */
#define OpSI              16ull  /* SI/ESI/RSI */
#define OpImmFAddr        17ull  /* Immediate far address */
#define OpMemFAddr        18ull  /* Far address in memory */
#define OpImmU16          19ull  /* Immediate operand, 16 bits, zero extended */
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#define OpES              20ull  /* ES */
#define OpCS              21ull  /* CS */
#define OpSS              22ull  /* SS */
#define OpDS              23ull  /* DS */
#define OpFS              24ull  /* FS */
#define OpGS              25ull  /* GS */
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#define OpMem8            26ull  /* 8-bit zero extended memory operand */
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#define OpBits             5  /* Width of operand field */
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#define OpMask             ((1ull << OpBits) - 1)
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/*
 * Opcode effective-address decode tables.
 * Note that we only emulate instructions that have at least one memory
 * operand (excluding implicit stack references). We assume that stack
 * references and instruction fetches will never occur in special memory
 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
 * not be handled.
 */

/* Operand sizes: 8-bit operands or specified/overridden size. */
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#define ByteOp      (1<<0)	/* 8-bit operands. */
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/* Destination operand type. */
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#define DstShift    1
#define ImplicitOps (OpImplicit << DstShift)
#define DstReg      (OpReg << DstShift)
#define DstMem      (OpMem << DstShift)
#define DstAcc      (OpAcc << DstShift)
#define DstDI       (OpDI << DstShift)
#define DstMem64    (OpMem64 << DstShift)
#define DstImmUByte (OpImmUByte << DstShift)
#define DstDX       (OpDX << DstShift)
#define DstMask     (OpMask << DstShift)
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/* Source operand type. */
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#define SrcShift    6
#define SrcNone     (OpNone << SrcShift)
#define SrcReg      (OpReg << SrcShift)
#define SrcMem      (OpMem << SrcShift)
#define SrcMem16    (OpMem16 << SrcShift)
#define SrcMem32    (OpMem32 << SrcShift)
#define SrcImm      (OpImm << SrcShift)
#define SrcImmByte  (OpImmByte << SrcShift)
#define SrcOne      (OpOne << SrcShift)
#define SrcImmUByte (OpImmUByte << SrcShift)
#define SrcImmU     (OpImmU << SrcShift)
#define SrcSI       (OpSI << SrcShift)
#define SrcImmFAddr (OpImmFAddr << SrcShift)
#define SrcMemFAddr (OpMemFAddr << SrcShift)
#define SrcAcc      (OpAcc << SrcShift)
#define SrcImmU16   (OpImmU16 << SrcShift)
#define SrcDX       (OpDX << SrcShift)
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#define SrcMem8     (OpMem8 << SrcShift)
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#define SrcMask     (OpMask << SrcShift)
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#define BitOp       (1<<11)
#define MemAbs      (1<<12)      /* Memory operand is absolute displacement */
#define String      (1<<13)     /* String instruction (rep capable) */
#define Stack       (1<<14)     /* Stack instruction (push/pop) */
#define GroupMask   (7<<15)     /* Opcode uses one of the group mechanisms */
#define Group       (1<<15)     /* Bits 3:5 of modrm byte extend opcode */
#define GroupDual   (2<<15)     /* Alternate decoding of mod == 3 */
#define Prefix      (3<<15)     /* Instruction varies with 66/f2/f3 prefix */
#define RMExt       (4<<15)     /* Opcode extension in ModRM r/m if mod == 3 */
#define Sse         (1<<18)     /* SSE Vector instruction */
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/* Generic ModRM decode. */
#define ModRM       (1<<19)
/* Destination is only written; never read. */
#define Mov         (1<<20)
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/* Misc flags */
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#define Prot        (1<<21) /* instruction generates #UD if not in prot-mode */
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#define VendorSpecific (1<<22) /* Vendor specific instruction */
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#define NoAccess    (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
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#define Op3264      (1<<24) /* Operand is 64b in long mode, 32b otherwise */
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#define Undefined   (1<<25) /* No Such Instruction */
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#define Lock        (1<<26) /* lock prefix is allowed for the instruction */
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#define Priv        (1<<27) /* instruction generates #GP if current CPL != 0 */
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#define No64	    (1<<28)
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#define PageTable   (1 << 29)   /* instruction used to write page table */
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/* Source 2 operand type */
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#define Src2Shift   (30)
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#define Src2None    (OpNone << Src2Shift)
#define Src2CL      (OpCL << Src2Shift)
#define Src2ImmByte (OpImmByte << Src2Shift)
#define Src2One     (OpOne << Src2Shift)
#define Src2Imm     (OpImm << Src2Shift)
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#define Src2ES      (OpES << Src2Shift)
#define Src2CS      (OpCS << Src2Shift)
#define Src2SS      (OpSS << Src2Shift)
#define Src2DS      (OpDS << Src2Shift)
#define Src2FS      (OpFS << Src2Shift)
#define Src2GS      (OpGS << Src2Shift)
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#define Src2Mask    (OpMask << Src2Shift)
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#define Mmx         ((u64)1 << 40)  /* MMX Vector instruction */
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#define Aligned     ((u64)1 << 41)  /* Explicitly aligned (e.g. MOVDQA) */
#define Unaligned   ((u64)1 << 42)  /* Explicitly unaligned (e.g. MOVDQU) */
#define Avx         ((u64)1 << 43)  /* Advanced Vector Extensions */
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#define X2(x...) x, x
#define X3(x...) X2(x), x
#define X4(x...) X2(x), X2(x)
#define X5(x...) X4(x), x
#define X6(x...) X4(x), X2(x)
#define X7(x...) X4(x), X3(x)
#define X8(x...) X4(x), X4(x)
#define X16(x...) X8(x), X8(x)
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struct opcode {
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	u64 flags : 56;
	u64 intercept : 8;
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	union {
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		int (*execute)(struct x86_emulate_ctxt *ctxt);
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		struct opcode *group;
		struct group_dual *gdual;
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		struct gprefix *gprefix;
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	} u;
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	int (*check_perm)(struct x86_emulate_ctxt *ctxt);
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};

struct group_dual {
	struct opcode mod012[8];
	struct opcode mod3[8];
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};

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struct gprefix {
	struct opcode pfx_no;
	struct opcode pfx_66;
	struct opcode pfx_f2;
	struct opcode pfx_f3;
};

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/* EFLAGS bit definitions. */
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#define EFLG_ID (1<<21)
#define EFLG_VIP (1<<20)
#define EFLG_VIF (1<<19)
#define EFLG_AC (1<<18)
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#define EFLG_VM (1<<17)
#define EFLG_RF (1<<16)
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#define EFLG_IOPL (3<<12)
#define EFLG_NT (1<<14)
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#define EFLG_OF (1<<11)
#define EFLG_DF (1<<10)
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#define EFLG_IF (1<<9)
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#define EFLG_TF (1<<8)
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#define EFLG_SF (1<<7)
#define EFLG_ZF (1<<6)
#define EFLG_AF (1<<4)
#define EFLG_PF (1<<2)
#define EFLG_CF (1<<0)

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#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
#define EFLG_RESERVED_ONE_MASK 2

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/*
 * Instruction emulation:
 * Most instructions are emulated directly via a fragment of inline assembly
 * code. This allows us to save/restore EFLAGS and thus very easily pick up
 * any modified flags.
 */

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#if defined(CONFIG_X86_64)
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#define _LO32 "k"		/* force 32-bit operand */
#define _STK  "%%rsp"		/* stack pointer */
#elif defined(__i386__)
#define _LO32 ""		/* force 32-bit operand */
#define _STK  "%%esp"		/* stack pointer */
#endif

/*
 * These EFLAGS bits are restored from saved value during emulation, and
 * any changes are written back to the saved value after emulation.
 */
#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)

/* Before executing instruction: restore necessary bits in EFLAGS. */
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#define _PRE_EFLAGS(_sav, _msk, _tmp)					\
	/* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
	"movl %"_sav",%"_LO32 _tmp"; "                                  \
	"push %"_tmp"; "                                                \
	"push %"_tmp"; "                                                \
	"movl %"_msk",%"_LO32 _tmp"; "                                  \
	"andl %"_LO32 _tmp",("_STK"); "                                 \
	"pushf; "                                                       \
	"notl %"_LO32 _tmp"; "                                          \
	"andl %"_LO32 _tmp",("_STK"); "                                 \
	"andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); "	\
	"pop  %"_tmp"; "                                                \
	"orl  %"_LO32 _tmp",("_STK"); "                                 \
	"popf; "                                                        \
	"pop  %"_sav"; "
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/* After executing instruction: write-back necessary bits in EFLAGS. */
#define _POST_EFLAGS(_sav, _msk, _tmp) \
	/* _sav |= EFLAGS & _msk; */		\
	"pushf; "				\
	"pop  %"_tmp"; "			\
	"andl %"_msk",%"_LO32 _tmp"; "		\
	"orl  %"_LO32 _tmp",%"_sav"; "

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#ifdef CONFIG_X86_64
#define ON64(x) x
#else
#define ON64(x)
#endif

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#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype)	\
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	do {								\
		__asm__ __volatile__ (					\
			_PRE_EFLAGS("0", "4", "2")			\
			_op _suffix " %"_x"3,%1; "			\
			_POST_EFLAGS("0", "4", "2")			\
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			: "=m" ((ctxt)->eflags),			\
			  "+q" (*(_dsttype*)&(ctxt)->dst.val),		\
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			  "=&r" (_tmp)					\
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			: _y ((ctxt)->src.val), "i" (EFLAGS_MASK));	\
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	} while (0)
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/* Raw emulation: instruction has two explicit operands. */
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#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy)		\
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	do {								\
		unsigned long _tmp;					\
									\
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		switch ((ctxt)->dst.bytes) {				\
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		case 2:							\
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			____emulate_2op(ctxt,_op,_wx,_wy,"w",u16);	\
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			break;						\
		case 4:							\
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			____emulate_2op(ctxt,_op,_lx,_ly,"l",u32);	\
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			break;						\
		case 8:							\
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			ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
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			break;						\
		}							\
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	} while (0)

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#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy)		     \
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	do {								     \
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		unsigned long _tmp;					     \
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		switch ((ctxt)->dst.bytes) {				     \
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		case 1:							     \
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			____emulate_2op(ctxt,_op,_bx,_by,"b",u8);	     \
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			break;						     \
		default:						     \
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			__emulate_2op_nobyte(ctxt, _op,			     \
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					     _wx, _wy, _lx, _ly, _qx, _qy);  \
			break;						     \
		}							     \
	} while (0)

/* Source operand is byte-sized and may be restricted to just %cl. */
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#define emulate_2op_SrcB(ctxt, _op)					\
	__emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
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/* Source operand is byte, word, long or quad sized. */
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#define emulate_2op_SrcV(ctxt, _op)					\
	__emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
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/* Source operand is word, long or quad sized. */
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#define emulate_2op_SrcV_nobyte(ctxt, _op)				\
	__emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
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/* Instruction has three operands and one operand is stored in ECX register */
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#define __emulate_2op_cl(ctxt, _op, _suffix, _type)		\
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	do {								\
		unsigned long _tmp;					\
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		_type _clv  = (ctxt)->src2.val;				\
		_type _srcv = (ctxt)->src.val;				\
		_type _dstv = (ctxt)->dst.val;				\
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									\
		__asm__ __volatile__ (					\
			_PRE_EFLAGS("0", "5", "2")			\
			_op _suffix " %4,%1 \n"				\
			_POST_EFLAGS("0", "5", "2")			\
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			: "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
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			: "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK)	\
			);						\
									\
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		(ctxt)->src2.val  = (unsigned long) _clv;		\
		(ctxt)->src2.val = (unsigned long) _srcv;		\
		(ctxt)->dst.val = (unsigned long) _dstv;		\
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	} while (0)

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#define emulate_2op_cl(ctxt, _op)					\
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	do {								\
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		switch ((ctxt)->dst.bytes) {				\
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		case 2:							\
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			__emulate_2op_cl(ctxt, _op, "w", u16);		\
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			break;						\
		case 4:							\
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			__emulate_2op_cl(ctxt, _op, "l", u32);		\
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			break;						\
		case 8:							\
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			ON64(__emulate_2op_cl(ctxt, _op, "q", ulong));	\
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			break;						\
		}							\
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	} while (0)

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#define __emulate_1op(ctxt, _op, _suffix)				\
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	do {								\
		unsigned long _tmp;					\
									\
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		__asm__ __volatile__ (					\
			_PRE_EFLAGS("0", "3", "2")			\
			_op _suffix " %1; "				\
			_POST_EFLAGS("0", "3", "2")			\
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			: "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
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			  "=&r" (_tmp)					\
			: "i" (EFLAGS_MASK));				\
	} while (0)

/* Instruction has only one explicit operand (no source operand). */
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#define emulate_1op(ctxt, _op)						\
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	do {								\
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		switch ((ctxt)->dst.bytes) {				\
		case 1:	__emulate_1op(ctxt, _op, "b"); break;		\
		case 2:	__emulate_1op(ctxt, _op, "w"); break;		\
		case 4:	__emulate_1op(ctxt, _op, "l"); break;		\
		case 8:	ON64(__emulate_1op(ctxt, _op, "q")); break;	\
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		}							\
	} while (0)

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#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex)			\
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	do {								\
		unsigned long _tmp;					\
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		ulong *rax = &(ctxt)->regs[VCPU_REGS_RAX];		\
		ulong *rdx = &(ctxt)->regs[VCPU_REGS_RDX];		\
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									\
		__asm__ __volatile__ (					\
			_PRE_EFLAGS("0", "5", "1")			\
			"1: \n\t"					\
			_op _suffix " %6; "				\
			"2: \n\t"					\
			_POST_EFLAGS("0", "5", "1")			\
			".pushsection .fixup,\"ax\" \n\t"		\
			"3: movb $1, %4 \n\t"				\
			"jmp 2b \n\t"					\
			".popsection \n\t"				\
			_ASM_EXTABLE(1b, 3b)				\
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			: "=m" ((ctxt)->eflags), "=&r" (_tmp),		\
			  "+a" (*rax), "+d" (*rdx), "+qm"(_ex)		\
			: "i" (EFLAGS_MASK), "m" ((ctxt)->src.val),	\
			  "a" (*rax), "d" (*rdx));			\
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	} while (0)

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/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
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#define emulate_1op_rax_rdx(ctxt, _op, _ex)	\
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	do {								\
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		switch((ctxt)->src.bytes) {				\
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		case 1:							\
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			__emulate_1op_rax_rdx(ctxt, _op, "b", _ex);	\
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			break;						\
		case 2:							\
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			__emulate_1op_rax_rdx(ctxt, _op, "w", _ex);	\
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			break;						\
		case 4:							\
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			__emulate_1op_rax_rdx(ctxt, _op, "l", _ex);	\
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			break;						\
		case 8: ON64(						\
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			__emulate_1op_rax_rdx(ctxt, _op, "q", _ex));	\
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			break;						\
		}							\
	} while (0)

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static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
				    enum x86_intercept intercept,
				    enum x86_intercept_stage stage)
{
	struct x86_instruction_info info = {
		.intercept  = intercept,
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		.rep_prefix = ctxt->rep_prefix,
		.modrm_mod  = ctxt->modrm_mod,
		.modrm_reg  = ctxt->modrm_reg,
		.modrm_rm   = ctxt->modrm_rm,
		.src_val    = ctxt->src.val64,
		.src_bytes  = ctxt->src.bytes,
		.dst_bytes  = ctxt->dst.bytes,
		.ad_bytes   = ctxt->ad_bytes,
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		.next_rip   = ctxt->eip,
	};

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	return ctxt->ops->intercept(ctxt, &info, stage);
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}

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static void assign_masked(ulong *dest, ulong src, ulong mask)
{
	*dest = (*dest & ~mask) | (src & mask);
}

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static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
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{
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	return (1UL << (ctxt->ad_bytes << 3)) - 1;
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}

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static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
{
	u16 sel;
	struct desc_struct ss;

	if (ctxt->mode == X86EMUL_MODE_PROT64)
		return ~0UL;
	ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
	return ~0U >> ((ss.d ^ 1) * 16);  /* d=0: 0xffff; d=1: 0xffffffff */
}

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/* Access/update address held in a register, based on addressing mode. */
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static inline unsigned long
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address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
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{
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	if (ctxt->ad_bytes == sizeof(unsigned long))
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		return reg;
	else
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		return reg & ad_mask(ctxt);
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}

static inline unsigned long
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register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
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{
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	return address_mask(ctxt, reg);
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}

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static inline void
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register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
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{
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	if (ctxt->ad_bytes == sizeof(unsigned long))
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		*reg += inc;
	else
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		*reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt));
480
}
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481

482
static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
483
{
484
	register_address_increment(ctxt, &ctxt->_eip, rel);
485
}
486

487 488 489 490 491 492 493
static u32 desc_limit_scaled(struct desc_struct *desc)
{
	u32 limit = get_desc_limit(desc);

	return desc->g ? (limit << 12) | 0xfff : limit;
}

494
static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
495
{
496 497
	ctxt->has_seg_override = true;
	ctxt->seg_override = seg;
498 499
}

500
static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
501 502 503 504
{
	if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
		return 0;

505
	return ctxt->ops->get_cached_segment_base(ctxt, seg);
506 507
}

508
static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
509
{
510
	if (!ctxt->has_seg_override)
511 512
		return 0;

513
	return ctxt->seg_override;
514 515
}

516 517
static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
			     u32 error, bool valid)
518
{
519 520 521
	ctxt->exception.vector = vec;
	ctxt->exception.error_code = error;
	ctxt->exception.error_code_valid = valid;
522
	return X86EMUL_PROPAGATE_FAULT;
523 524
}

525 526 527 528 529
static int emulate_db(struct x86_emulate_ctxt *ctxt)
{
	return emulate_exception(ctxt, DB_VECTOR, 0, false);
}

530
static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
531
{
532
	return emulate_exception(ctxt, GP_VECTOR, err, true);
533 534
}

535 536 537 538 539
static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
{
	return emulate_exception(ctxt, SS_VECTOR, err, true);
}

540
static int emulate_ud(struct x86_emulate_ctxt *ctxt)
541
{
542
	return emulate_exception(ctxt, UD_VECTOR, 0, false);
543 544
}

545
static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
546
{
547
	return emulate_exception(ctxt, TS_VECTOR, err, true);
548 549
}

550 551
static int emulate_de(struct x86_emulate_ctxt *ctxt)
{
552
	return emulate_exception(ctxt, DE_VECTOR, 0, false);
553 554
}

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static int emulate_nm(struct x86_emulate_ctxt *ctxt)
{
	return emulate_exception(ctxt, NM_VECTOR, 0, false);
}

560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579
static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
{
	u16 selector;
	struct desc_struct desc;

	ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
	return selector;
}

static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
				 unsigned seg)
{
	u16 dummy;
	u32 base3;
	struct desc_struct desc;

	ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
	ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
}

580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602
/*
 * x86 defines three classes of vector instructions: explicitly
 * aligned, explicitly unaligned, and the rest, which change behaviour
 * depending on whether they're AVX encoded or not.
 *
 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
 * subject to the same check.
 */
static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
{
	if (likely(size < 16))
		return false;

	if (ctxt->d & Aligned)
		return true;
	else if (ctxt->d & Unaligned)
		return false;
	else if (ctxt->d & Avx)
		return false;
	else
		return true;
}

603
static int __linearize(struct x86_emulate_ctxt *ctxt,
604
		     struct segmented_address addr,
605
		     unsigned size, bool write, bool fetch,
606 607
		     ulong *linear)
{
608 609
	struct desc_struct desc;
	bool usable;
610
	ulong la;
611
	u32 lim;
612
	u16 sel;
613
	unsigned cpl, rpl;
614

615
	la = seg_base(ctxt, addr.seg) + addr.ea;
616 617 618 619 620 621 622 623
	switch (ctxt->mode) {
	case X86EMUL_MODE_REAL:
		break;
	case X86EMUL_MODE_PROT64:
		if (((signed long)la << 16) >> 16 != la)
			return emulate_gp(ctxt, 0);
		break;
	default:
624 625
		usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
						addr.seg);
626 627 628 629 630 631
		if (!usable)
			goto bad;
		/* code segment or read-only data segment */
		if (((desc.type & 8) || !(desc.type & 2)) && write)
			goto bad;
		/* unreadable code segment */
632
		if (!fetch && (desc.type & 8) && !(desc.type & 2))
633 634 635 636 637 638 639 640 641 642 643 644 645 646
			goto bad;
		lim = desc_limit_scaled(&desc);
		if ((desc.type & 8) || !(desc.type & 4)) {
			/* expand-up segment */
			if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
				goto bad;
		} else {
			/* exapand-down segment */
			if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
				goto bad;
			lim = desc.d ? 0xffffffff : 0xffff;
			if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
				goto bad;
		}
647
		cpl = ctxt->ops->cpl(ctxt);
648
		rpl = sel & 3;
649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664
		cpl = max(cpl, rpl);
		if (!(desc.type & 8)) {
			/* data segment */
			if (cpl > desc.dpl)
				goto bad;
		} else if ((desc.type & 8) && !(desc.type & 4)) {
			/* nonconforming code segment */
			if (cpl != desc.dpl)
				goto bad;
		} else if ((desc.type & 8) && (desc.type & 4)) {
			/* conforming code segment */
			if (cpl < desc.dpl)
				goto bad;
		}
		break;
	}
665
	if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
666
		la &= (u32)-1;
667 668
	if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
		return emulate_gp(ctxt, 0);
669 670
	*linear = la;
	return X86EMUL_CONTINUE;
671 672 673 674 675
bad:
	if (addr.seg == VCPU_SREG_SS)
		return emulate_ss(ctxt, addr.seg);
	else
		return emulate_gp(ctxt, addr.seg);
676 677
}

678 679 680 681 682 683 684 685 686
static int linearize(struct x86_emulate_ctxt *ctxt,
		     struct segmented_address addr,
		     unsigned size, bool write,
		     ulong *linear)
{
	return __linearize(ctxt, addr, size, write, false, linear);
}


687 688 689 690 691
static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
			      struct segmented_address addr,
			      void *data,
			      unsigned size)
{
692 693 694
	int rc;
	ulong linear;

695
	rc = linearize(ctxt, addr, size, false, &linear);
696 697
	if (rc != X86EMUL_CONTINUE)
		return rc;
698
	return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
699 700
}

701 702 703 704 705 706 707 708
/*
 * Fetch the next byte of the instruction being emulated which is pointed to
 * by ctxt->_eip, then increment ctxt->_eip.
 *
 * Also prefetch the remaining bytes of the instruction without crossing page
 * boundary if they are not in fetch_cache yet.
 */
static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
709
{
710
	struct fetch_cache *fc = &ctxt->fetch;
711
	int rc;
712
	int size, cur_size;
713

714
	if (ctxt->_eip == fc->end) {
715
		unsigned long linear;
716 717
		struct segmented_address addr = { .seg = VCPU_SREG_CS,
						  .ea  = ctxt->_eip };
718
		cur_size = fc->end - fc->start;
719 720
		size = min(15UL - cur_size,
			   PAGE_SIZE - offset_in_page(ctxt->_eip));
721
		rc = __linearize(ctxt, addr, size, false, true, &linear);
722
		if (unlikely(rc != X86EMUL_CONTINUE))
723
			return rc;
724 725
		rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
				      size, &ctxt->exception);
726
		if (unlikely(rc != X86EMUL_CONTINUE))
727
			return rc;
728
		fc->end += size;
729
	}
730 731
	*dest = fc->data[ctxt->_eip - fc->start];
	ctxt->_eip++;
732
	return X86EMUL_CONTINUE;
733 734 735
}

static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
736
			 void *dest, unsigned size)
737
{
738
	int rc;
739

740
	/* x86 instructions are limited to 15 bytes. */
741
	if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
742
		return X86EMUL_UNHANDLEABLE;
743
	while (size--) {
744
		rc = do_insn_fetch_byte(ctxt, dest++);
745
		if (rc != X86EMUL_CONTINUE)
746 747
			return rc;
	}
748
	return X86EMUL_CONTINUE;
749 750
}

751
/* Fetch next part of the instruction being emulated. */
752
#define insn_fetch(_type, _ctxt)					\
753
({	unsigned long _x;						\
754
	rc = do_insn_fetch(_ctxt, &_x, sizeof(_type));			\
755 756 757 758 759
	if (rc != X86EMUL_CONTINUE)					\
		goto done;						\
	(_type)_x;							\
})

760 761
#define insn_fetch_arr(_arr, _size, _ctxt)				\
({	rc = do_insn_fetch(_ctxt, _arr, (_size));			\
762 763 764 765
	if (rc != X86EMUL_CONTINUE)					\
		goto done;						\
})

766 767 768 769 770 771 772
/*
 * Given the 'reg' portion of a ModRM byte, and a register block, return a
 * pointer into the block that addresses the relevant register.
 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
 */
static void *decode_register(u8 modrm_reg, unsigned long *regs,
			     int highbyte_regs)
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{
	void *p;

	p = &regs[modrm_reg];
	if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
		p = (unsigned char *)&regs[modrm_reg & 3] + 1;
	return p;
}

static int read_descriptor(struct x86_emulate_ctxt *ctxt,
783
			   struct segmented_address addr,
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			   u16 *size, unsigned long *address, int op_bytes)
{
	int rc;

	if (op_bytes == 2)
		op_bytes = 3;
	*address = 0;
791
	rc = segmented_read_std(ctxt, addr, size, 2);
792
	if (rc != X86EMUL_CONTINUE)
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		return rc;
794
	addr.ea += 2;
795
	rc = segmented_read_std(ctxt, addr, address, op_bytes);
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	return rc;
}

799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833
static int test_cc(unsigned int condition, unsigned int flags)
{
	int rc = 0;

	switch ((condition & 15) >> 1) {
	case 0: /* o */
		rc |= (flags & EFLG_OF);
		break;
	case 1: /* b/c/nae */
		rc |= (flags & EFLG_CF);
		break;
	case 2: /* z/e */
		rc |= (flags & EFLG_ZF);
		break;
	case 3: /* be/na */
		rc |= (flags & (EFLG_CF|EFLG_ZF));
		break;
	case 4: /* s */
		rc |= (flags & EFLG_SF);
		break;
	case 5: /* p/pe */
		rc |= (flags & EFLG_PF);
		break;
	case 7: /* le/ng */
		rc |= (flags & EFLG_ZF);
		/* fall through */
	case 6: /* l/nge */
		rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
		break;
	}

	/* Odd condition identifiers (lsb == 1) have inverted sense. */
	return (!!rc ^ (condition & 1));
}

834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851
static void fetch_register_operand(struct operand *op)
{
	switch (op->bytes) {
	case 1:
		op->val = *(u8 *)op->addr.reg;
		break;
	case 2:
		op->val = *(u16 *)op->addr.reg;
		break;
	case 4:
		op->val = *(u32 *)op->addr.reg;
		break;
	case 8:
		op->val = *(u64 *)op->addr.reg;
		break;
	}
}

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static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
{
	ctxt->ops->get_fpu(ctxt);
	switch (reg) {
	case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
	case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
	case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
	case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
	case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
	case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
	case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
	case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
#ifdef CONFIG_X86_64
	case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
	case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
	case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
	case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
	case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
	case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
	case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
	case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
#endif
	default: BUG();
	}
	ctxt->ops->put_fpu(ctxt);
}

static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
			  int reg)
{
	ctxt->ops->get_fpu(ctxt);
	switch (reg) {
	case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
	case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
	case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
	case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
	case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
	case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
	case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
	case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
#ifdef CONFIG_X86_64
	case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
	case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
	case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
	case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
	case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
	case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
	case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
	case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
#endif
	default: BUG();
	}
	ctxt->ops->put_fpu(ctxt);
}

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static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
{
	ctxt->ops->get_fpu(ctxt);
	switch (reg) {
	case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
	case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
	case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
	case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
	case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
	case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
	case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
	case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
	default: BUG();
	}
	ctxt->ops->put_fpu(ctxt);
}

static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
{
	ctxt->ops->get_fpu(ctxt);
	switch (reg) {
	case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
	case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
	case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
	case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
	case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
	case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
	case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
	case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
	default: BUG();
	}
	ctxt->ops->put_fpu(ctxt);
}

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static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
942
				    struct operand *op)
943
{
944 945
	unsigned reg = ctxt->modrm_reg;
	int highbyte_regs = ctxt->rex_prefix == 0;
946

947 948
	if (!(ctxt->d & ModRM))
		reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
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950
	if (ctxt->d & Sse) {
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		op->type = OP_XMM;
		op->bytes = 16;
		op->addr.xmm = reg;
		read_sse_reg(ctxt, &op->vec_val, reg);
		return;
	}
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	if (ctxt->d & Mmx) {
		reg &= 7;
		op->type = OP_MM;
		op->bytes = 8;
		op->addr.mm = reg;
		return;
	}
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964

965
	op->type = OP_REG;
966
	if (ctxt->d & ByteOp) {
967
		op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs);
968 969
		op->bytes = 1;
	} else {
970 971
		op->addr.reg = decode_register(reg, ctxt->regs, 0);
		op->bytes = ctxt->op_bytes;
972
	}
973
	fetch_register_operand(op);
974 975 976
	op->orig_val = op->val;
}

977 978 979 980 981 982
static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
{
	if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
		ctxt->modrm_seg = VCPU_SREG_SS;
}

983
static int decode_modrm(struct x86_emulate_ctxt *ctxt,
984
			struct operand *op)
985 986
{
	u8 sib;
987
	int index_reg = 0, base_reg = 0, scale;
988
	int rc = X86EMUL_CONTINUE;
989
	ulong modrm_ea = 0;
990

991 992 993 994
	if (ctxt->rex_prefix) {
		ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1;	/* REX.R */
		index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
		ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
995 996
	}

997 998 999 1000
	ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
	ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
	ctxt->modrm_rm |= (ctxt->modrm & 0x07);
	ctxt->modrm_seg = VCPU_SREG_DS;
1001

1002
	if (ctxt->modrm_mod == 3) {
1003
		op->type = OP_REG;
1004 1005 1006 1007
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		op->addr.reg = decode_register(ctxt->modrm_rm,
					       ctxt->regs, ctxt->d & ByteOp);
		if (ctxt->d & Sse) {
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			op->type = OP_XMM;
			op->bytes = 16;
1010 1011
			op->addr.xmm = ctxt->modrm_rm;
			read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
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			return rc;
		}
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		if (ctxt->d & Mmx) {
			op->type = OP_MM;
			op->bytes = 8;
			op->addr.xmm = ctxt->modrm_rm & 7;
			return rc;
		}
1020
		fetch_register_operand(op);
1021 1022 1023
		return rc;
	}

1024 1025
	op->type = OP_MEM;

1026 1027 1028 1029 1030
	if (ctxt->ad_bytes == 2) {
		unsigned bx = ctxt->regs[VCPU_REGS_RBX];
		unsigned bp = ctxt->regs[VCPU_REGS_RBP];
		unsigned si = ctxt->regs[VCPU_REGS_RSI];
		unsigned di = ctxt->regs[VCPU_REGS_RDI];
1031 1032

		/* 16-bit ModR/M decode. */
1033
		switch (ctxt->modrm_mod) {
1034
		case 0:
1035
			if (ctxt->modrm_rm == 6)
1036
				modrm_ea += insn_fetch(u16, ctxt);
1037 1038
			break;
		case 1:
1039
			modrm_ea += insn_fetch(s8, ctxt);
1040 1041
			break;
		case 2:
1042
			modrm_ea += insn_fetch(u16, ctxt);
1043 1044
			break;
		}
1045
		switch (ctxt->modrm_rm) {
1046
		case 0:
1047
			modrm_ea += bx + si;
1048 1049
			break;
		case 1:
1050
			modrm_ea += bx + di;
1051 1052
			break;
		case 2:
1053
			modrm_ea += bp + si;
1054 1055
			break;
		case 3:
1056
			modrm_ea += bp + di;
1057 1058
			break;
		case 4:
1059
			modrm_ea += si;
1060 1061
			break;
		case 5:
1062
			modrm_ea += di;
1063 1064
			break;
		case 6:
1065
			if (ctxt->modrm_mod != 0)
1066
				modrm_ea += bp;
1067 1068
			break;
		case 7:
1069
			modrm_ea += bx;
1070 1071
			break;
		}
1072 1073 1074
		if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
		    (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
			ctxt->modrm_seg = VCPU_SREG_SS;
1075
		modrm_ea = (u16)modrm_ea;
1076 1077
	} else {
		/* 32/64-bit ModR/M decode. */
1078
		if ((ctxt->modrm_rm & 7) == 4) {
1079
			sib = insn_fetch(u8, ctxt);
1080 1081 1082 1083
			index_reg |= (sib >> 3) & 7;
			base_reg |= sib & 7;
			scale = sib >> 6;

1084
			if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
1085
				modrm_ea += insn_fetch(s32, ctxt);
1086
			else {
1087
				modrm_ea += ctxt->regs[base_reg];
1088 1089
				adjust_modrm_seg(ctxt, base_reg);
			}
1090
			if (index_reg != 4)
1091 1092
				modrm_ea += ctxt->regs[index_reg] << scale;
		} else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
1093
			if (ctxt->mode == X86EMUL_MODE_PROT64)
1094
				ctxt->rip_relative = 1;
1095 1096 1097 1098 1099
		} else {
			base_reg = ctxt->modrm_rm;
			modrm_ea += ctxt->regs[base_reg];
			adjust_modrm_seg(ctxt, base_reg);
		}
1100
		switch (ctxt->modrm_mod) {
1101
		case 0:
1102
			if (ctxt->modrm_rm == 5)
1103
				modrm_ea += insn_fetch(s32, ctxt);
1104 1105
			break;
		case 1:
1106
			modrm_ea += insn_fetch(s8, ctxt);
1107 1108
			break;
		case 2:
1109
			modrm_ea += insn_fetch(s32, ctxt);
1110 1111 1112
			break;
		}
	}
1113
	op->addr.mem.ea = modrm_ea;
1114 1115 1116 1117 1118
done:
	return rc;
}

static int decode_abs(struct x86_emulate_ctxt *ctxt,
1119
		      struct operand *op)
1120
{
1121
	int rc = X86EMUL_CONTINUE;
1122

1123
	op->type = OP_MEM;
1124
	switch (ctxt->ad_bytes) {
1125
	case 2:
1126
		op->addr.mem.ea = insn_fetch(u16, ctxt);
1127 1128
		break;
	case 4:
1129
		op->addr.mem.ea = insn_fetch(u32, ctxt);
1130 1131
		break;
	case 8:
1132
		op->addr.mem.ea = insn_fetch(u64, ctxt);
1133 1134 1135 1136 1137 1138
		break;
	}
done:
	return rc;
}

1139
static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
1140
{
1141
	long sv = 0, mask;
1142

1143 1144
	if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
		mask = ~(ctxt->dst.bytes * 8 - 1);
1145

1146 1147 1148 1149
		if (ctxt->src.bytes == 2)
			sv = (s16)ctxt->src.val & (s16)mask;
		else if (ctxt->src.bytes == 4)
			sv = (s32)ctxt->src.val & (s32)mask;
1150

1151
		ctxt->dst.addr.mem.ea += (sv >> 3);
1152
	}
1153 1154

	/* only subword offset */
1155
	ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
1156 1157
}

1158 1159
static int read_emulated(struct x86_emulate_ctxt *ctxt,
			 unsigned long addr, void *dest, unsigned size)
A
Avi Kivity 已提交
1160
{
1161
	int rc;
1162
	struct read_cache *mc = &ctxt->mem_read;
A
Avi Kivity 已提交
1163

1164 1165 1166 1167 1168
	while (size) {
		int n = min(size, 8u);
		size -= n;
		if (mc->pos < mc->end)
			goto read_cached;
1169

1170 1171
		rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
					      &ctxt->exception);
1172 1173 1174
		if (rc != X86EMUL_CONTINUE)
			return rc;
		mc->end += n;
A
Avi Kivity 已提交
1175

1176 1177 1178 1179 1180
	read_cached:
		memcpy(dest, mc->data + mc->pos, n);
		mc->pos += n;
		dest += n;
		addr += n;
A
Avi Kivity 已提交
1181
	}
1182 1183
	return X86EMUL_CONTINUE;
}
A
Avi Kivity 已提交
1184

1185 1186 1187 1188 1189
static int segmented_read(struct x86_emulate_ctxt *ctxt,
			  struct segmented_address addr,
			  void *data,
			  unsigned size)
{
1190 1191 1192
	int rc;
	ulong linear;

1193
	rc = linearize(ctxt, addr, size, false, &linear);
1194 1195
	if (rc != X86EMUL_CONTINUE)
		return rc;
1196
	return read_emulated(ctxt, linear, data, size);
1197 1198 1199 1200 1201 1202 1203
}

static int segmented_write(struct x86_emulate_ctxt *ctxt,
			   struct segmented_address addr,
			   const void *data,
			   unsigned size)
{
1204 1205 1206
	int rc;
	ulong linear;

1207
	rc = linearize(ctxt, addr, size, true, &linear);
1208 1209
	if (rc != X86EMUL_CONTINUE)
		return rc;
1210 1211
	return ctxt->ops->write_emulated(ctxt, linear, data, size,
					 &ctxt->exception);
1212 1213 1214 1215 1216 1217 1218
}

static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
			     struct segmented_address addr,
			     const void *orig_data, const void *data,
			     unsigned size)
{
1219 1220 1221
	int rc;
	ulong linear;

1222
	rc = linearize(ctxt, addr, size, true, &linear);
1223 1224
	if (rc != X86EMUL_CONTINUE)
		return rc;
1225 1226
	return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
					   size, &ctxt->exception);
1227 1228
}

1229 1230 1231 1232
static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
			   unsigned int size, unsigned short port,
			   void *dest)
{
1233
	struct read_cache *rc = &ctxt->io_read;
1234

1235 1236
	if (rc->pos == rc->end) { /* refill pio read ahead */
		unsigned int in_page, n;
1237 1238
		unsigned int count = ctxt->rep_prefix ?
			address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) : 1;
1239
		in_page = (ctxt->eflags & EFLG_DF) ?
1240 1241
			offset_in_page(ctxt->regs[VCPU_REGS_RDI]) :
			PAGE_SIZE - offset_in_page(ctxt->regs[VCPU_REGS_RDI]);
1242 1243 1244 1245 1246
		n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
			count);
		if (n == 0)
			n = 1;
		rc->pos = rc->end = 0;
1247
		if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
1248 1249
			return 0;
		rc->end = n * size;
A
Avi Kivity 已提交
1250 1251
	}

1252 1253 1254 1255
	memcpy(dest, rc->data + rc->pos, size);
	rc->pos += size;
	return 1;
}
A
Avi Kivity 已提交
1256

1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272
static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
				     u16 index, struct desc_struct *desc)
{
	struct desc_ptr dt;
	ulong addr;

	ctxt->ops->get_idt(ctxt, &dt);

	if (dt.size < index * 8 + 7)
		return emulate_gp(ctxt, index << 3 | 0x2);

	addr = dt.address + index * 8;
	return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
				   &ctxt->exception);
}

1273 1274 1275
static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
				     u16 selector, struct desc_ptr *dt)
{
1276 1277
	struct x86_emulate_ops *ops = ctxt->ops;

1278 1279
	if (selector & 1 << 2) {
		struct desc_struct desc;
1280 1281
		u16 sel;

1282
		memset (dt, 0, sizeof *dt);
1283
		if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
1284
			return;
1285

1286 1287 1288
		dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
		dt->address = get_desc_base(&desc);
	} else
1289
		ops->get_gdt(ctxt, dt);
1290
}
1291

1292 1293 1294 1295 1296 1297 1298
/* allowed just for 8 bytes segments */
static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				   u16 selector, struct desc_struct *desc)
{
	struct desc_ptr dt;
	u16 index = selector >> 3;
	ulong addr;
1299

1300
	get_descriptor_table_ptr(ctxt, selector, &dt);
1301

1302 1303
	if (dt.size < index * 8 + 7)
		return emulate_gp(ctxt, selector & 0xfffc);
1304

1305 1306 1307
	addr = dt.address + index * 8;
	return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
				   &ctxt->exception);
1308
}
1309

1310 1311 1312 1313 1314 1315 1316
/* allowed just for 8 bytes segments */
static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				    u16 selector, struct desc_struct *desc)
{
	struct desc_ptr dt;
	u16 index = selector >> 3;
	ulong addr;
A
Avi Kivity 已提交
1317

1318
	get_descriptor_table_ptr(ctxt, selector, &dt);
1319

1320 1321
	if (dt.size < index * 8 + 7)
		return emulate_gp(ctxt, selector & 0xfffc);
A
Avi Kivity 已提交
1322

1323
	addr = dt.address + index * 8;
1324 1325
	return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
				    &ctxt->exception);
1326
}
1327

1328
/* Does not support long mode */
1329 1330 1331 1332 1333 1334 1335 1336 1337
static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				   u16 selector, int seg)
{
	struct desc_struct seg_desc;
	u8 dpl, rpl, cpl;
	unsigned err_vec = GP_VECTOR;
	u32 err_code = 0;
	bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
	int ret;
1338

1339
	memset(&seg_desc, 0, sizeof seg_desc);
1340

1341 1342 1343 1344 1345 1346 1347 1348
	if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
	    || ctxt->mode == X86EMUL_MODE_REAL) {
		/* set real mode segment descriptor */
		set_desc_base(&seg_desc, selector << 4);
		set_desc_limit(&seg_desc, 0xffff);
		seg_desc.type = 3;
		seg_desc.p = 1;
		seg_desc.s = 1;
1349 1350
		if (ctxt->mode == X86EMUL_MODE_VM86)
			seg_desc.dpl = 3;
1351 1352 1353
		goto load;
	}

1354 1355 1356 1357 1358 1359 1360 1361
	rpl = selector & 3;
	cpl = ctxt->ops->cpl(ctxt);

	/* NULL selector is not valid for TR, CS and SS (except for long mode) */
	if ((seg == VCPU_SREG_CS
	     || (seg == VCPU_SREG_SS
		 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
	     || seg == VCPU_SREG_TR)
1362 1363 1364 1365 1366 1367 1368 1369 1370 1371
	    && null_selector)
		goto exception;

	/* TR should be in GDT only */
	if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
		goto exception;

	if (null_selector) /* for NULL selector skip all following checks */
		goto load;

1372
	ret = read_segment_descriptor(ctxt, selector, &seg_desc);
1373 1374 1375 1376 1377 1378 1379 1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397
	if (ret != X86EMUL_CONTINUE)
		return ret;

	err_code = selector & 0xfffc;
	err_vec = GP_VECTOR;

	/* can't load system descriptor into segment selecor */
	if (seg <= VCPU_SREG_GS && !seg_desc.s)
		goto exception;

	if (!seg_desc.p) {
		err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
		goto exception;
	}

	dpl = seg_desc.dpl;

	switch (seg) {
	case VCPU_SREG_SS:
		/*
		 * segment is not a writable data segment or segment
		 * selector's RPL != CPL or segment selector's RPL != CPL
		 */
		if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
			goto exception;
A
Avi Kivity 已提交
1398
		break;
1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413
	case VCPU_SREG_CS:
		if (!(seg_desc.type & 8))
			goto exception;

		if (seg_desc.type & 4) {
			/* conforming */
			if (dpl > cpl)
				goto exception;
		} else {
			/* nonconforming */
			if (rpl > cpl || dpl != cpl)
				goto exception;
		}
		/* CS(RPL) <- CPL */
		selector = (selector & 0xfffc) | cpl;
A
Avi Kivity 已提交
1414
		break;
1415 1416 1417 1418 1419 1420 1421 1422 1423
	case VCPU_SREG_TR:
		if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
			goto exception;
		break;
	case VCPU_SREG_LDTR:
		if (seg_desc.s || seg_desc.type != 2)
			goto exception;
		break;
	default: /*  DS, ES, FS, or GS */
1424
		/*
1425 1426 1427
		 * segment is not a data or readable code segment or
		 * ((segment is a data or nonconforming code segment)
		 * and (both RPL and CPL > DPL))
1428
		 */
1429 1430 1431 1432
		if ((seg_desc.type & 0xa) == 0x8 ||
		    (((seg_desc.type & 0xc) != 0xc) &&
		     (rpl > dpl && cpl > dpl)))
			goto exception;
A
Avi Kivity 已提交
1433
		break;
1434 1435 1436 1437 1438
	}

	if (seg_desc.s) {
		/* mark segment as accessed */
		seg_desc.type |= 1;
1439
		ret = write_segment_descriptor(ctxt, selector, &seg_desc);
1440 1441 1442 1443
		if (ret != X86EMUL_CONTINUE)
			return ret;
	}
load:
1444
	ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
1445 1446 1447 1448 1449 1450
	return X86EMUL_CONTINUE;
exception:
	emulate_exception(ctxt, err_vec, err_code, true);
	return X86EMUL_PROPAGATE_FAULT;
}

1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464 1465 1466 1467 1468 1469
static void write_register_operand(struct operand *op)
{
	/* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
	switch (op->bytes) {
	case 1:
		*(u8 *)op->addr.reg = (u8)op->val;
		break;
	case 2:
		*(u16 *)op->addr.reg = (u16)op->val;
		break;
	case 4:
		*op->addr.reg = (u32)op->val;
		break;	/* 64b: zero-extend */
	case 8:
		*op->addr.reg = op->val;
		break;
	}
}

1470
static int writeback(struct x86_emulate_ctxt *ctxt)
1471 1472 1473
{
	int rc;

1474
	switch (ctxt->dst.type) {
1475
	case OP_REG:
1476
		write_register_operand(&ctxt->dst);
A
Avi Kivity 已提交
1477
		break;
1478
	case OP_MEM:
1479
		if (ctxt->lock_prefix)
1480
			rc = segmented_cmpxchg(ctxt,
1481 1482 1483 1484
					       ctxt->dst.addr.mem,
					       &ctxt->dst.orig_val,
					       &ctxt->dst.val,
					       ctxt->dst.bytes);
1485
		else
1486
			rc = segmented_write(ctxt,
1487 1488 1489
					     ctxt->dst.addr.mem,
					     &ctxt->dst.val,
					     ctxt->dst.bytes);
1490 1491
		if (rc != X86EMUL_CONTINUE)
			return rc;
1492
		break;
A
Avi Kivity 已提交
1493
	case OP_XMM:
1494
		write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
A
Avi Kivity 已提交
1495
		break;
A
Avi Kivity 已提交
1496 1497 1498
	case OP_MM:
		write_mmx_reg(ctxt, &ctxt->dst.mm_val, ctxt->dst.addr.mm);
		break;
1499 1500
	case OP_NONE:
		/* no writeback */
1501
		break;
1502
	default:
1503
		break;
A
Avi Kivity 已提交
1504
	}
1505 1506
	return X86EMUL_CONTINUE;
}
A
Avi Kivity 已提交
1507

1508
static int em_push(struct x86_emulate_ctxt *ctxt)
1509
{
1510
	struct segmented_address addr;
1511

1512 1513
	register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -ctxt->op_bytes);
	addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
1514 1515 1516
	addr.seg = VCPU_SREG_SS;

	/* Disable writeback. */
1517 1518
	ctxt->dst.type = OP_NONE;
	return segmented_write(ctxt, addr, &ctxt->src.val, ctxt->op_bytes);
1519
}
1520

1521 1522 1523 1524
static int emulate_pop(struct x86_emulate_ctxt *ctxt,
		       void *dest, int len)
{
	int rc;
1525
	struct segmented_address addr;
1526

1527
	addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
1528
	addr.seg = VCPU_SREG_SS;
1529
	rc = segmented_read(ctxt, addr, dest, len);
1530 1531 1532
	if (rc != X86EMUL_CONTINUE)
		return rc;

1533
	register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len);
1534
	return rc;
1535 1536
}

1537 1538
static int em_pop(struct x86_emulate_ctxt *ctxt)
{
1539
	return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1540 1541
}

1542
static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1543
			void *dest, int len)
1544 1545
{
	int rc;
1546 1547
	unsigned long val, change_mask;
	int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1548
	int cpl = ctxt->ops->cpl(ctxt);
1549

1550
	rc = emulate_pop(ctxt, &val, len);
1551 1552
	if (rc != X86EMUL_CONTINUE)
		return rc;
1553

1554 1555
	change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
		| EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1556

1557 1558 1559 1560 1561 1562 1563 1564 1565 1566
	switch(ctxt->mode) {
	case X86EMUL_MODE_PROT64:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT16:
		if (cpl == 0)
			change_mask |= EFLG_IOPL;
		if (cpl <= iopl)
			change_mask |= EFLG_IF;
		break;
	case X86EMUL_MODE_VM86:
1567 1568
		if (iopl < 3)
			return emulate_gp(ctxt, 0);
1569 1570 1571 1572 1573
		change_mask |= EFLG_IF;
		break;
	default: /* real mode */
		change_mask |= (EFLG_IOPL | EFLG_IF);
		break;
1574
	}
1575 1576 1577 1578 1579

	*(unsigned long *)dest =
		(ctxt->eflags & ~change_mask) | (val & change_mask);

	return rc;
1580 1581
}

1582 1583
static int em_popf(struct x86_emulate_ctxt *ctxt)
{
1584 1585 1586 1587
	ctxt->dst.type = OP_REG;
	ctxt->dst.addr.reg = &ctxt->eflags;
	ctxt->dst.bytes = ctxt->op_bytes;
	return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1588 1589
}

A
Avi Kivity 已提交
1590 1591 1592 1593 1594 1595 1596
static int em_leave(struct x86_emulate_ctxt *ctxt)
{
	assign_masked(&ctxt->regs[VCPU_REGS_RSP], ctxt->regs[VCPU_REGS_RBP],
		      stack_mask(ctxt));
	return emulate_pop(ctxt, &ctxt->regs[VCPU_REGS_RBP], ctxt->op_bytes);
}

1597
static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
1598
{
1599 1600
	int seg = ctxt->src2.val;

1601
	ctxt->src.val = get_segment_selector(ctxt, seg);
1602

1603
	return em_push(ctxt);
1604 1605
}

1606
static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
1607
{
1608
	int seg = ctxt->src2.val;
1609 1610
	unsigned long selector;
	int rc;
1611

1612
	rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
1613 1614 1615
	if (rc != X86EMUL_CONTINUE)
		return rc;

1616
	rc = load_segment_descriptor(ctxt, (u16)selector, seg);
1617
	return rc;
1618 1619
}

1620
static int em_pusha(struct x86_emulate_ctxt *ctxt)
1621
{
1622
	unsigned long old_esp = ctxt->regs[VCPU_REGS_RSP];
1623 1624
	int rc = X86EMUL_CONTINUE;
	int reg = VCPU_REGS_RAX;
1625

1626 1627
	while (reg <= VCPU_REGS_RDI) {
		(reg == VCPU_REGS_RSP) ?
1628
		(ctxt->src.val = old_esp) : (ctxt->src.val = ctxt->regs[reg]);
1629

1630
		rc = em_push(ctxt);
1631 1632
		if (rc != X86EMUL_CONTINUE)
			return rc;
1633

1634
		++reg;
1635 1636
	}

1637
	return rc;
1638 1639
}

1640 1641
static int em_pushf(struct x86_emulate_ctxt *ctxt)
{
1642
	ctxt->src.val =  (unsigned long)ctxt->eflags;
1643 1644 1645
	return em_push(ctxt);
}

1646
static int em_popa(struct x86_emulate_ctxt *ctxt)
1647
{
1648 1649
	int rc = X86EMUL_CONTINUE;
	int reg = VCPU_REGS_RDI;
1650

1651 1652
	while (reg >= VCPU_REGS_RAX) {
		if (reg == VCPU_REGS_RSP) {
1653 1654
			register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP],
							ctxt->op_bytes);
1655 1656
			--reg;
		}
1657

1658
		rc = emulate_pop(ctxt, &ctxt->regs[reg], ctxt->op_bytes);
1659 1660 1661
		if (rc != X86EMUL_CONTINUE)
			break;
		--reg;
1662
	}
1663
	return rc;
1664 1665
}

1666
int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1667
{
1668
	struct x86_emulate_ops *ops = ctxt->ops;
1669
	int rc;
1670 1671 1672 1673 1674 1675
	struct desc_ptr dt;
	gva_t cs_addr;
	gva_t eip_addr;
	u16 cs, eip;

	/* TODO: Add limit checks */
1676
	ctxt->src.val = ctxt->eflags;
1677
	rc = em_push(ctxt);
1678 1679
	if (rc != X86EMUL_CONTINUE)
		return rc;
1680 1681 1682

	ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);

1683
	ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
1684
	rc = em_push(ctxt);
1685 1686
	if (rc != X86EMUL_CONTINUE)
		return rc;
1687

1688
	ctxt->src.val = ctxt->_eip;
1689
	rc = em_push(ctxt);
1690 1691 1692
	if (rc != X86EMUL_CONTINUE)
		return rc;

1693
	ops->get_idt(ctxt, &dt);
1694 1695 1696 1697

	eip_addr = dt.address + (irq << 2);
	cs_addr = dt.address + (irq << 2) + 2;

1698
	rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
1699 1700 1701
	if (rc != X86EMUL_CONTINUE)
		return rc;

1702
	rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
1703 1704 1705
	if (rc != X86EMUL_CONTINUE)
		return rc;

1706
	rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
1707 1708 1709
	if (rc != X86EMUL_CONTINUE)
		return rc;

1710
	ctxt->_eip = eip;
1711 1712 1713 1714

	return rc;
}

1715
static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
1716 1717 1718
{
	switch(ctxt->mode) {
	case X86EMUL_MODE_REAL:
1719
		return emulate_int_real(ctxt, irq);
1720 1721 1722 1723 1724 1725 1726 1727 1728 1729
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT64:
	default:
		/* Protected mode interrupts unimplemented yet */
		return X86EMUL_UNHANDLEABLE;
	}
}

1730
static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
1731
{
1732 1733 1734 1735 1736 1737 1738 1739
	int rc = X86EMUL_CONTINUE;
	unsigned long temp_eip = 0;
	unsigned long temp_eflags = 0;
	unsigned long cs = 0;
	unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
			     EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
			     EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
	unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1740

1741
	/* TODO: Add stack limit check */
1742

1743
	rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
1744

1745 1746
	if (rc != X86EMUL_CONTINUE)
		return rc;
1747

1748 1749
	if (temp_eip & ~0xffff)
		return emulate_gp(ctxt, 0);
1750

1751
	rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1752

1753 1754
	if (rc != X86EMUL_CONTINUE)
		return rc;
1755

1756
	rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
1757

1758 1759
	if (rc != X86EMUL_CONTINUE)
		return rc;
1760

1761
	rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
1762

1763 1764
	if (rc != X86EMUL_CONTINUE)
		return rc;
1765

1766
	ctxt->_eip = temp_eip;
1767 1768


1769
	if (ctxt->op_bytes == 4)
1770
		ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1771
	else if (ctxt->op_bytes == 2) {
1772 1773
		ctxt->eflags &= ~0xffff;
		ctxt->eflags |= temp_eflags;
1774
	}
1775 1776 1777 1778 1779

	ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
	ctxt->eflags |= EFLG_RESERVED_ONE_MASK;

	return rc;
1780 1781
}

1782
static int em_iret(struct x86_emulate_ctxt *ctxt)
1783
{
1784 1785
	switch(ctxt->mode) {
	case X86EMUL_MODE_REAL:
1786
		return emulate_iret_real(ctxt);
1787 1788 1789 1790
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT64:
1791
	default:
1792 1793
		/* iret from protected mode unimplemented yet */
		return X86EMUL_UNHANDLEABLE;
1794 1795 1796
	}
}

1797 1798 1799 1800 1801
static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
{
	int rc;
	unsigned short sel;

1802
	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
1803

1804
	rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
1805 1806 1807
	if (rc != X86EMUL_CONTINUE)
		return rc;

1808 1809
	ctxt->_eip = 0;
	memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
1810 1811 1812
	return X86EMUL_CONTINUE;
}

1813
static int em_grp2(struct x86_emulate_ctxt *ctxt)
1814
{
1815
	switch (ctxt->modrm_reg) {
1816
	case 0:	/* rol */
1817
		emulate_2op_SrcB(ctxt, "rol");
1818 1819
		break;
	case 1:	/* ror */
1820
		emulate_2op_SrcB(ctxt, "ror");
1821 1822
		break;
	case 2:	/* rcl */
1823
		emulate_2op_SrcB(ctxt, "rcl");
1824 1825
		break;
	case 3:	/* rcr */
1826
		emulate_2op_SrcB(ctxt, "rcr");
1827 1828 1829
		break;
	case 4:	/* sal/shl */
	case 6:	/* sal/shl */
1830
		emulate_2op_SrcB(ctxt, "sal");
1831 1832
		break;
	case 5:	/* shr */
1833
		emulate_2op_SrcB(ctxt, "shr");
1834 1835
		break;
	case 7:	/* sar */
1836
		emulate_2op_SrcB(ctxt, "sar");
1837 1838
		break;
	}
1839
	return X86EMUL_CONTINUE;
1840 1841
}

1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870
static int em_not(struct x86_emulate_ctxt *ctxt)
{
	ctxt->dst.val = ~ctxt->dst.val;
	return X86EMUL_CONTINUE;
}

static int em_neg(struct x86_emulate_ctxt *ctxt)
{
	emulate_1op(ctxt, "neg");
	return X86EMUL_CONTINUE;
}

static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
{
	u8 ex = 0;

	emulate_1op_rax_rdx(ctxt, "mul", ex);
	return X86EMUL_CONTINUE;
}

static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
{
	u8 ex = 0;

	emulate_1op_rax_rdx(ctxt, "imul", ex);
	return X86EMUL_CONTINUE;
}

static int em_div_ex(struct x86_emulate_ctxt *ctxt)
1871
{
1872
	u8 de = 0;
1873

1874 1875 1876 1877 1878 1879 1880 1881 1882 1883 1884
	emulate_1op_rax_rdx(ctxt, "div", de);
	if (de)
		return emulate_de(ctxt);
	return X86EMUL_CONTINUE;
}

static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
{
	u8 de = 0;

	emulate_1op_rax_rdx(ctxt, "idiv", de);
1885 1886
	if (de)
		return emulate_de(ctxt);
1887
	return X86EMUL_CONTINUE;
1888 1889
}

1890
static int em_grp45(struct x86_emulate_ctxt *ctxt)
1891
{
1892
	int rc = X86EMUL_CONTINUE;
1893

1894
	switch (ctxt->modrm_reg) {
1895
	case 0:	/* inc */
1896
		emulate_1op(ctxt, "inc");
1897 1898
		break;
	case 1:	/* dec */
1899
		emulate_1op(ctxt, "dec");
1900
		break;
1901 1902
	case 2: /* call near abs */ {
		long int old_eip;
1903 1904 1905
		old_eip = ctxt->_eip;
		ctxt->_eip = ctxt->src.val;
		ctxt->src.val = old_eip;
1906
		rc = em_push(ctxt);
1907 1908
		break;
	}
1909
	case 4: /* jmp abs */
1910
		ctxt->_eip = ctxt->src.val;
1911
		break;
1912 1913 1914
	case 5: /* jmp far */
		rc = em_jmp_far(ctxt);
		break;
1915
	case 6:	/* push */
1916
		rc = em_push(ctxt);
1917 1918
		break;
	}
1919
	return rc;
1920 1921
}

1922
static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
1923
{
1924
	u64 old = ctxt->dst.orig_val64;
1925

1926 1927 1928 1929
	if (((u32) (old >> 0) != (u32) ctxt->regs[VCPU_REGS_RAX]) ||
	    ((u32) (old >> 32) != (u32) ctxt->regs[VCPU_REGS_RDX])) {
		ctxt->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
		ctxt->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1930
		ctxt->eflags &= ~EFLG_ZF;
1931
	} else {
1932 1933
		ctxt->dst.val64 = ((u64)ctxt->regs[VCPU_REGS_RCX] << 32) |
			(u32) ctxt->regs[VCPU_REGS_RBX];
1934

1935
		ctxt->eflags |= EFLG_ZF;
1936
	}
1937
	return X86EMUL_CONTINUE;
1938 1939
}

1940 1941
static int em_ret(struct x86_emulate_ctxt *ctxt)
{
1942 1943 1944
	ctxt->dst.type = OP_REG;
	ctxt->dst.addr.reg = &ctxt->_eip;
	ctxt->dst.bytes = ctxt->op_bytes;
1945 1946 1947
	return em_pop(ctxt);
}

1948
static int em_ret_far(struct x86_emulate_ctxt *ctxt)
1949 1950 1951 1952
{
	int rc;
	unsigned long cs;

1953
	rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1954
	if (rc != X86EMUL_CONTINUE)
1955
		return rc;
1956 1957 1958
	if (ctxt->op_bytes == 4)
		ctxt->_eip = (u32)ctxt->_eip;
	rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1959
	if (rc != X86EMUL_CONTINUE)
1960
		return rc;
1961
	rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
1962 1963 1964
	return rc;
}

1965 1966 1967 1968 1969 1970 1971 1972 1973 1974 1975 1976 1977 1978 1979 1980 1981 1982
static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
{
	/* Save real source value, then compare EAX against destination. */
	ctxt->src.orig_val = ctxt->src.val;
	ctxt->src.val = ctxt->regs[VCPU_REGS_RAX];
	emulate_2op_SrcV(ctxt, "cmp");

	if (ctxt->eflags & EFLG_ZF) {
		/* Success: write back to memory. */
		ctxt->dst.val = ctxt->src.orig_val;
	} else {
		/* Failure: write the value we saw to EAX. */
		ctxt->dst.type = OP_REG;
		ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX];
	}
	return X86EMUL_CONTINUE;
}

1983
static int em_lseg(struct x86_emulate_ctxt *ctxt)
1984
{
1985
	int seg = ctxt->src2.val;
1986 1987 1988
	unsigned short sel;
	int rc;

1989
	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
1990

1991
	rc = load_segment_descriptor(ctxt, sel, seg);
1992 1993 1994
	if (rc != X86EMUL_CONTINUE)
		return rc;

1995
	ctxt->dst.val = ctxt->src.val;
1996 1997 1998
	return rc;
}

1999
static void
2000
setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
2001
			struct desc_struct *cs, struct desc_struct *ss)
2002
{
2003 2004
	u16 selector;

2005
	memset(cs, 0, sizeof(struct desc_struct));
2006
	ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
2007
	memset(ss, 0, sizeof(struct desc_struct));
2008 2009

	cs->l = 0;		/* will be adjusted later */
2010
	set_desc_base(cs, 0);	/* flat segment */
2011
	cs->g = 1;		/* 4kb granularity */
2012
	set_desc_limit(cs, 0xfffff);	/* 4GB limit */
2013 2014 2015
	cs->type = 0x0b;	/* Read, Execute, Accessed */
	cs->s = 1;
	cs->dpl = 0;		/* will be adjusted later */
2016 2017
	cs->p = 1;
	cs->d = 1;
2018

2019 2020
	set_desc_base(ss, 0);	/* flat segment */
	set_desc_limit(ss, 0xfffff);	/* 4GB limit */
2021 2022 2023
	ss->g = 1;		/* 4kb granularity */
	ss->s = 1;
	ss->type = 0x03;	/* Read/Write, Accessed */
2024
	ss->d = 1;		/* 32bit stack segment */
2025
	ss->dpl = 0;
2026
	ss->p = 1;
2027 2028
}

2029 2030 2031 2032 2033
static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
{
	u32 eax, ebx, ecx, edx;

	eax = ecx = 0;
2034 2035
	ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
	return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
2036 2037 2038 2039
		&& ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
		&& edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
}

2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053
static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
{
	struct x86_emulate_ops *ops = ctxt->ops;
	u32 eax, ebx, ecx, edx;

	/*
	 * syscall should always be enabled in longmode - so only become
	 * vendor specific (cpuid) if other modes are active...
	 */
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		return true;

	eax = 0x00000000;
	ecx = 0x00000000;
2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078
	ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
	/*
	 * Intel ("GenuineIntel")
	 * remark: Intel CPUs only support "syscall" in 64bit
	 * longmode. Also an 64bit guest with a
	 * 32bit compat-app running will #UD !! While this
	 * behaviour can be fixed (by emulating) into AMD
	 * response - CPUs of AMD can't behave like Intel.
	 */
	if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
	    ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
	    edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
		return false;

	/* AMD ("AuthenticAMD") */
	if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
	    ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
	    edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
		return true;

	/* AMD ("AMDisbetter!") */
	if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
	    ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
	    edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
		return true;
2079 2080 2081 2082 2083

	/* default: (not Intel, not AMD), apply Intel's stricter rules... */
	return false;
}

2084
static int em_syscall(struct x86_emulate_ctxt *ctxt)
2085
{
2086
	struct x86_emulate_ops *ops = ctxt->ops;
2087
	struct desc_struct cs, ss;
2088
	u64 msr_data;
2089
	u16 cs_sel, ss_sel;
2090
	u64 efer = 0;
2091 2092

	/* syscall is not available in real mode */
2093
	if (ctxt->mode == X86EMUL_MODE_REAL ||
2094 2095
	    ctxt->mode == X86EMUL_MODE_VM86)
		return emulate_ud(ctxt);
2096

2097 2098 2099
	if (!(em_syscall_is_enabled(ctxt)))
		return emulate_ud(ctxt);

2100
	ops->get_msr(ctxt, MSR_EFER, &efer);
2101
	setup_syscalls_segments(ctxt, &cs, &ss);
2102

2103 2104 2105
	if (!(efer & EFER_SCE))
		return emulate_ud(ctxt);

2106
	ops->get_msr(ctxt, MSR_STAR, &msr_data);
2107
	msr_data >>= 32;
2108 2109
	cs_sel = (u16)(msr_data & 0xfffc);
	ss_sel = (u16)(msr_data + 8);
2110

2111
	if (efer & EFER_LMA) {
2112
		cs.d = 0;
2113 2114
		cs.l = 1;
	}
2115 2116
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2117

2118
	ctxt->regs[VCPU_REGS_RCX] = ctxt->_eip;
2119
	if (efer & EFER_LMA) {
2120
#ifdef CONFIG_X86_64
2121
		ctxt->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
2122

2123
		ops->get_msr(ctxt,
2124 2125
			     ctxt->mode == X86EMUL_MODE_PROT64 ?
			     MSR_LSTAR : MSR_CSTAR, &msr_data);
2126
		ctxt->_eip = msr_data;
2127

2128
		ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
2129 2130 2131 2132
		ctxt->eflags &= ~(msr_data | EFLG_RF);
#endif
	} else {
		/* legacy mode */
2133
		ops->get_msr(ctxt, MSR_STAR, &msr_data);
2134
		ctxt->_eip = (u32)msr_data;
2135 2136 2137 2138

		ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
	}

2139
	return X86EMUL_CONTINUE;
2140 2141
}

2142
static int em_sysenter(struct x86_emulate_ctxt *ctxt)
2143
{
2144
	struct x86_emulate_ops *ops = ctxt->ops;
2145
	struct desc_struct cs, ss;
2146
	u64 msr_data;
2147
	u16 cs_sel, ss_sel;
2148
	u64 efer = 0;
2149

2150
	ops->get_msr(ctxt, MSR_EFER, &efer);
2151
	/* inject #GP if in real mode */
2152 2153
	if (ctxt->mode == X86EMUL_MODE_REAL)
		return emulate_gp(ctxt, 0);
2154

2155 2156 2157 2158 2159 2160 2161 2162
	/*
	 * Not recognized on AMD in compat mode (but is recognized in legacy
	 * mode).
	 */
	if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
	    && !vendor_intel(ctxt))
		return emulate_ud(ctxt);

2163 2164 2165
	/* XXX sysenter/sysexit have not been tested in 64bit mode.
	* Therefore, we inject an #UD.
	*/
2166 2167
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		return emulate_ud(ctxt);
2168

2169
	setup_syscalls_segments(ctxt, &cs, &ss);
2170

2171
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2172 2173
	switch (ctxt->mode) {
	case X86EMUL_MODE_PROT32:
2174 2175
		if ((msr_data & 0xfffc) == 0x0)
			return emulate_gp(ctxt, 0);
2176 2177
		break;
	case X86EMUL_MODE_PROT64:
2178 2179
		if (msr_data == 0x0)
			return emulate_gp(ctxt, 0);
2180 2181 2182 2183
		break;
	}

	ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2184 2185 2186 2187
	cs_sel = (u16)msr_data;
	cs_sel &= ~SELECTOR_RPL_MASK;
	ss_sel = cs_sel + 8;
	ss_sel &= ~SELECTOR_RPL_MASK;
2188
	if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
2189
		cs.d = 0;
2190 2191 2192
		cs.l = 1;
	}

2193 2194
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2195

2196
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
2197
	ctxt->_eip = msr_data;
2198

2199
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
2200
	ctxt->regs[VCPU_REGS_RSP] = msr_data;
2201

2202
	return X86EMUL_CONTINUE;
2203 2204
}

2205
static int em_sysexit(struct x86_emulate_ctxt *ctxt)
2206
{
2207
	struct x86_emulate_ops *ops = ctxt->ops;
2208
	struct desc_struct cs, ss;
2209 2210
	u64 msr_data;
	int usermode;
X
Xiao Guangrong 已提交
2211
	u16 cs_sel = 0, ss_sel = 0;
2212

2213 2214
	/* inject #GP if in real mode or Virtual 8086 mode */
	if (ctxt->mode == X86EMUL_MODE_REAL ||
2215 2216
	    ctxt->mode == X86EMUL_MODE_VM86)
		return emulate_gp(ctxt, 0);
2217

2218
	setup_syscalls_segments(ctxt, &cs, &ss);
2219

2220
	if ((ctxt->rex_prefix & 0x8) != 0x0)
2221 2222 2223 2224 2225 2226
		usermode = X86EMUL_MODE_PROT64;
	else
		usermode = X86EMUL_MODE_PROT32;

	cs.dpl = 3;
	ss.dpl = 3;
2227
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2228 2229
	switch (usermode) {
	case X86EMUL_MODE_PROT32:
2230
		cs_sel = (u16)(msr_data + 16);
2231 2232
		if ((msr_data & 0xfffc) == 0x0)
			return emulate_gp(ctxt, 0);
2233
		ss_sel = (u16)(msr_data + 24);
2234 2235
		break;
	case X86EMUL_MODE_PROT64:
2236
		cs_sel = (u16)(msr_data + 32);
2237 2238
		if (msr_data == 0x0)
			return emulate_gp(ctxt, 0);
2239 2240
		ss_sel = cs_sel + 8;
		cs.d = 0;
2241 2242 2243
		cs.l = 1;
		break;
	}
2244 2245
	cs_sel |= SELECTOR_RPL_MASK;
	ss_sel |= SELECTOR_RPL_MASK;
2246

2247 2248
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2249

2250 2251
	ctxt->_eip = ctxt->regs[VCPU_REGS_RDX];
	ctxt->regs[VCPU_REGS_RSP] = ctxt->regs[VCPU_REGS_RCX];
2252

2253
	return X86EMUL_CONTINUE;
2254 2255
}

2256
static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
2257 2258 2259 2260 2261 2262 2263
{
	int iopl;
	if (ctxt->mode == X86EMUL_MODE_REAL)
		return false;
	if (ctxt->mode == X86EMUL_MODE_VM86)
		return true;
	iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
2264
	return ctxt->ops->cpl(ctxt) > iopl;
2265 2266 2267 2268 2269
}

static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
					    u16 port, u16 len)
{
2270
	struct x86_emulate_ops *ops = ctxt->ops;
2271
	struct desc_struct tr_seg;
2272
	u32 base3;
2273
	int r;
2274
	u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
2275
	unsigned mask = (1 << len) - 1;
2276
	unsigned long base;
2277

2278
	ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
2279
	if (!tr_seg.p)
2280
		return false;
2281
	if (desc_limit_scaled(&tr_seg) < 103)
2282
		return false;
2283 2284 2285 2286
	base = get_desc_base(&tr_seg);
#ifdef CONFIG_X86_64
	base |= ((u64)base3) << 32;
#endif
2287
	r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
2288 2289
	if (r != X86EMUL_CONTINUE)
		return false;
2290
	if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
2291
		return false;
2292
	r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
2293 2294 2295 2296 2297 2298 2299 2300 2301 2302
	if (r != X86EMUL_CONTINUE)
		return false;
	if ((perm >> bit_idx) & mask)
		return false;
	return true;
}

static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
				 u16 port, u16 len)
{
2303 2304 2305
	if (ctxt->perm_ok)
		return true;

2306 2307
	if (emulator_bad_iopl(ctxt))
		if (!emulator_io_port_access_allowed(ctxt, port, len))
2308
			return false;
2309 2310 2311

	ctxt->perm_ok = true;

2312 2313 2314
	return true;
}

2315 2316 2317
static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
				struct tss_segment_16 *tss)
{
2318
	tss->ip = ctxt->_eip;
2319
	tss->flag = ctxt->eflags;
2320 2321 2322 2323 2324 2325 2326 2327
	tss->ax = ctxt->regs[VCPU_REGS_RAX];
	tss->cx = ctxt->regs[VCPU_REGS_RCX];
	tss->dx = ctxt->regs[VCPU_REGS_RDX];
	tss->bx = ctxt->regs[VCPU_REGS_RBX];
	tss->sp = ctxt->regs[VCPU_REGS_RSP];
	tss->bp = ctxt->regs[VCPU_REGS_RBP];
	tss->si = ctxt->regs[VCPU_REGS_RSI];
	tss->di = ctxt->regs[VCPU_REGS_RDI];
2328

2329 2330 2331 2332 2333
	tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
	tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
	tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
	tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
	tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2334 2335 2336 2337 2338 2339 2340
}

static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
				 struct tss_segment_16 *tss)
{
	int ret;

2341
	ctxt->_eip = tss->ip;
2342
	ctxt->eflags = tss->flag | 2;
2343 2344 2345 2346 2347 2348 2349 2350
	ctxt->regs[VCPU_REGS_RAX] = tss->ax;
	ctxt->regs[VCPU_REGS_RCX] = tss->cx;
	ctxt->regs[VCPU_REGS_RDX] = tss->dx;
	ctxt->regs[VCPU_REGS_RBX] = tss->bx;
	ctxt->regs[VCPU_REGS_RSP] = tss->sp;
	ctxt->regs[VCPU_REGS_RBP] = tss->bp;
	ctxt->regs[VCPU_REGS_RSI] = tss->si;
	ctxt->regs[VCPU_REGS_RDI] = tss->di;
2351 2352 2353 2354 2355

	/*
	 * SDM says that segment selectors are loaded before segment
	 * descriptors
	 */
2356 2357 2358 2359 2360
	set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
	set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
	set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
	set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
	set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2361 2362 2363 2364 2365

	/*
	 * Now load segment descriptors. If fault happenes at this stage
	 * it is handled in a context of new task
	 */
2366
	ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
2367 2368
	if (ret != X86EMUL_CONTINUE)
		return ret;
2369
	ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
2370 2371
	if (ret != X86EMUL_CONTINUE)
		return ret;
2372
	ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
2373 2374
	if (ret != X86EMUL_CONTINUE)
		return ret;
2375
	ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
2376 2377
	if (ret != X86EMUL_CONTINUE)
		return ret;
2378
	ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
2379 2380 2381 2382 2383 2384 2385 2386 2387 2388
	if (ret != X86EMUL_CONTINUE)
		return ret;

	return X86EMUL_CONTINUE;
}

static int task_switch_16(struct x86_emulate_ctxt *ctxt,
			  u16 tss_selector, u16 old_tss_sel,
			  ulong old_tss_base, struct desc_struct *new_desc)
{
2389
	struct x86_emulate_ops *ops = ctxt->ops;
2390 2391
	struct tss_segment_16 tss_seg;
	int ret;
2392
	u32 new_tss_base = get_desc_base(new_desc);
2393

2394
	ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2395
			    &ctxt->exception);
2396
	if (ret != X86EMUL_CONTINUE)
2397 2398 2399
		/* FIXME: need to provide precise fault address */
		return ret;

2400
	save_state_to_tss16(ctxt, &tss_seg);
2401

2402
	ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2403
			     &ctxt->exception);
2404
	if (ret != X86EMUL_CONTINUE)
2405 2406 2407
		/* FIXME: need to provide precise fault address */
		return ret;

2408
	ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2409
			    &ctxt->exception);
2410
	if (ret != X86EMUL_CONTINUE)
2411 2412 2413 2414 2415 2416
		/* FIXME: need to provide precise fault address */
		return ret;

	if (old_tss_sel != 0xffff) {
		tss_seg.prev_task_link = old_tss_sel;

2417
		ret = ops->write_std(ctxt, new_tss_base,
2418 2419
				     &tss_seg.prev_task_link,
				     sizeof tss_seg.prev_task_link,
2420
				     &ctxt->exception);
2421
		if (ret != X86EMUL_CONTINUE)
2422 2423 2424 2425
			/* FIXME: need to provide precise fault address */
			return ret;
	}

2426
	return load_state_from_tss16(ctxt, &tss_seg);
2427 2428 2429 2430 2431
}

static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
				struct tss_segment_32 *tss)
{
2432
	tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
2433
	tss->eip = ctxt->_eip;
2434
	tss->eflags = ctxt->eflags;
2435 2436 2437 2438 2439 2440 2441 2442
	tss->eax = ctxt->regs[VCPU_REGS_RAX];
	tss->ecx = ctxt->regs[VCPU_REGS_RCX];
	tss->edx = ctxt->regs[VCPU_REGS_RDX];
	tss->ebx = ctxt->regs[VCPU_REGS_RBX];
	tss->esp = ctxt->regs[VCPU_REGS_RSP];
	tss->ebp = ctxt->regs[VCPU_REGS_RBP];
	tss->esi = ctxt->regs[VCPU_REGS_RSI];
	tss->edi = ctxt->regs[VCPU_REGS_RDI];
2443

2444 2445 2446 2447 2448 2449 2450
	tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
	tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
	tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
	tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
	tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
	tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
	tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2451 2452 2453 2454 2455 2456 2457
}

static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
				 struct tss_segment_32 *tss)
{
	int ret;

2458
	if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
2459
		return emulate_gp(ctxt, 0);
2460
	ctxt->_eip = tss->eip;
2461
	ctxt->eflags = tss->eflags | 2;
2462 2463

	/* General purpose registers */
2464 2465 2466 2467 2468 2469 2470 2471
	ctxt->regs[VCPU_REGS_RAX] = tss->eax;
	ctxt->regs[VCPU_REGS_RCX] = tss->ecx;
	ctxt->regs[VCPU_REGS_RDX] = tss->edx;
	ctxt->regs[VCPU_REGS_RBX] = tss->ebx;
	ctxt->regs[VCPU_REGS_RSP] = tss->esp;
	ctxt->regs[VCPU_REGS_RBP] = tss->ebp;
	ctxt->regs[VCPU_REGS_RSI] = tss->esi;
	ctxt->regs[VCPU_REGS_RDI] = tss->edi;
2472 2473 2474 2475 2476

	/*
	 * SDM says that segment selectors are loaded before segment
	 * descriptors
	 */
2477 2478 2479 2480 2481 2482 2483
	set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
	set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
	set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
	set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
	set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
	set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
	set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
2484

2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502
	/*
	 * If we're switching between Protected Mode and VM86, we need to make
	 * sure to update the mode before loading the segment descriptors so
	 * that the selectors are interpreted correctly.
	 *
	 * Need to get rflags to the vcpu struct immediately because it
	 * influences the CPL which is checked at least when loading the segment
	 * descriptors and when pushing an error code to the new kernel stack.
	 *
	 * TODO Introduce a separate ctxt->ops->set_cpl callback
	 */
	if (ctxt->eflags & X86_EFLAGS_VM)
		ctxt->mode = X86EMUL_MODE_VM86;
	else
		ctxt->mode = X86EMUL_MODE_PROT32;

	ctxt->ops->set_rflags(ctxt, ctxt->eflags);

2503 2504 2505 2506
	/*
	 * Now load segment descriptors. If fault happenes at this stage
	 * it is handled in a context of new task
	 */
2507
	ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2508 2509
	if (ret != X86EMUL_CONTINUE)
		return ret;
2510
	ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
2511 2512
	if (ret != X86EMUL_CONTINUE)
		return ret;
2513
	ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
2514 2515
	if (ret != X86EMUL_CONTINUE)
		return ret;
2516
	ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
2517 2518
	if (ret != X86EMUL_CONTINUE)
		return ret;
2519
	ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
2520 2521
	if (ret != X86EMUL_CONTINUE)
		return ret;
2522
	ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
2523 2524
	if (ret != X86EMUL_CONTINUE)
		return ret;
2525
	ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
2526 2527 2528 2529 2530 2531 2532 2533 2534 2535
	if (ret != X86EMUL_CONTINUE)
		return ret;

	return X86EMUL_CONTINUE;
}

static int task_switch_32(struct x86_emulate_ctxt *ctxt,
			  u16 tss_selector, u16 old_tss_sel,
			  ulong old_tss_base, struct desc_struct *new_desc)
{
2536
	struct x86_emulate_ops *ops = ctxt->ops;
2537 2538
	struct tss_segment_32 tss_seg;
	int ret;
2539
	u32 new_tss_base = get_desc_base(new_desc);
2540

2541
	ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2542
			    &ctxt->exception);
2543
	if (ret != X86EMUL_CONTINUE)
2544 2545 2546
		/* FIXME: need to provide precise fault address */
		return ret;

2547
	save_state_to_tss32(ctxt, &tss_seg);
2548

2549
	ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2550
			     &ctxt->exception);
2551
	if (ret != X86EMUL_CONTINUE)
2552 2553 2554
		/* FIXME: need to provide precise fault address */
		return ret;

2555
	ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2556
			    &ctxt->exception);
2557
	if (ret != X86EMUL_CONTINUE)
2558 2559 2560 2561 2562 2563
		/* FIXME: need to provide precise fault address */
		return ret;

	if (old_tss_sel != 0xffff) {
		tss_seg.prev_task_link = old_tss_sel;

2564
		ret = ops->write_std(ctxt, new_tss_base,
2565 2566
				     &tss_seg.prev_task_link,
				     sizeof tss_seg.prev_task_link,
2567
				     &ctxt->exception);
2568
		if (ret != X86EMUL_CONTINUE)
2569 2570 2571 2572
			/* FIXME: need to provide precise fault address */
			return ret;
	}

2573
	return load_state_from_tss32(ctxt, &tss_seg);
2574 2575 2576
}

static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2577
				   u16 tss_selector, int idt_index, int reason,
2578
				   bool has_error_code, u32 error_code)
2579
{
2580
	struct x86_emulate_ops *ops = ctxt->ops;
2581 2582
	struct desc_struct curr_tss_desc, next_tss_desc;
	int ret;
2583
	u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
2584
	ulong old_tss_base =
2585
		ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
2586
	u32 desc_limit;
2587 2588 2589

	/* FIXME: old_tss_base == ~0 ? */

2590
	ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
2591 2592
	if (ret != X86EMUL_CONTINUE)
		return ret;
2593
	ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
2594 2595 2596 2597 2598
	if (ret != X86EMUL_CONTINUE)
		return ret;

	/* FIXME: check that next_tss_desc is tss */

2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624
	/*
	 * Check privileges. The three cases are task switch caused by...
	 *
	 * 1. jmp/call/int to task gate: Check against DPL of the task gate
	 * 2. Exception/IRQ/iret: No check is performed
	 * 3. jmp/call to TSS: Check agains DPL of the TSS
	 */
	if (reason == TASK_SWITCH_GATE) {
		if (idt_index != -1) {
			/* Software interrupts */
			struct desc_struct task_gate_desc;
			int dpl;

			ret = read_interrupt_descriptor(ctxt, idt_index,
							&task_gate_desc);
			if (ret != X86EMUL_CONTINUE)
				return ret;

			dpl = task_gate_desc.dpl;
			if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
				return emulate_gp(ctxt, (idt_index << 3) | 0x2);
		}
	} else if (reason != TASK_SWITCH_IRET) {
		int dpl = next_tss_desc.dpl;
		if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
			return emulate_gp(ctxt, tss_selector);
2625 2626
	}

2627

2628 2629 2630 2631
	desc_limit = desc_limit_scaled(&next_tss_desc);
	if (!next_tss_desc.p ||
	    ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
	     desc_limit < 0x2b)) {
2632
		emulate_ts(ctxt, tss_selector & 0xfffc);
2633 2634 2635 2636 2637
		return X86EMUL_PROPAGATE_FAULT;
	}

	if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
		curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2638
		write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649
	}

	if (reason == TASK_SWITCH_IRET)
		ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;

	/* set back link to prev task only if NT bit is set in eflags
	   note that old_tss_sel is not used afetr this point */
	if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
		old_tss_sel = 0xffff;

	if (next_tss_desc.type & 8)
2650
		ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
2651 2652
				     old_tss_base, &next_tss_desc);
	else
2653
		ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
2654
				     old_tss_base, &next_tss_desc);
2655 2656
	if (ret != X86EMUL_CONTINUE)
		return ret;
2657 2658 2659 2660 2661 2662

	if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
		ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;

	if (reason != TASK_SWITCH_IRET) {
		next_tss_desc.type |= (1 << 1); /* set busy flag */
2663
		write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
2664 2665
	}

2666
	ops->set_cr(ctxt, 0,  ops->get_cr(ctxt, 0) | X86_CR0_TS);
2667
	ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
2668

2669
	if (has_error_code) {
2670 2671 2672
		ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
		ctxt->lock_prefix = 0;
		ctxt->src.val = (unsigned long) error_code;
2673
		ret = em_push(ctxt);
2674 2675
	}

2676 2677 2678 2679
	return ret;
}

int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2680
			 u16 tss_selector, int idt_index, int reason,
2681
			 bool has_error_code, u32 error_code)
2682 2683 2684
{
	int rc;

2685 2686
	ctxt->_eip = ctxt->eip;
	ctxt->dst.type = OP_NONE;
2687

2688
	rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
2689
				     has_error_code, error_code);
2690

2691
	if (rc == X86EMUL_CONTINUE)
2692
		ctxt->eip = ctxt->_eip;
2693

2694
	return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
2695 2696
}

2697
static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
2698
			    int reg, struct operand *op)
2699 2700 2701
{
	int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;

2702 2703
	register_address_increment(ctxt, &ctxt->regs[reg], df * op->bytes);
	op->addr.mem.ea = register_address(ctxt, ctxt->regs[reg]);
2704
	op->addr.mem.seg = seg;
2705 2706
}

2707 2708 2709 2710 2711 2712
static int em_das(struct x86_emulate_ctxt *ctxt)
{
	u8 al, old_al;
	bool af, cf, old_cf;

	cf = ctxt->eflags & X86_EFLAGS_CF;
2713
	al = ctxt->dst.val;
2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730

	old_al = al;
	old_cf = cf;
	cf = false;
	af = ctxt->eflags & X86_EFLAGS_AF;
	if ((al & 0x0f) > 9 || af) {
		al -= 6;
		cf = old_cf | (al >= 250);
		af = true;
	} else {
		af = false;
	}
	if (old_al > 0x99 || old_cf) {
		al -= 0x60;
		cf = true;
	}

2731
	ctxt->dst.val = al;
2732
	/* Set PF, ZF, SF */
2733 2734 2735
	ctxt->src.type = OP_IMM;
	ctxt->src.val = 0;
	ctxt->src.bytes = 1;
2736
	emulate_2op_SrcV(ctxt, "or");
2737 2738 2739 2740 2741 2742 2743 2744
	ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
	if (cf)
		ctxt->eflags |= X86_EFLAGS_CF;
	if (af)
		ctxt->eflags |= X86_EFLAGS_AF;
	return X86EMUL_CONTINUE;
}

2745 2746 2747 2748 2749 2750 2751 2752 2753
static int em_call(struct x86_emulate_ctxt *ctxt)
{
	long rel = ctxt->src.val;

	ctxt->src.val = (unsigned long)ctxt->_eip;
	jmp_rel(ctxt, rel);
	return em_push(ctxt);
}

2754 2755 2756 2757 2758 2759
static int em_call_far(struct x86_emulate_ctxt *ctxt)
{
	u16 sel, old_cs;
	ulong old_eip;
	int rc;

2760
	old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2761
	old_eip = ctxt->_eip;
2762

2763
	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2764
	if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
2765 2766
		return X86EMUL_CONTINUE;

2767 2768
	ctxt->_eip = 0;
	memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
2769

2770
	ctxt->src.val = old_cs;
2771
	rc = em_push(ctxt);
2772 2773 2774
	if (rc != X86EMUL_CONTINUE)
		return rc;

2775
	ctxt->src.val = old_eip;
2776
	return em_push(ctxt);
2777 2778
}

2779 2780 2781 2782
static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
{
	int rc;

2783 2784 2785 2786
	ctxt->dst.type = OP_REG;
	ctxt->dst.addr.reg = &ctxt->_eip;
	ctxt->dst.bytes = ctxt->op_bytes;
	rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
2787 2788
	if (rc != X86EMUL_CONTINUE)
		return rc;
2789
	register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val);
2790 2791 2792
	return X86EMUL_CONTINUE;
}

2793 2794
static int em_add(struct x86_emulate_ctxt *ctxt)
{
2795
	emulate_2op_SrcV(ctxt, "add");
2796 2797 2798 2799 2800
	return X86EMUL_CONTINUE;
}

static int em_or(struct x86_emulate_ctxt *ctxt)
{
2801
	emulate_2op_SrcV(ctxt, "or");
2802 2803 2804 2805 2806
	return X86EMUL_CONTINUE;
}

static int em_adc(struct x86_emulate_ctxt *ctxt)
{
2807
	emulate_2op_SrcV(ctxt, "adc");
2808 2809 2810 2811 2812
	return X86EMUL_CONTINUE;
}

static int em_sbb(struct x86_emulate_ctxt *ctxt)
{
2813
	emulate_2op_SrcV(ctxt, "sbb");
2814 2815 2816 2817 2818
	return X86EMUL_CONTINUE;
}

static int em_and(struct x86_emulate_ctxt *ctxt)
{
2819
	emulate_2op_SrcV(ctxt, "and");
2820 2821 2822 2823 2824
	return X86EMUL_CONTINUE;
}

static int em_sub(struct x86_emulate_ctxt *ctxt)
{
2825
	emulate_2op_SrcV(ctxt, "sub");
2826 2827 2828 2829 2830
	return X86EMUL_CONTINUE;
}

static int em_xor(struct x86_emulate_ctxt *ctxt)
{
2831
	emulate_2op_SrcV(ctxt, "xor");
2832 2833 2834 2835 2836
	return X86EMUL_CONTINUE;
}

static int em_cmp(struct x86_emulate_ctxt *ctxt)
{
2837
	emulate_2op_SrcV(ctxt, "cmp");
2838
	/* Disable writeback. */
2839
	ctxt->dst.type = OP_NONE;
2840 2841 2842
	return X86EMUL_CONTINUE;
}

2843 2844
static int em_test(struct x86_emulate_ctxt *ctxt)
{
2845
	emulate_2op_SrcV(ctxt, "test");
2846 2847
	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
2848 2849 2850
	return X86EMUL_CONTINUE;
}

2851 2852 2853
static int em_xchg(struct x86_emulate_ctxt *ctxt)
{
	/* Write back the register source. */
2854 2855
	ctxt->src.val = ctxt->dst.val;
	write_register_operand(&ctxt->src);
2856 2857

	/* Write back the memory destination with implicit LOCK prefix. */
2858 2859
	ctxt->dst.val = ctxt->src.orig_val;
	ctxt->lock_prefix = 1;
2860 2861 2862
	return X86EMUL_CONTINUE;
}

2863
static int em_imul(struct x86_emulate_ctxt *ctxt)
2864
{
2865
	emulate_2op_SrcV_nobyte(ctxt, "imul");
2866 2867 2868
	return X86EMUL_CONTINUE;
}

2869 2870
static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
{
2871
	ctxt->dst.val = ctxt->src2.val;
2872 2873 2874
	return em_imul(ctxt);
}

2875 2876
static int em_cwd(struct x86_emulate_ctxt *ctxt)
{
2877 2878 2879 2880
	ctxt->dst.type = OP_REG;
	ctxt->dst.bytes = ctxt->src.bytes;
	ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
	ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
2881 2882 2883 2884

	return X86EMUL_CONTINUE;
}

2885 2886 2887 2888
static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
{
	u64 tsc = 0;

2889
	ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
2890 2891
	ctxt->regs[VCPU_REGS_RAX] = (u32)tsc;
	ctxt->regs[VCPU_REGS_RDX] = tsc >> 32;
2892 2893 2894
	return X86EMUL_CONTINUE;
}

2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905
static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
{
	u64 pmc;

	if (ctxt->ops->read_pmc(ctxt, ctxt->regs[VCPU_REGS_RCX], &pmc))
		return emulate_gp(ctxt, 0);
	ctxt->regs[VCPU_REGS_RAX] = (u32)pmc;
	ctxt->regs[VCPU_REGS_RDX] = pmc >> 32;
	return X86EMUL_CONTINUE;
}

2906 2907
static int em_mov(struct x86_emulate_ctxt *ctxt)
{
S
Stefan Hajnoczi 已提交
2908
	memcpy(ctxt->dst.valptr, ctxt->src.valptr, ctxt->op_bytes);
2909 2910 2911
	return X86EMUL_CONTINUE;
}

2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939
static int em_cr_write(struct x86_emulate_ctxt *ctxt)
{
	if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
		return emulate_gp(ctxt, 0);

	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

static int em_dr_write(struct x86_emulate_ctxt *ctxt)
{
	unsigned long val;

	if (ctxt->mode == X86EMUL_MODE_PROT64)
		val = ctxt->src.val & ~0ULL;
	else
		val = ctxt->src.val & ~0U;

	/* #UD condition is already handled. */
	if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
		return emulate_gp(ctxt, 0);

	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963
static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
{
	u64 msr_data;

	msr_data = (u32)ctxt->regs[VCPU_REGS_RAX]
		| ((u64)ctxt->regs[VCPU_REGS_RDX] << 32);
	if (ctxt->ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data))
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
{
	u64 msr_data;

	if (ctxt->ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data))
		return emulate_gp(ctxt, 0);

	ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data;
	ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32;
	return X86EMUL_CONTINUE;
}

2964 2965
static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
{
2966
	if (ctxt->modrm_reg > VCPU_SREG_GS)
2967 2968
		return emulate_ud(ctxt);

2969
	ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
2970 2971 2972 2973 2974
	return X86EMUL_CONTINUE;
}

static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
{
2975
	u16 sel = ctxt->src.val;
2976

2977
	if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
2978 2979
		return emulate_ud(ctxt);

2980
	if (ctxt->modrm_reg == VCPU_SREG_SS)
2981 2982 2983
		ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;

	/* Disable writeback. */
2984 2985
	ctxt->dst.type = OP_NONE;
	return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
2986 2987
}

2988 2989
static int em_invlpg(struct x86_emulate_ctxt *ctxt)
{
2990 2991 2992
	int rc;
	ulong linear;

2993
	rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
2994
	if (rc == X86EMUL_CONTINUE)
2995
		ctxt->ops->invlpg(ctxt, linear);
2996
	/* Disable writeback. */
2997
	ctxt->dst.type = OP_NONE;
2998 2999 3000
	return X86EMUL_CONTINUE;
}

3001 3002 3003 3004 3005 3006 3007 3008 3009 3010
static int em_clts(struct x86_emulate_ctxt *ctxt)
{
	ulong cr0;

	cr0 = ctxt->ops->get_cr(ctxt, 0);
	cr0 &= ~X86_CR0_TS;
	ctxt->ops->set_cr(ctxt, 0, cr0);
	return X86EMUL_CONTINUE;
}

3011 3012 3013 3014
static int em_vmcall(struct x86_emulate_ctxt *ctxt)
{
	int rc;

3015
	if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
3016 3017 3018 3019 3020 3021 3022
		return X86EMUL_UNHANDLEABLE;

	rc = ctxt->ops->fix_hypercall(ctxt);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	/* Let the processor re-execute the fixed hypercall */
3023
	ctxt->_eip = ctxt->eip;
3024
	/* Disable writeback. */
3025
	ctxt->dst.type = OP_NONE;
3026 3027 3028
	return X86EMUL_CONTINUE;
}

3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053 3054 3055 3056 3057
static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
				  void (*get)(struct x86_emulate_ctxt *ctxt,
					      struct desc_ptr *ptr))
{
	struct desc_ptr desc_ptr;

	if (ctxt->mode == X86EMUL_MODE_PROT64)
		ctxt->op_bytes = 8;
	get(ctxt, &desc_ptr);
	if (ctxt->op_bytes == 2) {
		ctxt->op_bytes = 4;
		desc_ptr.address &= 0x00ffffff;
	}
	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return segmented_write(ctxt, ctxt->dst.addr.mem,
			       &desc_ptr, 2 + ctxt->op_bytes);
}

static int em_sgdt(struct x86_emulate_ctxt *ctxt)
{
	return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
}

static int em_sidt(struct x86_emulate_ctxt *ctxt)
{
	return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
}

3058 3059 3060 3061 3062
static int em_lgdt(struct x86_emulate_ctxt *ctxt)
{
	struct desc_ptr desc_ptr;
	int rc;

3063 3064
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		ctxt->op_bytes = 8;
3065
	rc = read_descriptor(ctxt, ctxt->src.addr.mem,
3066
			     &desc_ptr.size, &desc_ptr.address,
3067
			     ctxt->op_bytes);
3068 3069 3070 3071
	if (rc != X86EMUL_CONTINUE)
		return rc;
	ctxt->ops->set_gdt(ctxt, &desc_ptr);
	/* Disable writeback. */
3072
	ctxt->dst.type = OP_NONE;
3073 3074 3075
	return X86EMUL_CONTINUE;
}

3076
static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
3077 3078 3079
{
	int rc;

3080 3081
	rc = ctxt->ops->fix_hypercall(ctxt);

3082
	/* Disable writeback. */
3083
	ctxt->dst.type = OP_NONE;
3084 3085 3086 3087 3088 3089 3090 3091
	return rc;
}

static int em_lidt(struct x86_emulate_ctxt *ctxt)
{
	struct desc_ptr desc_ptr;
	int rc;

3092 3093
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		ctxt->op_bytes = 8;
3094
	rc = read_descriptor(ctxt, ctxt->src.addr.mem,
3095
			     &desc_ptr.size, &desc_ptr.address,
3096
			     ctxt->op_bytes);
3097 3098 3099 3100
	if (rc != X86EMUL_CONTINUE)
		return rc;
	ctxt->ops->set_idt(ctxt, &desc_ptr);
	/* Disable writeback. */
3101
	ctxt->dst.type = OP_NONE;
3102 3103 3104 3105 3106
	return X86EMUL_CONTINUE;
}

static int em_smsw(struct x86_emulate_ctxt *ctxt)
{
3107 3108
	ctxt->dst.bytes = 2;
	ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
3109 3110 3111 3112 3113 3114
	return X86EMUL_CONTINUE;
}

static int em_lmsw(struct x86_emulate_ctxt *ctxt)
{
	ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
3115 3116
			  | (ctxt->src.val & 0x0f));
	ctxt->dst.type = OP_NONE;
3117 3118 3119
	return X86EMUL_CONTINUE;
}

3120 3121
static int em_loop(struct x86_emulate_ctxt *ctxt)
{
3122 3123 3124 3125
	register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
	if ((address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) != 0) &&
	    (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
		jmp_rel(ctxt, ctxt->src.val);
3126 3127 3128 3129 3130 3131

	return X86EMUL_CONTINUE;
}

static int em_jcxz(struct x86_emulate_ctxt *ctxt)
{
3132 3133
	if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0)
		jmp_rel(ctxt, ctxt->src.val);
3134 3135 3136 3137

	return X86EMUL_CONTINUE;
}

3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154 3155
static int em_in(struct x86_emulate_ctxt *ctxt)
{
	if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
			     &ctxt->dst.val))
		return X86EMUL_IO_NEEDED;

	return X86EMUL_CONTINUE;
}

static int em_out(struct x86_emulate_ctxt *ctxt)
{
	ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
				    &ctxt->src.val, 1);
	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174
static int em_cli(struct x86_emulate_ctxt *ctxt)
{
	if (emulator_bad_iopl(ctxt))
		return emulate_gp(ctxt, 0);

	ctxt->eflags &= ~X86_EFLAGS_IF;
	return X86EMUL_CONTINUE;
}

static int em_sti(struct x86_emulate_ctxt *ctxt)
{
	if (emulator_bad_iopl(ctxt))
		return emulate_gp(ctxt, 0);

	ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
	ctxt->eflags |= X86_EFLAGS_IF;
	return X86EMUL_CONTINUE;
}

3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203
static int em_bt(struct x86_emulate_ctxt *ctxt)
{
	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	/* only subword offset */
	ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;

	emulate_2op_SrcV_nobyte(ctxt, "bt");
	return X86EMUL_CONTINUE;
}

static int em_bts(struct x86_emulate_ctxt *ctxt)
{
	emulate_2op_SrcV_nobyte(ctxt, "bts");
	return X86EMUL_CONTINUE;
}

static int em_btr(struct x86_emulate_ctxt *ctxt)
{
	emulate_2op_SrcV_nobyte(ctxt, "btr");
	return X86EMUL_CONTINUE;
}

static int em_btc(struct x86_emulate_ctxt *ctxt)
{
	emulate_2op_SrcV_nobyte(ctxt, "btc");
	return X86EMUL_CONTINUE;
}

3204 3205
static int em_bsf(struct x86_emulate_ctxt *ctxt)
{
3206
	emulate_2op_SrcV_nobyte(ctxt, "bsf");
3207 3208 3209 3210 3211
	return X86EMUL_CONTINUE;
}

static int em_bsr(struct x86_emulate_ctxt *ctxt)
{
3212
	emulate_2op_SrcV_nobyte(ctxt, "bsr");
3213 3214 3215
	return X86EMUL_CONTINUE;
}

A
Avi Kivity 已提交
3216 3217 3218 3219 3220 3221 3222 3223 3224 3225 3226 3227 3228 3229
static int em_cpuid(struct x86_emulate_ctxt *ctxt)
{
	u32 eax, ebx, ecx, edx;

	eax = ctxt->regs[VCPU_REGS_RAX];
	ecx = ctxt->regs[VCPU_REGS_RCX];
	ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
	ctxt->regs[VCPU_REGS_RAX] = eax;
	ctxt->regs[VCPU_REGS_RBX] = ebx;
	ctxt->regs[VCPU_REGS_RCX] = ecx;
	ctxt->regs[VCPU_REGS_RDX] = edx;
	return X86EMUL_CONTINUE;
}

A
Avi Kivity 已提交
3230 3231 3232 3233 3234 3235 3236
static int em_lahf(struct x86_emulate_ctxt *ctxt)
{
	ctxt->regs[VCPU_REGS_RAX] &= ~0xff00UL;
	ctxt->regs[VCPU_REGS_RAX] |= (ctxt->eflags & 0xff) << 8;
	return X86EMUL_CONTINUE;
}

3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247 3248 3249 3250
static bool valid_cr(int nr)
{
	switch (nr) {
	case 0:
	case 2 ... 4:
	case 8:
		return true;
	default:
		return false;
	}
}

static int check_cr_read(struct x86_emulate_ctxt *ctxt)
{
3251
	if (!valid_cr(ctxt->modrm_reg))
3252 3253 3254 3255 3256 3257 3258
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_cr_write(struct x86_emulate_ctxt *ctxt)
{
3259 3260
	u64 new_val = ctxt->src.val64;
	int cr = ctxt->modrm_reg;
3261
	u64 efer = 0;
3262 3263 3264 3265 3266 3267 3268 3269 3270 3271 3272 3273 3274 3275 3276 3277 3278

	static u64 cr_reserved_bits[] = {
		0xffffffff00000000ULL,
		0, 0, 0, /* CR3 checked later */
		CR4_RESERVED_BITS,
		0, 0, 0,
		CR8_RESERVED_BITS,
	};

	if (!valid_cr(cr))
		return emulate_ud(ctxt);

	if (new_val & cr_reserved_bits[cr])
		return emulate_gp(ctxt, 0);

	switch (cr) {
	case 0: {
3279
		u64 cr4;
3280 3281 3282 3283
		if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
		    ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
			return emulate_gp(ctxt, 0);

3284 3285
		cr4 = ctxt->ops->get_cr(ctxt, 4);
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3286 3287 3288 3289 3290 3291 3292 3293 3294 3295

		if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
		    !(cr4 & X86_CR4_PAE))
			return emulate_gp(ctxt, 0);

		break;
		}
	case 3: {
		u64 rsvd = 0;

3296 3297
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
		if (efer & EFER_LMA)
3298
			rsvd = CR3_L_MODE_RESERVED_BITS;
3299
		else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
3300
			rsvd = CR3_PAE_RESERVED_BITS;
3301
		else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
3302 3303 3304 3305 3306 3307 3308 3309
			rsvd = CR3_NONPAE_RESERVED_BITS;

		if (new_val & rsvd)
			return emulate_gp(ctxt, 0);

		break;
		}
	case 4: {
3310
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321

		if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
			return emulate_gp(ctxt, 0);

		break;
		}
	}

	return X86EMUL_CONTINUE;
}

3322 3323 3324 3325
static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
{
	unsigned long dr7;

3326
	ctxt->ops->get_dr(ctxt, 7, &dr7);
3327 3328 3329 3330 3331 3332 3333

	/* Check if DR7.Global_Enable is set */
	return dr7 & (1 << 13);
}

static int check_dr_read(struct x86_emulate_ctxt *ctxt)
{
3334
	int dr = ctxt->modrm_reg;
3335 3336 3337 3338 3339
	u64 cr4;

	if (dr > 7)
		return emulate_ud(ctxt);

3340
	cr4 = ctxt->ops->get_cr(ctxt, 4);
3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351
	if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
		return emulate_ud(ctxt);

	if (check_dr7_gd(ctxt))
		return emulate_db(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_dr_write(struct x86_emulate_ctxt *ctxt)
{
3352 3353
	u64 new_val = ctxt->src.val64;
	int dr = ctxt->modrm_reg;
3354 3355 3356 3357 3358 3359 3360

	if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
		return emulate_gp(ctxt, 0);

	return check_dr_read(ctxt);
}

3361 3362 3363 3364
static int check_svme(struct x86_emulate_ctxt *ctxt)
{
	u64 efer;

3365
	ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3366 3367 3368 3369 3370 3371 3372 3373 3374

	if (!(efer & EFER_SVME))
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
{
3375
	u64 rax = ctxt->regs[VCPU_REGS_RAX];
3376 3377

	/* Valid physical address? */
3378
	if (rax & 0xffff000000000000ULL)
3379 3380 3381 3382 3383
		return emulate_gp(ctxt, 0);

	return check_svme(ctxt);
}

3384 3385
static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
{
3386
	u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
3387

3388
	if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
3389 3390 3391 3392 3393
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

3394 3395
static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
{
3396
	u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
3397
	u64 rcx = ctxt->regs[VCPU_REGS_RCX];
3398

3399
	if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
3400 3401 3402 3403 3404 3405
	    (rcx > 3))
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

3406 3407
static int check_perm_in(struct x86_emulate_ctxt *ctxt)
{
3408 3409
	ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
	if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
3410 3411 3412 3413 3414 3415 3416
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

static int check_perm_out(struct x86_emulate_ctxt *ctxt)
{
3417 3418
	ctxt->src.bytes = min(ctxt->src.bytes, 4u);
	if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
3419 3420 3421 3422 3423
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

3424
#define D(_y) { .flags = (_y) }
3425
#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
3426 3427
#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
		      .check_perm = (_p) }
3428
#define N    D(0)
3429
#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
3430 3431
#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
3432
#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
3433 3434
#define II(_f, _e, _i) \
	{ .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
3435 3436 3437
#define IIP(_f, _e, _i, _p) \
	{ .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
	  .check_perm = (_p) }
3438
#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
3439

3440
#define D2bv(_f)      D((_f) | ByteOp), D(_f)
3441
#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
3442
#define I2bv(_f, _e)  I((_f) | ByteOp, _e), I(_f, _e)
3443 3444
#define I2bvIP(_f, _e, _i, _p) \
	IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
3445

3446 3447 3448
#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e),		\
		I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e),	\
		I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
3449

3450
static struct opcode group7_rm1[] = {
3451 3452
	DI(SrcNone | Priv, monitor),
	DI(SrcNone | Priv, mwait),
3453 3454 3455
	N, N, N, N, N, N,
};

3456
static struct opcode group7_rm3[] = {
3457 3458 3459 3460 3461 3462 3463 3464
	DIP(SrcNone | Prot | Priv,		vmrun,		check_svme_pa),
	II(SrcNone  | Prot | VendorSpecific,	em_vmmcall,	vmmcall),
	DIP(SrcNone | Prot | Priv,		vmload,		check_svme_pa),
	DIP(SrcNone | Prot | Priv,		vmsave,		check_svme_pa),
	DIP(SrcNone | Prot | Priv,		stgi,		check_svme),
	DIP(SrcNone | Prot | Priv,		clgi,		check_svme),
	DIP(SrcNone | Prot | Priv,		skinit,		check_svme),
	DIP(SrcNone | Prot | Priv,		invlpga,	check_svme),
3465
};
3466

3467 3468
static struct opcode group7_rm7[] = {
	N,
3469
	DIP(SrcNone, rdtscp, check_rdtsc),
3470 3471
	N, N, N, N, N, N,
};
3472

3473
static struct opcode group1[] = {
3474
	I(Lock, em_add),
3475
	I(Lock | PageTable, em_or),
3476 3477
	I(Lock, em_adc),
	I(Lock, em_sbb),
3478
	I(Lock | PageTable, em_and),
3479 3480 3481
	I(Lock, em_sub),
	I(Lock, em_xor),
	I(0, em_cmp),
3482 3483 3484
};

static struct opcode group1A[] = {
3485
	I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
3486 3487 3488
};

static struct opcode group3[] = {
3489 3490 3491 3492 3493 3494 3495 3496
	I(DstMem | SrcImm, em_test),
	I(DstMem | SrcImm, em_test),
	I(DstMem | SrcNone | Lock, em_not),
	I(DstMem | SrcNone | Lock, em_neg),
	I(SrcMem, em_mul_ex),
	I(SrcMem, em_imul_ex),
	I(SrcMem, em_div_ex),
	I(SrcMem, em_idiv_ex),
3497 3498 3499
};

static struct opcode group4[] = {
3500 3501
	I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
	I(ByteOp | DstMem | SrcNone | Lock, em_grp45),
3502 3503 3504 3505
	N, N, N, N, N, N,
};

static struct opcode group5[] = {
3506 3507 3508 3509 3510 3511 3512
	I(DstMem | SrcNone | Lock,		em_grp45),
	I(DstMem | SrcNone | Lock,		em_grp45),
	I(SrcMem | Stack,			em_grp45),
	I(SrcMemFAddr | ImplicitOps | Stack,	em_call_far),
	I(SrcMem | Stack,			em_grp45),
	I(SrcMemFAddr | ImplicitOps,		em_grp45),
	I(SrcMem | Stack,			em_grp45), N,
3513 3514
};

3515
static struct opcode group6[] = {
3516 3517 3518 3519
	DI(Prot,	sldt),
	DI(Prot,	str),
	DI(Prot | Priv,	lldt),
	DI(Prot | Priv,	ltr),
3520 3521 3522
	N, N, N, N,
};

3523
static struct group_dual group7 = { {
3524 3525
	II(Mov | DstMem | Priv,			em_sgdt, sgdt),
	II(Mov | DstMem | Priv,			em_sidt, sidt),
3526 3527 3528 3529 3530
	II(SrcMem | Priv,			em_lgdt, lgdt),
	II(SrcMem | Priv,			em_lidt, lidt),
	II(SrcNone | DstMem | Mov,		em_smsw, smsw), N,
	II(SrcMem16 | Mov | Priv,		em_lmsw, lmsw),
	II(SrcMem | ByteOp | Priv | NoAccess,	em_invlpg, invlpg),
3531
}, {
3532
	I(SrcNone | Priv | VendorSpecific,	em_vmcall),
3533
	EXT(0, group7_rm1),
3534
	N, EXT(0, group7_rm3),
3535 3536 3537
	II(SrcNone | DstMem | Mov,		em_smsw, smsw), N,
	II(SrcMem16 | Mov | Priv,		em_lmsw, lmsw),
	EXT(0, group7_rm7),
3538 3539 3540 3541
} };

static struct opcode group8[] = {
	N, N, N, N,
3542 3543 3544 3545
	I(DstMem | SrcImmByte,				em_bt),
	I(DstMem | SrcImmByte | Lock | PageTable,	em_bts),
	I(DstMem | SrcImmByte | Lock,			em_btr),
	I(DstMem | SrcImmByte | Lock | PageTable,	em_btc),
3546 3547 3548
};

static struct group_dual group9 = { {
3549
	N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
3550 3551 3552 3553
}, {
	N, N, N, N, N, N, N, N,
} };

3554
static struct opcode group11[] = {
3555
	I(DstMem | SrcImm | Mov | PageTable, em_mov),
3556
	X7(D(Undefined)),
3557 3558
};

3559
static struct gprefix pfx_0f_6f_0f_7f = {
3560
	I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
3561 3562
};

3563 3564 3565 3566
static struct gprefix pfx_vmovntpx = {
	I(0, em_mov), N, N, N,
};

3567 3568
static struct opcode opcode_table[256] = {
	/* 0x00 - 0x07 */
3569
	I6ALU(Lock, em_add),
3570 3571
	I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
	I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
3572
	/* 0x08 - 0x0F */
3573
	I6ALU(Lock | PageTable, em_or),
3574 3575
	I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
	N,
3576
	/* 0x10 - 0x17 */
3577
	I6ALU(Lock, em_adc),
3578 3579
	I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
	I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
3580
	/* 0x18 - 0x1F */
3581
	I6ALU(Lock, em_sbb),
3582 3583
	I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
	I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
3584
	/* 0x20 - 0x27 */
3585
	I6ALU(Lock | PageTable, em_and), N, N,
3586
	/* 0x28 - 0x2F */
3587
	I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
3588
	/* 0x30 - 0x37 */
3589
	I6ALU(Lock, em_xor), N, N,
3590
	/* 0x38 - 0x3F */
3591
	I6ALU(0, em_cmp), N, N,
3592 3593 3594
	/* 0x40 - 0x4F */
	X16(D(DstReg)),
	/* 0x50 - 0x57 */
3595
	X8(I(SrcReg | Stack, em_push)),
3596
	/* 0x58 - 0x5F */
3597
	X8(I(DstReg | Stack, em_pop)),
3598
	/* 0x60 - 0x67 */
3599 3600
	I(ImplicitOps | Stack | No64, em_pusha),
	I(ImplicitOps | Stack | No64, em_popa),
3601 3602 3603
	N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
	N, N, N, N,
	/* 0x68 - 0x6F */
3604 3605
	I(SrcImm | Mov | Stack, em_push),
	I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
3606 3607
	I(SrcImmByte | Mov | Stack, em_push),
	I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
3608 3609
	I2bvIP(DstDI | SrcDX | Mov | String, em_in, ins, check_perm_in), /* insb, insw/insd */
	I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
3610 3611 3612
	/* 0x70 - 0x7F */
	X16(D(SrcImmByte)),
	/* 0x80 - 0x87 */
3613 3614 3615 3616
	G(ByteOp | DstMem | SrcImm, group1),
	G(DstMem | SrcImm, group1),
	G(ByteOp | DstMem | SrcImm | No64, group1),
	G(DstMem | SrcImmByte, group1),
3617
	I2bv(DstMem | SrcReg | ModRM, em_test),
3618
	I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
3619
	/* 0x88 - 0x8F */
3620
	I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
3621
	I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
3622
	I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
3623 3624 3625
	D(ModRM | SrcMem | NoAccess | DstReg),
	I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
	G(0, group1A),
3626
	/* 0x90 - 0x97 */
3627
	DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
3628
	/* 0x98 - 0x9F */
3629
	D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
3630
	I(SrcImmFAddr | No64, em_call_far), N,
3631
	II(ImplicitOps | Stack, em_pushf, pushf),
A
Avi Kivity 已提交
3632
	II(ImplicitOps | Stack, em_popf, popf), N, I(ImplicitOps, em_lahf),
3633
	/* 0xA0 - 0xA7 */
3634
	I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
3635
	I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
3636
	I2bv(SrcSI | DstDI | Mov | String, em_mov),
3637
	I2bv(SrcSI | DstDI | String, em_cmp),
3638
	/* 0xA8 - 0xAF */
3639
	I2bv(DstAcc | SrcImm, em_test),
3640 3641
	I2bv(SrcAcc | DstDI | Mov | String, em_mov),
	I2bv(SrcSI | DstAcc | Mov | String, em_mov),
3642
	I2bv(SrcAcc | DstDI | String, em_cmp),
3643
	/* 0xB0 - 0xB7 */
3644
	X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
3645
	/* 0xB8 - 0xBF */
3646
	X8(I(DstReg | SrcImm | Mov, em_mov)),
3647
	/* 0xC0 - 0xC7 */
3648
	D2bv(DstMem | SrcImmByte | ModRM),
3649
	I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
3650
	I(ImplicitOps | Stack, em_ret),
3651 3652
	I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
	I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
3653
	G(ByteOp, group11), G(0, group11),
3654
	/* 0xC8 - 0xCF */
A
Avi Kivity 已提交
3655
	N, I(Stack, em_leave), N, I(ImplicitOps | Stack, em_ret_far),
3656
	D(ImplicitOps), DI(SrcImmByte, intn),
3657
	D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
3658
	/* 0xD0 - 0xD7 */
3659
	D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
3660 3661 3662 3663
	N, N, N, N,
	/* 0xD8 - 0xDF */
	N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xE7 */
3664 3665
	X3(I(SrcImmByte, em_loop)),
	I(SrcImmByte, em_jcxz),
3666 3667
	I2bvIP(SrcImmUByte | DstAcc, em_in,  in,  check_perm_in),
	I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
3668
	/* 0xE8 - 0xEF */
3669
	I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
3670
	I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
3671 3672
	I2bvIP(SrcDX | DstAcc, em_in,  in,  check_perm_in),
	I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
3673
	/* 0xF0 - 0xF7 */
3674
	N, DI(ImplicitOps, icebp), N, N,
3675 3676
	DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
	G(ByteOp, group3), G(0, group3),
3677
	/* 0xF8 - 0xFF */
3678 3679
	D(ImplicitOps), D(ImplicitOps),
	I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
3680 3681 3682 3683 3684
	D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
};

static struct opcode twobyte_table[256] = {
	/* 0x00 - 0x0F */
3685
	G(0, group6), GD(0, &group7), N, N,
3686 3687
	N, I(ImplicitOps | VendorSpecific, em_syscall),
	II(ImplicitOps | Priv, em_clts, clts), N,
3688
	DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3689 3690 3691 3692
	N, D(ImplicitOps | ModRM), N, N,
	/* 0x10 - 0x1F */
	N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
	/* 0x20 - 0x2F */
3693
	DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3694
	DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
3695 3696
	IIP(ModRM | SrcMem | Priv | Op3264, em_cr_write, cr_write, check_cr_write),
	IIP(ModRM | SrcMem | Priv | Op3264, em_dr_write, dr_write, check_dr_write),
3697
	N, N, N, N,
3698 3699
	N, N, N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
	N, N, N, N,
3700
	/* 0x30 - 0x3F */
3701
	II(ImplicitOps | Priv, em_wrmsr, wrmsr),
3702
	IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
3703
	II(ImplicitOps | Priv, em_rdmsr, rdmsr),
3704
	IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
3705 3706
	I(ImplicitOps | VendorSpecific, em_sysenter),
	I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
3707
	N, N,
3708 3709 3710 3711 3712 3713
	N, N, N, N, N, N, N, N,
	/* 0x40 - 0x4F */
	X16(D(DstReg | SrcMem | ModRM | Mov)),
	/* 0x50 - 0x5F */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0x60 - 0x6F */
3714 3715 3716 3717
	N, N, N, N,
	N, N, N, N,
	N, N, N, N,
	N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
3718
	/* 0x70 - 0x7F */
3719 3720 3721 3722
	N, N, N, N,
	N, N, N, N,
	N, N, N, N,
	N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
3723 3724 3725
	/* 0x80 - 0x8F */
	X16(D(SrcImm)),
	/* 0x90 - 0x9F */
3726
	X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
3727
	/* 0xA0 - 0xA7 */
3728
	I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
A
Avi Kivity 已提交
3729
	II(ImplicitOps, em_cpuid, cpuid), I(DstMem | SrcReg | ModRM | BitOp, em_bt),
3730 3731 3732
	D(DstMem | SrcReg | Src2ImmByte | ModRM),
	D(DstMem | SrcReg | Src2CL | ModRM), N, N,
	/* 0xA8 - 0xAF */
3733
	I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
3734
	DI(ImplicitOps, rsm),
3735
	I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
3736 3737
	D(DstMem | SrcReg | Src2ImmByte | ModRM),
	D(DstMem | SrcReg | Src2CL | ModRM),
3738
	D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
3739
	/* 0xB0 - 0xB7 */
3740
	I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
3741
	I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
3742
	I(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
3743 3744
	I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
	I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
3745
	D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3746 3747
	/* 0xB8 - 0xBF */
	N, N,
3748 3749
	G(BitOp, group8),
	I(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
3750
	I(DstReg | SrcMem | ModRM, em_bsf), I(DstReg | SrcMem | ModRM, em_bsr),
3751
	D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3752
	/* 0xC0 - 0xCF */
3753
	D2bv(DstMem | SrcReg | ModRM | Lock),
3754
	N, D(DstMem | SrcReg | ModRM | Mov),
3755 3756 3757 3758 3759 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769
	N, N, N, GD(0, &group9),
	N, N, N, N, N, N, N, N,
	/* 0xD0 - 0xDF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xEF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0xF0 - 0xFF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
};

#undef D
#undef N
#undef G
#undef GD
#undef I
3770
#undef GP
3771
#undef EXT
3772

3773
#undef D2bv
3774
#undef D2bvIP
3775
#undef I2bv
3776
#undef I2bvIP
3777
#undef I6ALU
3778

3779
static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
3780 3781 3782
{
	unsigned size;

3783
	size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3784 3785 3786 3787 3788 3789 3790 3791 3792 3793 3794 3795
	if (size == 8)
		size = 4;
	return size;
}

static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
		      unsigned size, bool sign_extension)
{
	int rc = X86EMUL_CONTINUE;

	op->type = OP_IMM;
	op->bytes = size;
3796
	op->addr.mem.ea = ctxt->_eip;
3797 3798 3799
	/* NB. Immediates are sign-extended as necessary. */
	switch (op->bytes) {
	case 1:
3800
		op->val = insn_fetch(s8, ctxt);
3801 3802
		break;
	case 2:
3803
		op->val = insn_fetch(s16, ctxt);
3804 3805
		break;
	case 4:
3806
		op->val = insn_fetch(s32, ctxt);
3807 3808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 3823 3824 3825
		break;
	}
	if (!sign_extension) {
		switch (op->bytes) {
		case 1:
			op->val &= 0xff;
			break;
		case 2:
			op->val &= 0xffff;
			break;
		case 4:
			op->val &= 0xffffffff;
			break;
		}
	}
done:
	return rc;
}

3826 3827 3828 3829 3830 3831 3832
static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
			  unsigned d)
{
	int rc = X86EMUL_CONTINUE;

	switch (d) {
	case OpReg:
3833
		decode_register_operand(ctxt, op);
3834 3835
		break;
	case OpImmUByte:
3836
		rc = decode_imm(ctxt, op, 1, false);
3837 3838
		break;
	case OpMem:
3839
		ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3840 3841 3842 3843
	mem_common:
		*op = ctxt->memop;
		ctxt->memopp = op;
		if ((ctxt->d & BitOp) && op == &ctxt->dst)
3844 3845 3846
			fetch_bit_operand(ctxt);
		op->orig_val = op->val;
		break;
3847 3848 3849
	case OpMem64:
		ctxt->memop.bytes = 8;
		goto mem_common;
3850 3851 3852 3853 3854 3855 3856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870
	case OpAcc:
		op->type = OP_REG;
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		op->addr.reg = &ctxt->regs[VCPU_REGS_RAX];
		fetch_register_operand(op);
		op->orig_val = op->val;
		break;
	case OpDI:
		op->type = OP_MEM;
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		op->addr.mem.ea =
			register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]);
		op->addr.mem.seg = VCPU_SREG_ES;
		op->val = 0;
		break;
	case OpDX:
		op->type = OP_REG;
		op->bytes = 2;
		op->addr.reg = &ctxt->regs[VCPU_REGS_RDX];
		fetch_register_operand(op);
		break;
3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884
	case OpCL:
		op->bytes = 1;
		op->val = ctxt->regs[VCPU_REGS_RCX] & 0xff;
		break;
	case OpImmByte:
		rc = decode_imm(ctxt, op, 1, true);
		break;
	case OpOne:
		op->bytes = 1;
		op->val = 1;
		break;
	case OpImm:
		rc = decode_imm(ctxt, op, imm_size(ctxt), true);
		break;
3885 3886 3887
	case OpMem8:
		ctxt->memop.bytes = 1;
		goto mem_common;
3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916
	case OpMem16:
		ctxt->memop.bytes = 2;
		goto mem_common;
	case OpMem32:
		ctxt->memop.bytes = 4;
		goto mem_common;
	case OpImmU16:
		rc = decode_imm(ctxt, op, 2, false);
		break;
	case OpImmU:
		rc = decode_imm(ctxt, op, imm_size(ctxt), false);
		break;
	case OpSI:
		op->type = OP_MEM;
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		op->addr.mem.ea =
			register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]);
		op->addr.mem.seg = seg_override(ctxt);
		op->val = 0;
		break;
	case OpImmFAddr:
		op->type = OP_IMM;
		op->addr.mem.ea = ctxt->_eip;
		op->bytes = ctxt->op_bytes + 2;
		insn_fetch_arr(op->valptr, op->bytes, ctxt);
		break;
	case OpMemFAddr:
		ctxt->memop.bytes = ctxt->op_bytes + 2;
		goto mem_common;
3917 3918 3919 3920 3921 3922 3923 3924 3925 3926 3927 3928 3929 3930 3931 3932 3933 3934
	case OpES:
		op->val = VCPU_SREG_ES;
		break;
	case OpCS:
		op->val = VCPU_SREG_CS;
		break;
	case OpSS:
		op->val = VCPU_SREG_SS;
		break;
	case OpDS:
		op->val = VCPU_SREG_DS;
		break;
	case OpFS:
		op->val = VCPU_SREG_FS;
		break;
	case OpGS:
		op->val = VCPU_SREG_GS;
		break;
3935 3936 3937 3938 3939 3940 3941 3942 3943 3944 3945
	case OpImplicit:
		/* Special instructions do their own operand decoding. */
	default:
		op->type = OP_NONE; /* Disable writeback. */
		break;
	}

done:
	return rc;
}

3946
int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
3947 3948 3949
{
	int rc = X86EMUL_CONTINUE;
	int mode = ctxt->mode;
3950
	int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
3951
	bool op_prefix = false;
3952
	struct opcode opcode;
3953

3954 3955
	ctxt->memop.type = OP_NONE;
	ctxt->memopp = NULL;
3956 3957 3958
	ctxt->_eip = ctxt->eip;
	ctxt->fetch.start = ctxt->_eip;
	ctxt->fetch.end = ctxt->fetch.start + insn_len;
3959
	if (insn_len > 0)
3960
		memcpy(ctxt->fetch.data, insn, insn_len);
3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977

	switch (mode) {
	case X86EMUL_MODE_REAL:
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
		def_op_bytes = def_ad_bytes = 2;
		break;
	case X86EMUL_MODE_PROT32:
		def_op_bytes = def_ad_bytes = 4;
		break;
#ifdef CONFIG_X86_64
	case X86EMUL_MODE_PROT64:
		def_op_bytes = 4;
		def_ad_bytes = 8;
		break;
#endif
	default:
3978
		return EMULATION_FAILED;
3979 3980
	}

3981 3982
	ctxt->op_bytes = def_op_bytes;
	ctxt->ad_bytes = def_ad_bytes;
3983 3984 3985

	/* Legacy prefixes. */
	for (;;) {
3986
		switch (ctxt->b = insn_fetch(u8, ctxt)) {
3987
		case 0x66:	/* operand-size override */
3988
			op_prefix = true;
3989
			/* switch between 2/4 bytes */
3990
			ctxt->op_bytes = def_op_bytes ^ 6;
3991 3992 3993 3994
			break;
		case 0x67:	/* address-size override */
			if (mode == X86EMUL_MODE_PROT64)
				/* switch between 4/8 bytes */
3995
				ctxt->ad_bytes = def_ad_bytes ^ 12;
3996 3997
			else
				/* switch between 2/4 bytes */
3998
				ctxt->ad_bytes = def_ad_bytes ^ 6;
3999 4000 4001 4002 4003
			break;
		case 0x26:	/* ES override */
		case 0x2e:	/* CS override */
		case 0x36:	/* SS override */
		case 0x3e:	/* DS override */
4004
			set_seg_override(ctxt, (ctxt->b >> 3) & 3);
4005 4006 4007
			break;
		case 0x64:	/* FS override */
		case 0x65:	/* GS override */
4008
			set_seg_override(ctxt, ctxt->b & 7);
4009 4010 4011 4012
			break;
		case 0x40 ... 0x4f: /* REX */
			if (mode != X86EMUL_MODE_PROT64)
				goto done_prefixes;
4013
			ctxt->rex_prefix = ctxt->b;
4014 4015
			continue;
		case 0xf0:	/* LOCK */
4016
			ctxt->lock_prefix = 1;
4017 4018 4019
			break;
		case 0xf2:	/* REPNE/REPNZ */
		case 0xf3:	/* REP/REPE/REPZ */
4020
			ctxt->rep_prefix = ctxt->b;
4021 4022 4023 4024 4025 4026 4027
			break;
		default:
			goto done_prefixes;
		}

		/* Any legacy prefix after a REX prefix nullifies its effect. */

4028
		ctxt->rex_prefix = 0;
4029 4030 4031 4032 4033
	}

done_prefixes:

	/* REX prefix. */
4034 4035
	if (ctxt->rex_prefix & 8)
		ctxt->op_bytes = 8;	/* REX.W */
4036 4037

	/* Opcode byte(s). */
4038
	opcode = opcode_table[ctxt->b];
4039
	/* Two-byte opcode? */
4040 4041
	if (ctxt->b == 0x0f) {
		ctxt->twobyte = 1;
4042
		ctxt->b = insn_fetch(u8, ctxt);
4043
		opcode = twobyte_table[ctxt->b];
4044
	}
4045
	ctxt->d = opcode.flags;
4046

4047 4048 4049
	if (ctxt->d & ModRM)
		ctxt->modrm = insn_fetch(u8, ctxt);

4050 4051
	while (ctxt->d & GroupMask) {
		switch (ctxt->d & GroupMask) {
4052
		case Group:
4053
			goffset = (ctxt->modrm >> 3) & 7;
4054 4055 4056
			opcode = opcode.u.group[goffset];
			break;
		case GroupDual:
4057 4058
			goffset = (ctxt->modrm >> 3) & 7;
			if ((ctxt->modrm >> 6) == 3)
4059 4060 4061 4062 4063
				opcode = opcode.u.gdual->mod3[goffset];
			else
				opcode = opcode.u.gdual->mod012[goffset];
			break;
		case RMExt:
4064
			goffset = ctxt->modrm & 7;
4065
			opcode = opcode.u.group[goffset];
4066 4067
			break;
		case Prefix:
4068
			if (ctxt->rep_prefix && op_prefix)
4069
				return EMULATION_FAILED;
4070
			simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
4071 4072 4073 4074 4075 4076 4077 4078
			switch (simd_prefix) {
			case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
			case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
			case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
			case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
			}
			break;
		default:
4079
			return EMULATION_FAILED;
4080
		}
4081

4082
		ctxt->d &= ~(u64)GroupMask;
4083
		ctxt->d |= opcode.flags;
4084 4085
	}

4086 4087 4088
	ctxt->execute = opcode.u.execute;
	ctxt->check_perm = opcode.check_perm;
	ctxt->intercept = opcode.intercept;
4089 4090

	/* Unrecognised? */
4091
	if (ctxt->d == 0 || (ctxt->d & Undefined))
4092
		return EMULATION_FAILED;
4093

4094
	if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
4095
		return EMULATION_FAILED;
4096

4097 4098
	if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
		ctxt->op_bytes = 8;
4099

4100
	if (ctxt->d & Op3264) {
4101
		if (mode == X86EMUL_MODE_PROT64)
4102
			ctxt->op_bytes = 8;
4103
		else
4104
			ctxt->op_bytes = 4;
4105 4106
	}

4107 4108
	if (ctxt->d & Sse)
		ctxt->op_bytes = 16;
A
Avi Kivity 已提交
4109 4110
	else if (ctxt->d & Mmx)
		ctxt->op_bytes = 8;
A
Avi Kivity 已提交
4111

4112
	/* ModRM and SIB bytes. */
4113
	if (ctxt->d & ModRM) {
4114
		rc = decode_modrm(ctxt, &ctxt->memop);
4115 4116 4117
		if (!ctxt->has_seg_override)
			set_seg_override(ctxt, ctxt->modrm_seg);
	} else if (ctxt->d & MemAbs)
4118
		rc = decode_abs(ctxt, &ctxt->memop);
4119 4120 4121
	if (rc != X86EMUL_CONTINUE)
		goto done;

4122 4123
	if (!ctxt->has_seg_override)
		set_seg_override(ctxt, VCPU_SREG_DS);
4124

4125
	ctxt->memop.addr.mem.seg = seg_override(ctxt);
4126

4127 4128
	if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
		ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
4129 4130 4131 4132 4133

	/*
	 * Decode and fetch the source operand: register, memory
	 * or immediate.
	 */
4134
	rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
4135 4136 4137
	if (rc != X86EMUL_CONTINUE)
		goto done;

4138 4139 4140 4141
	/*
	 * Decode and fetch the second source operand: register, memory
	 * or immediate.
	 */
4142
	rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
4143 4144 4145
	if (rc != X86EMUL_CONTINUE)
		goto done;

4146
	/* Decode and fetch the destination operand: register or memory. */
4147
	rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
4148 4149

done:
4150 4151
	if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
		ctxt->memopp->addr.mem.ea += ctxt->_eip;
4152

4153
	return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
4154 4155
}

4156 4157 4158 4159 4160
bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
{
	return ctxt->d & PageTable;
}

4161 4162 4163 4164 4165 4166 4167 4168 4169
static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
{
	/* The second termination condition only applies for REPE
	 * and REPNE. Test if the repeat string operation prefix is
	 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
	 * corresponding termination condition according to:
	 * 	- if REPE/REPZ and ZF = 0 then done
	 * 	- if REPNE/REPNZ and ZF = 1 then done
	 */
4170 4171 4172
	if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
	     (ctxt->b == 0xae) || (ctxt->b == 0xaf))
	    && (((ctxt->rep_prefix == REPE_PREFIX) &&
4173
		 ((ctxt->eflags & EFLG_ZF) == 0))
4174
		|| ((ctxt->rep_prefix == REPNE_PREFIX) &&
4175 4176 4177 4178 4179 4180
		    ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
		return true;

	return false;
}

A
Avi Kivity 已提交
4181 4182 4183 4184 4185 4186 4187 4188 4189 4190 4191 4192 4193
static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
{
	bool fault = false;

	ctxt->ops->get_fpu(ctxt);
	asm volatile("1: fwait \n\t"
		     "2: \n\t"
		     ".pushsection .fixup,\"ax\" \n\t"
		     "3: \n\t"
		     "movb $1, %[fault] \n\t"
		     "jmp 2b \n\t"
		     ".popsection \n\t"
		     _ASM_EXTABLE(1b, 3b)
4194
		     : [fault]"+qm"(fault));
A
Avi Kivity 已提交
4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209
	ctxt->ops->put_fpu(ctxt);

	if (unlikely(fault))
		return emulate_exception(ctxt, MF_VECTOR, 0, false);

	return X86EMUL_CONTINUE;
}

static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
				       struct operand *op)
{
	if (op->type == OP_MM)
		read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
}

4210
int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
4211
{
4212
	struct x86_emulate_ops *ops = ctxt->ops;
4213
	int rc = X86EMUL_CONTINUE;
4214
	int saved_dst_type = ctxt->dst.type;
4215

4216
	ctxt->mem_read.pos = 0;
4217

4218
	if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
4219
		rc = emulate_ud(ctxt);
4220 4221 4222
		goto done;
	}

4223
	/* LOCK prefix is allowed only with some instructions */
4224
	if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
4225
		rc = emulate_ud(ctxt);
4226 4227 4228
		goto done;
	}

4229
	if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
4230
		rc = emulate_ud(ctxt);
4231 4232 4233
		goto done;
	}

A
Avi Kivity 已提交
4234 4235
	if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
	    || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
A
Avi Kivity 已提交
4236 4237 4238 4239
		rc = emulate_ud(ctxt);
		goto done;
	}

A
Avi Kivity 已提交
4240
	if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
A
Avi Kivity 已提交
4241 4242 4243 4244
		rc = emulate_nm(ctxt);
		goto done;
	}

A
Avi Kivity 已提交
4245 4246 4247 4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258
	if (ctxt->d & Mmx) {
		rc = flush_pending_x87_faults(ctxt);
		if (rc != X86EMUL_CONTINUE)
			goto done;
		/*
		 * Now that we know the fpu is exception safe, we can fetch
		 * operands from it.
		 */
		fetch_possible_mmx_operand(ctxt, &ctxt->src);
		fetch_possible_mmx_operand(ctxt, &ctxt->src2);
		if (!(ctxt->d & Mov))
			fetch_possible_mmx_operand(ctxt, &ctxt->dst);
	}

4259 4260
	if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
		rc = emulator_check_intercept(ctxt, ctxt->intercept,
4261
					      X86_ICPT_PRE_EXCEPT);
4262 4263 4264 4265
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

4266
	/* Privileged instruction can be executed only in CPL=0 */
4267
	if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
4268
		rc = emulate_gp(ctxt, 0);
4269 4270 4271
		goto done;
	}

4272
	/* Instruction can only be executed in protected mode */
4273
	if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
4274 4275 4276 4277
		rc = emulate_ud(ctxt);
		goto done;
	}

4278
	/* Do instruction specific permission checks */
4279 4280
	if (ctxt->check_perm) {
		rc = ctxt->check_perm(ctxt);
4281 4282 4283 4284
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

4285 4286
	if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
		rc = emulator_check_intercept(ctxt, ctxt->intercept,
4287
					      X86_ICPT_POST_EXCEPT);
4288 4289 4290 4291
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

4292
	if (ctxt->rep_prefix && (ctxt->d & String)) {
4293
		/* All REP prefixes have the same first termination condition */
4294 4295
		if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) {
			ctxt->eip = ctxt->_eip;
4296 4297 4298 4299
			goto done;
		}
	}

4300 4301 4302
	if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
		rc = segmented_read(ctxt, ctxt->src.addr.mem,
				    ctxt->src.valptr, ctxt->src.bytes);
4303
		if (rc != X86EMUL_CONTINUE)
4304
			goto done;
4305
		ctxt->src.orig_val64 = ctxt->src.val64;
4306 4307
	}

4308 4309 4310
	if (ctxt->src2.type == OP_MEM) {
		rc = segmented_read(ctxt, ctxt->src2.addr.mem,
				    &ctxt->src2.val, ctxt->src2.bytes);
4311 4312 4313 4314
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

4315
	if ((ctxt->d & DstMask) == ImplicitOps)
4316 4317 4318
		goto special_insn;


4319
	if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
4320
		/* optimisation - avoid slow emulated read if Mov */
4321 4322
		rc = segmented_read(ctxt, ctxt->dst.addr.mem,
				   &ctxt->dst.val, ctxt->dst.bytes);
4323 4324
		if (rc != X86EMUL_CONTINUE)
			goto done;
4325
	}
4326
	ctxt->dst.orig_val = ctxt->dst.val;
4327

4328 4329
special_insn:

4330 4331
	if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
		rc = emulator_check_intercept(ctxt, ctxt->intercept,
4332
					      X86_ICPT_POST_MEMACCESS);
4333 4334 4335 4336
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

4337 4338
	if (ctxt->execute) {
		rc = ctxt->execute(ctxt);
4339 4340 4341 4342 4343
		if (rc != X86EMUL_CONTINUE)
			goto done;
		goto writeback;
	}

4344
	if (ctxt->twobyte)
A
Avi Kivity 已提交
4345 4346
		goto twobyte_insn;

4347
	switch (ctxt->b) {
4348
	case 0x40 ... 0x47: /* inc r16/r32 */
4349
		emulate_1op(ctxt, "inc");
4350 4351
		break;
	case 0x48 ... 0x4f: /* dec r16/r32 */
4352
		emulate_1op(ctxt, "dec");
4353
		break;
A
Avi Kivity 已提交
4354
	case 0x63:		/* movsxd */
4355
		if (ctxt->mode != X86EMUL_MODE_PROT64)
A
Avi Kivity 已提交
4356
			goto cannot_emulate;
4357
		ctxt->dst.val = (s32) ctxt->src.val;
A
Avi Kivity 已提交
4358
		break;
4359
	case 0x70 ... 0x7f: /* jcc (short) */
4360 4361
		if (test_cc(ctxt->b, ctxt->eflags))
			jmp_rel(ctxt, ctxt->src.val);
4362
		break;
N
Nitin A Kamble 已提交
4363
	case 0x8d: /* lea r16/r32, m */
4364
		ctxt->dst.val = ctxt->src.addr.mem.ea;
N
Nitin A Kamble 已提交
4365
		break;
4366
	case 0x90 ... 0x97: /* nop / xchg reg, rax */
4367
		if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX])
4368
			break;
4369 4370
		rc = em_xchg(ctxt);
		break;
4371
	case 0x98: /* cbw/cwde/cdqe */
4372 4373 4374 4375
		switch (ctxt->op_bytes) {
		case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
		case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
		case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
4376 4377
		}
		break;
4378
	case 0xc0 ... 0xc1:
4379
		rc = em_grp2(ctxt);
4380
		break;
4381
	case 0xcc:		/* int3 */
4382 4383
		rc = emulate_int(ctxt, 3);
		break;
4384
	case 0xcd:		/* int n */
4385
		rc = emulate_int(ctxt, ctxt->src.val);
4386 4387
		break;
	case 0xce:		/* into */
4388 4389
		if (ctxt->eflags & EFLG_OF)
			rc = emulate_int(ctxt, 4);
4390
		break;
4391
	case 0xd0 ... 0xd1:	/* Grp2 */
4392
		rc = em_grp2(ctxt);
4393 4394
		break;
	case 0xd2 ... 0xd3:	/* Grp2 */
4395
		ctxt->src.val = ctxt->regs[VCPU_REGS_RCX];
4396
		rc = em_grp2(ctxt);
4397
		break;
4398
	case 0xe9: /* jmp rel */
4399
	case 0xeb: /* jmp rel short */
4400 4401
		jmp_rel(ctxt, ctxt->src.val);
		ctxt->dst.type = OP_NONE; /* Disable writeback. */
4402
		break;
4403
	case 0xf4:              /* hlt */
4404
		ctxt->ops->halt(ctxt);
4405
		break;
4406 4407 4408 4409 4410 4411 4412
	case 0xf5:	/* cmc */
		/* complement carry flag from eflags reg */
		ctxt->eflags ^= EFLG_CF;
		break;
	case 0xf8: /* clc */
		ctxt->eflags &= ~EFLG_CF;
		break;
4413 4414 4415
	case 0xf9: /* stc */
		ctxt->eflags |= EFLG_CF;
		break;
4416 4417 4418 4419 4420 4421
	case 0xfc: /* cld */
		ctxt->eflags &= ~EFLG_DF;
		break;
	case 0xfd: /* std */
		ctxt->eflags |= EFLG_DF;
		break;
4422 4423
	default:
		goto cannot_emulate;
A
Avi Kivity 已提交
4424
	}
4425

4426 4427 4428
	if (rc != X86EMUL_CONTINUE)
		goto done;

4429
writeback:
4430
	rc = writeback(ctxt);
4431
	if (rc != X86EMUL_CONTINUE)
4432 4433
		goto done;

4434 4435 4436 4437
	/*
	 * restore dst type in case the decoding will be reused
	 * (happens for string instruction )
	 */
4438
	ctxt->dst.type = saved_dst_type;
4439

4440 4441 4442
	if ((ctxt->d & SrcMask) == SrcSI)
		string_addr_inc(ctxt, seg_override(ctxt),
				VCPU_REGS_RSI, &ctxt->src);
4443

4444
	if ((ctxt->d & DstMask) == DstDI)
4445
		string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
4446
				&ctxt->dst);
4447

4448 4449 4450
	if (ctxt->rep_prefix && (ctxt->d & String)) {
		struct read_cache *r = &ctxt->io_read;
		register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
4451

4452 4453 4454 4455 4456
		if (!string_insn_completed(ctxt)) {
			/*
			 * Re-enter guest when pio read ahead buffer is empty
			 * or, if it is not used, after each 1024 iteration.
			 */
4457
			if ((r->end != 0 || ctxt->regs[VCPU_REGS_RCX] & 0x3ff) &&
4458 4459 4460 4461 4462 4463
			    (r->end == 0 || r->end != r->pos)) {
				/*
				 * Reset read cache. Usually happens before
				 * decode, but since instruction is restarted
				 * we have to do it here.
				 */
4464
				ctxt->mem_read.end = 0;
4465 4466 4467
				return EMULATION_RESTART;
			}
			goto done; /* skip rip writeback */
4468
		}
4469
	}
4470

4471
	ctxt->eip = ctxt->_eip;
4472 4473

done:
4474 4475
	if (rc == X86EMUL_PROPAGATE_FAULT)
		ctxt->have_exception = true;
4476 4477 4478
	if (rc == X86EMUL_INTERCEPTED)
		return EMULATION_INTERCEPTED;

4479
	return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
A
Avi Kivity 已提交
4480 4481

twobyte_insn:
4482
	switch (ctxt->b) {
4483
	case 0x09:		/* wbinvd */
4484
		(ctxt->ops->wbinvd)(ctxt);
4485 4486
		break;
	case 0x08:		/* invd */
4487 4488 4489 4490
	case 0x0d:		/* GrpP (prefetch) */
	case 0x18:		/* Grp16 (prefetch/nop) */
		break;
	case 0x20: /* mov cr, reg */
4491
		ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
4492
		break;
A
Avi Kivity 已提交
4493
	case 0x21: /* mov from dr to reg */
4494
		ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
A
Avi Kivity 已提交
4495 4496
		break;
	case 0x40 ... 0x4f:	/* cmov */
4497 4498 4499
		ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
		if (!test_cc(ctxt->b, ctxt->eflags))
			ctxt->dst.type = OP_NONE; /* no writeback */
A
Avi Kivity 已提交
4500
		break;
4501
	case 0x80 ... 0x8f: /* jnz rel, etc*/
4502 4503
		if (test_cc(ctxt->b, ctxt->eflags))
			jmp_rel(ctxt, ctxt->src.val);
4504
		break;
4505
	case 0x90 ... 0x9f:     /* setcc r/m8 */
4506
		ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
4507
		break;
4508 4509
	case 0xa4: /* shld imm8, r, r/m */
	case 0xa5: /* shld cl, r, r/m */
4510
		emulate_2op_cl(ctxt, "shld");
4511 4512 4513
		break;
	case 0xac: /* shrd imm8, r, r/m */
	case 0xad: /* shrd cl, r, r/m */
4514
		emulate_2op_cl(ctxt, "shrd");
4515
		break;
4516 4517
	case 0xae:              /* clflush */
		break;
A
Avi Kivity 已提交
4518
	case 0xb6 ... 0xb7:	/* movzx */
4519
		ctxt->dst.bytes = ctxt->op_bytes;
4520
		ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
4521
						       : (u16) ctxt->src.val;
A
Avi Kivity 已提交
4522 4523
		break;
	case 0xbe ... 0xbf:	/* movsx */
4524
		ctxt->dst.bytes = ctxt->op_bytes;
4525
		ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
4526
							(s16) ctxt->src.val;
A
Avi Kivity 已提交
4527
		break;
4528
	case 0xc0 ... 0xc1:	/* xadd */
4529
		emulate_2op_SrcV(ctxt, "add");
4530
		/* Write back the register source. */
4531 4532
		ctxt->src.val = ctxt->dst.orig_val;
		write_register_operand(&ctxt->src);
4533
		break;
4534
	case 0xc3:		/* movnti */
4535 4536 4537
		ctxt->dst.bytes = ctxt->op_bytes;
		ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
							(u64) ctxt->src.val;
4538
		break;
4539 4540
	default:
		goto cannot_emulate;
A
Avi Kivity 已提交
4541
	}
4542 4543 4544 4545

	if (rc != X86EMUL_CONTINUE)
		goto done;

A
Avi Kivity 已提交
4546 4547 4548
	goto writeback;

cannot_emulate:
4549
	return EMULATION_FAILED;
A
Avi Kivity 已提交
4550
}