emulate.c 129.7 KB
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/******************************************************************************
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 * emulate.c
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 *
 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
 *
 * Copyright (c) 2005 Keir Fraser
 *
 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
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 * privileged instructions:
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 *
 * Copyright (C) 2006 Qumranet
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 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
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 *
 *   Avi Kivity <avi@qumranet.com>
 *   Yaniv Kamay <yaniv@qumranet.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
 */

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#include <linux/kvm_host.h>
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#include "kvm_cache_regs.h"
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#include <linux/module.h>
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#include <asm/kvm_emulate.h>
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#include <linux/stringify.h>
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#include "x86.h"
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#include "tss.h"
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/*
 * Operand types
 */
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#define OpNone             0ull
#define OpImplicit         1ull  /* No generic decode */
#define OpReg              2ull  /* Register */
#define OpMem              3ull  /* Memory */
#define OpAcc              4ull  /* Accumulator: AL/AX/EAX/RAX */
#define OpDI               5ull  /* ES:DI/EDI/RDI */
#define OpMem64            6ull  /* Memory, 64-bit */
#define OpImmUByte         7ull  /* Zero-extended 8-bit immediate */
#define OpDX               8ull  /* DX register */
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#define OpCL               9ull  /* CL register (for shifts) */
#define OpImmByte         10ull  /* 8-bit sign extended immediate */
#define OpOne             11ull  /* Implied 1 */
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#define OpImm             12ull  /* Sign extended up to 32-bit immediate */
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#define OpMem16           13ull  /* Memory operand (16-bit). */
#define OpMem32           14ull  /* Memory operand (32-bit). */
#define OpImmU            15ull  /* Immediate operand, zero extended */
#define OpSI              16ull  /* SI/ESI/RSI */
#define OpImmFAddr        17ull  /* Immediate far address */
#define OpMemFAddr        18ull  /* Far address in memory */
#define OpImmU16          19ull  /* Immediate operand, 16 bits, zero extended */
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#define OpES              20ull  /* ES */
#define OpCS              21ull  /* CS */
#define OpSS              22ull  /* SS */
#define OpDS              23ull  /* DS */
#define OpFS              24ull  /* FS */
#define OpGS              25ull  /* GS */
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#define OpMem8            26ull  /* 8-bit zero extended memory operand */
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#define OpImm64           27ull  /* Sign extended 16/32/64-bit immediate */
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#define OpXLat            28ull  /* memory at BX/EBX/RBX + zero-extended AL */
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#define OpAccLo           29ull  /* Low part of extended acc (AX/AX/EAX/RAX) */
#define OpAccHi           30ull  /* High part of extended acc (-/DX/EDX/RDX) */
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#define OpBits             5  /* Width of operand field */
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#define OpMask             ((1ull << OpBits) - 1)
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/*
 * Opcode effective-address decode tables.
 * Note that we only emulate instructions that have at least one memory
 * operand (excluding implicit stack references). We assume that stack
 * references and instruction fetches will never occur in special memory
 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
 * not be handled.
 */

/* Operand sizes: 8-bit operands or specified/overridden size. */
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#define ByteOp      (1<<0)	/* 8-bit operands. */
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/* Destination operand type. */
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#define DstShift    1
#define ImplicitOps (OpImplicit << DstShift)
#define DstReg      (OpReg << DstShift)
#define DstMem      (OpMem << DstShift)
#define DstAcc      (OpAcc << DstShift)
#define DstDI       (OpDI << DstShift)
#define DstMem64    (OpMem64 << DstShift)
#define DstImmUByte (OpImmUByte << DstShift)
#define DstDX       (OpDX << DstShift)
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#define DstAccLo    (OpAccLo << DstShift)
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#define DstMask     (OpMask << DstShift)
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/* Source operand type. */
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#define SrcShift    6
#define SrcNone     (OpNone << SrcShift)
#define SrcReg      (OpReg << SrcShift)
#define SrcMem      (OpMem << SrcShift)
#define SrcMem16    (OpMem16 << SrcShift)
#define SrcMem32    (OpMem32 << SrcShift)
#define SrcImm      (OpImm << SrcShift)
#define SrcImmByte  (OpImmByte << SrcShift)
#define SrcOne      (OpOne << SrcShift)
#define SrcImmUByte (OpImmUByte << SrcShift)
#define SrcImmU     (OpImmU << SrcShift)
#define SrcSI       (OpSI << SrcShift)
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#define SrcXLat     (OpXLat << SrcShift)
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#define SrcImmFAddr (OpImmFAddr << SrcShift)
#define SrcMemFAddr (OpMemFAddr << SrcShift)
#define SrcAcc      (OpAcc << SrcShift)
#define SrcImmU16   (OpImmU16 << SrcShift)
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#define SrcImm64    (OpImm64 << SrcShift)
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#define SrcDX       (OpDX << SrcShift)
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#define SrcMem8     (OpMem8 << SrcShift)
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#define SrcAccHi    (OpAccHi << SrcShift)
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#define SrcMask     (OpMask << SrcShift)
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#define BitOp       (1<<11)
#define MemAbs      (1<<12)      /* Memory operand is absolute displacement */
#define String      (1<<13)     /* String instruction (rep capable) */
#define Stack       (1<<14)     /* Stack instruction (push/pop) */
#define GroupMask   (7<<15)     /* Opcode uses one of the group mechanisms */
#define Group       (1<<15)     /* Bits 3:5 of modrm byte extend opcode */
#define GroupDual   (2<<15)     /* Alternate decoding of mod == 3 */
#define Prefix      (3<<15)     /* Instruction varies with 66/f2/f3 prefix */
#define RMExt       (4<<15)     /* Opcode extension in ModRM r/m if mod == 3 */
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#define Escape      (5<<15)     /* Escape to coprocessor instruction */
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#define Sse         (1<<18)     /* SSE Vector instruction */
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/* Generic ModRM decode. */
#define ModRM       (1<<19)
/* Destination is only written; never read. */
#define Mov         (1<<20)
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/* Misc flags */
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#define Prot        (1<<21) /* instruction generates #UD if not in prot-mode */
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#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
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#define NoAccess    (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
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#define Op3264      (1<<24) /* Operand is 64b in long mode, 32b otherwise */
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#define Undefined   (1<<25) /* No Such Instruction */
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#define Lock        (1<<26) /* lock prefix is allowed for the instruction */
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#define Priv        (1<<27) /* instruction generates #GP if current CPL != 0 */
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#define No64	    (1<<28)
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#define PageTable   (1 << 29)   /* instruction used to write page table */
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#define NotImpl     (1 << 30)   /* instruction is not implemented */
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/* Source 2 operand type */
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#define Src2Shift   (31)
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#define Src2None    (OpNone << Src2Shift)
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#define Src2Mem     (OpMem << Src2Shift)
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#define Src2CL      (OpCL << Src2Shift)
#define Src2ImmByte (OpImmByte << Src2Shift)
#define Src2One     (OpOne << Src2Shift)
#define Src2Imm     (OpImm << Src2Shift)
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#define Src2ES      (OpES << Src2Shift)
#define Src2CS      (OpCS << Src2Shift)
#define Src2SS      (OpSS << Src2Shift)
#define Src2DS      (OpDS << Src2Shift)
#define Src2FS      (OpFS << Src2Shift)
#define Src2GS      (OpGS << Src2Shift)
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#define Src2Mask    (OpMask << Src2Shift)
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#define Mmx         ((u64)1 << 40)  /* MMX Vector instruction */
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#define Aligned     ((u64)1 << 41)  /* Explicitly aligned (e.g. MOVDQA) */
#define Unaligned   ((u64)1 << 42)  /* Explicitly unaligned (e.g. MOVDQU) */
#define Avx         ((u64)1 << 43)  /* Advanced Vector Extensions */
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#define Fastop      ((u64)1 << 44)  /* Use opcode::u.fastop */
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#define NoWrite     ((u64)1 << 45)  /* No writeback */
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#define SrcWrite    ((u64)1 << 46)  /* Write back src operand */
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#define NoMod	    ((u64)1 << 47)  /* Mod field is ignored */
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#define Intercept   ((u64)1 << 48)  /* Has valid intercept field */
#define CheckPerm   ((u64)1 << 49)  /* Has valid check_perm field */
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#define NoBigReal   ((u64)1 << 50)  /* No big real mode */
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#define PrivUD      ((u64)1 << 51)  /* #UD instead of #GP on CPL > 0 */
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#define NearBranch  ((u64)1 << 52)  /* Near branches */
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#define DstXacc     (DstAccLo | SrcAccHi | SrcWrite)
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#define X2(x...) x, x
#define X3(x...) X2(x), x
#define X4(x...) X2(x), X2(x)
#define X5(x...) X4(x), x
#define X6(x...) X4(x), X2(x)
#define X7(x...) X4(x), X3(x)
#define X8(x...) X4(x), X4(x)
#define X16(x...) X8(x), X8(x)
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#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
#define FASTOP_SIZE 8

/*
 * fastop functions have a special calling convention:
 *
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 * dst:    rax        (in/out)
 * src:    rdx        (in/out)
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 * src2:   rcx        (in)
 * flags:  rflags     (in/out)
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 * ex:     rsi        (in:fastop pointer, out:zero if exception)
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 *
 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
 * different operand sizes can be reached by calculation, rather than a jump
 * table (which would be bigger than the code).
 *
 * fastop functions are declared as taking a never-defined fastop parameter,
 * so they can't be called from C directly.
 */

struct fastop;

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struct opcode {
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	u64 flags : 56;
	u64 intercept : 8;
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	union {
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		int (*execute)(struct x86_emulate_ctxt *ctxt);
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		const struct opcode *group;
		const struct group_dual *gdual;
		const struct gprefix *gprefix;
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		const struct escape *esc;
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		void (*fastop)(struct fastop *fake);
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	} u;
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	int (*check_perm)(struct x86_emulate_ctxt *ctxt);
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};

struct group_dual {
	struct opcode mod012[8];
	struct opcode mod3[8];
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};

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struct gprefix {
	struct opcode pfx_no;
	struct opcode pfx_66;
	struct opcode pfx_f2;
	struct opcode pfx_f3;
};

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struct escape {
	struct opcode op[8];
	struct opcode high[64];
};

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/* EFLAGS bit definitions. */
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#define EFLG_ID (1<<21)
#define EFLG_VIP (1<<20)
#define EFLG_VIF (1<<19)
#define EFLG_AC (1<<18)
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#define EFLG_VM (1<<17)
#define EFLG_RF (1<<16)
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#define EFLG_IOPL (3<<12)
#define EFLG_NT (1<<14)
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#define EFLG_OF (1<<11)
#define EFLG_DF (1<<10)
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#define EFLG_IF (1<<9)
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#define EFLG_TF (1<<8)
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#define EFLG_SF (1<<7)
#define EFLG_ZF (1<<6)
#define EFLG_AF (1<<4)
#define EFLG_PF (1<<2)
#define EFLG_CF (1<<0)

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#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
#define EFLG_RESERVED_ONE_MASK 2

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static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
{
	if (!(ctxt->regs_valid & (1 << nr))) {
		ctxt->regs_valid |= 1 << nr;
		ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
	}
	return ctxt->_regs[nr];
}

static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
{
	ctxt->regs_valid |= 1 << nr;
	ctxt->regs_dirty |= 1 << nr;
	return &ctxt->_regs[nr];
}

static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
{
	reg_read(ctxt, nr);
	return reg_write(ctxt, nr);
}

static void writeback_registers(struct x86_emulate_ctxt *ctxt)
{
	unsigned reg;

	for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
		ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
}

static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
{
	ctxt->regs_dirty = 0;
	ctxt->regs_valid = 0;
}

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/*
 * These EFLAGS bits are restored from saved value during emulation, and
 * any changes are written back to the saved value after emulation.
 */
#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)

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#ifdef CONFIG_X86_64
#define ON64(x) x
#else
#define ON64(x)
#endif

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static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));

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#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
#define FOP_RET   "ret \n\t"

#define FOP_START(op) \
	extern void em_##op(struct fastop *fake); \
	asm(".pushsection .text, \"ax\" \n\t" \
	    ".global em_" #op " \n\t" \
            FOP_ALIGN \
	    "em_" #op ": \n\t"

#define FOP_END \
	    ".popsection")

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#define FOPNOP() FOP_ALIGN FOP_RET

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#define FOP1E(op,  dst) \
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	FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET

#define FOP1EEX(op,  dst) \
	FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
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#define FASTOP1(op) \
	FOP_START(op) \
	FOP1E(op##b, al) \
	FOP1E(op##w, ax) \
	FOP1E(op##l, eax) \
	ON64(FOP1E(op##q, rax))	\
	FOP_END

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/* 1-operand, using src2 (for MUL/DIV r/m) */
#define FASTOP1SRC2(op, name) \
	FOP_START(name) \
	FOP1E(op, cl) \
	FOP1E(op, cx) \
	FOP1E(op, ecx) \
	ON64(FOP1E(op, rcx)) \
	FOP_END

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/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
#define FASTOP1SRC2EX(op, name) \
	FOP_START(name) \
	FOP1EEX(op, cl) \
	FOP1EEX(op, cx) \
	FOP1EEX(op, ecx) \
	ON64(FOP1EEX(op, rcx)) \
	FOP_END

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#define FOP2E(op,  dst, src)	   \
	FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET

#define FASTOP2(op) \
	FOP_START(op) \
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	FOP2E(op##b, al, dl) \
	FOP2E(op##w, ax, dx) \
	FOP2E(op##l, eax, edx) \
	ON64(FOP2E(op##q, rax, rdx)) \
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	FOP_END

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/* 2 operand, word only */
#define FASTOP2W(op) \
	FOP_START(op) \
	FOPNOP() \
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	FOP2E(op##w, ax, dx) \
	FOP2E(op##l, eax, edx) \
	ON64(FOP2E(op##q, rax, rdx)) \
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	FOP_END

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/* 2 operand, src is CL */
#define FASTOP2CL(op) \
	FOP_START(op) \
	FOP2E(op##b, al, cl) \
	FOP2E(op##w, ax, cl) \
	FOP2E(op##l, eax, cl) \
	ON64(FOP2E(op##q, rax, cl)) \
	FOP_END

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#define FOP3E(op,  dst, src, src2) \
	FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET

/* 3-operand, word-only, src2=cl */
#define FASTOP3WCL(op) \
	FOP_START(op) \
	FOPNOP() \
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	FOP3E(op##w, ax, dx, cl) \
	FOP3E(op##l, eax, edx, cl) \
	ON64(FOP3E(op##q, rax, rdx, cl)) \
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	FOP_END

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/* Special case for SETcc - 1 instruction per cc */
#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"

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asm(".global kvm_fastop_exception \n"
    "kvm_fastop_exception: xor %esi, %esi; ret");

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FOP_START(setcc)
FOP_SETCC(seto)
FOP_SETCC(setno)
FOP_SETCC(setc)
FOP_SETCC(setnc)
FOP_SETCC(setz)
FOP_SETCC(setnz)
FOP_SETCC(setbe)
FOP_SETCC(setnbe)
FOP_SETCC(sets)
FOP_SETCC(setns)
FOP_SETCC(setp)
FOP_SETCC(setnp)
FOP_SETCC(setl)
FOP_SETCC(setnl)
FOP_SETCC(setle)
FOP_SETCC(setnle)
FOP_END;

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FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
FOP_END;

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static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
				    enum x86_intercept intercept,
				    enum x86_intercept_stage stage)
{
	struct x86_instruction_info info = {
		.intercept  = intercept,
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		.rep_prefix = ctxt->rep_prefix,
		.modrm_mod  = ctxt->modrm_mod,
		.modrm_reg  = ctxt->modrm_reg,
		.modrm_rm   = ctxt->modrm_rm,
		.src_val    = ctxt->src.val64,
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		.dst_val    = ctxt->dst.val64,
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		.src_bytes  = ctxt->src.bytes,
		.dst_bytes  = ctxt->dst.bytes,
		.ad_bytes   = ctxt->ad_bytes,
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		.next_rip   = ctxt->eip,
	};

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	return ctxt->ops->intercept(ctxt, &info, stage);
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}

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static void assign_masked(ulong *dest, ulong src, ulong mask)
{
	*dest = (*dest & ~mask) | (src & mask);
}

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static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
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{
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	return (1UL << (ctxt->ad_bytes << 3)) - 1;
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}

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static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
{
	u16 sel;
	struct desc_struct ss;

	if (ctxt->mode == X86EMUL_MODE_PROT64)
		return ~0UL;
	ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
	return ~0U >> ((ss.d ^ 1) * 16);  /* d=0: 0xffff; d=1: 0xffffffff */
}

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static int stack_size(struct x86_emulate_ctxt *ctxt)
{
	return (__fls(stack_mask(ctxt)) + 1) >> 3;
}

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/* Access/update address held in a register, based on addressing mode. */
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static inline unsigned long
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address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
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{
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	if (ctxt->ad_bytes == sizeof(unsigned long))
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		return reg;
	else
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		return reg & ad_mask(ctxt);
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}

static inline unsigned long
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register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
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{
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	return address_mask(ctxt, reg);
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}

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static void masked_increment(ulong *reg, ulong mask, int inc)
{
	assign_masked(reg, *reg + inc, mask);
}

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static inline void
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register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
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{
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	ulong mask;

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	if (ctxt->ad_bytes == sizeof(unsigned long))
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		mask = ~0UL;
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	else
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		mask = ad_mask(ctxt);
	masked_increment(reg, mask, inc);
}

static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
{
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	masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
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}
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static u32 desc_limit_scaled(struct desc_struct *desc)
{
	u32 limit = get_desc_limit(desc);

	return desc->g ? (limit << 12) | 0xfff : limit;
}

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static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
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{
	if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
		return 0;

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	return ctxt->ops->get_cached_segment_base(ctxt, seg);
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}

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static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
			     u32 error, bool valid)
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{
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	WARN_ON(vec > 0x1f);
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	ctxt->exception.vector = vec;
	ctxt->exception.error_code = error;
	ctxt->exception.error_code_valid = valid;
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	return X86EMUL_PROPAGATE_FAULT;
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}

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static int emulate_db(struct x86_emulate_ctxt *ctxt)
{
	return emulate_exception(ctxt, DB_VECTOR, 0, false);
}

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static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
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{
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	return emulate_exception(ctxt, GP_VECTOR, err, true);
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}

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static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
{
	return emulate_exception(ctxt, SS_VECTOR, err, true);
}

548
static int emulate_ud(struct x86_emulate_ctxt *ctxt)
549
{
550
	return emulate_exception(ctxt, UD_VECTOR, 0, false);
551 552
}

553
static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
554
{
555
	return emulate_exception(ctxt, TS_VECTOR, err, true);
556 557
}

558 559
static int emulate_de(struct x86_emulate_ctxt *ctxt)
{
560
	return emulate_exception(ctxt, DE_VECTOR, 0, false);
561 562
}

A
Avi Kivity 已提交
563 564 565 566 567
static int emulate_nm(struct x86_emulate_ctxt *ctxt)
{
	return emulate_exception(ctxt, NM_VECTOR, 0, false);
}

568 569
static inline int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
			       int cs_l)
570 571 572 573 574 575 576 577
{
	switch (ctxt->op_bytes) {
	case 2:
		ctxt->_eip = (u16)dst;
		break;
	case 4:
		ctxt->_eip = (u32)dst;
		break;
578
#ifdef CONFIG_X86_64
579
	case 8:
580
		if ((cs_l && is_noncanonical_address(dst)) ||
581
		    (!cs_l && (dst >> 32) != 0))
582
			return emulate_gp(ctxt, 0);
583 584
		ctxt->_eip = dst;
		break;
585
#endif
586 587 588
	default:
		WARN(1, "unsupported eip assignment size\n");
	}
589 590 591 592 593 594
	return X86EMUL_CONTINUE;
}

static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
{
	return assign_eip_far(ctxt, dst, ctxt->mode == X86EMUL_MODE_PROT64);
595 596
}

597
static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
598
{
599
	return assign_eip_near(ctxt, ctxt->_eip + rel);
600 601
}

602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621
static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
{
	u16 selector;
	struct desc_struct desc;

	ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
	return selector;
}

static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
				 unsigned seg)
{
	u16 dummy;
	u32 base3;
	struct desc_struct desc;

	ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
	ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
}

622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644
/*
 * x86 defines three classes of vector instructions: explicitly
 * aligned, explicitly unaligned, and the rest, which change behaviour
 * depending on whether they're AVX encoded or not.
 *
 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
 * subject to the same check.
 */
static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
{
	if (likely(size < 16))
		return false;

	if (ctxt->d & Aligned)
		return true;
	else if (ctxt->d & Unaligned)
		return false;
	else if (ctxt->d & Avx)
		return false;
	else
		return true;
}

645 646 647 648 649
static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
				       struct segmented_address addr,
				       unsigned *max_size, unsigned size,
				       bool write, bool fetch,
				       ulong *linear)
650
{
651 652
	struct desc_struct desc;
	bool usable;
653
	ulong la;
654
	u32 lim;
655
	u16 sel;
656
	unsigned cpl;
657

658
	la = seg_base(ctxt, addr.seg) + addr.ea;
659
	*max_size = 0;
660 661
	switch (ctxt->mode) {
	case X86EMUL_MODE_PROT64:
662
		if (is_noncanonical_address(la))
663
			return emulate_gp(ctxt, 0);
664 665 666 667

		*max_size = min_t(u64, ~0u, (1ull << 48) - la);
		if (size > *max_size)
			goto bad;
668 669
		break;
	default:
670 671
		usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
						addr.seg);
672 673
		if (!usable)
			goto bad;
674 675 676
		/* code segment in protected mode or read-only data segment */
		if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
					|| !(desc.type & 2)) && write)
677 678
			goto bad;
		/* unreadable code segment */
679
		if (!fetch && (desc.type & 8) && !(desc.type & 2))
680 681
			goto bad;
		lim = desc_limit_scaled(&desc);
682 683 684
		if ((ctxt->mode == X86EMUL_MODE_REAL) && !fetch &&
		    (ctxt->d & NoBigReal)) {
			/* la is between zero and 0xffff */
685
			if (la > 0xffff)
686
				goto bad;
687
			*max_size = 0x10000 - la;
688
		} else if ((desc.type & 8) || !(desc.type & 4)) {
689
			/* expand-up segment */
690
			if (addr.ea > lim)
691
				goto bad;
692
			*max_size = min_t(u64, ~0u, (u64)lim + 1 - addr.ea);
693
		} else {
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694
			/* expand-down segment */
695
			if (addr.ea <= lim)
696 697
				goto bad;
			lim = desc.d ? 0xffffffff : 0xffff;
698
			if (addr.ea > lim)
699
				goto bad;
700
			*max_size = min_t(u64, ~0u, (u64)lim + 1 - addr.ea);
701
		}
702 703
		if (size > *max_size)
			goto bad;
704
		cpl = ctxt->ops->cpl(ctxt);
705 706 707 708 709 710 711 712 713 714 715 716 717 718 719
		if (!(desc.type & 8)) {
			/* data segment */
			if (cpl > desc.dpl)
				goto bad;
		} else if ((desc.type & 8) && !(desc.type & 4)) {
			/* nonconforming code segment */
			if (cpl != desc.dpl)
				goto bad;
		} else if ((desc.type & 8) && (desc.type & 4)) {
			/* conforming code segment */
			if (cpl < desc.dpl)
				goto bad;
		}
		break;
	}
720
	if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
721
		la &= (u32)-1;
722 723
	if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
		return emulate_gp(ctxt, 0);
724 725
	*linear = la;
	return X86EMUL_CONTINUE;
726 727
bad:
	if (addr.seg == VCPU_SREG_SS)
728
		return emulate_ss(ctxt, 0);
729
	else
730
		return emulate_gp(ctxt, 0);
731 732
}

733 734 735 736 737
static int linearize(struct x86_emulate_ctxt *ctxt,
		     struct segmented_address addr,
		     unsigned size, bool write,
		     ulong *linear)
{
738 739
	unsigned max_size;
	return __linearize(ctxt, addr, &max_size, size, write, false, linear);
740 741 742
}


743 744 745 746 747
static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
			      struct segmented_address addr,
			      void *data,
			      unsigned size)
{
748 749 750
	int rc;
	ulong linear;

751
	rc = linearize(ctxt, addr, size, false, &linear);
752 753
	if (rc != X86EMUL_CONTINUE)
		return rc;
754
	return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
755 756
}

757
/*
758
 * Prefetch the remaining bytes of the instruction without crossing page
759 760
 * boundary if they are not in fetch_cache yet.
 */
761
static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
762 763
{
	int rc;
764
	unsigned size, max_size;
765
	unsigned long linear;
766
	int cur_size = ctxt->fetch.end - ctxt->fetch.data;
767
	struct segmented_address addr = { .seg = VCPU_SREG_CS,
768 769
					   .ea = ctxt->eip + cur_size };

770 771 772 773 774 775 776 777 778 779 780
	/*
	 * We do not know exactly how many bytes will be needed, and
	 * __linearize is expensive, so fetch as much as possible.  We
	 * just have to avoid going beyond the 15 byte limit, the end
	 * of the segment, or the end of the page.
	 *
	 * __linearize is called with size 0 so that it does not do any
	 * boundary check itself.  Instead, we use max_size to check
	 * against op_size.
	 */
	rc = __linearize(ctxt, addr, &max_size, 0, false, true, &linear);
781 782 783
	if (unlikely(rc != X86EMUL_CONTINUE))
		return rc;

784
	size = min_t(unsigned, 15UL ^ cur_size, max_size);
785
	size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
786 787 788 789 790 791 792 793

	/*
	 * One instruction can only straddle two pages,
	 * and one has been loaded at the beginning of
	 * x86_decode_insn.  So, if not enough bytes
	 * still, we must have hit the 15-byte boundary.
	 */
	if (unlikely(size < op_size))
794 795
		return emulate_gp(ctxt, 0);

796
	rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
797 798 799
			      size, &ctxt->exception);
	if (unlikely(rc != X86EMUL_CONTINUE))
		return rc;
800
	ctxt->fetch.end += size;
801
	return X86EMUL_CONTINUE;
802 803
}

804 805
static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
					       unsigned size)
806
{
807 808 809 810
	unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;

	if (unlikely(done_size < size))
		return __do_insn_fetch_bytes(ctxt, size - done_size);
811 812
	else
		return X86EMUL_CONTINUE;
813 814
}

815
/* Fetch next part of the instruction being emulated. */
816
#define insn_fetch(_type, _ctxt)					\
817 818 819
({	_type _x;							\
									\
	rc = do_insn_fetch_bytes(_ctxt, sizeof(_type));			\
820 821
	if (rc != X86EMUL_CONTINUE)					\
		goto done;						\
822
	ctxt->_eip += sizeof(_type);					\
823 824
	_x = *(_type __aligned(1) *) ctxt->fetch.ptr;			\
	ctxt->fetch.ptr += sizeof(_type);				\
825
	_x;								\
826 827
})

828
#define insn_fetch_arr(_arr, _size, _ctxt)				\
829 830
({									\
	rc = do_insn_fetch_bytes(_ctxt, _size);				\
831 832
	if (rc != X86EMUL_CONTINUE)					\
		goto done;						\
833
	ctxt->_eip += (_size);						\
834 835
	memcpy(_arr, ctxt->fetch.ptr, _size);				\
	ctxt->fetch.ptr += (_size);					\
836 837
})

838 839 840 841 842
/*
 * Given the 'reg' portion of a ModRM byte, and a register block, return a
 * pointer into the block that addresses the relevant register.
 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
 */
843
static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
844
			     int byteop)
A
Avi Kivity 已提交
845 846
{
	void *p;
847
	int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
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848 849

	if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
850 851 852
		p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
	else
		p = reg_rmw(ctxt, modrm_reg);
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853 854 855 856
	return p;
}

static int read_descriptor(struct x86_emulate_ctxt *ctxt,
857
			   struct segmented_address addr,
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858 859 860 861 862 863 864
			   u16 *size, unsigned long *address, int op_bytes)
{
	int rc;

	if (op_bytes == 2)
		op_bytes = 3;
	*address = 0;
865
	rc = segmented_read_std(ctxt, addr, size, 2);
866
	if (rc != X86EMUL_CONTINUE)
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Avi Kivity 已提交
867
		return rc;
868
	addr.ea += 2;
869
	rc = segmented_read_std(ctxt, addr, address, op_bytes);
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870 871 872
	return rc;
}

873 874 875 876 877 878 879 880 881 882
FASTOP2(add);
FASTOP2(or);
FASTOP2(adc);
FASTOP2(sbb);
FASTOP2(and);
FASTOP2(sub);
FASTOP2(xor);
FASTOP2(cmp);
FASTOP2(test);

883 884
FASTOP1SRC2(mul, mul_ex);
FASTOP1SRC2(imul, imul_ex);
885 886
FASTOP1SRC2EX(div, div_ex);
FASTOP1SRC2EX(idiv, idiv_ex);
887

888 889 890 891 892 893 894 895 896 897 898 899 900 901 902 903 904 905 906 907 908 909 910 911 912
FASTOP3WCL(shld);
FASTOP3WCL(shrd);

FASTOP2W(imul);

FASTOP1(not);
FASTOP1(neg);
FASTOP1(inc);
FASTOP1(dec);

FASTOP2CL(rol);
FASTOP2CL(ror);
FASTOP2CL(rcl);
FASTOP2CL(rcr);
FASTOP2CL(shl);
FASTOP2CL(shr);
FASTOP2CL(sar);

FASTOP2W(bsf);
FASTOP2W(bsr);
FASTOP2W(bt);
FASTOP2W(bts);
FASTOP2W(btr);
FASTOP2W(btc);

913 914
FASTOP2(xadd);

915
static u8 test_cc(unsigned int condition, unsigned long flags)
916
{
917 918
	u8 rc;
	void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
919

920
	flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
921
	asm("push %[flags]; popf; call *%[fastop]"
922 923
	    : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
	return rc;
924 925
}

926 927 928 929 930 931 932 933 934 935 936 937 938 939 940 941 942 943
static void fetch_register_operand(struct operand *op)
{
	switch (op->bytes) {
	case 1:
		op->val = *(u8 *)op->addr.reg;
		break;
	case 2:
		op->val = *(u16 *)op->addr.reg;
		break;
	case 4:
		op->val = *(u32 *)op->addr.reg;
		break;
	case 8:
		op->val = *(u64 *)op->addr.reg;
		break;
	}
}

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944 945 946 947
static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
{
	ctxt->ops->get_fpu(ctxt);
	switch (reg) {
948 949 950 951 952 953 954 955
	case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
	case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
	case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
	case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
	case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
	case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
	case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
	case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
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#ifdef CONFIG_X86_64
957 958 959 960 961 962 963 964
	case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
	case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
	case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
	case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
	case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
	case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
	case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
	case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
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#endif
	default: BUG();
	}
	ctxt->ops->put_fpu(ctxt);
}

static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
			  int reg)
{
	ctxt->ops->get_fpu(ctxt);
	switch (reg) {
976 977 978 979 980 981 982 983
	case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
	case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
	case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
	case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
	case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
	case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
	case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
	case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
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984
#ifdef CONFIG_X86_64
985 986 987 988 989 990 991 992
	case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
	case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
	case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
	case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
	case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
	case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
	case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
	case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
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#endif
	default: BUG();
	}
	ctxt->ops->put_fpu(ctxt);
}

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999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032
static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
{
	ctxt->ops->get_fpu(ctxt);
	switch (reg) {
	case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
	case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
	case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
	case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
	case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
	case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
	case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
	case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
	default: BUG();
	}
	ctxt->ops->put_fpu(ctxt);
}

static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
{
	ctxt->ops->get_fpu(ctxt);
	switch (reg) {
	case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
	case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
	case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
	case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
	case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
	case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
	case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
	case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
	default: BUG();
	}
	ctxt->ops->put_fpu(ctxt);
}

1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079
static int em_fninit(struct x86_emulate_ctxt *ctxt)
{
	if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
		return emulate_nm(ctxt);

	ctxt->ops->get_fpu(ctxt);
	asm volatile("fninit");
	ctxt->ops->put_fpu(ctxt);
	return X86EMUL_CONTINUE;
}

static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
{
	u16 fcw;

	if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
		return emulate_nm(ctxt);

	ctxt->ops->get_fpu(ctxt);
	asm volatile("fnstcw %0": "+m"(fcw));
	ctxt->ops->put_fpu(ctxt);

	/* force 2 byte destination */
	ctxt->dst.bytes = 2;
	ctxt->dst.val = fcw;

	return X86EMUL_CONTINUE;
}

static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
{
	u16 fsw;

	if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
		return emulate_nm(ctxt);

	ctxt->ops->get_fpu(ctxt);
	asm volatile("fnstsw %0": "+m"(fsw));
	ctxt->ops->put_fpu(ctxt);

	/* force 2 byte destination */
	ctxt->dst.bytes = 2;
	ctxt->dst.val = fsw;

	return X86EMUL_CONTINUE;
}

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1080
static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
1081
				    struct operand *op)
1082
{
1083
	unsigned reg = ctxt->modrm_reg;
1084

1085 1086
	if (!(ctxt->d & ModRM))
		reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
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1087

1088
	if (ctxt->d & Sse) {
A
Avi Kivity 已提交
1089 1090 1091 1092 1093 1094
		op->type = OP_XMM;
		op->bytes = 16;
		op->addr.xmm = reg;
		read_sse_reg(ctxt, &op->vec_val, reg);
		return;
	}
A
Avi Kivity 已提交
1095 1096 1097 1098 1099 1100 1101
	if (ctxt->d & Mmx) {
		reg &= 7;
		op->type = OP_MM;
		op->bytes = 8;
		op->addr.mm = reg;
		return;
	}
A
Avi Kivity 已提交
1102

1103
	op->type = OP_REG;
1104 1105 1106
	op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
	op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);

1107
	fetch_register_operand(op);
1108 1109 1110
	op->orig_val = op->val;
}

1111 1112 1113 1114 1115 1116
static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
{
	if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
		ctxt->modrm_seg = VCPU_SREG_SS;
}

1117
static int decode_modrm(struct x86_emulate_ctxt *ctxt,
1118
			struct operand *op)
1119 1120
{
	u8 sib;
B
Bandan Das 已提交
1121
	int index_reg, base_reg, scale;
1122
	int rc = X86EMUL_CONTINUE;
1123
	ulong modrm_ea = 0;
1124

B
Bandan Das 已提交
1125 1126 1127
	ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
	index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
	base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1128

B
Bandan Das 已提交
1129
	ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
1130
	ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
B
Bandan Das 已提交
1131
	ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
1132
	ctxt->modrm_seg = VCPU_SREG_DS;
1133

1134
	if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
1135
		op->type = OP_REG;
1136
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1137
		op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
1138
				ctxt->d & ByteOp);
1139
		if (ctxt->d & Sse) {
A
Avi Kivity 已提交
1140 1141
			op->type = OP_XMM;
			op->bytes = 16;
1142 1143
			op->addr.xmm = ctxt->modrm_rm;
			read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
A
Avi Kivity 已提交
1144 1145
			return rc;
		}
A
Avi Kivity 已提交
1146 1147 1148
		if (ctxt->d & Mmx) {
			op->type = OP_MM;
			op->bytes = 8;
1149
			op->addr.mm = ctxt->modrm_rm & 7;
A
Avi Kivity 已提交
1150 1151
			return rc;
		}
1152
		fetch_register_operand(op);
1153 1154 1155
		return rc;
	}

1156 1157
	op->type = OP_MEM;

1158
	if (ctxt->ad_bytes == 2) {
1159 1160 1161 1162
		unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
		unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
		unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
		unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1163 1164

		/* 16-bit ModR/M decode. */
1165
		switch (ctxt->modrm_mod) {
1166
		case 0:
1167
			if (ctxt->modrm_rm == 6)
1168
				modrm_ea += insn_fetch(u16, ctxt);
1169 1170
			break;
		case 1:
1171
			modrm_ea += insn_fetch(s8, ctxt);
1172 1173
			break;
		case 2:
1174
			modrm_ea += insn_fetch(u16, ctxt);
1175 1176
			break;
		}
1177
		switch (ctxt->modrm_rm) {
1178
		case 0:
1179
			modrm_ea += bx + si;
1180 1181
			break;
		case 1:
1182
			modrm_ea += bx + di;
1183 1184
			break;
		case 2:
1185
			modrm_ea += bp + si;
1186 1187
			break;
		case 3:
1188
			modrm_ea += bp + di;
1189 1190
			break;
		case 4:
1191
			modrm_ea += si;
1192 1193
			break;
		case 5:
1194
			modrm_ea += di;
1195 1196
			break;
		case 6:
1197
			if (ctxt->modrm_mod != 0)
1198
				modrm_ea += bp;
1199 1200
			break;
		case 7:
1201
			modrm_ea += bx;
1202 1203
			break;
		}
1204 1205 1206
		if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
		    (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
			ctxt->modrm_seg = VCPU_SREG_SS;
1207
		modrm_ea = (u16)modrm_ea;
1208 1209
	} else {
		/* 32/64-bit ModR/M decode. */
1210
		if ((ctxt->modrm_rm & 7) == 4) {
1211
			sib = insn_fetch(u8, ctxt);
1212 1213 1214 1215
			index_reg |= (sib >> 3) & 7;
			base_reg |= sib & 7;
			scale = sib >> 6;

1216
			if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
1217
				modrm_ea += insn_fetch(s32, ctxt);
1218
			else {
1219
				modrm_ea += reg_read(ctxt, base_reg);
1220 1221
				adjust_modrm_seg(ctxt, base_reg);
			}
1222
			if (index_reg != 4)
1223
				modrm_ea += reg_read(ctxt, index_reg) << scale;
1224
		} else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
1225
			if (ctxt->mode == X86EMUL_MODE_PROT64)
1226
				ctxt->rip_relative = 1;
1227 1228
		} else {
			base_reg = ctxt->modrm_rm;
1229
			modrm_ea += reg_read(ctxt, base_reg);
1230 1231
			adjust_modrm_seg(ctxt, base_reg);
		}
1232
		switch (ctxt->modrm_mod) {
1233
		case 0:
1234
			if (ctxt->modrm_rm == 5)
1235
				modrm_ea += insn_fetch(s32, ctxt);
1236 1237
			break;
		case 1:
1238
			modrm_ea += insn_fetch(s8, ctxt);
1239 1240
			break;
		case 2:
1241
			modrm_ea += insn_fetch(s32, ctxt);
1242 1243 1244
			break;
		}
	}
1245
	op->addr.mem.ea = modrm_ea;
1246 1247 1248
	if (ctxt->ad_bytes != 8)
		ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;

1249 1250 1251 1252 1253
done:
	return rc;
}

static int decode_abs(struct x86_emulate_ctxt *ctxt,
1254
		      struct operand *op)
1255
{
1256
	int rc = X86EMUL_CONTINUE;
1257

1258
	op->type = OP_MEM;
1259
	switch (ctxt->ad_bytes) {
1260
	case 2:
1261
		op->addr.mem.ea = insn_fetch(u16, ctxt);
1262 1263
		break;
	case 4:
1264
		op->addr.mem.ea = insn_fetch(u32, ctxt);
1265 1266
		break;
	case 8:
1267
		op->addr.mem.ea = insn_fetch(u64, ctxt);
1268 1269 1270 1271 1272 1273
		break;
	}
done:
	return rc;
}

1274
static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
1275
{
1276
	long sv = 0, mask;
1277

1278
	if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1279
		mask = ~((long)ctxt->dst.bytes * 8 - 1);
1280

1281 1282 1283 1284
		if (ctxt->src.bytes == 2)
			sv = (s16)ctxt->src.val & (s16)mask;
		else if (ctxt->src.bytes == 4)
			sv = (s32)ctxt->src.val & (s32)mask;
1285 1286
		else
			sv = (s64)ctxt->src.val & (s64)mask;
1287

1288
		ctxt->dst.addr.mem.ea += (sv >> 3);
1289
	}
1290 1291

	/* only subword offset */
1292
	ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
1293 1294
}

1295 1296
static int read_emulated(struct x86_emulate_ctxt *ctxt,
			 unsigned long addr, void *dest, unsigned size)
A
Avi Kivity 已提交
1297
{
1298
	int rc;
1299
	struct read_cache *mc = &ctxt->mem_read;
A
Avi Kivity 已提交
1300

1301 1302
	if (mc->pos < mc->end)
		goto read_cached;
A
Avi Kivity 已提交
1303

1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315
	WARN_ON((mc->end + size) >= sizeof(mc->data));

	rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
				      &ctxt->exception);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	mc->end += size;

read_cached:
	memcpy(dest, mc->data + mc->pos, size);
	mc->pos += size;
1316 1317
	return X86EMUL_CONTINUE;
}
A
Avi Kivity 已提交
1318

1319 1320 1321 1322 1323
static int segmented_read(struct x86_emulate_ctxt *ctxt,
			  struct segmented_address addr,
			  void *data,
			  unsigned size)
{
1324 1325 1326
	int rc;
	ulong linear;

1327
	rc = linearize(ctxt, addr, size, false, &linear);
1328 1329
	if (rc != X86EMUL_CONTINUE)
		return rc;
1330
	return read_emulated(ctxt, linear, data, size);
1331 1332 1333 1334 1335 1336 1337
}

static int segmented_write(struct x86_emulate_ctxt *ctxt,
			   struct segmented_address addr,
			   const void *data,
			   unsigned size)
{
1338 1339 1340
	int rc;
	ulong linear;

1341
	rc = linearize(ctxt, addr, size, true, &linear);
1342 1343
	if (rc != X86EMUL_CONTINUE)
		return rc;
1344 1345
	return ctxt->ops->write_emulated(ctxt, linear, data, size,
					 &ctxt->exception);
1346 1347 1348 1349 1350 1351 1352
}

static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
			     struct segmented_address addr,
			     const void *orig_data, const void *data,
			     unsigned size)
{
1353 1354 1355
	int rc;
	ulong linear;

1356
	rc = linearize(ctxt, addr, size, true, &linear);
1357 1358
	if (rc != X86EMUL_CONTINUE)
		return rc;
1359 1360
	return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
					   size, &ctxt->exception);
1361 1362
}

1363 1364 1365 1366
static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
			   unsigned int size, unsigned short port,
			   void *dest)
{
1367
	struct read_cache *rc = &ctxt->io_read;
1368

1369 1370
	if (rc->pos == rc->end) { /* refill pio read ahead */
		unsigned int in_page, n;
1371
		unsigned int count = ctxt->rep_prefix ?
1372
			address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
1373
		in_page = (ctxt->eflags & EFLG_DF) ?
1374 1375
			offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
			PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
1376
		n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
1377 1378 1379
		if (n == 0)
			n = 1;
		rc->pos = rc->end = 0;
1380
		if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
1381 1382
			return 0;
		rc->end = n * size;
A
Avi Kivity 已提交
1383 1384
	}

1385 1386
	if (ctxt->rep_prefix && (ctxt->d & String) &&
	    !(ctxt->eflags & EFLG_DF)) {
1387 1388 1389 1390 1391 1392 1393 1394
		ctxt->dst.data = rc->data + rc->pos;
		ctxt->dst.type = OP_MEM_STR;
		ctxt->dst.count = (rc->end - rc->pos) / size;
		rc->pos = rc->end;
	} else {
		memcpy(dest, rc->data + rc->pos, size);
		rc->pos += size;
	}
1395 1396
	return 1;
}
A
Avi Kivity 已提交
1397

1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413
static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
				     u16 index, struct desc_struct *desc)
{
	struct desc_ptr dt;
	ulong addr;

	ctxt->ops->get_idt(ctxt, &dt);

	if (dt.size < index * 8 + 7)
		return emulate_gp(ctxt, index << 3 | 0x2);

	addr = dt.address + index * 8;
	return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
				   &ctxt->exception);
}

1414 1415 1416
static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
				     u16 selector, struct desc_ptr *dt)
{
1417
	const struct x86_emulate_ops *ops = ctxt->ops;
1418
	u32 base3 = 0;
1419

1420 1421
	if (selector & 1 << 2) {
		struct desc_struct desc;
1422 1423
		u16 sel;

1424
		memset (dt, 0, sizeof *dt);
1425 1426
		if (!ops->get_segment(ctxt, &sel, &desc, &base3,
				      VCPU_SREG_LDTR))
1427
			return;
1428

1429
		dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1430
		dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
1431
	} else
1432
		ops->get_gdt(ctxt, dt);
1433
}
1434

1435 1436
/* allowed just for 8 bytes segments */
static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1437 1438
				   u16 selector, struct desc_struct *desc,
				   ulong *desc_addr_p)
1439 1440 1441 1442
{
	struct desc_ptr dt;
	u16 index = selector >> 3;
	ulong addr;
1443

1444
	get_descriptor_table_ptr(ctxt, selector, &dt);
1445

1446 1447
	if (dt.size < index * 8 + 7)
		return emulate_gp(ctxt, selector & 0xfffc);
1448

1449
	*desc_addr_p = addr = dt.address + index * 8;
1450 1451
	return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
				   &ctxt->exception);
1452
}
1453

1454 1455 1456 1457 1458 1459 1460
/* allowed just for 8 bytes segments */
static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				    u16 selector, struct desc_struct *desc)
{
	struct desc_ptr dt;
	u16 index = selector >> 3;
	ulong addr;
A
Avi Kivity 已提交
1461

1462
	get_descriptor_table_ptr(ctxt, selector, &dt);
1463

1464 1465
	if (dt.size < index * 8 + 7)
		return emulate_gp(ctxt, selector & 0xfffc);
A
Avi Kivity 已提交
1466

1467
	addr = dt.address + index * 8;
1468 1469
	return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
				    &ctxt->exception);
1470
}
1471

1472
/* Does not support long mode */
1473
static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1474 1475 1476
				     u16 selector, int seg, u8 cpl,
				     bool in_task_switch,
				     struct desc_struct *desc)
1477
{
1478
	struct desc_struct seg_desc, old_desc;
1479
	u8 dpl, rpl;
1480 1481 1482
	unsigned err_vec = GP_VECTOR;
	u32 err_code = 0;
	bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1483
	ulong desc_addr;
1484
	int ret;
1485
	u16 dummy;
1486
	u32 base3 = 0;
1487

1488
	memset(&seg_desc, 0, sizeof seg_desc);
1489

1490 1491 1492
	if (ctxt->mode == X86EMUL_MODE_REAL) {
		/* set real mode segment descriptor (keep limit etc. for
		 * unreal mode) */
1493
		ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
1494 1495
		set_desc_base(&seg_desc, selector << 4);
		goto load;
1496 1497 1498 1499 1500 1501 1502 1503 1504
	} else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
		/* VM86 needs a clean new segment descriptor */
		set_desc_base(&seg_desc, selector << 4);
		set_desc_limit(&seg_desc, 0xffff);
		seg_desc.type = 3;
		seg_desc.p = 1;
		seg_desc.s = 1;
		seg_desc.dpl = 3;
		goto load;
1505 1506
	}

1507 1508 1509 1510 1511 1512 1513
	rpl = selector & 3;

	/* NULL selector is not valid for TR, CS and SS (except for long mode) */
	if ((seg == VCPU_SREG_CS
	     || (seg == VCPU_SREG_SS
		 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
	     || seg == VCPU_SREG_TR)
1514 1515 1516 1517 1518 1519 1520 1521 1522 1523
	    && null_selector)
		goto exception;

	/* TR should be in GDT only */
	if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
		goto exception;

	if (null_selector) /* for NULL selector skip all following checks */
		goto load;

1524
	ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
1525 1526 1527 1528
	if (ret != X86EMUL_CONTINUE)
		return ret;

	err_code = selector & 0xfffc;
1529
	err_vec = in_task_switch ? TS_VECTOR : GP_VECTOR;
1530

G
Guo Chao 已提交
1531
	/* can't load system descriptor into segment selector */
1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549
	if (seg <= VCPU_SREG_GS && !seg_desc.s)
		goto exception;

	if (!seg_desc.p) {
		err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
		goto exception;
	}

	dpl = seg_desc.dpl;

	switch (seg) {
	case VCPU_SREG_SS:
		/*
		 * segment is not a writable data segment or segment
		 * selector's RPL != CPL or segment selector's RPL != CPL
		 */
		if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
			goto exception;
A
Avi Kivity 已提交
1550
		break;
1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563
	case VCPU_SREG_CS:
		if (!(seg_desc.type & 8))
			goto exception;

		if (seg_desc.type & 4) {
			/* conforming */
			if (dpl > cpl)
				goto exception;
		} else {
			/* nonconforming */
			if (rpl > cpl || dpl != cpl)
				goto exception;
		}
1564 1565 1566 1567 1568 1569 1570 1571 1572
		/* in long-mode d/b must be clear if l is set */
		if (seg_desc.d && seg_desc.l) {
			u64 efer = 0;

			ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
			if (efer & EFER_LMA)
				goto exception;
		}

1573 1574
		/* CS(RPL) <- CPL */
		selector = (selector & 0xfffc) | cpl;
A
Avi Kivity 已提交
1575
		break;
1576 1577 1578
	case VCPU_SREG_TR:
		if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
			goto exception;
1579 1580 1581 1582 1583 1584
		old_desc = seg_desc;
		seg_desc.type |= 2; /* busy */
		ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
						  sizeof(seg_desc), &ctxt->exception);
		if (ret != X86EMUL_CONTINUE)
			return ret;
1585 1586 1587 1588 1589 1590
		break;
	case VCPU_SREG_LDTR:
		if (seg_desc.s || seg_desc.type != 2)
			goto exception;
		break;
	default: /*  DS, ES, FS, or GS */
1591
		/*
1592 1593 1594
		 * segment is not a data or readable code segment or
		 * ((segment is a data or nonconforming code segment)
		 * and (both RPL and CPL > DPL))
1595
		 */
1596 1597 1598 1599
		if ((seg_desc.type & 0xa) == 0x8 ||
		    (((seg_desc.type & 0xc) != 0xc) &&
		     (rpl > dpl && cpl > dpl)))
			goto exception;
A
Avi Kivity 已提交
1600
		break;
1601 1602 1603 1604 1605
	}

	if (seg_desc.s) {
		/* mark segment as accessed */
		seg_desc.type |= 1;
1606
		ret = write_segment_descriptor(ctxt, selector, &seg_desc);
1607 1608
		if (ret != X86EMUL_CONTINUE)
			return ret;
1609 1610 1611 1612 1613
	} else if (ctxt->mode == X86EMUL_MODE_PROT64) {
		ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
				sizeof(base3), &ctxt->exception);
		if (ret != X86EMUL_CONTINUE)
			return ret;
1614 1615
	}
load:
1616
	ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
1617 1618
	if (desc)
		*desc = seg_desc;
1619 1620
	return X86EMUL_CONTINUE;
exception:
1621
	return emulate_exception(ctxt, err_vec, err_code, true);
1622 1623
}

1624 1625 1626 1627
static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				   u16 selector, int seg)
{
	u8 cpl = ctxt->ops->cpl(ctxt);
1628
	return __load_segment_descriptor(ctxt, selector, seg, cpl, false, NULL);
1629 1630
}

1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 1647 1648 1649
static void write_register_operand(struct operand *op)
{
	/* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
	switch (op->bytes) {
	case 1:
		*(u8 *)op->addr.reg = (u8)op->val;
		break;
	case 2:
		*(u16 *)op->addr.reg = (u16)op->val;
		break;
	case 4:
		*op->addr.reg = (u32)op->val;
		break;	/* 64b: zero-extend */
	case 8:
		*op->addr.reg = op->val;
		break;
	}
}

1650
static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
1651
{
1652
	switch (op->type) {
1653
	case OP_REG:
1654
		write_register_operand(op);
A
Avi Kivity 已提交
1655
		break;
1656
	case OP_MEM:
1657
		if (ctxt->lock_prefix)
P
Paolo Bonzini 已提交
1658 1659 1660 1661 1662 1663 1664
			return segmented_cmpxchg(ctxt,
						 op->addr.mem,
						 &op->orig_val,
						 &op->val,
						 op->bytes);
		else
			return segmented_write(ctxt,
1665 1666 1667
					       op->addr.mem,
					       &op->val,
					       op->bytes);
1668
		break;
1669
	case OP_MEM_STR:
P
Paolo Bonzini 已提交
1670 1671 1672 1673
		return segmented_write(ctxt,
				       op->addr.mem,
				       op->data,
				       op->bytes * op->count);
1674
		break;
A
Avi Kivity 已提交
1675
	case OP_XMM:
1676
		write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
A
Avi Kivity 已提交
1677
		break;
A
Avi Kivity 已提交
1678
	case OP_MM:
1679
		write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
A
Avi Kivity 已提交
1680
		break;
1681 1682
	case OP_NONE:
		/* no writeback */
1683
		break;
1684
	default:
1685
		break;
A
Avi Kivity 已提交
1686
	}
1687 1688
	return X86EMUL_CONTINUE;
}
A
Avi Kivity 已提交
1689

1690
static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
1691
{
1692
	struct segmented_address addr;
1693

1694
	rsp_increment(ctxt, -bytes);
1695
	addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1696 1697
	addr.seg = VCPU_SREG_SS;

1698 1699 1700 1701 1702
	return segmented_write(ctxt, addr, data, bytes);
}

static int em_push(struct x86_emulate_ctxt *ctxt)
{
1703
	/* Disable writeback. */
1704
	ctxt->dst.type = OP_NONE;
1705
	return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
1706
}
1707

1708 1709 1710 1711
static int emulate_pop(struct x86_emulate_ctxt *ctxt,
		       void *dest, int len)
{
	int rc;
1712
	struct segmented_address addr;
1713

1714
	addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1715
	addr.seg = VCPU_SREG_SS;
1716
	rc = segmented_read(ctxt, addr, dest, len);
1717 1718 1719
	if (rc != X86EMUL_CONTINUE)
		return rc;

1720
	rsp_increment(ctxt, len);
1721
	return rc;
1722 1723
}

1724 1725
static int em_pop(struct x86_emulate_ctxt *ctxt)
{
1726
	return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1727 1728
}

1729
static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1730
			void *dest, int len)
1731 1732
{
	int rc;
1733 1734
	unsigned long val, change_mask;
	int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1735
	int cpl = ctxt->ops->cpl(ctxt);
1736

1737
	rc = emulate_pop(ctxt, &val, len);
1738 1739
	if (rc != X86EMUL_CONTINUE)
		return rc;
1740

1741
	change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1742
		| EFLG_TF | EFLG_DF | EFLG_NT | EFLG_AC | EFLG_ID;
1743

1744 1745 1746 1747 1748 1749 1750 1751 1752 1753
	switch(ctxt->mode) {
	case X86EMUL_MODE_PROT64:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT16:
		if (cpl == 0)
			change_mask |= EFLG_IOPL;
		if (cpl <= iopl)
			change_mask |= EFLG_IF;
		break;
	case X86EMUL_MODE_VM86:
1754 1755
		if (iopl < 3)
			return emulate_gp(ctxt, 0);
1756 1757 1758 1759 1760
		change_mask |= EFLG_IF;
		break;
	default: /* real mode */
		change_mask |= (EFLG_IOPL | EFLG_IF);
		break;
1761
	}
1762 1763 1764 1765 1766

	*(unsigned long *)dest =
		(ctxt->eflags & ~change_mask) | (val & change_mask);

	return rc;
1767 1768
}

1769 1770
static int em_popf(struct x86_emulate_ctxt *ctxt)
{
1771 1772 1773 1774
	ctxt->dst.type = OP_REG;
	ctxt->dst.addr.reg = &ctxt->eflags;
	ctxt->dst.bytes = ctxt->op_bytes;
	return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1775 1776
}

A
Avi Kivity 已提交
1777 1778 1779 1780 1781
static int em_enter(struct x86_emulate_ctxt *ctxt)
{
	int rc;
	unsigned frame_size = ctxt->src.val;
	unsigned nesting_level = ctxt->src2.val & 31;
1782
	ulong rbp;
A
Avi Kivity 已提交
1783 1784 1785 1786

	if (nesting_level)
		return X86EMUL_UNHANDLEABLE;

1787 1788
	rbp = reg_read(ctxt, VCPU_REGS_RBP);
	rc = push(ctxt, &rbp, stack_size(ctxt));
A
Avi Kivity 已提交
1789 1790
	if (rc != X86EMUL_CONTINUE)
		return rc;
1791
	assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
A
Avi Kivity 已提交
1792
		      stack_mask(ctxt));
1793 1794
	assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
		      reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
A
Avi Kivity 已提交
1795 1796 1797 1798
		      stack_mask(ctxt));
	return X86EMUL_CONTINUE;
}

A
Avi Kivity 已提交
1799 1800
static int em_leave(struct x86_emulate_ctxt *ctxt)
{
1801
	assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
A
Avi Kivity 已提交
1802
		      stack_mask(ctxt));
1803
	return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
A
Avi Kivity 已提交
1804 1805
}

1806
static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
1807
{
1808 1809
	int seg = ctxt->src2.val;

1810
	ctxt->src.val = get_segment_selector(ctxt, seg);
1811

1812
	return em_push(ctxt);
1813 1814
}

1815
static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
1816
{
1817
	int seg = ctxt->src2.val;
1818 1819
	unsigned long selector;
	int rc;
1820

1821
	rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
1822 1823 1824
	if (rc != X86EMUL_CONTINUE)
		return rc;

1825 1826 1827
	if (ctxt->modrm_reg == VCPU_SREG_SS)
		ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;

1828
	rc = load_segment_descriptor(ctxt, (u16)selector, seg);
1829
	return rc;
1830 1831
}

1832
static int em_pusha(struct x86_emulate_ctxt *ctxt)
1833
{
1834
	unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
1835 1836
	int rc = X86EMUL_CONTINUE;
	int reg = VCPU_REGS_RAX;
1837

1838 1839
	while (reg <= VCPU_REGS_RDI) {
		(reg == VCPU_REGS_RSP) ?
1840
		(ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
1841

1842
		rc = em_push(ctxt);
1843 1844
		if (rc != X86EMUL_CONTINUE)
			return rc;
1845

1846
		++reg;
1847 1848
	}

1849
	return rc;
1850 1851
}

1852 1853
static int em_pushf(struct x86_emulate_ctxt *ctxt)
{
1854
	ctxt->src.val =  (unsigned long)ctxt->eflags;
1855 1856 1857
	return em_push(ctxt);
}

1858
static int em_popa(struct x86_emulate_ctxt *ctxt)
1859
{
1860 1861
	int rc = X86EMUL_CONTINUE;
	int reg = VCPU_REGS_RDI;
1862

1863 1864
	while (reg >= VCPU_REGS_RAX) {
		if (reg == VCPU_REGS_RSP) {
1865
			rsp_increment(ctxt, ctxt->op_bytes);
1866 1867
			--reg;
		}
1868

1869
		rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
1870 1871 1872
		if (rc != X86EMUL_CONTINUE)
			break;
		--reg;
1873
	}
1874
	return rc;
1875 1876
}

1877
static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1878
{
1879
	const struct x86_emulate_ops *ops = ctxt->ops;
1880
	int rc;
1881 1882 1883 1884 1885 1886
	struct desc_ptr dt;
	gva_t cs_addr;
	gva_t eip_addr;
	u16 cs, eip;

	/* TODO: Add limit checks */
1887
	ctxt->src.val = ctxt->eflags;
1888
	rc = em_push(ctxt);
1889 1890
	if (rc != X86EMUL_CONTINUE)
		return rc;
1891 1892 1893

	ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);

1894
	ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
1895
	rc = em_push(ctxt);
1896 1897
	if (rc != X86EMUL_CONTINUE)
		return rc;
1898

1899
	ctxt->src.val = ctxt->_eip;
1900
	rc = em_push(ctxt);
1901 1902 1903
	if (rc != X86EMUL_CONTINUE)
		return rc;

1904
	ops->get_idt(ctxt, &dt);
1905 1906 1907 1908

	eip_addr = dt.address + (irq << 2);
	cs_addr = dt.address + (irq << 2) + 2;

1909
	rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
1910 1911 1912
	if (rc != X86EMUL_CONTINUE)
		return rc;

1913
	rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
1914 1915 1916
	if (rc != X86EMUL_CONTINUE)
		return rc;

1917
	rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
1918 1919 1920
	if (rc != X86EMUL_CONTINUE)
		return rc;

1921
	ctxt->_eip = eip;
1922 1923 1924 1925

	return rc;
}

1926 1927 1928 1929 1930 1931 1932 1933 1934 1935 1936
int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
{
	int rc;

	invalidate_registers(ctxt);
	rc = __emulate_int_real(ctxt, irq);
	if (rc == X86EMUL_CONTINUE)
		writeback_registers(ctxt);
	return rc;
}

1937
static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
1938 1939 1940
{
	switch(ctxt->mode) {
	case X86EMUL_MODE_REAL:
1941
		return __emulate_int_real(ctxt, irq);
1942 1943 1944 1945 1946 1947 1948 1949 1950 1951
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT64:
	default:
		/* Protected mode interrupts unimplemented yet */
		return X86EMUL_UNHANDLEABLE;
	}
}

1952
static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
1953
{
1954 1955 1956 1957 1958 1959 1960 1961
	int rc = X86EMUL_CONTINUE;
	unsigned long temp_eip = 0;
	unsigned long temp_eflags = 0;
	unsigned long cs = 0;
	unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
			     EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
			     EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
	unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1962

1963
	/* TODO: Add stack limit check */
1964

1965
	rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
1966

1967 1968
	if (rc != X86EMUL_CONTINUE)
		return rc;
1969

1970 1971
	if (temp_eip & ~0xffff)
		return emulate_gp(ctxt, 0);
1972

1973
	rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1974

1975 1976
	if (rc != X86EMUL_CONTINUE)
		return rc;
1977

1978
	rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
1979

1980 1981
	if (rc != X86EMUL_CONTINUE)
		return rc;
1982

1983
	rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
1984

1985 1986
	if (rc != X86EMUL_CONTINUE)
		return rc;
1987

1988
	ctxt->_eip = temp_eip;
1989 1990


1991
	if (ctxt->op_bytes == 4)
1992
		ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1993
	else if (ctxt->op_bytes == 2) {
1994 1995
		ctxt->eflags &= ~0xffff;
		ctxt->eflags |= temp_eflags;
1996
	}
1997 1998 1999 2000 2001

	ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
	ctxt->eflags |= EFLG_RESERVED_ONE_MASK;

	return rc;
2002 2003
}

2004
static int em_iret(struct x86_emulate_ctxt *ctxt)
2005
{
2006 2007
	switch(ctxt->mode) {
	case X86EMUL_MODE_REAL:
2008
		return emulate_iret_real(ctxt);
2009 2010 2011 2012
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT64:
2013
	default:
2014 2015
		/* iret from protected mode unimplemented yet */
		return X86EMUL_UNHANDLEABLE;
2016 2017 2018
	}
}

2019 2020 2021
static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
{
	int rc;
2022 2023 2024 2025 2026 2027 2028 2029 2030
	unsigned short sel, old_sel;
	struct desc_struct old_desc, new_desc;
	const struct x86_emulate_ops *ops = ctxt->ops;
	u8 cpl = ctxt->ops->cpl(ctxt);

	/* Assignment of RIP may only fail in 64-bit mode */
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		ops->get_segment(ctxt, &old_sel, &old_desc, NULL,
				 VCPU_SREG_CS);
2031

2032
	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2033

2034 2035
	rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, false,
				       &new_desc);
2036 2037 2038
	if (rc != X86EMUL_CONTINUE)
		return rc;

2039 2040
	rc = assign_eip_far(ctxt, ctxt->src.val, new_desc.l);
	if (rc != X86EMUL_CONTINUE) {
2041
		WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
2042 2043 2044 2045 2046
		/* assigning eip failed; restore the old cs */
		ops->set_segment(ctxt, old_sel, &old_desc, 0, VCPU_SREG_CS);
		return rc;
	}
	return rc;
2047 2048
}

2049
static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
2050
{
2051 2052
	return assign_eip_near(ctxt, ctxt->src.val);
}
2053

2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064
static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
{
	int rc;
	long int old_eip;

	old_eip = ctxt->_eip;
	rc = assign_eip_near(ctxt, ctxt->src.val);
	if (rc != X86EMUL_CONTINUE)
		return rc;
	ctxt->src.val = old_eip;
	rc = em_push(ctxt);
2065
	return rc;
2066 2067
}

2068
static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
2069
{
2070
	u64 old = ctxt->dst.orig_val64;
2071

2072 2073 2074
	if (ctxt->dst.bytes == 16)
		return X86EMUL_UNHANDLEABLE;

2075 2076 2077 2078
	if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
	    ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
		*reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
		*reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
2079
		ctxt->eflags &= ~EFLG_ZF;
2080
	} else {
2081 2082
		ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
			(u32) reg_read(ctxt, VCPU_REGS_RBX);
2083

2084
		ctxt->eflags |= EFLG_ZF;
2085
	}
2086
	return X86EMUL_CONTINUE;
2087 2088
}

2089 2090
static int em_ret(struct x86_emulate_ctxt *ctxt)
{
2091 2092 2093 2094 2095 2096 2097 2098
	int rc;
	unsigned long eip;

	rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	return assign_eip_near(ctxt, eip);
2099 2100
}

2101
static int em_ret_far(struct x86_emulate_ctxt *ctxt)
2102 2103
{
	int rc;
2104 2105
	unsigned long eip, cs;
	u16 old_cs;
2106
	int cpl = ctxt->ops->cpl(ctxt);
2107 2108 2109 2110 2111 2112
	struct desc_struct old_desc, new_desc;
	const struct x86_emulate_ops *ops = ctxt->ops;

	if (ctxt->mode == X86EMUL_MODE_PROT64)
		ops->get_segment(ctxt, &old_cs, &old_desc, NULL,
				 VCPU_SREG_CS);
2113

2114
	rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2115
	if (rc != X86EMUL_CONTINUE)
2116
		return rc;
2117
	rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
2118
	if (rc != X86EMUL_CONTINUE)
2119
		return rc;
2120 2121 2122
	/* Outer-privilege level return is not implemented */
	if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
		return X86EMUL_UNHANDLEABLE;
2123 2124 2125 2126 2127 2128
	rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, 0, false,
				       &new_desc);
	if (rc != X86EMUL_CONTINUE)
		return rc;
	rc = assign_eip_far(ctxt, eip, new_desc.l);
	if (rc != X86EMUL_CONTINUE) {
2129
		WARN_ON(ctxt->mode != X86EMUL_MODE_PROT64);
2130 2131
		ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
	}
2132 2133 2134
	return rc;
}

2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145
static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
{
        int rc;

        rc = em_ret_far(ctxt);
        if (rc != X86EMUL_CONTINUE)
                return rc;
        rsp_increment(ctxt, ctxt->src.val);
        return X86EMUL_CONTINUE;
}

2146 2147 2148
static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
{
	/* Save real source value, then compare EAX against destination. */
2149 2150
	ctxt->dst.orig_val = ctxt->dst.val;
	ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
2151
	ctxt->src.orig_val = ctxt->src.val;
2152
	ctxt->src.val = ctxt->dst.orig_val;
2153
	fastop(ctxt, em_cmp);
2154 2155 2156 2157 2158 2159 2160

	if (ctxt->eflags & EFLG_ZF) {
		/* Success: write back to memory. */
		ctxt->dst.val = ctxt->src.orig_val;
	} else {
		/* Failure: write the value we saw to EAX. */
		ctxt->dst.type = OP_REG;
2161
		ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
2162
		ctxt->dst.val = ctxt->dst.orig_val;
2163 2164 2165 2166
	}
	return X86EMUL_CONTINUE;
}

2167
static int em_lseg(struct x86_emulate_ctxt *ctxt)
2168
{
2169
	int seg = ctxt->src2.val;
2170 2171 2172
	unsigned short sel;
	int rc;

2173
	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2174

2175
	rc = load_segment_descriptor(ctxt, sel, seg);
2176 2177 2178
	if (rc != X86EMUL_CONTINUE)
		return rc;

2179
	ctxt->dst.val = ctxt->src.val;
2180 2181 2182
	return rc;
}

2183
static void
2184
setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
2185
			struct desc_struct *cs, struct desc_struct *ss)
2186 2187
{
	cs->l = 0;		/* will be adjusted later */
2188
	set_desc_base(cs, 0);	/* flat segment */
2189
	cs->g = 1;		/* 4kb granularity */
2190
	set_desc_limit(cs, 0xfffff);	/* 4GB limit */
2191 2192 2193
	cs->type = 0x0b;	/* Read, Execute, Accessed */
	cs->s = 1;
	cs->dpl = 0;		/* will be adjusted later */
2194 2195
	cs->p = 1;
	cs->d = 1;
2196
	cs->avl = 0;
2197

2198 2199
	set_desc_base(ss, 0);	/* flat segment */
	set_desc_limit(ss, 0xfffff);	/* 4GB limit */
2200 2201 2202
	ss->g = 1;		/* 4kb granularity */
	ss->s = 1;
	ss->type = 0x03;	/* Read/Write, Accessed */
2203
	ss->d = 1;		/* 32bit stack segment */
2204
	ss->dpl = 0;
2205
	ss->p = 1;
2206 2207
	ss->l = 0;
	ss->avl = 0;
2208 2209
}

2210 2211 2212 2213 2214
static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
{
	u32 eax, ebx, ecx, edx;

	eax = ecx = 0;
2215 2216
	ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
	return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
2217 2218 2219 2220
		&& ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
		&& edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
}

2221 2222
static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
{
2223
	const struct x86_emulate_ops *ops = ctxt->ops;
2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234
	u32 eax, ebx, ecx, edx;

	/*
	 * syscall should always be enabled in longmode - so only become
	 * vendor specific (cpuid) if other modes are active...
	 */
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		return true;

	eax = 0x00000000;
	ecx = 0x00000000;
2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259
	ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
	/*
	 * Intel ("GenuineIntel")
	 * remark: Intel CPUs only support "syscall" in 64bit
	 * longmode. Also an 64bit guest with a
	 * 32bit compat-app running will #UD !! While this
	 * behaviour can be fixed (by emulating) into AMD
	 * response - CPUs of AMD can't behave like Intel.
	 */
	if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
	    ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
	    edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
		return false;

	/* AMD ("AuthenticAMD") */
	if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
	    ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
	    edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
		return true;

	/* AMD ("AMDisbetter!") */
	if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
	    ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
	    edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
		return true;
2260 2261 2262 2263 2264

	/* default: (not Intel, not AMD), apply Intel's stricter rules... */
	return false;
}

2265
static int em_syscall(struct x86_emulate_ctxt *ctxt)
2266
{
2267
	const struct x86_emulate_ops *ops = ctxt->ops;
2268
	struct desc_struct cs, ss;
2269
	u64 msr_data;
2270
	u16 cs_sel, ss_sel;
2271
	u64 efer = 0;
2272 2273

	/* syscall is not available in real mode */
2274
	if (ctxt->mode == X86EMUL_MODE_REAL ||
2275 2276
	    ctxt->mode == X86EMUL_MODE_VM86)
		return emulate_ud(ctxt);
2277

2278 2279 2280
	if (!(em_syscall_is_enabled(ctxt)))
		return emulate_ud(ctxt);

2281
	ops->get_msr(ctxt, MSR_EFER, &efer);
2282
	setup_syscalls_segments(ctxt, &cs, &ss);
2283

2284 2285 2286
	if (!(efer & EFER_SCE))
		return emulate_ud(ctxt);

2287
	ops->get_msr(ctxt, MSR_STAR, &msr_data);
2288
	msr_data >>= 32;
2289 2290
	cs_sel = (u16)(msr_data & 0xfffc);
	ss_sel = (u16)(msr_data + 8);
2291

2292
	if (efer & EFER_LMA) {
2293
		cs.d = 0;
2294 2295
		cs.l = 1;
	}
2296 2297
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2298

2299
	*reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
2300
	if (efer & EFER_LMA) {
2301
#ifdef CONFIG_X86_64
2302
		*reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
2303

2304
		ops->get_msr(ctxt,
2305 2306
			     ctxt->mode == X86EMUL_MODE_PROT64 ?
			     MSR_LSTAR : MSR_CSTAR, &msr_data);
2307
		ctxt->_eip = msr_data;
2308

2309
		ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
2310
		ctxt->eflags &= ~msr_data;
2311 2312 2313
#endif
	} else {
		/* legacy mode */
2314
		ops->get_msr(ctxt, MSR_STAR, &msr_data);
2315
		ctxt->_eip = (u32)msr_data;
2316

2317
		ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
2318 2319
	}

2320
	return X86EMUL_CONTINUE;
2321 2322
}

2323
static int em_sysenter(struct x86_emulate_ctxt *ctxt)
2324
{
2325
	const struct x86_emulate_ops *ops = ctxt->ops;
2326
	struct desc_struct cs, ss;
2327
	u64 msr_data;
2328
	u16 cs_sel, ss_sel;
2329
	u64 efer = 0;
2330

2331
	ops->get_msr(ctxt, MSR_EFER, &efer);
2332
	/* inject #GP if in real mode */
2333 2334
	if (ctxt->mode == X86EMUL_MODE_REAL)
		return emulate_gp(ctxt, 0);
2335

2336 2337 2338 2339 2340 2341 2342 2343
	/*
	 * Not recognized on AMD in compat mode (but is recognized in legacy
	 * mode).
	 */
	if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
	    && !vendor_intel(ctxt))
		return emulate_ud(ctxt);

2344 2345 2346
	/* XXX sysenter/sysexit have not been tested in 64bit mode.
	* Therefore, we inject an #UD.
	*/
2347 2348
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		return emulate_ud(ctxt);
2349

2350
	setup_syscalls_segments(ctxt, &cs, &ss);
2351

2352
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2353 2354
	switch (ctxt->mode) {
	case X86EMUL_MODE_PROT32:
2355 2356
		if ((msr_data & 0xfffc) == 0x0)
			return emulate_gp(ctxt, 0);
2357 2358
		break;
	case X86EMUL_MODE_PROT64:
2359 2360
		if (msr_data == 0x0)
			return emulate_gp(ctxt, 0);
2361
		break;
2362 2363
	default:
		break;
2364 2365
	}

2366
	ctxt->eflags &= ~(EFLG_VM | EFLG_IF);
2367 2368 2369 2370
	cs_sel = (u16)msr_data;
	cs_sel &= ~SELECTOR_RPL_MASK;
	ss_sel = cs_sel + 8;
	ss_sel &= ~SELECTOR_RPL_MASK;
2371
	if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
2372
		cs.d = 0;
2373 2374 2375
		cs.l = 1;
	}

2376 2377
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2378

2379
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
2380
	ctxt->_eip = msr_data;
2381

2382
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
2383
	*reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
2384

2385
	return X86EMUL_CONTINUE;
2386 2387
}

2388
static int em_sysexit(struct x86_emulate_ctxt *ctxt)
2389
{
2390
	const struct x86_emulate_ops *ops = ctxt->ops;
2391
	struct desc_struct cs, ss;
2392
	u64 msr_data, rcx, rdx;
2393
	int usermode;
X
Xiao Guangrong 已提交
2394
	u16 cs_sel = 0, ss_sel = 0;
2395

2396 2397
	/* inject #GP if in real mode or Virtual 8086 mode */
	if (ctxt->mode == X86EMUL_MODE_REAL ||
2398 2399
	    ctxt->mode == X86EMUL_MODE_VM86)
		return emulate_gp(ctxt, 0);
2400

2401
	setup_syscalls_segments(ctxt, &cs, &ss);
2402

2403
	if ((ctxt->rex_prefix & 0x8) != 0x0)
2404 2405 2406 2407
		usermode = X86EMUL_MODE_PROT64;
	else
		usermode = X86EMUL_MODE_PROT32;

2408 2409 2410
	rcx = reg_read(ctxt, VCPU_REGS_RCX);
	rdx = reg_read(ctxt, VCPU_REGS_RDX);

2411 2412
	cs.dpl = 3;
	ss.dpl = 3;
2413
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2414 2415
	switch (usermode) {
	case X86EMUL_MODE_PROT32:
2416
		cs_sel = (u16)(msr_data + 16);
2417 2418
		if ((msr_data & 0xfffc) == 0x0)
			return emulate_gp(ctxt, 0);
2419
		ss_sel = (u16)(msr_data + 24);
2420 2421
		break;
	case X86EMUL_MODE_PROT64:
2422
		cs_sel = (u16)(msr_data + 32);
2423 2424
		if (msr_data == 0x0)
			return emulate_gp(ctxt, 0);
2425 2426
		ss_sel = cs_sel + 8;
		cs.d = 0;
2427
		cs.l = 1;
2428 2429 2430
		if (is_noncanonical_address(rcx) ||
		    is_noncanonical_address(rdx))
			return emulate_gp(ctxt, 0);
2431 2432
		break;
	}
2433 2434
	cs_sel |= SELECTOR_RPL_MASK;
	ss_sel |= SELECTOR_RPL_MASK;
2435

2436 2437
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2438

2439 2440
	ctxt->_eip = rdx;
	*reg_write(ctxt, VCPU_REGS_RSP) = rcx;
2441

2442
	return X86EMUL_CONTINUE;
2443 2444
}

2445
static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
2446 2447 2448 2449 2450 2451 2452
{
	int iopl;
	if (ctxt->mode == X86EMUL_MODE_REAL)
		return false;
	if (ctxt->mode == X86EMUL_MODE_VM86)
		return true;
	iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
2453
	return ctxt->ops->cpl(ctxt) > iopl;
2454 2455 2456 2457 2458
}

static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
					    u16 port, u16 len)
{
2459
	const struct x86_emulate_ops *ops = ctxt->ops;
2460
	struct desc_struct tr_seg;
2461
	u32 base3;
2462
	int r;
2463
	u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
2464
	unsigned mask = (1 << len) - 1;
2465
	unsigned long base;
2466

2467
	ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
2468
	if (!tr_seg.p)
2469
		return false;
2470
	if (desc_limit_scaled(&tr_seg) < 103)
2471
		return false;
2472 2473 2474 2475
	base = get_desc_base(&tr_seg);
#ifdef CONFIG_X86_64
	base |= ((u64)base3) << 32;
#endif
2476
	r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
2477 2478
	if (r != X86EMUL_CONTINUE)
		return false;
2479
	if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
2480
		return false;
2481
	r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
2482 2483 2484 2485 2486 2487 2488 2489 2490 2491
	if (r != X86EMUL_CONTINUE)
		return false;
	if ((perm >> bit_idx) & mask)
		return false;
	return true;
}

static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
				 u16 port, u16 len)
{
2492 2493 2494
	if (ctxt->perm_ok)
		return true;

2495 2496
	if (emulator_bad_iopl(ctxt))
		if (!emulator_io_port_access_allowed(ctxt, port, len))
2497
			return false;
2498 2499 2500

	ctxt->perm_ok = true;

2501 2502 2503
	return true;
}

2504 2505 2506
static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
				struct tss_segment_16 *tss)
{
2507
	tss->ip = ctxt->_eip;
2508
	tss->flag = ctxt->eflags;
2509 2510 2511 2512 2513 2514 2515 2516
	tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
	tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
	tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
	tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
	tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
	tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
	tss->si = reg_read(ctxt, VCPU_REGS_RSI);
	tss->di = reg_read(ctxt, VCPU_REGS_RDI);
2517

2518 2519 2520 2521 2522
	tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
	tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
	tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
	tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
	tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2523 2524 2525 2526 2527 2528
}

static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
				 struct tss_segment_16 *tss)
{
	int ret;
2529
	u8 cpl;
2530

2531
	ctxt->_eip = tss->ip;
2532
	ctxt->eflags = tss->flag | 2;
2533 2534 2535 2536 2537 2538 2539 2540
	*reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
	*reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
	*reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
	*reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
	*reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
	*reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
	*reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
	*reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
2541 2542 2543 2544 2545

	/*
	 * SDM says that segment selectors are loaded before segment
	 * descriptors
	 */
2546 2547 2548 2549 2550
	set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
	set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
	set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
	set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
	set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2551

2552 2553
	cpl = tss->cs & 3;

2554
	/*
G
Guo Chao 已提交
2555
	 * Now load segment descriptors. If fault happens at this stage
2556 2557
	 * it is handled in a context of new task
	 */
2558 2559
	ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
					true, NULL);
2560 2561
	if (ret != X86EMUL_CONTINUE)
		return ret;
2562 2563
	ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
					true, NULL);
2564 2565
	if (ret != X86EMUL_CONTINUE)
		return ret;
2566 2567
	ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
					true, NULL);
2568 2569
	if (ret != X86EMUL_CONTINUE)
		return ret;
2570 2571
	ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
					true, NULL);
2572 2573
	if (ret != X86EMUL_CONTINUE)
		return ret;
2574 2575
	ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
					true, NULL);
2576 2577 2578 2579 2580 2581 2582 2583 2584 2585
	if (ret != X86EMUL_CONTINUE)
		return ret;

	return X86EMUL_CONTINUE;
}

static int task_switch_16(struct x86_emulate_ctxt *ctxt,
			  u16 tss_selector, u16 old_tss_sel,
			  ulong old_tss_base, struct desc_struct *new_desc)
{
2586
	const struct x86_emulate_ops *ops = ctxt->ops;
2587 2588
	struct tss_segment_16 tss_seg;
	int ret;
2589
	u32 new_tss_base = get_desc_base(new_desc);
2590

2591
	ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2592
			    &ctxt->exception);
2593
	if (ret != X86EMUL_CONTINUE)
2594 2595 2596
		/* FIXME: need to provide precise fault address */
		return ret;

2597
	save_state_to_tss16(ctxt, &tss_seg);
2598

2599
	ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2600
			     &ctxt->exception);
2601
	if (ret != X86EMUL_CONTINUE)
2602 2603 2604
		/* FIXME: need to provide precise fault address */
		return ret;

2605
	ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2606
			    &ctxt->exception);
2607
	if (ret != X86EMUL_CONTINUE)
2608 2609 2610 2611 2612 2613
		/* FIXME: need to provide precise fault address */
		return ret;

	if (old_tss_sel != 0xffff) {
		tss_seg.prev_task_link = old_tss_sel;

2614
		ret = ops->write_std(ctxt, new_tss_base,
2615 2616
				     &tss_seg.prev_task_link,
				     sizeof tss_seg.prev_task_link,
2617
				     &ctxt->exception);
2618
		if (ret != X86EMUL_CONTINUE)
2619 2620 2621 2622
			/* FIXME: need to provide precise fault address */
			return ret;
	}

2623
	return load_state_from_tss16(ctxt, &tss_seg);
2624 2625 2626 2627 2628
}

static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
				struct tss_segment_32 *tss)
{
2629
	/* CR3 and ldt selector are not saved intentionally */
2630
	tss->eip = ctxt->_eip;
2631
	tss->eflags = ctxt->eflags;
2632 2633 2634 2635 2636 2637 2638 2639
	tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
	tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
	tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
	tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
	tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
	tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
	tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
	tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
2640

2641 2642 2643 2644 2645 2646
	tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
	tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
	tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
	tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
	tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
	tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2647 2648 2649 2650 2651 2652
}

static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
				 struct tss_segment_32 *tss)
{
	int ret;
2653
	u8 cpl;
2654

2655
	if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
2656
		return emulate_gp(ctxt, 0);
2657
	ctxt->_eip = tss->eip;
2658
	ctxt->eflags = tss->eflags | 2;
2659 2660

	/* General purpose registers */
2661 2662 2663 2664 2665 2666 2667 2668
	*reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
	*reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
	*reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
	*reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
	*reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
	*reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
	*reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
	*reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
2669 2670 2671

	/*
	 * SDM says that segment selectors are loaded before segment
2672 2673
	 * descriptors.  This is important because CPL checks will
	 * use CS.RPL.
2674
	 */
2675 2676 2677 2678 2679 2680 2681
	set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
	set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
	set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
	set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
	set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
	set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
	set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
2682

2683 2684 2685 2686 2687
	/*
	 * If we're switching between Protected Mode and VM86, we need to make
	 * sure to update the mode before loading the segment descriptors so
	 * that the selectors are interpreted correctly.
	 */
2688
	if (ctxt->eflags & X86_EFLAGS_VM) {
2689
		ctxt->mode = X86EMUL_MODE_VM86;
2690 2691
		cpl = 3;
	} else {
2692
		ctxt->mode = X86EMUL_MODE_PROT32;
2693 2694
		cpl = tss->cs & 3;
	}
2695

2696 2697 2698 2699
	/*
	 * Now load segment descriptors. If fault happenes at this stage
	 * it is handled in a context of new task
	 */
2700 2701
	ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
					cpl, true, NULL);
2702 2703
	if (ret != X86EMUL_CONTINUE)
		return ret;
2704 2705
	ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
					true, NULL);
2706 2707
	if (ret != X86EMUL_CONTINUE)
		return ret;
2708 2709
	ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
					true, NULL);
2710 2711
	if (ret != X86EMUL_CONTINUE)
		return ret;
2712 2713
	ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
					true, NULL);
2714 2715
	if (ret != X86EMUL_CONTINUE)
		return ret;
2716 2717
	ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
					true, NULL);
2718 2719
	if (ret != X86EMUL_CONTINUE)
		return ret;
2720 2721
	ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
					true, NULL);
2722 2723
	if (ret != X86EMUL_CONTINUE)
		return ret;
2724 2725
	ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
					true, NULL);
2726 2727 2728 2729 2730 2731 2732 2733 2734 2735
	if (ret != X86EMUL_CONTINUE)
		return ret;

	return X86EMUL_CONTINUE;
}

static int task_switch_32(struct x86_emulate_ctxt *ctxt,
			  u16 tss_selector, u16 old_tss_sel,
			  ulong old_tss_base, struct desc_struct *new_desc)
{
2736
	const struct x86_emulate_ops *ops = ctxt->ops;
2737 2738
	struct tss_segment_32 tss_seg;
	int ret;
2739
	u32 new_tss_base = get_desc_base(new_desc);
2740 2741
	u32 eip_offset = offsetof(struct tss_segment_32, eip);
	u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
2742

2743
	ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2744
			    &ctxt->exception);
2745
	if (ret != X86EMUL_CONTINUE)
2746 2747 2748
		/* FIXME: need to provide precise fault address */
		return ret;

2749
	save_state_to_tss32(ctxt, &tss_seg);
2750

2751 2752 2753
	/* Only GP registers and segment selectors are saved */
	ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
			     ldt_sel_offset - eip_offset, &ctxt->exception);
2754
	if (ret != X86EMUL_CONTINUE)
2755 2756 2757
		/* FIXME: need to provide precise fault address */
		return ret;

2758
	ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2759
			    &ctxt->exception);
2760
	if (ret != X86EMUL_CONTINUE)
2761 2762 2763 2764 2765 2766
		/* FIXME: need to provide precise fault address */
		return ret;

	if (old_tss_sel != 0xffff) {
		tss_seg.prev_task_link = old_tss_sel;

2767
		ret = ops->write_std(ctxt, new_tss_base,
2768 2769
				     &tss_seg.prev_task_link,
				     sizeof tss_seg.prev_task_link,
2770
				     &ctxt->exception);
2771
		if (ret != X86EMUL_CONTINUE)
2772 2773 2774 2775
			/* FIXME: need to provide precise fault address */
			return ret;
	}

2776
	return load_state_from_tss32(ctxt, &tss_seg);
2777 2778 2779
}

static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2780
				   u16 tss_selector, int idt_index, int reason,
2781
				   bool has_error_code, u32 error_code)
2782
{
2783
	const struct x86_emulate_ops *ops = ctxt->ops;
2784 2785
	struct desc_struct curr_tss_desc, next_tss_desc;
	int ret;
2786
	u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
2787
	ulong old_tss_base =
2788
		ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
2789
	u32 desc_limit;
2790
	ulong desc_addr;
2791 2792 2793

	/* FIXME: old_tss_base == ~0 ? */

2794
	ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
2795 2796
	if (ret != X86EMUL_CONTINUE)
		return ret;
2797
	ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
2798 2799 2800 2801 2802
	if (ret != X86EMUL_CONTINUE)
		return ret;

	/* FIXME: check that next_tss_desc is tss */

2803 2804 2805 2806 2807
	/*
	 * Check privileges. The three cases are task switch caused by...
	 *
	 * 1. jmp/call/int to task gate: Check against DPL of the task gate
	 * 2. Exception/IRQ/iret: No check is performed
G
Guo Chao 已提交
2808
	 * 3. jmp/call to TSS: Check against DPL of the TSS
2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828
	 */
	if (reason == TASK_SWITCH_GATE) {
		if (idt_index != -1) {
			/* Software interrupts */
			struct desc_struct task_gate_desc;
			int dpl;

			ret = read_interrupt_descriptor(ctxt, idt_index,
							&task_gate_desc);
			if (ret != X86EMUL_CONTINUE)
				return ret;

			dpl = task_gate_desc.dpl;
			if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
				return emulate_gp(ctxt, (idt_index << 3) | 0x2);
		}
	} else if (reason != TASK_SWITCH_IRET) {
		int dpl = next_tss_desc.dpl;
		if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
			return emulate_gp(ctxt, tss_selector);
2829 2830
	}

2831

2832 2833 2834 2835
	desc_limit = desc_limit_scaled(&next_tss_desc);
	if (!next_tss_desc.p ||
	    ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
	     desc_limit < 0x2b)) {
2836
		return emulate_ts(ctxt, tss_selector & 0xfffc);
2837 2838 2839 2840
	}

	if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
		curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2841
		write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
2842 2843 2844 2845 2846 2847
	}

	if (reason == TASK_SWITCH_IRET)
		ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;

	/* set back link to prev task only if NT bit is set in eflags
G
Guo Chao 已提交
2848
	   note that old_tss_sel is not used after this point */
2849 2850 2851 2852
	if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
		old_tss_sel = 0xffff;

	if (next_tss_desc.type & 8)
2853
		ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
2854 2855
				     old_tss_base, &next_tss_desc);
	else
2856
		ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
2857
				     old_tss_base, &next_tss_desc);
2858 2859
	if (ret != X86EMUL_CONTINUE)
		return ret;
2860 2861 2862 2863 2864 2865

	if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
		ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;

	if (reason != TASK_SWITCH_IRET) {
		next_tss_desc.type |= (1 << 1); /* set busy flag */
2866
		write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
2867 2868
	}

2869
	ops->set_cr(ctxt, 0,  ops->get_cr(ctxt, 0) | X86_CR0_TS);
2870
	ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
2871

2872
	if (has_error_code) {
2873 2874 2875
		ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
		ctxt->lock_prefix = 0;
		ctxt->src.val = (unsigned long) error_code;
2876
		ret = em_push(ctxt);
2877 2878
	}

2879 2880 2881 2882
	return ret;
}

int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2883
			 u16 tss_selector, int idt_index, int reason,
2884
			 bool has_error_code, u32 error_code)
2885 2886 2887
{
	int rc;

2888
	invalidate_registers(ctxt);
2889 2890
	ctxt->_eip = ctxt->eip;
	ctxt->dst.type = OP_NONE;
2891

2892
	rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
2893
				     has_error_code, error_code);
2894

2895
	if (rc == X86EMUL_CONTINUE) {
2896
		ctxt->eip = ctxt->_eip;
2897 2898
		writeback_registers(ctxt);
	}
2899

2900
	return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
2901 2902
}

2903 2904
static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
		struct operand *op)
2905
{
2906
	int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
2907

2908 2909
	register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
	op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
2910 2911
}

2912 2913 2914 2915 2916 2917
static int em_das(struct x86_emulate_ctxt *ctxt)
{
	u8 al, old_al;
	bool af, cf, old_cf;

	cf = ctxt->eflags & X86_EFLAGS_CF;
2918
	al = ctxt->dst.val;
2919 2920 2921 2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935

	old_al = al;
	old_cf = cf;
	cf = false;
	af = ctxt->eflags & X86_EFLAGS_AF;
	if ((al & 0x0f) > 9 || af) {
		al -= 6;
		cf = old_cf | (al >= 250);
		af = true;
	} else {
		af = false;
	}
	if (old_al > 0x99 || old_cf) {
		al -= 0x60;
		cf = true;
	}

2936
	ctxt->dst.val = al;
2937
	/* Set PF, ZF, SF */
2938 2939 2940
	ctxt->src.type = OP_IMM;
	ctxt->src.val = 0;
	ctxt->src.bytes = 1;
2941
	fastop(ctxt, em_or);
2942 2943 2944 2945 2946 2947 2948 2949
	ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
	if (cf)
		ctxt->eflags |= X86_EFLAGS_CF;
	if (af)
		ctxt->eflags |= X86_EFLAGS_AF;
	return X86EMUL_CONTINUE;
}

P
Paolo Bonzini 已提交
2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971
static int em_aam(struct x86_emulate_ctxt *ctxt)
{
	u8 al, ah;

	if (ctxt->src.val == 0)
		return emulate_de(ctxt);

	al = ctxt->dst.val & 0xff;
	ah = al / ctxt->src.val;
	al %= ctxt->src.val;

	ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);

	/* Set PF, ZF, SF */
	ctxt->src.type = OP_IMM;
	ctxt->src.val = 0;
	ctxt->src.bytes = 1;
	fastop(ctxt, em_or);

	return X86EMUL_CONTINUE;
}

2972 2973 2974 2975 2976 2977 2978 2979 2980
static int em_aad(struct x86_emulate_ctxt *ctxt)
{
	u8 al = ctxt->dst.val & 0xff;
	u8 ah = (ctxt->dst.val >> 8) & 0xff;

	al = (al + (ah * ctxt->src.val)) & 0xff;

	ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;

2981 2982 2983 2984 2985
	/* Set PF, ZF, SF */
	ctxt->src.type = OP_IMM;
	ctxt->src.val = 0;
	ctxt->src.bytes = 1;
	fastop(ctxt, em_or);
2986 2987 2988 2989

	return X86EMUL_CONTINUE;
}

2990 2991
static int em_call(struct x86_emulate_ctxt *ctxt)
{
2992
	int rc;
2993 2994 2995
	long rel = ctxt->src.val;

	ctxt->src.val = (unsigned long)ctxt->_eip;
2996 2997 2998
	rc = jmp_rel(ctxt, rel);
	if (rc != X86EMUL_CONTINUE)
		return rc;
2999 3000 3001
	return em_push(ctxt);
}

3002 3003 3004 3005 3006
static int em_call_far(struct x86_emulate_ctxt *ctxt)
{
	u16 sel, old_cs;
	ulong old_eip;
	int rc;
3007 3008 3009
	struct desc_struct old_desc, new_desc;
	const struct x86_emulate_ops *ops = ctxt->ops;
	int cpl = ctxt->ops->cpl(ctxt);
3010

3011
	old_eip = ctxt->_eip;
3012
	ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
3013

3014
	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
3015 3016 3017
	rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl, false,
				       &new_desc);
	if (rc != X86EMUL_CONTINUE)
3018 3019
		return X86EMUL_CONTINUE;

3020 3021 3022
	rc = assign_eip_far(ctxt, ctxt->src.val, new_desc.l);
	if (rc != X86EMUL_CONTINUE)
		goto fail;
3023

3024
	ctxt->src.val = old_cs;
3025
	rc = em_push(ctxt);
3026
	if (rc != X86EMUL_CONTINUE)
3027
		goto fail;
3028

3029
	ctxt->src.val = old_eip;
3030 3031 3032 3033 3034 3035 3036 3037 3038 3039
	rc = em_push(ctxt);
	/* If we failed, we tainted the memory, but the very least we should
	   restore cs */
	if (rc != X86EMUL_CONTINUE)
		goto fail;
	return rc;
fail:
	ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
	return rc;

3040 3041
}

3042 3043 3044
static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
{
	int rc;
3045
	unsigned long eip;
3046

3047 3048 3049 3050
	rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
	if (rc != X86EMUL_CONTINUE)
		return rc;
	rc = assign_eip_near(ctxt, eip);
3051 3052
	if (rc != X86EMUL_CONTINUE)
		return rc;
3053
	rsp_increment(ctxt, ctxt->src.val);
3054 3055 3056
	return X86EMUL_CONTINUE;
}

3057 3058 3059
static int em_xchg(struct x86_emulate_ctxt *ctxt)
{
	/* Write back the register source. */
3060 3061
	ctxt->src.val = ctxt->dst.val;
	write_register_operand(&ctxt->src);
3062 3063

	/* Write back the memory destination with implicit LOCK prefix. */
3064 3065
	ctxt->dst.val = ctxt->src.orig_val;
	ctxt->lock_prefix = 1;
3066 3067 3068
	return X86EMUL_CONTINUE;
}

3069 3070
static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
{
3071
	ctxt->dst.val = ctxt->src2.val;
3072
	return fastop(ctxt, em_imul);
3073 3074
}

3075 3076
static int em_cwd(struct x86_emulate_ctxt *ctxt)
{
3077 3078
	ctxt->dst.type = OP_REG;
	ctxt->dst.bytes = ctxt->src.bytes;
3079
	ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
3080
	ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
3081 3082 3083 3084

	return X86EMUL_CONTINUE;
}

3085 3086 3087 3088
static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
{
	u64 tsc = 0;

3089
	ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
3090 3091
	*reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
	*reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
3092 3093 3094
	return X86EMUL_CONTINUE;
}

3095 3096 3097 3098
static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
{
	u64 pmc;

3099
	if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
3100
		return emulate_gp(ctxt, 0);
3101 3102
	*reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
	*reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
3103 3104 3105
	return X86EMUL_CONTINUE;
}

3106 3107
static int em_mov(struct x86_emulate_ctxt *ctxt)
{
3108
	memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
3109 3110 3111
	return X86EMUL_CONTINUE;
}

B
Borislav Petkov 已提交
3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146
#define FFL(x) bit(X86_FEATURE_##x)

static int em_movbe(struct x86_emulate_ctxt *ctxt)
{
	u32 ebx, ecx, edx, eax = 1;
	u16 tmp;

	/*
	 * Check MOVBE is set in the guest-visible CPUID leaf.
	 */
	ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
	if (!(ecx & FFL(MOVBE)))
		return emulate_ud(ctxt);

	switch (ctxt->op_bytes) {
	case 2:
		/*
		 * From MOVBE definition: "...When the operand size is 16 bits,
		 * the upper word of the destination register remains unchanged
		 * ..."
		 *
		 * Both casting ->valptr and ->val to u16 breaks strict aliasing
		 * rules so we have to do the operation almost per hand.
		 */
		tmp = (u16)ctxt->src.val;
		ctxt->dst.val &= ~0xffffUL;
		ctxt->dst.val |= (unsigned long)swab16(tmp);
		break;
	case 4:
		ctxt->dst.val = swab32((u32)ctxt->src.val);
		break;
	case 8:
		ctxt->dst.val = swab64(ctxt->src.val);
		break;
	default:
3147
		BUG();
B
Borislav Petkov 已提交
3148 3149 3150 3151
	}
	return X86EMUL_CONTINUE;
}

3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179
static int em_cr_write(struct x86_emulate_ctxt *ctxt)
{
	if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
		return emulate_gp(ctxt, 0);

	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

static int em_dr_write(struct x86_emulate_ctxt *ctxt)
{
	unsigned long val;

	if (ctxt->mode == X86EMUL_MODE_PROT64)
		val = ctxt->src.val & ~0ULL;
	else
		val = ctxt->src.val & ~0U;

	/* #UD condition is already handled. */
	if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
		return emulate_gp(ctxt, 0);

	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

3180 3181 3182 3183
static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
{
	u64 msr_data;

3184 3185 3186
	msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
		| ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
	if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
3187 3188 3189 3190 3191 3192 3193 3194 3195
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
{
	u64 msr_data;

3196
	if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
3197 3198
		return emulate_gp(ctxt, 0);

3199 3200
	*reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
	*reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
3201 3202 3203
	return X86EMUL_CONTINUE;
}

3204 3205
static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
{
3206
	if (ctxt->modrm_reg > VCPU_SREG_GS)
3207 3208
		return emulate_ud(ctxt);

3209
	ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
3210 3211 3212 3213 3214
	return X86EMUL_CONTINUE;
}

static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
{
3215
	u16 sel = ctxt->src.val;
3216

3217
	if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
3218 3219
		return emulate_ud(ctxt);

3220
	if (ctxt->modrm_reg == VCPU_SREG_SS)
3221 3222 3223
		ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;

	/* Disable writeback. */
3224 3225
	ctxt->dst.type = OP_NONE;
	return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
3226 3227
}

A
Avi Kivity 已提交
3228 3229 3230 3231 3232 3233 3234 3235 3236
static int em_lldt(struct x86_emulate_ctxt *ctxt)
{
	u16 sel = ctxt->src.val;

	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
}

A
Avi Kivity 已提交
3237 3238 3239 3240 3241 3242 3243 3244 3245
static int em_ltr(struct x86_emulate_ctxt *ctxt)
{
	u16 sel = ctxt->src.val;

	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
}

3246 3247
static int em_invlpg(struct x86_emulate_ctxt *ctxt)
{
3248 3249 3250
	int rc;
	ulong linear;

3251
	rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
3252
	if (rc == X86EMUL_CONTINUE)
3253
		ctxt->ops->invlpg(ctxt, linear);
3254
	/* Disable writeback. */
3255
	ctxt->dst.type = OP_NONE;
3256 3257 3258
	return X86EMUL_CONTINUE;
}

3259 3260 3261 3262 3263 3264 3265 3266 3267 3268
static int em_clts(struct x86_emulate_ctxt *ctxt)
{
	ulong cr0;

	cr0 = ctxt->ops->get_cr(ctxt, 0);
	cr0 &= ~X86_CR0_TS;
	ctxt->ops->set_cr(ctxt, 0, cr0);
	return X86EMUL_CONTINUE;
}

3269 3270
static int em_vmcall(struct x86_emulate_ctxt *ctxt)
{
3271
	int rc = ctxt->ops->fix_hypercall(ctxt);
3272 3273 3274 3275 3276

	if (rc != X86EMUL_CONTINUE)
		return rc;

	/* Let the processor re-execute the fixed hypercall */
3277
	ctxt->_eip = ctxt->eip;
3278
	/* Disable writeback. */
3279
	ctxt->dst.type = OP_NONE;
3280 3281 3282
	return X86EMUL_CONTINUE;
}

3283 3284 3285 3286 3287 3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310 3311
static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
				  void (*get)(struct x86_emulate_ctxt *ctxt,
					      struct desc_ptr *ptr))
{
	struct desc_ptr desc_ptr;

	if (ctxt->mode == X86EMUL_MODE_PROT64)
		ctxt->op_bytes = 8;
	get(ctxt, &desc_ptr);
	if (ctxt->op_bytes == 2) {
		ctxt->op_bytes = 4;
		desc_ptr.address &= 0x00ffffff;
	}
	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return segmented_write(ctxt, ctxt->dst.addr.mem,
			       &desc_ptr, 2 + ctxt->op_bytes);
}

static int em_sgdt(struct x86_emulate_ctxt *ctxt)
{
	return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
}

static int em_sidt(struct x86_emulate_ctxt *ctxt)
{
	return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
}

3312 3313 3314 3315 3316
static int em_lgdt(struct x86_emulate_ctxt *ctxt)
{
	struct desc_ptr desc_ptr;
	int rc;

3317 3318
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		ctxt->op_bytes = 8;
3319
	rc = read_descriptor(ctxt, ctxt->src.addr.mem,
3320
			     &desc_ptr.size, &desc_ptr.address,
3321
			     ctxt->op_bytes);
3322 3323 3324 3325
	if (rc != X86EMUL_CONTINUE)
		return rc;
	ctxt->ops->set_gdt(ctxt, &desc_ptr);
	/* Disable writeback. */
3326
	ctxt->dst.type = OP_NONE;
3327 3328 3329
	return X86EMUL_CONTINUE;
}

3330
static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
3331 3332 3333
{
	int rc;

3334 3335
	rc = ctxt->ops->fix_hypercall(ctxt);

3336
	/* Disable writeback. */
3337
	ctxt->dst.type = OP_NONE;
3338 3339 3340 3341 3342 3343 3344 3345
	return rc;
}

static int em_lidt(struct x86_emulate_ctxt *ctxt)
{
	struct desc_ptr desc_ptr;
	int rc;

3346 3347
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		ctxt->op_bytes = 8;
3348
	rc = read_descriptor(ctxt, ctxt->src.addr.mem,
3349
			     &desc_ptr.size, &desc_ptr.address,
3350
			     ctxt->op_bytes);
3351 3352 3353 3354
	if (rc != X86EMUL_CONTINUE)
		return rc;
	ctxt->ops->set_idt(ctxt, &desc_ptr);
	/* Disable writeback. */
3355
	ctxt->dst.type = OP_NONE;
3356 3357 3358 3359 3360
	return X86EMUL_CONTINUE;
}

static int em_smsw(struct x86_emulate_ctxt *ctxt)
{
3361 3362
	if (ctxt->dst.type == OP_MEM)
		ctxt->dst.bytes = 2;
3363
	ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
3364 3365 3366 3367 3368 3369
	return X86EMUL_CONTINUE;
}

static int em_lmsw(struct x86_emulate_ctxt *ctxt)
{
	ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
3370 3371
			  | (ctxt->src.val & 0x0f));
	ctxt->dst.type = OP_NONE;
3372 3373 3374
	return X86EMUL_CONTINUE;
}

3375 3376
static int em_loop(struct x86_emulate_ctxt *ctxt)
{
3377 3378
	int rc = X86EMUL_CONTINUE;

3379 3380
	register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
	if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
3381
	    (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3382
		rc = jmp_rel(ctxt, ctxt->src.val);
3383

3384
	return rc;
3385 3386 3387 3388
}

static int em_jcxz(struct x86_emulate_ctxt *ctxt)
{
3389 3390
	int rc = X86EMUL_CONTINUE;

3391
	if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
3392
		rc = jmp_rel(ctxt, ctxt->src.val);
3393

3394
	return rc;
3395 3396
}

3397 3398 3399 3400 3401 3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414
static int em_in(struct x86_emulate_ctxt *ctxt)
{
	if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
			     &ctxt->dst.val))
		return X86EMUL_IO_NEEDED;

	return X86EMUL_CONTINUE;
}

static int em_out(struct x86_emulate_ctxt *ctxt)
{
	ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
				    &ctxt->src.val, 1);
	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433
static int em_cli(struct x86_emulate_ctxt *ctxt)
{
	if (emulator_bad_iopl(ctxt))
		return emulate_gp(ctxt, 0);

	ctxt->eflags &= ~X86_EFLAGS_IF;
	return X86EMUL_CONTINUE;
}

static int em_sti(struct x86_emulate_ctxt *ctxt)
{
	if (emulator_bad_iopl(ctxt))
		return emulate_gp(ctxt, 0);

	ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
	ctxt->eflags |= X86_EFLAGS_IF;
	return X86EMUL_CONTINUE;
}

A
Avi Kivity 已提交
3434 3435 3436 3437
static int em_cpuid(struct x86_emulate_ctxt *ctxt)
{
	u32 eax, ebx, ecx, edx;

3438 3439
	eax = reg_read(ctxt, VCPU_REGS_RAX);
	ecx = reg_read(ctxt, VCPU_REGS_RCX);
A
Avi Kivity 已提交
3440
	ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3441 3442 3443 3444
	*reg_write(ctxt, VCPU_REGS_RAX) = eax;
	*reg_write(ctxt, VCPU_REGS_RBX) = ebx;
	*reg_write(ctxt, VCPU_REGS_RCX) = ecx;
	*reg_write(ctxt, VCPU_REGS_RDX) = edx;
A
Avi Kivity 已提交
3445 3446 3447
	return X86EMUL_CONTINUE;
}

P
Paolo Bonzini 已提交
3448 3449 3450 3451 3452 3453 3454 3455 3456 3457 3458 3459
static int em_sahf(struct x86_emulate_ctxt *ctxt)
{
	u32 flags;

	flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
	flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;

	ctxt->eflags &= ~0xffUL;
	ctxt->eflags |= flags | X86_EFLAGS_FIXED;
	return X86EMUL_CONTINUE;
}

A
Avi Kivity 已提交
3460 3461
static int em_lahf(struct x86_emulate_ctxt *ctxt)
{
3462 3463
	*reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
	*reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
A
Avi Kivity 已提交
3464 3465 3466
	return X86EMUL_CONTINUE;
}

A
Avi Kivity 已提交
3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481
static int em_bswap(struct x86_emulate_ctxt *ctxt)
{
	switch (ctxt->op_bytes) {
#ifdef CONFIG_X86_64
	case 8:
		asm("bswap %0" : "+r"(ctxt->dst.val));
		break;
#endif
	default:
		asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
		break;
	}
	return X86EMUL_CONTINUE;
}

3482 3483 3484 3485 3486 3487
static int em_clflush(struct x86_emulate_ctxt *ctxt)
{
	/* emulating clflush regardless of cpuid */
	return X86EMUL_CONTINUE;
}

3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498 3499 3500 3501
static bool valid_cr(int nr)
{
	switch (nr) {
	case 0:
	case 2 ... 4:
	case 8:
		return true;
	default:
		return false;
	}
}

static int check_cr_read(struct x86_emulate_ctxt *ctxt)
{
3502
	if (!valid_cr(ctxt->modrm_reg))
3503 3504 3505 3506 3507 3508 3509
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_cr_write(struct x86_emulate_ctxt *ctxt)
{
3510 3511
	u64 new_val = ctxt->src.val64;
	int cr = ctxt->modrm_reg;
3512
	u64 efer = 0;
3513 3514 3515 3516 3517 3518 3519 3520 3521 3522 3523 3524 3525 3526 3527 3528 3529

	static u64 cr_reserved_bits[] = {
		0xffffffff00000000ULL,
		0, 0, 0, /* CR3 checked later */
		CR4_RESERVED_BITS,
		0, 0, 0,
		CR8_RESERVED_BITS,
	};

	if (!valid_cr(cr))
		return emulate_ud(ctxt);

	if (new_val & cr_reserved_bits[cr])
		return emulate_gp(ctxt, 0);

	switch (cr) {
	case 0: {
3530
		u64 cr4;
3531 3532 3533 3534
		if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
		    ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
			return emulate_gp(ctxt, 0);

3535 3536
		cr4 = ctxt->ops->get_cr(ctxt, 4);
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3537 3538 3539 3540 3541 3542 3543 3544 3545 3546

		if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
		    !(cr4 & X86_CR4_PAE))
			return emulate_gp(ctxt, 0);

		break;
		}
	case 3: {
		u64 rsvd = 0;

3547 3548
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
		if (efer & EFER_LMA)
3549 3550 3551 3552 3553 3554 3555 3556
			rsvd = CR3_L_MODE_RESERVED_BITS;

		if (new_val & rsvd)
			return emulate_gp(ctxt, 0);

		break;
		}
	case 4: {
3557
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3558 3559 3560 3561 3562 3563 3564 3565 3566 3567 3568

		if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
			return emulate_gp(ctxt, 0);

		break;
		}
	}

	return X86EMUL_CONTINUE;
}

3569 3570 3571 3572
static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
{
	unsigned long dr7;

3573
	ctxt->ops->get_dr(ctxt, 7, &dr7);
3574 3575 3576 3577 3578 3579 3580

	/* Check if DR7.Global_Enable is set */
	return dr7 & (1 << 13);
}

static int check_dr_read(struct x86_emulate_ctxt *ctxt)
{
3581
	int dr = ctxt->modrm_reg;
3582 3583 3584 3585 3586
	u64 cr4;

	if (dr > 7)
		return emulate_ud(ctxt);

3587
	cr4 = ctxt->ops->get_cr(ctxt, 4);
3588 3589 3590 3591 3592 3593 3594 3595 3596 3597 3598
	if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
		return emulate_ud(ctxt);

	if (check_dr7_gd(ctxt))
		return emulate_db(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_dr_write(struct x86_emulate_ctxt *ctxt)
{
3599 3600
	u64 new_val = ctxt->src.val64;
	int dr = ctxt->modrm_reg;
3601 3602 3603 3604 3605 3606 3607

	if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
		return emulate_gp(ctxt, 0);

	return check_dr_read(ctxt);
}

3608 3609 3610 3611
static int check_svme(struct x86_emulate_ctxt *ctxt)
{
	u64 efer;

3612
	ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3613 3614 3615 3616 3617 3618 3619 3620 3621

	if (!(efer & EFER_SVME))
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
{
3622
	u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
3623 3624

	/* Valid physical address? */
3625
	if (rax & 0xffff000000000000ULL)
3626 3627 3628 3629 3630
		return emulate_gp(ctxt, 0);

	return check_svme(ctxt);
}

3631 3632
static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
{
3633
	u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
3634

3635
	if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
3636 3637 3638 3639 3640
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

3641 3642
static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
{
3643
	u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
3644
	u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
3645

3646
	if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
3647
	    ctxt->ops->check_pmc(ctxt, rcx))
3648 3649 3650 3651 3652
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

3653 3654
static int check_perm_in(struct x86_emulate_ctxt *ctxt)
{
3655 3656
	ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
	if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
3657 3658 3659 3660 3661 3662 3663
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

static int check_perm_out(struct x86_emulate_ctxt *ctxt)
{
3664 3665
	ctxt->src.bytes = min(ctxt->src.bytes, 4u);
	if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
3666 3667 3668 3669 3670
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

3671
#define D(_y) { .flags = (_y) }
3672 3673 3674
#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
		      .intercept = x86_intercept_##_i, .check_perm = (_p) }
3675
#define N    D(NotImpl)
3676
#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
3677 3678
#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
3679
#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
3680
#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
3681
#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
3682
#define II(_f, _e, _i) \
3683
	{ .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
3684
#define IIP(_f, _e, _i, _p) \
3685 3686
	{ .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
	  .intercept = x86_intercept_##_i, .check_perm = (_p) }
3687
#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
3688

3689
#define D2bv(_f)      D((_f) | ByteOp), D(_f)
3690
#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
3691
#define I2bv(_f, _e)  I((_f) | ByteOp, _e), I(_f, _e)
3692
#define F2bv(_f, _e)  F((_f) | ByteOp, _e), F(_f, _e)
3693 3694
#define I2bvIP(_f, _e, _i, _p) \
	IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
3695

3696 3697 3698
#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e),		\
		F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e),	\
		F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
3699

3700 3701 3702 3703 3704 3705
static const struct opcode group7_rm0[] = {
	N,
	I(SrcNone | Priv | EmulateOnUD,	em_vmcall),
	N, N, N, N, N, N,
};

3706
static const struct opcode group7_rm1[] = {
3707 3708
	DI(SrcNone | Priv, monitor),
	DI(SrcNone | Priv, mwait),
3709 3710 3711
	N, N, N, N, N, N,
};

3712
static const struct opcode group7_rm3[] = {
3713
	DIP(SrcNone | Prot | Priv,		vmrun,		check_svme_pa),
3714
	II(SrcNone  | Prot | EmulateOnUD,	em_vmmcall,	vmmcall),
3715 3716 3717 3718 3719 3720
	DIP(SrcNone | Prot | Priv,		vmload,		check_svme_pa),
	DIP(SrcNone | Prot | Priv,		vmsave,		check_svme_pa),
	DIP(SrcNone | Prot | Priv,		stgi,		check_svme),
	DIP(SrcNone | Prot | Priv,		clgi,		check_svme),
	DIP(SrcNone | Prot | Priv,		skinit,		check_svme),
	DIP(SrcNone | Prot | Priv,		invlpga,	check_svme),
3721
};
3722

3723
static const struct opcode group7_rm7[] = {
3724
	N,
3725
	DIP(SrcNone, rdtscp, check_rdtsc),
3726 3727
	N, N, N, N, N, N,
};
3728

3729
static const struct opcode group1[] = {
3730 3731 3732 3733 3734 3735 3736 3737
	F(Lock, em_add),
	F(Lock | PageTable, em_or),
	F(Lock, em_adc),
	F(Lock, em_sbb),
	F(Lock | PageTable, em_and),
	F(Lock, em_sub),
	F(Lock, em_xor),
	F(NoWrite, em_cmp),
3738 3739
};

3740
static const struct opcode group1A[] = {
3741
	I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
3742 3743
};

3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754
static const struct opcode group2[] = {
	F(DstMem | ModRM, em_rol),
	F(DstMem | ModRM, em_ror),
	F(DstMem | ModRM, em_rcl),
	F(DstMem | ModRM, em_rcr),
	F(DstMem | ModRM, em_shl),
	F(DstMem | ModRM, em_shr),
	F(DstMem | ModRM, em_shl),
	F(DstMem | ModRM, em_sar),
};

3755
static const struct opcode group3[] = {
3756 3757
	F(DstMem | SrcImm | NoWrite, em_test),
	F(DstMem | SrcImm | NoWrite, em_test),
3758 3759
	F(DstMem | SrcNone | Lock, em_not),
	F(DstMem | SrcNone | Lock, em_neg),
3760 3761
	F(DstXacc | Src2Mem, em_mul_ex),
	F(DstXacc | Src2Mem, em_imul_ex),
3762 3763
	F(DstXacc | Src2Mem, em_div_ex),
	F(DstXacc | Src2Mem, em_idiv_ex),
3764 3765
};

3766
static const struct opcode group4[] = {
3767 3768
	F(ByteOp | DstMem | SrcNone | Lock, em_inc),
	F(ByteOp | DstMem | SrcNone | Lock, em_dec),
3769 3770 3771
	N, N, N, N, N, N,
};

3772
static const struct opcode group5[] = {
3773 3774
	F(DstMem | SrcNone | Lock,		em_inc),
	F(DstMem | SrcNone | Lock,		em_dec),
3775
	I(SrcMem | NearBranch,			em_call_near_abs),
3776
	I(SrcMemFAddr | ImplicitOps | Stack,	em_call_far),
3777
	I(SrcMem | NearBranch,			em_jmp_abs),
3778 3779
	I(SrcMemFAddr | ImplicitOps,		em_jmp_far),
	I(SrcMem | Stack,			em_push), D(Undefined),
3780 3781
};

3782
static const struct opcode group6[] = {
3783 3784
	DI(Prot,	sldt),
	DI(Prot,	str),
A
Avi Kivity 已提交
3785
	II(Prot | Priv | SrcMem16, em_lldt, lldt),
A
Avi Kivity 已提交
3786
	II(Prot | Priv | SrcMem16, em_ltr, ltr),
3787 3788 3789
	N, N, N, N,
};

3790
static const struct group_dual group7 = { {
3791 3792
	II(Mov | DstMem,			em_sgdt, sgdt),
	II(Mov | DstMem,			em_sidt, sidt),
3793 3794 3795 3796 3797
	II(SrcMem | Priv,			em_lgdt, lgdt),
	II(SrcMem | Priv,			em_lidt, lidt),
	II(SrcNone | DstMem | Mov,		em_smsw, smsw), N,
	II(SrcMem16 | Mov | Priv,		em_lmsw, lmsw),
	II(SrcMem | ByteOp | Priv | NoAccess,	em_invlpg, invlpg),
3798
}, {
3799
	EXT(0, group7_rm0),
3800
	EXT(0, group7_rm1),
3801
	N, EXT(0, group7_rm3),
3802 3803 3804
	II(SrcNone | DstMem | Mov,		em_smsw, smsw), N,
	II(SrcMem16 | Mov | Priv,		em_lmsw, lmsw),
	EXT(0, group7_rm7),
3805 3806
} };

3807
static const struct opcode group8[] = {
3808
	N, N, N, N,
3809 3810 3811 3812
	F(DstMem | SrcImmByte | NoWrite,		em_bt),
	F(DstMem | SrcImmByte | Lock | PageTable,	em_bts),
	F(DstMem | SrcImmByte | Lock,			em_btr),
	F(DstMem | SrcImmByte | Lock | PageTable,	em_btc),
3813 3814
};

3815
static const struct group_dual group9 = { {
3816
	N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
3817 3818 3819 3820
}, {
	N, N, N, N, N, N, N, N,
} };

3821
static const struct opcode group11[] = {
3822
	I(DstMem | SrcImm | Mov | PageTable, em_mov),
3823
	X7(D(Undefined)),
3824 3825
};

3826
static const struct gprefix pfx_0f_ae_7 = {
3827
	I(SrcMem | ByteOp, em_clflush), N, N, N,
3828 3829 3830 3831 3832 3833 3834 3835
};

static const struct group_dual group15 = { {
	N, N, N, N, N, N, N, GP(0, &pfx_0f_ae_7),
}, {
	N, N, N, N, N, N, N, N,
} };

3836
static const struct gprefix pfx_0f_6f_0f_7f = {
3837
	I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
3838 3839
};

3840 3841
static const struct gprefix pfx_0f_2b = {
	I(0, em_mov), I(0, em_mov), N, N,
3842 3843
};

3844
static const struct gprefix pfx_0f_28_0f_29 = {
3845
	I(Aligned, em_mov), I(Aligned, em_mov), N, N,
3846 3847
};

3848 3849 3850 3851
static const struct gprefix pfx_0f_e7 = {
	N, I(Sse, em_mov), N, N,
};

3852 3853 3854 3855 3856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 3871 3872 3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904 3905 3906 3907 3908 3909 3910 3911 3912 3913 3914
static const struct escape escape_d9 = { {
	N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
}, {
	/* 0xC0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xC8 - 0xCF */
	N, N, N, N, N, N, N, N,
	/* 0xD0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xD8 - 0xDF */
	N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xE7 */
	N, N, N, N, N, N, N, N,
	/* 0xE8 - 0xEF */
	N, N, N, N, N, N, N, N,
	/* 0xF0 - 0xF7 */
	N, N, N, N, N, N, N, N,
	/* 0xF8 - 0xFF */
	N, N, N, N, N, N, N, N,
} };

static const struct escape escape_db = { {
	N, N, N, N, N, N, N, N,
}, {
	/* 0xC0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xC8 - 0xCF */
	N, N, N, N, N, N, N, N,
	/* 0xD0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xD8 - 0xDF */
	N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xE7 */
	N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
	/* 0xE8 - 0xEF */
	N, N, N, N, N, N, N, N,
	/* 0xF0 - 0xF7 */
	N, N, N, N, N, N, N, N,
	/* 0xF8 - 0xFF */
	N, N, N, N, N, N, N, N,
} };

static const struct escape escape_dd = { {
	N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
}, {
	/* 0xC0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xC8 - 0xCF */
	N, N, N, N, N, N, N, N,
	/* 0xD0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xD8 - 0xDF */
	N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xE7 */
	N, N, N, N, N, N, N, N,
	/* 0xE8 - 0xEF */
	N, N, N, N, N, N, N, N,
	/* 0xF0 - 0xF7 */
	N, N, N, N, N, N, N, N,
	/* 0xF8 - 0xFF */
	N, N, N, N, N, N, N, N,
} };

3915
static const struct opcode opcode_table[256] = {
3916
	/* 0x00 - 0x07 */
3917
	F6ALU(Lock, em_add),
3918 3919
	I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
	I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
3920
	/* 0x08 - 0x0F */
3921
	F6ALU(Lock | PageTable, em_or),
3922 3923
	I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
	N,
3924
	/* 0x10 - 0x17 */
3925
	F6ALU(Lock, em_adc),
3926 3927
	I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
	I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
3928
	/* 0x18 - 0x1F */
3929
	F6ALU(Lock, em_sbb),
3930 3931
	I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
	I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
3932
	/* 0x20 - 0x27 */
3933
	F6ALU(Lock | PageTable, em_and), N, N,
3934
	/* 0x28 - 0x2F */
3935
	F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
3936
	/* 0x30 - 0x37 */
3937
	F6ALU(Lock, em_xor), N, N,
3938
	/* 0x38 - 0x3F */
3939
	F6ALU(NoWrite, em_cmp), N, N,
3940
	/* 0x40 - 0x4F */
3941
	X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
3942
	/* 0x50 - 0x57 */
3943
	X8(I(SrcReg | Stack, em_push)),
3944
	/* 0x58 - 0x5F */
3945
	X8(I(DstReg | Stack, em_pop)),
3946
	/* 0x60 - 0x67 */
3947 3948
	I(ImplicitOps | Stack | No64, em_pusha),
	I(ImplicitOps | Stack | No64, em_popa),
3949 3950 3951
	N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
	N, N, N, N,
	/* 0x68 - 0x6F */
3952 3953
	I(SrcImm | Mov | Stack, em_push),
	I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
3954 3955
	I(SrcImmByte | Mov | Stack, em_push),
	I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
3956
	I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
3957
	I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
3958
	/* 0x70 - 0x7F */
3959
	X16(D(SrcImmByte | NearBranch)),
3960
	/* 0x80 - 0x87 */
3961 3962 3963 3964
	G(ByteOp | DstMem | SrcImm, group1),
	G(DstMem | SrcImm, group1),
	G(ByteOp | DstMem | SrcImm | No64, group1),
	G(DstMem | SrcImmByte, group1),
3965
	F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
3966
	I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
3967
	/* 0x88 - 0x8F */
3968
	I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
3969
	I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
3970
	I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
3971 3972 3973
	D(ModRM | SrcMem | NoAccess | DstReg),
	I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
	G(0, group1A),
3974
	/* 0x90 - 0x97 */
3975
	DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
3976
	/* 0x98 - 0x9F */
3977
	D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
3978
	I(SrcImmFAddr | No64, em_call_far), N,
3979
	II(ImplicitOps | Stack, em_pushf, pushf),
P
Paolo Bonzini 已提交
3980 3981
	II(ImplicitOps | Stack, em_popf, popf),
	I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
3982
	/* 0xA0 - 0xA7 */
3983
	I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
3984
	I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
3985
	I2bv(SrcSI | DstDI | Mov | String, em_mov),
3986
	F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
3987
	/* 0xA8 - 0xAF */
3988
	F2bv(DstAcc | SrcImm | NoWrite, em_test),
3989 3990
	I2bv(SrcAcc | DstDI | Mov | String, em_mov),
	I2bv(SrcSI | DstAcc | Mov | String, em_mov),
3991
	F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
3992
	/* 0xB0 - 0xB7 */
3993
	X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
3994
	/* 0xB8 - 0xBF */
3995
	X8(I(DstReg | SrcImm64 | Mov, em_mov)),
3996
	/* 0xC0 - 0xC7 */
3997
	G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
3998 3999
	I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
	I(ImplicitOps | NearBranch, em_ret),
4000 4001
	I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
	I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
4002
	G(ByteOp, group11), G(0, group11),
4003
	/* 0xC8 - 0xCF */
A
Avi Kivity 已提交
4004
	I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
4005 4006
	I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
	I(ImplicitOps | Stack, em_ret_far),
4007
	D(ImplicitOps), DI(SrcImmByte, intn),
4008
	D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
4009
	/* 0xD0 - 0xD7 */
4010 4011
	G(Src2One | ByteOp, group2), G(Src2One, group2),
	G(Src2CL | ByteOp, group2), G(Src2CL, group2),
P
Paolo Bonzini 已提交
4012
	I(DstAcc | SrcImmUByte | No64, em_aam),
P
Paolo Bonzini 已提交
4013 4014
	I(DstAcc | SrcImmUByte | No64, em_aad),
	F(DstAcc | ByteOp | No64, em_salc),
P
Paolo Bonzini 已提交
4015
	I(DstAcc | SrcXLat | ByteOp, em_mov),
4016
	/* 0xD8 - 0xDF */
4017
	N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
4018
	/* 0xE0 - 0xE7 */
4019 4020
	X3(I(SrcImmByte | NearBranch, em_loop)),
	I(SrcImmByte | NearBranch, em_jcxz),
4021 4022
	I2bvIP(SrcImmUByte | DstAcc, em_in,  in,  check_perm_in),
	I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
4023
	/* 0xE8 - 0xEF */
4024 4025 4026
	I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
	I(SrcImmFAddr | No64, em_jmp_far),
	D(SrcImmByte | ImplicitOps | NearBranch),
4027 4028
	I2bvIP(SrcDX | DstAcc, em_in,  in,  check_perm_in),
	I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
4029
	/* 0xF0 - 0xF7 */
4030
	N, DI(ImplicitOps, icebp), N, N,
4031 4032
	DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
	G(ByteOp, group3), G(0, group3),
4033
	/* 0xF8 - 0xFF */
4034 4035
	D(ImplicitOps), D(ImplicitOps),
	I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
4036 4037 4038
	D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
};

4039
static const struct opcode twobyte_table[256] = {
4040
	/* 0x00 - 0x0F */
4041
	G(0, group6), GD(0, &group7), N, N,
4042
	N, I(ImplicitOps | EmulateOnUD, em_syscall),
4043
	II(ImplicitOps | Priv, em_clts, clts), N,
4044
	DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
4045
	N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
4046
	/* 0x10 - 0x1F */
P
Paolo Bonzini 已提交
4047
	N, N, N, N, N, N, N, N,
4048 4049
	D(ImplicitOps | ModRM | SrcMem | NoAccess),
	N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
4050
	/* 0x20 - 0x2F */
4051 4052 4053 4054 4055 4056
	DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
	DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
	IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
						check_cr_write),
	IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
						check_dr_write),
4057
	N, N, N, N,
4058 4059
	GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
	GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
4060
	N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
4061
	N, N, N, N,
4062
	/* 0x30 - 0x3F */
4063
	II(ImplicitOps | Priv, em_wrmsr, wrmsr),
4064
	IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
4065
	II(ImplicitOps | Priv, em_rdmsr, rdmsr),
4066
	IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
4067 4068
	I(ImplicitOps | EmulateOnUD, em_sysenter),
	I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
4069
	N, N,
4070 4071
	N, N, N, N, N, N, N, N,
	/* 0x40 - 0x4F */
4072
	X16(D(DstReg | SrcMem | ModRM)),
4073 4074 4075
	/* 0x50 - 0x5F */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0x60 - 0x6F */
4076 4077 4078 4079
	N, N, N, N,
	N, N, N, N,
	N, N, N, N,
	N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
4080
	/* 0x70 - 0x7F */
4081 4082 4083 4084
	N, N, N, N,
	N, N, N, N,
	N, N, N, N,
	N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
4085
	/* 0x80 - 0x8F */
4086
	X16(D(SrcImm | NearBranch)),
4087
	/* 0x90 - 0x9F */
4088
	X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
4089
	/* 0xA0 - 0xA7 */
4090
	I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
4091 4092
	II(ImplicitOps, em_cpuid, cpuid),
	F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
4093 4094
	F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
	F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
4095
	/* 0xA8 - 0xAF */
4096
	I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
4097
	DI(ImplicitOps, rsm),
4098
	F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
4099 4100
	F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
	F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4101
	GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
4102
	/* 0xB0 - 0xB7 */
4103
	I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
4104
	I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
4105
	F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
4106 4107
	I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
	I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
4108
	D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
4109 4110
	/* 0xB8 - 0xBF */
	N, N,
4111
	G(BitOp, group8),
4112 4113
	F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
	F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
4114
	D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
A
Avi Kivity 已提交
4115
	/* 0xC0 - 0xC7 */
4116
	F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
4117
	N, D(DstMem | SrcReg | ModRM | Mov),
4118
	N, N, N, GD(0, &group9),
A
Avi Kivity 已提交
4119 4120
	/* 0xC8 - 0xCF */
	X8(I(DstReg, em_bswap)),
4121 4122 4123
	/* 0xD0 - 0xDF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xEF */
4124 4125
	N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
	N, N, N, N, N, N, N, N,
4126 4127 4128 4129
	/* 0xF0 - 0xFF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
};

4130
static const struct gprefix three_byte_0f_38_f0 = {
B
Borislav Petkov 已提交
4131
	I(DstReg | SrcMem | Mov, em_movbe), N, N, N
4132 4133 4134
};

static const struct gprefix three_byte_0f_38_f1 = {
B
Borislav Petkov 已提交
4135
	I(DstMem | SrcReg | Mov, em_movbe), N, N, N
4136 4137 4138 4139 4140 4141 4142 4143 4144
};

/*
 * Insns below are selected by the prefix which indexed by the third opcode
 * byte.
 */
static const struct opcode opcode_map_0f_38[256] = {
	/* 0x00 - 0x7f */
	X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
B
Borislav Petkov 已提交
4145 4146 4147 4148 4149 4150 4151
	/* 0x80 - 0xef */
	X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
	/* 0xf0 - 0xf1 */
	GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f0),
	GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f1),
	/* 0xf2 - 0xff */
	N, N, X4(N), X8(N)
4152 4153
};

4154 4155 4156 4157 4158
#undef D
#undef N
#undef G
#undef GD
#undef I
4159
#undef GP
4160
#undef EXT
4161

4162
#undef D2bv
4163
#undef D2bvIP
4164
#undef I2bv
4165
#undef I2bvIP
4166
#undef I6ALU
4167

4168
static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
4169 4170 4171
{
	unsigned size;

4172
	size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4173 4174 4175 4176 4177 4178 4179 4180 4181 4182 4183 4184
	if (size == 8)
		size = 4;
	return size;
}

static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
		      unsigned size, bool sign_extension)
{
	int rc = X86EMUL_CONTINUE;

	op->type = OP_IMM;
	op->bytes = size;
4185
	op->addr.mem.ea = ctxt->_eip;
4186 4187 4188
	/* NB. Immediates are sign-extended as necessary. */
	switch (op->bytes) {
	case 1:
4189
		op->val = insn_fetch(s8, ctxt);
4190 4191
		break;
	case 2:
4192
		op->val = insn_fetch(s16, ctxt);
4193 4194
		break;
	case 4:
4195
		op->val = insn_fetch(s32, ctxt);
4196
		break;
4197 4198 4199
	case 8:
		op->val = insn_fetch(s64, ctxt);
		break;
4200 4201 4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212 4213 4214 4215 4216 4217
	}
	if (!sign_extension) {
		switch (op->bytes) {
		case 1:
			op->val &= 0xff;
			break;
		case 2:
			op->val &= 0xffff;
			break;
		case 4:
			op->val &= 0xffffffff;
			break;
		}
	}
done:
	return rc;
}

4218 4219 4220 4221 4222 4223 4224
static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
			  unsigned d)
{
	int rc = X86EMUL_CONTINUE;

	switch (d) {
	case OpReg:
4225
		decode_register_operand(ctxt, op);
4226 4227
		break;
	case OpImmUByte:
4228
		rc = decode_imm(ctxt, op, 1, false);
4229 4230
		break;
	case OpMem:
4231
		ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4232 4233 4234
	mem_common:
		*op = ctxt->memop;
		ctxt->memopp = op;
4235
		if (ctxt->d & BitOp)
4236 4237 4238
			fetch_bit_operand(ctxt);
		op->orig_val = op->val;
		break;
4239
	case OpMem64:
4240
		ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
4241
		goto mem_common;
4242 4243 4244
	case OpAcc:
		op->type = OP_REG;
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4245
		op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4246 4247 4248
		fetch_register_operand(op);
		op->orig_val = op->val;
		break;
4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259 4260 4261 4262 4263 4264 4265 4266
	case OpAccLo:
		op->type = OP_REG;
		op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
		op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
		fetch_register_operand(op);
		op->orig_val = op->val;
		break;
	case OpAccHi:
		if (ctxt->d & ByteOp) {
			op->type = OP_NONE;
			break;
		}
		op->type = OP_REG;
		op->bytes = ctxt->op_bytes;
		op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
		fetch_register_operand(op);
		op->orig_val = op->val;
		break;
4267 4268 4269 4270
	case OpDI:
		op->type = OP_MEM;
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		op->addr.mem.ea =
4271
			register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
4272 4273
		op->addr.mem.seg = VCPU_SREG_ES;
		op->val = 0;
4274
		op->count = 1;
4275 4276 4277 4278
		break;
	case OpDX:
		op->type = OP_REG;
		op->bytes = 2;
4279
		op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4280 4281
		fetch_register_operand(op);
		break;
4282 4283
	case OpCL:
		op->bytes = 1;
4284
		op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295
		break;
	case OpImmByte:
		rc = decode_imm(ctxt, op, 1, true);
		break;
	case OpOne:
		op->bytes = 1;
		op->val = 1;
		break;
	case OpImm:
		rc = decode_imm(ctxt, op, imm_size(ctxt), true);
		break;
4296 4297 4298
	case OpImm64:
		rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
		break;
4299 4300
	case OpMem8:
		ctxt->memop.bytes = 1;
4301
		if (ctxt->memop.type == OP_REG) {
4302 4303
			ctxt->memop.addr.reg = decode_register(ctxt,
					ctxt->modrm_rm, true);
4304 4305
			fetch_register_operand(&ctxt->memop);
		}
4306
		goto mem_common;
4307 4308 4309 4310 4311 4312 4313 4314 4315 4316 4317 4318 4319 4320 4321 4322
	case OpMem16:
		ctxt->memop.bytes = 2;
		goto mem_common;
	case OpMem32:
		ctxt->memop.bytes = 4;
		goto mem_common;
	case OpImmU16:
		rc = decode_imm(ctxt, op, 2, false);
		break;
	case OpImmU:
		rc = decode_imm(ctxt, op, imm_size(ctxt), false);
		break;
	case OpSI:
		op->type = OP_MEM;
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		op->addr.mem.ea =
4323
			register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
B
Bandan Das 已提交
4324
		op->addr.mem.seg = ctxt->seg_override;
4325
		op->val = 0;
4326
		op->count = 1;
4327
		break;
P
Paolo Bonzini 已提交
4328 4329 4330 4331 4332 4333 4334
	case OpXLat:
		op->type = OP_MEM;
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		op->addr.mem.ea =
			register_address(ctxt,
				reg_read(ctxt, VCPU_REGS_RBX) +
				(reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
B
Bandan Das 已提交
4335
		op->addr.mem.seg = ctxt->seg_override;
P
Paolo Bonzini 已提交
4336 4337
		op->val = 0;
		break;
4338 4339 4340 4341 4342 4343 4344 4345 4346
	case OpImmFAddr:
		op->type = OP_IMM;
		op->addr.mem.ea = ctxt->_eip;
		op->bytes = ctxt->op_bytes + 2;
		insn_fetch_arr(op->valptr, op->bytes, ctxt);
		break;
	case OpMemFAddr:
		ctxt->memop.bytes = ctxt->op_bytes + 2;
		goto mem_common;
4347 4348 4349 4350 4351 4352 4353 4354 4355 4356 4357 4358 4359 4360 4361 4362 4363 4364
	case OpES:
		op->val = VCPU_SREG_ES;
		break;
	case OpCS:
		op->val = VCPU_SREG_CS;
		break;
	case OpSS:
		op->val = VCPU_SREG_SS;
		break;
	case OpDS:
		op->val = VCPU_SREG_DS;
		break;
	case OpFS:
		op->val = VCPU_SREG_FS;
		break;
	case OpGS:
		op->val = VCPU_SREG_GS;
		break;
4365 4366 4367 4368 4369 4370 4371 4372 4373 4374 4375
	case OpImplicit:
		/* Special instructions do their own operand decoding. */
	default:
		op->type = OP_NONE; /* Disable writeback. */
		break;
	}

done:
	return rc;
}

4376
int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
4377 4378 4379
{
	int rc = X86EMUL_CONTINUE;
	int mode = ctxt->mode;
4380
	int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
4381
	bool op_prefix = false;
B
Bandan Das 已提交
4382
	bool has_seg_override = false;
4383
	struct opcode opcode;
4384

4385 4386
	ctxt->memop.type = OP_NONE;
	ctxt->memopp = NULL;
4387
	ctxt->_eip = ctxt->eip;
4388 4389
	ctxt->fetch.ptr = ctxt->fetch.data;
	ctxt->fetch.end = ctxt->fetch.data + insn_len;
B
Borislav Petkov 已提交
4390
	ctxt->opcode_len = 1;
4391
	if (insn_len > 0)
4392
		memcpy(ctxt->fetch.data, insn, insn_len);
4393
	else {
4394
		rc = __do_insn_fetch_bytes(ctxt, 1);
4395 4396 4397
		if (rc != X86EMUL_CONTINUE)
			return rc;
	}
4398 4399 4400 4401 4402 4403 4404 4405 4406 4407 4408 4409 4410 4411 4412 4413 4414

	switch (mode) {
	case X86EMUL_MODE_REAL:
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
		def_op_bytes = def_ad_bytes = 2;
		break;
	case X86EMUL_MODE_PROT32:
		def_op_bytes = def_ad_bytes = 4;
		break;
#ifdef CONFIG_X86_64
	case X86EMUL_MODE_PROT64:
		def_op_bytes = 4;
		def_ad_bytes = 8;
		break;
#endif
	default:
4415
		return EMULATION_FAILED;
4416 4417
	}

4418 4419
	ctxt->op_bytes = def_op_bytes;
	ctxt->ad_bytes = def_ad_bytes;
4420 4421 4422

	/* Legacy prefixes. */
	for (;;) {
4423
		switch (ctxt->b = insn_fetch(u8, ctxt)) {
4424
		case 0x66:	/* operand-size override */
4425
			op_prefix = true;
4426
			/* switch between 2/4 bytes */
4427
			ctxt->op_bytes = def_op_bytes ^ 6;
4428 4429 4430 4431
			break;
		case 0x67:	/* address-size override */
			if (mode == X86EMUL_MODE_PROT64)
				/* switch between 4/8 bytes */
4432
				ctxt->ad_bytes = def_ad_bytes ^ 12;
4433 4434
			else
				/* switch between 2/4 bytes */
4435
				ctxt->ad_bytes = def_ad_bytes ^ 6;
4436 4437 4438 4439 4440
			break;
		case 0x26:	/* ES override */
		case 0x2e:	/* CS override */
		case 0x36:	/* SS override */
		case 0x3e:	/* DS override */
B
Bandan Das 已提交
4441 4442
			has_seg_override = true;
			ctxt->seg_override = (ctxt->b >> 3) & 3;
4443 4444 4445
			break;
		case 0x64:	/* FS override */
		case 0x65:	/* GS override */
B
Bandan Das 已提交
4446 4447
			has_seg_override = true;
			ctxt->seg_override = ctxt->b & 7;
4448 4449 4450 4451
			break;
		case 0x40 ... 0x4f: /* REX */
			if (mode != X86EMUL_MODE_PROT64)
				goto done_prefixes;
4452
			ctxt->rex_prefix = ctxt->b;
4453 4454
			continue;
		case 0xf0:	/* LOCK */
4455
			ctxt->lock_prefix = 1;
4456 4457 4458
			break;
		case 0xf2:	/* REPNE/REPNZ */
		case 0xf3:	/* REP/REPE/REPZ */
4459
			ctxt->rep_prefix = ctxt->b;
4460 4461 4462 4463 4464 4465 4466
			break;
		default:
			goto done_prefixes;
		}

		/* Any legacy prefix after a REX prefix nullifies its effect. */

4467
		ctxt->rex_prefix = 0;
4468 4469 4470 4471 4472
	}

done_prefixes:

	/* REX prefix. */
4473 4474
	if (ctxt->rex_prefix & 8)
		ctxt->op_bytes = 8;	/* REX.W */
4475 4476

	/* Opcode byte(s). */
4477
	opcode = opcode_table[ctxt->b];
4478
	/* Two-byte opcode? */
4479
	if (ctxt->b == 0x0f) {
B
Borislav Petkov 已提交
4480
		ctxt->opcode_len = 2;
4481
		ctxt->b = insn_fetch(u8, ctxt);
4482
		opcode = twobyte_table[ctxt->b];
4483 4484 4485 4486 4487 4488 4489

		/* 0F_38 opcode map */
		if (ctxt->b == 0x38) {
			ctxt->opcode_len = 3;
			ctxt->b = insn_fetch(u8, ctxt);
			opcode = opcode_map_0f_38[ctxt->b];
		}
4490
	}
4491
	ctxt->d = opcode.flags;
4492

4493 4494 4495
	if (ctxt->d & ModRM)
		ctxt->modrm = insn_fetch(u8, ctxt);

4496 4497 4498 4499 4500 4501 4502
	/* vex-prefix instructions are not implemented */
	if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
	    (mode == X86EMUL_MODE_PROT64 ||
	    (mode >= X86EMUL_MODE_PROT16 && (ctxt->modrm & 0x80)))) {
		ctxt->d = NotImpl;
	}

4503 4504
	while (ctxt->d & GroupMask) {
		switch (ctxt->d & GroupMask) {
4505
		case Group:
4506
			goffset = (ctxt->modrm >> 3) & 7;
4507 4508 4509
			opcode = opcode.u.group[goffset];
			break;
		case GroupDual:
4510 4511
			goffset = (ctxt->modrm >> 3) & 7;
			if ((ctxt->modrm >> 6) == 3)
4512 4513 4514 4515 4516
				opcode = opcode.u.gdual->mod3[goffset];
			else
				opcode = opcode.u.gdual->mod012[goffset];
			break;
		case RMExt:
4517
			goffset = ctxt->modrm & 7;
4518
			opcode = opcode.u.group[goffset];
4519 4520
			break;
		case Prefix:
4521
			if (ctxt->rep_prefix && op_prefix)
4522
				return EMULATION_FAILED;
4523
			simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
4524 4525 4526 4527 4528 4529 4530
			switch (simd_prefix) {
			case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
			case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
			case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
			case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
			}
			break;
4531 4532 4533 4534 4535 4536
		case Escape:
			if (ctxt->modrm > 0xbf)
				opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
			else
				opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
			break;
4537
		default:
4538
			return EMULATION_FAILED;
4539
		}
4540

4541
		ctxt->d &= ~(u64)GroupMask;
4542
		ctxt->d |= opcode.flags;
4543 4544
	}

4545 4546 4547 4548
	/* Unrecognised? */
	if (ctxt->d == 0)
		return EMULATION_FAILED;

4549
	ctxt->execute = opcode.u.execute;
4550

4551 4552 4553
	if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
		return EMULATION_FAILED;

4554
	if (unlikely(ctxt->d &
4555
	    (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch))) {
4556 4557 4558 4559 4560 4561
		/*
		 * These are copied unconditionally here, and checked unconditionally
		 * in x86_emulate_insn.
		 */
		ctxt->check_perm = opcode.check_perm;
		ctxt->intercept = opcode.intercept;
4562

4563 4564
		if (ctxt->d & NotImpl)
			return EMULATION_FAILED;
4565

4566 4567 4568 4569 4570 4571
		if (mode == X86EMUL_MODE_PROT64) {
			if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
				ctxt->op_bytes = 8;
			else if (ctxt->d & NearBranch)
				ctxt->op_bytes = 8;
		}
4572

4573 4574 4575 4576 4577 4578 4579 4580 4581 4582 4583 4584
		if (ctxt->d & Op3264) {
			if (mode == X86EMUL_MODE_PROT64)
				ctxt->op_bytes = 8;
			else
				ctxt->op_bytes = 4;
		}

		if (ctxt->d & Sse)
			ctxt->op_bytes = 16;
		else if (ctxt->d & Mmx)
			ctxt->op_bytes = 8;
	}
A
Avi Kivity 已提交
4585

4586
	/* ModRM and SIB bytes. */
4587
	if (ctxt->d & ModRM) {
4588
		rc = decode_modrm(ctxt, &ctxt->memop);
B
Bandan Das 已提交
4589 4590 4591 4592
		if (!has_seg_override) {
			has_seg_override = true;
			ctxt->seg_override = ctxt->modrm_seg;
		}
4593
	} else if (ctxt->d & MemAbs)
4594
		rc = decode_abs(ctxt, &ctxt->memop);
4595 4596 4597
	if (rc != X86EMUL_CONTINUE)
		goto done;

B
Bandan Das 已提交
4598 4599
	if (!has_seg_override)
		ctxt->seg_override = VCPU_SREG_DS;
4600

B
Bandan Das 已提交
4601
	ctxt->memop.addr.mem.seg = ctxt->seg_override;
4602 4603 4604 4605 4606

	/*
	 * Decode and fetch the source operand: register, memory
	 * or immediate.
	 */
4607
	rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
4608 4609 4610
	if (rc != X86EMUL_CONTINUE)
		goto done;

4611 4612 4613 4614
	/*
	 * Decode and fetch the second source operand: register, memory
	 * or immediate.
	 */
4615
	rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
4616 4617 4618
	if (rc != X86EMUL_CONTINUE)
		goto done;

4619
	/* Decode and fetch the destination operand: register or memory. */
4620
	rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
4621

4622
	if (ctxt->rip_relative)
4623
		ctxt->memopp->addr.mem.ea += ctxt->_eip;
4624

4625
done:
4626
	return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
4627 4628
}

4629 4630 4631 4632 4633
bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
{
	return ctxt->d & PageTable;
}

4634 4635 4636 4637 4638 4639 4640 4641 4642
static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
{
	/* The second termination condition only applies for REPE
	 * and REPNE. Test if the repeat string operation prefix is
	 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
	 * corresponding termination condition according to:
	 * 	- if REPE/REPZ and ZF = 0 then done
	 * 	- if REPNE/REPNZ and ZF = 1 then done
	 */
4643 4644 4645
	if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
	     (ctxt->b == 0xae) || (ctxt->b == 0xaf))
	    && (((ctxt->rep_prefix == REPE_PREFIX) &&
4646
		 ((ctxt->eflags & EFLG_ZF) == 0))
4647
		|| ((ctxt->rep_prefix == REPNE_PREFIX) &&
4648 4649 4650 4651 4652 4653
		    ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
		return true;

	return false;
}

A
Avi Kivity 已提交
4654 4655 4656 4657 4658 4659 4660 4661 4662 4663 4664 4665 4666
static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
{
	bool fault = false;

	ctxt->ops->get_fpu(ctxt);
	asm volatile("1: fwait \n\t"
		     "2: \n\t"
		     ".pushsection .fixup,\"ax\" \n\t"
		     "3: \n\t"
		     "movb $1, %[fault] \n\t"
		     "jmp 2b \n\t"
		     ".popsection \n\t"
		     _ASM_EXTABLE(1b, 3b)
4667
		     : [fault]"+qm"(fault));
A
Avi Kivity 已提交
4668 4669 4670 4671 4672 4673 4674 4675 4676 4677 4678 4679 4680 4681 4682
	ctxt->ops->put_fpu(ctxt);

	if (unlikely(fault))
		return emulate_exception(ctxt, MF_VECTOR, 0, false);

	return X86EMUL_CONTINUE;
}

static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
				       struct operand *op)
{
	if (op->type == OP_MM)
		read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
}

4683 4684 4685
static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
{
	ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
4686 4687
	if (!(ctxt->d & ByteOp))
		fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
4688
	asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
4689 4690 4691
	    : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
	      [fastop]"+S"(fop)
	    : "c"(ctxt->src2.val));
4692
	ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
4693 4694
	if (!fop) /* exception is returned in fop variable */
		return emulate_de(ctxt);
4695 4696
	return X86EMUL_CONTINUE;
}
4697

4698 4699
void init_decode_cache(struct x86_emulate_ctxt *ctxt)
{
B
Bandan Das 已提交
4700 4701
	memset(&ctxt->rip_relative, 0,
	       (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
4702 4703 4704 4705 4706 4707

	ctxt->io_read.pos = 0;
	ctxt->io_read.end = 0;
	ctxt->mem_read.end = 0;
}

4708
int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
4709
{
4710
	const struct x86_emulate_ops *ops = ctxt->ops;
4711
	int rc = X86EMUL_CONTINUE;
4712
	int saved_dst_type = ctxt->dst.type;
4713

4714
	ctxt->mem_read.pos = 0;
4715

4716 4717
	/* LOCK prefix is allowed only with some instructions */
	if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
4718
		rc = emulate_ud(ctxt);
4719 4720 4721
		goto done;
	}

4722
	if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
4723
		rc = emulate_ud(ctxt);
4724 4725 4726
		goto done;
	}

4727 4728 4729 4730 4731 4732 4733
	if (unlikely(ctxt->d &
		     (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
		if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
				(ctxt->d & Undefined)) {
			rc = emulate_ud(ctxt);
			goto done;
		}
A
Avi Kivity 已提交
4734

4735 4736 4737
		if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
		    || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
			rc = emulate_ud(ctxt);
A
Avi Kivity 已提交
4738
			goto done;
4739
		}
A
Avi Kivity 已提交
4740

4741 4742
		if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
			rc = emulate_nm(ctxt);
4743
			goto done;
4744
		}
4745

4746 4747 4748 4749 4750 4751 4752 4753 4754 4755 4756 4757 4758
		if (ctxt->d & Mmx) {
			rc = flush_pending_x87_faults(ctxt);
			if (rc != X86EMUL_CONTINUE)
				goto done;
			/*
			 * Now that we know the fpu is exception safe, we can fetch
			 * operands from it.
			 */
			fetch_possible_mmx_operand(ctxt, &ctxt->src);
			fetch_possible_mmx_operand(ctxt, &ctxt->src2);
			if (!(ctxt->d & Mov))
				fetch_possible_mmx_operand(ctxt, &ctxt->dst);
		}
4759

4760
		if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
4761 4762 4763 4764 4765
			rc = emulator_check_intercept(ctxt, ctxt->intercept,
						      X86_ICPT_PRE_EXCEPT);
			if (rc != X86EMUL_CONTINUE)
				goto done;
		}
4766

4767 4768
		/* Privileged instruction can be executed only in CPL=0 */
		if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
4769 4770 4771 4772
			if (ctxt->d & PrivUD)
				rc = emulate_ud(ctxt);
			else
				rc = emulate_gp(ctxt, 0);
4773
			goto done;
4774
		}
4775

4776 4777 4778
		/* Instruction can only be executed in protected mode */
		if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
			rc = emulate_ud(ctxt);
4779
			goto done;
4780
		}
4781

4782
		/* Do instruction specific permission checks */
4783
		if (ctxt->d & CheckPerm) {
4784 4785 4786 4787 4788
			rc = ctxt->check_perm(ctxt);
			if (rc != X86EMUL_CONTINUE)
				goto done;
		}

4789
		if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
4790 4791 4792 4793 4794 4795 4796 4797 4798 4799
			rc = emulator_check_intercept(ctxt, ctxt->intercept,
						      X86_ICPT_POST_EXCEPT);
			if (rc != X86EMUL_CONTINUE)
				goto done;
		}

		if (ctxt->rep_prefix && (ctxt->d & String)) {
			/* All REP prefixes have the same first termination condition */
			if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
				ctxt->eip = ctxt->_eip;
4800
				ctxt->eflags &= ~EFLG_RF;
4801 4802
				goto done;
			}
4803 4804 4805
		}
	}

4806 4807 4808
	if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
		rc = segmented_read(ctxt, ctxt->src.addr.mem,
				    ctxt->src.valptr, ctxt->src.bytes);
4809
		if (rc != X86EMUL_CONTINUE)
4810
			goto done;
4811
		ctxt->src.orig_val64 = ctxt->src.val64;
4812 4813
	}

4814 4815 4816
	if (ctxt->src2.type == OP_MEM) {
		rc = segmented_read(ctxt, ctxt->src2.addr.mem,
				    &ctxt->src2.val, ctxt->src2.bytes);
4817 4818 4819 4820
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

4821
	if ((ctxt->d & DstMask) == ImplicitOps)
4822 4823 4824
		goto special_insn;


4825
	if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
4826
		/* optimisation - avoid slow emulated read if Mov */
4827 4828
		rc = segmented_read(ctxt, ctxt->dst.addr.mem,
				   &ctxt->dst.val, ctxt->dst.bytes);
4829 4830
		if (rc != X86EMUL_CONTINUE)
			goto done;
4831
	}
4832
	ctxt->dst.orig_val = ctxt->dst.val;
4833

4834 4835
special_insn:

4836
	if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
4837
		rc = emulator_check_intercept(ctxt, ctxt->intercept,
4838
					      X86_ICPT_POST_MEMACCESS);
4839 4840 4841 4842
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

4843 4844 4845 4846
	if (ctxt->rep_prefix && (ctxt->d & String))
		ctxt->eflags |= EFLG_RF;
	else
		ctxt->eflags &= ~EFLG_RF;
4847

4848
	if (ctxt->execute) {
4849 4850 4851 4852 4853 4854 4855
		if (ctxt->d & Fastop) {
			void (*fop)(struct fastop *) = (void *)ctxt->execute;
			rc = fastop(ctxt, fop);
			if (rc != X86EMUL_CONTINUE)
				goto done;
			goto writeback;
		}
4856
		rc = ctxt->execute(ctxt);
4857 4858 4859 4860 4861
		if (rc != X86EMUL_CONTINUE)
			goto done;
		goto writeback;
	}

B
Borislav Petkov 已提交
4862
	if (ctxt->opcode_len == 2)
A
Avi Kivity 已提交
4863
		goto twobyte_insn;
4864 4865
	else if (ctxt->opcode_len == 3)
		goto threebyte_insn;
A
Avi Kivity 已提交
4866

4867
	switch (ctxt->b) {
A
Avi Kivity 已提交
4868
	case 0x63:		/* movsxd */
4869
		if (ctxt->mode != X86EMUL_MODE_PROT64)
A
Avi Kivity 已提交
4870
			goto cannot_emulate;
4871
		ctxt->dst.val = (s32) ctxt->src.val;
A
Avi Kivity 已提交
4872
		break;
4873
	case 0x70 ... 0x7f: /* jcc (short) */
4874
		if (test_cc(ctxt->b, ctxt->eflags))
4875
			rc = jmp_rel(ctxt, ctxt->src.val);
4876
		break;
N
Nitin A Kamble 已提交
4877
	case 0x8d: /* lea r16/r32, m */
4878
		ctxt->dst.val = ctxt->src.addr.mem.ea;
N
Nitin A Kamble 已提交
4879
		break;
4880
	case 0x90 ... 0x97: /* nop / xchg reg, rax */
4881
		if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
4882 4883 4884
			ctxt->dst.type = OP_NONE;
		else
			rc = em_xchg(ctxt);
4885
		break;
4886
	case 0x98: /* cbw/cwde/cdqe */
4887 4888 4889 4890
		switch (ctxt->op_bytes) {
		case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
		case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
		case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
4891 4892
		}
		break;
4893
	case 0xcc:		/* int3 */
4894 4895
		rc = emulate_int(ctxt, 3);
		break;
4896
	case 0xcd:		/* int n */
4897
		rc = emulate_int(ctxt, ctxt->src.val);
4898 4899
		break;
	case 0xce:		/* into */
4900 4901
		if (ctxt->eflags & EFLG_OF)
			rc = emulate_int(ctxt, 4);
4902
		break;
4903
	case 0xe9: /* jmp rel */
4904
	case 0xeb: /* jmp rel short */
4905
		rc = jmp_rel(ctxt, ctxt->src.val);
4906
		ctxt->dst.type = OP_NONE; /* Disable writeback. */
4907
		break;
4908
	case 0xf4:              /* hlt */
4909
		ctxt->ops->halt(ctxt);
4910
		break;
4911 4912 4913 4914 4915 4916 4917
	case 0xf5:	/* cmc */
		/* complement carry flag from eflags reg */
		ctxt->eflags ^= EFLG_CF;
		break;
	case 0xf8: /* clc */
		ctxt->eflags &= ~EFLG_CF;
		break;
4918 4919 4920
	case 0xf9: /* stc */
		ctxt->eflags |= EFLG_CF;
		break;
4921 4922 4923 4924 4925 4926
	case 0xfc: /* cld */
		ctxt->eflags &= ~EFLG_DF;
		break;
	case 0xfd: /* std */
		ctxt->eflags |= EFLG_DF;
		break;
4927 4928
	default:
		goto cannot_emulate;
A
Avi Kivity 已提交
4929
	}
4930

4931 4932 4933
	if (rc != X86EMUL_CONTINUE)
		goto done;

4934
writeback:
4935 4936 4937 4938 4939 4940
	if (ctxt->d & SrcWrite) {
		BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
		rc = writeback(ctxt, &ctxt->src);
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}
4941 4942 4943 4944 4945
	if (!(ctxt->d & NoWrite)) {
		rc = writeback(ctxt, &ctxt->dst);
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}
4946

4947 4948 4949 4950
	/*
	 * restore dst type in case the decoding will be reused
	 * (happens for string instruction )
	 */
4951
	ctxt->dst.type = saved_dst_type;
4952

4953
	if ((ctxt->d & SrcMask) == SrcSI)
4954
		string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
4955

4956
	if ((ctxt->d & DstMask) == DstDI)
4957
		string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
4958

4959
	if (ctxt->rep_prefix && (ctxt->d & String)) {
4960
		unsigned int count;
4961
		struct read_cache *r = &ctxt->io_read;
4962 4963 4964 4965 4966 4967
		if ((ctxt->d & SrcMask) == SrcSI)
			count = ctxt->src.count;
		else
			count = ctxt->dst.count;
		register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
				-count);
4968

4969 4970 4971 4972 4973
		if (!string_insn_completed(ctxt)) {
			/*
			 * Re-enter guest when pio read ahead buffer is empty
			 * or, if it is not used, after each 1024 iteration.
			 */
4974
			if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
4975 4976 4977 4978 4979 4980
			    (r->end == 0 || r->end != r->pos)) {
				/*
				 * Reset read cache. Usually happens before
				 * decode, but since instruction is restarted
				 * we have to do it here.
				 */
4981
				ctxt->mem_read.end = 0;
4982
				writeback_registers(ctxt);
4983 4984 4985
				return EMULATION_RESTART;
			}
			goto done; /* skip rip writeback */
4986
		}
4987
		ctxt->eflags &= ~EFLG_RF;
4988
	}
4989

4990
	ctxt->eip = ctxt->_eip;
4991 4992

done:
4993 4994
	if (rc == X86EMUL_PROPAGATE_FAULT) {
		WARN_ON(ctxt->exception.vector > 0x1f);
4995
		ctxt->have_exception = true;
4996
	}
4997 4998 4999
	if (rc == X86EMUL_INTERCEPTED)
		return EMULATION_INTERCEPTED;

5000 5001 5002
	if (rc == X86EMUL_CONTINUE)
		writeback_registers(ctxt);

5003
	return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
A
Avi Kivity 已提交
5004 5005

twobyte_insn:
5006
	switch (ctxt->b) {
5007
	case 0x09:		/* wbinvd */
5008
		(ctxt->ops->wbinvd)(ctxt);
5009 5010
		break;
	case 0x08:		/* invd */
5011 5012
	case 0x0d:		/* GrpP (prefetch) */
	case 0x18:		/* Grp16 (prefetch/nop) */
P
Paolo Bonzini 已提交
5013
	case 0x1f:		/* nop */
5014 5015
		break;
	case 0x20: /* mov cr, reg */
5016
		ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
5017
		break;
A
Avi Kivity 已提交
5018
	case 0x21: /* mov from dr to reg */
5019
		ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
A
Avi Kivity 已提交
5020 5021
		break;
	case 0x40 ... 0x4f:	/* cmov */
5022 5023 5024 5025
		if (test_cc(ctxt->b, ctxt->eflags))
			ctxt->dst.val = ctxt->src.val;
		else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
			 ctxt->op_bytes != 4)
5026
			ctxt->dst.type = OP_NONE; /* no writeback */
A
Avi Kivity 已提交
5027
		break;
5028
	case 0x80 ... 0x8f: /* jnz rel, etc*/
5029
		if (test_cc(ctxt->b, ctxt->eflags))
5030
			rc = jmp_rel(ctxt, ctxt->src.val);
5031
		break;
5032
	case 0x90 ... 0x9f:     /* setcc r/m8 */
5033
		ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
5034
		break;
A
Avi Kivity 已提交
5035
	case 0xb6 ... 0xb7:	/* movzx */
5036
		ctxt->dst.bytes = ctxt->op_bytes;
5037
		ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
5038
						       : (u16) ctxt->src.val;
A
Avi Kivity 已提交
5039 5040
		break;
	case 0xbe ... 0xbf:	/* movsx */
5041
		ctxt->dst.bytes = ctxt->op_bytes;
5042
		ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
5043
							(s16) ctxt->src.val;
A
Avi Kivity 已提交
5044
		break;
5045
	case 0xc3:		/* movnti */
5046
		ctxt->dst.bytes = ctxt->op_bytes;
5047 5048
		ctxt->dst.val = (ctxt->op_bytes == 8) ? (u64) ctxt->src.val :
							(u32) ctxt->src.val;
5049
		break;
5050 5051
	default:
		goto cannot_emulate;
A
Avi Kivity 已提交
5052
	}
5053

5054 5055
threebyte_insn:

5056 5057 5058
	if (rc != X86EMUL_CONTINUE)
		goto done;

A
Avi Kivity 已提交
5059 5060 5061
	goto writeback;

cannot_emulate:
5062
	return EMULATION_FAILED;
A
Avi Kivity 已提交
5063
}
5064 5065 5066 5067 5068 5069 5070 5071 5072 5073

void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
{
	invalidate_registers(ctxt);
}

void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
{
	writeback_registers(ctxt);
}