emulate.c 108.2 KB
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/******************************************************************************
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 * emulate.c
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 *
 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
 *
 * Copyright (c) 2005 Keir Fraser
 *
 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
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 * privileged instructions:
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 *
 * Copyright (C) 2006 Qumranet
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 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
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 *
 *   Avi Kivity <avi@qumranet.com>
 *   Yaniv Kamay <yaniv@qumranet.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
 */

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#include <linux/kvm_host.h>
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#include "kvm_cache_regs.h"
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#include <linux/module.h>
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#include <asm/kvm_emulate.h>
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#include "x86.h"
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#include "tss.h"
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/*
 * Operand types
 */
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#define OpNone             0ull
#define OpImplicit         1ull  /* No generic decode */
#define OpReg              2ull  /* Register */
#define OpMem              3ull  /* Memory */
#define OpAcc              4ull  /* Accumulator: AL/AX/EAX/RAX */
#define OpDI               5ull  /* ES:DI/EDI/RDI */
#define OpMem64            6ull  /* Memory, 64-bit */
#define OpImmUByte         7ull  /* Zero-extended 8-bit immediate */
#define OpDX               8ull  /* DX register */
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#define OpCL               9ull  /* CL register (for shifts) */
#define OpImmByte         10ull  /* 8-bit sign extended immediate */
#define OpOne             11ull  /* Implied 1 */
#define OpImm             12ull  /* Sign extended immediate */
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#define OpBits             4  /* Width of operand field */
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#define OpMask             ((1ull << OpBits) - 1)
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/*
 * Opcode effective-address decode tables.
 * Note that we only emulate instructions that have at least one memory
 * operand (excluding implicit stack references). We assume that stack
 * references and instruction fetches will never occur in special memory
 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
 * not be handled.
 */

/* Operand sizes: 8-bit operands or specified/overridden size. */
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#define ByteOp      (1<<0)	/* 8-bit operands. */
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/* Destination operand type. */
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#define DstShift    1
#define ImplicitOps (OpImplicit << DstShift)
#define DstReg      (OpReg << DstShift)
#define DstMem      (OpMem << DstShift)
#define DstAcc      (OpAcc << DstShift)
#define DstDI       (OpDI << DstShift)
#define DstMem64    (OpMem64 << DstShift)
#define DstImmUByte (OpImmUByte << DstShift)
#define DstDX       (OpDX << DstShift)
#define DstMask     (OpMask << DstShift)
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/* Source operand type. */
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#define SrcNone     (0<<5)	/* No source operand. */
#define SrcReg      (1<<5)	/* Register operand. */
#define SrcMem      (2<<5)	/* Memory operand. */
#define SrcMem16    (3<<5)	/* Memory operand (16-bit). */
#define SrcMem32    (4<<5)	/* Memory operand (32-bit). */
#define SrcImm      (5<<5)	/* Immediate operand. */
#define SrcImmByte  (6<<5)	/* 8-bit sign-extended immediate operand. */
#define SrcOne      (7<<5)	/* Implied '1' */
#define SrcImmUByte (8<<5)      /* 8-bit unsigned immediate operand. */
#define SrcImmU     (9<<5)      /* Immediate operand, unsigned */
#define SrcSI       (0xa<<5)	/* Source is in the DS:RSI */
#define SrcImmFAddr (0xb<<5)	/* Source is immediate far address */
#define SrcMemFAddr (0xc<<5)	/* Source is far address in memory */
#define SrcAcc      (0xd<<5)	/* Source Accumulator */
#define SrcImmU16   (0xe<<5)    /* Immediate operand, unsigned, 16 bits */
#define SrcDX       (0xf<<5)	/* Source is in DX register */
#define SrcMask     (0xf<<5)
#define BitOp       (1<<11)
#define MemAbs      (1<<12)      /* Memory operand is absolute displacement */
#define String      (1<<13)     /* String instruction (rep capable) */
#define Stack       (1<<14)     /* Stack instruction (push/pop) */
#define GroupMask   (7<<15)     /* Opcode uses one of the group mechanisms */
#define Group       (1<<15)     /* Bits 3:5 of modrm byte extend opcode */
#define GroupDual   (2<<15)     /* Alternate decoding of mod == 3 */
#define Prefix      (3<<15)     /* Instruction varies with 66/f2/f3 prefix */
#define RMExt       (4<<15)     /* Opcode extension in ModRM r/m if mod == 3 */
#define Sse         (1<<18)     /* SSE Vector instruction */
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/* Generic ModRM decode. */
#define ModRM       (1<<19)
/* Destination is only written; never read. */
#define Mov         (1<<20)
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/* Misc flags */
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#define Prot        (1<<21) /* instruction generates #UD if not in prot-mode */
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#define VendorSpecific (1<<22) /* Vendor specific instruction */
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#define NoAccess    (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
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#define Op3264      (1<<24) /* Operand is 64b in long mode, 32b otherwise */
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#define Undefined   (1<<25) /* No Such Instruction */
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#define Lock        (1<<26) /* lock prefix is allowed for the instruction */
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#define Priv        (1<<27) /* instruction generates #GP if current CPL != 0 */
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#define No64	    (1<<28)
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/* Source 2 operand type */
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#define Src2Shift   (29)
#define Src2None    (OpNone << Src2Shift)
#define Src2CL      (OpCL << Src2Shift)
#define Src2ImmByte (OpImmByte << Src2Shift)
#define Src2One     (OpOne << Src2Shift)
#define Src2Imm     (OpImm << Src2Shift)
#define Src2Mask    (OpMask << Src2Shift)
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#define X2(x...) x, x
#define X3(x...) X2(x), x
#define X4(x...) X2(x), X2(x)
#define X5(x...) X4(x), x
#define X6(x...) X4(x), X2(x)
#define X7(x...) X4(x), X3(x)
#define X8(x...) X4(x), X4(x)
#define X16(x...) X8(x), X8(x)
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struct opcode {
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	u64 flags : 56;
	u64 intercept : 8;
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	union {
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		int (*execute)(struct x86_emulate_ctxt *ctxt);
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		struct opcode *group;
		struct group_dual *gdual;
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		struct gprefix *gprefix;
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	} u;
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	int (*check_perm)(struct x86_emulate_ctxt *ctxt);
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};

struct group_dual {
	struct opcode mod012[8];
	struct opcode mod3[8];
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};

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struct gprefix {
	struct opcode pfx_no;
	struct opcode pfx_66;
	struct opcode pfx_f2;
	struct opcode pfx_f3;
};

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/* EFLAGS bit definitions. */
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#define EFLG_ID (1<<21)
#define EFLG_VIP (1<<20)
#define EFLG_VIF (1<<19)
#define EFLG_AC (1<<18)
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#define EFLG_VM (1<<17)
#define EFLG_RF (1<<16)
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#define EFLG_IOPL (3<<12)
#define EFLG_NT (1<<14)
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#define EFLG_OF (1<<11)
#define EFLG_DF (1<<10)
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#define EFLG_IF (1<<9)
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#define EFLG_TF (1<<8)
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#define EFLG_SF (1<<7)
#define EFLG_ZF (1<<6)
#define EFLG_AF (1<<4)
#define EFLG_PF (1<<2)
#define EFLG_CF (1<<0)

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#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
#define EFLG_RESERVED_ONE_MASK 2

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/*
 * Instruction emulation:
 * Most instructions are emulated directly via a fragment of inline assembly
 * code. This allows us to save/restore EFLAGS and thus very easily pick up
 * any modified flags.
 */

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#if defined(CONFIG_X86_64)
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#define _LO32 "k"		/* force 32-bit operand */
#define _STK  "%%rsp"		/* stack pointer */
#elif defined(__i386__)
#define _LO32 ""		/* force 32-bit operand */
#define _STK  "%%esp"		/* stack pointer */
#endif

/*
 * These EFLAGS bits are restored from saved value during emulation, and
 * any changes are written back to the saved value after emulation.
 */
#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)

/* Before executing instruction: restore necessary bits in EFLAGS. */
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#define _PRE_EFLAGS(_sav, _msk, _tmp)					\
	/* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
	"movl %"_sav",%"_LO32 _tmp"; "                                  \
	"push %"_tmp"; "                                                \
	"push %"_tmp"; "                                                \
	"movl %"_msk",%"_LO32 _tmp"; "                                  \
	"andl %"_LO32 _tmp",("_STK"); "                                 \
	"pushf; "                                                       \
	"notl %"_LO32 _tmp"; "                                          \
	"andl %"_LO32 _tmp",("_STK"); "                                 \
	"andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); "	\
	"pop  %"_tmp"; "                                                \
	"orl  %"_LO32 _tmp",("_STK"); "                                 \
	"popf; "                                                        \
	"pop  %"_sav"; "
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/* After executing instruction: write-back necessary bits in EFLAGS. */
#define _POST_EFLAGS(_sav, _msk, _tmp) \
	/* _sav |= EFLAGS & _msk; */		\
	"pushf; "				\
	"pop  %"_tmp"; "			\
	"andl %"_msk",%"_LO32 _tmp"; "		\
	"orl  %"_LO32 _tmp",%"_sav"; "

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#ifdef CONFIG_X86_64
#define ON64(x) x
#else
#define ON64(x)
#endif

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#define ____emulate_2op(ctxt, _op, _x, _y, _suffix, _dsttype)	\
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	do {								\
		__asm__ __volatile__ (					\
			_PRE_EFLAGS("0", "4", "2")			\
			_op _suffix " %"_x"3,%1; "			\
			_POST_EFLAGS("0", "4", "2")			\
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			: "=m" ((ctxt)->eflags),			\
			  "+q" (*(_dsttype*)&(ctxt)->dst.val),		\
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			  "=&r" (_tmp)					\
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			: _y ((ctxt)->src.val), "i" (EFLAGS_MASK));	\
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	} while (0)
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/* Raw emulation: instruction has two explicit operands. */
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#define __emulate_2op_nobyte(ctxt,_op,_wx,_wy,_lx,_ly,_qx,_qy)		\
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	do {								\
		unsigned long _tmp;					\
									\
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		switch ((ctxt)->dst.bytes) {				\
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		case 2:							\
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			____emulate_2op(ctxt,_op,_wx,_wy,"w",u16);	\
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			break;						\
		case 4:							\
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			____emulate_2op(ctxt,_op,_lx,_ly,"l",u32);	\
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			break;						\
		case 8:							\
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			ON64(____emulate_2op(ctxt,_op,_qx,_qy,"q",u64)); \
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			break;						\
		}							\
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	} while (0)

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#define __emulate_2op(ctxt,_op,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy)		     \
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	do {								     \
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		unsigned long _tmp;					     \
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		switch ((ctxt)->dst.bytes) {				     \
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		case 1:							     \
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			____emulate_2op(ctxt,_op,_bx,_by,"b",u8);	     \
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			break;						     \
		default:						     \
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			__emulate_2op_nobyte(ctxt, _op,			     \
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					     _wx, _wy, _lx, _ly, _qx, _qy);  \
			break;						     \
		}							     \
	} while (0)

/* Source operand is byte-sized and may be restricted to just %cl. */
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#define emulate_2op_SrcB(ctxt, _op)					\
	__emulate_2op(ctxt, _op, "b", "c", "b", "c", "b", "c", "b", "c")
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/* Source operand is byte, word, long or quad sized. */
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#define emulate_2op_SrcV(ctxt, _op)					\
	__emulate_2op(ctxt, _op, "b", "q", "w", "r", _LO32, "r", "", "r")
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/* Source operand is word, long or quad sized. */
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#define emulate_2op_SrcV_nobyte(ctxt, _op)				\
	__emulate_2op_nobyte(ctxt, _op, "w", "r", _LO32, "r", "", "r")
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/* Instruction has three operands and one operand is stored in ECX register */
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#define __emulate_2op_cl(ctxt, _op, _suffix, _type)		\
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	do {								\
		unsigned long _tmp;					\
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		_type _clv  = (ctxt)->src2.val;				\
		_type _srcv = (ctxt)->src.val;				\
		_type _dstv = (ctxt)->dst.val;				\
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									\
		__asm__ __volatile__ (					\
			_PRE_EFLAGS("0", "5", "2")			\
			_op _suffix " %4,%1 \n"				\
			_POST_EFLAGS("0", "5", "2")			\
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			: "=m" ((ctxt)->eflags), "+r" (_dstv), "=&r" (_tmp) \
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			: "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK)	\
			);						\
									\
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		(ctxt)->src2.val  = (unsigned long) _clv;		\
		(ctxt)->src2.val = (unsigned long) _srcv;		\
		(ctxt)->dst.val = (unsigned long) _dstv;		\
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	} while (0)

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#define emulate_2op_cl(ctxt, _op)					\
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	do {								\
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		switch ((ctxt)->dst.bytes) {				\
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		case 2:							\
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			__emulate_2op_cl(ctxt, _op, "w", u16);		\
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			break;						\
		case 4:							\
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			__emulate_2op_cl(ctxt, _op, "l", u32);		\
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			break;						\
		case 8:							\
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			ON64(__emulate_2op_cl(ctxt, _op, "q", ulong));	\
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			break;						\
		}							\
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	} while (0)

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#define __emulate_1op(ctxt, _op, _suffix)				\
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	do {								\
		unsigned long _tmp;					\
									\
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		__asm__ __volatile__ (					\
			_PRE_EFLAGS("0", "3", "2")			\
			_op _suffix " %1; "				\
			_POST_EFLAGS("0", "3", "2")			\
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			: "=m" ((ctxt)->eflags), "+m" ((ctxt)->dst.val), \
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			  "=&r" (_tmp)					\
			: "i" (EFLAGS_MASK));				\
	} while (0)

/* Instruction has only one explicit operand (no source operand). */
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#define emulate_1op(ctxt, _op)						\
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	do {								\
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		switch ((ctxt)->dst.bytes) {				\
		case 1:	__emulate_1op(ctxt, _op, "b"); break;		\
		case 2:	__emulate_1op(ctxt, _op, "w"); break;		\
		case 4:	__emulate_1op(ctxt, _op, "l"); break;		\
		case 8:	ON64(__emulate_1op(ctxt, _op, "q")); break;	\
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		}							\
	} while (0)

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#define __emulate_1op_rax_rdx(ctxt, _op, _suffix, _ex)			\
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	do {								\
		unsigned long _tmp;					\
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		ulong *rax = &(ctxt)->regs[VCPU_REGS_RAX];		\
		ulong *rdx = &(ctxt)->regs[VCPU_REGS_RDX];		\
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									\
		__asm__ __volatile__ (					\
			_PRE_EFLAGS("0", "5", "1")			\
			"1: \n\t"					\
			_op _suffix " %6; "				\
			"2: \n\t"					\
			_POST_EFLAGS("0", "5", "1")			\
			".pushsection .fixup,\"ax\" \n\t"		\
			"3: movb $1, %4 \n\t"				\
			"jmp 2b \n\t"					\
			".popsection \n\t"				\
			_ASM_EXTABLE(1b, 3b)				\
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			: "=m" ((ctxt)->eflags), "=&r" (_tmp),		\
			  "+a" (*rax), "+d" (*rdx), "+qm"(_ex)		\
			: "i" (EFLAGS_MASK), "m" ((ctxt)->src.val),	\
			  "a" (*rax), "d" (*rdx));			\
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	} while (0)

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/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
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#define emulate_1op_rax_rdx(ctxt, _op, _ex)	\
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	do {								\
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		switch((ctxt)->src.bytes) {				\
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		case 1:							\
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			__emulate_1op_rax_rdx(ctxt, _op, "b", _ex);	\
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			break;						\
		case 2:							\
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			__emulate_1op_rax_rdx(ctxt, _op, "w", _ex);	\
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			break;						\
		case 4:							\
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			__emulate_1op_rax_rdx(ctxt, _op, "l", _ex);	\
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			break;						\
		case 8: ON64(						\
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			__emulate_1op_rax_rdx(ctxt, _op, "q", _ex));	\
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			break;						\
		}							\
	} while (0)

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static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
				    enum x86_intercept intercept,
				    enum x86_intercept_stage stage)
{
	struct x86_instruction_info info = {
		.intercept  = intercept,
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		.rep_prefix = ctxt->rep_prefix,
		.modrm_mod  = ctxt->modrm_mod,
		.modrm_reg  = ctxt->modrm_reg,
		.modrm_rm   = ctxt->modrm_rm,
		.src_val    = ctxt->src.val64,
		.src_bytes  = ctxt->src.bytes,
		.dst_bytes  = ctxt->dst.bytes,
		.ad_bytes   = ctxt->ad_bytes,
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		.next_rip   = ctxt->eip,
	};

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	return ctxt->ops->intercept(ctxt, &info, stage);
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}

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static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
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{
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	return (1UL << (ctxt->ad_bytes << 3)) - 1;
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}

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/* Access/update address held in a register, based on addressing mode. */
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static inline unsigned long
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address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
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{
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	if (ctxt->ad_bytes == sizeof(unsigned long))
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		return reg;
	else
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		return reg & ad_mask(ctxt);
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}

static inline unsigned long
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register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
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{
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	return address_mask(ctxt, reg);
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}

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static inline void
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register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
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{
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	if (ctxt->ad_bytes == sizeof(unsigned long))
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		*reg += inc;
	else
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		*reg = (*reg & ~ad_mask(ctxt)) | ((*reg + inc) & ad_mask(ctxt));
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}
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static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
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{
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	register_address_increment(ctxt, &ctxt->_eip, rel);
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}
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static u32 desc_limit_scaled(struct desc_struct *desc)
{
	u32 limit = get_desc_limit(desc);

	return desc->g ? (limit << 12) | 0xfff : limit;
}

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static void set_seg_override(struct x86_emulate_ctxt *ctxt, int seg)
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{
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	ctxt->has_seg_override = true;
	ctxt->seg_override = seg;
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}

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static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
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{
	if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
		return 0;

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	return ctxt->ops->get_cached_segment_base(ctxt, seg);
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}

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static unsigned seg_override(struct x86_emulate_ctxt *ctxt)
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{
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	if (!ctxt->has_seg_override)
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		return 0;

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	return ctxt->seg_override;
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}

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static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
			     u32 error, bool valid)
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{
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	ctxt->exception.vector = vec;
	ctxt->exception.error_code = error;
	ctxt->exception.error_code_valid = valid;
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	return X86EMUL_PROPAGATE_FAULT;
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}

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static int emulate_db(struct x86_emulate_ctxt *ctxt)
{
	return emulate_exception(ctxt, DB_VECTOR, 0, false);
}

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static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
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{
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	return emulate_exception(ctxt, GP_VECTOR, err, true);
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}

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static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
{
	return emulate_exception(ctxt, SS_VECTOR, err, true);
}

497
static int emulate_ud(struct x86_emulate_ctxt *ctxt)
498
{
499
	return emulate_exception(ctxt, UD_VECTOR, 0, false);
500 501
}

502
static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
503
{
504
	return emulate_exception(ctxt, TS_VECTOR, err, true);
505 506
}

507 508
static int emulate_de(struct x86_emulate_ctxt *ctxt)
{
509
	return emulate_exception(ctxt, DE_VECTOR, 0, false);
510 511
}

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512 513 514 515 516
static int emulate_nm(struct x86_emulate_ctxt *ctxt)
{
	return emulate_exception(ctxt, NM_VECTOR, 0, false);
}

517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536
static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
{
	u16 selector;
	struct desc_struct desc;

	ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
	return selector;
}

static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
				 unsigned seg)
{
	u16 dummy;
	u32 base3;
	struct desc_struct desc;

	ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
	ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
}

537
static int __linearize(struct x86_emulate_ctxt *ctxt,
538
		     struct segmented_address addr,
539
		     unsigned size, bool write, bool fetch,
540 541
		     ulong *linear)
{
542 543
	struct desc_struct desc;
	bool usable;
544
	ulong la;
545
	u32 lim;
546
	u16 sel;
547
	unsigned cpl, rpl;
548

549
	la = seg_base(ctxt, addr.seg) + addr.ea;
550 551 552 553 554 555 556 557
	switch (ctxt->mode) {
	case X86EMUL_MODE_REAL:
		break;
	case X86EMUL_MODE_PROT64:
		if (((signed long)la << 16) >> 16 != la)
			return emulate_gp(ctxt, 0);
		break;
	default:
558 559
		usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
						addr.seg);
560 561 562 563 564 565
		if (!usable)
			goto bad;
		/* code segment or read-only data segment */
		if (((desc.type & 8) || !(desc.type & 2)) && write)
			goto bad;
		/* unreadable code segment */
566
		if (!fetch && (desc.type & 8) && !(desc.type & 2))
567 568 569 570 571 572 573 574 575 576 577 578 579 580
			goto bad;
		lim = desc_limit_scaled(&desc);
		if ((desc.type & 8) || !(desc.type & 4)) {
			/* expand-up segment */
			if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
				goto bad;
		} else {
			/* exapand-down segment */
			if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
				goto bad;
			lim = desc.d ? 0xffffffff : 0xffff;
			if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
				goto bad;
		}
581
		cpl = ctxt->ops->cpl(ctxt);
582
		rpl = sel & 3;
583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598
		cpl = max(cpl, rpl);
		if (!(desc.type & 8)) {
			/* data segment */
			if (cpl > desc.dpl)
				goto bad;
		} else if ((desc.type & 8) && !(desc.type & 4)) {
			/* nonconforming code segment */
			if (cpl != desc.dpl)
				goto bad;
		} else if ((desc.type & 8) && (desc.type & 4)) {
			/* conforming code segment */
			if (cpl < desc.dpl)
				goto bad;
		}
		break;
	}
599
	if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
600 601 602
		la &= (u32)-1;
	*linear = la;
	return X86EMUL_CONTINUE;
603 604 605 606 607
bad:
	if (addr.seg == VCPU_SREG_SS)
		return emulate_ss(ctxt, addr.seg);
	else
		return emulate_gp(ctxt, addr.seg);
608 609
}

610 611 612 613 614 615 616 617 618
static int linearize(struct x86_emulate_ctxt *ctxt,
		     struct segmented_address addr,
		     unsigned size, bool write,
		     ulong *linear)
{
	return __linearize(ctxt, addr, size, write, false, linear);
}


619 620 621 622 623
static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
			      struct segmented_address addr,
			      void *data,
			      unsigned size)
{
624 625 626
	int rc;
	ulong linear;

627
	rc = linearize(ctxt, addr, size, false, &linear);
628 629
	if (rc != X86EMUL_CONTINUE)
		return rc;
630
	return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
631 632
}

633 634 635 636 637 638 639 640
/*
 * Fetch the next byte of the instruction being emulated which is pointed to
 * by ctxt->_eip, then increment ctxt->_eip.
 *
 * Also prefetch the remaining bytes of the instruction without crossing page
 * boundary if they are not in fetch_cache yet.
 */
static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt, u8 *dest)
641
{
642
	struct fetch_cache *fc = &ctxt->fetch;
643
	int rc;
644
	int size, cur_size;
645

646
	if (ctxt->_eip == fc->end) {
647
		unsigned long linear;
648 649
		struct segmented_address addr = { .seg = VCPU_SREG_CS,
						  .ea  = ctxt->_eip };
650
		cur_size = fc->end - fc->start;
651 652
		size = min(15UL - cur_size,
			   PAGE_SIZE - offset_in_page(ctxt->_eip));
653
		rc = __linearize(ctxt, addr, size, false, true, &linear);
654
		if (unlikely(rc != X86EMUL_CONTINUE))
655
			return rc;
656 657
		rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
				      size, &ctxt->exception);
658
		if (unlikely(rc != X86EMUL_CONTINUE))
659
			return rc;
660
		fc->end += size;
661
	}
662 663
	*dest = fc->data[ctxt->_eip - fc->start];
	ctxt->_eip++;
664
	return X86EMUL_CONTINUE;
665 666 667
}

static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
668
			 void *dest, unsigned size)
669
{
670
	int rc;
671

672
	/* x86 instructions are limited to 15 bytes. */
673
	if (unlikely(ctxt->_eip + size - ctxt->eip > 15))
674
		return X86EMUL_UNHANDLEABLE;
675
	while (size--) {
676
		rc = do_insn_fetch_byte(ctxt, dest++);
677
		if (rc != X86EMUL_CONTINUE)
678 679
			return rc;
	}
680
	return X86EMUL_CONTINUE;
681 682
}

683
/* Fetch next part of the instruction being emulated. */
684
#define insn_fetch(_type, _ctxt)					\
685
({	unsigned long _x;						\
686
	rc = do_insn_fetch(_ctxt, &_x, sizeof(_type));			\
687 688 689 690 691
	if (rc != X86EMUL_CONTINUE)					\
		goto done;						\
	(_type)_x;							\
})

692 693
#define insn_fetch_arr(_arr, _size, _ctxt)				\
({	rc = do_insn_fetch(_ctxt, _arr, (_size));			\
694 695 696 697
	if (rc != X86EMUL_CONTINUE)					\
		goto done;						\
})

698 699 700 701 702 703 704
/*
 * Given the 'reg' portion of a ModRM byte, and a register block, return a
 * pointer into the block that addresses the relevant register.
 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
 */
static void *decode_register(u8 modrm_reg, unsigned long *regs,
			     int highbyte_regs)
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{
	void *p;

	p = &regs[modrm_reg];
	if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
		p = (unsigned char *)&regs[modrm_reg & 3] + 1;
	return p;
}

static int read_descriptor(struct x86_emulate_ctxt *ctxt,
715
			   struct segmented_address addr,
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716 717 718 719 720 721 722
			   u16 *size, unsigned long *address, int op_bytes)
{
	int rc;

	if (op_bytes == 2)
		op_bytes = 3;
	*address = 0;
723
	rc = segmented_read_std(ctxt, addr, size, 2);
724
	if (rc != X86EMUL_CONTINUE)
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725
		return rc;
726
	addr.ea += 2;
727
	rc = segmented_read_std(ctxt, addr, address, op_bytes);
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728 729 730
	return rc;
}

731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765
static int test_cc(unsigned int condition, unsigned int flags)
{
	int rc = 0;

	switch ((condition & 15) >> 1) {
	case 0: /* o */
		rc |= (flags & EFLG_OF);
		break;
	case 1: /* b/c/nae */
		rc |= (flags & EFLG_CF);
		break;
	case 2: /* z/e */
		rc |= (flags & EFLG_ZF);
		break;
	case 3: /* be/na */
		rc |= (flags & (EFLG_CF|EFLG_ZF));
		break;
	case 4: /* s */
		rc |= (flags & EFLG_SF);
		break;
	case 5: /* p/pe */
		rc |= (flags & EFLG_PF);
		break;
	case 7: /* le/ng */
		rc |= (flags & EFLG_ZF);
		/* fall through */
	case 6: /* l/nge */
		rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
		break;
	}

	/* Odd condition identifiers (lsb == 1) have inverted sense. */
	return (!!rc ^ (condition & 1));
}

766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783
static void fetch_register_operand(struct operand *op)
{
	switch (op->bytes) {
	case 1:
		op->val = *(u8 *)op->addr.reg;
		break;
	case 2:
		op->val = *(u16 *)op->addr.reg;
		break;
	case 4:
		op->val = *(u32 *)op->addr.reg;
		break;
	case 8:
		op->val = *(u64 *)op->addr.reg;
		break;
	}
}

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784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840
static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
{
	ctxt->ops->get_fpu(ctxt);
	switch (reg) {
	case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
	case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
	case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
	case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
	case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
	case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
	case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
	case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
#ifdef CONFIG_X86_64
	case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
	case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
	case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
	case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
	case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
	case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
	case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
	case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
#endif
	default: BUG();
	}
	ctxt->ops->put_fpu(ctxt);
}

static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
			  int reg)
{
	ctxt->ops->get_fpu(ctxt);
	switch (reg) {
	case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
	case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
	case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
	case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
	case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
	case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
	case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
	case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
#ifdef CONFIG_X86_64
	case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
	case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
	case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
	case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
	case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
	case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
	case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
	case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
#endif
	default: BUG();
	}
	ctxt->ops->put_fpu(ctxt);
}

static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
				    struct operand *op,
841 842
				    int inhibit_bytereg)
{
843 844
	unsigned reg = ctxt->modrm_reg;
	int highbyte_regs = ctxt->rex_prefix == 0;
845

846 847
	if (!(ctxt->d & ModRM))
		reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
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Avi Kivity 已提交
848

849
	if (ctxt->d & Sse) {
A
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850 851 852 853 854 855 856
		op->type = OP_XMM;
		op->bytes = 16;
		op->addr.xmm = reg;
		read_sse_reg(ctxt, &op->vec_val, reg);
		return;
	}

857
	op->type = OP_REG;
858 859
	if ((ctxt->d & ByteOp) && !inhibit_bytereg) {
		op->addr.reg = decode_register(reg, ctxt->regs, highbyte_regs);
860 861
		op->bytes = 1;
	} else {
862 863
		op->addr.reg = decode_register(reg, ctxt->regs, 0);
		op->bytes = ctxt->op_bytes;
864
	}
865
	fetch_register_operand(op);
866 867 868
	op->orig_val = op->val;
}

869
static int decode_modrm(struct x86_emulate_ctxt *ctxt,
870
			struct operand *op)
871 872
{
	u8 sib;
873
	int index_reg = 0, base_reg = 0, scale;
874
	int rc = X86EMUL_CONTINUE;
875
	ulong modrm_ea = 0;
876

877 878 879 880
	if (ctxt->rex_prefix) {
		ctxt->modrm_reg = (ctxt->rex_prefix & 4) << 1;	/* REX.R */
		index_reg = (ctxt->rex_prefix & 2) << 2; /* REX.X */
		ctxt->modrm_rm = base_reg = (ctxt->rex_prefix & 1) << 3; /* REG.B */
881 882
	}

883
	ctxt->modrm = insn_fetch(u8, ctxt);
884 885 886 887
	ctxt->modrm_mod |= (ctxt->modrm & 0xc0) >> 6;
	ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
	ctxt->modrm_rm |= (ctxt->modrm & 0x07);
	ctxt->modrm_seg = VCPU_SREG_DS;
888

889
	if (ctxt->modrm_mod == 3) {
890
		op->type = OP_REG;
891 892 893 894
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		op->addr.reg = decode_register(ctxt->modrm_rm,
					       ctxt->regs, ctxt->d & ByteOp);
		if (ctxt->d & Sse) {
A
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895 896
			op->type = OP_XMM;
			op->bytes = 16;
897 898
			op->addr.xmm = ctxt->modrm_rm;
			read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
A
Avi Kivity 已提交
899 900
			return rc;
		}
901
		fetch_register_operand(op);
902 903 904
		return rc;
	}

905 906
	op->type = OP_MEM;

907 908 909 910 911
	if (ctxt->ad_bytes == 2) {
		unsigned bx = ctxt->regs[VCPU_REGS_RBX];
		unsigned bp = ctxt->regs[VCPU_REGS_RBP];
		unsigned si = ctxt->regs[VCPU_REGS_RSI];
		unsigned di = ctxt->regs[VCPU_REGS_RDI];
912 913

		/* 16-bit ModR/M decode. */
914
		switch (ctxt->modrm_mod) {
915
		case 0:
916
			if (ctxt->modrm_rm == 6)
917
				modrm_ea += insn_fetch(u16, ctxt);
918 919
			break;
		case 1:
920
			modrm_ea += insn_fetch(s8, ctxt);
921 922
			break;
		case 2:
923
			modrm_ea += insn_fetch(u16, ctxt);
924 925
			break;
		}
926
		switch (ctxt->modrm_rm) {
927
		case 0:
928
			modrm_ea += bx + si;
929 930
			break;
		case 1:
931
			modrm_ea += bx + di;
932 933
			break;
		case 2:
934
			modrm_ea += bp + si;
935 936
			break;
		case 3:
937
			modrm_ea += bp + di;
938 939
			break;
		case 4:
940
			modrm_ea += si;
941 942
			break;
		case 5:
943
			modrm_ea += di;
944 945
			break;
		case 6:
946
			if (ctxt->modrm_mod != 0)
947
				modrm_ea += bp;
948 949
			break;
		case 7:
950
			modrm_ea += bx;
951 952
			break;
		}
953 954 955
		if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
		    (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
			ctxt->modrm_seg = VCPU_SREG_SS;
956
		modrm_ea = (u16)modrm_ea;
957 958
	} else {
		/* 32/64-bit ModR/M decode. */
959
		if ((ctxt->modrm_rm & 7) == 4) {
960
			sib = insn_fetch(u8, ctxt);
961 962 963 964
			index_reg |= (sib >> 3) & 7;
			base_reg |= sib & 7;
			scale = sib >> 6;

965
			if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
966
				modrm_ea += insn_fetch(s32, ctxt);
967
			else
968
				modrm_ea += ctxt->regs[base_reg];
969
			if (index_reg != 4)
970 971
				modrm_ea += ctxt->regs[index_reg] << scale;
		} else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
972
			if (ctxt->mode == X86EMUL_MODE_PROT64)
973
				ctxt->rip_relative = 1;
974
		} else
975 976
			modrm_ea += ctxt->regs[ctxt->modrm_rm];
		switch (ctxt->modrm_mod) {
977
		case 0:
978
			if (ctxt->modrm_rm == 5)
979
				modrm_ea += insn_fetch(s32, ctxt);
980 981
			break;
		case 1:
982
			modrm_ea += insn_fetch(s8, ctxt);
983 984
			break;
		case 2:
985
			modrm_ea += insn_fetch(s32, ctxt);
986 987 988
			break;
		}
	}
989
	op->addr.mem.ea = modrm_ea;
990 991 992 993 994
done:
	return rc;
}

static int decode_abs(struct x86_emulate_ctxt *ctxt,
995
		      struct operand *op)
996
{
997
	int rc = X86EMUL_CONTINUE;
998

999
	op->type = OP_MEM;
1000
	switch (ctxt->ad_bytes) {
1001
	case 2:
1002
		op->addr.mem.ea = insn_fetch(u16, ctxt);
1003 1004
		break;
	case 4:
1005
		op->addr.mem.ea = insn_fetch(u32, ctxt);
1006 1007
		break;
	case 8:
1008
		op->addr.mem.ea = insn_fetch(u64, ctxt);
1009 1010 1011 1012 1013 1014
		break;
	}
done:
	return rc;
}

1015
static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
1016
{
1017
	long sv = 0, mask;
1018

1019 1020
	if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
		mask = ~(ctxt->dst.bytes * 8 - 1);
1021

1022 1023 1024 1025
		if (ctxt->src.bytes == 2)
			sv = (s16)ctxt->src.val & (s16)mask;
		else if (ctxt->src.bytes == 4)
			sv = (s32)ctxt->src.val & (s32)mask;
1026

1027
		ctxt->dst.addr.mem.ea += (sv >> 3);
1028
	}
1029 1030

	/* only subword offset */
1031
	ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
1032 1033
}

1034 1035
static int read_emulated(struct x86_emulate_ctxt *ctxt,
			 unsigned long addr, void *dest, unsigned size)
A
Avi Kivity 已提交
1036
{
1037
	int rc;
1038
	struct read_cache *mc = &ctxt->mem_read;
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Avi Kivity 已提交
1039

1040 1041 1042 1043 1044
	while (size) {
		int n = min(size, 8u);
		size -= n;
		if (mc->pos < mc->end)
			goto read_cached;
1045

1046 1047
		rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
					      &ctxt->exception);
1048 1049 1050
		if (rc != X86EMUL_CONTINUE)
			return rc;
		mc->end += n;
A
Avi Kivity 已提交
1051

1052 1053 1054 1055 1056
	read_cached:
		memcpy(dest, mc->data + mc->pos, n);
		mc->pos += n;
		dest += n;
		addr += n;
A
Avi Kivity 已提交
1057
	}
1058 1059
	return X86EMUL_CONTINUE;
}
A
Avi Kivity 已提交
1060

1061 1062 1063 1064 1065
static int segmented_read(struct x86_emulate_ctxt *ctxt,
			  struct segmented_address addr,
			  void *data,
			  unsigned size)
{
1066 1067 1068
	int rc;
	ulong linear;

1069
	rc = linearize(ctxt, addr, size, false, &linear);
1070 1071
	if (rc != X86EMUL_CONTINUE)
		return rc;
1072
	return read_emulated(ctxt, linear, data, size);
1073 1074 1075 1076 1077 1078 1079
}

static int segmented_write(struct x86_emulate_ctxt *ctxt,
			   struct segmented_address addr,
			   const void *data,
			   unsigned size)
{
1080 1081 1082
	int rc;
	ulong linear;

1083
	rc = linearize(ctxt, addr, size, true, &linear);
1084 1085
	if (rc != X86EMUL_CONTINUE)
		return rc;
1086 1087
	return ctxt->ops->write_emulated(ctxt, linear, data, size,
					 &ctxt->exception);
1088 1089 1090 1091 1092 1093 1094
}

static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
			     struct segmented_address addr,
			     const void *orig_data, const void *data,
			     unsigned size)
{
1095 1096 1097
	int rc;
	ulong linear;

1098
	rc = linearize(ctxt, addr, size, true, &linear);
1099 1100
	if (rc != X86EMUL_CONTINUE)
		return rc;
1101 1102
	return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
					   size, &ctxt->exception);
1103 1104
}

1105 1106 1107 1108
static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
			   unsigned int size, unsigned short port,
			   void *dest)
{
1109
	struct read_cache *rc = &ctxt->io_read;
1110

1111 1112
	if (rc->pos == rc->end) { /* refill pio read ahead */
		unsigned int in_page, n;
1113 1114
		unsigned int count = ctxt->rep_prefix ?
			address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) : 1;
1115
		in_page = (ctxt->eflags & EFLG_DF) ?
1116 1117
			offset_in_page(ctxt->regs[VCPU_REGS_RDI]) :
			PAGE_SIZE - offset_in_page(ctxt->regs[VCPU_REGS_RDI]);
1118 1119 1120 1121 1122
		n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
			count);
		if (n == 0)
			n = 1;
		rc->pos = rc->end = 0;
1123
		if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
1124 1125
			return 0;
		rc->end = n * size;
A
Avi Kivity 已提交
1126 1127
	}

1128 1129 1130 1131
	memcpy(dest, rc->data + rc->pos, size);
	rc->pos += size;
	return 1;
}
A
Avi Kivity 已提交
1132

1133 1134 1135
static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
				     u16 selector, struct desc_ptr *dt)
{
1136 1137
	struct x86_emulate_ops *ops = ctxt->ops;

1138 1139
	if (selector & 1 << 2) {
		struct desc_struct desc;
1140 1141
		u16 sel;

1142
		memset (dt, 0, sizeof *dt);
1143
		if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
1144
			return;
1145

1146 1147 1148
		dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
		dt->address = get_desc_base(&desc);
	} else
1149
		ops->get_gdt(ctxt, dt);
1150
}
1151

1152 1153 1154 1155 1156 1157 1158
/* allowed just for 8 bytes segments */
static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				   u16 selector, struct desc_struct *desc)
{
	struct desc_ptr dt;
	u16 index = selector >> 3;
	ulong addr;
1159

1160
	get_descriptor_table_ptr(ctxt, selector, &dt);
1161

1162 1163
	if (dt.size < index * 8 + 7)
		return emulate_gp(ctxt, selector & 0xfffc);
1164

1165 1166 1167
	addr = dt.address + index * 8;
	return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
				   &ctxt->exception);
1168
}
1169

1170 1171 1172 1173 1174 1175 1176
/* allowed just for 8 bytes segments */
static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				    u16 selector, struct desc_struct *desc)
{
	struct desc_ptr dt;
	u16 index = selector >> 3;
	ulong addr;
A
Avi Kivity 已提交
1177

1178
	get_descriptor_table_ptr(ctxt, selector, &dt);
1179

1180 1181
	if (dt.size < index * 8 + 7)
		return emulate_gp(ctxt, selector & 0xfffc);
A
Avi Kivity 已提交
1182

1183
	addr = dt.address + index * 8;
1184 1185
	return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
				    &ctxt->exception);
1186
}
1187

1188
/* Does not support long mode */
1189 1190 1191 1192 1193 1194 1195 1196 1197
static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				   u16 selector, int seg)
{
	struct desc_struct seg_desc;
	u8 dpl, rpl, cpl;
	unsigned err_vec = GP_VECTOR;
	u32 err_code = 0;
	bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
	int ret;
1198

1199
	memset(&seg_desc, 0, sizeof seg_desc);
1200

1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223
	if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
	    || ctxt->mode == X86EMUL_MODE_REAL) {
		/* set real mode segment descriptor */
		set_desc_base(&seg_desc, selector << 4);
		set_desc_limit(&seg_desc, 0xffff);
		seg_desc.type = 3;
		seg_desc.p = 1;
		seg_desc.s = 1;
		goto load;
	}

	/* NULL selector is not valid for TR, CS and SS */
	if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
	    && null_selector)
		goto exception;

	/* TR should be in GDT only */
	if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
		goto exception;

	if (null_selector) /* for NULL selector skip all following checks */
		goto load;

1224
	ret = read_segment_descriptor(ctxt, selector, &seg_desc);
1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241
	if (ret != X86EMUL_CONTINUE)
		return ret;

	err_code = selector & 0xfffc;
	err_vec = GP_VECTOR;

	/* can't load system descriptor into segment selecor */
	if (seg <= VCPU_SREG_GS && !seg_desc.s)
		goto exception;

	if (!seg_desc.p) {
		err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
		goto exception;
	}

	rpl = selector & 3;
	dpl = seg_desc.dpl;
1242
	cpl = ctxt->ops->cpl(ctxt);
1243 1244 1245 1246 1247 1248 1249 1250 1251

	switch (seg) {
	case VCPU_SREG_SS:
		/*
		 * segment is not a writable data segment or segment
		 * selector's RPL != CPL or segment selector's RPL != CPL
		 */
		if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
			goto exception;
A
Avi Kivity 已提交
1252
		break;
1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267
	case VCPU_SREG_CS:
		if (!(seg_desc.type & 8))
			goto exception;

		if (seg_desc.type & 4) {
			/* conforming */
			if (dpl > cpl)
				goto exception;
		} else {
			/* nonconforming */
			if (rpl > cpl || dpl != cpl)
				goto exception;
		}
		/* CS(RPL) <- CPL */
		selector = (selector & 0xfffc) | cpl;
A
Avi Kivity 已提交
1268
		break;
1269 1270 1271 1272 1273 1274 1275 1276 1277
	case VCPU_SREG_TR:
		if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
			goto exception;
		break;
	case VCPU_SREG_LDTR:
		if (seg_desc.s || seg_desc.type != 2)
			goto exception;
		break;
	default: /*  DS, ES, FS, or GS */
1278
		/*
1279 1280 1281
		 * segment is not a data or readable code segment or
		 * ((segment is a data or nonconforming code segment)
		 * and (both RPL and CPL > DPL))
1282
		 */
1283 1284 1285 1286
		if ((seg_desc.type & 0xa) == 0x8 ||
		    (((seg_desc.type & 0xc) != 0xc) &&
		     (rpl > dpl && cpl > dpl)))
			goto exception;
A
Avi Kivity 已提交
1287
		break;
1288 1289 1290 1291 1292
	}

	if (seg_desc.s) {
		/* mark segment as accessed */
		seg_desc.type |= 1;
1293
		ret = write_segment_descriptor(ctxt, selector, &seg_desc);
1294 1295 1296 1297
		if (ret != X86EMUL_CONTINUE)
			return ret;
	}
load:
1298
	ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
1299 1300 1301 1302 1303 1304
	return X86EMUL_CONTINUE;
exception:
	emulate_exception(ctxt, err_vec, err_code, true);
	return X86EMUL_PROPAGATE_FAULT;
}

1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323
static void write_register_operand(struct operand *op)
{
	/* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
	switch (op->bytes) {
	case 1:
		*(u8 *)op->addr.reg = (u8)op->val;
		break;
	case 2:
		*(u16 *)op->addr.reg = (u16)op->val;
		break;
	case 4:
		*op->addr.reg = (u32)op->val;
		break;	/* 64b: zero-extend */
	case 8:
		*op->addr.reg = op->val;
		break;
	}
}

1324
static int writeback(struct x86_emulate_ctxt *ctxt)
1325 1326 1327
{
	int rc;

1328
	switch (ctxt->dst.type) {
1329
	case OP_REG:
1330
		write_register_operand(&ctxt->dst);
A
Avi Kivity 已提交
1331
		break;
1332
	case OP_MEM:
1333
		if (ctxt->lock_prefix)
1334
			rc = segmented_cmpxchg(ctxt,
1335 1336 1337 1338
					       ctxt->dst.addr.mem,
					       &ctxt->dst.orig_val,
					       &ctxt->dst.val,
					       ctxt->dst.bytes);
1339
		else
1340
			rc = segmented_write(ctxt,
1341 1342 1343
					     ctxt->dst.addr.mem,
					     &ctxt->dst.val,
					     ctxt->dst.bytes);
1344 1345
		if (rc != X86EMUL_CONTINUE)
			return rc;
1346
		break;
A
Avi Kivity 已提交
1347
	case OP_XMM:
1348
		write_sse_reg(ctxt, &ctxt->dst.vec_val, ctxt->dst.addr.xmm);
A
Avi Kivity 已提交
1349
		break;
1350 1351
	case OP_NONE:
		/* no writeback */
1352
		break;
1353
	default:
1354
		break;
A
Avi Kivity 已提交
1355
	}
1356 1357
	return X86EMUL_CONTINUE;
}
A
Avi Kivity 已提交
1358

1359
static int em_push(struct x86_emulate_ctxt *ctxt)
1360
{
1361
	struct segmented_address addr;
1362

1363 1364
	register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], -ctxt->op_bytes);
	addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
1365 1366 1367
	addr.seg = VCPU_SREG_SS;

	/* Disable writeback. */
1368 1369
	ctxt->dst.type = OP_NONE;
	return segmented_write(ctxt, addr, &ctxt->src.val, ctxt->op_bytes);
1370
}
1371

1372 1373 1374 1375
static int emulate_pop(struct x86_emulate_ctxt *ctxt,
		       void *dest, int len)
{
	int rc;
1376
	struct segmented_address addr;
1377

1378
	addr.ea = register_address(ctxt, ctxt->regs[VCPU_REGS_RSP]);
1379
	addr.seg = VCPU_SREG_SS;
1380
	rc = segmented_read(ctxt, addr, dest, len);
1381 1382 1383
	if (rc != X86EMUL_CONTINUE)
		return rc;

1384
	register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], len);
1385
	return rc;
1386 1387
}

1388 1389
static int em_pop(struct x86_emulate_ctxt *ctxt)
{
1390
	return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1391 1392
}

1393
static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1394
			void *dest, int len)
1395 1396
{
	int rc;
1397 1398
	unsigned long val, change_mask;
	int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1399
	int cpl = ctxt->ops->cpl(ctxt);
1400

1401
	rc = emulate_pop(ctxt, &val, len);
1402 1403
	if (rc != X86EMUL_CONTINUE)
		return rc;
1404

1405 1406
	change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
		| EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1407

1408 1409 1410 1411 1412 1413 1414 1415 1416 1417
	switch(ctxt->mode) {
	case X86EMUL_MODE_PROT64:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT16:
		if (cpl == 0)
			change_mask |= EFLG_IOPL;
		if (cpl <= iopl)
			change_mask |= EFLG_IF;
		break;
	case X86EMUL_MODE_VM86:
1418 1419
		if (iopl < 3)
			return emulate_gp(ctxt, 0);
1420 1421 1422 1423 1424
		change_mask |= EFLG_IF;
		break;
	default: /* real mode */
		change_mask |= (EFLG_IOPL | EFLG_IF);
		break;
1425
	}
1426 1427 1428 1429 1430

	*(unsigned long *)dest =
		(ctxt->eflags & ~change_mask) | (val & change_mask);

	return rc;
1431 1432
}

1433 1434
static int em_popf(struct x86_emulate_ctxt *ctxt)
{
1435 1436 1437 1438
	ctxt->dst.type = OP_REG;
	ctxt->dst.addr.reg = &ctxt->eflags;
	ctxt->dst.bytes = ctxt->op_bytes;
	return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1439 1440
}

1441
static int emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg)
1442
{
1443
	ctxt->src.val = get_segment_selector(ctxt, seg);
1444

1445
	return em_push(ctxt);
1446 1447
}

1448
static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt, int seg)
1449
{
1450 1451
	unsigned long selector;
	int rc;
1452

1453
	rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
1454 1455 1456
	if (rc != X86EMUL_CONTINUE)
		return rc;

1457
	rc = load_segment_descriptor(ctxt, (u16)selector, seg);
1458
	return rc;
1459 1460
}

1461
static int em_pusha(struct x86_emulate_ctxt *ctxt)
1462
{
1463
	unsigned long old_esp = ctxt->regs[VCPU_REGS_RSP];
1464 1465
	int rc = X86EMUL_CONTINUE;
	int reg = VCPU_REGS_RAX;
1466

1467 1468
	while (reg <= VCPU_REGS_RDI) {
		(reg == VCPU_REGS_RSP) ?
1469
		(ctxt->src.val = old_esp) : (ctxt->src.val = ctxt->regs[reg]);
1470

1471
		rc = em_push(ctxt);
1472 1473
		if (rc != X86EMUL_CONTINUE)
			return rc;
1474

1475
		++reg;
1476 1477
	}

1478
	return rc;
1479 1480
}

1481 1482
static int em_pushf(struct x86_emulate_ctxt *ctxt)
{
1483
	ctxt->src.val =  (unsigned long)ctxt->eflags;
1484 1485 1486
	return em_push(ctxt);
}

1487
static int em_popa(struct x86_emulate_ctxt *ctxt)
1488
{
1489 1490
	int rc = X86EMUL_CONTINUE;
	int reg = VCPU_REGS_RDI;
1491

1492 1493
	while (reg >= VCPU_REGS_RAX) {
		if (reg == VCPU_REGS_RSP) {
1494 1495
			register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP],
							ctxt->op_bytes);
1496 1497
			--reg;
		}
1498

1499
		rc = emulate_pop(ctxt, &ctxt->regs[reg], ctxt->op_bytes);
1500 1501 1502
		if (rc != X86EMUL_CONTINUE)
			break;
		--reg;
1503
	}
1504
	return rc;
1505 1506
}

1507
int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1508
{
1509
	struct x86_emulate_ops *ops = ctxt->ops;
1510
	int rc;
1511 1512 1513 1514 1515 1516
	struct desc_ptr dt;
	gva_t cs_addr;
	gva_t eip_addr;
	u16 cs, eip;

	/* TODO: Add limit checks */
1517
	ctxt->src.val = ctxt->eflags;
1518
	rc = em_push(ctxt);
1519 1520
	if (rc != X86EMUL_CONTINUE)
		return rc;
1521 1522 1523

	ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);

1524
	ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
1525
	rc = em_push(ctxt);
1526 1527
	if (rc != X86EMUL_CONTINUE)
		return rc;
1528

1529
	ctxt->src.val = ctxt->_eip;
1530
	rc = em_push(ctxt);
1531 1532 1533
	if (rc != X86EMUL_CONTINUE)
		return rc;

1534
	ops->get_idt(ctxt, &dt);
1535 1536 1537 1538

	eip_addr = dt.address + (irq << 2);
	cs_addr = dt.address + (irq << 2) + 2;

1539
	rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
1540 1541 1542
	if (rc != X86EMUL_CONTINUE)
		return rc;

1543
	rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
1544 1545 1546
	if (rc != X86EMUL_CONTINUE)
		return rc;

1547
	rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
1548 1549 1550
	if (rc != X86EMUL_CONTINUE)
		return rc;

1551
	ctxt->_eip = eip;
1552 1553 1554 1555

	return rc;
}

1556
static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
1557 1558 1559
{
	switch(ctxt->mode) {
	case X86EMUL_MODE_REAL:
1560
		return emulate_int_real(ctxt, irq);
1561 1562 1563 1564 1565 1566 1567 1568 1569 1570
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT64:
	default:
		/* Protected mode interrupts unimplemented yet */
		return X86EMUL_UNHANDLEABLE;
	}
}

1571
static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
1572
{
1573 1574 1575 1576 1577 1578 1579 1580
	int rc = X86EMUL_CONTINUE;
	unsigned long temp_eip = 0;
	unsigned long temp_eflags = 0;
	unsigned long cs = 0;
	unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
			     EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
			     EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
	unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1581

1582
	/* TODO: Add stack limit check */
1583

1584
	rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
1585

1586 1587
	if (rc != X86EMUL_CONTINUE)
		return rc;
1588

1589 1590
	if (temp_eip & ~0xffff)
		return emulate_gp(ctxt, 0);
1591

1592
	rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1593

1594 1595
	if (rc != X86EMUL_CONTINUE)
		return rc;
1596

1597
	rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
1598

1599 1600
	if (rc != X86EMUL_CONTINUE)
		return rc;
1601

1602
	rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
1603

1604 1605
	if (rc != X86EMUL_CONTINUE)
		return rc;
1606

1607
	ctxt->_eip = temp_eip;
1608 1609


1610
	if (ctxt->op_bytes == 4)
1611
		ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1612
	else if (ctxt->op_bytes == 2) {
1613 1614
		ctxt->eflags &= ~0xffff;
		ctxt->eflags |= temp_eflags;
1615
	}
1616 1617 1618 1619 1620

	ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
	ctxt->eflags |= EFLG_RESERVED_ONE_MASK;

	return rc;
1621 1622
}

1623
static int em_iret(struct x86_emulate_ctxt *ctxt)
1624
{
1625 1626
	switch(ctxt->mode) {
	case X86EMUL_MODE_REAL:
1627
		return emulate_iret_real(ctxt);
1628 1629 1630 1631
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT64:
1632
	default:
1633 1634
		/* iret from protected mode unimplemented yet */
		return X86EMUL_UNHANDLEABLE;
1635 1636 1637
	}
}

1638 1639 1640 1641 1642
static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
{
	int rc;
	unsigned short sel;

1643
	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
1644

1645
	rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
1646 1647 1648
	if (rc != X86EMUL_CONTINUE)
		return rc;

1649 1650
	ctxt->_eip = 0;
	memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
1651 1652 1653
	return X86EMUL_CONTINUE;
}

1654
static int em_grp1a(struct x86_emulate_ctxt *ctxt)
1655
{
1656
	return emulate_pop(ctxt, &ctxt->dst.val, ctxt->dst.bytes);
1657 1658
}

1659
static int em_grp2(struct x86_emulate_ctxt *ctxt)
1660
{
1661
	switch (ctxt->modrm_reg) {
1662
	case 0:	/* rol */
1663
		emulate_2op_SrcB(ctxt, "rol");
1664 1665
		break;
	case 1:	/* ror */
1666
		emulate_2op_SrcB(ctxt, "ror");
1667 1668
		break;
	case 2:	/* rcl */
1669
		emulate_2op_SrcB(ctxt, "rcl");
1670 1671
		break;
	case 3:	/* rcr */
1672
		emulate_2op_SrcB(ctxt, "rcr");
1673 1674 1675
		break;
	case 4:	/* sal/shl */
	case 6:	/* sal/shl */
1676
		emulate_2op_SrcB(ctxt, "sal");
1677 1678
		break;
	case 5:	/* shr */
1679
		emulate_2op_SrcB(ctxt, "shr");
1680 1681
		break;
	case 7:	/* sar */
1682
		emulate_2op_SrcB(ctxt, "sar");
1683 1684
		break;
	}
1685
	return X86EMUL_CONTINUE;
1686 1687
}

1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706 1707 1708 1709 1710 1711 1712 1713 1714 1715 1716
static int em_not(struct x86_emulate_ctxt *ctxt)
{
	ctxt->dst.val = ~ctxt->dst.val;
	return X86EMUL_CONTINUE;
}

static int em_neg(struct x86_emulate_ctxt *ctxt)
{
	emulate_1op(ctxt, "neg");
	return X86EMUL_CONTINUE;
}

static int em_mul_ex(struct x86_emulate_ctxt *ctxt)
{
	u8 ex = 0;

	emulate_1op_rax_rdx(ctxt, "mul", ex);
	return X86EMUL_CONTINUE;
}

static int em_imul_ex(struct x86_emulate_ctxt *ctxt)
{
	u8 ex = 0;

	emulate_1op_rax_rdx(ctxt, "imul", ex);
	return X86EMUL_CONTINUE;
}

static int em_div_ex(struct x86_emulate_ctxt *ctxt)
1717
{
1718
	u8 de = 0;
1719

1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730
	emulate_1op_rax_rdx(ctxt, "div", de);
	if (de)
		return emulate_de(ctxt);
	return X86EMUL_CONTINUE;
}

static int em_idiv_ex(struct x86_emulate_ctxt *ctxt)
{
	u8 de = 0;

	emulate_1op_rax_rdx(ctxt, "idiv", de);
1731 1732
	if (de)
		return emulate_de(ctxt);
1733
	return X86EMUL_CONTINUE;
1734 1735
}

1736
static int em_grp45(struct x86_emulate_ctxt *ctxt)
1737
{
1738
	int rc = X86EMUL_CONTINUE;
1739

1740
	switch (ctxt->modrm_reg) {
1741
	case 0:	/* inc */
1742
		emulate_1op(ctxt, "inc");
1743 1744
		break;
	case 1:	/* dec */
1745
		emulate_1op(ctxt, "dec");
1746
		break;
1747 1748
	case 2: /* call near abs */ {
		long int old_eip;
1749 1750 1751
		old_eip = ctxt->_eip;
		ctxt->_eip = ctxt->src.val;
		ctxt->src.val = old_eip;
1752
		rc = em_push(ctxt);
1753 1754
		break;
	}
1755
	case 4: /* jmp abs */
1756
		ctxt->_eip = ctxt->src.val;
1757
		break;
1758 1759 1760
	case 5: /* jmp far */
		rc = em_jmp_far(ctxt);
		break;
1761
	case 6:	/* push */
1762
		rc = em_push(ctxt);
1763 1764
		break;
	}
1765
	return rc;
1766 1767
}

1768
static int em_grp9(struct x86_emulate_ctxt *ctxt)
1769
{
1770
	u64 old = ctxt->dst.orig_val64;
1771

1772 1773 1774 1775
	if (((u32) (old >> 0) != (u32) ctxt->regs[VCPU_REGS_RAX]) ||
	    ((u32) (old >> 32) != (u32) ctxt->regs[VCPU_REGS_RDX])) {
		ctxt->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
		ctxt->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1776
		ctxt->eflags &= ~EFLG_ZF;
1777
	} else {
1778 1779
		ctxt->dst.val64 = ((u64)ctxt->regs[VCPU_REGS_RCX] << 32) |
			(u32) ctxt->regs[VCPU_REGS_RBX];
1780

1781
		ctxt->eflags |= EFLG_ZF;
1782
	}
1783
	return X86EMUL_CONTINUE;
1784 1785
}

1786 1787
static int em_ret(struct x86_emulate_ctxt *ctxt)
{
1788 1789 1790
	ctxt->dst.type = OP_REG;
	ctxt->dst.addr.reg = &ctxt->_eip;
	ctxt->dst.bytes = ctxt->op_bytes;
1791 1792 1793
	return em_pop(ctxt);
}

1794
static int em_ret_far(struct x86_emulate_ctxt *ctxt)
1795 1796 1797 1798
{
	int rc;
	unsigned long cs;

1799
	rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
1800
	if (rc != X86EMUL_CONTINUE)
1801
		return rc;
1802 1803 1804
	if (ctxt->op_bytes == 4)
		ctxt->_eip = (u32)ctxt->_eip;
	rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1805
	if (rc != X86EMUL_CONTINUE)
1806
		return rc;
1807
	rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
1808 1809 1810
	return rc;
}

1811
static int emulate_load_segment(struct x86_emulate_ctxt *ctxt, int seg)
1812 1813 1814 1815
{
	unsigned short sel;
	int rc;

1816
	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
1817

1818
	rc = load_segment_descriptor(ctxt, sel, seg);
1819 1820 1821
	if (rc != X86EMUL_CONTINUE)
		return rc;

1822
	ctxt->dst.val = ctxt->src.val;
1823 1824 1825
	return rc;
}

1826
static void
1827
setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1828
			struct desc_struct *cs, struct desc_struct *ss)
1829
{
1830 1831
	u16 selector;

1832
	memset(cs, 0, sizeof(struct desc_struct));
1833
	ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
1834
	memset(ss, 0, sizeof(struct desc_struct));
1835 1836

	cs->l = 0;		/* will be adjusted later */
1837
	set_desc_base(cs, 0);	/* flat segment */
1838
	cs->g = 1;		/* 4kb granularity */
1839
	set_desc_limit(cs, 0xfffff);	/* 4GB limit */
1840 1841 1842
	cs->type = 0x0b;	/* Read, Execute, Accessed */
	cs->s = 1;
	cs->dpl = 0;		/* will be adjusted later */
1843 1844
	cs->p = 1;
	cs->d = 1;
1845

1846 1847
	set_desc_base(ss, 0);	/* flat segment */
	set_desc_limit(ss, 0xfffff);	/* 4GB limit */
1848 1849 1850
	ss->g = 1;		/* 4kb granularity */
	ss->s = 1;
	ss->type = 0x03;	/* Read/Write, Accessed */
1851
	ss->d = 1;		/* 32bit stack segment */
1852
	ss->dpl = 0;
1853
	ss->p = 1;
1854 1855
}

1856
static int em_syscall(struct x86_emulate_ctxt *ctxt)
1857
{
1858
	struct x86_emulate_ops *ops = ctxt->ops;
1859
	struct desc_struct cs, ss;
1860
	u64 msr_data;
1861
	u16 cs_sel, ss_sel;
1862
	u64 efer = 0;
1863 1864

	/* syscall is not available in real mode */
1865
	if (ctxt->mode == X86EMUL_MODE_REAL ||
1866 1867
	    ctxt->mode == X86EMUL_MODE_VM86)
		return emulate_ud(ctxt);
1868

1869
	ops->get_msr(ctxt, MSR_EFER, &efer);
1870
	setup_syscalls_segments(ctxt, &cs, &ss);
1871

1872
	ops->get_msr(ctxt, MSR_STAR, &msr_data);
1873
	msr_data >>= 32;
1874 1875
	cs_sel = (u16)(msr_data & 0xfffc);
	ss_sel = (u16)(msr_data + 8);
1876

1877
	if (efer & EFER_LMA) {
1878
		cs.d = 0;
1879 1880
		cs.l = 1;
	}
1881 1882
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
1883

1884
	ctxt->regs[VCPU_REGS_RCX] = ctxt->_eip;
1885
	if (efer & EFER_LMA) {
1886
#ifdef CONFIG_X86_64
1887
		ctxt->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1888

1889
		ops->get_msr(ctxt,
1890 1891
			     ctxt->mode == X86EMUL_MODE_PROT64 ?
			     MSR_LSTAR : MSR_CSTAR, &msr_data);
1892
		ctxt->_eip = msr_data;
1893

1894
		ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
1895 1896 1897 1898
		ctxt->eflags &= ~(msr_data | EFLG_RF);
#endif
	} else {
		/* legacy mode */
1899
		ops->get_msr(ctxt, MSR_STAR, &msr_data);
1900
		ctxt->_eip = (u32)msr_data;
1901 1902 1903 1904

		ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
	}

1905
	return X86EMUL_CONTINUE;
1906 1907
}

1908
static int em_sysenter(struct x86_emulate_ctxt *ctxt)
1909
{
1910
	struct x86_emulate_ops *ops = ctxt->ops;
1911
	struct desc_struct cs, ss;
1912
	u64 msr_data;
1913
	u16 cs_sel, ss_sel;
1914
	u64 efer = 0;
1915

1916
	ops->get_msr(ctxt, MSR_EFER, &efer);
1917
	/* inject #GP if in real mode */
1918 1919
	if (ctxt->mode == X86EMUL_MODE_REAL)
		return emulate_gp(ctxt, 0);
1920 1921 1922 1923

	/* XXX sysenter/sysexit have not been tested in 64bit mode.
	* Therefore, we inject an #UD.
	*/
1924 1925
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		return emulate_ud(ctxt);
1926

1927
	setup_syscalls_segments(ctxt, &cs, &ss);
1928

1929
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
1930 1931
	switch (ctxt->mode) {
	case X86EMUL_MODE_PROT32:
1932 1933
		if ((msr_data & 0xfffc) == 0x0)
			return emulate_gp(ctxt, 0);
1934 1935
		break;
	case X86EMUL_MODE_PROT64:
1936 1937
		if (msr_data == 0x0)
			return emulate_gp(ctxt, 0);
1938 1939 1940 1941
		break;
	}

	ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1942 1943 1944 1945
	cs_sel = (u16)msr_data;
	cs_sel &= ~SELECTOR_RPL_MASK;
	ss_sel = cs_sel + 8;
	ss_sel &= ~SELECTOR_RPL_MASK;
1946
	if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
1947
		cs.d = 0;
1948 1949 1950
		cs.l = 1;
	}

1951 1952
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
1953

1954
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
1955
	ctxt->_eip = msr_data;
1956

1957
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
1958
	ctxt->regs[VCPU_REGS_RSP] = msr_data;
1959

1960
	return X86EMUL_CONTINUE;
1961 1962
}

1963
static int em_sysexit(struct x86_emulate_ctxt *ctxt)
1964
{
1965
	struct x86_emulate_ops *ops = ctxt->ops;
1966
	struct desc_struct cs, ss;
1967 1968
	u64 msr_data;
	int usermode;
X
Xiao Guangrong 已提交
1969
	u16 cs_sel = 0, ss_sel = 0;
1970

1971 1972
	/* inject #GP if in real mode or Virtual 8086 mode */
	if (ctxt->mode == X86EMUL_MODE_REAL ||
1973 1974
	    ctxt->mode == X86EMUL_MODE_VM86)
		return emulate_gp(ctxt, 0);
1975

1976
	setup_syscalls_segments(ctxt, &cs, &ss);
1977

1978
	if ((ctxt->rex_prefix & 0x8) != 0x0)
1979 1980 1981 1982 1983 1984
		usermode = X86EMUL_MODE_PROT64;
	else
		usermode = X86EMUL_MODE_PROT32;

	cs.dpl = 3;
	ss.dpl = 3;
1985
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
1986 1987
	switch (usermode) {
	case X86EMUL_MODE_PROT32:
1988
		cs_sel = (u16)(msr_data + 16);
1989 1990
		if ((msr_data & 0xfffc) == 0x0)
			return emulate_gp(ctxt, 0);
1991
		ss_sel = (u16)(msr_data + 24);
1992 1993
		break;
	case X86EMUL_MODE_PROT64:
1994
		cs_sel = (u16)(msr_data + 32);
1995 1996
		if (msr_data == 0x0)
			return emulate_gp(ctxt, 0);
1997 1998
		ss_sel = cs_sel + 8;
		cs.d = 0;
1999 2000 2001
		cs.l = 1;
		break;
	}
2002 2003
	cs_sel |= SELECTOR_RPL_MASK;
	ss_sel |= SELECTOR_RPL_MASK;
2004

2005 2006
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2007

2008 2009
	ctxt->_eip = ctxt->regs[VCPU_REGS_RDX];
	ctxt->regs[VCPU_REGS_RSP] = ctxt->regs[VCPU_REGS_RCX];
2010

2011
	return X86EMUL_CONTINUE;
2012 2013
}

2014
static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
2015 2016 2017 2018 2019 2020 2021
{
	int iopl;
	if (ctxt->mode == X86EMUL_MODE_REAL)
		return false;
	if (ctxt->mode == X86EMUL_MODE_VM86)
		return true;
	iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
2022
	return ctxt->ops->cpl(ctxt) > iopl;
2023 2024 2025 2026 2027
}

static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
					    u16 port, u16 len)
{
2028
	struct x86_emulate_ops *ops = ctxt->ops;
2029
	struct desc_struct tr_seg;
2030
	u32 base3;
2031
	int r;
2032
	u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
2033
	unsigned mask = (1 << len) - 1;
2034
	unsigned long base;
2035

2036
	ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
2037
	if (!tr_seg.p)
2038
		return false;
2039
	if (desc_limit_scaled(&tr_seg) < 103)
2040
		return false;
2041 2042 2043 2044
	base = get_desc_base(&tr_seg);
#ifdef CONFIG_X86_64
	base |= ((u64)base3) << 32;
#endif
2045
	r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
2046 2047
	if (r != X86EMUL_CONTINUE)
		return false;
2048
	if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
2049
		return false;
2050
	r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
2051 2052 2053 2054 2055 2056 2057 2058 2059 2060
	if (r != X86EMUL_CONTINUE)
		return false;
	if ((perm >> bit_idx) & mask)
		return false;
	return true;
}

static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
				 u16 port, u16 len)
{
2061 2062 2063
	if (ctxt->perm_ok)
		return true;

2064 2065
	if (emulator_bad_iopl(ctxt))
		if (!emulator_io_port_access_allowed(ctxt, port, len))
2066
			return false;
2067 2068 2069

	ctxt->perm_ok = true;

2070 2071 2072
	return true;
}

2073 2074 2075
static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
				struct tss_segment_16 *tss)
{
2076
	tss->ip = ctxt->_eip;
2077
	tss->flag = ctxt->eflags;
2078 2079 2080 2081 2082 2083 2084 2085
	tss->ax = ctxt->regs[VCPU_REGS_RAX];
	tss->cx = ctxt->regs[VCPU_REGS_RCX];
	tss->dx = ctxt->regs[VCPU_REGS_RDX];
	tss->bx = ctxt->regs[VCPU_REGS_RBX];
	tss->sp = ctxt->regs[VCPU_REGS_RSP];
	tss->bp = ctxt->regs[VCPU_REGS_RBP];
	tss->si = ctxt->regs[VCPU_REGS_RSI];
	tss->di = ctxt->regs[VCPU_REGS_RDI];
2086

2087 2088 2089 2090 2091
	tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
	tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
	tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
	tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
	tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2092 2093 2094 2095 2096 2097 2098
}

static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
				 struct tss_segment_16 *tss)
{
	int ret;

2099
	ctxt->_eip = tss->ip;
2100
	ctxt->eflags = tss->flag | 2;
2101 2102 2103 2104 2105 2106 2107 2108
	ctxt->regs[VCPU_REGS_RAX] = tss->ax;
	ctxt->regs[VCPU_REGS_RCX] = tss->cx;
	ctxt->regs[VCPU_REGS_RDX] = tss->dx;
	ctxt->regs[VCPU_REGS_RBX] = tss->bx;
	ctxt->regs[VCPU_REGS_RSP] = tss->sp;
	ctxt->regs[VCPU_REGS_RBP] = tss->bp;
	ctxt->regs[VCPU_REGS_RSI] = tss->si;
	ctxt->regs[VCPU_REGS_RDI] = tss->di;
2109 2110 2111 2112 2113

	/*
	 * SDM says that segment selectors are loaded before segment
	 * descriptors
	 */
2114 2115 2116 2117 2118
	set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
	set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
	set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
	set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
	set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2119 2120 2121 2122 2123

	/*
	 * Now load segment descriptors. If fault happenes at this stage
	 * it is handled in a context of new task
	 */
2124
	ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
2125 2126
	if (ret != X86EMUL_CONTINUE)
		return ret;
2127
	ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
2128 2129
	if (ret != X86EMUL_CONTINUE)
		return ret;
2130
	ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
2131 2132
	if (ret != X86EMUL_CONTINUE)
		return ret;
2133
	ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
2134 2135
	if (ret != X86EMUL_CONTINUE)
		return ret;
2136
	ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
2137 2138 2139 2140 2141 2142 2143 2144 2145 2146
	if (ret != X86EMUL_CONTINUE)
		return ret;

	return X86EMUL_CONTINUE;
}

static int task_switch_16(struct x86_emulate_ctxt *ctxt,
			  u16 tss_selector, u16 old_tss_sel,
			  ulong old_tss_base, struct desc_struct *new_desc)
{
2147
	struct x86_emulate_ops *ops = ctxt->ops;
2148 2149
	struct tss_segment_16 tss_seg;
	int ret;
2150
	u32 new_tss_base = get_desc_base(new_desc);
2151

2152
	ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2153
			    &ctxt->exception);
2154
	if (ret != X86EMUL_CONTINUE)
2155 2156 2157
		/* FIXME: need to provide precise fault address */
		return ret;

2158
	save_state_to_tss16(ctxt, &tss_seg);
2159

2160
	ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2161
			     &ctxt->exception);
2162
	if (ret != X86EMUL_CONTINUE)
2163 2164 2165
		/* FIXME: need to provide precise fault address */
		return ret;

2166
	ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2167
			    &ctxt->exception);
2168
	if (ret != X86EMUL_CONTINUE)
2169 2170 2171 2172 2173 2174
		/* FIXME: need to provide precise fault address */
		return ret;

	if (old_tss_sel != 0xffff) {
		tss_seg.prev_task_link = old_tss_sel;

2175
		ret = ops->write_std(ctxt, new_tss_base,
2176 2177
				     &tss_seg.prev_task_link,
				     sizeof tss_seg.prev_task_link,
2178
				     &ctxt->exception);
2179
		if (ret != X86EMUL_CONTINUE)
2180 2181 2182 2183
			/* FIXME: need to provide precise fault address */
			return ret;
	}

2184
	return load_state_from_tss16(ctxt, &tss_seg);
2185 2186 2187 2188 2189
}

static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
				struct tss_segment_32 *tss)
{
2190
	tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
2191
	tss->eip = ctxt->_eip;
2192
	tss->eflags = ctxt->eflags;
2193 2194 2195 2196 2197 2198 2199 2200
	tss->eax = ctxt->regs[VCPU_REGS_RAX];
	tss->ecx = ctxt->regs[VCPU_REGS_RCX];
	tss->edx = ctxt->regs[VCPU_REGS_RDX];
	tss->ebx = ctxt->regs[VCPU_REGS_RBX];
	tss->esp = ctxt->regs[VCPU_REGS_RSP];
	tss->ebp = ctxt->regs[VCPU_REGS_RBP];
	tss->esi = ctxt->regs[VCPU_REGS_RSI];
	tss->edi = ctxt->regs[VCPU_REGS_RDI];
2201

2202 2203 2204 2205 2206 2207 2208
	tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
	tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
	tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
	tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
	tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
	tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
	tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2209 2210 2211 2212 2213 2214 2215
}

static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
				 struct tss_segment_32 *tss)
{
	int ret;

2216
	if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
2217
		return emulate_gp(ctxt, 0);
2218
	ctxt->_eip = tss->eip;
2219
	ctxt->eflags = tss->eflags | 2;
2220 2221 2222 2223 2224 2225 2226 2227
	ctxt->regs[VCPU_REGS_RAX] = tss->eax;
	ctxt->regs[VCPU_REGS_RCX] = tss->ecx;
	ctxt->regs[VCPU_REGS_RDX] = tss->edx;
	ctxt->regs[VCPU_REGS_RBX] = tss->ebx;
	ctxt->regs[VCPU_REGS_RSP] = tss->esp;
	ctxt->regs[VCPU_REGS_RBP] = tss->ebp;
	ctxt->regs[VCPU_REGS_RSI] = tss->esi;
	ctxt->regs[VCPU_REGS_RDI] = tss->edi;
2228 2229 2230 2231 2232

	/*
	 * SDM says that segment selectors are loaded before segment
	 * descriptors
	 */
2233 2234 2235 2236 2237 2238 2239
	set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
	set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
	set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
	set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
	set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
	set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
	set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
2240 2241 2242 2243 2244

	/*
	 * Now load segment descriptors. If fault happenes at this stage
	 * it is handled in a context of new task
	 */
2245
	ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2246 2247
	if (ret != X86EMUL_CONTINUE)
		return ret;
2248
	ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
2249 2250
	if (ret != X86EMUL_CONTINUE)
		return ret;
2251
	ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
2252 2253
	if (ret != X86EMUL_CONTINUE)
		return ret;
2254
	ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
2255 2256
	if (ret != X86EMUL_CONTINUE)
		return ret;
2257
	ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
2258 2259
	if (ret != X86EMUL_CONTINUE)
		return ret;
2260
	ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
2261 2262
	if (ret != X86EMUL_CONTINUE)
		return ret;
2263
	ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
2264 2265 2266 2267 2268 2269 2270 2271 2272 2273
	if (ret != X86EMUL_CONTINUE)
		return ret;

	return X86EMUL_CONTINUE;
}

static int task_switch_32(struct x86_emulate_ctxt *ctxt,
			  u16 tss_selector, u16 old_tss_sel,
			  ulong old_tss_base, struct desc_struct *new_desc)
{
2274
	struct x86_emulate_ops *ops = ctxt->ops;
2275 2276
	struct tss_segment_32 tss_seg;
	int ret;
2277
	u32 new_tss_base = get_desc_base(new_desc);
2278

2279
	ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2280
			    &ctxt->exception);
2281
	if (ret != X86EMUL_CONTINUE)
2282 2283 2284
		/* FIXME: need to provide precise fault address */
		return ret;

2285
	save_state_to_tss32(ctxt, &tss_seg);
2286

2287
	ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2288
			     &ctxt->exception);
2289
	if (ret != X86EMUL_CONTINUE)
2290 2291 2292
		/* FIXME: need to provide precise fault address */
		return ret;

2293
	ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2294
			    &ctxt->exception);
2295
	if (ret != X86EMUL_CONTINUE)
2296 2297 2298 2299 2300 2301
		/* FIXME: need to provide precise fault address */
		return ret;

	if (old_tss_sel != 0xffff) {
		tss_seg.prev_task_link = old_tss_sel;

2302
		ret = ops->write_std(ctxt, new_tss_base,
2303 2304
				     &tss_seg.prev_task_link,
				     sizeof tss_seg.prev_task_link,
2305
				     &ctxt->exception);
2306
		if (ret != X86EMUL_CONTINUE)
2307 2308 2309 2310
			/* FIXME: need to provide precise fault address */
			return ret;
	}

2311
	return load_state_from_tss32(ctxt, &tss_seg);
2312 2313 2314
}

static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2315 2316
				   u16 tss_selector, int reason,
				   bool has_error_code, u32 error_code)
2317
{
2318
	struct x86_emulate_ops *ops = ctxt->ops;
2319 2320
	struct desc_struct curr_tss_desc, next_tss_desc;
	int ret;
2321
	u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
2322
	ulong old_tss_base =
2323
		ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
2324
	u32 desc_limit;
2325 2326 2327

	/* FIXME: old_tss_base == ~0 ? */

2328
	ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
2329 2330
	if (ret != X86EMUL_CONTINUE)
		return ret;
2331
	ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
2332 2333 2334 2335 2336 2337 2338
	if (ret != X86EMUL_CONTINUE)
		return ret;

	/* FIXME: check that next_tss_desc is tss */

	if (reason != TASK_SWITCH_IRET) {
		if ((tss_selector & 3) > next_tss_desc.dpl ||
2339
		    ops->cpl(ctxt) > next_tss_desc.dpl)
2340
			return emulate_gp(ctxt, 0);
2341 2342
	}

2343 2344 2345 2346
	desc_limit = desc_limit_scaled(&next_tss_desc);
	if (!next_tss_desc.p ||
	    ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
	     desc_limit < 0x2b)) {
2347
		emulate_ts(ctxt, tss_selector & 0xfffc);
2348 2349 2350 2351 2352
		return X86EMUL_PROPAGATE_FAULT;
	}

	if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
		curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2353
		write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364
	}

	if (reason == TASK_SWITCH_IRET)
		ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;

	/* set back link to prev task only if NT bit is set in eflags
	   note that old_tss_sel is not used afetr this point */
	if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
		old_tss_sel = 0xffff;

	if (next_tss_desc.type & 8)
2365
		ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
2366 2367
				     old_tss_base, &next_tss_desc);
	else
2368
		ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
2369
				     old_tss_base, &next_tss_desc);
2370 2371
	if (ret != X86EMUL_CONTINUE)
		return ret;
2372 2373 2374 2375 2376 2377

	if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
		ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;

	if (reason != TASK_SWITCH_IRET) {
		next_tss_desc.type |= (1 << 1); /* set busy flag */
2378
		write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
2379 2380
	}

2381
	ops->set_cr(ctxt, 0,  ops->get_cr(ctxt, 0) | X86_CR0_TS);
2382
	ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
2383

2384
	if (has_error_code) {
2385 2386 2387
		ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
		ctxt->lock_prefix = 0;
		ctxt->src.val = (unsigned long) error_code;
2388
		ret = em_push(ctxt);
2389 2390
	}

2391 2392 2393 2394
	return ret;
}

int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2395 2396
			 u16 tss_selector, int reason,
			 bool has_error_code, u32 error_code)
2397 2398 2399
{
	int rc;

2400 2401
	ctxt->_eip = ctxt->eip;
	ctxt->dst.type = OP_NONE;
2402

2403
	rc = emulator_do_task_switch(ctxt, tss_selector, reason,
2404
				     has_error_code, error_code);
2405

2406
	if (rc == X86EMUL_CONTINUE)
2407
		ctxt->eip = ctxt->_eip;
2408

2409
	return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
2410 2411
}

2412
static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
2413
			    int reg, struct operand *op)
2414 2415 2416
{
	int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;

2417 2418
	register_address_increment(ctxt, &ctxt->regs[reg], df * op->bytes);
	op->addr.mem.ea = register_address(ctxt, ctxt->regs[reg]);
2419
	op->addr.mem.seg = seg;
2420 2421
}

2422 2423 2424 2425 2426 2427
static int em_das(struct x86_emulate_ctxt *ctxt)
{
	u8 al, old_al;
	bool af, cf, old_cf;

	cf = ctxt->eflags & X86_EFLAGS_CF;
2428
	al = ctxt->dst.val;
2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445

	old_al = al;
	old_cf = cf;
	cf = false;
	af = ctxt->eflags & X86_EFLAGS_AF;
	if ((al & 0x0f) > 9 || af) {
		al -= 6;
		cf = old_cf | (al >= 250);
		af = true;
	} else {
		af = false;
	}
	if (old_al > 0x99 || old_cf) {
		al -= 0x60;
		cf = true;
	}

2446
	ctxt->dst.val = al;
2447
	/* Set PF, ZF, SF */
2448 2449 2450
	ctxt->src.type = OP_IMM;
	ctxt->src.val = 0;
	ctxt->src.bytes = 1;
2451
	emulate_2op_SrcV(ctxt, "or");
2452 2453 2454 2455 2456 2457 2458 2459
	ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
	if (cf)
		ctxt->eflags |= X86_EFLAGS_CF;
	if (af)
		ctxt->eflags |= X86_EFLAGS_AF;
	return X86EMUL_CONTINUE;
}

2460 2461 2462 2463 2464 2465
static int em_call_far(struct x86_emulate_ctxt *ctxt)
{
	u16 sel, old_cs;
	ulong old_eip;
	int rc;

2466
	old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2467
	old_eip = ctxt->_eip;
2468

2469
	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2470
	if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
2471 2472
		return X86EMUL_CONTINUE;

2473 2474
	ctxt->_eip = 0;
	memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
2475

2476
	ctxt->src.val = old_cs;
2477
	rc = em_push(ctxt);
2478 2479 2480
	if (rc != X86EMUL_CONTINUE)
		return rc;

2481
	ctxt->src.val = old_eip;
2482
	return em_push(ctxt);
2483 2484
}

2485 2486 2487 2488
static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
{
	int rc;

2489 2490 2491 2492
	ctxt->dst.type = OP_REG;
	ctxt->dst.addr.reg = &ctxt->_eip;
	ctxt->dst.bytes = ctxt->op_bytes;
	rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
2493 2494
	if (rc != X86EMUL_CONTINUE)
		return rc;
2495
	register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RSP], ctxt->src.val);
2496 2497 2498
	return X86EMUL_CONTINUE;
}

2499 2500
static int em_add(struct x86_emulate_ctxt *ctxt)
{
2501
	emulate_2op_SrcV(ctxt, "add");
2502 2503 2504 2505 2506
	return X86EMUL_CONTINUE;
}

static int em_or(struct x86_emulate_ctxt *ctxt)
{
2507
	emulate_2op_SrcV(ctxt, "or");
2508 2509 2510 2511 2512
	return X86EMUL_CONTINUE;
}

static int em_adc(struct x86_emulate_ctxt *ctxt)
{
2513
	emulate_2op_SrcV(ctxt, "adc");
2514 2515 2516 2517 2518
	return X86EMUL_CONTINUE;
}

static int em_sbb(struct x86_emulate_ctxt *ctxt)
{
2519
	emulate_2op_SrcV(ctxt, "sbb");
2520 2521 2522 2523 2524
	return X86EMUL_CONTINUE;
}

static int em_and(struct x86_emulate_ctxt *ctxt)
{
2525
	emulate_2op_SrcV(ctxt, "and");
2526 2527 2528 2529 2530
	return X86EMUL_CONTINUE;
}

static int em_sub(struct x86_emulate_ctxt *ctxt)
{
2531
	emulate_2op_SrcV(ctxt, "sub");
2532 2533 2534 2535 2536
	return X86EMUL_CONTINUE;
}

static int em_xor(struct x86_emulate_ctxt *ctxt)
{
2537
	emulate_2op_SrcV(ctxt, "xor");
2538 2539 2540 2541 2542
	return X86EMUL_CONTINUE;
}

static int em_cmp(struct x86_emulate_ctxt *ctxt)
{
2543
	emulate_2op_SrcV(ctxt, "cmp");
2544
	/* Disable writeback. */
2545
	ctxt->dst.type = OP_NONE;
2546 2547 2548
	return X86EMUL_CONTINUE;
}

2549 2550
static int em_test(struct x86_emulate_ctxt *ctxt)
{
2551
	emulate_2op_SrcV(ctxt, "test");
2552 2553
	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
2554 2555 2556
	return X86EMUL_CONTINUE;
}

2557 2558 2559
static int em_xchg(struct x86_emulate_ctxt *ctxt)
{
	/* Write back the register source. */
2560 2561
	ctxt->src.val = ctxt->dst.val;
	write_register_operand(&ctxt->src);
2562 2563

	/* Write back the memory destination with implicit LOCK prefix. */
2564 2565
	ctxt->dst.val = ctxt->src.orig_val;
	ctxt->lock_prefix = 1;
2566 2567 2568
	return X86EMUL_CONTINUE;
}

2569
static int em_imul(struct x86_emulate_ctxt *ctxt)
2570
{
2571
	emulate_2op_SrcV_nobyte(ctxt, "imul");
2572 2573 2574
	return X86EMUL_CONTINUE;
}

2575 2576
static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
{
2577
	ctxt->dst.val = ctxt->src2.val;
2578 2579 2580
	return em_imul(ctxt);
}

2581 2582
static int em_cwd(struct x86_emulate_ctxt *ctxt)
{
2583 2584 2585 2586
	ctxt->dst.type = OP_REG;
	ctxt->dst.bytes = ctxt->src.bytes;
	ctxt->dst.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
	ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
2587 2588 2589 2590

	return X86EMUL_CONTINUE;
}

2591 2592 2593 2594
static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
{
	u64 tsc = 0;

2595
	ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
2596 2597
	ctxt->regs[VCPU_REGS_RAX] = (u32)tsc;
	ctxt->regs[VCPU_REGS_RDX] = tsc >> 32;
2598 2599 2600
	return X86EMUL_CONTINUE;
}

2601 2602
static int em_mov(struct x86_emulate_ctxt *ctxt)
{
2603
	ctxt->dst.val = ctxt->src.val;
2604 2605 2606
	return X86EMUL_CONTINUE;
}

2607 2608
static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
{
2609
	if (ctxt->modrm_reg > VCPU_SREG_GS)
2610 2611
		return emulate_ud(ctxt);

2612
	ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
2613 2614 2615 2616 2617
	return X86EMUL_CONTINUE;
}

static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
{
2618
	u16 sel = ctxt->src.val;
2619

2620
	if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
2621 2622
		return emulate_ud(ctxt);

2623
	if (ctxt->modrm_reg == VCPU_SREG_SS)
2624 2625 2626
		ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;

	/* Disable writeback. */
2627 2628
	ctxt->dst.type = OP_NONE;
	return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
2629 2630
}

2631 2632
static int em_movdqu(struct x86_emulate_ctxt *ctxt)
{
2633
	memcpy(&ctxt->dst.vec_val, &ctxt->src.vec_val, ctxt->op_bytes);
2634 2635 2636
	return X86EMUL_CONTINUE;
}

2637 2638
static int em_invlpg(struct x86_emulate_ctxt *ctxt)
{
2639 2640 2641
	int rc;
	ulong linear;

2642
	rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
2643
	if (rc == X86EMUL_CONTINUE)
2644
		ctxt->ops->invlpg(ctxt, linear);
2645
	/* Disable writeback. */
2646
	ctxt->dst.type = OP_NONE;
2647 2648 2649
	return X86EMUL_CONTINUE;
}

2650 2651 2652 2653 2654 2655 2656 2657 2658 2659
static int em_clts(struct x86_emulate_ctxt *ctxt)
{
	ulong cr0;

	cr0 = ctxt->ops->get_cr(ctxt, 0);
	cr0 &= ~X86_CR0_TS;
	ctxt->ops->set_cr(ctxt, 0, cr0);
	return X86EMUL_CONTINUE;
}

2660 2661 2662 2663
static int em_vmcall(struct x86_emulate_ctxt *ctxt)
{
	int rc;

2664
	if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
2665 2666 2667 2668 2669 2670 2671
		return X86EMUL_UNHANDLEABLE;

	rc = ctxt->ops->fix_hypercall(ctxt);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	/* Let the processor re-execute the fixed hypercall */
2672
	ctxt->_eip = ctxt->eip;
2673
	/* Disable writeback. */
2674
	ctxt->dst.type = OP_NONE;
2675 2676 2677 2678 2679 2680 2681 2682
	return X86EMUL_CONTINUE;
}

static int em_lgdt(struct x86_emulate_ctxt *ctxt)
{
	struct desc_ptr desc_ptr;
	int rc;

2683
	rc = read_descriptor(ctxt, ctxt->src.addr.mem,
2684
			     &desc_ptr.size, &desc_ptr.address,
2685
			     ctxt->op_bytes);
2686 2687 2688 2689
	if (rc != X86EMUL_CONTINUE)
		return rc;
	ctxt->ops->set_gdt(ctxt, &desc_ptr);
	/* Disable writeback. */
2690
	ctxt->dst.type = OP_NONE;
2691 2692 2693
	return X86EMUL_CONTINUE;
}

2694
static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
2695 2696 2697
{
	int rc;

2698 2699
	rc = ctxt->ops->fix_hypercall(ctxt);

2700
	/* Disable writeback. */
2701
	ctxt->dst.type = OP_NONE;
2702 2703 2704 2705 2706 2707 2708 2709
	return rc;
}

static int em_lidt(struct x86_emulate_ctxt *ctxt)
{
	struct desc_ptr desc_ptr;
	int rc;

2710
	rc = read_descriptor(ctxt, ctxt->src.addr.mem,
2711
			     &desc_ptr.size, &desc_ptr.address,
2712
			     ctxt->op_bytes);
2713 2714 2715 2716
	if (rc != X86EMUL_CONTINUE)
		return rc;
	ctxt->ops->set_idt(ctxt, &desc_ptr);
	/* Disable writeback. */
2717
	ctxt->dst.type = OP_NONE;
2718 2719 2720 2721 2722
	return X86EMUL_CONTINUE;
}

static int em_smsw(struct x86_emulate_ctxt *ctxt)
{
2723 2724
	ctxt->dst.bytes = 2;
	ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
2725 2726 2727 2728 2729 2730
	return X86EMUL_CONTINUE;
}

static int em_lmsw(struct x86_emulate_ctxt *ctxt)
{
	ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
2731 2732
			  | (ctxt->src.val & 0x0f));
	ctxt->dst.type = OP_NONE;
2733 2734 2735
	return X86EMUL_CONTINUE;
}

2736 2737
static int em_loop(struct x86_emulate_ctxt *ctxt)
{
2738 2739 2740 2741
	register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
	if ((address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) != 0) &&
	    (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
		jmp_rel(ctxt, ctxt->src.val);
2742 2743 2744 2745 2746 2747

	return X86EMUL_CONTINUE;
}

static int em_jcxz(struct x86_emulate_ctxt *ctxt)
{
2748 2749
	if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0)
		jmp_rel(ctxt, ctxt->src.val);
2750 2751 2752 2753

	return X86EMUL_CONTINUE;
}

2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772
static int em_cli(struct x86_emulate_ctxt *ctxt)
{
	if (emulator_bad_iopl(ctxt))
		return emulate_gp(ctxt, 0);

	ctxt->eflags &= ~X86_EFLAGS_IF;
	return X86EMUL_CONTINUE;
}

static int em_sti(struct x86_emulate_ctxt *ctxt)
{
	if (emulator_bad_iopl(ctxt))
		return emulate_gp(ctxt, 0);

	ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
	ctxt->eflags |= X86_EFLAGS_IF;
	return X86EMUL_CONTINUE;
}

2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786
static bool valid_cr(int nr)
{
	switch (nr) {
	case 0:
	case 2 ... 4:
	case 8:
		return true;
	default:
		return false;
	}
}

static int check_cr_read(struct x86_emulate_ctxt *ctxt)
{
2787
	if (!valid_cr(ctxt->modrm_reg))
2788 2789 2790 2791 2792 2793 2794
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_cr_write(struct x86_emulate_ctxt *ctxt)
{
2795 2796
	u64 new_val = ctxt->src.val64;
	int cr = ctxt->modrm_reg;
2797
	u64 efer = 0;
2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814

	static u64 cr_reserved_bits[] = {
		0xffffffff00000000ULL,
		0, 0, 0, /* CR3 checked later */
		CR4_RESERVED_BITS,
		0, 0, 0,
		CR8_RESERVED_BITS,
	};

	if (!valid_cr(cr))
		return emulate_ud(ctxt);

	if (new_val & cr_reserved_bits[cr])
		return emulate_gp(ctxt, 0);

	switch (cr) {
	case 0: {
2815
		u64 cr4;
2816 2817 2818 2819
		if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
		    ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
			return emulate_gp(ctxt, 0);

2820 2821
		cr4 = ctxt->ops->get_cr(ctxt, 4);
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2822 2823 2824 2825 2826 2827 2828 2829 2830 2831

		if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
		    !(cr4 & X86_CR4_PAE))
			return emulate_gp(ctxt, 0);

		break;
		}
	case 3: {
		u64 rsvd = 0;

2832 2833
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
		if (efer & EFER_LMA)
2834
			rsvd = CR3_L_MODE_RESERVED_BITS;
2835
		else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
2836
			rsvd = CR3_PAE_RESERVED_BITS;
2837
		else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
2838 2839 2840 2841 2842 2843 2844 2845
			rsvd = CR3_NONPAE_RESERVED_BITS;

		if (new_val & rsvd)
			return emulate_gp(ctxt, 0);

		break;
		}
	case 4: {
2846
		u64 cr4;
2847

2848 2849
		cr4 = ctxt->ops->get_cr(ctxt, 4);
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860

		if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
			return emulate_gp(ctxt, 0);

		break;
		}
	}

	return X86EMUL_CONTINUE;
}

2861 2862 2863 2864
static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
{
	unsigned long dr7;

2865
	ctxt->ops->get_dr(ctxt, 7, &dr7);
2866 2867 2868 2869 2870 2871 2872

	/* Check if DR7.Global_Enable is set */
	return dr7 & (1 << 13);
}

static int check_dr_read(struct x86_emulate_ctxt *ctxt)
{
2873
	int dr = ctxt->modrm_reg;
2874 2875 2876 2877 2878
	u64 cr4;

	if (dr > 7)
		return emulate_ud(ctxt);

2879
	cr4 = ctxt->ops->get_cr(ctxt, 4);
2880 2881 2882 2883 2884 2885 2886 2887 2888 2889 2890
	if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
		return emulate_ud(ctxt);

	if (check_dr7_gd(ctxt))
		return emulate_db(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_dr_write(struct x86_emulate_ctxt *ctxt)
{
2891 2892
	u64 new_val = ctxt->src.val64;
	int dr = ctxt->modrm_reg;
2893 2894 2895 2896 2897 2898 2899

	if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
		return emulate_gp(ctxt, 0);

	return check_dr_read(ctxt);
}

2900 2901 2902 2903
static int check_svme(struct x86_emulate_ctxt *ctxt)
{
	u64 efer;

2904
	ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2905 2906 2907 2908 2909 2910 2911 2912 2913

	if (!(efer & EFER_SVME))
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
{
2914
	u64 rax = ctxt->regs[VCPU_REGS_RAX];
2915 2916

	/* Valid physical address? */
2917
	if (rax & 0xffff000000000000ULL)
2918 2919 2920 2921 2922
		return emulate_gp(ctxt, 0);

	return check_svme(ctxt);
}

2923 2924
static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
{
2925
	u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
2926

2927
	if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
2928 2929 2930 2931 2932
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

2933 2934
static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
{
2935
	u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
2936
	u64 rcx = ctxt->regs[VCPU_REGS_RCX];
2937

2938
	if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
2939 2940 2941 2942 2943 2944
	    (rcx > 3))
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

2945 2946
static int check_perm_in(struct x86_emulate_ctxt *ctxt)
{
2947 2948
	ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
	if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
2949 2950 2951 2952 2953 2954 2955
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

static int check_perm_out(struct x86_emulate_ctxt *ctxt)
{
2956 2957
	ctxt->src.bytes = min(ctxt->src.bytes, 4u);
	if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
2958 2959 2960 2961 2962
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

2963
#define D(_y) { .flags = (_y) }
2964
#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
2965 2966
#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
		      .check_perm = (_p) }
2967
#define N    D(0)
2968
#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
2969
#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2970
#define GD(_f, _g) { .flags = ((_f) | GroupDual), .u.gdual = (_g) }
2971
#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2972 2973
#define II(_f, _e, _i) \
	{ .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
2974 2975 2976
#define IIP(_f, _e, _i, _p) \
	{ .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
	  .check_perm = (_p) }
2977
#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
2978

2979
#define D2bv(_f)      D((_f) | ByteOp), D(_f)
2980
#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
2981 2982
#define I2bv(_f, _e)  I((_f) | ByteOp, _e), I(_f, _e)

2983 2984 2985
#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e),		\
		I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e),	\
		I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
2986

2987 2988 2989 2990 2991 2992
static struct opcode group7_rm1[] = {
	DI(SrcNone | ModRM | Priv, monitor),
	DI(SrcNone | ModRM | Priv, mwait),
	N, N, N, N, N, N,
};

2993 2994
static struct opcode group7_rm3[] = {
	DIP(SrcNone | ModRM | Prot | Priv, vmrun,   check_svme_pa),
2995
	II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall),
2996 2997 2998 2999 3000 3001 3002
	DIP(SrcNone | ModRM | Prot | Priv, vmload,  check_svme_pa),
	DIP(SrcNone | ModRM | Prot | Priv, vmsave,  check_svme_pa),
	DIP(SrcNone | ModRM | Prot | Priv, stgi,    check_svme),
	DIP(SrcNone | ModRM | Prot | Priv, clgi,    check_svme),
	DIP(SrcNone | ModRM | Prot | Priv, skinit,  check_svme),
	DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
};
3003

3004 3005 3006 3007 3008
static struct opcode group7_rm7[] = {
	N,
	DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
	N, N, N, N, N, N,
};
3009

3010
static struct opcode group1[] = {
3011 3012 3013 3014 3015 3016 3017 3018
	I(Lock, em_add),
	I(Lock, em_or),
	I(Lock, em_adc),
	I(Lock, em_sbb),
	I(Lock, em_and),
	I(Lock, em_sub),
	I(Lock, em_xor),
	I(0, em_cmp),
3019 3020 3021 3022 3023 3024 3025
};

static struct opcode group1A[] = {
	D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
};

static struct opcode group3[] = {
3026 3027 3028 3029 3030 3031 3032 3033
	I(DstMem | SrcImm | ModRM, em_test),
	I(DstMem | SrcImm | ModRM, em_test),
	I(DstMem | SrcNone | ModRM | Lock, em_not),
	I(DstMem | SrcNone | ModRM | Lock, em_neg),
	I(SrcMem | ModRM, em_mul_ex),
	I(SrcMem | ModRM, em_imul_ex),
	I(SrcMem | ModRM, em_div_ex),
	I(SrcMem | ModRM, em_idiv_ex),
3034 3035 3036 3037 3038 3039 3040 3041 3042
};

static struct opcode group4[] = {
	D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
	N, N, N, N, N, N,
};

static struct opcode group5[] = {
	D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3043 3044
	D(SrcMem | ModRM | Stack),
	I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
3045 3046 3047 3048
	D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
	D(SrcMem | ModRM | Stack), N,
};

3049 3050 3051 3052 3053 3054 3055 3056
static struct opcode group6[] = {
	DI(ModRM | Prot,        sldt),
	DI(ModRM | Prot,        str),
	DI(ModRM | Prot | Priv, lldt),
	DI(ModRM | Prot | Priv, ltr),
	N, N, N, N,
};

3057
static struct group_dual group7 = { {
3058 3059
	DI(ModRM | Mov | DstMem | Priv, sgdt),
	DI(ModRM | Mov | DstMem | Priv, sidt),
3060 3061 3062 3063 3064
	II(ModRM | SrcMem | Priv, em_lgdt, lgdt),
	II(ModRM | SrcMem | Priv, em_lidt, lidt),
	II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
	II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw),
	II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
3065
}, {
3066 3067
	I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall),
	EXT(0, group7_rm1),
3068
	N, EXT(0, group7_rm3),
3069 3070
	II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
	II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7),
3071 3072 3073 3074 3075 3076 3077 3078 3079 3080 3081 3082 3083 3084
} };

static struct opcode group8[] = {
	N, N, N, N,
	D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
	D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
};

static struct group_dual group9 = { {
	N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
}, {
	N, N, N, N, N, N, N, N,
} };

3085 3086 3087 3088
static struct opcode group11[] = {
	I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
};

3089 3090 3091 3092
static struct gprefix pfx_0f_6f_0f_7f = {
	N, N, N, I(Sse, em_movdqu),
};

3093 3094
static struct opcode opcode_table[256] = {
	/* 0x00 - 0x07 */
3095
	I6ALU(Lock, em_add),
3096 3097
	D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
	/* 0x08 - 0x0F */
3098
	I6ALU(Lock, em_or),
3099 3100
	D(ImplicitOps | Stack | No64), N,
	/* 0x10 - 0x17 */
3101
	I6ALU(Lock, em_adc),
3102 3103
	D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
	/* 0x18 - 0x1F */
3104
	I6ALU(Lock, em_sbb),
3105 3106
	D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
	/* 0x20 - 0x27 */
3107
	I6ALU(Lock, em_and), N, N,
3108
	/* 0x28 - 0x2F */
3109
	I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
3110
	/* 0x30 - 0x37 */
3111
	I6ALU(Lock, em_xor), N, N,
3112
	/* 0x38 - 0x3F */
3113
	I6ALU(0, em_cmp), N, N,
3114 3115 3116
	/* 0x40 - 0x4F */
	X16(D(DstReg)),
	/* 0x50 - 0x57 */
3117
	X8(I(SrcReg | Stack, em_push)),
3118
	/* 0x58 - 0x5F */
3119
	X8(I(DstReg | Stack, em_pop)),
3120
	/* 0x60 - 0x67 */
3121 3122
	I(ImplicitOps | Stack | No64, em_pusha),
	I(ImplicitOps | Stack | No64, em_popa),
3123 3124 3125
	N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
	N, N, N, N,
	/* 0x68 - 0x6F */
3126 3127
	I(SrcImm | Mov | Stack, em_push),
	I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
3128 3129
	I(SrcImmByte | Mov | Stack, em_push),
	I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
3130 3131
	D2bvIP(DstDI | SrcDX | Mov | String, ins, check_perm_in), /* insb, insw/insd */
	D2bvIP(SrcSI | DstDX | String, outs, check_perm_out), /* outsb, outsw/outsd */
3132 3133 3134 3135 3136 3137 3138
	/* 0x70 - 0x7F */
	X16(D(SrcImmByte)),
	/* 0x80 - 0x87 */
	G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
	G(DstMem | SrcImm | ModRM | Group, group1),
	G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
	G(DstMem | SrcImmByte | ModRM | Group, group1),
3139
	I2bv(DstMem | SrcReg | ModRM, em_test),
3140
	I2bv(DstMem | SrcReg | ModRM | Lock, em_xchg),
3141
	/* 0x88 - 0x8F */
3142 3143
	I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
	I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
3144 3145 3146 3147
	I(DstMem | SrcNone | ModRM | Mov, em_mov_rm_sreg),
	D(ModRM | SrcMem | NoAccess | DstReg),
	I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
	G(0, group1A),
3148
	/* 0x90 - 0x97 */
3149
	DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
3150
	/* 0x98 - 0x9F */
3151
	D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
3152
	I(SrcImmFAddr | No64, em_call_far), N,
3153 3154
	II(ImplicitOps | Stack, em_pushf, pushf),
	II(ImplicitOps | Stack, em_popf, popf), N, N,
3155
	/* 0xA0 - 0xA7 */
3156 3157 3158
	I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
	I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
	I2bv(SrcSI | DstDI | Mov | String, em_mov),
3159
	I2bv(SrcSI | DstDI | String, em_cmp),
3160
	/* 0xA8 - 0xAF */
3161
	I2bv(DstAcc | SrcImm, em_test),
3162 3163
	I2bv(SrcAcc | DstDI | Mov | String, em_mov),
	I2bv(SrcSI | DstAcc | Mov | String, em_mov),
3164
	I2bv(SrcAcc | DstDI | String, em_cmp),
3165
	/* 0xB0 - 0xB7 */
3166
	X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
3167
	/* 0xB8 - 0xBF */
3168
	X8(I(DstReg | SrcImm | Mov, em_mov)),
3169
	/* 0xC0 - 0xC7 */
3170
	D2bv(DstMem | SrcImmByte | ModRM),
3171
	I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
3172
	I(ImplicitOps | Stack, em_ret),
3173
	D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
3174
	G(ByteOp, group11), G(0, group11),
3175
	/* 0xC8 - 0xCF */
3176
	N, N, N, I(ImplicitOps | Stack, em_ret_far),
3177
	D(ImplicitOps), DI(SrcImmByte, intn),
3178
	D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
3179
	/* 0xD0 - 0xD7 */
3180
	D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
3181 3182 3183 3184
	N, N, N, N,
	/* 0xD8 - 0xDF */
	N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xE7 */
3185 3186
	X3(I(SrcImmByte, em_loop)),
	I(SrcImmByte, em_jcxz),
3187 3188
	D2bvIP(SrcImmUByte | DstAcc, in,  check_perm_in),
	D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
3189 3190
	/* 0xE8 - 0xEF */
	D(SrcImm | Stack), D(SrcImm | ImplicitOps),
3191
	I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
3192 3193
	D2bvIP(SrcDX | DstAcc, in,  check_perm_in),
	D2bvIP(SrcAcc | DstDX, out, check_perm_out),
3194
	/* 0xF0 - 0xF7 */
3195
	N, DI(ImplicitOps, icebp), N, N,
3196 3197
	DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
	G(ByteOp, group3), G(0, group3),
3198
	/* 0xF8 - 0xFF */
3199 3200
	D(ImplicitOps), D(ImplicitOps),
	I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
3201 3202 3203 3204 3205
	D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
};

static struct opcode twobyte_table[256] = {
	/* 0x00 - 0x0F */
3206
	G(0, group6), GD(0, &group7), N, N,
3207 3208
	N, I(ImplicitOps | VendorSpecific, em_syscall),
	II(ImplicitOps | Priv, em_clts, clts), N,
3209
	DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3210 3211 3212 3213
	N, D(ImplicitOps | ModRM), N, N,
	/* 0x10 - 0x1F */
	N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
	/* 0x20 - 0x2F */
3214
	DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3215
	DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
3216
	DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
3217
	DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
3218 3219 3220
	N, N, N, N,
	N, N, N, N, N, N, N, N,
	/* 0x30 - 0x3F */
3221 3222 3223 3224
	DI(ImplicitOps | Priv, wrmsr),
	IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
	DI(ImplicitOps | Priv, rdmsr),
	DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
3225 3226
	I(ImplicitOps | VendorSpecific, em_sysenter),
	I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
3227
	N, N,
3228 3229 3230 3231 3232 3233
	N, N, N, N, N, N, N, N,
	/* 0x40 - 0x4F */
	X16(D(DstReg | SrcMem | ModRM | Mov)),
	/* 0x50 - 0x5F */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0x60 - 0x6F */
3234 3235 3236 3237
	N, N, N, N,
	N, N, N, N,
	N, N, N, N,
	N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
3238
	/* 0x70 - 0x7F */
3239 3240 3241 3242
	N, N, N, N,
	N, N, N, N,
	N, N, N, N,
	N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
3243 3244 3245
	/* 0x80 - 0x8F */
	X16(D(SrcImm)),
	/* 0x90 - 0x9F */
3246
	X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
3247 3248
	/* 0xA0 - 0xA7 */
	D(ImplicitOps | Stack), D(ImplicitOps | Stack),
3249
	DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
3250 3251 3252 3253
	D(DstMem | SrcReg | Src2ImmByte | ModRM),
	D(DstMem | SrcReg | Src2CL | ModRM), N, N,
	/* 0xA8 - 0xAF */
	D(ImplicitOps | Stack), D(ImplicitOps | Stack),
3254
	DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3255 3256
	D(DstMem | SrcReg | Src2ImmByte | ModRM),
	D(DstMem | SrcReg | Src2CL | ModRM),
3257
	D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
3258
	/* 0xB0 - 0xB7 */
3259
	D2bv(DstMem | SrcReg | ModRM | Lock),
3260 3261 3262
	D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
	D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
	D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3263 3264
	/* 0xB8 - 0xBF */
	N, N,
3265
	G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3266 3267
	D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
	D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3268
	/* 0xC0 - 0xCF */
3269
	D2bv(DstMem | SrcReg | ModRM | Lock),
3270
	N, D(DstMem | SrcReg | ModRM | Mov),
3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285
	N, N, N, GD(0, &group9),
	N, N, N, N, N, N, N, N,
	/* 0xD0 - 0xDF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xEF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0xF0 - 0xFF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
};

#undef D
#undef N
#undef G
#undef GD
#undef I
3286
#undef GP
3287
#undef EXT
3288

3289
#undef D2bv
3290
#undef D2bvIP
3291
#undef I2bv
3292
#undef I6ALU
3293

3294
static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
3295 3296 3297
{
	unsigned size;

3298
	size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3299 3300 3301 3302 3303 3304 3305 3306 3307 3308 3309 3310
	if (size == 8)
		size = 4;
	return size;
}

static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
		      unsigned size, bool sign_extension)
{
	int rc = X86EMUL_CONTINUE;

	op->type = OP_IMM;
	op->bytes = size;
3311
	op->addr.mem.ea = ctxt->_eip;
3312 3313 3314
	/* NB. Immediates are sign-extended as necessary. */
	switch (op->bytes) {
	case 1:
3315
		op->val = insn_fetch(s8, ctxt);
3316 3317
		break;
	case 2:
3318
		op->val = insn_fetch(s16, ctxt);
3319 3320
		break;
	case 4:
3321
		op->val = insn_fetch(s32, ctxt);
3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340
		break;
	}
	if (!sign_extension) {
		switch (op->bytes) {
		case 1:
			op->val &= 0xff;
			break;
		case 2:
			op->val &= 0xffff;
			break;
		case 4:
			op->val &= 0xffffffff;
			break;
		}
	}
done:
	return rc;
}

3341 3342 3343 3344 3345 3346 3347 3348
static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
			  unsigned d)
{
	int rc = X86EMUL_CONTINUE;

	switch (d) {
	case OpReg:
		decode_register_operand(ctxt, op,
3349
			 op == &ctxt->dst &&
3350 3351 3352
			 ctxt->twobyte && (ctxt->b == 0xb6 || ctxt->b == 0xb7));
		break;
	case OpImmUByte:
3353
		rc = decode_imm(ctxt, op, 1, false);
3354 3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387
		break;
	case OpMem:
	case OpMem64:
		*op = ctxt->memop;
		ctxt->memopp = op;
		if (d == OpMem64)
			op->bytes = 8;
		else
			op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		if (ctxt->d & BitOp)
			fetch_bit_operand(ctxt);
		op->orig_val = op->val;
		break;
	case OpAcc:
		op->type = OP_REG;
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		op->addr.reg = &ctxt->regs[VCPU_REGS_RAX];
		fetch_register_operand(op);
		op->orig_val = op->val;
		break;
	case OpDI:
		op->type = OP_MEM;
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		op->addr.mem.ea =
			register_address(ctxt, ctxt->regs[VCPU_REGS_RDI]);
		op->addr.mem.seg = VCPU_SREG_ES;
		op->val = 0;
		break;
	case OpDX:
		op->type = OP_REG;
		op->bytes = 2;
		op->addr.reg = &ctxt->regs[VCPU_REGS_RDX];
		fetch_register_operand(op);
		break;
3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401
	case OpCL:
		op->bytes = 1;
		op->val = ctxt->regs[VCPU_REGS_RCX] & 0xff;
		break;
	case OpImmByte:
		rc = decode_imm(ctxt, op, 1, true);
		break;
	case OpOne:
		op->bytes = 1;
		op->val = 1;
		break;
	case OpImm:
		rc = decode_imm(ctxt, op, imm_size(ctxt), true);
		break;
3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412
	case OpImplicit:
		/* Special instructions do their own operand decoding. */
	default:
		op->type = OP_NONE; /* Disable writeback. */
		break;
	}

done:
	return rc;
}

3413
int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
3414 3415 3416
{
	int rc = X86EMUL_CONTINUE;
	int mode = ctxt->mode;
3417
	int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
3418
	bool op_prefix = false;
3419
	struct opcode opcode;
3420

3421 3422
	ctxt->memop.type = OP_NONE;
	ctxt->memopp = NULL;
3423 3424 3425
	ctxt->_eip = ctxt->eip;
	ctxt->fetch.start = ctxt->_eip;
	ctxt->fetch.end = ctxt->fetch.start + insn_len;
3426
	if (insn_len > 0)
3427
		memcpy(ctxt->fetch.data, insn, insn_len);
3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444

	switch (mode) {
	case X86EMUL_MODE_REAL:
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
		def_op_bytes = def_ad_bytes = 2;
		break;
	case X86EMUL_MODE_PROT32:
		def_op_bytes = def_ad_bytes = 4;
		break;
#ifdef CONFIG_X86_64
	case X86EMUL_MODE_PROT64:
		def_op_bytes = 4;
		def_ad_bytes = 8;
		break;
#endif
	default:
3445
		return EMULATION_FAILED;
3446 3447
	}

3448 3449
	ctxt->op_bytes = def_op_bytes;
	ctxt->ad_bytes = def_ad_bytes;
3450 3451 3452

	/* Legacy prefixes. */
	for (;;) {
3453
		switch (ctxt->b = insn_fetch(u8, ctxt)) {
3454
		case 0x66:	/* operand-size override */
3455
			op_prefix = true;
3456
			/* switch between 2/4 bytes */
3457
			ctxt->op_bytes = def_op_bytes ^ 6;
3458 3459 3460 3461
			break;
		case 0x67:	/* address-size override */
			if (mode == X86EMUL_MODE_PROT64)
				/* switch between 4/8 bytes */
3462
				ctxt->ad_bytes = def_ad_bytes ^ 12;
3463 3464
			else
				/* switch between 2/4 bytes */
3465
				ctxt->ad_bytes = def_ad_bytes ^ 6;
3466 3467 3468 3469 3470
			break;
		case 0x26:	/* ES override */
		case 0x2e:	/* CS override */
		case 0x36:	/* SS override */
		case 0x3e:	/* DS override */
3471
			set_seg_override(ctxt, (ctxt->b >> 3) & 3);
3472 3473 3474
			break;
		case 0x64:	/* FS override */
		case 0x65:	/* GS override */
3475
			set_seg_override(ctxt, ctxt->b & 7);
3476 3477 3478 3479
			break;
		case 0x40 ... 0x4f: /* REX */
			if (mode != X86EMUL_MODE_PROT64)
				goto done_prefixes;
3480
			ctxt->rex_prefix = ctxt->b;
3481 3482
			continue;
		case 0xf0:	/* LOCK */
3483
			ctxt->lock_prefix = 1;
3484 3485 3486
			break;
		case 0xf2:	/* REPNE/REPNZ */
		case 0xf3:	/* REP/REPE/REPZ */
3487
			ctxt->rep_prefix = ctxt->b;
3488 3489 3490 3491 3492 3493 3494
			break;
		default:
			goto done_prefixes;
		}

		/* Any legacy prefix after a REX prefix nullifies its effect. */

3495
		ctxt->rex_prefix = 0;
3496 3497 3498 3499 3500
	}

done_prefixes:

	/* REX prefix. */
3501 3502
	if (ctxt->rex_prefix & 8)
		ctxt->op_bytes = 8;	/* REX.W */
3503 3504

	/* Opcode byte(s). */
3505
	opcode = opcode_table[ctxt->b];
3506
	/* Two-byte opcode? */
3507 3508
	if (ctxt->b == 0x0f) {
		ctxt->twobyte = 1;
3509
		ctxt->b = insn_fetch(u8, ctxt);
3510
		opcode = twobyte_table[ctxt->b];
3511
	}
3512
	ctxt->d = opcode.flags;
3513

3514 3515
	while (ctxt->d & GroupMask) {
		switch (ctxt->d & GroupMask) {
3516
		case Group:
3517
			ctxt->modrm = insn_fetch(u8, ctxt);
3518 3519
			--ctxt->_eip;
			goffset = (ctxt->modrm >> 3) & 7;
3520 3521 3522
			opcode = opcode.u.group[goffset];
			break;
		case GroupDual:
3523
			ctxt->modrm = insn_fetch(u8, ctxt);
3524 3525 3526
			--ctxt->_eip;
			goffset = (ctxt->modrm >> 3) & 7;
			if ((ctxt->modrm >> 6) == 3)
3527 3528 3529 3530 3531
				opcode = opcode.u.gdual->mod3[goffset];
			else
				opcode = opcode.u.gdual->mod012[goffset];
			break;
		case RMExt:
3532
			goffset = ctxt->modrm & 7;
3533
			opcode = opcode.u.group[goffset];
3534 3535
			break;
		case Prefix:
3536
			if (ctxt->rep_prefix && op_prefix)
3537
				return EMULATION_FAILED;
3538
			simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
3539 3540 3541 3542 3543 3544 3545 3546
			switch (simd_prefix) {
			case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
			case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
			case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
			case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
			}
			break;
		default:
3547
			return EMULATION_FAILED;
3548
		}
3549

3550
		ctxt->d &= ~(u64)GroupMask;
3551
		ctxt->d |= opcode.flags;
3552 3553
	}

3554 3555 3556
	ctxt->execute = opcode.u.execute;
	ctxt->check_perm = opcode.check_perm;
	ctxt->intercept = opcode.intercept;
3557 3558

	/* Unrecognised? */
3559
	if (ctxt->d == 0 || (ctxt->d & Undefined))
3560
		return EMULATION_FAILED;
3561

3562
	if (!(ctxt->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
3563
		return EMULATION_FAILED;
3564

3565 3566
	if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
		ctxt->op_bytes = 8;
3567

3568
	if (ctxt->d & Op3264) {
3569
		if (mode == X86EMUL_MODE_PROT64)
3570
			ctxt->op_bytes = 8;
3571
		else
3572
			ctxt->op_bytes = 4;
3573 3574
	}

3575 3576
	if (ctxt->d & Sse)
		ctxt->op_bytes = 16;
A
Avi Kivity 已提交
3577

3578
	/* ModRM and SIB bytes. */
3579
	if (ctxt->d & ModRM) {
3580
		rc = decode_modrm(ctxt, &ctxt->memop);
3581 3582 3583
		if (!ctxt->has_seg_override)
			set_seg_override(ctxt, ctxt->modrm_seg);
	} else if (ctxt->d & MemAbs)
3584
		rc = decode_abs(ctxt, &ctxt->memop);
3585 3586 3587
	if (rc != X86EMUL_CONTINUE)
		goto done;

3588 3589
	if (!ctxt->has_seg_override)
		set_seg_override(ctxt, VCPU_SREG_DS);
3590

3591
	ctxt->memop.addr.mem.seg = seg_override(ctxt);
3592

3593 3594
	if (ctxt->memop.type == OP_MEM && ctxt->ad_bytes != 8)
		ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;
3595 3596 3597 3598 3599

	/*
	 * Decode and fetch the source operand: register, memory
	 * or immediate.
	 */
3600
	switch (ctxt->d & SrcMask) {
3601 3602 3603
	case SrcNone:
		break;
	case SrcReg:
3604
		decode_register_operand(ctxt, &ctxt->src, 0);
3605 3606
		break;
	case SrcMem16:
3607
		ctxt->memop.bytes = 2;
3608 3609
		goto srcmem_common;
	case SrcMem32:
3610
		ctxt->memop.bytes = 4;
3611 3612
		goto srcmem_common;
	case SrcMem:
3613
		ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
3614
	srcmem_common:
3615 3616
		ctxt->src = ctxt->memop;
		ctxt->memopp = &ctxt->src;
3617
		break;
3618
	case SrcImmU16:
3619
		rc = decode_imm(ctxt, &ctxt->src, 2, false);
3620
		break;
3621
	case SrcImm:
3622
		rc = decode_imm(ctxt, &ctxt->src, imm_size(ctxt), true);
3623
		break;
3624
	case SrcImmU:
3625
		rc = decode_imm(ctxt, &ctxt->src, imm_size(ctxt), false);
3626 3627
		break;
	case SrcImmByte:
3628
		rc = decode_imm(ctxt, &ctxt->src, 1, true);
3629
		break;
3630
	case SrcImmUByte:
3631
		rc = decode_imm(ctxt, &ctxt->src, 1, false);
3632 3633
		break;
	case SrcAcc:
3634 3635 3636 3637
		ctxt->src.type = OP_REG;
		ctxt->src.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		ctxt->src.addr.reg = &ctxt->regs[VCPU_REGS_RAX];
		fetch_register_operand(&ctxt->src);
3638 3639
		break;
	case SrcOne:
3640 3641
		ctxt->src.bytes = 1;
		ctxt->src.val = 1;
3642 3643
		break;
	case SrcSI:
3644 3645 3646 3647 3648 3649
		ctxt->src.type = OP_MEM;
		ctxt->src.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		ctxt->src.addr.mem.ea =
			register_address(ctxt, ctxt->regs[VCPU_REGS_RSI]);
		ctxt->src.addr.mem.seg = seg_override(ctxt);
		ctxt->src.val = 0;
3650 3651
		break;
	case SrcImmFAddr:
3652 3653 3654
		ctxt->src.type = OP_IMM;
		ctxt->src.addr.mem.ea = ctxt->_eip;
		ctxt->src.bytes = ctxt->op_bytes + 2;
3655
		insn_fetch_arr(ctxt->src.valptr, ctxt->src.bytes, ctxt);
3656 3657
		break;
	case SrcMemFAddr:
3658
		ctxt->memop.bytes = ctxt->op_bytes + 2;
3659
		goto srcmem_common;
3660
		break;
3661
	case SrcDX:
3662 3663 3664 3665
		ctxt->src.type = OP_REG;
		ctxt->src.bytes = 2;
		ctxt->src.addr.reg = &ctxt->regs[VCPU_REGS_RDX];
		fetch_register_operand(&ctxt->src);
3666
		break;
3667 3668
	}

3669 3670 3671
	if (rc != X86EMUL_CONTINUE)
		goto done;

3672 3673 3674 3675
	/*
	 * Decode and fetch the second source operand: register, memory
	 * or immediate.
	 */
3676
	rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
3677 3678 3679
	if (rc != X86EMUL_CONTINUE)
		goto done;

3680
	/* Decode and fetch the destination operand: register or memory. */
3681
	rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
3682 3683

done:
3684 3685
	if (ctxt->memopp && ctxt->memopp->type == OP_MEM && ctxt->rip_relative)
		ctxt->memopp->addr.mem.ea += ctxt->_eip;
3686

3687
	return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
3688 3689
}

3690 3691 3692 3693 3694 3695 3696 3697 3698
static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
{
	/* The second termination condition only applies for REPE
	 * and REPNE. Test if the repeat string operation prefix is
	 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
	 * corresponding termination condition according to:
	 * 	- if REPE/REPZ and ZF = 0 then done
	 * 	- if REPNE/REPNZ and ZF = 1 then done
	 */
3699 3700 3701
	if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
	     (ctxt->b == 0xae) || (ctxt->b == 0xaf))
	    && (((ctxt->rep_prefix == REPE_PREFIX) &&
3702
		 ((ctxt->eflags & EFLG_ZF) == 0))
3703
		|| ((ctxt->rep_prefix == REPNE_PREFIX) &&
3704 3705 3706 3707 3708 3709
		    ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
		return true;

	return false;
}

3710
int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
3711
{
3712
	struct x86_emulate_ops *ops = ctxt->ops;
3713
	u64 msr_data;
3714
	int rc = X86EMUL_CONTINUE;
3715
	int saved_dst_type = ctxt->dst.type;
3716

3717
	ctxt->mem_read.pos = 0;
3718

3719
	if (ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) {
3720
		rc = emulate_ud(ctxt);
3721 3722 3723
		goto done;
	}

3724
	/* LOCK prefix is allowed only with some instructions */
3725
	if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
3726
		rc = emulate_ud(ctxt);
3727 3728 3729
		goto done;
	}

3730
	if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
3731
		rc = emulate_ud(ctxt);
3732 3733 3734
		goto done;
	}

3735
	if ((ctxt->d & Sse)
3736 3737
	    && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)
		|| !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
A
Avi Kivity 已提交
3738 3739 3740 3741
		rc = emulate_ud(ctxt);
		goto done;
	}

3742
	if ((ctxt->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
A
Avi Kivity 已提交
3743 3744 3745 3746
		rc = emulate_nm(ctxt);
		goto done;
	}

3747 3748
	if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
		rc = emulator_check_intercept(ctxt, ctxt->intercept,
3749
					      X86_ICPT_PRE_EXCEPT);
3750 3751 3752 3753
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

3754
	/* Privileged instruction can be executed only in CPL=0 */
3755
	if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
3756
		rc = emulate_gp(ctxt, 0);
3757 3758 3759
		goto done;
	}

3760
	/* Instruction can only be executed in protected mode */
3761
	if ((ctxt->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
3762 3763 3764 3765
		rc = emulate_ud(ctxt);
		goto done;
	}

3766
	/* Do instruction specific permission checks */
3767 3768
	if (ctxt->check_perm) {
		rc = ctxt->check_perm(ctxt);
3769 3770 3771 3772
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

3773 3774
	if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
		rc = emulator_check_intercept(ctxt, ctxt->intercept,
3775
					      X86_ICPT_POST_EXCEPT);
3776 3777 3778 3779
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

3780
	if (ctxt->rep_prefix && (ctxt->d & String)) {
3781
		/* All REP prefixes have the same first termination condition */
3782 3783
		if (address_mask(ctxt, ctxt->regs[VCPU_REGS_RCX]) == 0) {
			ctxt->eip = ctxt->_eip;
3784 3785 3786 3787
			goto done;
		}
	}

3788 3789 3790
	if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
		rc = segmented_read(ctxt, ctxt->src.addr.mem,
				    ctxt->src.valptr, ctxt->src.bytes);
3791
		if (rc != X86EMUL_CONTINUE)
3792
			goto done;
3793
		ctxt->src.orig_val64 = ctxt->src.val64;
3794 3795
	}

3796 3797 3798
	if (ctxt->src2.type == OP_MEM) {
		rc = segmented_read(ctxt, ctxt->src2.addr.mem,
				    &ctxt->src2.val, ctxt->src2.bytes);
3799 3800 3801 3802
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

3803
	if ((ctxt->d & DstMask) == ImplicitOps)
3804 3805 3806
		goto special_insn;


3807
	if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
3808
		/* optimisation - avoid slow emulated read if Mov */
3809 3810
		rc = segmented_read(ctxt, ctxt->dst.addr.mem,
				   &ctxt->dst.val, ctxt->dst.bytes);
3811 3812
		if (rc != X86EMUL_CONTINUE)
			goto done;
3813
	}
3814
	ctxt->dst.orig_val = ctxt->dst.val;
3815

3816 3817
special_insn:

3818 3819
	if (unlikely(ctxt->guest_mode) && ctxt->intercept) {
		rc = emulator_check_intercept(ctxt, ctxt->intercept,
3820
					      X86_ICPT_POST_MEMACCESS);
3821 3822 3823 3824
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

3825 3826
	if (ctxt->execute) {
		rc = ctxt->execute(ctxt);
3827 3828 3829 3830 3831
		if (rc != X86EMUL_CONTINUE)
			goto done;
		goto writeback;
	}

3832
	if (ctxt->twobyte)
A
Avi Kivity 已提交
3833 3834
		goto twobyte_insn;

3835
	switch (ctxt->b) {
3836
	case 0x06:		/* push es */
3837
		rc = emulate_push_sreg(ctxt, VCPU_SREG_ES);
3838 3839
		break;
	case 0x07:		/* pop es */
3840
		rc = emulate_pop_sreg(ctxt, VCPU_SREG_ES);
3841 3842
		break;
	case 0x0e:		/* push cs */
3843
		rc = emulate_push_sreg(ctxt, VCPU_SREG_CS);
3844 3845
		break;
	case 0x16:		/* push ss */
3846
		rc = emulate_push_sreg(ctxt, VCPU_SREG_SS);
3847 3848
		break;
	case 0x17:		/* pop ss */
3849
		rc = emulate_pop_sreg(ctxt, VCPU_SREG_SS);
3850 3851
		break;
	case 0x1e:		/* push ds */
3852
		rc = emulate_push_sreg(ctxt, VCPU_SREG_DS);
3853 3854
		break;
	case 0x1f:		/* pop ds */
3855
		rc = emulate_pop_sreg(ctxt, VCPU_SREG_DS);
3856
		break;
3857
	case 0x40 ... 0x47: /* inc r16/r32 */
3858
		emulate_1op(ctxt, "inc");
3859 3860
		break;
	case 0x48 ... 0x4f: /* dec r16/r32 */
3861
		emulate_1op(ctxt, "dec");
3862
		break;
A
Avi Kivity 已提交
3863
	case 0x63:		/* movsxd */
3864
		if (ctxt->mode != X86EMUL_MODE_PROT64)
A
Avi Kivity 已提交
3865
			goto cannot_emulate;
3866
		ctxt->dst.val = (s32) ctxt->src.val;
A
Avi Kivity 已提交
3867
		break;
3868 3869
	case 0x6c:		/* insb */
	case 0x6d:		/* insw/insd */
3870
		ctxt->src.val = ctxt->regs[VCPU_REGS_RDX];
3871
		goto do_io_in;
3872 3873
	case 0x6e:		/* outsb */
	case 0x6f:		/* outsw/outsd */
3874
		ctxt->dst.val = ctxt->regs[VCPU_REGS_RDX];
3875
		goto do_io_out;
3876
		break;
3877
	case 0x70 ... 0x7f: /* jcc (short) */
3878 3879
		if (test_cc(ctxt->b, ctxt->eflags))
			jmp_rel(ctxt, ctxt->src.val);
3880
		break;
N
Nitin A Kamble 已提交
3881
	case 0x8d: /* lea r16/r32, m */
3882
		ctxt->dst.val = ctxt->src.addr.mem.ea;
N
Nitin A Kamble 已提交
3883
		break;
A
Avi Kivity 已提交
3884
	case 0x8f:		/* pop (sole member of Grp1a) */
3885
		rc = em_grp1a(ctxt);
A
Avi Kivity 已提交
3886
		break;
3887
	case 0x90 ... 0x97: /* nop / xchg reg, rax */
3888
		if (ctxt->dst.addr.reg == &ctxt->regs[VCPU_REGS_RAX])
3889
			break;
3890 3891
		rc = em_xchg(ctxt);
		break;
3892
	case 0x98: /* cbw/cwde/cdqe */
3893 3894 3895 3896
		switch (ctxt->op_bytes) {
		case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
		case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
		case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
3897 3898
		}
		break;
3899
	case 0xc0 ... 0xc1:
3900
		rc = em_grp2(ctxt);
3901
		break;
3902
	case 0xc4:		/* les */
3903
		rc = emulate_load_segment(ctxt, VCPU_SREG_ES);
3904 3905
		break;
	case 0xc5:		/* lds */
3906
		rc = emulate_load_segment(ctxt, VCPU_SREG_DS);
3907
		break;
3908
	case 0xcc:		/* int3 */
3909 3910
		rc = emulate_int(ctxt, 3);
		break;
3911
	case 0xcd:		/* int n */
3912
		rc = emulate_int(ctxt, ctxt->src.val);
3913 3914
		break;
	case 0xce:		/* into */
3915 3916
		if (ctxt->eflags & EFLG_OF)
			rc = emulate_int(ctxt, 4);
3917
		break;
3918
	case 0xd0 ... 0xd1:	/* Grp2 */
3919
		rc = em_grp2(ctxt);
3920 3921
		break;
	case 0xd2 ... 0xd3:	/* Grp2 */
3922
		ctxt->src.val = ctxt->regs[VCPU_REGS_RCX];
3923
		rc = em_grp2(ctxt);
3924
		break;
3925 3926
	case 0xe4: 	/* inb */
	case 0xe5: 	/* in */
3927
		goto do_io_in;
3928 3929
	case 0xe6: /* outb */
	case 0xe7: /* out */
3930
		goto do_io_out;
3931
	case 0xe8: /* call (near) */ {
3932 3933 3934
		long int rel = ctxt->src.val;
		ctxt->src.val = (unsigned long) ctxt->_eip;
		jmp_rel(ctxt, rel);
3935
		rc = em_push(ctxt);
3936
		break;
3937 3938
	}
	case 0xe9: /* jmp rel */
3939
	case 0xeb: /* jmp rel short */
3940 3941
		jmp_rel(ctxt, ctxt->src.val);
		ctxt->dst.type = OP_NONE; /* Disable writeback. */
3942
		break;
3943 3944
	case 0xec: /* in al,dx */
	case 0xed: /* in (e/r)ax,dx */
3945
	do_io_in:
3946 3947
		if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
				     &ctxt->dst.val))
3948 3949
			goto done; /* IO is needed */
		break;
3950 3951
	case 0xee: /* out dx,al */
	case 0xef: /* out dx,(e/r)ax */
3952
	do_io_out:
3953 3954 3955
		ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
				      &ctxt->src.val, 1);
		ctxt->dst.type = OP_NONE;	/* Disable writeback. */
3956
		break;
3957
	case 0xf4:              /* hlt */
3958
		ctxt->ops->halt(ctxt);
3959
		break;
3960 3961 3962 3963 3964 3965 3966
	case 0xf5:	/* cmc */
		/* complement carry flag from eflags reg */
		ctxt->eflags ^= EFLG_CF;
		break;
	case 0xf8: /* clc */
		ctxt->eflags &= ~EFLG_CF;
		break;
3967 3968 3969
	case 0xf9: /* stc */
		ctxt->eflags |= EFLG_CF;
		break;
3970 3971 3972 3973 3974 3975
	case 0xfc: /* cld */
		ctxt->eflags &= ~EFLG_DF;
		break;
	case 0xfd: /* std */
		ctxt->eflags |= EFLG_DF;
		break;
3976
	case 0xfe: /* Grp4 */
3977
		rc = em_grp45(ctxt);
3978
		break;
3979
	case 0xff: /* Grp5 */
3980 3981
		rc = em_grp45(ctxt);
		break;
3982 3983
	default:
		goto cannot_emulate;
A
Avi Kivity 已提交
3984
	}
3985

3986 3987 3988
	if (rc != X86EMUL_CONTINUE)
		goto done;

3989
writeback:
3990
	rc = writeback(ctxt);
3991
	if (rc != X86EMUL_CONTINUE)
3992 3993
		goto done;

3994 3995 3996 3997
	/*
	 * restore dst type in case the decoding will be reused
	 * (happens for string instruction )
	 */
3998
	ctxt->dst.type = saved_dst_type;
3999

4000 4001 4002
	if ((ctxt->d & SrcMask) == SrcSI)
		string_addr_inc(ctxt, seg_override(ctxt),
				VCPU_REGS_RSI, &ctxt->src);
4003

4004
	if ((ctxt->d & DstMask) == DstDI)
4005
		string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
4006
				&ctxt->dst);
4007

4008 4009 4010
	if (ctxt->rep_prefix && (ctxt->d & String)) {
		struct read_cache *r = &ctxt->io_read;
		register_address_increment(ctxt, &ctxt->regs[VCPU_REGS_RCX], -1);
4011

4012 4013 4014 4015 4016
		if (!string_insn_completed(ctxt)) {
			/*
			 * Re-enter guest when pio read ahead buffer is empty
			 * or, if it is not used, after each 1024 iteration.
			 */
4017
			if ((r->end != 0 || ctxt->regs[VCPU_REGS_RCX] & 0x3ff) &&
4018 4019 4020 4021 4022 4023
			    (r->end == 0 || r->end != r->pos)) {
				/*
				 * Reset read cache. Usually happens before
				 * decode, but since instruction is restarted
				 * we have to do it here.
				 */
4024
				ctxt->mem_read.end = 0;
4025 4026 4027
				return EMULATION_RESTART;
			}
			goto done; /* skip rip writeback */
4028
		}
4029
	}
4030

4031
	ctxt->eip = ctxt->_eip;
4032 4033

done:
4034 4035
	if (rc == X86EMUL_PROPAGATE_FAULT)
		ctxt->have_exception = true;
4036 4037 4038
	if (rc == X86EMUL_INTERCEPTED)
		return EMULATION_INTERCEPTED;

4039
	return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
A
Avi Kivity 已提交
4040 4041

twobyte_insn:
4042
	switch (ctxt->b) {
4043
	case 0x09:		/* wbinvd */
4044
		(ctxt->ops->wbinvd)(ctxt);
4045 4046
		break;
	case 0x08:		/* invd */
4047 4048 4049 4050
	case 0x0d:		/* GrpP (prefetch) */
	case 0x18:		/* Grp16 (prefetch/nop) */
		break;
	case 0x20: /* mov cr, reg */
4051
		ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
4052
		break;
A
Avi Kivity 已提交
4053
	case 0x21: /* mov from dr to reg */
4054
		ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
A
Avi Kivity 已提交
4055
		break;
4056
	case 0x22: /* mov reg, cr */
4057
		if (ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val)) {
4058
			emulate_gp(ctxt, 0);
4059
			rc = X86EMUL_PROPAGATE_FAULT;
4060 4061
			goto done;
		}
4062
		ctxt->dst.type = OP_NONE;
4063
		break;
A
Avi Kivity 已提交
4064
	case 0x23: /* mov from reg to dr */
4065
		if (ops->set_dr(ctxt, ctxt->modrm_reg, ctxt->src.val &
4066
				((ctxt->mode == X86EMUL_MODE_PROT64) ?
4067
				 ~0ULL : ~0U)) < 0) {
4068
			/* #UD condition is already handled by the code above */
4069
			emulate_gp(ctxt, 0);
4070
			rc = X86EMUL_PROPAGATE_FAULT;
4071 4072 4073
			goto done;
		}

4074
		ctxt->dst.type = OP_NONE;	/* no writeback */
A
Avi Kivity 已提交
4075
		break;
4076 4077
	case 0x30:
		/* wrmsr */
4078 4079 4080
		msr_data = (u32)ctxt->regs[VCPU_REGS_RAX]
			| ((u64)ctxt->regs[VCPU_REGS_RDX] << 32);
		if (ops->set_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], msr_data)) {
4081
			emulate_gp(ctxt, 0);
4082
			rc = X86EMUL_PROPAGATE_FAULT;
4083
			goto done;
4084 4085 4086 4087 4088
		}
		rc = X86EMUL_CONTINUE;
		break;
	case 0x32:
		/* rdmsr */
4089
		if (ops->get_msr(ctxt, ctxt->regs[VCPU_REGS_RCX], &msr_data)) {
4090
			emulate_gp(ctxt, 0);
4091
			rc = X86EMUL_PROPAGATE_FAULT;
4092
			goto done;
4093
		} else {
4094 4095
			ctxt->regs[VCPU_REGS_RAX] = (u32)msr_data;
			ctxt->regs[VCPU_REGS_RDX] = msr_data >> 32;
4096 4097 4098
		}
		rc = X86EMUL_CONTINUE;
		break;
A
Avi Kivity 已提交
4099
	case 0x40 ... 0x4f:	/* cmov */
4100 4101 4102
		ctxt->dst.val = ctxt->dst.orig_val = ctxt->src.val;
		if (!test_cc(ctxt->b, ctxt->eflags))
			ctxt->dst.type = OP_NONE; /* no writeback */
A
Avi Kivity 已提交
4103
		break;
4104
	case 0x80 ... 0x8f: /* jnz rel, etc*/
4105 4106
		if (test_cc(ctxt->b, ctxt->eflags))
			jmp_rel(ctxt, ctxt->src.val);
4107
		break;
4108
	case 0x90 ... 0x9f:     /* setcc r/m8 */
4109
		ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
4110
		break;
4111
	case 0xa0:	  /* push fs */
4112
		rc = emulate_push_sreg(ctxt, VCPU_SREG_FS);
4113 4114
		break;
	case 0xa1:	 /* pop fs */
4115
		rc = emulate_pop_sreg(ctxt, VCPU_SREG_FS);
4116
		break;
4117 4118
	case 0xa3:
	      bt:		/* bt */
4119
		ctxt->dst.type = OP_NONE;
4120
		/* only subword offset */
4121
		ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
4122
		emulate_2op_SrcV_nobyte(ctxt, "bt");
4123
		break;
4124 4125
	case 0xa4: /* shld imm8, r, r/m */
	case 0xa5: /* shld cl, r, r/m */
4126
		emulate_2op_cl(ctxt, "shld");
4127
		break;
4128
	case 0xa8:	/* push gs */
4129
		rc = emulate_push_sreg(ctxt, VCPU_SREG_GS);
4130 4131
		break;
	case 0xa9:	/* pop gs */
4132
		rc = emulate_pop_sreg(ctxt, VCPU_SREG_GS);
4133
		break;
4134 4135
	case 0xab:
	      bts:		/* bts */
4136
		emulate_2op_SrcV_nobyte(ctxt, "bts");
4137
		break;
4138 4139
	case 0xac: /* shrd imm8, r, r/m */
	case 0xad: /* shrd cl, r, r/m */
4140
		emulate_2op_cl(ctxt, "shrd");
4141
		break;
4142 4143
	case 0xae:              /* clflush */
		break;
A
Avi Kivity 已提交
4144 4145 4146 4147 4148
	case 0xb0 ... 0xb1:	/* cmpxchg */
		/*
		 * Save real source value, then compare EAX against
		 * destination.
		 */
4149 4150
		ctxt->src.orig_val = ctxt->src.val;
		ctxt->src.val = ctxt->regs[VCPU_REGS_RAX];
4151
		emulate_2op_SrcV(ctxt, "cmp");
4152
		if (ctxt->eflags & EFLG_ZF) {
A
Avi Kivity 已提交
4153
			/* Success: write back to memory. */
4154
			ctxt->dst.val = ctxt->src.orig_val;
A
Avi Kivity 已提交
4155 4156
		} else {
			/* Failure: write the value we saw to EAX. */
4157 4158
			ctxt->dst.type = OP_REG;
			ctxt->dst.addr.reg = (unsigned long *)&ctxt->regs[VCPU_REGS_RAX];
A
Avi Kivity 已提交
4159 4160
		}
		break;
4161
	case 0xb2:		/* lss */
4162
		rc = emulate_load_segment(ctxt, VCPU_SREG_SS);
4163
		break;
A
Avi Kivity 已提交
4164 4165
	case 0xb3:
	      btr:		/* btr */
4166
		emulate_2op_SrcV_nobyte(ctxt, "btr");
A
Avi Kivity 已提交
4167
		break;
4168
	case 0xb4:		/* lfs */
4169
		rc = emulate_load_segment(ctxt, VCPU_SREG_FS);
4170 4171
		break;
	case 0xb5:		/* lgs */
4172
		rc = emulate_load_segment(ctxt, VCPU_SREG_GS);
4173
		break;
A
Avi Kivity 已提交
4174
	case 0xb6 ... 0xb7:	/* movzx */
4175 4176 4177
		ctxt->dst.bytes = ctxt->op_bytes;
		ctxt->dst.val = (ctxt->d & ByteOp) ? (u8) ctxt->src.val
						       : (u16) ctxt->src.val;
A
Avi Kivity 已提交
4178 4179
		break;
	case 0xba:		/* Grp8 */
4180
		switch (ctxt->modrm_reg & 3) {
A
Avi Kivity 已提交
4181 4182 4183 4184 4185 4186 4187 4188 4189 4190
		case 0:
			goto bt;
		case 1:
			goto bts;
		case 2:
			goto btr;
		case 3:
			goto btc;
		}
		break;
4191 4192
	case 0xbb:
	      btc:		/* btc */
4193
		emulate_2op_SrcV_nobyte(ctxt, "btc");
4194
		break;
4195 4196 4197
	case 0xbc: {		/* bsf */
		u8 zf;
		__asm__ ("bsf %2, %0; setz %1"
4198 4199
			 : "=r"(ctxt->dst.val), "=q"(zf)
			 : "r"(ctxt->src.val));
4200 4201 4202
		ctxt->eflags &= ~X86_EFLAGS_ZF;
		if (zf) {
			ctxt->eflags |= X86_EFLAGS_ZF;
4203
			ctxt->dst.type = OP_NONE;	/* Disable writeback. */
4204 4205 4206 4207 4208 4209
		}
		break;
	}
	case 0xbd: {		/* bsr */
		u8 zf;
		__asm__ ("bsr %2, %0; setz %1"
4210 4211
			 : "=r"(ctxt->dst.val), "=q"(zf)
			 : "r"(ctxt->src.val));
4212 4213 4214
		ctxt->eflags &= ~X86_EFLAGS_ZF;
		if (zf) {
			ctxt->eflags |= X86_EFLAGS_ZF;
4215
			ctxt->dst.type = OP_NONE;	/* Disable writeback. */
4216 4217 4218
		}
		break;
	}
A
Avi Kivity 已提交
4219
	case 0xbe ... 0xbf:	/* movsx */
4220 4221 4222
		ctxt->dst.bytes = ctxt->op_bytes;
		ctxt->dst.val = (ctxt->d & ByteOp) ? (s8) ctxt->src.val :
							(s16) ctxt->src.val;
A
Avi Kivity 已提交
4223
		break;
4224
	case 0xc0 ... 0xc1:	/* xadd */
4225
		emulate_2op_SrcV(ctxt, "add");
4226
		/* Write back the register source. */
4227 4228
		ctxt->src.val = ctxt->dst.orig_val;
		write_register_operand(&ctxt->src);
4229
		break;
4230
	case 0xc3:		/* movnti */
4231 4232 4233
		ctxt->dst.bytes = ctxt->op_bytes;
		ctxt->dst.val = (ctxt->op_bytes == 4) ? (u32) ctxt->src.val :
							(u64) ctxt->src.val;
4234
		break;
A
Avi Kivity 已提交
4235
	case 0xc7:		/* Grp9 (cmpxchg8b) */
4236
		rc = em_grp9(ctxt);
4237
		break;
4238 4239
	default:
		goto cannot_emulate;
A
Avi Kivity 已提交
4240
	}
4241 4242 4243 4244

	if (rc != X86EMUL_CONTINUE)
		goto done;

A
Avi Kivity 已提交
4245 4246 4247
	goto writeback;

cannot_emulate:
4248
	return EMULATION_FAILED;
A
Avi Kivity 已提交
4249
}