emulate.c 110.1 KB
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/******************************************************************************
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 * emulate.c
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 *
 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
 *
 * Copyright (c) 2005 Keir Fraser
 *
 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
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 * privileged instructions:
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 *
 * Copyright (C) 2006 Qumranet
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 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
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 *
 *   Avi Kivity <avi@qumranet.com>
 *   Yaniv Kamay <yaniv@qumranet.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
 */

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#include <linux/kvm_host.h>
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#include "kvm_cache_regs.h"
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#include <linux/module.h>
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#include <asm/kvm_emulate.h>
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#include "x86.h"
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#include "tss.h"
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/*
 * Opcode effective-address decode tables.
 * Note that we only emulate instructions that have at least one memory
 * operand (excluding implicit stack references). We assume that stack
 * references and instruction fetches will never occur in special memory
 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
 * not be handled.
 */

/* Operand sizes: 8-bit operands or specified/overridden size. */
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#define ByteOp      (1<<0)	/* 8-bit operands. */
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/* Destination operand type. */
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#define ImplicitOps (1<<1)	/* Implicit in opcode. No generic decode. */
#define DstReg      (2<<1)	/* Register operand. */
#define DstMem      (3<<1)	/* Memory operand. */
#define DstAcc      (4<<1)	/* Destination Accumulator */
#define DstDI       (5<<1)	/* Destination is in ES:(E)DI */
#define DstMem64    (6<<1)	/* 64bit memory operand */
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#define DstImmUByte (7<<1)	/* 8-bit unsigned immediate operand */
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#define DstDX       (8<<1)	/* Destination is in DX register */
#define DstMask     (0xf<<1)
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/* Source operand type. */
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#define SrcNone     (0<<5)	/* No source operand. */
#define SrcReg      (1<<5)	/* Register operand. */
#define SrcMem      (2<<5)	/* Memory operand. */
#define SrcMem16    (3<<5)	/* Memory operand (16-bit). */
#define SrcMem32    (4<<5)	/* Memory operand (32-bit). */
#define SrcImm      (5<<5)	/* Immediate operand. */
#define SrcImmByte  (6<<5)	/* 8-bit sign-extended immediate operand. */
#define SrcOne      (7<<5)	/* Implied '1' */
#define SrcImmUByte (8<<5)      /* 8-bit unsigned immediate operand. */
#define SrcImmU     (9<<5)      /* Immediate operand, unsigned */
#define SrcSI       (0xa<<5)	/* Source is in the DS:RSI */
#define SrcImmFAddr (0xb<<5)	/* Source is immediate far address */
#define SrcMemFAddr (0xc<<5)	/* Source is far address in memory */
#define SrcAcc      (0xd<<5)	/* Source Accumulator */
#define SrcImmU16   (0xe<<5)    /* Immediate operand, unsigned, 16 bits */
#define SrcDX       (0xf<<5)	/* Source is in DX register */
#define SrcMask     (0xf<<5)
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/* Generic ModRM decode. */
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#define ModRM       (1<<9)
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/* Destination is only written; never read. */
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#define Mov         (1<<10)
#define BitOp       (1<<11)
#define MemAbs      (1<<12)      /* Memory operand is absolute displacement */
#define String      (1<<13)     /* String instruction (rep capable) */
#define Stack       (1<<14)     /* Stack instruction (push/pop) */
#define GroupMask   (7<<15)     /* Opcode uses one of the group mechanisms */
#define Group       (1<<15)     /* Bits 3:5 of modrm byte extend opcode */
#define GroupDual   (2<<15)     /* Alternate decoding of mod == 3 */
#define Prefix      (3<<15)     /* Instruction varies with 66/f2/f3 prefix */
#define RMExt       (4<<15)     /* Opcode extension in ModRM r/m if mod == 3 */
#define Sse         (1<<18)     /* SSE Vector instruction */
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/* Misc flags */
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#define Prot        (1<<21) /* instruction generates #UD if not in prot-mode */
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#define VendorSpecific (1<<22) /* Vendor specific instruction */
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#define NoAccess    (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
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#define Op3264      (1<<24) /* Operand is 64b in long mode, 32b otherwise */
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#define Undefined   (1<<25) /* No Such Instruction */
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#define Lock        (1<<26) /* lock prefix is allowed for the instruction */
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#define Priv        (1<<27) /* instruction generates #GP if current CPL != 0 */
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#define No64	    (1<<28)
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/* Source 2 operand type */
#define Src2None    (0<<29)
#define Src2CL      (1<<29)
#define Src2ImmByte (2<<29)
#define Src2One     (3<<29)
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#define Src2Imm     (4<<29)
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#define Src2Mask    (7<<29)
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#define X2(x...) x, x
#define X3(x...) X2(x), x
#define X4(x...) X2(x), X2(x)
#define X5(x...) X4(x), x
#define X6(x...) X4(x), X2(x)
#define X7(x...) X4(x), X3(x)
#define X8(x...) X4(x), X4(x)
#define X16(x...) X8(x), X8(x)
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struct opcode {
	u32 flags;
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	u8 intercept;
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	union {
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		int (*execute)(struct x86_emulate_ctxt *ctxt);
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		struct opcode *group;
		struct group_dual *gdual;
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		struct gprefix *gprefix;
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	} u;
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	int (*check_perm)(struct x86_emulate_ctxt *ctxt);
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};

struct group_dual {
	struct opcode mod012[8];
	struct opcode mod3[8];
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};

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struct gprefix {
	struct opcode pfx_no;
	struct opcode pfx_66;
	struct opcode pfx_f2;
	struct opcode pfx_f3;
};

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/* EFLAGS bit definitions. */
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#define EFLG_ID (1<<21)
#define EFLG_VIP (1<<20)
#define EFLG_VIF (1<<19)
#define EFLG_AC (1<<18)
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#define EFLG_VM (1<<17)
#define EFLG_RF (1<<16)
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#define EFLG_IOPL (3<<12)
#define EFLG_NT (1<<14)
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#define EFLG_OF (1<<11)
#define EFLG_DF (1<<10)
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#define EFLG_IF (1<<9)
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#define EFLG_TF (1<<8)
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#define EFLG_SF (1<<7)
#define EFLG_ZF (1<<6)
#define EFLG_AF (1<<4)
#define EFLG_PF (1<<2)
#define EFLG_CF (1<<0)

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#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
#define EFLG_RESERVED_ONE_MASK 2

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/*
 * Instruction emulation:
 * Most instructions are emulated directly via a fragment of inline assembly
 * code. This allows us to save/restore EFLAGS and thus very easily pick up
 * any modified flags.
 */

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#if defined(CONFIG_X86_64)
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#define _LO32 "k"		/* force 32-bit operand */
#define _STK  "%%rsp"		/* stack pointer */
#elif defined(__i386__)
#define _LO32 ""		/* force 32-bit operand */
#define _STK  "%%esp"		/* stack pointer */
#endif

/*
 * These EFLAGS bits are restored from saved value during emulation, and
 * any changes are written back to the saved value after emulation.
 */
#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)

/* Before executing instruction: restore necessary bits in EFLAGS. */
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#define _PRE_EFLAGS(_sav, _msk, _tmp)					\
	/* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
	"movl %"_sav",%"_LO32 _tmp"; "                                  \
	"push %"_tmp"; "                                                \
	"push %"_tmp"; "                                                \
	"movl %"_msk",%"_LO32 _tmp"; "                                  \
	"andl %"_LO32 _tmp",("_STK"); "                                 \
	"pushf; "                                                       \
	"notl %"_LO32 _tmp"; "                                          \
	"andl %"_LO32 _tmp",("_STK"); "                                 \
	"andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); "	\
	"pop  %"_tmp"; "                                                \
	"orl  %"_LO32 _tmp",("_STK"); "                                 \
	"popf; "                                                        \
	"pop  %"_sav"; "
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/* After executing instruction: write-back necessary bits in EFLAGS. */
#define _POST_EFLAGS(_sav, _msk, _tmp) \
	/* _sav |= EFLAGS & _msk; */		\
	"pushf; "				\
	"pop  %"_tmp"; "			\
	"andl %"_msk",%"_LO32 _tmp"; "		\
	"orl  %"_LO32 _tmp",%"_sav"; "

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#ifdef CONFIG_X86_64
#define ON64(x) x
#else
#define ON64(x)
#endif

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#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
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	do {								\
		__asm__ __volatile__ (					\
			_PRE_EFLAGS("0", "4", "2")			\
			_op _suffix " %"_x"3,%1; "			\
			_POST_EFLAGS("0", "4", "2")			\
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			: "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
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			  "=&r" (_tmp)					\
			: _y ((_src).val), "i" (EFLAGS_MASK));		\
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	} while (0)
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/* Raw emulation: instruction has two explicit operands. */
#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
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	do {								\
		unsigned long _tmp;					\
									\
		switch ((_dst).bytes) {					\
		case 2:							\
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			____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
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			break;						\
		case 4:							\
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			____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
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			break;						\
		case 8:							\
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			ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
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			break;						\
		}							\
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	} while (0)

#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
	do {								     \
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		unsigned long _tmp;					     \
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		switch ((_dst).bytes) {				             \
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		case 1:							     \
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			____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
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			break;						     \
		default:						     \
			__emulate_2op_nobyte(_op, _src, _dst, _eflags,	     \
					     _wx, _wy, _lx, _ly, _qx, _qy);  \
			break;						     \
		}							     \
	} while (0)

/* Source operand is byte-sized and may be restricted to just %cl. */
#define emulate_2op_SrcB(_op, _src, _dst, _eflags)                      \
	__emulate_2op(_op, _src, _dst, _eflags,				\
		      "b", "c", "b", "c", "b", "c", "b", "c")

/* Source operand is byte, word, long or quad sized. */
#define emulate_2op_SrcV(_op, _src, _dst, _eflags)                      \
	__emulate_2op(_op, _src, _dst, _eflags,				\
		      "b", "q", "w", "r", _LO32, "r", "", "r")

/* Source operand is word, long or quad sized. */
#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags)               \
	__emulate_2op_nobyte(_op, _src, _dst, _eflags,			\
			     "w", "r", _LO32, "r", "", "r")

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/* Instruction has three operands and one operand is stored in ECX register */
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#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type)	\
	do {								\
		unsigned long _tmp;					\
		_type _clv  = (_cl).val;				\
		_type _srcv = (_src).val;				\
		_type _dstv = (_dst).val;				\
									\
		__asm__ __volatile__ (					\
			_PRE_EFLAGS("0", "5", "2")			\
			_op _suffix " %4,%1 \n"				\
			_POST_EFLAGS("0", "5", "2")			\
			: "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp)	\
			: "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK)	\
			);						\
									\
		(_cl).val  = (unsigned long) _clv;			\
		(_src).val = (unsigned long) _srcv;			\
		(_dst).val = (unsigned long) _dstv;			\
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	} while (0)

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#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags)			\
	do {								\
		switch ((_dst).bytes) {					\
		case 2:							\
			__emulate_2op_cl(_op, _cl, _src, _dst, _eflags,	\
					 "w", unsigned short);         	\
			break;						\
		case 4:							\
			__emulate_2op_cl(_op, _cl, _src, _dst, _eflags,	\
					 "l", unsigned int);           	\
			break;						\
		case 8:							\
			ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
					      "q", unsigned long));	\
			break;						\
		}							\
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	} while (0)

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#define __emulate_1op(_op, _dst, _eflags, _suffix)			\
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	do {								\
		unsigned long _tmp;					\
									\
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		__asm__ __volatile__ (					\
			_PRE_EFLAGS("0", "3", "2")			\
			_op _suffix " %1; "				\
			_POST_EFLAGS("0", "3", "2")			\
			: "=m" (_eflags), "+m" ((_dst).val),		\
			  "=&r" (_tmp)					\
			: "i" (EFLAGS_MASK));				\
	} while (0)

/* Instruction has only one explicit operand (no source operand). */
#define emulate_1op(_op, _dst, _eflags)                                    \
	do {								\
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		switch ((_dst).bytes) {				        \
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		case 1:	__emulate_1op(_op, _dst, _eflags, "b"); break;	\
		case 2:	__emulate_1op(_op, _dst, _eflags, "w"); break;	\
		case 4:	__emulate_1op(_op, _dst, _eflags, "l"); break;	\
		case 8:	ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
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		}							\
	} while (0)

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#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix)		\
	do {								\
		unsigned long _tmp;					\
									\
		__asm__ __volatile__ (					\
			_PRE_EFLAGS("0", "4", "1")			\
			_op _suffix " %5; "				\
			_POST_EFLAGS("0", "4", "1")			\
			: "=m" (_eflags), "=&r" (_tmp),			\
			  "+a" (_rax), "+d" (_rdx)			\
			: "i" (EFLAGS_MASK), "m" ((_src).val),		\
			  "a" (_rax), "d" (_rdx));			\
	} while (0)

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#define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
	do {								\
		unsigned long _tmp;					\
									\
		__asm__ __volatile__ (					\
			_PRE_EFLAGS("0", "5", "1")			\
			"1: \n\t"					\
			_op _suffix " %6; "				\
			"2: \n\t"					\
			_POST_EFLAGS("0", "5", "1")			\
			".pushsection .fixup,\"ax\" \n\t"		\
			"3: movb $1, %4 \n\t"				\
			"jmp 2b \n\t"					\
			".popsection \n\t"				\
			_ASM_EXTABLE(1b, 3b)				\
			: "=m" (_eflags), "=&r" (_tmp),			\
			  "+a" (_rax), "+d" (_rdx), "+qm"(_ex)		\
			: "i" (EFLAGS_MASK), "m" ((_src).val),		\
			  "a" (_rax), "d" (_rdx));			\
	} while (0)

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/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
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#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags)		\
	do {								\
		switch((_src).bytes) {					\
		case 1:							\
			__emulate_1op_rax_rdx(_op, _src, _rax, _rdx,	\
					      _eflags, "b");		\
			break;						\
		case 2:							\
			__emulate_1op_rax_rdx(_op, _src, _rax, _rdx,	\
					      _eflags, "w");		\
			break;						\
		case 4:							\
			__emulate_1op_rax_rdx(_op, _src, _rax, _rdx,	\
					      _eflags, "l");		\
			break;						\
		case 8:							\
			ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
						   _eflags, "q"));	\
			break;						\
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		}							\
	} while (0)

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#define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex)	\
	do {								\
		switch((_src).bytes) {					\
		case 1:							\
			__emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx,	\
						 _eflags, "b", _ex);	\
			break;						\
		case 2:							\
			__emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
						 _eflags, "w", _ex);	\
			break;						\
		case 4:							\
			__emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
						 _eflags, "l", _ex);	\
			break;						\
		case 8: ON64(						\
			__emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
						 _eflags, "q", _ex));	\
			break;						\
		}							\
	} while (0)

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static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
				    enum x86_intercept intercept,
				    enum x86_intercept_stage stage)
{
	struct x86_instruction_info info = {
		.intercept  = intercept,
		.rep_prefix = ctxt->decode.rep_prefix,
		.modrm_mod  = ctxt->decode.modrm_mod,
		.modrm_reg  = ctxt->decode.modrm_reg,
		.modrm_rm   = ctxt->decode.modrm_rm,
		.src_val    = ctxt->decode.src.val64,
		.src_bytes  = ctxt->decode.src.bytes,
		.dst_bytes  = ctxt->decode.dst.bytes,
		.ad_bytes   = ctxt->decode.ad_bytes,
		.next_rip   = ctxt->eip,
	};

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	return ctxt->ops->intercept(ctxt, &info, stage);
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}

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static inline unsigned long ad_mask(struct decode_cache *c)
{
	return (1UL << (c->ad_bytes << 3)) - 1;
}

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/* Access/update address held in a register, based on addressing mode. */
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static inline unsigned long
address_mask(struct decode_cache *c, unsigned long reg)
{
	if (c->ad_bytes == sizeof(unsigned long))
		return reg;
	else
		return reg & ad_mask(c);
}

static inline unsigned long
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register_address(struct decode_cache *c, unsigned long reg)
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{
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	return address_mask(c, reg);
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}

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static inline void
register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
{
	if (c->ad_bytes == sizeof(unsigned long))
		*reg += inc;
	else
		*reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
}
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static inline void jmp_rel(struct decode_cache *c, int rel)
{
	register_address_increment(c, &c->eip, rel);
}
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static u32 desc_limit_scaled(struct desc_struct *desc)
{
	u32 limit = get_desc_limit(desc);

	return desc->g ? (limit << 12) | 0xfff : limit;
}

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static void set_seg_override(struct decode_cache *c, int seg)
{
	c->has_seg_override = true;
	c->seg_override = seg;
}

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static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
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{
	if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
		return 0;

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	return ctxt->ops->get_cached_segment_base(ctxt, seg);
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}

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static unsigned seg_override(struct x86_emulate_ctxt *ctxt,
			     struct decode_cache *c)
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{
	if (!c->has_seg_override)
		return 0;

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	return c->seg_override;
493 494
}

495 496
static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
			     u32 error, bool valid)
497
{
498 499 500
	ctxt->exception.vector = vec;
	ctxt->exception.error_code = error;
	ctxt->exception.error_code_valid = valid;
501
	return X86EMUL_PROPAGATE_FAULT;
502 503
}

504 505 506 507 508
static int emulate_db(struct x86_emulate_ctxt *ctxt)
{
	return emulate_exception(ctxt, DB_VECTOR, 0, false);
}

509
static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
510
{
511
	return emulate_exception(ctxt, GP_VECTOR, err, true);
512 513
}

514 515 516 517 518
static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
{
	return emulate_exception(ctxt, SS_VECTOR, err, true);
}

519
static int emulate_ud(struct x86_emulate_ctxt *ctxt)
520
{
521
	return emulate_exception(ctxt, UD_VECTOR, 0, false);
522 523
}

524
static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
525
{
526
	return emulate_exception(ctxt, TS_VECTOR, err, true);
527 528
}

529 530
static int emulate_de(struct x86_emulate_ctxt *ctxt)
{
531
	return emulate_exception(ctxt, DE_VECTOR, 0, false);
532 533
}

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static int emulate_nm(struct x86_emulate_ctxt *ctxt)
{
	return emulate_exception(ctxt, NM_VECTOR, 0, false);
}

539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558
static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
{
	u16 selector;
	struct desc_struct desc;

	ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
	return selector;
}

static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
				 unsigned seg)
{
	u16 dummy;
	u32 base3;
	struct desc_struct desc;

	ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
	ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
}

559
static int __linearize(struct x86_emulate_ctxt *ctxt,
560
		     struct segmented_address addr,
561
		     unsigned size, bool write, bool fetch,
562 563 564
		     ulong *linear)
{
	struct decode_cache *c = &ctxt->decode;
565 566
	struct desc_struct desc;
	bool usable;
567
	ulong la;
568
	u32 lim;
569
	u16 sel;
570
	unsigned cpl, rpl;
571

572
	la = seg_base(ctxt, addr.seg) + addr.ea;
573 574 575 576 577 578 579 580
	switch (ctxt->mode) {
	case X86EMUL_MODE_REAL:
		break;
	case X86EMUL_MODE_PROT64:
		if (((signed long)la << 16) >> 16 != la)
			return emulate_gp(ctxt, 0);
		break;
	default:
581 582
		usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
						addr.seg);
583 584 585 586 587 588
		if (!usable)
			goto bad;
		/* code segment or read-only data segment */
		if (((desc.type & 8) || !(desc.type & 2)) && write)
			goto bad;
		/* unreadable code segment */
589
		if (!fetch && (desc.type & 8) && !(desc.type & 2))
590 591 592 593 594 595 596 597 598 599 600 601 602 603
			goto bad;
		lim = desc_limit_scaled(&desc);
		if ((desc.type & 8) || !(desc.type & 4)) {
			/* expand-up segment */
			if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
				goto bad;
		} else {
			/* exapand-down segment */
			if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
				goto bad;
			lim = desc.d ? 0xffffffff : 0xffff;
			if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
				goto bad;
		}
604
		cpl = ctxt->ops->cpl(ctxt);
605
		rpl = sel & 3;
606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621
		cpl = max(cpl, rpl);
		if (!(desc.type & 8)) {
			/* data segment */
			if (cpl > desc.dpl)
				goto bad;
		} else if ((desc.type & 8) && !(desc.type & 4)) {
			/* nonconforming code segment */
			if (cpl != desc.dpl)
				goto bad;
		} else if ((desc.type & 8) && (desc.type & 4)) {
			/* conforming code segment */
			if (cpl < desc.dpl)
				goto bad;
		}
		break;
	}
622
	if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : c->ad_bytes != 8)
623 624 625
		la &= (u32)-1;
	*linear = la;
	return X86EMUL_CONTINUE;
626 627 628 629 630
bad:
	if (addr.seg == VCPU_SREG_SS)
		return emulate_ss(ctxt, addr.seg);
	else
		return emulate_gp(ctxt, addr.seg);
631 632
}

633 634 635 636 637 638 639 640 641
static int linearize(struct x86_emulate_ctxt *ctxt,
		     struct segmented_address addr,
		     unsigned size, bool write,
		     ulong *linear)
{
	return __linearize(ctxt, addr, size, write, false, linear);
}


642 643 644 645 646
static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
			      struct segmented_address addr,
			      void *data,
			      unsigned size)
{
647 648 649
	int rc;
	ulong linear;

650
	rc = linearize(ctxt, addr, size, false, &linear);
651 652
	if (rc != X86EMUL_CONTINUE)
		return rc;
653
	return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
654 655
}

656
static int do_insn_fetch_byte(struct x86_emulate_ctxt *ctxt,
657
			      unsigned long eip, u8 *dest)
658 659 660
{
	struct fetch_cache *fc = &ctxt->decode.fetch;
	int rc;
661
	int size, cur_size;
662

663
	if (eip == fc->end) {
664 665
		unsigned long linear;
		struct segmented_address addr = { .seg=VCPU_SREG_CS, .ea=eip};
666 667
		cur_size = fc->end - fc->start;
		size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
668 669 670
		rc = __linearize(ctxt, addr, size, false, true, &linear);
		if (rc != X86EMUL_CONTINUE)
			return rc;
671 672
		rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
				      size, &ctxt->exception);
673
		if (rc != X86EMUL_CONTINUE)
674
			return rc;
675
		fc->end += size;
676
	}
677
	*dest = fc->data[eip - fc->start];
678
	return X86EMUL_CONTINUE;
679 680 681 682 683
}

static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
			 unsigned long eip, void *dest, unsigned size)
{
684
	int rc;
685

686
	/* x86 instructions are limited to 15 bytes. */
687
	if (eip + size - ctxt->eip > 15)
688
		return X86EMUL_UNHANDLEABLE;
689
	while (size--) {
690
		rc = do_insn_fetch_byte(ctxt, eip++, dest++);
691
		if (rc != X86EMUL_CONTINUE)
692 693
			return rc;
	}
694
	return X86EMUL_CONTINUE;
695 696
}

697 698 699
/* Fetch next part of the instruction being emulated. */
#define insn_fetch(_type, _size, _eip)					\
({	unsigned long _x;						\
700
	rc = do_insn_fetch(ctxt, (_eip), &_x, (_size));			\
701 702 703 704 705 706 707
	if (rc != X86EMUL_CONTINUE)					\
		goto done;						\
	(_eip) += (_size);						\
	(_type)_x;							\
})

#define insn_fetch_arr(_arr, _size, _eip)				\
708
({	rc = do_insn_fetch(ctxt, (_eip), _arr, (_size));		\
709 710 711 712 713
	if (rc != X86EMUL_CONTINUE)					\
		goto done;						\
	(_eip) += (_size);						\
})

714 715 716 717 718 719 720
/*
 * Given the 'reg' portion of a ModRM byte, and a register block, return a
 * pointer into the block that addresses the relevant register.
 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
 */
static void *decode_register(u8 modrm_reg, unsigned long *regs,
			     int highbyte_regs)
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{
	void *p;

	p = &regs[modrm_reg];
	if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
		p = (unsigned char *)&regs[modrm_reg & 3] + 1;
	return p;
}

static int read_descriptor(struct x86_emulate_ctxt *ctxt,
731
			   struct segmented_address addr,
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732 733 734 735 736 737 738
			   u16 *size, unsigned long *address, int op_bytes)
{
	int rc;

	if (op_bytes == 2)
		op_bytes = 3;
	*address = 0;
739
	rc = segmented_read_std(ctxt, addr, size, 2);
740
	if (rc != X86EMUL_CONTINUE)
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741
		return rc;
742
	addr.ea += 2;
743
	rc = segmented_read_std(ctxt, addr, address, op_bytes);
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744 745 746
	return rc;
}

747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781
static int test_cc(unsigned int condition, unsigned int flags)
{
	int rc = 0;

	switch ((condition & 15) >> 1) {
	case 0: /* o */
		rc |= (flags & EFLG_OF);
		break;
	case 1: /* b/c/nae */
		rc |= (flags & EFLG_CF);
		break;
	case 2: /* z/e */
		rc |= (flags & EFLG_ZF);
		break;
	case 3: /* be/na */
		rc |= (flags & (EFLG_CF|EFLG_ZF));
		break;
	case 4: /* s */
		rc |= (flags & EFLG_SF);
		break;
	case 5: /* p/pe */
		rc |= (flags & EFLG_PF);
		break;
	case 7: /* le/ng */
		rc |= (flags & EFLG_ZF);
		/* fall through */
	case 6: /* l/nge */
		rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
		break;
	}

	/* Odd condition identifiers (lsb == 1) have inverted sense. */
	return (!!rc ^ (condition & 1));
}

782 783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799
static void fetch_register_operand(struct operand *op)
{
	switch (op->bytes) {
	case 1:
		op->val = *(u8 *)op->addr.reg;
		break;
	case 2:
		op->val = *(u16 *)op->addr.reg;
		break;
	case 4:
		op->val = *(u32 *)op->addr.reg;
		break;
	case 8:
		op->val = *(u64 *)op->addr.reg;
		break;
	}
}

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static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
{
	ctxt->ops->get_fpu(ctxt);
	switch (reg) {
	case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
	case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
	case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
	case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
	case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
	case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
	case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
	case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
#ifdef CONFIG_X86_64
	case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
	case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
	case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
	case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
	case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
	case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
	case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
	case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
#endif
	default: BUG();
	}
	ctxt->ops->put_fpu(ctxt);
}

static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
			  int reg)
{
	ctxt->ops->get_fpu(ctxt);
	switch (reg) {
	case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
	case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
	case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
	case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
	case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
	case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
	case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
	case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
#ifdef CONFIG_X86_64
	case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
	case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
	case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
	case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
	case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
	case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
	case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
	case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
#endif
	default: BUG();
	}
	ctxt->ops->put_fpu(ctxt);
}

static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
				    struct operand *op,
857 858 859
				    struct decode_cache *c,
				    int inhibit_bytereg)
{
860
	unsigned reg = c->modrm_reg;
861
	int highbyte_regs = c->rex_prefix == 0;
862 863 864

	if (!(c->d & ModRM))
		reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
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865 866 867 868 869 870 871 872 873

	if (c->d & Sse) {
		op->type = OP_XMM;
		op->bytes = 16;
		op->addr.xmm = reg;
		read_sse_reg(ctxt, &op->vec_val, reg);
		return;
	}

874 875
	op->type = OP_REG;
	if ((c->d & ByteOp) && !inhibit_bytereg) {
876
		op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
877 878
		op->bytes = 1;
	} else {
879
		op->addr.reg = decode_register(reg, c->regs, 0);
880 881
		op->bytes = c->op_bytes;
	}
882
	fetch_register_operand(op);
883 884 885
	op->orig_val = op->val;
}

886
static int decode_modrm(struct x86_emulate_ctxt *ctxt,
887
			struct operand *op)
888 889 890
{
	struct decode_cache *c = &ctxt->decode;
	u8 sib;
891
	int index_reg = 0, base_reg = 0, scale;
892
	int rc = X86EMUL_CONTINUE;
893
	ulong modrm_ea = 0;
894 895 896 897 898 899 900 901 902 903 904

	if (c->rex_prefix) {
		c->modrm_reg = (c->rex_prefix & 4) << 1;	/* REX.R */
		index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
		c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
	}

	c->modrm = insn_fetch(u8, 1, c->eip);
	c->modrm_mod |= (c->modrm & 0xc0) >> 6;
	c->modrm_reg |= (c->modrm & 0x38) >> 3;
	c->modrm_rm |= (c->modrm & 0x07);
905
	c->modrm_seg = VCPU_SREG_DS;
906 907

	if (c->modrm_mod == 3) {
908 909 910
		op->type = OP_REG;
		op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
		op->addr.reg = decode_register(c->modrm_rm,
911
					       c->regs, c->d & ByteOp);
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Avi Kivity 已提交
912 913 914 915 916 917 918
		if (c->d & Sse) {
			op->type = OP_XMM;
			op->bytes = 16;
			op->addr.xmm = c->modrm_rm;
			read_sse_reg(ctxt, &op->vec_val, c->modrm_rm);
			return rc;
		}
919
		fetch_register_operand(op);
920 921 922
		return rc;
	}

923 924
	op->type = OP_MEM;

925 926 927 928 929 930 931 932 933 934
	if (c->ad_bytes == 2) {
		unsigned bx = c->regs[VCPU_REGS_RBX];
		unsigned bp = c->regs[VCPU_REGS_RBP];
		unsigned si = c->regs[VCPU_REGS_RSI];
		unsigned di = c->regs[VCPU_REGS_RDI];

		/* 16-bit ModR/M decode. */
		switch (c->modrm_mod) {
		case 0:
			if (c->modrm_rm == 6)
935
				modrm_ea += insn_fetch(u16, 2, c->eip);
936 937
			break;
		case 1:
938
			modrm_ea += insn_fetch(s8, 1, c->eip);
939 940
			break;
		case 2:
941
			modrm_ea += insn_fetch(u16, 2, c->eip);
942 943 944 945
			break;
		}
		switch (c->modrm_rm) {
		case 0:
946
			modrm_ea += bx + si;
947 948
			break;
		case 1:
949
			modrm_ea += bx + di;
950 951
			break;
		case 2:
952
			modrm_ea += bp + si;
953 954
			break;
		case 3:
955
			modrm_ea += bp + di;
956 957
			break;
		case 4:
958
			modrm_ea += si;
959 960
			break;
		case 5:
961
			modrm_ea += di;
962 963 964
			break;
		case 6:
			if (c->modrm_mod != 0)
965
				modrm_ea += bp;
966 967
			break;
		case 7:
968
			modrm_ea += bx;
969 970 971 972
			break;
		}
		if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
		    (c->modrm_rm == 6 && c->modrm_mod != 0))
973
			c->modrm_seg = VCPU_SREG_SS;
974
		modrm_ea = (u16)modrm_ea;
975 976
	} else {
		/* 32/64-bit ModR/M decode. */
977
		if ((c->modrm_rm & 7) == 4) {
978 979 980 981 982
			sib = insn_fetch(u8, 1, c->eip);
			index_reg |= (sib >> 3) & 7;
			base_reg |= sib & 7;
			scale = sib >> 6;

983
			if ((base_reg & 7) == 5 && c->modrm_mod == 0)
984
				modrm_ea += insn_fetch(s32, 4, c->eip);
985
			else
986
				modrm_ea += c->regs[base_reg];
987
			if (index_reg != 4)
988
				modrm_ea += c->regs[index_reg] << scale;
989 990
		} else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
			if (ctxt->mode == X86EMUL_MODE_PROT64)
991
				c->rip_relative = 1;
992
		} else
993
			modrm_ea += c->regs[c->modrm_rm];
994 995 996
		switch (c->modrm_mod) {
		case 0:
			if (c->modrm_rm == 5)
997
				modrm_ea += insn_fetch(s32, 4, c->eip);
998 999
			break;
		case 1:
1000
			modrm_ea += insn_fetch(s8, 1, c->eip);
1001 1002
			break;
		case 2:
1003
			modrm_ea += insn_fetch(s32, 4, c->eip);
1004 1005 1006
			break;
		}
	}
1007
	op->addr.mem.ea = modrm_ea;
1008 1009 1010 1011 1012
done:
	return rc;
}

static int decode_abs(struct x86_emulate_ctxt *ctxt,
1013
		      struct operand *op)
1014 1015
{
	struct decode_cache *c = &ctxt->decode;
1016
	int rc = X86EMUL_CONTINUE;
1017

1018
	op->type = OP_MEM;
1019 1020
	switch (c->ad_bytes) {
	case 2:
1021
		op->addr.mem.ea = insn_fetch(u16, 2, c->eip);
1022 1023
		break;
	case 4:
1024
		op->addr.mem.ea = insn_fetch(u32, 4, c->eip);
1025 1026
		break;
	case 8:
1027
		op->addr.mem.ea = insn_fetch(u64, 8, c->eip);
1028 1029 1030 1031 1032 1033
		break;
	}
done:
	return rc;
}

1034 1035
static void fetch_bit_operand(struct decode_cache *c)
{
1036
	long sv = 0, mask;
1037

1038
	if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
1039 1040 1041 1042 1043 1044 1045
		mask = ~(c->dst.bytes * 8 - 1);

		if (c->src.bytes == 2)
			sv = (s16)c->src.val & (s16)mask;
		else if (c->src.bytes == 4)
			sv = (s32)c->src.val & (s32)mask;

1046
		c->dst.addr.mem.ea += (sv >> 3);
1047
	}
1048 1049 1050

	/* only subword offset */
	c->src.val &= (c->dst.bytes << 3) - 1;
1051 1052
}

1053 1054
static int read_emulated(struct x86_emulate_ctxt *ctxt,
			 unsigned long addr, void *dest, unsigned size)
A
Avi Kivity 已提交
1055
{
1056 1057
	int rc;
	struct read_cache *mc = &ctxt->decode.mem_read;
A
Avi Kivity 已提交
1058

1059 1060 1061 1062 1063
	while (size) {
		int n = min(size, 8u);
		size -= n;
		if (mc->pos < mc->end)
			goto read_cached;
1064

1065 1066
		rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
					      &ctxt->exception);
1067 1068 1069
		if (rc != X86EMUL_CONTINUE)
			return rc;
		mc->end += n;
A
Avi Kivity 已提交
1070

1071 1072 1073 1074 1075
	read_cached:
		memcpy(dest, mc->data + mc->pos, n);
		mc->pos += n;
		dest += n;
		addr += n;
A
Avi Kivity 已提交
1076
	}
1077 1078
	return X86EMUL_CONTINUE;
}
A
Avi Kivity 已提交
1079

1080 1081 1082 1083 1084
static int segmented_read(struct x86_emulate_ctxt *ctxt,
			  struct segmented_address addr,
			  void *data,
			  unsigned size)
{
1085 1086 1087
	int rc;
	ulong linear;

1088
	rc = linearize(ctxt, addr, size, false, &linear);
1089 1090
	if (rc != X86EMUL_CONTINUE)
		return rc;
1091
	return read_emulated(ctxt, linear, data, size);
1092 1093 1094 1095 1096 1097 1098
}

static int segmented_write(struct x86_emulate_ctxt *ctxt,
			   struct segmented_address addr,
			   const void *data,
			   unsigned size)
{
1099 1100 1101
	int rc;
	ulong linear;

1102
	rc = linearize(ctxt, addr, size, true, &linear);
1103 1104
	if (rc != X86EMUL_CONTINUE)
		return rc;
1105 1106
	return ctxt->ops->write_emulated(ctxt, linear, data, size,
					 &ctxt->exception);
1107 1108 1109 1110 1111 1112 1113
}

static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
			     struct segmented_address addr,
			     const void *orig_data, const void *data,
			     unsigned size)
{
1114 1115 1116
	int rc;
	ulong linear;

1117
	rc = linearize(ctxt, addr, size, true, &linear);
1118 1119
	if (rc != X86EMUL_CONTINUE)
		return rc;
1120 1121
	return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
					   size, &ctxt->exception);
1122 1123
}

1124 1125 1126 1127 1128
static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
			   unsigned int size, unsigned short port,
			   void *dest)
{
	struct read_cache *rc = &ctxt->decode.io_read;
1129

1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142
	if (rc->pos == rc->end) { /* refill pio read ahead */
		struct decode_cache *c = &ctxt->decode;
		unsigned int in_page, n;
		unsigned int count = c->rep_prefix ?
			address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
		in_page = (ctxt->eflags & EFLG_DF) ?
			offset_in_page(c->regs[VCPU_REGS_RDI]) :
			PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
		n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
			count);
		if (n == 0)
			n = 1;
		rc->pos = rc->end = 0;
1143
		if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
1144 1145
			return 0;
		rc->end = n * size;
A
Avi Kivity 已提交
1146 1147
	}

1148 1149 1150 1151
	memcpy(dest, rc->data + rc->pos, size);
	rc->pos += size;
	return 1;
}
A
Avi Kivity 已提交
1152

1153 1154 1155
static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
				     u16 selector, struct desc_ptr *dt)
{
1156 1157
	struct x86_emulate_ops *ops = ctxt->ops;

1158 1159
	if (selector & 1 << 2) {
		struct desc_struct desc;
1160 1161
		u16 sel;

1162
		memset (dt, 0, sizeof *dt);
1163
		if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
1164
			return;
1165

1166 1167 1168
		dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
		dt->address = get_desc_base(&desc);
	} else
1169
		ops->get_gdt(ctxt, dt);
1170
}
1171

1172 1173 1174 1175 1176 1177 1178
/* allowed just for 8 bytes segments */
static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				   u16 selector, struct desc_struct *desc)
{
	struct desc_ptr dt;
	u16 index = selector >> 3;
	ulong addr;
1179

1180
	get_descriptor_table_ptr(ctxt, selector, &dt);
1181

1182 1183
	if (dt.size < index * 8 + 7)
		return emulate_gp(ctxt, selector & 0xfffc);
1184

1185 1186 1187
	addr = dt.address + index * 8;
	return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
				   &ctxt->exception);
1188
}
1189

1190 1191 1192 1193 1194 1195 1196
/* allowed just for 8 bytes segments */
static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				    u16 selector, struct desc_struct *desc)
{
	struct desc_ptr dt;
	u16 index = selector >> 3;
	ulong addr;
A
Avi Kivity 已提交
1197

1198
	get_descriptor_table_ptr(ctxt, selector, &dt);
1199

1200 1201
	if (dt.size < index * 8 + 7)
		return emulate_gp(ctxt, selector & 0xfffc);
A
Avi Kivity 已提交
1202

1203
	addr = dt.address + index * 8;
1204 1205
	return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
				    &ctxt->exception);
1206
}
1207

1208
/* Does not support long mode */
1209 1210 1211 1212 1213 1214 1215 1216 1217
static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				   u16 selector, int seg)
{
	struct desc_struct seg_desc;
	u8 dpl, rpl, cpl;
	unsigned err_vec = GP_VECTOR;
	u32 err_code = 0;
	bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
	int ret;
1218

1219
	memset(&seg_desc, 0, sizeof seg_desc);
1220

1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243
	if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
	    || ctxt->mode == X86EMUL_MODE_REAL) {
		/* set real mode segment descriptor */
		set_desc_base(&seg_desc, selector << 4);
		set_desc_limit(&seg_desc, 0xffff);
		seg_desc.type = 3;
		seg_desc.p = 1;
		seg_desc.s = 1;
		goto load;
	}

	/* NULL selector is not valid for TR, CS and SS */
	if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
	    && null_selector)
		goto exception;

	/* TR should be in GDT only */
	if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
		goto exception;

	if (null_selector) /* for NULL selector skip all following checks */
		goto load;

1244
	ret = read_segment_descriptor(ctxt, selector, &seg_desc);
1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261
	if (ret != X86EMUL_CONTINUE)
		return ret;

	err_code = selector & 0xfffc;
	err_vec = GP_VECTOR;

	/* can't load system descriptor into segment selecor */
	if (seg <= VCPU_SREG_GS && !seg_desc.s)
		goto exception;

	if (!seg_desc.p) {
		err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
		goto exception;
	}

	rpl = selector & 3;
	dpl = seg_desc.dpl;
1262
	cpl = ctxt->ops->cpl(ctxt);
1263 1264 1265 1266 1267 1268 1269 1270 1271

	switch (seg) {
	case VCPU_SREG_SS:
		/*
		 * segment is not a writable data segment or segment
		 * selector's RPL != CPL or segment selector's RPL != CPL
		 */
		if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
			goto exception;
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1272
		break;
1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287
	case VCPU_SREG_CS:
		if (!(seg_desc.type & 8))
			goto exception;

		if (seg_desc.type & 4) {
			/* conforming */
			if (dpl > cpl)
				goto exception;
		} else {
			/* nonconforming */
			if (rpl > cpl || dpl != cpl)
				goto exception;
		}
		/* CS(RPL) <- CPL */
		selector = (selector & 0xfffc) | cpl;
A
Avi Kivity 已提交
1288
		break;
1289 1290 1291 1292 1293 1294 1295 1296 1297
	case VCPU_SREG_TR:
		if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
			goto exception;
		break;
	case VCPU_SREG_LDTR:
		if (seg_desc.s || seg_desc.type != 2)
			goto exception;
		break;
	default: /*  DS, ES, FS, or GS */
1298
		/*
1299 1300 1301
		 * segment is not a data or readable code segment or
		 * ((segment is a data or nonconforming code segment)
		 * and (both RPL and CPL > DPL))
1302
		 */
1303 1304 1305 1306
		if ((seg_desc.type & 0xa) == 0x8 ||
		    (((seg_desc.type & 0xc) != 0xc) &&
		     (rpl > dpl && cpl > dpl)))
			goto exception;
A
Avi Kivity 已提交
1307
		break;
1308 1309 1310 1311 1312
	}

	if (seg_desc.s) {
		/* mark segment as accessed */
		seg_desc.type |= 1;
1313
		ret = write_segment_descriptor(ctxt, selector, &seg_desc);
1314 1315 1316 1317
		if (ret != X86EMUL_CONTINUE)
			return ret;
	}
load:
1318
	ctxt->ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
1319 1320 1321 1322 1323 1324
	return X86EMUL_CONTINUE;
exception:
	emulate_exception(ctxt, err_vec, err_code, true);
	return X86EMUL_PROPAGATE_FAULT;
}

1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343
static void write_register_operand(struct operand *op)
{
	/* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
	switch (op->bytes) {
	case 1:
		*(u8 *)op->addr.reg = (u8)op->val;
		break;
	case 2:
		*(u16 *)op->addr.reg = (u16)op->val;
		break;
	case 4:
		*op->addr.reg = (u32)op->val;
		break;	/* 64b: zero-extend */
	case 8:
		*op->addr.reg = op->val;
		break;
	}
}

1344
static int writeback(struct x86_emulate_ctxt *ctxt)
1345 1346 1347 1348 1349 1350
{
	int rc;
	struct decode_cache *c = &ctxt->decode;

	switch (c->dst.type) {
	case OP_REG:
1351
		write_register_operand(&c->dst);
A
Avi Kivity 已提交
1352
		break;
1353 1354
	case OP_MEM:
		if (c->lock_prefix)
1355 1356 1357 1358 1359
			rc = segmented_cmpxchg(ctxt,
					       c->dst.addr.mem,
					       &c->dst.orig_val,
					       &c->dst.val,
					       c->dst.bytes);
1360
		else
1361 1362 1363 1364
			rc = segmented_write(ctxt,
					     c->dst.addr.mem,
					     &c->dst.val,
					     c->dst.bytes);
1365 1366
		if (rc != X86EMUL_CONTINUE)
			return rc;
1367
		break;
A
Avi Kivity 已提交
1368 1369 1370
	case OP_XMM:
		write_sse_reg(ctxt, &c->dst.vec_val, c->dst.addr.xmm);
		break;
1371 1372
	case OP_NONE:
		/* no writeback */
1373
		break;
1374
	default:
1375
		break;
A
Avi Kivity 已提交
1376
	}
1377 1378
	return X86EMUL_CONTINUE;
}
A
Avi Kivity 已提交
1379

1380
static int em_push(struct x86_emulate_ctxt *ctxt)
1381 1382
{
	struct decode_cache *c = &ctxt->decode;
1383
	struct segmented_address addr;
1384

1385
	register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1386 1387 1388 1389 1390 1391
	addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
	addr.seg = VCPU_SREG_SS;

	/* Disable writeback. */
	c->dst.type = OP_NONE;
	return segmented_write(ctxt, addr, &c->src.val, c->op_bytes);
1392
}
1393

1394 1395 1396 1397 1398
static int emulate_pop(struct x86_emulate_ctxt *ctxt,
		       void *dest, int len)
{
	struct decode_cache *c = &ctxt->decode;
	int rc;
1399
	struct segmented_address addr;
1400

1401 1402
	addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
	addr.seg = VCPU_SREG_SS;
1403
	rc = segmented_read(ctxt, addr, dest, len);
1404 1405 1406 1407 1408
	if (rc != X86EMUL_CONTINUE)
		return rc;

	register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
	return rc;
1409 1410
}

1411 1412 1413 1414
static int em_pop(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

1415
	return emulate_pop(ctxt, &c->dst.val, c->op_bytes);
1416 1417
}

1418
static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1419
			void *dest, int len)
1420 1421
{
	int rc;
1422 1423
	unsigned long val, change_mask;
	int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1424
	int cpl = ctxt->ops->cpl(ctxt);
1425

1426
	rc = emulate_pop(ctxt, &val, len);
1427 1428
	if (rc != X86EMUL_CONTINUE)
		return rc;
1429

1430 1431
	change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
		| EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1432

1433 1434 1435 1436 1437 1438 1439 1440 1441 1442
	switch(ctxt->mode) {
	case X86EMUL_MODE_PROT64:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT16:
		if (cpl == 0)
			change_mask |= EFLG_IOPL;
		if (cpl <= iopl)
			change_mask |= EFLG_IF;
		break;
	case X86EMUL_MODE_VM86:
1443 1444
		if (iopl < 3)
			return emulate_gp(ctxt, 0);
1445 1446 1447 1448 1449
		change_mask |= EFLG_IF;
		break;
	default: /* real mode */
		change_mask |= (EFLG_IOPL | EFLG_IF);
		break;
1450
	}
1451 1452 1453 1454 1455

	*(unsigned long *)dest =
		(ctxt->eflags & ~change_mask) | (val & change_mask);

	return rc;
1456 1457
}

1458 1459 1460 1461 1462 1463 1464
static int em_popf(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	c->dst.type = OP_REG;
	c->dst.addr.reg = &ctxt->eflags;
	c->dst.bytes = c->op_bytes;
1465
	return emulate_popf(ctxt, &c->dst.val, c->op_bytes);
1466 1467
}

1468
static int emulate_push_sreg(struct x86_emulate_ctxt *ctxt, int seg)
1469
{
1470
	struct decode_cache *c = &ctxt->decode;
1471

1472
	c->src.val = get_segment_selector(ctxt, seg);
1473

1474
	return em_push(ctxt);
1475 1476
}

1477
static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt, int seg)
1478
{
1479 1480 1481
	struct decode_cache *c = &ctxt->decode;
	unsigned long selector;
	int rc;
1482

1483
	rc = emulate_pop(ctxt, &selector, c->op_bytes);
1484 1485 1486
	if (rc != X86EMUL_CONTINUE)
		return rc;

1487
	rc = load_segment_descriptor(ctxt, (u16)selector, seg);
1488
	return rc;
1489 1490
}

1491
static int em_pusha(struct x86_emulate_ctxt *ctxt)
1492
{
1493 1494 1495 1496
	struct decode_cache *c = &ctxt->decode;
	unsigned long old_esp = c->regs[VCPU_REGS_RSP];
	int rc = X86EMUL_CONTINUE;
	int reg = VCPU_REGS_RAX;
1497

1498 1499 1500
	while (reg <= VCPU_REGS_RDI) {
		(reg == VCPU_REGS_RSP) ?
		(c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1501

1502
		rc = em_push(ctxt);
1503 1504
		if (rc != X86EMUL_CONTINUE)
			return rc;
1505

1506
		++reg;
1507 1508
	}

1509
	return rc;
1510 1511
}

1512 1513 1514 1515 1516 1517 1518 1519
static int em_pushf(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	c->src.val =  (unsigned long)ctxt->eflags;
	return em_push(ctxt);
}

1520
static int em_popa(struct x86_emulate_ctxt *ctxt)
1521
{
1522 1523 1524
	struct decode_cache *c = &ctxt->decode;
	int rc = X86EMUL_CONTINUE;
	int reg = VCPU_REGS_RDI;
1525

1526 1527 1528 1529 1530 1531
	while (reg >= VCPU_REGS_RAX) {
		if (reg == VCPU_REGS_RSP) {
			register_address_increment(c, &c->regs[VCPU_REGS_RSP],
							c->op_bytes);
			--reg;
		}
1532

1533
		rc = emulate_pop(ctxt, &c->regs[reg], c->op_bytes);
1534 1535 1536
		if (rc != X86EMUL_CONTINUE)
			break;
		--reg;
1537
	}
1538
	return rc;
1539 1540
}

1541
int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1542 1543
{
	struct decode_cache *c = &ctxt->decode;
1544
	struct x86_emulate_ops *ops = ctxt->ops;
1545
	int rc;
1546 1547 1548 1549 1550 1551 1552
	struct desc_ptr dt;
	gva_t cs_addr;
	gva_t eip_addr;
	u16 cs, eip;

	/* TODO: Add limit checks */
	c->src.val = ctxt->eflags;
1553
	rc = em_push(ctxt);
1554 1555
	if (rc != X86EMUL_CONTINUE)
		return rc;
1556 1557 1558

	ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);

1559
	c->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
1560
	rc = em_push(ctxt);
1561 1562
	if (rc != X86EMUL_CONTINUE)
		return rc;
1563 1564

	c->src.val = c->eip;
1565
	rc = em_push(ctxt);
1566 1567 1568
	if (rc != X86EMUL_CONTINUE)
		return rc;

1569
	ops->get_idt(ctxt, &dt);
1570 1571 1572 1573

	eip_addr = dt.address + (irq << 2);
	cs_addr = dt.address + (irq << 2) + 2;

1574
	rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
1575 1576 1577
	if (rc != X86EMUL_CONTINUE)
		return rc;

1578
	rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
1579 1580 1581
	if (rc != X86EMUL_CONTINUE)
		return rc;

1582
	rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
1583 1584 1585 1586 1587 1588 1589 1590
	if (rc != X86EMUL_CONTINUE)
		return rc;

	c->eip = eip;

	return rc;
}

1591
static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
1592 1593 1594
{
	switch(ctxt->mode) {
	case X86EMUL_MODE_REAL:
1595
		return emulate_int_real(ctxt, irq);
1596 1597 1598 1599 1600 1601 1602 1603 1604 1605
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT64:
	default:
		/* Protected mode interrupts unimplemented yet */
		return X86EMUL_UNHANDLEABLE;
	}
}

1606
static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
1607
{
1608 1609 1610 1611 1612 1613 1614 1615 1616
	struct decode_cache *c = &ctxt->decode;
	int rc = X86EMUL_CONTINUE;
	unsigned long temp_eip = 0;
	unsigned long temp_eflags = 0;
	unsigned long cs = 0;
	unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
			     EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
			     EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
	unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1617

1618
	/* TODO: Add stack limit check */
1619

1620
	rc = emulate_pop(ctxt, &temp_eip, c->op_bytes);
1621

1622 1623
	if (rc != X86EMUL_CONTINUE)
		return rc;
1624

1625 1626
	if (temp_eip & ~0xffff)
		return emulate_gp(ctxt, 0);
1627

1628
	rc = emulate_pop(ctxt, &cs, c->op_bytes);
1629

1630 1631
	if (rc != X86EMUL_CONTINUE)
		return rc;
1632

1633
	rc = emulate_pop(ctxt, &temp_eflags, c->op_bytes);
1634

1635 1636
	if (rc != X86EMUL_CONTINUE)
		return rc;
1637

1638
	rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
1639

1640 1641
	if (rc != X86EMUL_CONTINUE)
		return rc;
1642

1643
	c->eip = temp_eip;
1644 1645


1646 1647 1648 1649 1650
	if (c->op_bytes == 4)
		ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
	else if (c->op_bytes == 2) {
		ctxt->eflags &= ~0xffff;
		ctxt->eflags |= temp_eflags;
1651
	}
1652 1653 1654 1655 1656

	ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
	ctxt->eflags |= EFLG_RESERVED_ONE_MASK;

	return rc;
1657 1658
}

1659
static int em_iret(struct x86_emulate_ctxt *ctxt)
1660
{
1661 1662
	switch(ctxt->mode) {
	case X86EMUL_MODE_REAL:
1663
		return emulate_iret_real(ctxt);
1664 1665 1666 1667
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT64:
1668
	default:
1669 1670
		/* iret from protected mode unimplemented yet */
		return X86EMUL_UNHANDLEABLE;
1671 1672 1673
	}
}

1674 1675 1676 1677 1678 1679 1680 1681
static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	int rc;
	unsigned short sel;

	memcpy(&sel, c->src.valptr + c->op_bytes, 2);

1682
	rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
1683 1684 1685 1686 1687 1688 1689 1690
	if (rc != X86EMUL_CONTINUE)
		return rc;

	c->eip = 0;
	memcpy(&c->eip, c->src.valptr, c->op_bytes);
	return X86EMUL_CONTINUE;
}

1691
static int em_grp1a(struct x86_emulate_ctxt *ctxt)
1692 1693 1694
{
	struct decode_cache *c = &ctxt->decode;

1695
	return emulate_pop(ctxt, &c->dst.val, c->dst.bytes);
1696 1697
}

1698
static int em_grp2(struct x86_emulate_ctxt *ctxt)
1699
{
1700
	struct decode_cache *c = &ctxt->decode;
1701 1702
	switch (c->modrm_reg) {
	case 0:	/* rol */
1703
		emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1704 1705
		break;
	case 1:	/* ror */
1706
		emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1707 1708
		break;
	case 2:	/* rcl */
1709
		emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1710 1711
		break;
	case 3:	/* rcr */
1712
		emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1713 1714 1715
		break;
	case 4:	/* sal/shl */
	case 6:	/* sal/shl */
1716
		emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1717 1718
		break;
	case 5:	/* shr */
1719
		emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1720 1721
		break;
	case 7:	/* sar */
1722
		emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1723 1724
		break;
	}
1725
	return X86EMUL_CONTINUE;
1726 1727
}

1728
static int em_grp3(struct x86_emulate_ctxt *ctxt)
1729 1730
{
	struct decode_cache *c = &ctxt->decode;
1731 1732
	unsigned long *rax = &c->regs[VCPU_REGS_RAX];
	unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
1733
	u8 de = 0;
1734 1735 1736

	switch (c->modrm_reg) {
	case 0 ... 1:	/* test */
1737
		emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1738 1739 1740 1741 1742
		break;
	case 2:	/* not */
		c->dst.val = ~c->dst.val;
		break;
	case 3:	/* neg */
1743
		emulate_1op("neg", c->dst, ctxt->eflags);
1744
		break;
1745 1746 1747 1748 1749 1750 1751
	case 4: /* mul */
		emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
		break;
	case 5: /* imul */
		emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
		break;
	case 6: /* div */
1752 1753
		emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx,
				       ctxt->eflags, de);
1754 1755
		break;
	case 7: /* idiv */
1756 1757
		emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx,
				       ctxt->eflags, de);
1758
		break;
1759
	default:
1760
		return X86EMUL_UNHANDLEABLE;
1761
	}
1762 1763
	if (de)
		return emulate_de(ctxt);
1764
	return X86EMUL_CONTINUE;
1765 1766
}

1767
static int em_grp45(struct x86_emulate_ctxt *ctxt)
1768 1769
{
	struct decode_cache *c = &ctxt->decode;
1770
	int rc = X86EMUL_CONTINUE;
1771 1772 1773

	switch (c->modrm_reg) {
	case 0:	/* inc */
1774
		emulate_1op("inc", c->dst, ctxt->eflags);
1775 1776
		break;
	case 1:	/* dec */
1777
		emulate_1op("dec", c->dst, ctxt->eflags);
1778
		break;
1779 1780 1781 1782 1783
	case 2: /* call near abs */ {
		long int old_eip;
		old_eip = c->eip;
		c->eip = c->src.val;
		c->src.val = old_eip;
1784
		rc = em_push(ctxt);
1785 1786
		break;
	}
1787
	case 4: /* jmp abs */
1788
		c->eip = c->src.val;
1789
		break;
1790 1791 1792
	case 5: /* jmp far */
		rc = em_jmp_far(ctxt);
		break;
1793
	case 6:	/* push */
1794
		rc = em_push(ctxt);
1795 1796
		break;
	}
1797
	return rc;
1798 1799
}

1800
static int em_grp9(struct x86_emulate_ctxt *ctxt)
1801 1802
{
	struct decode_cache *c = &ctxt->decode;
1803
	u64 old = c->dst.orig_val64;
1804 1805 1806 1807 1808

	if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
	    ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
		c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
		c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1809
		ctxt->eflags &= ~EFLG_ZF;
1810
	} else {
1811 1812
		c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
			(u32) c->regs[VCPU_REGS_RBX];
1813

1814
		ctxt->eflags |= EFLG_ZF;
1815
	}
1816
	return X86EMUL_CONTINUE;
1817 1818
}

1819
static int em_ret_far(struct x86_emulate_ctxt *ctxt)
1820 1821 1822 1823 1824
{
	struct decode_cache *c = &ctxt->decode;
	int rc;
	unsigned long cs;

1825
	rc = emulate_pop(ctxt, &c->eip, c->op_bytes);
1826
	if (rc != X86EMUL_CONTINUE)
1827 1828 1829
		return rc;
	if (c->op_bytes == 4)
		c->eip = (u32)c->eip;
1830
	rc = emulate_pop(ctxt, &cs, c->op_bytes);
1831
	if (rc != X86EMUL_CONTINUE)
1832
		return rc;
1833
	rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
1834 1835 1836
	return rc;
}

1837
static int emulate_load_segment(struct x86_emulate_ctxt *ctxt, int seg)
1838 1839 1840 1841 1842 1843 1844
{
	struct decode_cache *c = &ctxt->decode;
	unsigned short sel;
	int rc;

	memcpy(&sel, c->src.valptr + c->op_bytes, 2);

1845
	rc = load_segment_descriptor(ctxt, sel, seg);
1846 1847 1848 1849 1850 1851 1852
	if (rc != X86EMUL_CONTINUE)
		return rc;

	c->dst.val = c->src.val;
	return rc;
}

1853
static void
1854
setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1855
			struct desc_struct *cs, struct desc_struct *ss)
1856
{
1857 1858
	u16 selector;

1859
	memset(cs, 0, sizeof(struct desc_struct));
1860
	ctxt->ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
1861
	memset(ss, 0, sizeof(struct desc_struct));
1862 1863

	cs->l = 0;		/* will be adjusted later */
1864
	set_desc_base(cs, 0);	/* flat segment */
1865
	cs->g = 1;		/* 4kb granularity */
1866
	set_desc_limit(cs, 0xfffff);	/* 4GB limit */
1867 1868 1869
	cs->type = 0x0b;	/* Read, Execute, Accessed */
	cs->s = 1;
	cs->dpl = 0;		/* will be adjusted later */
1870 1871
	cs->p = 1;
	cs->d = 1;
1872

1873 1874
	set_desc_base(ss, 0);	/* flat segment */
	set_desc_limit(ss, 0xfffff);	/* 4GB limit */
1875 1876 1877
	ss->g = 1;		/* 4kb granularity */
	ss->s = 1;
	ss->type = 0x03;	/* Read/Write, Accessed */
1878
	ss->d = 1;		/* 32bit stack segment */
1879
	ss->dpl = 0;
1880
	ss->p = 1;
1881 1882
}

1883
static int em_syscall(struct x86_emulate_ctxt *ctxt)
1884 1885
{
	struct decode_cache *c = &ctxt->decode;
1886
	struct x86_emulate_ops *ops = ctxt->ops;
1887
	struct desc_struct cs, ss;
1888
	u64 msr_data;
1889
	u16 cs_sel, ss_sel;
1890
	u64 efer = 0;
1891 1892

	/* syscall is not available in real mode */
1893
	if (ctxt->mode == X86EMUL_MODE_REAL ||
1894 1895
	    ctxt->mode == X86EMUL_MODE_VM86)
		return emulate_ud(ctxt);
1896

1897
	ops->get_msr(ctxt, MSR_EFER, &efer);
1898
	setup_syscalls_segments(ctxt, &cs, &ss);
1899

1900
	ops->get_msr(ctxt, MSR_STAR, &msr_data);
1901
	msr_data >>= 32;
1902 1903
	cs_sel = (u16)(msr_data & 0xfffc);
	ss_sel = (u16)(msr_data + 8);
1904

1905
	if (efer & EFER_LMA) {
1906
		cs.d = 0;
1907 1908
		cs.l = 1;
	}
1909 1910
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
1911 1912

	c->regs[VCPU_REGS_RCX] = c->eip;
1913
	if (efer & EFER_LMA) {
1914 1915 1916
#ifdef CONFIG_X86_64
		c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;

1917
		ops->get_msr(ctxt,
1918 1919
			     ctxt->mode == X86EMUL_MODE_PROT64 ?
			     MSR_LSTAR : MSR_CSTAR, &msr_data);
1920 1921
		c->eip = msr_data;

1922
		ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
1923 1924 1925 1926
		ctxt->eflags &= ~(msr_data | EFLG_RF);
#endif
	} else {
		/* legacy mode */
1927
		ops->get_msr(ctxt, MSR_STAR, &msr_data);
1928 1929 1930 1931 1932
		c->eip = (u32)msr_data;

		ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
	}

1933
	return X86EMUL_CONTINUE;
1934 1935
}

1936
static int em_sysenter(struct x86_emulate_ctxt *ctxt)
1937 1938
{
	struct decode_cache *c = &ctxt->decode;
1939
	struct x86_emulate_ops *ops = ctxt->ops;
1940
	struct desc_struct cs, ss;
1941
	u64 msr_data;
1942
	u16 cs_sel, ss_sel;
1943
	u64 efer = 0;
1944

1945
	ops->get_msr(ctxt, MSR_EFER, &efer);
1946
	/* inject #GP if in real mode */
1947 1948
	if (ctxt->mode == X86EMUL_MODE_REAL)
		return emulate_gp(ctxt, 0);
1949 1950 1951 1952

	/* XXX sysenter/sysexit have not been tested in 64bit mode.
	* Therefore, we inject an #UD.
	*/
1953 1954
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		return emulate_ud(ctxt);
1955

1956
	setup_syscalls_segments(ctxt, &cs, &ss);
1957

1958
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
1959 1960
	switch (ctxt->mode) {
	case X86EMUL_MODE_PROT32:
1961 1962
		if ((msr_data & 0xfffc) == 0x0)
			return emulate_gp(ctxt, 0);
1963 1964
		break;
	case X86EMUL_MODE_PROT64:
1965 1966
		if (msr_data == 0x0)
			return emulate_gp(ctxt, 0);
1967 1968 1969 1970
		break;
	}

	ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1971 1972 1973 1974
	cs_sel = (u16)msr_data;
	cs_sel &= ~SELECTOR_RPL_MASK;
	ss_sel = cs_sel + 8;
	ss_sel &= ~SELECTOR_RPL_MASK;
1975
	if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
1976
		cs.d = 0;
1977 1978 1979
		cs.l = 1;
	}

1980 1981
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
1982

1983
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
1984 1985
	c->eip = msr_data;

1986
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
1987 1988
	c->regs[VCPU_REGS_RSP] = msr_data;

1989
	return X86EMUL_CONTINUE;
1990 1991
}

1992
static int em_sysexit(struct x86_emulate_ctxt *ctxt)
1993 1994
{
	struct decode_cache *c = &ctxt->decode;
1995
	struct x86_emulate_ops *ops = ctxt->ops;
1996
	struct desc_struct cs, ss;
1997 1998
	u64 msr_data;
	int usermode;
X
Xiao Guangrong 已提交
1999
	u16 cs_sel = 0, ss_sel = 0;
2000

2001 2002
	/* inject #GP if in real mode or Virtual 8086 mode */
	if (ctxt->mode == X86EMUL_MODE_REAL ||
2003 2004
	    ctxt->mode == X86EMUL_MODE_VM86)
		return emulate_gp(ctxt, 0);
2005

2006
	setup_syscalls_segments(ctxt, &cs, &ss);
2007 2008 2009 2010 2011 2012 2013 2014

	if ((c->rex_prefix & 0x8) != 0x0)
		usermode = X86EMUL_MODE_PROT64;
	else
		usermode = X86EMUL_MODE_PROT32;

	cs.dpl = 3;
	ss.dpl = 3;
2015
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2016 2017
	switch (usermode) {
	case X86EMUL_MODE_PROT32:
2018
		cs_sel = (u16)(msr_data + 16);
2019 2020
		if ((msr_data & 0xfffc) == 0x0)
			return emulate_gp(ctxt, 0);
2021
		ss_sel = (u16)(msr_data + 24);
2022 2023
		break;
	case X86EMUL_MODE_PROT64:
2024
		cs_sel = (u16)(msr_data + 32);
2025 2026
		if (msr_data == 0x0)
			return emulate_gp(ctxt, 0);
2027 2028
		ss_sel = cs_sel + 8;
		cs.d = 0;
2029 2030 2031
		cs.l = 1;
		break;
	}
2032 2033
	cs_sel |= SELECTOR_RPL_MASK;
	ss_sel |= SELECTOR_RPL_MASK;
2034

2035 2036
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2037

2038 2039
	c->eip = c->regs[VCPU_REGS_RDX];
	c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
2040

2041
	return X86EMUL_CONTINUE;
2042 2043
}

2044
static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
2045 2046 2047 2048 2049 2050 2051
{
	int iopl;
	if (ctxt->mode == X86EMUL_MODE_REAL)
		return false;
	if (ctxt->mode == X86EMUL_MODE_VM86)
		return true;
	iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
2052
	return ctxt->ops->cpl(ctxt) > iopl;
2053 2054 2055 2056 2057
}

static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
					    u16 port, u16 len)
{
2058
	struct x86_emulate_ops *ops = ctxt->ops;
2059
	struct desc_struct tr_seg;
2060
	u32 base3;
2061
	int r;
2062
	u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
2063
	unsigned mask = (1 << len) - 1;
2064
	unsigned long base;
2065

2066
	ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
2067
	if (!tr_seg.p)
2068
		return false;
2069
	if (desc_limit_scaled(&tr_seg) < 103)
2070
		return false;
2071 2072 2073 2074
	base = get_desc_base(&tr_seg);
#ifdef CONFIG_X86_64
	base |= ((u64)base3) << 32;
#endif
2075
	r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
2076 2077
	if (r != X86EMUL_CONTINUE)
		return false;
2078
	if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
2079
		return false;
2080
	r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
2081 2082 2083 2084 2085 2086 2087 2088 2089 2090
	if (r != X86EMUL_CONTINUE)
		return false;
	if ((perm >> bit_idx) & mask)
		return false;
	return true;
}

static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
				 u16 port, u16 len)
{
2091 2092 2093
	if (ctxt->perm_ok)
		return true;

2094 2095
	if (emulator_bad_iopl(ctxt))
		if (!emulator_io_port_access_allowed(ctxt, port, len))
2096
			return false;
2097 2098 2099

	ctxt->perm_ok = true;

2100 2101 2102
	return true;
}

2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113 2114 2115 2116 2117 2118
static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
				struct tss_segment_16 *tss)
{
	struct decode_cache *c = &ctxt->decode;

	tss->ip = c->eip;
	tss->flag = ctxt->eflags;
	tss->ax = c->regs[VCPU_REGS_RAX];
	tss->cx = c->regs[VCPU_REGS_RCX];
	tss->dx = c->regs[VCPU_REGS_RDX];
	tss->bx = c->regs[VCPU_REGS_RBX];
	tss->sp = c->regs[VCPU_REGS_RSP];
	tss->bp = c->regs[VCPU_REGS_RBP];
	tss->si = c->regs[VCPU_REGS_RSI];
	tss->di = c->regs[VCPU_REGS_RDI];

2119 2120 2121 2122 2123
	tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
	tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
	tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
	tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
	tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146
}

static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
				 struct tss_segment_16 *tss)
{
	struct decode_cache *c = &ctxt->decode;
	int ret;

	c->eip = tss->ip;
	ctxt->eflags = tss->flag | 2;
	c->regs[VCPU_REGS_RAX] = tss->ax;
	c->regs[VCPU_REGS_RCX] = tss->cx;
	c->regs[VCPU_REGS_RDX] = tss->dx;
	c->regs[VCPU_REGS_RBX] = tss->bx;
	c->regs[VCPU_REGS_RSP] = tss->sp;
	c->regs[VCPU_REGS_RBP] = tss->bp;
	c->regs[VCPU_REGS_RSI] = tss->si;
	c->regs[VCPU_REGS_RDI] = tss->di;

	/*
	 * SDM says that segment selectors are loaded before segment
	 * descriptors
	 */
2147 2148 2149 2150 2151
	set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
	set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
	set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
	set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
	set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2152 2153 2154 2155 2156

	/*
	 * Now load segment descriptors. If fault happenes at this stage
	 * it is handled in a context of new task
	 */
2157
	ret = load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR);
2158 2159
	if (ret != X86EMUL_CONTINUE)
		return ret;
2160
	ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
2161 2162
	if (ret != X86EMUL_CONTINUE)
		return ret;
2163
	ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
2164 2165
	if (ret != X86EMUL_CONTINUE)
		return ret;
2166
	ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
2167 2168
	if (ret != X86EMUL_CONTINUE)
		return ret;
2169
	ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
2170 2171 2172 2173 2174 2175 2176 2177 2178 2179
	if (ret != X86EMUL_CONTINUE)
		return ret;

	return X86EMUL_CONTINUE;
}

static int task_switch_16(struct x86_emulate_ctxt *ctxt,
			  u16 tss_selector, u16 old_tss_sel,
			  ulong old_tss_base, struct desc_struct *new_desc)
{
2180
	struct x86_emulate_ops *ops = ctxt->ops;
2181 2182
	struct tss_segment_16 tss_seg;
	int ret;
2183
	u32 new_tss_base = get_desc_base(new_desc);
2184

2185
	ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2186
			    &ctxt->exception);
2187
	if (ret != X86EMUL_CONTINUE)
2188 2189 2190
		/* FIXME: need to provide precise fault address */
		return ret;

2191
	save_state_to_tss16(ctxt, &tss_seg);
2192

2193
	ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2194
			     &ctxt->exception);
2195
	if (ret != X86EMUL_CONTINUE)
2196 2197 2198
		/* FIXME: need to provide precise fault address */
		return ret;

2199
	ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2200
			    &ctxt->exception);
2201
	if (ret != X86EMUL_CONTINUE)
2202 2203 2204 2205 2206 2207
		/* FIXME: need to provide precise fault address */
		return ret;

	if (old_tss_sel != 0xffff) {
		tss_seg.prev_task_link = old_tss_sel;

2208
		ret = ops->write_std(ctxt, new_tss_base,
2209 2210
				     &tss_seg.prev_task_link,
				     sizeof tss_seg.prev_task_link,
2211
				     &ctxt->exception);
2212
		if (ret != X86EMUL_CONTINUE)
2213 2214 2215 2216
			/* FIXME: need to provide precise fault address */
			return ret;
	}

2217
	return load_state_from_tss16(ctxt, &tss_seg);
2218 2219 2220 2221 2222 2223 2224
}

static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
				struct tss_segment_32 *tss)
{
	struct decode_cache *c = &ctxt->decode;

2225
	tss->cr3 = ctxt->ops->get_cr(ctxt, 3);
2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236
	tss->eip = c->eip;
	tss->eflags = ctxt->eflags;
	tss->eax = c->regs[VCPU_REGS_RAX];
	tss->ecx = c->regs[VCPU_REGS_RCX];
	tss->edx = c->regs[VCPU_REGS_RDX];
	tss->ebx = c->regs[VCPU_REGS_RBX];
	tss->esp = c->regs[VCPU_REGS_RSP];
	tss->ebp = c->regs[VCPU_REGS_RBP];
	tss->esi = c->regs[VCPU_REGS_RSI];
	tss->edi = c->regs[VCPU_REGS_RDI];

2237 2238 2239 2240 2241 2242 2243
	tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
	tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
	tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
	tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
	tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
	tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
	tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2244 2245 2246 2247 2248 2249 2250 2251
}

static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
				 struct tss_segment_32 *tss)
{
	struct decode_cache *c = &ctxt->decode;
	int ret;

2252
	if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
2253
		return emulate_gp(ctxt, 0);
2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268
	c->eip = tss->eip;
	ctxt->eflags = tss->eflags | 2;
	c->regs[VCPU_REGS_RAX] = tss->eax;
	c->regs[VCPU_REGS_RCX] = tss->ecx;
	c->regs[VCPU_REGS_RDX] = tss->edx;
	c->regs[VCPU_REGS_RBX] = tss->ebx;
	c->regs[VCPU_REGS_RSP] = tss->esp;
	c->regs[VCPU_REGS_RBP] = tss->ebp;
	c->regs[VCPU_REGS_RSI] = tss->esi;
	c->regs[VCPU_REGS_RDI] = tss->edi;

	/*
	 * SDM says that segment selectors are loaded before segment
	 * descriptors
	 */
2269 2270 2271 2272 2273 2274 2275
	set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
	set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
	set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
	set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
	set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
	set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
	set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
2276 2277 2278 2279 2280

	/*
	 * Now load segment descriptors. If fault happenes at this stage
	 * it is handled in a context of new task
	 */
2281
	ret = load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
2282 2283
	if (ret != X86EMUL_CONTINUE)
		return ret;
2284
	ret = load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES);
2285 2286
	if (ret != X86EMUL_CONTINUE)
		return ret;
2287
	ret = load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS);
2288 2289
	if (ret != X86EMUL_CONTINUE)
		return ret;
2290
	ret = load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS);
2291 2292
	if (ret != X86EMUL_CONTINUE)
		return ret;
2293
	ret = load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS);
2294 2295
	if (ret != X86EMUL_CONTINUE)
		return ret;
2296
	ret = load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS);
2297 2298
	if (ret != X86EMUL_CONTINUE)
		return ret;
2299
	ret = load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS);
2300 2301 2302 2303 2304 2305 2306 2307 2308 2309
	if (ret != X86EMUL_CONTINUE)
		return ret;

	return X86EMUL_CONTINUE;
}

static int task_switch_32(struct x86_emulate_ctxt *ctxt,
			  u16 tss_selector, u16 old_tss_sel,
			  ulong old_tss_base, struct desc_struct *new_desc)
{
2310
	struct x86_emulate_ops *ops = ctxt->ops;
2311 2312
	struct tss_segment_32 tss_seg;
	int ret;
2313
	u32 new_tss_base = get_desc_base(new_desc);
2314

2315
	ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2316
			    &ctxt->exception);
2317
	if (ret != X86EMUL_CONTINUE)
2318 2319 2320
		/* FIXME: need to provide precise fault address */
		return ret;

2321
	save_state_to_tss32(ctxt, &tss_seg);
2322

2323
	ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2324
			     &ctxt->exception);
2325
	if (ret != X86EMUL_CONTINUE)
2326 2327 2328
		/* FIXME: need to provide precise fault address */
		return ret;

2329
	ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2330
			    &ctxt->exception);
2331
	if (ret != X86EMUL_CONTINUE)
2332 2333 2334 2335 2336 2337
		/* FIXME: need to provide precise fault address */
		return ret;

	if (old_tss_sel != 0xffff) {
		tss_seg.prev_task_link = old_tss_sel;

2338
		ret = ops->write_std(ctxt, new_tss_base,
2339 2340
				     &tss_seg.prev_task_link,
				     sizeof tss_seg.prev_task_link,
2341
				     &ctxt->exception);
2342
		if (ret != X86EMUL_CONTINUE)
2343 2344 2345 2346
			/* FIXME: need to provide precise fault address */
			return ret;
	}

2347
	return load_state_from_tss32(ctxt, &tss_seg);
2348 2349 2350
}

static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2351 2352
				   u16 tss_selector, int reason,
				   bool has_error_code, u32 error_code)
2353
{
2354
	struct x86_emulate_ops *ops = ctxt->ops;
2355 2356
	struct desc_struct curr_tss_desc, next_tss_desc;
	int ret;
2357
	u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
2358
	ulong old_tss_base =
2359
		ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
2360
	u32 desc_limit;
2361 2362 2363

	/* FIXME: old_tss_base == ~0 ? */

2364
	ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
2365 2366
	if (ret != X86EMUL_CONTINUE)
		return ret;
2367
	ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
2368 2369 2370 2371 2372 2373 2374
	if (ret != X86EMUL_CONTINUE)
		return ret;

	/* FIXME: check that next_tss_desc is tss */

	if (reason != TASK_SWITCH_IRET) {
		if ((tss_selector & 3) > next_tss_desc.dpl ||
2375
		    ops->cpl(ctxt) > next_tss_desc.dpl)
2376
			return emulate_gp(ctxt, 0);
2377 2378
	}

2379 2380 2381 2382
	desc_limit = desc_limit_scaled(&next_tss_desc);
	if (!next_tss_desc.p ||
	    ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
	     desc_limit < 0x2b)) {
2383
		emulate_ts(ctxt, tss_selector & 0xfffc);
2384 2385 2386 2387 2388
		return X86EMUL_PROPAGATE_FAULT;
	}

	if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
		curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2389
		write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400
	}

	if (reason == TASK_SWITCH_IRET)
		ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;

	/* set back link to prev task only if NT bit is set in eflags
	   note that old_tss_sel is not used afetr this point */
	if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
		old_tss_sel = 0xffff;

	if (next_tss_desc.type & 8)
2401
		ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
2402 2403
				     old_tss_base, &next_tss_desc);
	else
2404
		ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
2405
				     old_tss_base, &next_tss_desc);
2406 2407
	if (ret != X86EMUL_CONTINUE)
		return ret;
2408 2409 2410 2411 2412 2413

	if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
		ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;

	if (reason != TASK_SWITCH_IRET) {
		next_tss_desc.type |= (1 << 1); /* set busy flag */
2414
		write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
2415 2416
	}

2417
	ops->set_cr(ctxt, 0,  ops->get_cr(ctxt, 0) | X86_CR0_TS);
2418
	ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
2419

2420 2421 2422 2423 2424 2425
	if (has_error_code) {
		struct decode_cache *c = &ctxt->decode;

		c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
		c->lock_prefix = 0;
		c->src.val = (unsigned long) error_code;
2426
		ret = em_push(ctxt);
2427 2428
	}

2429 2430 2431 2432
	return ret;
}

int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2433 2434
			 u16 tss_selector, int reason,
			 bool has_error_code, u32 error_code)
2435 2436 2437 2438 2439
{
	struct decode_cache *c = &ctxt->decode;
	int rc;

	c->eip = ctxt->eip;
2440
	c->dst.type = OP_NONE;
2441

2442
	rc = emulator_do_task_switch(ctxt, tss_selector, reason,
2443
				     has_error_code, error_code);
2444

2445 2446
	if (rc == X86EMUL_CONTINUE)
		ctxt->eip = c->eip;
2447

2448
	return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
2449 2450
}

2451
static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
2452
			    int reg, struct operand *op)
2453 2454 2455 2456
{
	struct decode_cache *c = &ctxt->decode;
	int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;

2457
	register_address_increment(c, &c->regs[reg], df * op->bytes);
2458 2459
	op->addr.mem.ea = register_address(c, c->regs[reg]);
	op->addr.mem.seg = seg;
2460 2461
}

2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500
static int em_das(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	u8 al, old_al;
	bool af, cf, old_cf;

	cf = ctxt->eflags & X86_EFLAGS_CF;
	al = c->dst.val;

	old_al = al;
	old_cf = cf;
	cf = false;
	af = ctxt->eflags & X86_EFLAGS_AF;
	if ((al & 0x0f) > 9 || af) {
		al -= 6;
		cf = old_cf | (al >= 250);
		af = true;
	} else {
		af = false;
	}
	if (old_al > 0x99 || old_cf) {
		al -= 0x60;
		cf = true;
	}

	c->dst.val = al;
	/* Set PF, ZF, SF */
	c->src.type = OP_IMM;
	c->src.val = 0;
	c->src.bytes = 1;
	emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
	ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
	if (cf)
		ctxt->eflags |= X86_EFLAGS_CF;
	if (af)
		ctxt->eflags |= X86_EFLAGS_AF;
	return X86EMUL_CONTINUE;
}

2501 2502 2503 2504 2505 2506 2507
static int em_call_far(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	u16 sel, old_cs;
	ulong old_eip;
	int rc;

2508
	old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2509 2510 2511
	old_eip = c->eip;

	memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2512
	if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
2513 2514 2515 2516 2517 2518
		return X86EMUL_CONTINUE;

	c->eip = 0;
	memcpy(&c->eip, c->src.valptr, c->op_bytes);

	c->src.val = old_cs;
2519
	rc = em_push(ctxt);
2520 2521 2522 2523
	if (rc != X86EMUL_CONTINUE)
		return rc;

	c->src.val = old_eip;
2524
	return em_push(ctxt);
2525 2526
}

2527 2528 2529 2530 2531 2532 2533 2534
static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	int rc;

	c->dst.type = OP_REG;
	c->dst.addr.reg = &c->eip;
	c->dst.bytes = c->op_bytes;
2535
	rc = emulate_pop(ctxt, &c->dst.val, c->op_bytes);
2536 2537 2538 2539 2540 2541
	if (rc != X86EMUL_CONTINUE)
		return rc;
	register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
	return X86EMUL_CONTINUE;
}

2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607
static int em_add(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
	return X86EMUL_CONTINUE;
}

static int em_or(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
	return X86EMUL_CONTINUE;
}

static int em_adc(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
	return X86EMUL_CONTINUE;
}

static int em_sbb(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
	return X86EMUL_CONTINUE;
}

static int em_and(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
	return X86EMUL_CONTINUE;
}

static int em_sub(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
	return X86EMUL_CONTINUE;
}

static int em_xor(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
	return X86EMUL_CONTINUE;
}

static int em_cmp(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
	/* Disable writeback. */
	c->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

2608 2609 2610 2611 2612 2613 2614 2615
static int em_test(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
	return X86EMUL_CONTINUE;
}

2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629
static int em_xchg(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	/* Write back the register source. */
	c->src.val = c->dst.val;
	write_register_operand(&c->src);

	/* Write back the memory destination with implicit LOCK prefix. */
	c->dst.val = c->src.orig_val;
	c->lock_prefix = 1;
	return X86EMUL_CONTINUE;
}

2630
static int em_imul(struct x86_emulate_ctxt *ctxt)
2631 2632 2633 2634 2635 2636 2637
{
	struct decode_cache *c = &ctxt->decode;

	emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
	return X86EMUL_CONTINUE;
}

2638 2639 2640 2641 2642 2643 2644 2645
static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	c->dst.val = c->src2.val;
	return em_imul(ctxt);
}

2646 2647 2648 2649 2650 2651 2652 2653 2654 2655 2656 2657
static int em_cwd(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	c->dst.type = OP_REG;
	c->dst.bytes = c->src.bytes;
	c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
	c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);

	return X86EMUL_CONTINUE;
}

2658 2659 2660 2661 2662
static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	u64 tsc = 0;

2663
	ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
2664 2665 2666 2667 2668
	c->regs[VCPU_REGS_RAX] = (u32)tsc;
	c->regs[VCPU_REGS_RDX] = tsc >> 32;
	return X86EMUL_CONTINUE;
}

2669 2670 2671 2672 2673 2674 2675
static int em_mov(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	c->dst.val = c->src.val;
	return X86EMUL_CONTINUE;
}

2676 2677 2678 2679 2680 2681 2682
static int em_movdqu(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	memcpy(&c->dst.vec_val, &c->src.vec_val, c->op_bytes);
	return X86EMUL_CONTINUE;
}

2683 2684 2685
static int em_invlpg(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
2686 2687 2688
	int rc;
	ulong linear;

2689
	rc = linearize(ctxt, c->src.addr.mem, 1, false, &linear);
2690
	if (rc == X86EMUL_CONTINUE)
2691
		ctxt->ops->invlpg(ctxt, linear);
2692 2693 2694 2695 2696
	/* Disable writeback. */
	c->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

2697 2698 2699 2700 2701 2702 2703 2704 2705 2706
static int em_clts(struct x86_emulate_ctxt *ctxt)
{
	ulong cr0;

	cr0 = ctxt->ops->get_cr(ctxt, 0);
	cr0 &= ~X86_CR0_TS;
	ctxt->ops->set_cr(ctxt, 0, cr0);
	return X86EMUL_CONTINUE;
}

2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731
static int em_vmcall(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	int rc;

	if (c->modrm_mod != 3 || c->modrm_rm != 1)
		return X86EMUL_UNHANDLEABLE;

	rc = ctxt->ops->fix_hypercall(ctxt);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	/* Let the processor re-execute the fixed hypercall */
	c->eip = ctxt->eip;
	/* Disable writeback. */
	c->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

static int em_lgdt(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	struct desc_ptr desc_ptr;
	int rc;

2732
	rc = read_descriptor(ctxt, c->src.addr.mem,
2733 2734 2735 2736 2737 2738 2739 2740 2741 2742
			     &desc_ptr.size, &desc_ptr.address,
			     c->op_bytes);
	if (rc != X86EMUL_CONTINUE)
		return rc;
	ctxt->ops->set_gdt(ctxt, &desc_ptr);
	/* Disable writeback. */
	c->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

2743
static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
2744 2745 2746 2747
{
	struct decode_cache *c = &ctxt->decode;
	int rc;

2748 2749
	rc = ctxt->ops->fix_hypercall(ctxt);

2750 2751 2752 2753 2754 2755 2756 2757 2758 2759 2760
	/* Disable writeback. */
	c->dst.type = OP_NONE;
	return rc;
}

static int em_lidt(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	struct desc_ptr desc_ptr;
	int rc;

2761 2762
	rc = read_descriptor(ctxt, c->src.addr.mem,
			     &desc_ptr.size, &desc_ptr.address,
2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789
			     c->op_bytes);
	if (rc != X86EMUL_CONTINUE)
		return rc;
	ctxt->ops->set_idt(ctxt, &desc_ptr);
	/* Disable writeback. */
	c->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

static int em_smsw(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	c->dst.bytes = 2;
	c->dst.val = ctxt->ops->get_cr(ctxt, 0);
	return X86EMUL_CONTINUE;
}

static int em_lmsw(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
			  | (c->src.val & 0x0f));
	c->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816
static bool valid_cr(int nr)
{
	switch (nr) {
	case 0:
	case 2 ... 4:
	case 8:
		return true;
	default:
		return false;
	}
}

static int check_cr_read(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	if (!valid_cr(c->modrm_reg))
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_cr_write(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	u64 new_val = c->src.val64;
	int cr = c->modrm_reg;
2817
	u64 efer = 0;
2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834

	static u64 cr_reserved_bits[] = {
		0xffffffff00000000ULL,
		0, 0, 0, /* CR3 checked later */
		CR4_RESERVED_BITS,
		0, 0, 0,
		CR8_RESERVED_BITS,
	};

	if (!valid_cr(cr))
		return emulate_ud(ctxt);

	if (new_val & cr_reserved_bits[cr])
		return emulate_gp(ctxt, 0);

	switch (cr) {
	case 0: {
2835
		u64 cr4;
2836 2837 2838 2839
		if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
		    ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
			return emulate_gp(ctxt, 0);

2840 2841
		cr4 = ctxt->ops->get_cr(ctxt, 4);
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2842 2843 2844 2845 2846 2847 2848 2849 2850 2851

		if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
		    !(cr4 & X86_CR4_PAE))
			return emulate_gp(ctxt, 0);

		break;
		}
	case 3: {
		u64 rsvd = 0;

2852 2853
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
		if (efer & EFER_LMA)
2854
			rsvd = CR3_L_MODE_RESERVED_BITS;
2855
		else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
2856
			rsvd = CR3_PAE_RESERVED_BITS;
2857
		else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
2858 2859 2860 2861 2862 2863 2864 2865
			rsvd = CR3_NONPAE_RESERVED_BITS;

		if (new_val & rsvd)
			return emulate_gp(ctxt, 0);

		break;
		}
	case 4: {
2866
		u64 cr4;
2867

2868 2869
		cr4 = ctxt->ops->get_cr(ctxt, 4);
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880

		if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
			return emulate_gp(ctxt, 0);

		break;
		}
	}

	return X86EMUL_CONTINUE;
}

2881 2882 2883 2884
static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
{
	unsigned long dr7;

2885
	ctxt->ops->get_dr(ctxt, 7, &dr7);
2886 2887 2888 2889 2890 2891 2892 2893 2894 2895 2896 2897 2898 2899

	/* Check if DR7.Global_Enable is set */
	return dr7 & (1 << 13);
}

static int check_dr_read(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	int dr = c->modrm_reg;
	u64 cr4;

	if (dr > 7)
		return emulate_ud(ctxt);

2900
	cr4 = ctxt->ops->get_cr(ctxt, 4);
2901 2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921
	if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
		return emulate_ud(ctxt);

	if (check_dr7_gd(ctxt))
		return emulate_db(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_dr_write(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	u64 new_val = c->src.val64;
	int dr = c->modrm_reg;

	if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
		return emulate_gp(ctxt, 0);

	return check_dr_read(ctxt);
}

2922 2923 2924 2925
static int check_svme(struct x86_emulate_ctxt *ctxt)
{
	u64 efer;

2926
	ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2927 2928 2929 2930 2931 2932 2933 2934 2935

	if (!(efer & EFER_SVME))
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
{
2936
	u64 rax = ctxt->decode.regs[VCPU_REGS_RAX];
2937 2938

	/* Valid physical address? */
2939
	if (rax & 0xffff000000000000ULL)
2940 2941 2942 2943 2944
		return emulate_gp(ctxt, 0);

	return check_svme(ctxt);
}

2945 2946
static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
{
2947
	u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
2948

2949
	if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
2950 2951 2952 2953 2954
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

2955 2956
static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
{
2957
	u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
2958
	u64 rcx = ctxt->decode.regs[VCPU_REGS_RCX];
2959

2960
	if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
2961 2962 2963 2964 2965 2966
	    (rcx > 3))
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

2967 2968 2969 2970 2971
static int check_perm_in(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	c->dst.bytes = min(c->dst.bytes, 4u);
2972
	if (!emulator_io_permited(ctxt, c->src.val, c->dst.bytes))
2973 2974 2975 2976 2977 2978 2979 2980 2981 2982
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

static int check_perm_out(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	c->src.bytes = min(c->src.bytes, 4u);
2983
	if (!emulator_io_permited(ctxt, c->dst.val, c->src.bytes))
2984 2985 2986 2987 2988
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

2989
#define D(_y) { .flags = (_y) }
2990
#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
2991 2992
#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
		      .check_perm = (_p) }
2993
#define N    D(0)
2994
#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
2995
#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2996
#define GD(_f, _g) { .flags = ((_f) | GroupDual), .u.gdual = (_g) }
2997
#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2998 2999
#define II(_f, _e, _i) \
	{ .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
3000 3001 3002
#define IIP(_f, _e, _i, _p) \
	{ .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
	  .check_perm = (_p) }
3003
#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
3004

3005
#define D2bv(_f)      D((_f) | ByteOp), D(_f)
3006
#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
3007 3008
#define I2bv(_f, _e)  I((_f) | ByteOp, _e), I(_f, _e)

3009 3010 3011
#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e),		\
		I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e),	\
		I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
3012

3013 3014 3015 3016 3017 3018
static struct opcode group7_rm1[] = {
	DI(SrcNone | ModRM | Priv, monitor),
	DI(SrcNone | ModRM | Priv, mwait),
	N, N, N, N, N, N,
};

3019 3020
static struct opcode group7_rm3[] = {
	DIP(SrcNone | ModRM | Prot | Priv, vmrun,   check_svme_pa),
3021
	II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall),
3022 3023 3024 3025 3026 3027 3028
	DIP(SrcNone | ModRM | Prot | Priv, vmload,  check_svme_pa),
	DIP(SrcNone | ModRM | Prot | Priv, vmsave,  check_svme_pa),
	DIP(SrcNone | ModRM | Prot | Priv, stgi,    check_svme),
	DIP(SrcNone | ModRM | Prot | Priv, clgi,    check_svme),
	DIP(SrcNone | ModRM | Prot | Priv, skinit,  check_svme),
	DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
};
3029

3030 3031 3032 3033 3034
static struct opcode group7_rm7[] = {
	N,
	DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
	N, N, N, N, N, N,
};
3035

3036
static struct opcode group1[] = {
3037 3038 3039 3040 3041 3042 3043 3044
	I(Lock, em_add),
	I(Lock, em_or),
	I(Lock, em_adc),
	I(Lock, em_sbb),
	I(Lock, em_and),
	I(Lock, em_sub),
	I(Lock, em_xor),
	I(0, em_cmp),
3045 3046 3047 3048 3049 3050 3051 3052 3053
};

static struct opcode group1A[] = {
	D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
};

static struct opcode group3[] = {
	D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
	D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3054
	X4(D(SrcMem | ModRM)),
3055 3056 3057 3058 3059 3060 3061 3062 3063
};

static struct opcode group4[] = {
	D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
	N, N, N, N, N, N,
};

static struct opcode group5[] = {
	D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3064 3065
	D(SrcMem | ModRM | Stack),
	I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
3066 3067 3068 3069
	D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
	D(SrcMem | ModRM | Stack), N,
};

3070 3071 3072 3073 3074 3075 3076 3077
static struct opcode group6[] = {
	DI(ModRM | Prot,        sldt),
	DI(ModRM | Prot,        str),
	DI(ModRM | Prot | Priv, lldt),
	DI(ModRM | Prot | Priv, ltr),
	N, N, N, N,
};

3078
static struct group_dual group7 = { {
3079 3080
	DI(ModRM | Mov | DstMem | Priv, sgdt),
	DI(ModRM | Mov | DstMem | Priv, sidt),
3081 3082 3083 3084 3085
	II(ModRM | SrcMem | Priv, em_lgdt, lgdt),
	II(ModRM | SrcMem | Priv, em_lidt, lidt),
	II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
	II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw),
	II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
3086
}, {
3087 3088
	I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall),
	EXT(0, group7_rm1),
3089
	N, EXT(0, group7_rm3),
3090 3091
	II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
	II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7),
3092 3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105
} };

static struct opcode group8[] = {
	N, N, N, N,
	D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
	D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
};

static struct group_dual group9 = { {
	N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
}, {
	N, N, N, N, N, N, N, N,
} };

3106 3107 3108 3109
static struct opcode group11[] = {
	I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
};

3110 3111 3112 3113
static struct gprefix pfx_0f_6f_0f_7f = {
	N, N, N, I(Sse, em_movdqu),
};

3114 3115
static struct opcode opcode_table[256] = {
	/* 0x00 - 0x07 */
3116
	I6ALU(Lock, em_add),
3117 3118
	D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
	/* 0x08 - 0x0F */
3119
	I6ALU(Lock, em_or),
3120 3121
	D(ImplicitOps | Stack | No64), N,
	/* 0x10 - 0x17 */
3122
	I6ALU(Lock, em_adc),
3123 3124
	D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
	/* 0x18 - 0x1F */
3125
	I6ALU(Lock, em_sbb),
3126 3127
	D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
	/* 0x20 - 0x27 */
3128
	I6ALU(Lock, em_and), N, N,
3129
	/* 0x28 - 0x2F */
3130
	I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
3131
	/* 0x30 - 0x37 */
3132
	I6ALU(Lock, em_xor), N, N,
3133
	/* 0x38 - 0x3F */
3134
	I6ALU(0, em_cmp), N, N,
3135 3136 3137
	/* 0x40 - 0x4F */
	X16(D(DstReg)),
	/* 0x50 - 0x57 */
3138
	X8(I(SrcReg | Stack, em_push)),
3139
	/* 0x58 - 0x5F */
3140
	X8(I(DstReg | Stack, em_pop)),
3141
	/* 0x60 - 0x67 */
3142 3143
	I(ImplicitOps | Stack | No64, em_pusha),
	I(ImplicitOps | Stack | No64, em_popa),
3144 3145 3146
	N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
	N, N, N, N,
	/* 0x68 - 0x6F */
3147 3148
	I(SrcImm | Mov | Stack, em_push),
	I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
3149 3150
	I(SrcImmByte | Mov | Stack, em_push),
	I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
3151 3152
	D2bvIP(DstDI | SrcDX | Mov | String, ins, check_perm_in), /* insb, insw/insd */
	D2bvIP(SrcSI | DstDX | String, outs, check_perm_out), /* outsb, outsw/outsd */
3153 3154 3155 3156 3157 3158 3159
	/* 0x70 - 0x7F */
	X16(D(SrcImmByte)),
	/* 0x80 - 0x87 */
	G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
	G(DstMem | SrcImm | ModRM | Group, group1),
	G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
	G(DstMem | SrcImmByte | ModRM | Group, group1),
3160
	I2bv(DstMem | SrcReg | ModRM, em_test),
3161
	I2bv(DstMem | SrcReg | ModRM | Lock, em_xchg),
3162
	/* 0x88 - 0x8F */
3163 3164
	I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
	I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
3165
	D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
3166 3167
	D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
	/* 0x90 - 0x97 */
3168
	DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
3169
	/* 0x98 - 0x9F */
3170
	D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
3171
	I(SrcImmFAddr | No64, em_call_far), N,
3172 3173
	II(ImplicitOps | Stack, em_pushf, pushf),
	II(ImplicitOps | Stack, em_popf, popf), N, N,
3174
	/* 0xA0 - 0xA7 */
3175 3176 3177
	I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
	I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
	I2bv(SrcSI | DstDI | Mov | String, em_mov),
3178
	I2bv(SrcSI | DstDI | String, em_cmp),
3179
	/* 0xA8 - 0xAF */
3180
	I2bv(DstAcc | SrcImm, em_test),
3181 3182
	I2bv(SrcAcc | DstDI | Mov | String, em_mov),
	I2bv(SrcSI | DstAcc | Mov | String, em_mov),
3183
	I2bv(SrcAcc | DstDI | String, em_cmp),
3184
	/* 0xB0 - 0xB7 */
3185
	X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
3186
	/* 0xB8 - 0xBF */
3187
	X8(I(DstReg | SrcImm | Mov, em_mov)),
3188
	/* 0xC0 - 0xC7 */
3189
	D2bv(DstMem | SrcImmByte | ModRM),
3190 3191
	I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
	D(ImplicitOps | Stack),
3192
	D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
3193
	G(ByteOp, group11), G(0, group11),
3194
	/* 0xC8 - 0xCF */
3195
	N, N, N, I(ImplicitOps | Stack, em_ret_far),
3196
	D(ImplicitOps), DI(SrcImmByte, intn),
3197
	D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
3198
	/* 0xD0 - 0xD7 */
3199
	D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
3200 3201 3202 3203
	N, N, N, N,
	/* 0xD8 - 0xDF */
	N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xE7 */
3204
	X4(D(SrcImmByte)),
3205 3206
	D2bvIP(SrcImmUByte | DstAcc, in,  check_perm_in),
	D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
3207 3208
	/* 0xE8 - 0xEF */
	D(SrcImm | Stack), D(SrcImm | ImplicitOps),
3209
	I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
3210 3211
	D2bvIP(SrcDX | DstAcc, in,  check_perm_in),
	D2bvIP(SrcAcc | DstDX, out, check_perm_out),
3212
	/* 0xF0 - 0xF7 */
3213
	N, DI(ImplicitOps, icebp), N, N,
3214 3215
	DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
	G(ByteOp, group3), G(0, group3),
3216
	/* 0xF8 - 0xFF */
3217
	D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
3218 3219 3220 3221 3222
	D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
};

static struct opcode twobyte_table[256] = {
	/* 0x00 - 0x0F */
3223
	G(0, group6), GD(0, &group7), N, N,
3224 3225
	N, I(ImplicitOps | VendorSpecific, em_syscall),
	II(ImplicitOps | Priv, em_clts, clts), N,
3226
	DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3227 3228 3229 3230
	N, D(ImplicitOps | ModRM), N, N,
	/* 0x10 - 0x1F */
	N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
	/* 0x20 - 0x2F */
3231
	DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3232
	DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
3233
	DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
3234
	DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
3235 3236 3237
	N, N, N, N,
	N, N, N, N, N, N, N, N,
	/* 0x30 - 0x3F */
3238 3239 3240 3241
	DI(ImplicitOps | Priv, wrmsr),
	IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
	DI(ImplicitOps | Priv, rdmsr),
	DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
3242 3243
	I(ImplicitOps | VendorSpecific, em_sysenter),
	I(ImplicitOps | Priv | VendorSpecific, em_sysexit),
3244
	N, N,
3245 3246 3247 3248 3249 3250
	N, N, N, N, N, N, N, N,
	/* 0x40 - 0x4F */
	X16(D(DstReg | SrcMem | ModRM | Mov)),
	/* 0x50 - 0x5F */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0x60 - 0x6F */
3251 3252 3253 3254
	N, N, N, N,
	N, N, N, N,
	N, N, N, N,
	N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
3255
	/* 0x70 - 0x7F */
3256 3257 3258 3259
	N, N, N, N,
	N, N, N, N,
	N, N, N, N,
	N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
3260 3261 3262
	/* 0x80 - 0x8F */
	X16(D(SrcImm)),
	/* 0x90 - 0x9F */
3263
	X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
3264 3265
	/* 0xA0 - 0xA7 */
	D(ImplicitOps | Stack), D(ImplicitOps | Stack),
3266
	DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
3267 3268 3269 3270
	D(DstMem | SrcReg | Src2ImmByte | ModRM),
	D(DstMem | SrcReg | Src2CL | ModRM), N, N,
	/* 0xA8 - 0xAF */
	D(ImplicitOps | Stack), D(ImplicitOps | Stack),
3271
	DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3272 3273
	D(DstMem | SrcReg | Src2ImmByte | ModRM),
	D(DstMem | SrcReg | Src2CL | ModRM),
3274
	D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
3275
	/* 0xB0 - 0xB7 */
3276
	D2bv(DstMem | SrcReg | ModRM | Lock),
3277 3278 3279
	D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
	D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
	D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3280 3281
	/* 0xB8 - 0xBF */
	N, N,
3282
	G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3283 3284
	D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
	D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3285
	/* 0xC0 - 0xCF */
3286
	D2bv(DstMem | SrcReg | ModRM | Lock),
3287
	N, D(DstMem | SrcReg | ModRM | Mov),
3288 3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302
	N, N, N, GD(0, &group9),
	N, N, N, N, N, N, N, N,
	/* 0xD0 - 0xDF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xEF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0xF0 - 0xFF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
};

#undef D
#undef N
#undef G
#undef GD
#undef I
3303
#undef GP
3304
#undef EXT
3305

3306
#undef D2bv
3307
#undef D2bvIP
3308
#undef I2bv
3309
#undef I6ALU
3310

3311 3312 3313 3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328
static unsigned imm_size(struct decode_cache *c)
{
	unsigned size;

	size = (c->d & ByteOp) ? 1 : c->op_bytes;
	if (size == 8)
		size = 4;
	return size;
}

static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
		      unsigned size, bool sign_extension)
{
	struct decode_cache *c = &ctxt->decode;
	int rc = X86EMUL_CONTINUE;

	op->type = OP_IMM;
	op->bytes = size;
3329
	op->addr.mem.ea = c->eip;
3330 3331 3332 3333 3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358
	/* NB. Immediates are sign-extended as necessary. */
	switch (op->bytes) {
	case 1:
		op->val = insn_fetch(s8, 1, c->eip);
		break;
	case 2:
		op->val = insn_fetch(s16, 2, c->eip);
		break;
	case 4:
		op->val = insn_fetch(s32, 4, c->eip);
		break;
	}
	if (!sign_extension) {
		switch (op->bytes) {
		case 1:
			op->val &= 0xff;
			break;
		case 2:
			op->val &= 0xffff;
			break;
		case 4:
			op->val &= 0xffffffff;
			break;
		}
	}
done:
	return rc;
}

3359
int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
3360 3361 3362 3363
{
	struct decode_cache *c = &ctxt->decode;
	int rc = X86EMUL_CONTINUE;
	int mode = ctxt->mode;
3364
	int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
3365
	bool op_prefix = false;
3366
	struct opcode opcode;
3367
	struct operand memop = { .type = OP_NONE }, *memopp = NULL;
3368 3369

	c->eip = ctxt->eip;
3370 3371 3372 3373
	c->fetch.start = c->eip;
	c->fetch.end = c->fetch.start + insn_len;
	if (insn_len > 0)
		memcpy(c->fetch.data, insn, insn_len);
3374 3375 3376 3377 3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399 3400

	switch (mode) {
	case X86EMUL_MODE_REAL:
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
		def_op_bytes = def_ad_bytes = 2;
		break;
	case X86EMUL_MODE_PROT32:
		def_op_bytes = def_ad_bytes = 4;
		break;
#ifdef CONFIG_X86_64
	case X86EMUL_MODE_PROT64:
		def_op_bytes = 4;
		def_ad_bytes = 8;
		break;
#endif
	default:
		return -1;
	}

	c->op_bytes = def_op_bytes;
	c->ad_bytes = def_ad_bytes;

	/* Legacy prefixes. */
	for (;;) {
		switch (c->b = insn_fetch(u8, 1, c->eip)) {
		case 0x66:	/* operand-size override */
3401
			op_prefix = true;
3402 3403 3404 3405 3406 3407 3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432
			/* switch between 2/4 bytes */
			c->op_bytes = def_op_bytes ^ 6;
			break;
		case 0x67:	/* address-size override */
			if (mode == X86EMUL_MODE_PROT64)
				/* switch between 4/8 bytes */
				c->ad_bytes = def_ad_bytes ^ 12;
			else
				/* switch between 2/4 bytes */
				c->ad_bytes = def_ad_bytes ^ 6;
			break;
		case 0x26:	/* ES override */
		case 0x2e:	/* CS override */
		case 0x36:	/* SS override */
		case 0x3e:	/* DS override */
			set_seg_override(c, (c->b >> 3) & 3);
			break;
		case 0x64:	/* FS override */
		case 0x65:	/* GS override */
			set_seg_override(c, c->b & 7);
			break;
		case 0x40 ... 0x4f: /* REX */
			if (mode != X86EMUL_MODE_PROT64)
				goto done_prefixes;
			c->rex_prefix = c->b;
			continue;
		case 0xf0:	/* LOCK */
			c->lock_prefix = 1;
			break;
		case 0xf2:	/* REPNE/REPNZ */
		case 0xf3:	/* REP/REPE/REPZ */
3433
			c->rep_prefix = c->b;
3434 3435 3436 3437 3438 3439 3440 3441 3442 3443 3444 3445 3446
			break;
		default:
			goto done_prefixes;
		}

		/* Any legacy prefix after a REX prefix nullifies its effect. */

		c->rex_prefix = 0;
	}

done_prefixes:

	/* REX prefix. */
3447 3448
	if (c->rex_prefix & 8)
		c->op_bytes = 8;	/* REX.W */
3449 3450 3451

	/* Opcode byte(s). */
	opcode = opcode_table[c->b];
3452 3453 3454 3455 3456
	/* Two-byte opcode? */
	if (c->b == 0x0f) {
		c->twobyte = 1;
		c->b = insn_fetch(u8, 1, c->eip);
		opcode = twobyte_table[c->b];
3457 3458 3459
	}
	c->d = opcode.flags;

3460 3461 3462 3463 3464 3465 3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477
	while (c->d & GroupMask) {
		switch (c->d & GroupMask) {
		case Group:
			c->modrm = insn_fetch(u8, 1, c->eip);
			--c->eip;
			goffset = (c->modrm >> 3) & 7;
			opcode = opcode.u.group[goffset];
			break;
		case GroupDual:
			c->modrm = insn_fetch(u8, 1, c->eip);
			--c->eip;
			goffset = (c->modrm >> 3) & 7;
			if ((c->modrm >> 6) == 3)
				opcode = opcode.u.gdual->mod3[goffset];
			else
				opcode = opcode.u.gdual->mod012[goffset];
			break;
		case RMExt:
3478 3479
			goffset = c->modrm & 7;
			opcode = opcode.u.group[goffset];
3480 3481 3482 3483 3484 3485 3486 3487 3488 3489 3490 3491 3492
			break;
		case Prefix:
			if (c->rep_prefix && op_prefix)
				return X86EMUL_UNHANDLEABLE;
			simd_prefix = op_prefix ? 0x66 : c->rep_prefix;
			switch (simd_prefix) {
			case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
			case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
			case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
			case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
			}
			break;
		default:
3493 3494
			return X86EMUL_UNHANDLEABLE;
		}
3495 3496

		c->d &= ~GroupMask;
3497 3498 3499
		c->d |= opcode.flags;
	}

3500
	c->execute = opcode.u.execute;
3501
	c->check_perm = opcode.check_perm;
3502
	c->intercept = opcode.intercept;
3503 3504

	/* Unrecognised? */
A
Avi Kivity 已提交
3505
	if (c->d == 0 || (c->d & Undefined))
3506 3507
		return -1;

3508 3509 3510
	if (!(c->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
		return -1;

3511 3512 3513
	if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
		c->op_bytes = 8;

3514 3515 3516 3517 3518 3519 3520
	if (c->d & Op3264) {
		if (mode == X86EMUL_MODE_PROT64)
			c->op_bytes = 8;
		else
			c->op_bytes = 4;
	}

A
Avi Kivity 已提交
3521 3522 3523
	if (c->d & Sse)
		c->op_bytes = 16;

3524
	/* ModRM and SIB bytes. */
3525
	if (c->d & ModRM) {
3526
		rc = decode_modrm(ctxt, &memop);
3527 3528 3529
		if (!c->has_seg_override)
			set_seg_override(c, c->modrm_seg);
	} else if (c->d & MemAbs)
3530
		rc = decode_abs(ctxt, &memop);
3531 3532 3533 3534 3535 3536
	if (rc != X86EMUL_CONTINUE)
		goto done;

	if (!c->has_seg_override)
		set_seg_override(c, VCPU_SREG_DS);

3537
	memop.addr.mem.seg = seg_override(ctxt, c);
3538

3539
	if (memop.type == OP_MEM && c->ad_bytes != 8)
3540
		memop.addr.mem.ea = (u32)memop.addr.mem.ea;
3541 3542 3543 3544 3545 3546 3547 3548 3549

	/*
	 * Decode and fetch the source operand: register, memory
	 * or immediate.
	 */
	switch (c->d & SrcMask) {
	case SrcNone:
		break;
	case SrcReg:
A
Avi Kivity 已提交
3550
		decode_register_operand(ctxt, &c->src, c, 0);
3551 3552
		break;
	case SrcMem16:
3553
		memop.bytes = 2;
3554 3555
		goto srcmem_common;
	case SrcMem32:
3556
		memop.bytes = 4;
3557 3558
		goto srcmem_common;
	case SrcMem:
3559
		memop.bytes = (c->d & ByteOp) ? 1 :
3560 3561
							   c->op_bytes;
	srcmem_common:
3562
		c->src = memop;
3563
		memopp = &c->src;
3564
		break;
3565
	case SrcImmU16:
3566 3567
		rc = decode_imm(ctxt, &c->src, 2, false);
		break;
3568
	case SrcImm:
3569 3570
		rc = decode_imm(ctxt, &c->src, imm_size(c), true);
		break;
3571
	case SrcImmU:
3572
		rc = decode_imm(ctxt, &c->src, imm_size(c), false);
3573 3574
		break;
	case SrcImmByte:
3575 3576
		rc = decode_imm(ctxt, &c->src, 1, true);
		break;
3577
	case SrcImmUByte:
3578
		rc = decode_imm(ctxt, &c->src, 1, false);
3579 3580 3581 3582
		break;
	case SrcAcc:
		c->src.type = OP_REG;
		c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3583
		c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
3584
		fetch_register_operand(&c->src);
3585 3586 3587 3588 3589 3590 3591 3592
		break;
	case SrcOne:
		c->src.bytes = 1;
		c->src.val = 1;
		break;
	case SrcSI:
		c->src.type = OP_MEM;
		c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3593 3594
		c->src.addr.mem.ea =
			register_address(c, c->regs[VCPU_REGS_RSI]);
3595
		c->src.addr.mem.seg = seg_override(ctxt, c);
3596 3597 3598 3599
		c->src.val = 0;
		break;
	case SrcImmFAddr:
		c->src.type = OP_IMM;
3600
		c->src.addr.mem.ea = c->eip;
3601 3602 3603 3604
		c->src.bytes = c->op_bytes + 2;
		insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
		break;
	case SrcMemFAddr:
3605 3606
		memop.bytes = c->op_bytes + 2;
		goto srcmem_common;
3607
		break;
3608 3609 3610 3611 3612 3613
	case SrcDX:
		c->src.type = OP_REG;
		c->src.bytes = 2;
		c->src.addr.reg = &c->regs[VCPU_REGS_RDX];
		fetch_register_operand(&c->src);
		break;
3614 3615
	}

3616 3617 3618
	if (rc != X86EMUL_CONTINUE)
		goto done;

3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630
	/*
	 * Decode and fetch the second source operand: register, memory
	 * or immediate.
	 */
	switch (c->d & Src2Mask) {
	case Src2None:
		break;
	case Src2CL:
		c->src2.bytes = 1;
		c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
		break;
	case Src2ImmByte:
3631
		rc = decode_imm(ctxt, &c->src2, 1, true);
3632 3633 3634 3635 3636
		break;
	case Src2One:
		c->src2.bytes = 1;
		c->src2.val = 1;
		break;
3637 3638 3639
	case Src2Imm:
		rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
		break;
3640 3641
	}

3642 3643 3644
	if (rc != X86EMUL_CONTINUE)
		goto done;

3645 3646 3647
	/* Decode and fetch the destination operand: register or memory. */
	switch (c->d & DstMask) {
	case DstReg:
A
Avi Kivity 已提交
3648
		decode_register_operand(ctxt, &c->dst, c,
3649 3650
			 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
		break;
3651 3652
	case DstImmUByte:
		c->dst.type = OP_IMM;
3653
		c->dst.addr.mem.ea = c->eip;
3654 3655 3656
		c->dst.bytes = 1;
		c->dst.val = insn_fetch(u8, 1, c->eip);
		break;
3657 3658
	case DstMem:
	case DstMem64:
3659
		c->dst = memop;
3660
		memopp = &c->dst;
3661 3662 3663 3664
		if ((c->d & DstMask) == DstMem64)
			c->dst.bytes = 8;
		else
			c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3665 3666
		if (c->d & BitOp)
			fetch_bit_operand(c);
3667
		c->dst.orig_val = c->dst.val;
3668 3669 3670 3671
		break;
	case DstAcc:
		c->dst.type = OP_REG;
		c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3672
		c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
3673
		fetch_register_operand(&c->dst);
3674 3675 3676 3677 3678
		c->dst.orig_val = c->dst.val;
		break;
	case DstDI:
		c->dst.type = OP_MEM;
		c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3679 3680 3681
		c->dst.addr.mem.ea =
			register_address(c, c->regs[VCPU_REGS_RDI]);
		c->dst.addr.mem.seg = VCPU_SREG_ES;
3682 3683
		c->dst.val = 0;
		break;
3684 3685 3686 3687 3688 3689
	case DstDX:
		c->dst.type = OP_REG;
		c->dst.bytes = 2;
		c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
		fetch_register_operand(&c->dst);
		break;
3690 3691 3692 3693
	case ImplicitOps:
		/* Special instructions do their own operand decoding. */
	default:
		c->dst.type = OP_NONE; /* Disable writeback. */
3694
		break;
3695 3696 3697
	}

done:
3698 3699 3700
	if (memopp && memopp->type == OP_MEM && c->rip_relative)
		memopp->addr.mem.ea += c->eip;

3701
	return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
3702 3703
}

3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725
static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	/* The second termination condition only applies for REPE
	 * and REPNE. Test if the repeat string operation prefix is
	 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
	 * corresponding termination condition according to:
	 * 	- if REPE/REPZ and ZF = 0 then done
	 * 	- if REPNE/REPNZ and ZF = 1 then done
	 */
	if (((c->b == 0xa6) || (c->b == 0xa7) ||
	     (c->b == 0xae) || (c->b == 0xaf))
	    && (((c->rep_prefix == REPE_PREFIX) &&
		 ((ctxt->eflags & EFLG_ZF) == 0))
		|| ((c->rep_prefix == REPNE_PREFIX) &&
		    ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
		return true;

	return false;
}

3726
int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
3727
{
3728
	struct x86_emulate_ops *ops = ctxt->ops;
3729 3730
	u64 msr_data;
	struct decode_cache *c = &ctxt->decode;
3731
	int rc = X86EMUL_CONTINUE;
3732
	int saved_dst_type = c->dst.type;
3733
	int irq; /* Used for int 3, int, and into */
3734

3735
	c->mem_read.pos = 0;
3736

3737
	if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
3738
		rc = emulate_ud(ctxt);
3739 3740 3741
		goto done;
	}

3742
	/* LOCK prefix is allowed only with some instructions */
3743
	if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
3744
		rc = emulate_ud(ctxt);
3745 3746 3747
		goto done;
	}

3748
	if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
3749
		rc = emulate_ud(ctxt);
3750 3751 3752
		goto done;
	}

A
Avi Kivity 已提交
3753
	if ((c->d & Sse)
3754 3755
	    && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)
		|| !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
A
Avi Kivity 已提交
3756 3757 3758 3759
		rc = emulate_ud(ctxt);
		goto done;
	}

3760
	if ((c->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
A
Avi Kivity 已提交
3761 3762 3763 3764
		rc = emulate_nm(ctxt);
		goto done;
	}

3765
	if (unlikely(ctxt->guest_mode) && c->intercept) {
3766 3767
		rc = emulator_check_intercept(ctxt, c->intercept,
					      X86_ICPT_PRE_EXCEPT);
3768 3769 3770 3771
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

3772
	/* Privileged instruction can be executed only in CPL=0 */
3773
	if ((c->d & Priv) && ops->cpl(ctxt)) {
3774
		rc = emulate_gp(ctxt, 0);
3775 3776 3777
		goto done;
	}

3778 3779 3780 3781 3782 3783
	/* Instruction can only be executed in protected mode */
	if ((c->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
		rc = emulate_ud(ctxt);
		goto done;
	}

3784 3785 3786 3787 3788 3789 3790
	/* Do instruction specific permission checks */
	if (c->check_perm) {
		rc = c->check_perm(ctxt);
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

3791
	if (unlikely(ctxt->guest_mode) && c->intercept) {
3792 3793
		rc = emulator_check_intercept(ctxt, c->intercept,
					      X86_ICPT_POST_EXCEPT);
3794 3795 3796 3797
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

3798 3799
	if (c->rep_prefix && (c->d & String)) {
		/* All REP prefixes have the same first termination condition */
3800
		if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
3801
			ctxt->eip = c->eip;
3802 3803 3804 3805
			goto done;
		}
	}

3806
	if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
3807 3808
		rc = segmented_read(ctxt, c->src.addr.mem,
				    c->src.valptr, c->src.bytes);
3809
		if (rc != X86EMUL_CONTINUE)
3810
			goto done;
3811
		c->src.orig_val64 = c->src.val64;
3812 3813
	}

3814
	if (c->src2.type == OP_MEM) {
3815 3816
		rc = segmented_read(ctxt, c->src2.addr.mem,
				    &c->src2.val, c->src2.bytes);
3817 3818 3819 3820
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

3821 3822 3823 3824
	if ((c->d & DstMask) == ImplicitOps)
		goto special_insn;


3825 3826
	if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
		/* optimisation - avoid slow emulated read if Mov */
3827
		rc = segmented_read(ctxt, c->dst.addr.mem,
3828
				   &c->dst.val, c->dst.bytes);
3829 3830
		if (rc != X86EMUL_CONTINUE)
			goto done;
3831
	}
3832
	c->dst.orig_val = c->dst.val;
3833

3834 3835
special_insn:

3836
	if (unlikely(ctxt->guest_mode) && c->intercept) {
3837 3838
		rc = emulator_check_intercept(ctxt, c->intercept,
					      X86_ICPT_POST_MEMACCESS);
3839 3840 3841 3842
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

3843 3844 3845 3846 3847 3848 3849
	if (c->execute) {
		rc = c->execute(ctxt);
		if (rc != X86EMUL_CONTINUE)
			goto done;
		goto writeback;
	}

3850
	if (c->twobyte)
A
Avi Kivity 已提交
3851 3852
		goto twobyte_insn;

3853
	switch (c->b) {
3854
	case 0x06:		/* push es */
3855
		rc = emulate_push_sreg(ctxt, VCPU_SREG_ES);
3856 3857
		break;
	case 0x07:		/* pop es */
3858
		rc = emulate_pop_sreg(ctxt, VCPU_SREG_ES);
3859 3860
		break;
	case 0x0e:		/* push cs */
3861
		rc = emulate_push_sreg(ctxt, VCPU_SREG_CS);
3862 3863
		break;
	case 0x16:		/* push ss */
3864
		rc = emulate_push_sreg(ctxt, VCPU_SREG_SS);
3865 3866
		break;
	case 0x17:		/* pop ss */
3867
		rc = emulate_pop_sreg(ctxt, VCPU_SREG_SS);
3868 3869
		break;
	case 0x1e:		/* push ds */
3870
		rc = emulate_push_sreg(ctxt, VCPU_SREG_DS);
3871 3872
		break;
	case 0x1f:		/* pop ds */
3873
		rc = emulate_pop_sreg(ctxt, VCPU_SREG_DS);
3874
		break;
3875 3876 3877 3878 3879 3880
	case 0x40 ... 0x47: /* inc r16/r32 */
		emulate_1op("inc", c->dst, ctxt->eflags);
		break;
	case 0x48 ... 0x4f: /* dec r16/r32 */
		emulate_1op("dec", c->dst, ctxt->eflags);
		break;
A
Avi Kivity 已提交
3881
	case 0x63:		/* movsxd */
3882
		if (ctxt->mode != X86EMUL_MODE_PROT64)
A
Avi Kivity 已提交
3883
			goto cannot_emulate;
3884
		c->dst.val = (s32) c->src.val;
A
Avi Kivity 已提交
3885
		break;
3886 3887
	case 0x6c:		/* insb */
	case 0x6d:		/* insw/insd */
3888 3889
		c->src.val = c->regs[VCPU_REGS_RDX];
		goto do_io_in;
3890 3891
	case 0x6e:		/* outsb */
	case 0x6f:		/* outsw/outsd */
3892 3893
		c->dst.val = c->regs[VCPU_REGS_RDX];
		goto do_io_out;
3894
		break;
3895
	case 0x70 ... 0x7f: /* jcc (short) */
3896
		if (test_cc(c->b, ctxt->eflags))
3897
			jmp_rel(c, c->src.val);
3898
		break;
3899 3900
	case 0x8c:  /* mov r/m, sreg */
		if (c->modrm_reg > VCPU_SREG_GS) {
3901
			rc = emulate_ud(ctxt);
3902
			goto done;
3903
		}
3904
		c->dst.val = get_segment_selector(ctxt, c->modrm_reg);
3905
		break;
N
Nitin A Kamble 已提交
3906
	case 0x8d: /* lea r16/r32, m */
3907
		c->dst.val = c->src.addr.mem.ea;
N
Nitin A Kamble 已提交
3908
		break;
3909 3910 3911 3912
	case 0x8e: { /* mov seg, r/m16 */
		uint16_t sel;

		sel = c->src.val;
3913

3914 3915
		if (c->modrm_reg == VCPU_SREG_CS ||
		    c->modrm_reg > VCPU_SREG_GS) {
3916
			rc = emulate_ud(ctxt);
3917 3918 3919
			goto done;
		}

3920
		if (c->modrm_reg == VCPU_SREG_SS)
3921
			ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3922

3923
		rc = load_segment_descriptor(ctxt, sel, c->modrm_reg);
3924 3925 3926 3927

		c->dst.type = OP_NONE;  /* Disable writeback. */
		break;
	}
A
Avi Kivity 已提交
3928
	case 0x8f:		/* pop (sole member of Grp1a) */
3929
		rc = em_grp1a(ctxt);
A
Avi Kivity 已提交
3930
		break;
3931 3932
	case 0x90 ... 0x97: /* nop / xchg reg, rax */
		if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
3933
			break;
3934 3935
		rc = em_xchg(ctxt);
		break;
3936 3937 3938 3939 3940 3941 3942
	case 0x98: /* cbw/cwde/cdqe */
		switch (c->op_bytes) {
		case 2: c->dst.val = (s8)c->dst.val; break;
		case 4: c->dst.val = (s16)c->dst.val; break;
		case 8: c->dst.val = (s32)c->dst.val; break;
		}
		break;
3943
	case 0xc0 ... 0xc1:
3944
		rc = em_grp2(ctxt);
3945
		break;
3946
	case 0xc3: /* ret */
A
Avi Kivity 已提交
3947
		c->dst.type = OP_REG;
3948
		c->dst.addr.reg = &c->eip;
A
Avi Kivity 已提交
3949
		c->dst.bytes = c->op_bytes;
3950 3951
		rc = em_pop(ctxt);
		break;
3952
	case 0xc4:		/* les */
3953
		rc = emulate_load_segment(ctxt, VCPU_SREG_ES);
3954 3955
		break;
	case 0xc5:		/* lds */
3956
		rc = emulate_load_segment(ctxt, VCPU_SREG_DS);
3957
		break;
3958 3959 3960 3961 3962 3963
	case 0xcc:		/* int3 */
		irq = 3;
		goto do_interrupt;
	case 0xcd:		/* int n */
		irq = c->src.val;
	do_interrupt:
3964
		rc = emulate_int(ctxt, irq);
3965 3966 3967 3968 3969 3970 3971
		break;
	case 0xce:		/* into */
		if (ctxt->eflags & EFLG_OF) {
			irq = 4;
			goto do_interrupt;
		}
		break;
3972
	case 0xd0 ... 0xd1:	/* Grp2 */
3973
		rc = em_grp2(ctxt);
3974 3975 3976
		break;
	case 0xd2 ... 0xd3:	/* Grp2 */
		c->src.val = c->regs[VCPU_REGS_RCX];
3977
		rc = em_grp2(ctxt);
3978
		break;
3979 3980 3981 3982 3983 3984
	case 0xe0 ... 0xe2:	/* loop/loopz/loopnz */
		register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
		if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
		    (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
			jmp_rel(c, c->src.val);
		break;
3985 3986 3987 3988
	case 0xe3:	/* jcxz/jecxz/jrcxz */
		if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
			jmp_rel(c, c->src.val);
		break;
3989 3990
	case 0xe4: 	/* inb */
	case 0xe5: 	/* in */
3991
		goto do_io_in;
3992 3993
	case 0xe6: /* outb */
	case 0xe7: /* out */
3994
		goto do_io_out;
3995
	case 0xe8: /* call (near) */ {
3996
		long int rel = c->src.val;
3997
		c->src.val = (unsigned long) c->eip;
3998
		jmp_rel(c, rel);
3999
		rc = em_push(ctxt);
4000
		break;
4001 4002
	}
	case 0xe9: /* jmp rel */
4003
	case 0xeb: /* jmp rel short */
4004
		jmp_rel(c, c->src.val);
4005
		c->dst.type = OP_NONE; /* Disable writeback. */
4006
		break;
4007 4008
	case 0xec: /* in al,dx */
	case 0xed: /* in (e/r)ax,dx */
4009
	do_io_in:
4010
		if (!pio_in_emulated(ctxt, c->dst.bytes, c->src.val,
4011
				     &c->dst.val))
4012 4013
			goto done; /* IO is needed */
		break;
4014 4015
	case 0xee: /* out dx,al */
	case 0xef: /* out dx,(e/r)ax */
4016
	do_io_out:
4017 4018
		ops->pio_out_emulated(ctxt, c->src.bytes, c->dst.val,
				      &c->src.val, 1);
4019
		c->dst.type = OP_NONE;	/* Disable writeback. */
4020
		break;
4021
	case 0xf4:              /* hlt */
4022
		ctxt->ops->halt(ctxt);
4023
		break;
4024 4025 4026 4027
	case 0xf5:	/* cmc */
		/* complement carry flag from eflags reg */
		ctxt->eflags ^= EFLG_CF;
		break;
4028
	case 0xf6 ... 0xf7:	/* Grp3 */
4029
		rc = em_grp3(ctxt);
4030
		break;
4031 4032 4033
	case 0xf8: /* clc */
		ctxt->eflags &= ~EFLG_CF;
		break;
4034 4035 4036
	case 0xf9: /* stc */
		ctxt->eflags |= EFLG_CF;
		break;
4037
	case 0xfa: /* cli */
4038
		if (emulator_bad_iopl(ctxt)) {
4039
			rc = emulate_gp(ctxt, 0);
4040
			goto done;
4041
		} else
4042
			ctxt->eflags &= ~X86_EFLAGS_IF;
4043 4044
		break;
	case 0xfb: /* sti */
4045
		if (emulator_bad_iopl(ctxt)) {
4046
			rc = emulate_gp(ctxt, 0);
4047 4048
			goto done;
		} else {
4049
			ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
4050 4051
			ctxt->eflags |= X86_EFLAGS_IF;
		}
4052
		break;
4053 4054 4055 4056 4057 4058
	case 0xfc: /* cld */
		ctxt->eflags &= ~EFLG_DF;
		break;
	case 0xfd: /* std */
		ctxt->eflags |= EFLG_DF;
		break;
4059
	case 0xfe: /* Grp4 */
4060
		rc = em_grp45(ctxt);
4061
		break;
4062
	case 0xff: /* Grp5 */
4063 4064
		rc = em_grp45(ctxt);
		break;
4065 4066
	default:
		goto cannot_emulate;
A
Avi Kivity 已提交
4067
	}
4068

4069 4070 4071
	if (rc != X86EMUL_CONTINUE)
		goto done;

4072
writeback:
4073
	rc = writeback(ctxt);
4074
	if (rc != X86EMUL_CONTINUE)
4075 4076
		goto done;

4077 4078 4079 4080 4081 4082
	/*
	 * restore dst type in case the decoding will be reused
	 * (happens for string instruction )
	 */
	c->dst.type = saved_dst_type;

4083
	if ((c->d & SrcMask) == SrcSI)
4084
		string_addr_inc(ctxt, seg_override(ctxt, c),
4085
				VCPU_REGS_RSI, &c->src);
4086 4087

	if ((c->d & DstMask) == DstDI)
4088
		string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
4089
				&c->dst);
4090

4091
	if (c->rep_prefix && (c->d & String)) {
4092
		struct read_cache *r = &c->io_read;
4093
		register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
4094

4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106
		if (!string_insn_completed(ctxt)) {
			/*
			 * Re-enter guest when pio read ahead buffer is empty
			 * or, if it is not used, after each 1024 iteration.
			 */
			if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
			    (r->end == 0 || r->end != r->pos)) {
				/*
				 * Reset read cache. Usually happens before
				 * decode, but since instruction is restarted
				 * we have to do it here.
				 */
4107
				c->mem_read.end = 0;
4108 4109 4110
				return EMULATION_RESTART;
			}
			goto done; /* skip rip writeback */
4111
		}
4112
	}
4113 4114

	ctxt->eip = c->eip;
4115 4116

done:
4117 4118
	if (rc == X86EMUL_PROPAGATE_FAULT)
		ctxt->have_exception = true;
4119 4120 4121
	if (rc == X86EMUL_INTERCEPTED)
		return EMULATION_INTERCEPTED;

4122
	return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
A
Avi Kivity 已提交
4123 4124

twobyte_insn:
4125
	switch (c->b) {
4126
	case 0x09:		/* wbinvd */
4127
		(ctxt->ops->wbinvd)(ctxt);
4128 4129
		break;
	case 0x08:		/* invd */
4130 4131 4132 4133
	case 0x0d:		/* GrpP (prefetch) */
	case 0x18:		/* Grp16 (prefetch/nop) */
		break;
	case 0x20: /* mov cr, reg */
4134
		c->dst.val = ops->get_cr(ctxt, c->modrm_reg);
4135
		break;
A
Avi Kivity 已提交
4136
	case 0x21: /* mov from dr to reg */
4137
		ops->get_dr(ctxt, c->modrm_reg, &c->dst.val);
A
Avi Kivity 已提交
4138
		break;
4139
	case 0x22: /* mov reg, cr */
4140
		if (ops->set_cr(ctxt, c->modrm_reg, c->src.val)) {
4141
			emulate_gp(ctxt, 0);
4142
			rc = X86EMUL_PROPAGATE_FAULT;
4143 4144
			goto done;
		}
4145 4146
		c->dst.type = OP_NONE;
		break;
A
Avi Kivity 已提交
4147
	case 0x23: /* mov from reg to dr */
4148
		if (ops->set_dr(ctxt, c->modrm_reg, c->src.val &
4149
				((ctxt->mode == X86EMUL_MODE_PROT64) ?
4150
				 ~0ULL : ~0U)) < 0) {
4151
			/* #UD condition is already handled by the code above */
4152
			emulate_gp(ctxt, 0);
4153
			rc = X86EMUL_PROPAGATE_FAULT;
4154 4155 4156
			goto done;
		}

4157
		c->dst.type = OP_NONE;	/* no writeback */
A
Avi Kivity 已提交
4158
		break;
4159 4160 4161 4162
	case 0x30:
		/* wrmsr */
		msr_data = (u32)c->regs[VCPU_REGS_RAX]
			| ((u64)c->regs[VCPU_REGS_RDX] << 32);
4163
		if (ops->set_msr(ctxt, c->regs[VCPU_REGS_RCX], msr_data)) {
4164
			emulate_gp(ctxt, 0);
4165
			rc = X86EMUL_PROPAGATE_FAULT;
4166
			goto done;
4167 4168 4169 4170 4171
		}
		rc = X86EMUL_CONTINUE;
		break;
	case 0x32:
		/* rdmsr */
4172
		if (ops->get_msr(ctxt, c->regs[VCPU_REGS_RCX], &msr_data)) {
4173
			emulate_gp(ctxt, 0);
4174
			rc = X86EMUL_PROPAGATE_FAULT;
4175
			goto done;
4176 4177 4178 4179 4180 4181
		} else {
			c->regs[VCPU_REGS_RAX] = (u32)msr_data;
			c->regs[VCPU_REGS_RDX] = msr_data >> 32;
		}
		rc = X86EMUL_CONTINUE;
		break;
A
Avi Kivity 已提交
4182
	case 0x40 ... 0x4f:	/* cmov */
4183
		c->dst.val = c->dst.orig_val = c->src.val;
4184 4185
		if (!test_cc(c->b, ctxt->eflags))
			c->dst.type = OP_NONE; /* no writeback */
A
Avi Kivity 已提交
4186
		break;
4187
	case 0x80 ... 0x8f: /* jnz rel, etc*/
4188
		if (test_cc(c->b, ctxt->eflags))
4189
			jmp_rel(c, c->src.val);
4190
		break;
4191 4192 4193
	case 0x90 ... 0x9f:     /* setcc r/m8 */
		c->dst.val = test_cc(c->b, ctxt->eflags);
		break;
4194
	case 0xa0:	  /* push fs */
4195
		rc = emulate_push_sreg(ctxt, VCPU_SREG_FS);
4196 4197
		break;
	case 0xa1:	 /* pop fs */
4198
		rc = emulate_pop_sreg(ctxt, VCPU_SREG_FS);
4199
		break;
4200 4201
	case 0xa3:
	      bt:		/* bt */
Q
Qing He 已提交
4202
		c->dst.type = OP_NONE;
4203 4204
		/* only subword offset */
		c->src.val &= (c->dst.bytes << 3) - 1;
4205
		emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
4206
		break;
4207 4208 4209 4210
	case 0xa4: /* shld imm8, r, r/m */
	case 0xa5: /* shld cl, r, r/m */
		emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
		break;
4211
	case 0xa8:	/* push gs */
4212
		rc = emulate_push_sreg(ctxt, VCPU_SREG_GS);
4213 4214
		break;
	case 0xa9:	/* pop gs */
4215
		rc = emulate_pop_sreg(ctxt, VCPU_SREG_GS);
4216
		break;
4217 4218
	case 0xab:
	      bts:		/* bts */
4219
		emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
4220
		break;
4221 4222 4223 4224
	case 0xac: /* shrd imm8, r, r/m */
	case 0xad: /* shrd cl, r, r/m */
		emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
		break;
4225 4226
	case 0xae:              /* clflush */
		break;
A
Avi Kivity 已提交
4227 4228 4229 4230 4231
	case 0xb0 ... 0xb1:	/* cmpxchg */
		/*
		 * Save real source value, then compare EAX against
		 * destination.
		 */
4232 4233
		c->src.orig_val = c->src.val;
		c->src.val = c->regs[VCPU_REGS_RAX];
4234 4235
		emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
		if (ctxt->eflags & EFLG_ZF) {
A
Avi Kivity 已提交
4236
			/* Success: write back to memory. */
4237
			c->dst.val = c->src.orig_val;
A
Avi Kivity 已提交
4238 4239
		} else {
			/* Failure: write the value we saw to EAX. */
4240
			c->dst.type = OP_REG;
4241
			c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
A
Avi Kivity 已提交
4242 4243
		}
		break;
4244
	case 0xb2:		/* lss */
4245
		rc = emulate_load_segment(ctxt, VCPU_SREG_SS);
4246
		break;
A
Avi Kivity 已提交
4247 4248
	case 0xb3:
	      btr:		/* btr */
4249
		emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
A
Avi Kivity 已提交
4250
		break;
4251
	case 0xb4:		/* lfs */
4252
		rc = emulate_load_segment(ctxt, VCPU_SREG_FS);
4253 4254
		break;
	case 0xb5:		/* lgs */
4255
		rc = emulate_load_segment(ctxt, VCPU_SREG_GS);
4256
		break;
A
Avi Kivity 已提交
4257
	case 0xb6 ... 0xb7:	/* movzx */
4258 4259 4260
		c->dst.bytes = c->op_bytes;
		c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
						       : (u16) c->src.val;
A
Avi Kivity 已提交
4261 4262
		break;
	case 0xba:		/* Grp8 */
4263
		switch (c->modrm_reg & 3) {
A
Avi Kivity 已提交
4264 4265 4266 4267 4268 4269 4270 4271 4272 4273
		case 0:
			goto bt;
		case 1:
			goto bts;
		case 2:
			goto btr;
		case 3:
			goto btc;
		}
		break;
4274 4275
	case 0xbb:
	      btc:		/* btc */
4276
		emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
4277
		break;
4278 4279 4280 4281 4282 4283 4284 4285 4286 4287 4288 4289 4290 4291 4292 4293 4294 4295 4296 4297 4298 4299 4300 4301
	case 0xbc: {		/* bsf */
		u8 zf;
		__asm__ ("bsf %2, %0; setz %1"
			 : "=r"(c->dst.val), "=q"(zf)
			 : "r"(c->src.val));
		ctxt->eflags &= ~X86_EFLAGS_ZF;
		if (zf) {
			ctxt->eflags |= X86_EFLAGS_ZF;
			c->dst.type = OP_NONE;	/* Disable writeback. */
		}
		break;
	}
	case 0xbd: {		/* bsr */
		u8 zf;
		__asm__ ("bsr %2, %0; setz %1"
			 : "=r"(c->dst.val), "=q"(zf)
			 : "r"(c->src.val));
		ctxt->eflags &= ~X86_EFLAGS_ZF;
		if (zf) {
			ctxt->eflags |= X86_EFLAGS_ZF;
			c->dst.type = OP_NONE;	/* Disable writeback. */
		}
		break;
	}
A
Avi Kivity 已提交
4302
	case 0xbe ... 0xbf:	/* movsx */
4303 4304 4305
		c->dst.bytes = c->op_bytes;
		c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
							(s16) c->src.val;
A
Avi Kivity 已提交
4306
		break;
4307 4308 4309 4310 4311 4312
	case 0xc0 ... 0xc1:	/* xadd */
		emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
		/* Write back the register source. */
		c->src.val = c->dst.orig_val;
		write_register_operand(&c->src);
		break;
4313
	case 0xc3:		/* movnti */
4314 4315 4316
		c->dst.bytes = c->op_bytes;
		c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
							(u64) c->src.val;
4317
		break;
A
Avi Kivity 已提交
4318
	case 0xc7:		/* Grp9 (cmpxchg8b) */
4319
		rc = em_grp9(ctxt);
4320
		break;
4321 4322
	default:
		goto cannot_emulate;
A
Avi Kivity 已提交
4323
	}
4324 4325 4326 4327

	if (rc != X86EMUL_CONTINUE)
		goto done;

A
Avi Kivity 已提交
4328 4329 4330
	goto writeback;

cannot_emulate:
4331
	return EMULATION_FAILED;
A
Avi Kivity 已提交
4332
}