emulate.c 125.3 KB
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/******************************************************************************
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 * emulate.c
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 *
 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
 *
 * Copyright (c) 2005 Keir Fraser
 *
 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
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 * privileged instructions:
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 *
 * Copyright (C) 2006 Qumranet
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 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
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 *
 *   Avi Kivity <avi@qumranet.com>
 *   Yaniv Kamay <yaniv@qumranet.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
 */

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#include <linux/kvm_host.h>
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#include "kvm_cache_regs.h"
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#include <linux/module.h>
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#include <asm/kvm_emulate.h>
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#include <linux/stringify.h>
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#include "x86.h"
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#include "tss.h"
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/*
 * Operand types
 */
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#define OpNone             0ull
#define OpImplicit         1ull  /* No generic decode */
#define OpReg              2ull  /* Register */
#define OpMem              3ull  /* Memory */
#define OpAcc              4ull  /* Accumulator: AL/AX/EAX/RAX */
#define OpDI               5ull  /* ES:DI/EDI/RDI */
#define OpMem64            6ull  /* Memory, 64-bit */
#define OpImmUByte         7ull  /* Zero-extended 8-bit immediate */
#define OpDX               8ull  /* DX register */
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#define OpCL               9ull  /* CL register (for shifts) */
#define OpImmByte         10ull  /* 8-bit sign extended immediate */
#define OpOne             11ull  /* Implied 1 */
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#define OpImm             12ull  /* Sign extended up to 32-bit immediate */
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#define OpMem16           13ull  /* Memory operand (16-bit). */
#define OpMem32           14ull  /* Memory operand (32-bit). */
#define OpImmU            15ull  /* Immediate operand, zero extended */
#define OpSI              16ull  /* SI/ESI/RSI */
#define OpImmFAddr        17ull  /* Immediate far address */
#define OpMemFAddr        18ull  /* Far address in memory */
#define OpImmU16          19ull  /* Immediate operand, 16 bits, zero extended */
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#define OpES              20ull  /* ES */
#define OpCS              21ull  /* CS */
#define OpSS              22ull  /* SS */
#define OpDS              23ull  /* DS */
#define OpFS              24ull  /* FS */
#define OpGS              25ull  /* GS */
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#define OpMem8            26ull  /* 8-bit zero extended memory operand */
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#define OpImm64           27ull  /* Sign extended 16/32/64-bit immediate */
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#define OpXLat            28ull  /* memory at BX/EBX/RBX + zero-extended AL */
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#define OpAccLo           29ull  /* Low part of extended acc (AX/AX/EAX/RAX) */
#define OpAccHi           30ull  /* High part of extended acc (-/DX/EDX/RDX) */
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#define OpBits             5  /* Width of operand field */
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#define OpMask             ((1ull << OpBits) - 1)
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/*
 * Opcode effective-address decode tables.
 * Note that we only emulate instructions that have at least one memory
 * operand (excluding implicit stack references). We assume that stack
 * references and instruction fetches will never occur in special memory
 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
 * not be handled.
 */

/* Operand sizes: 8-bit operands or specified/overridden size. */
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#define ByteOp      (1<<0)	/* 8-bit operands. */
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/* Destination operand type. */
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#define DstShift    1
#define ImplicitOps (OpImplicit << DstShift)
#define DstReg      (OpReg << DstShift)
#define DstMem      (OpMem << DstShift)
#define DstAcc      (OpAcc << DstShift)
#define DstDI       (OpDI << DstShift)
#define DstMem64    (OpMem64 << DstShift)
#define DstImmUByte (OpImmUByte << DstShift)
#define DstDX       (OpDX << DstShift)
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#define DstAccLo    (OpAccLo << DstShift)
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#define DstMask     (OpMask << DstShift)
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/* Source operand type. */
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#define SrcShift    6
#define SrcNone     (OpNone << SrcShift)
#define SrcReg      (OpReg << SrcShift)
#define SrcMem      (OpMem << SrcShift)
#define SrcMem16    (OpMem16 << SrcShift)
#define SrcMem32    (OpMem32 << SrcShift)
#define SrcImm      (OpImm << SrcShift)
#define SrcImmByte  (OpImmByte << SrcShift)
#define SrcOne      (OpOne << SrcShift)
#define SrcImmUByte (OpImmUByte << SrcShift)
#define SrcImmU     (OpImmU << SrcShift)
#define SrcSI       (OpSI << SrcShift)
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#define SrcXLat     (OpXLat << SrcShift)
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#define SrcImmFAddr (OpImmFAddr << SrcShift)
#define SrcMemFAddr (OpMemFAddr << SrcShift)
#define SrcAcc      (OpAcc << SrcShift)
#define SrcImmU16   (OpImmU16 << SrcShift)
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#define SrcImm64    (OpImm64 << SrcShift)
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#define SrcDX       (OpDX << SrcShift)
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#define SrcMem8     (OpMem8 << SrcShift)
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#define SrcAccHi    (OpAccHi << SrcShift)
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#define SrcMask     (OpMask << SrcShift)
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#define BitOp       (1<<11)
#define MemAbs      (1<<12)      /* Memory operand is absolute displacement */
#define String      (1<<13)     /* String instruction (rep capable) */
#define Stack       (1<<14)     /* Stack instruction (push/pop) */
#define GroupMask   (7<<15)     /* Opcode uses one of the group mechanisms */
#define Group       (1<<15)     /* Bits 3:5 of modrm byte extend opcode */
#define GroupDual   (2<<15)     /* Alternate decoding of mod == 3 */
#define Prefix      (3<<15)     /* Instruction varies with 66/f2/f3 prefix */
#define RMExt       (4<<15)     /* Opcode extension in ModRM r/m if mod == 3 */
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#define Escape      (5<<15)     /* Escape to coprocessor instruction */
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#define Sse         (1<<18)     /* SSE Vector instruction */
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/* Generic ModRM decode. */
#define ModRM       (1<<19)
/* Destination is only written; never read. */
#define Mov         (1<<20)
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/* Misc flags */
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#define Prot        (1<<21) /* instruction generates #UD if not in prot-mode */
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#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
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#define NoAccess    (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
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#define Op3264      (1<<24) /* Operand is 64b in long mode, 32b otherwise */
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#define Undefined   (1<<25) /* No Such Instruction */
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#define Lock        (1<<26) /* lock prefix is allowed for the instruction */
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#define Priv        (1<<27) /* instruction generates #GP if current CPL != 0 */
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#define No64	    (1<<28)
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#define PageTable   (1 << 29)   /* instruction used to write page table */
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#define NotImpl     (1 << 30)   /* instruction is not implemented */
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/* Source 2 operand type */
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#define Src2Shift   (31)
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#define Src2None    (OpNone << Src2Shift)
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#define Src2Mem     (OpMem << Src2Shift)
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#define Src2CL      (OpCL << Src2Shift)
#define Src2ImmByte (OpImmByte << Src2Shift)
#define Src2One     (OpOne << Src2Shift)
#define Src2Imm     (OpImm << Src2Shift)
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#define Src2ES      (OpES << Src2Shift)
#define Src2CS      (OpCS << Src2Shift)
#define Src2SS      (OpSS << Src2Shift)
#define Src2DS      (OpDS << Src2Shift)
#define Src2FS      (OpFS << Src2Shift)
#define Src2GS      (OpGS << Src2Shift)
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#define Src2Mask    (OpMask << Src2Shift)
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#define Mmx         ((u64)1 << 40)  /* MMX Vector instruction */
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#define Aligned     ((u64)1 << 41)  /* Explicitly aligned (e.g. MOVDQA) */
#define Unaligned   ((u64)1 << 42)  /* Explicitly unaligned (e.g. MOVDQU) */
#define Avx         ((u64)1 << 43)  /* Advanced Vector Extensions */
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#define Fastop      ((u64)1 << 44)  /* Use opcode::u.fastop */
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#define NoWrite     ((u64)1 << 45)  /* No writeback */
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#define SrcWrite    ((u64)1 << 46)  /* Write back src operand */
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#define NoMod	    ((u64)1 << 47)  /* Mod field is ignored */
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#define Intercept   ((u64)1 << 48)  /* Has valid intercept field */
#define CheckPerm   ((u64)1 << 49)  /* Has valid check_perm field */
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#define DstXacc     (DstAccLo | SrcAccHi | SrcWrite)
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#define X2(x...) x, x
#define X3(x...) X2(x), x
#define X4(x...) X2(x), X2(x)
#define X5(x...) X4(x), x
#define X6(x...) X4(x), X2(x)
#define X7(x...) X4(x), X3(x)
#define X8(x...) X4(x), X4(x)
#define X16(x...) X8(x), X8(x)
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#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
#define FASTOP_SIZE 8

/*
 * fastop functions have a special calling convention:
 *
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 * dst:    rax        (in/out)
 * src:    rdx        (in/out)
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 * src2:   rcx        (in)
 * flags:  rflags     (in/out)
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 * ex:     rsi        (in:fastop pointer, out:zero if exception)
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 *
 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
 * different operand sizes can be reached by calculation, rather than a jump
 * table (which would be bigger than the code).
 *
 * fastop functions are declared as taking a never-defined fastop parameter,
 * so they can't be called from C directly.
 */

struct fastop;

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struct opcode {
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	u64 flags : 56;
	u64 intercept : 8;
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	union {
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		int (*execute)(struct x86_emulate_ctxt *ctxt);
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		const struct opcode *group;
		const struct group_dual *gdual;
		const struct gprefix *gprefix;
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		const struct escape *esc;
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		void (*fastop)(struct fastop *fake);
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	} u;
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	int (*check_perm)(struct x86_emulate_ctxt *ctxt);
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};

struct group_dual {
	struct opcode mod012[8];
	struct opcode mod3[8];
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};

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struct gprefix {
	struct opcode pfx_no;
	struct opcode pfx_66;
	struct opcode pfx_f2;
	struct opcode pfx_f3;
};

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struct escape {
	struct opcode op[8];
	struct opcode high[64];
};

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/* EFLAGS bit definitions. */
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#define EFLG_ID (1<<21)
#define EFLG_VIP (1<<20)
#define EFLG_VIF (1<<19)
#define EFLG_AC (1<<18)
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#define EFLG_VM (1<<17)
#define EFLG_RF (1<<16)
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#define EFLG_IOPL (3<<12)
#define EFLG_NT (1<<14)
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#define EFLG_OF (1<<11)
#define EFLG_DF (1<<10)
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#define EFLG_IF (1<<9)
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#define EFLG_TF (1<<8)
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#define EFLG_SF (1<<7)
#define EFLG_ZF (1<<6)
#define EFLG_AF (1<<4)
#define EFLG_PF (1<<2)
#define EFLG_CF (1<<0)

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#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
#define EFLG_RESERVED_ONE_MASK 2

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static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
{
	if (!(ctxt->regs_valid & (1 << nr))) {
		ctxt->regs_valid |= 1 << nr;
		ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
	}
	return ctxt->_regs[nr];
}

static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
{
	ctxt->regs_valid |= 1 << nr;
	ctxt->regs_dirty |= 1 << nr;
	return &ctxt->_regs[nr];
}

static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
{
	reg_read(ctxt, nr);
	return reg_write(ctxt, nr);
}

static void writeback_registers(struct x86_emulate_ctxt *ctxt)
{
	unsigned reg;

	for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
		ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
}

static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
{
	ctxt->regs_dirty = 0;
	ctxt->regs_valid = 0;
}

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/*
 * These EFLAGS bits are restored from saved value during emulation, and
 * any changes are written back to the saved value after emulation.
 */
#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)

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#ifdef CONFIG_X86_64
#define ON64(x) x
#else
#define ON64(x)
#endif

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static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));

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#define FOP_ALIGN ".align " __stringify(FASTOP_SIZE) " \n\t"
#define FOP_RET   "ret \n\t"

#define FOP_START(op) \
	extern void em_##op(struct fastop *fake); \
	asm(".pushsection .text, \"ax\" \n\t" \
	    ".global em_" #op " \n\t" \
            FOP_ALIGN \
	    "em_" #op ": \n\t"

#define FOP_END \
	    ".popsection")

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#define FOPNOP() FOP_ALIGN FOP_RET

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#define FOP1E(op,  dst) \
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	FOP_ALIGN "10: " #op " %" #dst " \n\t" FOP_RET

#define FOP1EEX(op,  dst) \
	FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
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#define FASTOP1(op) \
	FOP_START(op) \
	FOP1E(op##b, al) \
	FOP1E(op##w, ax) \
	FOP1E(op##l, eax) \
	ON64(FOP1E(op##q, rax))	\
	FOP_END

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/* 1-operand, using src2 (for MUL/DIV r/m) */
#define FASTOP1SRC2(op, name) \
	FOP_START(name) \
	FOP1E(op, cl) \
	FOP1E(op, cx) \
	FOP1E(op, ecx) \
	ON64(FOP1E(op, rcx)) \
	FOP_END

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/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
#define FASTOP1SRC2EX(op, name) \
	FOP_START(name) \
	FOP1EEX(op, cl) \
	FOP1EEX(op, cx) \
	FOP1EEX(op, ecx) \
	ON64(FOP1EEX(op, rcx)) \
	FOP_END

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#define FOP2E(op,  dst, src)	   \
	FOP_ALIGN #op " %" #src ", %" #dst " \n\t" FOP_RET

#define FASTOP2(op) \
	FOP_START(op) \
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	FOP2E(op##b, al, dl) \
	FOP2E(op##w, ax, dx) \
	FOP2E(op##l, eax, edx) \
	ON64(FOP2E(op##q, rax, rdx)) \
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	FOP_END

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/* 2 operand, word only */
#define FASTOP2W(op) \
	FOP_START(op) \
	FOPNOP() \
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	FOP2E(op##w, ax, dx) \
	FOP2E(op##l, eax, edx) \
	ON64(FOP2E(op##q, rax, rdx)) \
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	FOP_END

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/* 2 operand, src is CL */
#define FASTOP2CL(op) \
	FOP_START(op) \
	FOP2E(op##b, al, cl) \
	FOP2E(op##w, ax, cl) \
	FOP2E(op##l, eax, cl) \
	ON64(FOP2E(op##q, rax, cl)) \
	FOP_END

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#define FOP3E(op,  dst, src, src2) \
	FOP_ALIGN #op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET

/* 3-operand, word-only, src2=cl */
#define FASTOP3WCL(op) \
	FOP_START(op) \
	FOPNOP() \
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	FOP3E(op##w, ax, dx, cl) \
	FOP3E(op##l, eax, edx, cl) \
	ON64(FOP3E(op##q, rax, rdx, cl)) \
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	FOP_END

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/* Special case for SETcc - 1 instruction per cc */
#define FOP_SETCC(op) ".align 4; " #op " %al; ret \n\t"

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asm(".global kvm_fastop_exception \n"
    "kvm_fastop_exception: xor %esi, %esi; ret");

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FOP_START(setcc)
FOP_SETCC(seto)
FOP_SETCC(setno)
FOP_SETCC(setc)
FOP_SETCC(setnc)
FOP_SETCC(setz)
FOP_SETCC(setnz)
FOP_SETCC(setbe)
FOP_SETCC(setnbe)
FOP_SETCC(sets)
FOP_SETCC(setns)
FOP_SETCC(setp)
FOP_SETCC(setnp)
FOP_SETCC(setl)
FOP_SETCC(setnl)
FOP_SETCC(setle)
FOP_SETCC(setnle)
FOP_END;

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FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
FOP_END;

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static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
				    enum x86_intercept intercept,
				    enum x86_intercept_stage stage)
{
	struct x86_instruction_info info = {
		.intercept  = intercept,
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		.rep_prefix = ctxt->rep_prefix,
		.modrm_mod  = ctxt->modrm_mod,
		.modrm_reg  = ctxt->modrm_reg,
		.modrm_rm   = ctxt->modrm_rm,
		.src_val    = ctxt->src.val64,
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		.dst_val    = ctxt->dst.val64,
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		.src_bytes  = ctxt->src.bytes,
		.dst_bytes  = ctxt->dst.bytes,
		.ad_bytes   = ctxt->ad_bytes,
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		.next_rip   = ctxt->eip,
	};

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	return ctxt->ops->intercept(ctxt, &info, stage);
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}

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static void assign_masked(ulong *dest, ulong src, ulong mask)
{
	*dest = (*dest & ~mask) | (src & mask);
}

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static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
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{
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	return (1UL << (ctxt->ad_bytes << 3)) - 1;
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}

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static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
{
	u16 sel;
	struct desc_struct ss;

	if (ctxt->mode == X86EMUL_MODE_PROT64)
		return ~0UL;
	ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
	return ~0U >> ((ss.d ^ 1) * 16);  /* d=0: 0xffff; d=1: 0xffffffff */
}

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static int stack_size(struct x86_emulate_ctxt *ctxt)
{
	return (__fls(stack_mask(ctxt)) + 1) >> 3;
}

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/* Access/update address held in a register, based on addressing mode. */
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static inline unsigned long
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address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
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{
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	if (ctxt->ad_bytes == sizeof(unsigned long))
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		return reg;
	else
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		return reg & ad_mask(ctxt);
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}

static inline unsigned long
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register_address(struct x86_emulate_ctxt *ctxt, unsigned long reg)
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{
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	return address_mask(ctxt, reg);
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}

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static void masked_increment(ulong *reg, ulong mask, int inc)
{
	assign_masked(reg, *reg + inc, mask);
}

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static inline void
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register_address_increment(struct x86_emulate_ctxt *ctxt, unsigned long *reg, int inc)
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{
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	ulong mask;

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	if (ctxt->ad_bytes == sizeof(unsigned long))
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		mask = ~0UL;
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	else
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		mask = ad_mask(ctxt);
	masked_increment(reg, mask, inc);
}

static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
{
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	masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
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}
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static inline void jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
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{
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	register_address_increment(ctxt, &ctxt->_eip, rel);
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}
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static u32 desc_limit_scaled(struct desc_struct *desc)
{
	u32 limit = get_desc_limit(desc);

	return desc->g ? (limit << 12) | 0xfff : limit;
}

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static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
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{
	if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
		return 0;

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	return ctxt->ops->get_cached_segment_base(ctxt, seg);
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}

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static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
			     u32 error, bool valid)
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{
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	ctxt->exception.vector = vec;
	ctxt->exception.error_code = error;
	ctxt->exception.error_code_valid = valid;
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	return X86EMUL_PROPAGATE_FAULT;
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}

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static int emulate_db(struct x86_emulate_ctxt *ctxt)
{
	return emulate_exception(ctxt, DB_VECTOR, 0, false);
}

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static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
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{
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	return emulate_exception(ctxt, GP_VECTOR, err, true);
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}

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static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
{
	return emulate_exception(ctxt, SS_VECTOR, err, true);
}

549
static int emulate_ud(struct x86_emulate_ctxt *ctxt)
550
{
551
	return emulate_exception(ctxt, UD_VECTOR, 0, false);
552 553
}

554
static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
555
{
556
	return emulate_exception(ctxt, TS_VECTOR, err, true);
557 558
}

559 560
static int emulate_de(struct x86_emulate_ctxt *ctxt)
{
561
	return emulate_exception(ctxt, DE_VECTOR, 0, false);
562 563
}

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static int emulate_nm(struct x86_emulate_ctxt *ctxt)
{
	return emulate_exception(ctxt, NM_VECTOR, 0, false);
}

569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588
static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
{
	u16 selector;
	struct desc_struct desc;

	ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
	return selector;
}

static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
				 unsigned seg)
{
	u16 dummy;
	u32 base3;
	struct desc_struct desc;

	ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
	ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
}

589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611
/*
 * x86 defines three classes of vector instructions: explicitly
 * aligned, explicitly unaligned, and the rest, which change behaviour
 * depending on whether they're AVX encoded or not.
 *
 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
 * subject to the same check.
 */
static bool insn_aligned(struct x86_emulate_ctxt *ctxt, unsigned size)
{
	if (likely(size < 16))
		return false;

	if (ctxt->d & Aligned)
		return true;
	else if (ctxt->d & Unaligned)
		return false;
	else if (ctxt->d & Avx)
		return false;
	else
		return true;
}

612
static int __linearize(struct x86_emulate_ctxt *ctxt,
613
		     struct segmented_address addr,
614
		     unsigned size, bool write, bool fetch,
615 616
		     ulong *linear)
{
617 618
	struct desc_struct desc;
	bool usable;
619
	ulong la;
620
	u32 lim;
621
	u16 sel;
622
	unsigned cpl;
623

624
	la = seg_base(ctxt, addr.seg) + addr.ea;
625 626 627 628 629 630
	switch (ctxt->mode) {
	case X86EMUL_MODE_PROT64:
		if (((signed long)la << 16) >> 16 != la)
			return emulate_gp(ctxt, 0);
		break;
	default:
631 632
		usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
						addr.seg);
633 634
		if (!usable)
			goto bad;
635 636 637
		/* code segment in protected mode or read-only data segment */
		if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
					|| !(desc.type & 2)) && write)
638 639
			goto bad;
		/* unreadable code segment */
640
		if (!fetch && (desc.type & 8) && !(desc.type & 2))
641 642 643 644 645 646 647
			goto bad;
		lim = desc_limit_scaled(&desc);
		if ((desc.type & 8) || !(desc.type & 4)) {
			/* expand-up segment */
			if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
				goto bad;
		} else {
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648
			/* expand-down segment */
649 650 651 652 653 654
			if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
				goto bad;
			lim = desc.d ? 0xffffffff : 0xffff;
			if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
				goto bad;
		}
655
		cpl = ctxt->ops->cpl(ctxt);
656 657 658 659 660 661 662 663 664 665 666 667 668 669 670
		if (!(desc.type & 8)) {
			/* data segment */
			if (cpl > desc.dpl)
				goto bad;
		} else if ((desc.type & 8) && !(desc.type & 4)) {
			/* nonconforming code segment */
			if (cpl != desc.dpl)
				goto bad;
		} else if ((desc.type & 8) && (desc.type & 4)) {
			/* conforming code segment */
			if (cpl < desc.dpl)
				goto bad;
		}
		break;
	}
671
	if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : ctxt->ad_bytes != 8)
672
		la &= (u32)-1;
673 674
	if (insn_aligned(ctxt, size) && ((la & (size - 1)) != 0))
		return emulate_gp(ctxt, 0);
675 676
	*linear = la;
	return X86EMUL_CONTINUE;
677 678
bad:
	if (addr.seg == VCPU_SREG_SS)
679
		return emulate_ss(ctxt, sel);
680
	else
681
		return emulate_gp(ctxt, sel);
682 683
}

684 685 686 687 688 689 690 691 692
static int linearize(struct x86_emulate_ctxt *ctxt,
		     struct segmented_address addr,
		     unsigned size, bool write,
		     ulong *linear)
{
	return __linearize(ctxt, addr, size, write, false, linear);
}


693 694 695 696 697
static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
			      struct segmented_address addr,
			      void *data,
			      unsigned size)
{
698 699 700
	int rc;
	ulong linear;

701
	rc = linearize(ctxt, addr, size, false, &linear);
702 703
	if (rc != X86EMUL_CONTINUE)
		return rc;
704
	return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
705 706
}

707
/*
708
 * Prefetch the remaining bytes of the instruction without crossing page
709 710
 * boundary if they are not in fetch_cache yet.
 */
711
static int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
712
{
713
	struct fetch_cache *fc = &ctxt->fetch;
714
	int rc;
715
	int size, cur_size;
716 717 718 719 720 721 722
	unsigned long linear;

	struct segmented_address addr = { .seg = VCPU_SREG_CS,
					  .ea  = fc->end };
	cur_size = fc->end - fc->start;
	size = min(15UL - cur_size,
		   PAGE_SIZE - offset_in_page(fc->end));
723 724 725 726 727 728 729 730

	/*
	 * One instruction can only straddle two pages,
	 * and one has been loaded at the beginning of
	 * x86_decode_insn.  So, if not enough bytes
	 * still, we must have hit the 15-byte boundary.
	 */
	if (unlikely(size < op_size))
731 732 733 734 735 736 737 738 739
		return X86EMUL_UNHANDLEABLE;
	rc = __linearize(ctxt, addr, size, false, true, &linear);
	if (unlikely(rc != X86EMUL_CONTINUE))
		return rc;
	rc = ctxt->ops->fetch(ctxt, linear, fc->data + cur_size,
			      size, &ctxt->exception);
	if (unlikely(rc != X86EMUL_CONTINUE))
		return rc;
	fc->end += size;
740
	return X86EMUL_CONTINUE;
741 742 743
}

static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
744
			 void *__dest, unsigned size)
745
{
746 747 748
	struct fetch_cache *fc = &ctxt->fetch;
	u8 *dest = __dest;
	u8 *src = &fc->data[ctxt->_eip - fc->start];
749

750 751 752 753 754 755 756
	/* We have to be careful about overflow! */
	if (unlikely(ctxt->_eip > fc->end - size)) {
		int rc = do_insn_fetch_bytes(ctxt, size);
		if (rc != X86EMUL_CONTINUE)
			return rc;
	}

757
	while (size--) {
758 759 760
		*dest++ = *src++;
		ctxt->_eip++;
		continue;
761
	}
762
	return X86EMUL_CONTINUE;
763 764
}

765
/* Fetch next part of the instruction being emulated. */
766
#define insn_fetch(_type, _ctxt)					\
767
({	unsigned long _x;						\
768
	rc = do_insn_fetch(_ctxt, &_x, sizeof(_type));			\
769 770 771 772 773
	if (rc != X86EMUL_CONTINUE)					\
		goto done;						\
	(_type)_x;							\
})

774 775
#define insn_fetch_arr(_arr, _size, _ctxt)				\
({	rc = do_insn_fetch(_ctxt, _arr, (_size));			\
776 777 778 779
	if (rc != X86EMUL_CONTINUE)					\
		goto done;						\
})

780 781 782 783 784
/*
 * Given the 'reg' portion of a ModRM byte, and a register block, return a
 * pointer into the block that addresses the relevant register.
 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
 */
785
static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
786
			     int byteop)
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{
	void *p;
789
	int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
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	if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
792 793 794
		p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
	else
		p = reg_rmw(ctxt, modrm_reg);
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	return p;
}

static int read_descriptor(struct x86_emulate_ctxt *ctxt,
799
			   struct segmented_address addr,
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			   u16 *size, unsigned long *address, int op_bytes)
{
	int rc;

	if (op_bytes == 2)
		op_bytes = 3;
	*address = 0;
807
	rc = segmented_read_std(ctxt, addr, size, 2);
808
	if (rc != X86EMUL_CONTINUE)
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		return rc;
810
	addr.ea += 2;
811
	rc = segmented_read_std(ctxt, addr, address, op_bytes);
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	return rc;
}

815 816 817 818 819 820 821 822 823 824
FASTOP2(add);
FASTOP2(or);
FASTOP2(adc);
FASTOP2(sbb);
FASTOP2(and);
FASTOP2(sub);
FASTOP2(xor);
FASTOP2(cmp);
FASTOP2(test);

825 826
FASTOP1SRC2(mul, mul_ex);
FASTOP1SRC2(imul, imul_ex);
827 828
FASTOP1SRC2EX(div, div_ex);
FASTOP1SRC2EX(idiv, idiv_ex);
829

830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854
FASTOP3WCL(shld);
FASTOP3WCL(shrd);

FASTOP2W(imul);

FASTOP1(not);
FASTOP1(neg);
FASTOP1(inc);
FASTOP1(dec);

FASTOP2CL(rol);
FASTOP2CL(ror);
FASTOP2CL(rcl);
FASTOP2CL(rcr);
FASTOP2CL(shl);
FASTOP2CL(shr);
FASTOP2CL(sar);

FASTOP2W(bsf);
FASTOP2W(bsr);
FASTOP2W(bt);
FASTOP2W(bts);
FASTOP2W(btr);
FASTOP2W(btc);

855 856
FASTOP2(xadd);

857
static u8 test_cc(unsigned int condition, unsigned long flags)
858
{
859 860
	u8 rc;
	void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
861

862
	flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
863
	asm("push %[flags]; popf; call *%[fastop]"
864 865
	    : "=a"(rc) : [fastop]"r"(fop), [flags]"r"(flags));
	return rc;
866 867
}

868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885
static void fetch_register_operand(struct operand *op)
{
	switch (op->bytes) {
	case 1:
		op->val = *(u8 *)op->addr.reg;
		break;
	case 2:
		op->val = *(u16 *)op->addr.reg;
		break;
	case 4:
		op->val = *(u32 *)op->addr.reg;
		break;
	case 8:
		op->val = *(u64 *)op->addr.reg;
		break;
	}
}

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static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
{
	ctxt->ops->get_fpu(ctxt);
	switch (reg) {
890 891 892 893 894 895 896 897
	case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
	case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
	case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
	case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
	case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
	case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
	case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
	case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
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#ifdef CONFIG_X86_64
899 900 901 902 903 904 905 906
	case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
	case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
	case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
	case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
	case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
	case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
	case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
	case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
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#endif
	default: BUG();
	}
	ctxt->ops->put_fpu(ctxt);
}

static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
			  int reg)
{
	ctxt->ops->get_fpu(ctxt);
	switch (reg) {
918 919 920 921 922 923 924 925
	case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
	case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
	case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
	case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
	case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
	case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
	case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
	case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
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#ifdef CONFIG_X86_64
927 928 929 930 931 932 933 934
	case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
	case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
	case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
	case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
	case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
	case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
	case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
	case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
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#endif
	default: BUG();
	}
	ctxt->ops->put_fpu(ctxt);
}

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static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
{
	ctxt->ops->get_fpu(ctxt);
	switch (reg) {
	case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
	case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
	case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
	case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
	case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
	case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
	case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
	case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
	default: BUG();
	}
	ctxt->ops->put_fpu(ctxt);
}

static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
{
	ctxt->ops->get_fpu(ctxt);
	switch (reg) {
	case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
	case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
	case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
	case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
	case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
	case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
	case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
	case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
	default: BUG();
	}
	ctxt->ops->put_fpu(ctxt);
}

975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021
static int em_fninit(struct x86_emulate_ctxt *ctxt)
{
	if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
		return emulate_nm(ctxt);

	ctxt->ops->get_fpu(ctxt);
	asm volatile("fninit");
	ctxt->ops->put_fpu(ctxt);
	return X86EMUL_CONTINUE;
}

static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
{
	u16 fcw;

	if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
		return emulate_nm(ctxt);

	ctxt->ops->get_fpu(ctxt);
	asm volatile("fnstcw %0": "+m"(fcw));
	ctxt->ops->put_fpu(ctxt);

	/* force 2 byte destination */
	ctxt->dst.bytes = 2;
	ctxt->dst.val = fcw;

	return X86EMUL_CONTINUE;
}

static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
{
	u16 fsw;

	if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
		return emulate_nm(ctxt);

	ctxt->ops->get_fpu(ctxt);
	asm volatile("fnstsw %0": "+m"(fsw));
	ctxt->ops->put_fpu(ctxt);

	/* force 2 byte destination */
	ctxt->dst.bytes = 2;
	ctxt->dst.val = fsw;

	return X86EMUL_CONTINUE;
}

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1022
static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
1023
				    struct operand *op)
1024
{
1025
	unsigned reg = ctxt->modrm_reg;
1026

1027 1028
	if (!(ctxt->d & ModRM))
		reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
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1029

1030
	if (ctxt->d & Sse) {
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1031 1032 1033 1034 1035 1036
		op->type = OP_XMM;
		op->bytes = 16;
		op->addr.xmm = reg;
		read_sse_reg(ctxt, &op->vec_val, reg);
		return;
	}
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1037 1038 1039 1040 1041 1042 1043
	if (ctxt->d & Mmx) {
		reg &= 7;
		op->type = OP_MM;
		op->bytes = 8;
		op->addr.mm = reg;
		return;
	}
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1044

1045
	op->type = OP_REG;
1046 1047 1048
	op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
	op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);

1049
	fetch_register_operand(op);
1050 1051 1052
	op->orig_val = op->val;
}

1053 1054 1055 1056 1057 1058
static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
{
	if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
		ctxt->modrm_seg = VCPU_SREG_SS;
}

1059
static int decode_modrm(struct x86_emulate_ctxt *ctxt,
1060
			struct operand *op)
1061 1062
{
	u8 sib;
B
Bandan Das 已提交
1063
	int index_reg, base_reg, scale;
1064
	int rc = X86EMUL_CONTINUE;
1065
	ulong modrm_ea = 0;
1066

B
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1067 1068 1069
	ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
	index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
	base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1070

B
Bandan Das 已提交
1071
	ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
1072
	ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
B
Bandan Das 已提交
1073
	ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
1074
	ctxt->modrm_seg = VCPU_SREG_DS;
1075

1076
	if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
1077
		op->type = OP_REG;
1078
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1079
		op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
1080
				ctxt->d & ByteOp);
1081
		if (ctxt->d & Sse) {
A
Avi Kivity 已提交
1082 1083
			op->type = OP_XMM;
			op->bytes = 16;
1084 1085
			op->addr.xmm = ctxt->modrm_rm;
			read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
A
Avi Kivity 已提交
1086 1087
			return rc;
		}
A
Avi Kivity 已提交
1088 1089 1090
		if (ctxt->d & Mmx) {
			op->type = OP_MM;
			op->bytes = 8;
1091
			op->addr.mm = ctxt->modrm_rm & 7;
A
Avi Kivity 已提交
1092 1093
			return rc;
		}
1094
		fetch_register_operand(op);
1095 1096 1097
		return rc;
	}

1098 1099
	op->type = OP_MEM;

1100
	if (ctxt->ad_bytes == 2) {
1101 1102 1103 1104
		unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
		unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
		unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
		unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1105 1106

		/* 16-bit ModR/M decode. */
1107
		switch (ctxt->modrm_mod) {
1108
		case 0:
1109
			if (ctxt->modrm_rm == 6)
1110
				modrm_ea += insn_fetch(u16, ctxt);
1111 1112
			break;
		case 1:
1113
			modrm_ea += insn_fetch(s8, ctxt);
1114 1115
			break;
		case 2:
1116
			modrm_ea += insn_fetch(u16, ctxt);
1117 1118
			break;
		}
1119
		switch (ctxt->modrm_rm) {
1120
		case 0:
1121
			modrm_ea += bx + si;
1122 1123
			break;
		case 1:
1124
			modrm_ea += bx + di;
1125 1126
			break;
		case 2:
1127
			modrm_ea += bp + si;
1128 1129
			break;
		case 3:
1130
			modrm_ea += bp + di;
1131 1132
			break;
		case 4:
1133
			modrm_ea += si;
1134 1135
			break;
		case 5:
1136
			modrm_ea += di;
1137 1138
			break;
		case 6:
1139
			if (ctxt->modrm_mod != 0)
1140
				modrm_ea += bp;
1141 1142
			break;
		case 7:
1143
			modrm_ea += bx;
1144 1145
			break;
		}
1146 1147 1148
		if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
		    (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
			ctxt->modrm_seg = VCPU_SREG_SS;
1149
		modrm_ea = (u16)modrm_ea;
1150 1151
	} else {
		/* 32/64-bit ModR/M decode. */
1152
		if ((ctxt->modrm_rm & 7) == 4) {
1153
			sib = insn_fetch(u8, ctxt);
1154 1155 1156 1157
			index_reg |= (sib >> 3) & 7;
			base_reg |= sib & 7;
			scale = sib >> 6;

1158
			if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
1159
				modrm_ea += insn_fetch(s32, ctxt);
1160
			else {
1161
				modrm_ea += reg_read(ctxt, base_reg);
1162 1163
				adjust_modrm_seg(ctxt, base_reg);
			}
1164
			if (index_reg != 4)
1165
				modrm_ea += reg_read(ctxt, index_reg) << scale;
1166
		} else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
1167
			if (ctxt->mode == X86EMUL_MODE_PROT64)
1168
				ctxt->rip_relative = 1;
1169 1170
		} else {
			base_reg = ctxt->modrm_rm;
1171
			modrm_ea += reg_read(ctxt, base_reg);
1172 1173
			adjust_modrm_seg(ctxt, base_reg);
		}
1174
		switch (ctxt->modrm_mod) {
1175
		case 0:
1176
			if (ctxt->modrm_rm == 5)
1177
				modrm_ea += insn_fetch(s32, ctxt);
1178 1179
			break;
		case 1:
1180
			modrm_ea += insn_fetch(s8, ctxt);
1181 1182
			break;
		case 2:
1183
			modrm_ea += insn_fetch(s32, ctxt);
1184 1185 1186
			break;
		}
	}
1187
	op->addr.mem.ea = modrm_ea;
1188 1189 1190
	if (ctxt->ad_bytes != 8)
		ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;

1191 1192 1193 1194 1195
done:
	return rc;
}

static int decode_abs(struct x86_emulate_ctxt *ctxt,
1196
		      struct operand *op)
1197
{
1198
	int rc = X86EMUL_CONTINUE;
1199

1200
	op->type = OP_MEM;
1201
	switch (ctxt->ad_bytes) {
1202
	case 2:
1203
		op->addr.mem.ea = insn_fetch(u16, ctxt);
1204 1205
		break;
	case 4:
1206
		op->addr.mem.ea = insn_fetch(u32, ctxt);
1207 1208
		break;
	case 8:
1209
		op->addr.mem.ea = insn_fetch(u64, ctxt);
1210 1211 1212 1213 1214 1215
		break;
	}
done:
	return rc;
}

1216
static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
1217
{
1218
	long sv = 0, mask;
1219

1220
	if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1221
		mask = ~((long)ctxt->dst.bytes * 8 - 1);
1222

1223 1224 1225 1226
		if (ctxt->src.bytes == 2)
			sv = (s16)ctxt->src.val & (s16)mask;
		else if (ctxt->src.bytes == 4)
			sv = (s32)ctxt->src.val & (s32)mask;
1227 1228
		else
			sv = (s64)ctxt->src.val & (s64)mask;
1229

1230
		ctxt->dst.addr.mem.ea += (sv >> 3);
1231
	}
1232 1233

	/* only subword offset */
1234
	ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
1235 1236
}

1237 1238
static int read_emulated(struct x86_emulate_ctxt *ctxt,
			 unsigned long addr, void *dest, unsigned size)
A
Avi Kivity 已提交
1239
{
1240
	int rc;
1241
	struct read_cache *mc = &ctxt->mem_read;
A
Avi Kivity 已提交
1242

1243 1244
	if (mc->pos < mc->end)
		goto read_cached;
A
Avi Kivity 已提交
1245

1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257
	WARN_ON((mc->end + size) >= sizeof(mc->data));

	rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
				      &ctxt->exception);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	mc->end += size;

read_cached:
	memcpy(dest, mc->data + mc->pos, size);
	mc->pos += size;
1258 1259
	return X86EMUL_CONTINUE;
}
A
Avi Kivity 已提交
1260

1261 1262 1263 1264 1265
static int segmented_read(struct x86_emulate_ctxt *ctxt,
			  struct segmented_address addr,
			  void *data,
			  unsigned size)
{
1266 1267 1268
	int rc;
	ulong linear;

1269
	rc = linearize(ctxt, addr, size, false, &linear);
1270 1271
	if (rc != X86EMUL_CONTINUE)
		return rc;
1272
	return read_emulated(ctxt, linear, data, size);
1273 1274 1275 1276 1277 1278 1279
}

static int segmented_write(struct x86_emulate_ctxt *ctxt,
			   struct segmented_address addr,
			   const void *data,
			   unsigned size)
{
1280 1281 1282
	int rc;
	ulong linear;

1283
	rc = linearize(ctxt, addr, size, true, &linear);
1284 1285
	if (rc != X86EMUL_CONTINUE)
		return rc;
1286 1287
	return ctxt->ops->write_emulated(ctxt, linear, data, size,
					 &ctxt->exception);
1288 1289 1290 1291 1292 1293 1294
}

static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
			     struct segmented_address addr,
			     const void *orig_data, const void *data,
			     unsigned size)
{
1295 1296 1297
	int rc;
	ulong linear;

1298
	rc = linearize(ctxt, addr, size, true, &linear);
1299 1300
	if (rc != X86EMUL_CONTINUE)
		return rc;
1301 1302
	return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
					   size, &ctxt->exception);
1303 1304
}

1305 1306 1307 1308
static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
			   unsigned int size, unsigned short port,
			   void *dest)
{
1309
	struct read_cache *rc = &ctxt->io_read;
1310

1311 1312
	if (rc->pos == rc->end) { /* refill pio read ahead */
		unsigned int in_page, n;
1313
		unsigned int count = ctxt->rep_prefix ?
1314
			address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
1315
		in_page = (ctxt->eflags & EFLG_DF) ?
1316 1317
			offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
			PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
1318 1319 1320 1321 1322
		n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
			count);
		if (n == 0)
			n = 1;
		rc->pos = rc->end = 0;
1323
		if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
1324 1325
			return 0;
		rc->end = n * size;
A
Avi Kivity 已提交
1326 1327
	}

1328 1329
	if (ctxt->rep_prefix && (ctxt->d & String) &&
	    !(ctxt->eflags & EFLG_DF)) {
1330 1331 1332 1333 1334 1335 1336 1337
		ctxt->dst.data = rc->data + rc->pos;
		ctxt->dst.type = OP_MEM_STR;
		ctxt->dst.count = (rc->end - rc->pos) / size;
		rc->pos = rc->end;
	} else {
		memcpy(dest, rc->data + rc->pos, size);
		rc->pos += size;
	}
1338 1339
	return 1;
}
A
Avi Kivity 已提交
1340

1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356
static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
				     u16 index, struct desc_struct *desc)
{
	struct desc_ptr dt;
	ulong addr;

	ctxt->ops->get_idt(ctxt, &dt);

	if (dt.size < index * 8 + 7)
		return emulate_gp(ctxt, index << 3 | 0x2);

	addr = dt.address + index * 8;
	return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
				   &ctxt->exception);
}

1357 1358 1359
static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
				     u16 selector, struct desc_ptr *dt)
{
1360
	const struct x86_emulate_ops *ops = ctxt->ops;
1361
	u32 base3 = 0;
1362

1363 1364
	if (selector & 1 << 2) {
		struct desc_struct desc;
1365 1366
		u16 sel;

1367
		memset (dt, 0, sizeof *dt);
1368 1369
		if (!ops->get_segment(ctxt, &sel, &desc, &base3,
				      VCPU_SREG_LDTR))
1370
			return;
1371

1372
		dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1373
		dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
1374
	} else
1375
		ops->get_gdt(ctxt, dt);
1376
}
1377

1378 1379
/* allowed just for 8 bytes segments */
static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1380 1381
				   u16 selector, struct desc_struct *desc,
				   ulong *desc_addr_p)
1382 1383 1384 1385
{
	struct desc_ptr dt;
	u16 index = selector >> 3;
	ulong addr;
1386

1387
	get_descriptor_table_ptr(ctxt, selector, &dt);
1388

1389 1390
	if (dt.size < index * 8 + 7)
		return emulate_gp(ctxt, selector & 0xfffc);
1391

1392
	*desc_addr_p = addr = dt.address + index * 8;
1393 1394
	return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
				   &ctxt->exception);
1395
}
1396

1397 1398 1399 1400 1401 1402 1403
/* allowed just for 8 bytes segments */
static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				    u16 selector, struct desc_struct *desc)
{
	struct desc_ptr dt;
	u16 index = selector >> 3;
	ulong addr;
A
Avi Kivity 已提交
1404

1405
	get_descriptor_table_ptr(ctxt, selector, &dt);
1406

1407 1408
	if (dt.size < index * 8 + 7)
		return emulate_gp(ctxt, selector & 0xfffc);
A
Avi Kivity 已提交
1409

1410
	addr = dt.address + index * 8;
1411 1412
	return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
				    &ctxt->exception);
1413
}
1414

1415
/* Does not support long mode */
1416
static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1417
				     u16 selector, int seg, u8 cpl, bool in_task_switch)
1418
{
1419
	struct desc_struct seg_desc, old_desc;
1420
	u8 dpl, rpl;
1421 1422 1423
	unsigned err_vec = GP_VECTOR;
	u32 err_code = 0;
	bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1424
	ulong desc_addr;
1425
	int ret;
1426
	u16 dummy;
1427
	u32 base3 = 0;
1428

1429
	memset(&seg_desc, 0, sizeof seg_desc);
1430

1431 1432 1433
	if (ctxt->mode == X86EMUL_MODE_REAL) {
		/* set real mode segment descriptor (keep limit etc. for
		 * unreal mode) */
1434
		ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
1435 1436
		set_desc_base(&seg_desc, selector << 4);
		goto load;
1437 1438 1439 1440 1441 1442 1443 1444 1445
	} else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
		/* VM86 needs a clean new segment descriptor */
		set_desc_base(&seg_desc, selector << 4);
		set_desc_limit(&seg_desc, 0xffff);
		seg_desc.type = 3;
		seg_desc.p = 1;
		seg_desc.s = 1;
		seg_desc.dpl = 3;
		goto load;
1446 1447
	}

1448 1449 1450 1451 1452 1453 1454
	rpl = selector & 3;

	/* NULL selector is not valid for TR, CS and SS (except for long mode) */
	if ((seg == VCPU_SREG_CS
	     || (seg == VCPU_SREG_SS
		 && (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl))
	     || seg == VCPU_SREG_TR)
1455 1456 1457 1458 1459 1460 1461 1462 1463 1464
	    && null_selector)
		goto exception;

	/* TR should be in GDT only */
	if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
		goto exception;

	if (null_selector) /* for NULL selector skip all following checks */
		goto load;

1465
	ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
1466 1467 1468 1469 1470 1471
	if (ret != X86EMUL_CONTINUE)
		return ret;

	err_code = selector & 0xfffc;
	err_vec = GP_VECTOR;

G
Guo Chao 已提交
1472
	/* can't load system descriptor into segment selector */
1473 1474 1475 1476 1477 1478 1479 1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490
	if (seg <= VCPU_SREG_GS && !seg_desc.s)
		goto exception;

	if (!seg_desc.p) {
		err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
		goto exception;
	}

	dpl = seg_desc.dpl;

	switch (seg) {
	case VCPU_SREG_SS:
		/*
		 * segment is not a writable data segment or segment
		 * selector's RPL != CPL or segment selector's RPL != CPL
		 */
		if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
			goto exception;
A
Avi Kivity 已提交
1491
		break;
1492
	case VCPU_SREG_CS:
1493 1494 1495
		if (in_task_switch && rpl != dpl)
			goto exception;

1496 1497 1498 1499 1500 1501 1502 1503 1504 1505 1506 1507 1508 1509
		if (!(seg_desc.type & 8))
			goto exception;

		if (seg_desc.type & 4) {
			/* conforming */
			if (dpl > cpl)
				goto exception;
		} else {
			/* nonconforming */
			if (rpl > cpl || dpl != cpl)
				goto exception;
		}
		/* CS(RPL) <- CPL */
		selector = (selector & 0xfffc) | cpl;
A
Avi Kivity 已提交
1510
		break;
1511 1512 1513
	case VCPU_SREG_TR:
		if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
			goto exception;
1514 1515 1516 1517 1518 1519
		old_desc = seg_desc;
		seg_desc.type |= 2; /* busy */
		ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
						  sizeof(seg_desc), &ctxt->exception);
		if (ret != X86EMUL_CONTINUE)
			return ret;
1520 1521 1522 1523 1524 1525
		break;
	case VCPU_SREG_LDTR:
		if (seg_desc.s || seg_desc.type != 2)
			goto exception;
		break;
	default: /*  DS, ES, FS, or GS */
1526
		/*
1527 1528 1529
		 * segment is not a data or readable code segment or
		 * ((segment is a data or nonconforming code segment)
		 * and (both RPL and CPL > DPL))
1530
		 */
1531 1532 1533 1534
		if ((seg_desc.type & 0xa) == 0x8 ||
		    (((seg_desc.type & 0xc) != 0xc) &&
		     (rpl > dpl && cpl > dpl)))
			goto exception;
A
Avi Kivity 已提交
1535
		break;
1536 1537 1538 1539 1540
	}

	if (seg_desc.s) {
		/* mark segment as accessed */
		seg_desc.type |= 1;
1541
		ret = write_segment_descriptor(ctxt, selector, &seg_desc);
1542 1543
		if (ret != X86EMUL_CONTINUE)
			return ret;
1544 1545 1546 1547 1548
	} else if (ctxt->mode == X86EMUL_MODE_PROT64) {
		ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
				sizeof(base3), &ctxt->exception);
		if (ret != X86EMUL_CONTINUE)
			return ret;
1549 1550
	}
load:
1551
	ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
1552 1553 1554 1555 1556 1557
	return X86EMUL_CONTINUE;
exception:
	emulate_exception(ctxt, err_vec, err_code, true);
	return X86EMUL_PROPAGATE_FAULT;
}

1558 1559 1560 1561
static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				   u16 selector, int seg)
{
	u8 cpl = ctxt->ops->cpl(ctxt);
1562
	return __load_segment_descriptor(ctxt, selector, seg, cpl, false);
1563 1564
}

1565 1566 1567 1568 1569 1570 1571 1572 1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583
static void write_register_operand(struct operand *op)
{
	/* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
	switch (op->bytes) {
	case 1:
		*(u8 *)op->addr.reg = (u8)op->val;
		break;
	case 2:
		*(u16 *)op->addr.reg = (u16)op->val;
		break;
	case 4:
		*op->addr.reg = (u32)op->val;
		break;	/* 64b: zero-extend */
	case 8:
		*op->addr.reg = op->val;
		break;
	}
}

1584
static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
1585
{
1586
	switch (op->type) {
1587
	case OP_REG:
1588
		write_register_operand(op);
A
Avi Kivity 已提交
1589
		break;
1590
	case OP_MEM:
1591
		if (ctxt->lock_prefix)
P
Paolo Bonzini 已提交
1592 1593 1594 1595 1596 1597 1598
			return segmented_cmpxchg(ctxt,
						 op->addr.mem,
						 &op->orig_val,
						 &op->val,
						 op->bytes);
		else
			return segmented_write(ctxt,
1599 1600 1601
					       op->addr.mem,
					       &op->val,
					       op->bytes);
1602
		break;
1603
	case OP_MEM_STR:
P
Paolo Bonzini 已提交
1604 1605 1606 1607
		return segmented_write(ctxt,
				       op->addr.mem,
				       op->data,
				       op->bytes * op->count);
1608
		break;
A
Avi Kivity 已提交
1609
	case OP_XMM:
1610
		write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
A
Avi Kivity 已提交
1611
		break;
A
Avi Kivity 已提交
1612
	case OP_MM:
1613
		write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
A
Avi Kivity 已提交
1614
		break;
1615 1616
	case OP_NONE:
		/* no writeback */
1617
		break;
1618
	default:
1619
		break;
A
Avi Kivity 已提交
1620
	}
1621 1622
	return X86EMUL_CONTINUE;
}
A
Avi Kivity 已提交
1623

1624
static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
1625
{
1626
	struct segmented_address addr;
1627

1628
	rsp_increment(ctxt, -bytes);
1629
	addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1630 1631
	addr.seg = VCPU_SREG_SS;

1632 1633 1634 1635 1636
	return segmented_write(ctxt, addr, data, bytes);
}

static int em_push(struct x86_emulate_ctxt *ctxt)
{
1637
	/* Disable writeback. */
1638
	ctxt->dst.type = OP_NONE;
1639
	return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
1640
}
1641

1642 1643 1644 1645
static int emulate_pop(struct x86_emulate_ctxt *ctxt,
		       void *dest, int len)
{
	int rc;
1646
	struct segmented_address addr;
1647

1648
	addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1649
	addr.seg = VCPU_SREG_SS;
1650
	rc = segmented_read(ctxt, addr, dest, len);
1651 1652 1653
	if (rc != X86EMUL_CONTINUE)
		return rc;

1654
	rsp_increment(ctxt, len);
1655
	return rc;
1656 1657
}

1658 1659
static int em_pop(struct x86_emulate_ctxt *ctxt)
{
1660
	return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1661 1662
}

1663
static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1664
			void *dest, int len)
1665 1666
{
	int rc;
1667 1668
	unsigned long val, change_mask;
	int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1669
	int cpl = ctxt->ops->cpl(ctxt);
1670

1671
	rc = emulate_pop(ctxt, &val, len);
1672 1673
	if (rc != X86EMUL_CONTINUE)
		return rc;
1674

1675 1676
	change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
		| EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1677

1678 1679 1680 1681 1682 1683 1684 1685 1686 1687
	switch(ctxt->mode) {
	case X86EMUL_MODE_PROT64:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT16:
		if (cpl == 0)
			change_mask |= EFLG_IOPL;
		if (cpl <= iopl)
			change_mask |= EFLG_IF;
		break;
	case X86EMUL_MODE_VM86:
1688 1689
		if (iopl < 3)
			return emulate_gp(ctxt, 0);
1690 1691 1692 1693 1694
		change_mask |= EFLG_IF;
		break;
	default: /* real mode */
		change_mask |= (EFLG_IOPL | EFLG_IF);
		break;
1695
	}
1696 1697 1698 1699 1700

	*(unsigned long *)dest =
		(ctxt->eflags & ~change_mask) | (val & change_mask);

	return rc;
1701 1702
}

1703 1704
static int em_popf(struct x86_emulate_ctxt *ctxt)
{
1705 1706 1707 1708
	ctxt->dst.type = OP_REG;
	ctxt->dst.addr.reg = &ctxt->eflags;
	ctxt->dst.bytes = ctxt->op_bytes;
	return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1709 1710
}

A
Avi Kivity 已提交
1711 1712 1713 1714 1715
static int em_enter(struct x86_emulate_ctxt *ctxt)
{
	int rc;
	unsigned frame_size = ctxt->src.val;
	unsigned nesting_level = ctxt->src2.val & 31;
1716
	ulong rbp;
A
Avi Kivity 已提交
1717 1718 1719 1720

	if (nesting_level)
		return X86EMUL_UNHANDLEABLE;

1721 1722
	rbp = reg_read(ctxt, VCPU_REGS_RBP);
	rc = push(ctxt, &rbp, stack_size(ctxt));
A
Avi Kivity 已提交
1723 1724
	if (rc != X86EMUL_CONTINUE)
		return rc;
1725
	assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
A
Avi Kivity 已提交
1726
		      stack_mask(ctxt));
1727 1728
	assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
		      reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
A
Avi Kivity 已提交
1729 1730 1731 1732
		      stack_mask(ctxt));
	return X86EMUL_CONTINUE;
}

A
Avi Kivity 已提交
1733 1734
static int em_leave(struct x86_emulate_ctxt *ctxt)
{
1735
	assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
A
Avi Kivity 已提交
1736
		      stack_mask(ctxt));
1737
	return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
A
Avi Kivity 已提交
1738 1739
}

1740
static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
1741
{
1742 1743
	int seg = ctxt->src2.val;

1744
	ctxt->src.val = get_segment_selector(ctxt, seg);
1745

1746
	return em_push(ctxt);
1747 1748
}

1749
static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
1750
{
1751
	int seg = ctxt->src2.val;
1752 1753
	unsigned long selector;
	int rc;
1754

1755
	rc = emulate_pop(ctxt, &selector, ctxt->op_bytes);
1756 1757 1758
	if (rc != X86EMUL_CONTINUE)
		return rc;

1759 1760 1761
	if (ctxt->modrm_reg == VCPU_SREG_SS)
		ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;

1762
	rc = load_segment_descriptor(ctxt, (u16)selector, seg);
1763
	return rc;
1764 1765
}

1766
static int em_pusha(struct x86_emulate_ctxt *ctxt)
1767
{
1768
	unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
1769 1770
	int rc = X86EMUL_CONTINUE;
	int reg = VCPU_REGS_RAX;
1771

1772 1773
	while (reg <= VCPU_REGS_RDI) {
		(reg == VCPU_REGS_RSP) ?
1774
		(ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
1775

1776
		rc = em_push(ctxt);
1777 1778
		if (rc != X86EMUL_CONTINUE)
			return rc;
1779

1780
		++reg;
1781 1782
	}

1783
	return rc;
1784 1785
}

1786 1787
static int em_pushf(struct x86_emulate_ctxt *ctxt)
{
1788
	ctxt->src.val =  (unsigned long)ctxt->eflags;
1789 1790 1791
	return em_push(ctxt);
}

1792
static int em_popa(struct x86_emulate_ctxt *ctxt)
1793
{
1794 1795
	int rc = X86EMUL_CONTINUE;
	int reg = VCPU_REGS_RDI;
1796

1797 1798
	while (reg >= VCPU_REGS_RAX) {
		if (reg == VCPU_REGS_RSP) {
1799
			rsp_increment(ctxt, ctxt->op_bytes);
1800 1801
			--reg;
		}
1802

1803
		rc = emulate_pop(ctxt, reg_rmw(ctxt, reg), ctxt->op_bytes);
1804 1805 1806
		if (rc != X86EMUL_CONTINUE)
			break;
		--reg;
1807
	}
1808
	return rc;
1809 1810
}

1811
static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
1812
{
1813
	const struct x86_emulate_ops *ops = ctxt->ops;
1814
	int rc;
1815 1816 1817 1818 1819 1820
	struct desc_ptr dt;
	gva_t cs_addr;
	gva_t eip_addr;
	u16 cs, eip;

	/* TODO: Add limit checks */
1821
	ctxt->src.val = ctxt->eflags;
1822
	rc = em_push(ctxt);
1823 1824
	if (rc != X86EMUL_CONTINUE)
		return rc;
1825 1826 1827

	ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);

1828
	ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
1829
	rc = em_push(ctxt);
1830 1831
	if (rc != X86EMUL_CONTINUE)
		return rc;
1832

1833
	ctxt->src.val = ctxt->_eip;
1834
	rc = em_push(ctxt);
1835 1836 1837
	if (rc != X86EMUL_CONTINUE)
		return rc;

1838
	ops->get_idt(ctxt, &dt);
1839 1840 1841 1842

	eip_addr = dt.address + (irq << 2);
	cs_addr = dt.address + (irq << 2) + 2;

1843
	rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
1844 1845 1846
	if (rc != X86EMUL_CONTINUE)
		return rc;

1847
	rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
1848 1849 1850
	if (rc != X86EMUL_CONTINUE)
		return rc;

1851
	rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
1852 1853 1854
	if (rc != X86EMUL_CONTINUE)
		return rc;

1855
	ctxt->_eip = eip;
1856 1857 1858 1859

	return rc;
}

1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870
int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
{
	int rc;

	invalidate_registers(ctxt);
	rc = __emulate_int_real(ctxt, irq);
	if (rc == X86EMUL_CONTINUE)
		writeback_registers(ctxt);
	return rc;
}

1871
static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
1872 1873 1874
{
	switch(ctxt->mode) {
	case X86EMUL_MODE_REAL:
1875
		return __emulate_int_real(ctxt, irq);
1876 1877 1878 1879 1880 1881 1882 1883 1884 1885
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT64:
	default:
		/* Protected mode interrupts unimplemented yet */
		return X86EMUL_UNHANDLEABLE;
	}
}

1886
static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
1887
{
1888 1889 1890 1891 1892 1893 1894 1895
	int rc = X86EMUL_CONTINUE;
	unsigned long temp_eip = 0;
	unsigned long temp_eflags = 0;
	unsigned long cs = 0;
	unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
			     EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
			     EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
	unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1896

1897
	/* TODO: Add stack limit check */
1898

1899
	rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
1900

1901 1902
	if (rc != X86EMUL_CONTINUE)
		return rc;
1903

1904 1905
	if (temp_eip & ~0xffff)
		return emulate_gp(ctxt, 0);
1906

1907
	rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
1908

1909 1910
	if (rc != X86EMUL_CONTINUE)
		return rc;
1911

1912
	rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
1913

1914 1915
	if (rc != X86EMUL_CONTINUE)
		return rc;
1916

1917
	rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
1918

1919 1920
	if (rc != X86EMUL_CONTINUE)
		return rc;
1921

1922
	ctxt->_eip = temp_eip;
1923 1924


1925
	if (ctxt->op_bytes == 4)
1926
		ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1927
	else if (ctxt->op_bytes == 2) {
1928 1929
		ctxt->eflags &= ~0xffff;
		ctxt->eflags |= temp_eflags;
1930
	}
1931 1932 1933 1934 1935

	ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
	ctxt->eflags |= EFLG_RESERVED_ONE_MASK;

	return rc;
1936 1937
}

1938
static int em_iret(struct x86_emulate_ctxt *ctxt)
1939
{
1940 1941
	switch(ctxt->mode) {
	case X86EMUL_MODE_REAL:
1942
		return emulate_iret_real(ctxt);
1943 1944 1945 1946
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT64:
1947
	default:
1948 1949
		/* iret from protected mode unimplemented yet */
		return X86EMUL_UNHANDLEABLE;
1950 1951 1952
	}
}

1953 1954 1955 1956 1957
static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
{
	int rc;
	unsigned short sel;

1958
	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
1959

1960
	rc = load_segment_descriptor(ctxt, sel, VCPU_SREG_CS);
1961 1962 1963
	if (rc != X86EMUL_CONTINUE)
		return rc;

1964 1965
	ctxt->_eip = 0;
	memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
1966 1967 1968
	return X86EMUL_CONTINUE;
}

1969
static int em_grp45(struct x86_emulate_ctxt *ctxt)
1970
{
1971
	int rc = X86EMUL_CONTINUE;
1972

1973
	switch (ctxt->modrm_reg) {
1974 1975
	case 2: /* call near abs */ {
		long int old_eip;
1976 1977 1978
		old_eip = ctxt->_eip;
		ctxt->_eip = ctxt->src.val;
		ctxt->src.val = old_eip;
1979
		rc = em_push(ctxt);
1980 1981
		break;
	}
1982
	case 4: /* jmp abs */
1983
		ctxt->_eip = ctxt->src.val;
1984
		break;
1985 1986 1987
	case 5: /* jmp far */
		rc = em_jmp_far(ctxt);
		break;
1988
	case 6:	/* push */
1989
		rc = em_push(ctxt);
1990 1991
		break;
	}
1992
	return rc;
1993 1994
}

1995
static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
1996
{
1997
	u64 old = ctxt->dst.orig_val64;
1998

1999 2000 2001
	if (ctxt->dst.bytes == 16)
		return X86EMUL_UNHANDLEABLE;

2002 2003 2004 2005
	if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
	    ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
		*reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
		*reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
2006
		ctxt->eflags &= ~EFLG_ZF;
2007
	} else {
2008 2009
		ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
			(u32) reg_read(ctxt, VCPU_REGS_RBX);
2010

2011
		ctxt->eflags |= EFLG_ZF;
2012
	}
2013
	return X86EMUL_CONTINUE;
2014 2015
}

2016 2017
static int em_ret(struct x86_emulate_ctxt *ctxt)
{
2018 2019 2020
	ctxt->dst.type = OP_REG;
	ctxt->dst.addr.reg = &ctxt->_eip;
	ctxt->dst.bytes = ctxt->op_bytes;
2021 2022 2023
	return em_pop(ctxt);
}

2024
static int em_ret_far(struct x86_emulate_ctxt *ctxt)
2025 2026 2027
{
	int rc;
	unsigned long cs;
2028
	int cpl = ctxt->ops->cpl(ctxt);
2029

2030
	rc = emulate_pop(ctxt, &ctxt->_eip, ctxt->op_bytes);
2031
	if (rc != X86EMUL_CONTINUE)
2032
		return rc;
2033 2034 2035
	if (ctxt->op_bytes == 4)
		ctxt->_eip = (u32)ctxt->_eip;
	rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
2036
	if (rc != X86EMUL_CONTINUE)
2037
		return rc;
2038 2039 2040
	/* Outer-privilege level return is not implemented */
	if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
		return X86EMUL_UNHANDLEABLE;
2041
	rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
2042 2043 2044
	return rc;
}

2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055
static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
{
        int rc;

        rc = em_ret_far(ctxt);
        if (rc != X86EMUL_CONTINUE)
                return rc;
        rsp_increment(ctxt, ctxt->src.val);
        return X86EMUL_CONTINUE;
}

2056 2057 2058
static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
{
	/* Save real source value, then compare EAX against destination. */
2059 2060
	ctxt->dst.orig_val = ctxt->dst.val;
	ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
2061
	ctxt->src.orig_val = ctxt->src.val;
2062
	ctxt->src.val = ctxt->dst.orig_val;
2063
	fastop(ctxt, em_cmp);
2064 2065 2066 2067 2068 2069 2070

	if (ctxt->eflags & EFLG_ZF) {
		/* Success: write back to memory. */
		ctxt->dst.val = ctxt->src.orig_val;
	} else {
		/* Failure: write the value we saw to EAX. */
		ctxt->dst.type = OP_REG;
2071
		ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
2072
		ctxt->dst.val = ctxt->dst.orig_val;
2073 2074 2075 2076
	}
	return X86EMUL_CONTINUE;
}

2077
static int em_lseg(struct x86_emulate_ctxt *ctxt)
2078
{
2079
	int seg = ctxt->src2.val;
2080 2081 2082
	unsigned short sel;
	int rc;

2083
	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2084

2085
	rc = load_segment_descriptor(ctxt, sel, seg);
2086 2087 2088
	if (rc != X86EMUL_CONTINUE)
		return rc;

2089
	ctxt->dst.val = ctxt->src.val;
2090 2091 2092
	return rc;
}

2093
static void
2094
setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
2095
			struct desc_struct *cs, struct desc_struct *ss)
2096 2097
{
	cs->l = 0;		/* will be adjusted later */
2098
	set_desc_base(cs, 0);	/* flat segment */
2099
	cs->g = 1;		/* 4kb granularity */
2100
	set_desc_limit(cs, 0xfffff);	/* 4GB limit */
2101 2102 2103
	cs->type = 0x0b;	/* Read, Execute, Accessed */
	cs->s = 1;
	cs->dpl = 0;		/* will be adjusted later */
2104 2105
	cs->p = 1;
	cs->d = 1;
2106
	cs->avl = 0;
2107

2108 2109
	set_desc_base(ss, 0);	/* flat segment */
	set_desc_limit(ss, 0xfffff);	/* 4GB limit */
2110 2111 2112
	ss->g = 1;		/* 4kb granularity */
	ss->s = 1;
	ss->type = 0x03;	/* Read/Write, Accessed */
2113
	ss->d = 1;		/* 32bit stack segment */
2114
	ss->dpl = 0;
2115
	ss->p = 1;
2116 2117
	ss->l = 0;
	ss->avl = 0;
2118 2119
}

2120 2121 2122 2123 2124
static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
{
	u32 eax, ebx, ecx, edx;

	eax = ecx = 0;
2125 2126
	ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
	return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
2127 2128 2129 2130
		&& ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
		&& edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
}

2131 2132
static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
{
2133
	const struct x86_emulate_ops *ops = ctxt->ops;
2134 2135 2136 2137 2138 2139 2140 2141 2142 2143 2144
	u32 eax, ebx, ecx, edx;

	/*
	 * syscall should always be enabled in longmode - so only become
	 * vendor specific (cpuid) if other modes are active...
	 */
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		return true;

	eax = 0x00000000;
	ecx = 0x00000000;
2145 2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169
	ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
	/*
	 * Intel ("GenuineIntel")
	 * remark: Intel CPUs only support "syscall" in 64bit
	 * longmode. Also an 64bit guest with a
	 * 32bit compat-app running will #UD !! While this
	 * behaviour can be fixed (by emulating) into AMD
	 * response - CPUs of AMD can't behave like Intel.
	 */
	if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
	    ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
	    edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
		return false;

	/* AMD ("AuthenticAMD") */
	if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
	    ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
	    edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
		return true;

	/* AMD ("AMDisbetter!") */
	if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
	    ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
	    edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
		return true;
2170 2171 2172 2173 2174

	/* default: (not Intel, not AMD), apply Intel's stricter rules... */
	return false;
}

2175
static int em_syscall(struct x86_emulate_ctxt *ctxt)
2176
{
2177
	const struct x86_emulate_ops *ops = ctxt->ops;
2178
	struct desc_struct cs, ss;
2179
	u64 msr_data;
2180
	u16 cs_sel, ss_sel;
2181
	u64 efer = 0;
2182 2183

	/* syscall is not available in real mode */
2184
	if (ctxt->mode == X86EMUL_MODE_REAL ||
2185 2186
	    ctxt->mode == X86EMUL_MODE_VM86)
		return emulate_ud(ctxt);
2187

2188 2189 2190
	if (!(em_syscall_is_enabled(ctxt)))
		return emulate_ud(ctxt);

2191
	ops->get_msr(ctxt, MSR_EFER, &efer);
2192
	setup_syscalls_segments(ctxt, &cs, &ss);
2193

2194 2195 2196
	if (!(efer & EFER_SCE))
		return emulate_ud(ctxt);

2197
	ops->get_msr(ctxt, MSR_STAR, &msr_data);
2198
	msr_data >>= 32;
2199 2200
	cs_sel = (u16)(msr_data & 0xfffc);
	ss_sel = (u16)(msr_data + 8);
2201

2202
	if (efer & EFER_LMA) {
2203
		cs.d = 0;
2204 2205
		cs.l = 1;
	}
2206 2207
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2208

2209
	*reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
2210
	if (efer & EFER_LMA) {
2211
#ifdef CONFIG_X86_64
2212
		*reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags & ~EFLG_RF;
2213

2214
		ops->get_msr(ctxt,
2215 2216
			     ctxt->mode == X86EMUL_MODE_PROT64 ?
			     MSR_LSTAR : MSR_CSTAR, &msr_data);
2217
		ctxt->_eip = msr_data;
2218

2219
		ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
2220 2221 2222 2223
		ctxt->eflags &= ~(msr_data | EFLG_RF);
#endif
	} else {
		/* legacy mode */
2224
		ops->get_msr(ctxt, MSR_STAR, &msr_data);
2225
		ctxt->_eip = (u32)msr_data;
2226 2227 2228 2229

		ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
	}

2230
	return X86EMUL_CONTINUE;
2231 2232
}

2233
static int em_sysenter(struct x86_emulate_ctxt *ctxt)
2234
{
2235
	const struct x86_emulate_ops *ops = ctxt->ops;
2236
	struct desc_struct cs, ss;
2237
	u64 msr_data;
2238
	u16 cs_sel, ss_sel;
2239
	u64 efer = 0;
2240

2241
	ops->get_msr(ctxt, MSR_EFER, &efer);
2242
	/* inject #GP if in real mode */
2243 2244
	if (ctxt->mode == X86EMUL_MODE_REAL)
		return emulate_gp(ctxt, 0);
2245

2246 2247 2248 2249 2250 2251 2252 2253
	/*
	 * Not recognized on AMD in compat mode (but is recognized in legacy
	 * mode).
	 */
	if ((ctxt->mode == X86EMUL_MODE_PROT32) && (efer & EFER_LMA)
	    && !vendor_intel(ctxt))
		return emulate_ud(ctxt);

2254 2255 2256
	/* XXX sysenter/sysexit have not been tested in 64bit mode.
	* Therefore, we inject an #UD.
	*/
2257 2258
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		return emulate_ud(ctxt);
2259

2260
	setup_syscalls_segments(ctxt, &cs, &ss);
2261

2262
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2263 2264
	switch (ctxt->mode) {
	case X86EMUL_MODE_PROT32:
2265 2266
		if ((msr_data & 0xfffc) == 0x0)
			return emulate_gp(ctxt, 0);
2267 2268
		break;
	case X86EMUL_MODE_PROT64:
2269 2270
		if (msr_data == 0x0)
			return emulate_gp(ctxt, 0);
2271
		break;
2272 2273
	default:
		break;
2274 2275 2276
	}

	ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
2277 2278 2279 2280
	cs_sel = (u16)msr_data;
	cs_sel &= ~SELECTOR_RPL_MASK;
	ss_sel = cs_sel + 8;
	ss_sel &= ~SELECTOR_RPL_MASK;
2281
	if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
2282
		cs.d = 0;
2283 2284 2285
		cs.l = 1;
	}

2286 2287
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2288

2289
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
2290
	ctxt->_eip = msr_data;
2291

2292
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
2293
	*reg_write(ctxt, VCPU_REGS_RSP) = msr_data;
2294

2295
	return X86EMUL_CONTINUE;
2296 2297
}

2298
static int em_sysexit(struct x86_emulate_ctxt *ctxt)
2299
{
2300
	const struct x86_emulate_ops *ops = ctxt->ops;
2301
	struct desc_struct cs, ss;
2302 2303
	u64 msr_data;
	int usermode;
X
Xiao Guangrong 已提交
2304
	u16 cs_sel = 0, ss_sel = 0;
2305

2306 2307
	/* inject #GP if in real mode or Virtual 8086 mode */
	if (ctxt->mode == X86EMUL_MODE_REAL ||
2308 2309
	    ctxt->mode == X86EMUL_MODE_VM86)
		return emulate_gp(ctxt, 0);
2310

2311
	setup_syscalls_segments(ctxt, &cs, &ss);
2312

2313
	if ((ctxt->rex_prefix & 0x8) != 0x0)
2314 2315 2316 2317 2318 2319
		usermode = X86EMUL_MODE_PROT64;
	else
		usermode = X86EMUL_MODE_PROT32;

	cs.dpl = 3;
	ss.dpl = 3;
2320
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2321 2322
	switch (usermode) {
	case X86EMUL_MODE_PROT32:
2323
		cs_sel = (u16)(msr_data + 16);
2324 2325
		if ((msr_data & 0xfffc) == 0x0)
			return emulate_gp(ctxt, 0);
2326
		ss_sel = (u16)(msr_data + 24);
2327 2328
		break;
	case X86EMUL_MODE_PROT64:
2329
		cs_sel = (u16)(msr_data + 32);
2330 2331
		if (msr_data == 0x0)
			return emulate_gp(ctxt, 0);
2332 2333
		ss_sel = cs_sel + 8;
		cs.d = 0;
2334 2335 2336
		cs.l = 1;
		break;
	}
2337 2338
	cs_sel |= SELECTOR_RPL_MASK;
	ss_sel |= SELECTOR_RPL_MASK;
2339

2340 2341
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2342

2343 2344
	ctxt->_eip = reg_read(ctxt, VCPU_REGS_RDX);
	*reg_write(ctxt, VCPU_REGS_RSP) = reg_read(ctxt, VCPU_REGS_RCX);
2345

2346
	return X86EMUL_CONTINUE;
2347 2348
}

2349
static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
2350 2351 2352 2353 2354 2355 2356
{
	int iopl;
	if (ctxt->mode == X86EMUL_MODE_REAL)
		return false;
	if (ctxt->mode == X86EMUL_MODE_VM86)
		return true;
	iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
2357
	return ctxt->ops->cpl(ctxt) > iopl;
2358 2359 2360 2361 2362
}

static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
					    u16 port, u16 len)
{
2363
	const struct x86_emulate_ops *ops = ctxt->ops;
2364
	struct desc_struct tr_seg;
2365
	u32 base3;
2366
	int r;
2367
	u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
2368
	unsigned mask = (1 << len) - 1;
2369
	unsigned long base;
2370

2371
	ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
2372
	if (!tr_seg.p)
2373
		return false;
2374
	if (desc_limit_scaled(&tr_seg) < 103)
2375
		return false;
2376 2377 2378 2379
	base = get_desc_base(&tr_seg);
#ifdef CONFIG_X86_64
	base |= ((u64)base3) << 32;
#endif
2380
	r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
2381 2382
	if (r != X86EMUL_CONTINUE)
		return false;
2383
	if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
2384
		return false;
2385
	r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
2386 2387 2388 2389 2390 2391 2392 2393 2394 2395
	if (r != X86EMUL_CONTINUE)
		return false;
	if ((perm >> bit_idx) & mask)
		return false;
	return true;
}

static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
				 u16 port, u16 len)
{
2396 2397 2398
	if (ctxt->perm_ok)
		return true;

2399 2400
	if (emulator_bad_iopl(ctxt))
		if (!emulator_io_port_access_allowed(ctxt, port, len))
2401
			return false;
2402 2403 2404

	ctxt->perm_ok = true;

2405 2406 2407
	return true;
}

2408 2409 2410
static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
				struct tss_segment_16 *tss)
{
2411
	tss->ip = ctxt->_eip;
2412
	tss->flag = ctxt->eflags;
2413 2414 2415 2416 2417 2418 2419 2420
	tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
	tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
	tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
	tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
	tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
	tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
	tss->si = reg_read(ctxt, VCPU_REGS_RSI);
	tss->di = reg_read(ctxt, VCPU_REGS_RDI);
2421

2422 2423 2424 2425 2426
	tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
	tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
	tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
	tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
	tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2427 2428 2429 2430 2431 2432
}

static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
				 struct tss_segment_16 *tss)
{
	int ret;
2433
	u8 cpl;
2434

2435
	ctxt->_eip = tss->ip;
2436
	ctxt->eflags = tss->flag | 2;
2437 2438 2439 2440 2441 2442 2443 2444
	*reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
	*reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
	*reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
	*reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
	*reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
	*reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
	*reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
	*reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
2445 2446 2447 2448 2449

	/*
	 * SDM says that segment selectors are loaded before segment
	 * descriptors
	 */
2450 2451 2452 2453 2454
	set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
	set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
	set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
	set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
	set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2455

2456 2457
	cpl = tss->cs & 3;

2458
	/*
G
Guo Chao 已提交
2459
	 * Now load segment descriptors. If fault happens at this stage
2460 2461
	 * it is handled in a context of new task
	 */
2462
	ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl, true);
2463 2464
	if (ret != X86EMUL_CONTINUE)
		return ret;
2465
	ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
2466 2467
	if (ret != X86EMUL_CONTINUE)
		return ret;
2468
	ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
2469 2470
	if (ret != X86EMUL_CONTINUE)
		return ret;
2471
	ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
2472 2473
	if (ret != X86EMUL_CONTINUE)
		return ret;
2474
	ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
2475 2476 2477 2478 2479 2480 2481 2482 2483 2484
	if (ret != X86EMUL_CONTINUE)
		return ret;

	return X86EMUL_CONTINUE;
}

static int task_switch_16(struct x86_emulate_ctxt *ctxt,
			  u16 tss_selector, u16 old_tss_sel,
			  ulong old_tss_base, struct desc_struct *new_desc)
{
2485
	const struct x86_emulate_ops *ops = ctxt->ops;
2486 2487
	struct tss_segment_16 tss_seg;
	int ret;
2488
	u32 new_tss_base = get_desc_base(new_desc);
2489

2490
	ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2491
			    &ctxt->exception);
2492
	if (ret != X86EMUL_CONTINUE)
2493 2494 2495
		/* FIXME: need to provide precise fault address */
		return ret;

2496
	save_state_to_tss16(ctxt, &tss_seg);
2497

2498
	ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2499
			     &ctxt->exception);
2500
	if (ret != X86EMUL_CONTINUE)
2501 2502 2503
		/* FIXME: need to provide precise fault address */
		return ret;

2504
	ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2505
			    &ctxt->exception);
2506
	if (ret != X86EMUL_CONTINUE)
2507 2508 2509 2510 2511 2512
		/* FIXME: need to provide precise fault address */
		return ret;

	if (old_tss_sel != 0xffff) {
		tss_seg.prev_task_link = old_tss_sel;

2513
		ret = ops->write_std(ctxt, new_tss_base,
2514 2515
				     &tss_seg.prev_task_link,
				     sizeof tss_seg.prev_task_link,
2516
				     &ctxt->exception);
2517
		if (ret != X86EMUL_CONTINUE)
2518 2519 2520 2521
			/* FIXME: need to provide precise fault address */
			return ret;
	}

2522
	return load_state_from_tss16(ctxt, &tss_seg);
2523 2524 2525 2526 2527
}

static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
				struct tss_segment_32 *tss)
{
2528
	/* CR3 and ldt selector are not saved intentionally */
2529
	tss->eip = ctxt->_eip;
2530
	tss->eflags = ctxt->eflags;
2531 2532 2533 2534 2535 2536 2537 2538
	tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
	tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
	tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
	tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
	tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
	tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
	tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
	tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
2539

2540 2541 2542 2543 2544 2545
	tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
	tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
	tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
	tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
	tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
	tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
2546 2547 2548 2549 2550 2551
}

static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
				 struct tss_segment_32 *tss)
{
	int ret;
2552
	u8 cpl;
2553

2554
	if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
2555
		return emulate_gp(ctxt, 0);
2556
	ctxt->_eip = tss->eip;
2557
	ctxt->eflags = tss->eflags | 2;
2558 2559

	/* General purpose registers */
2560 2561 2562 2563 2564 2565 2566 2567
	*reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
	*reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
	*reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
	*reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
	*reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
	*reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
	*reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
	*reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
2568 2569 2570

	/*
	 * SDM says that segment selectors are loaded before segment
2571 2572
	 * descriptors.  This is important because CPL checks will
	 * use CS.RPL.
2573
	 */
2574 2575 2576 2577 2578 2579 2580
	set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
	set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
	set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
	set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
	set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
	set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
	set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
2581

2582 2583 2584 2585 2586
	/*
	 * If we're switching between Protected Mode and VM86, we need to make
	 * sure to update the mode before loading the segment descriptors so
	 * that the selectors are interpreted correctly.
	 */
2587
	if (ctxt->eflags & X86_EFLAGS_VM) {
2588
		ctxt->mode = X86EMUL_MODE_VM86;
2589 2590
		cpl = 3;
	} else {
2591
		ctxt->mode = X86EMUL_MODE_PROT32;
2592 2593
		cpl = tss->cs & 3;
	}
2594

2595 2596 2597 2598
	/*
	 * Now load segment descriptors. If fault happenes at this stage
	 * it is handled in a context of new task
	 */
2599
	ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR, cpl, true);
2600 2601
	if (ret != X86EMUL_CONTINUE)
		return ret;
2602
	ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl, true);
2603 2604
	if (ret != X86EMUL_CONTINUE)
		return ret;
2605
	ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl, true);
2606 2607
	if (ret != X86EMUL_CONTINUE)
		return ret;
2608
	ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl, true);
2609 2610
	if (ret != X86EMUL_CONTINUE)
		return ret;
2611
	ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl, true);
2612 2613
	if (ret != X86EMUL_CONTINUE)
		return ret;
2614
	ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl, true);
2615 2616
	if (ret != X86EMUL_CONTINUE)
		return ret;
2617
	ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl, true);
2618 2619 2620 2621 2622 2623 2624 2625 2626 2627
	if (ret != X86EMUL_CONTINUE)
		return ret;

	return X86EMUL_CONTINUE;
}

static int task_switch_32(struct x86_emulate_ctxt *ctxt,
			  u16 tss_selector, u16 old_tss_sel,
			  ulong old_tss_base, struct desc_struct *new_desc)
{
2628
	const struct x86_emulate_ops *ops = ctxt->ops;
2629 2630
	struct tss_segment_32 tss_seg;
	int ret;
2631
	u32 new_tss_base = get_desc_base(new_desc);
2632 2633
	u32 eip_offset = offsetof(struct tss_segment_32, eip);
	u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
2634

2635
	ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2636
			    &ctxt->exception);
2637
	if (ret != X86EMUL_CONTINUE)
2638 2639 2640
		/* FIXME: need to provide precise fault address */
		return ret;

2641
	save_state_to_tss32(ctxt, &tss_seg);
2642

2643 2644 2645
	/* Only GP registers and segment selectors are saved */
	ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
			     ldt_sel_offset - eip_offset, &ctxt->exception);
2646
	if (ret != X86EMUL_CONTINUE)
2647 2648 2649
		/* FIXME: need to provide precise fault address */
		return ret;

2650
	ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2651
			    &ctxt->exception);
2652
	if (ret != X86EMUL_CONTINUE)
2653 2654 2655 2656 2657 2658
		/* FIXME: need to provide precise fault address */
		return ret;

	if (old_tss_sel != 0xffff) {
		tss_seg.prev_task_link = old_tss_sel;

2659
		ret = ops->write_std(ctxt, new_tss_base,
2660 2661
				     &tss_seg.prev_task_link,
				     sizeof tss_seg.prev_task_link,
2662
				     &ctxt->exception);
2663
		if (ret != X86EMUL_CONTINUE)
2664 2665 2666 2667
			/* FIXME: need to provide precise fault address */
			return ret;
	}

2668
	return load_state_from_tss32(ctxt, &tss_seg);
2669 2670 2671
}

static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2672
				   u16 tss_selector, int idt_index, int reason,
2673
				   bool has_error_code, u32 error_code)
2674
{
2675
	const struct x86_emulate_ops *ops = ctxt->ops;
2676 2677
	struct desc_struct curr_tss_desc, next_tss_desc;
	int ret;
2678
	u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
2679
	ulong old_tss_base =
2680
		ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
2681
	u32 desc_limit;
2682
	ulong desc_addr;
2683 2684 2685

	/* FIXME: old_tss_base == ~0 ? */

2686
	ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
2687 2688
	if (ret != X86EMUL_CONTINUE)
		return ret;
2689
	ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
2690 2691 2692 2693 2694
	if (ret != X86EMUL_CONTINUE)
		return ret;

	/* FIXME: check that next_tss_desc is tss */

2695 2696 2697 2698 2699
	/*
	 * Check privileges. The three cases are task switch caused by...
	 *
	 * 1. jmp/call/int to task gate: Check against DPL of the task gate
	 * 2. Exception/IRQ/iret: No check is performed
G
Guo Chao 已提交
2700
	 * 3. jmp/call to TSS: Check against DPL of the TSS
2701 2702 2703 2704 2705 2706 2707 2708 2709 2710 2711 2712 2713 2714 2715 2716 2717 2718 2719 2720
	 */
	if (reason == TASK_SWITCH_GATE) {
		if (idt_index != -1) {
			/* Software interrupts */
			struct desc_struct task_gate_desc;
			int dpl;

			ret = read_interrupt_descriptor(ctxt, idt_index,
							&task_gate_desc);
			if (ret != X86EMUL_CONTINUE)
				return ret;

			dpl = task_gate_desc.dpl;
			if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
				return emulate_gp(ctxt, (idt_index << 3) | 0x2);
		}
	} else if (reason != TASK_SWITCH_IRET) {
		int dpl = next_tss_desc.dpl;
		if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
			return emulate_gp(ctxt, tss_selector);
2721 2722
	}

2723

2724 2725 2726 2727
	desc_limit = desc_limit_scaled(&next_tss_desc);
	if (!next_tss_desc.p ||
	    ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
	     desc_limit < 0x2b)) {
2728
		emulate_ts(ctxt, tss_selector & 0xfffc);
2729 2730 2731 2732 2733
		return X86EMUL_PROPAGATE_FAULT;
	}

	if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
		curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2734
		write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
2735 2736 2737 2738 2739 2740
	}

	if (reason == TASK_SWITCH_IRET)
		ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;

	/* set back link to prev task only if NT bit is set in eflags
G
Guo Chao 已提交
2741
	   note that old_tss_sel is not used after this point */
2742 2743 2744 2745
	if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
		old_tss_sel = 0xffff;

	if (next_tss_desc.type & 8)
2746
		ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
2747 2748
				     old_tss_base, &next_tss_desc);
	else
2749
		ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
2750
				     old_tss_base, &next_tss_desc);
2751 2752
	if (ret != X86EMUL_CONTINUE)
		return ret;
2753 2754 2755 2756 2757 2758

	if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
		ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;

	if (reason != TASK_SWITCH_IRET) {
		next_tss_desc.type |= (1 << 1); /* set busy flag */
2759
		write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
2760 2761
	}

2762
	ops->set_cr(ctxt, 0,  ops->get_cr(ctxt, 0) | X86_CR0_TS);
2763
	ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
2764

2765
	if (has_error_code) {
2766 2767 2768
		ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
		ctxt->lock_prefix = 0;
		ctxt->src.val = (unsigned long) error_code;
2769
		ret = em_push(ctxt);
2770 2771
	}

2772 2773 2774 2775
	return ret;
}

int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2776
			 u16 tss_selector, int idt_index, int reason,
2777
			 bool has_error_code, u32 error_code)
2778 2779 2780
{
	int rc;

2781
	invalidate_registers(ctxt);
2782 2783
	ctxt->_eip = ctxt->eip;
	ctxt->dst.type = OP_NONE;
2784

2785
	rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
2786
				     has_error_code, error_code);
2787

2788
	if (rc == X86EMUL_CONTINUE) {
2789
		ctxt->eip = ctxt->_eip;
2790 2791
		writeback_registers(ctxt);
	}
2792

2793
	return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
2794 2795
}

2796 2797
static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
		struct operand *op)
2798
{
2799
	int df = (ctxt->eflags & EFLG_DF) ? -op->count : op->count;
2800

2801 2802
	register_address_increment(ctxt, reg_rmw(ctxt, reg), df * op->bytes);
	op->addr.mem.ea = register_address(ctxt, reg_read(ctxt, reg));
2803 2804
}

2805 2806 2807 2808 2809 2810
static int em_das(struct x86_emulate_ctxt *ctxt)
{
	u8 al, old_al;
	bool af, cf, old_cf;

	cf = ctxt->eflags & X86_EFLAGS_CF;
2811
	al = ctxt->dst.val;
2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822 2823 2824 2825 2826 2827 2828

	old_al = al;
	old_cf = cf;
	cf = false;
	af = ctxt->eflags & X86_EFLAGS_AF;
	if ((al & 0x0f) > 9 || af) {
		al -= 6;
		cf = old_cf | (al >= 250);
		af = true;
	} else {
		af = false;
	}
	if (old_al > 0x99 || old_cf) {
		al -= 0x60;
		cf = true;
	}

2829
	ctxt->dst.val = al;
2830
	/* Set PF, ZF, SF */
2831 2832 2833
	ctxt->src.type = OP_IMM;
	ctxt->src.val = 0;
	ctxt->src.bytes = 1;
2834
	fastop(ctxt, em_or);
2835 2836 2837 2838 2839 2840 2841 2842
	ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
	if (cf)
		ctxt->eflags |= X86_EFLAGS_CF;
	if (af)
		ctxt->eflags |= X86_EFLAGS_AF;
	return X86EMUL_CONTINUE;
}

P
Paolo Bonzini 已提交
2843 2844 2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 2861 2862 2863 2864
static int em_aam(struct x86_emulate_ctxt *ctxt)
{
	u8 al, ah;

	if (ctxt->src.val == 0)
		return emulate_de(ctxt);

	al = ctxt->dst.val & 0xff;
	ah = al / ctxt->src.val;
	al %= ctxt->src.val;

	ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);

	/* Set PF, ZF, SF */
	ctxt->src.type = OP_IMM;
	ctxt->src.val = 0;
	ctxt->src.bytes = 1;
	fastop(ctxt, em_or);

	return X86EMUL_CONTINUE;
}

2865 2866 2867 2868 2869 2870 2871 2872 2873
static int em_aad(struct x86_emulate_ctxt *ctxt)
{
	u8 al = ctxt->dst.val & 0xff;
	u8 ah = (ctxt->dst.val >> 8) & 0xff;

	al = (al + (ah * ctxt->src.val)) & 0xff;

	ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;

2874 2875 2876 2877 2878
	/* Set PF, ZF, SF */
	ctxt->src.type = OP_IMM;
	ctxt->src.val = 0;
	ctxt->src.bytes = 1;
	fastop(ctxt, em_or);
2879 2880 2881 2882

	return X86EMUL_CONTINUE;
}

2883 2884 2885 2886 2887 2888 2889 2890 2891
static int em_call(struct x86_emulate_ctxt *ctxt)
{
	long rel = ctxt->src.val;

	ctxt->src.val = (unsigned long)ctxt->_eip;
	jmp_rel(ctxt, rel);
	return em_push(ctxt);
}

2892 2893 2894 2895 2896 2897
static int em_call_far(struct x86_emulate_ctxt *ctxt)
{
	u16 sel, old_cs;
	ulong old_eip;
	int rc;

2898
	old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2899
	old_eip = ctxt->_eip;
2900

2901
	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2902
	if (load_segment_descriptor(ctxt, sel, VCPU_SREG_CS))
2903 2904
		return X86EMUL_CONTINUE;

2905 2906
	ctxt->_eip = 0;
	memcpy(&ctxt->_eip, ctxt->src.valptr, ctxt->op_bytes);
2907

2908
	ctxt->src.val = old_cs;
2909
	rc = em_push(ctxt);
2910 2911 2912
	if (rc != X86EMUL_CONTINUE)
		return rc;

2913
	ctxt->src.val = old_eip;
2914
	return em_push(ctxt);
2915 2916
}

2917 2918 2919 2920
static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
{
	int rc;

2921 2922 2923 2924
	ctxt->dst.type = OP_REG;
	ctxt->dst.addr.reg = &ctxt->_eip;
	ctxt->dst.bytes = ctxt->op_bytes;
	rc = emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
2925 2926
	if (rc != X86EMUL_CONTINUE)
		return rc;
2927
	rsp_increment(ctxt, ctxt->src.val);
2928 2929 2930
	return X86EMUL_CONTINUE;
}

2931 2932 2933
static int em_xchg(struct x86_emulate_ctxt *ctxt)
{
	/* Write back the register source. */
2934 2935
	ctxt->src.val = ctxt->dst.val;
	write_register_operand(&ctxt->src);
2936 2937

	/* Write back the memory destination with implicit LOCK prefix. */
2938 2939
	ctxt->dst.val = ctxt->src.orig_val;
	ctxt->lock_prefix = 1;
2940 2941 2942
	return X86EMUL_CONTINUE;
}

2943 2944
static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
{
2945
	ctxt->dst.val = ctxt->src2.val;
2946
	return fastop(ctxt, em_imul);
2947 2948
}

2949 2950
static int em_cwd(struct x86_emulate_ctxt *ctxt)
{
2951 2952
	ctxt->dst.type = OP_REG;
	ctxt->dst.bytes = ctxt->src.bytes;
2953
	ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
2954
	ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
2955 2956 2957 2958

	return X86EMUL_CONTINUE;
}

2959 2960 2961 2962
static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
{
	u64 tsc = 0;

2963
	ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
2964 2965
	*reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
	*reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
2966 2967 2968
	return X86EMUL_CONTINUE;
}

2969 2970 2971 2972
static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
{
	u64 pmc;

2973
	if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
2974
		return emulate_gp(ctxt, 0);
2975 2976
	*reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
	*reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
2977 2978 2979
	return X86EMUL_CONTINUE;
}

2980 2981
static int em_mov(struct x86_emulate_ctxt *ctxt)
{
2982
	memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
2983 2984 2985
	return X86EMUL_CONTINUE;
}

B
Borislav Petkov 已提交
2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 3021 3022 3023 3024 3025
#define FFL(x) bit(X86_FEATURE_##x)

static int em_movbe(struct x86_emulate_ctxt *ctxt)
{
	u32 ebx, ecx, edx, eax = 1;
	u16 tmp;

	/*
	 * Check MOVBE is set in the guest-visible CPUID leaf.
	 */
	ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
	if (!(ecx & FFL(MOVBE)))
		return emulate_ud(ctxt);

	switch (ctxt->op_bytes) {
	case 2:
		/*
		 * From MOVBE definition: "...When the operand size is 16 bits,
		 * the upper word of the destination register remains unchanged
		 * ..."
		 *
		 * Both casting ->valptr and ->val to u16 breaks strict aliasing
		 * rules so we have to do the operation almost per hand.
		 */
		tmp = (u16)ctxt->src.val;
		ctxt->dst.val &= ~0xffffUL;
		ctxt->dst.val |= (unsigned long)swab16(tmp);
		break;
	case 4:
		ctxt->dst.val = swab32((u32)ctxt->src.val);
		break;
	case 8:
		ctxt->dst.val = swab64(ctxt->src.val);
		break;
	default:
		return X86EMUL_PROPAGATE_FAULT;
	}
	return X86EMUL_CONTINUE;
}

3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 3053
static int em_cr_write(struct x86_emulate_ctxt *ctxt)
{
	if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
		return emulate_gp(ctxt, 0);

	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

static int em_dr_write(struct x86_emulate_ctxt *ctxt)
{
	unsigned long val;

	if (ctxt->mode == X86EMUL_MODE_PROT64)
		val = ctxt->src.val & ~0ULL;
	else
		val = ctxt->src.val & ~0U;

	/* #UD condition is already handled. */
	if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
		return emulate_gp(ctxt, 0);

	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

3054 3055 3056 3057
static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
{
	u64 msr_data;

3058 3059 3060
	msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
		| ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
	if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
3061 3062 3063 3064 3065 3066 3067 3068 3069
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
{
	u64 msr_data;

3070
	if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
3071 3072
		return emulate_gp(ctxt, 0);

3073 3074
	*reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
	*reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
3075 3076 3077
	return X86EMUL_CONTINUE;
}

3078 3079
static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
{
3080
	if (ctxt->modrm_reg > VCPU_SREG_GS)
3081 3082
		return emulate_ud(ctxt);

3083
	ctxt->dst.val = get_segment_selector(ctxt, ctxt->modrm_reg);
3084 3085 3086 3087 3088
	return X86EMUL_CONTINUE;
}

static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
{
3089
	u16 sel = ctxt->src.val;
3090

3091
	if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
3092 3093
		return emulate_ud(ctxt);

3094
	if (ctxt->modrm_reg == VCPU_SREG_SS)
3095 3096 3097
		ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;

	/* Disable writeback. */
3098 3099
	ctxt->dst.type = OP_NONE;
	return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
3100 3101
}

A
Avi Kivity 已提交
3102 3103 3104 3105 3106 3107 3108 3109 3110
static int em_lldt(struct x86_emulate_ctxt *ctxt)
{
	u16 sel = ctxt->src.val;

	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
}

A
Avi Kivity 已提交
3111 3112 3113 3114 3115 3116 3117 3118 3119
static int em_ltr(struct x86_emulate_ctxt *ctxt)
{
	u16 sel = ctxt->src.val;

	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
}

3120 3121
static int em_invlpg(struct x86_emulate_ctxt *ctxt)
{
3122 3123 3124
	int rc;
	ulong linear;

3125
	rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
3126
	if (rc == X86EMUL_CONTINUE)
3127
		ctxt->ops->invlpg(ctxt, linear);
3128
	/* Disable writeback. */
3129
	ctxt->dst.type = OP_NONE;
3130 3131 3132
	return X86EMUL_CONTINUE;
}

3133 3134 3135 3136 3137 3138 3139 3140 3141 3142
static int em_clts(struct x86_emulate_ctxt *ctxt)
{
	ulong cr0;

	cr0 = ctxt->ops->get_cr(ctxt, 0);
	cr0 &= ~X86_CR0_TS;
	ctxt->ops->set_cr(ctxt, 0, cr0);
	return X86EMUL_CONTINUE;
}

3143 3144 3145 3146
static int em_vmcall(struct x86_emulate_ctxt *ctxt)
{
	int rc;

3147
	if (ctxt->modrm_mod != 3 || ctxt->modrm_rm != 1)
3148 3149 3150 3151 3152 3153 3154
		return X86EMUL_UNHANDLEABLE;

	rc = ctxt->ops->fix_hypercall(ctxt);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	/* Let the processor re-execute the fixed hypercall */
3155
	ctxt->_eip = ctxt->eip;
3156
	/* Disable writeback. */
3157
	ctxt->dst.type = OP_NONE;
3158 3159 3160
	return X86EMUL_CONTINUE;
}

3161 3162 3163 3164 3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175 3176 3177 3178 3179 3180 3181 3182 3183 3184 3185 3186 3187 3188 3189
static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
				  void (*get)(struct x86_emulate_ctxt *ctxt,
					      struct desc_ptr *ptr))
{
	struct desc_ptr desc_ptr;

	if (ctxt->mode == X86EMUL_MODE_PROT64)
		ctxt->op_bytes = 8;
	get(ctxt, &desc_ptr);
	if (ctxt->op_bytes == 2) {
		ctxt->op_bytes = 4;
		desc_ptr.address &= 0x00ffffff;
	}
	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return segmented_write(ctxt, ctxt->dst.addr.mem,
			       &desc_ptr, 2 + ctxt->op_bytes);
}

static int em_sgdt(struct x86_emulate_ctxt *ctxt)
{
	return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
}

static int em_sidt(struct x86_emulate_ctxt *ctxt)
{
	return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
}

3190 3191 3192 3193 3194
static int em_lgdt(struct x86_emulate_ctxt *ctxt)
{
	struct desc_ptr desc_ptr;
	int rc;

3195 3196
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		ctxt->op_bytes = 8;
3197
	rc = read_descriptor(ctxt, ctxt->src.addr.mem,
3198
			     &desc_ptr.size, &desc_ptr.address,
3199
			     ctxt->op_bytes);
3200 3201 3202 3203
	if (rc != X86EMUL_CONTINUE)
		return rc;
	ctxt->ops->set_gdt(ctxt, &desc_ptr);
	/* Disable writeback. */
3204
	ctxt->dst.type = OP_NONE;
3205 3206 3207
	return X86EMUL_CONTINUE;
}

3208
static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
3209 3210 3211
{
	int rc;

3212 3213
	rc = ctxt->ops->fix_hypercall(ctxt);

3214
	/* Disable writeback. */
3215
	ctxt->dst.type = OP_NONE;
3216 3217 3218 3219 3220 3221 3222 3223
	return rc;
}

static int em_lidt(struct x86_emulate_ctxt *ctxt)
{
	struct desc_ptr desc_ptr;
	int rc;

3224 3225
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		ctxt->op_bytes = 8;
3226
	rc = read_descriptor(ctxt, ctxt->src.addr.mem,
3227
			     &desc_ptr.size, &desc_ptr.address,
3228
			     ctxt->op_bytes);
3229 3230 3231 3232
	if (rc != X86EMUL_CONTINUE)
		return rc;
	ctxt->ops->set_idt(ctxt, &desc_ptr);
	/* Disable writeback. */
3233
	ctxt->dst.type = OP_NONE;
3234 3235 3236 3237 3238
	return X86EMUL_CONTINUE;
}

static int em_smsw(struct x86_emulate_ctxt *ctxt)
{
3239 3240
	if (ctxt->dst.type == OP_MEM)
		ctxt->dst.bytes = 2;
3241
	ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
3242 3243 3244 3245 3246 3247
	return X86EMUL_CONTINUE;
}

static int em_lmsw(struct x86_emulate_ctxt *ctxt)
{
	ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
3248 3249
			  | (ctxt->src.val & 0x0f));
	ctxt->dst.type = OP_NONE;
3250 3251 3252
	return X86EMUL_CONTINUE;
}

3253 3254
static int em_loop(struct x86_emulate_ctxt *ctxt)
{
3255 3256
	register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX), -1);
	if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
3257 3258
	    (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
		jmp_rel(ctxt, ctxt->src.val);
3259 3260 3261 3262 3263 3264

	return X86EMUL_CONTINUE;
}

static int em_jcxz(struct x86_emulate_ctxt *ctxt)
{
3265
	if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
3266
		jmp_rel(ctxt, ctxt->src.val);
3267 3268 3269 3270

	return X86EMUL_CONTINUE;
}

3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288
static int em_in(struct x86_emulate_ctxt *ctxt)
{
	if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
			     &ctxt->dst.val))
		return X86EMUL_IO_NEEDED;

	return X86EMUL_CONTINUE;
}

static int em_out(struct x86_emulate_ctxt *ctxt)
{
	ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
				    &ctxt->src.val, 1);
	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

3289 3290 3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305 3306 3307
static int em_cli(struct x86_emulate_ctxt *ctxt)
{
	if (emulator_bad_iopl(ctxt))
		return emulate_gp(ctxt, 0);

	ctxt->eflags &= ~X86_EFLAGS_IF;
	return X86EMUL_CONTINUE;
}

static int em_sti(struct x86_emulate_ctxt *ctxt)
{
	if (emulator_bad_iopl(ctxt))
		return emulate_gp(ctxt, 0);

	ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
	ctxt->eflags |= X86_EFLAGS_IF;
	return X86EMUL_CONTINUE;
}

A
Avi Kivity 已提交
3308 3309 3310 3311
static int em_cpuid(struct x86_emulate_ctxt *ctxt)
{
	u32 eax, ebx, ecx, edx;

3312 3313
	eax = reg_read(ctxt, VCPU_REGS_RAX);
	ecx = reg_read(ctxt, VCPU_REGS_RCX);
A
Avi Kivity 已提交
3314
	ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx);
3315 3316 3317 3318
	*reg_write(ctxt, VCPU_REGS_RAX) = eax;
	*reg_write(ctxt, VCPU_REGS_RBX) = ebx;
	*reg_write(ctxt, VCPU_REGS_RCX) = ecx;
	*reg_write(ctxt, VCPU_REGS_RDX) = edx;
A
Avi Kivity 已提交
3319 3320 3321
	return X86EMUL_CONTINUE;
}

P
Paolo Bonzini 已提交
3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333
static int em_sahf(struct x86_emulate_ctxt *ctxt)
{
	u32 flags;

	flags = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF;
	flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;

	ctxt->eflags &= ~0xffUL;
	ctxt->eflags |= flags | X86_EFLAGS_FIXED;
	return X86EMUL_CONTINUE;
}

A
Avi Kivity 已提交
3334 3335
static int em_lahf(struct x86_emulate_ctxt *ctxt)
{
3336 3337
	*reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
	*reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
A
Avi Kivity 已提交
3338 3339 3340
	return X86EMUL_CONTINUE;
}

A
Avi Kivity 已提交
3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355
static int em_bswap(struct x86_emulate_ctxt *ctxt)
{
	switch (ctxt->op_bytes) {
#ifdef CONFIG_X86_64
	case 8:
		asm("bswap %0" : "+r"(ctxt->dst.val));
		break;
#endif
	default:
		asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
		break;
	}
	return X86EMUL_CONTINUE;
}

3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369
static bool valid_cr(int nr)
{
	switch (nr) {
	case 0:
	case 2 ... 4:
	case 8:
		return true;
	default:
		return false;
	}
}

static int check_cr_read(struct x86_emulate_ctxt *ctxt)
{
3370
	if (!valid_cr(ctxt->modrm_reg))
3371 3372 3373 3374 3375 3376 3377
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_cr_write(struct x86_emulate_ctxt *ctxt)
{
3378 3379
	u64 new_val = ctxt->src.val64;
	int cr = ctxt->modrm_reg;
3380
	u64 efer = 0;
3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397

	static u64 cr_reserved_bits[] = {
		0xffffffff00000000ULL,
		0, 0, 0, /* CR3 checked later */
		CR4_RESERVED_BITS,
		0, 0, 0,
		CR8_RESERVED_BITS,
	};

	if (!valid_cr(cr))
		return emulate_ud(ctxt);

	if (new_val & cr_reserved_bits[cr])
		return emulate_gp(ctxt, 0);

	switch (cr) {
	case 0: {
3398
		u64 cr4;
3399 3400 3401 3402
		if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
		    ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
			return emulate_gp(ctxt, 0);

3403 3404
		cr4 = ctxt->ops->get_cr(ctxt, 4);
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3405 3406 3407 3408 3409 3410 3411 3412 3413 3414

		if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
		    !(cr4 & X86_CR4_PAE))
			return emulate_gp(ctxt, 0);

		break;
		}
	case 3: {
		u64 rsvd = 0;

3415 3416
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
		if (efer & EFER_LMA)
3417 3418 3419 3420 3421 3422 3423 3424
			rsvd = CR3_L_MODE_RESERVED_BITS;

		if (new_val & rsvd)
			return emulate_gp(ctxt, 0);

		break;
		}
	case 4: {
3425
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436

		if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
			return emulate_gp(ctxt, 0);

		break;
		}
	}

	return X86EMUL_CONTINUE;
}

3437 3438 3439 3440
static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
{
	unsigned long dr7;

3441
	ctxt->ops->get_dr(ctxt, 7, &dr7);
3442 3443 3444 3445 3446 3447 3448

	/* Check if DR7.Global_Enable is set */
	return dr7 & (1 << 13);
}

static int check_dr_read(struct x86_emulate_ctxt *ctxt)
{
3449
	int dr = ctxt->modrm_reg;
3450 3451 3452 3453 3454
	u64 cr4;

	if (dr > 7)
		return emulate_ud(ctxt);

3455
	cr4 = ctxt->ops->get_cr(ctxt, 4);
3456 3457 3458 3459 3460 3461 3462 3463 3464 3465 3466
	if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
		return emulate_ud(ctxt);

	if (check_dr7_gd(ctxt))
		return emulate_db(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_dr_write(struct x86_emulate_ctxt *ctxt)
{
3467 3468
	u64 new_val = ctxt->src.val64;
	int dr = ctxt->modrm_reg;
3469 3470 3471 3472 3473 3474 3475

	if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
		return emulate_gp(ctxt, 0);

	return check_dr_read(ctxt);
}

3476 3477 3478 3479
static int check_svme(struct x86_emulate_ctxt *ctxt)
{
	u64 efer;

3480
	ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
3481 3482 3483 3484 3485 3486 3487 3488 3489

	if (!(efer & EFER_SVME))
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
{
3490
	u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
3491 3492

	/* Valid physical address? */
3493
	if (rax & 0xffff000000000000ULL)
3494 3495 3496 3497 3498
		return emulate_gp(ctxt, 0);

	return check_svme(ctxt);
}

3499 3500
static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
{
3501
	u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
3502

3503
	if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
3504 3505 3506 3507 3508
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

3509 3510
static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
{
3511
	u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
3512
	u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
3513

3514
	if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
3515
	    ctxt->ops->check_pmc(ctxt, rcx))
3516 3517 3518 3519 3520
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

3521 3522
static int check_perm_in(struct x86_emulate_ctxt *ctxt)
{
3523 3524
	ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
	if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
3525 3526 3527 3528 3529 3530 3531
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

static int check_perm_out(struct x86_emulate_ctxt *ctxt)
{
3532 3533
	ctxt->src.bytes = min(ctxt->src.bytes, 4u);
	if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
3534 3535 3536 3537 3538
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

3539
#define D(_y) { .flags = (_y) }
3540 3541 3542
#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
		      .intercept = x86_intercept_##_i, .check_perm = (_p) }
3543
#define N    D(NotImpl)
3544
#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
3545 3546
#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
3547
#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
3548
#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
3549
#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
3550
#define II(_f, _e, _i) \
3551
	{ .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
3552
#define IIP(_f, _e, _i, _p) \
3553 3554
	{ .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
	  .intercept = x86_intercept_##_i, .check_perm = (_p) }
3555
#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
3556

3557
#define D2bv(_f)      D((_f) | ByteOp), D(_f)
3558
#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
3559
#define I2bv(_f, _e)  I((_f) | ByteOp, _e), I(_f, _e)
3560
#define F2bv(_f, _e)  F((_f) | ByteOp, _e), F(_f, _e)
3561 3562
#define I2bvIP(_f, _e, _i, _p) \
	IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
3563

3564 3565 3566
#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e),		\
		F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e),	\
		F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
3567

3568
static const struct opcode group7_rm1[] = {
3569 3570
	DI(SrcNone | Priv, monitor),
	DI(SrcNone | Priv, mwait),
3571 3572 3573
	N, N, N, N, N, N,
};

3574
static const struct opcode group7_rm3[] = {
3575
	DIP(SrcNone | Prot | Priv,		vmrun,		check_svme_pa),
3576
	II(SrcNone  | Prot | EmulateOnUD,	em_vmmcall,	vmmcall),
3577 3578 3579 3580 3581 3582
	DIP(SrcNone | Prot | Priv,		vmload,		check_svme_pa),
	DIP(SrcNone | Prot | Priv,		vmsave,		check_svme_pa),
	DIP(SrcNone | Prot | Priv,		stgi,		check_svme),
	DIP(SrcNone | Prot | Priv,		clgi,		check_svme),
	DIP(SrcNone | Prot | Priv,		skinit,		check_svme),
	DIP(SrcNone | Prot | Priv,		invlpga,	check_svme),
3583
};
3584

3585
static const struct opcode group7_rm7[] = {
3586
	N,
3587
	DIP(SrcNone, rdtscp, check_rdtsc),
3588 3589
	N, N, N, N, N, N,
};
3590

3591
static const struct opcode group1[] = {
3592 3593 3594 3595 3596 3597 3598 3599
	F(Lock, em_add),
	F(Lock | PageTable, em_or),
	F(Lock, em_adc),
	F(Lock, em_sbb),
	F(Lock | PageTable, em_and),
	F(Lock, em_sub),
	F(Lock, em_xor),
	F(NoWrite, em_cmp),
3600 3601
};

3602
static const struct opcode group1A[] = {
3603
	I(DstMem | SrcNone | Mov | Stack, em_pop), N, N, N, N, N, N, N,
3604 3605
};

3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616
static const struct opcode group2[] = {
	F(DstMem | ModRM, em_rol),
	F(DstMem | ModRM, em_ror),
	F(DstMem | ModRM, em_rcl),
	F(DstMem | ModRM, em_rcr),
	F(DstMem | ModRM, em_shl),
	F(DstMem | ModRM, em_shr),
	F(DstMem | ModRM, em_shl),
	F(DstMem | ModRM, em_sar),
};

3617
static const struct opcode group3[] = {
3618 3619
	F(DstMem | SrcImm | NoWrite, em_test),
	F(DstMem | SrcImm | NoWrite, em_test),
3620 3621
	F(DstMem | SrcNone | Lock, em_not),
	F(DstMem | SrcNone | Lock, em_neg),
3622 3623
	F(DstXacc | Src2Mem, em_mul_ex),
	F(DstXacc | Src2Mem, em_imul_ex),
3624 3625
	F(DstXacc | Src2Mem, em_div_ex),
	F(DstXacc | Src2Mem, em_idiv_ex),
3626 3627
};

3628
static const struct opcode group4[] = {
3629 3630
	F(ByteOp | DstMem | SrcNone | Lock, em_inc),
	F(ByteOp | DstMem | SrcNone | Lock, em_dec),
3631 3632 3633
	N, N, N, N, N, N,
};

3634
static const struct opcode group5[] = {
3635 3636
	F(DstMem | SrcNone | Lock,		em_inc),
	F(DstMem | SrcNone | Lock,		em_dec),
3637 3638 3639 3640
	I(SrcMem | Stack,			em_grp45),
	I(SrcMemFAddr | ImplicitOps | Stack,	em_call_far),
	I(SrcMem | Stack,			em_grp45),
	I(SrcMemFAddr | ImplicitOps,		em_grp45),
3641
	I(SrcMem | Stack,			em_grp45), D(Undefined),
3642 3643
};

3644
static const struct opcode group6[] = {
3645 3646
	DI(Prot,	sldt),
	DI(Prot,	str),
A
Avi Kivity 已提交
3647
	II(Prot | Priv | SrcMem16, em_lldt, lldt),
A
Avi Kivity 已提交
3648
	II(Prot | Priv | SrcMem16, em_ltr, ltr),
3649 3650 3651
	N, N, N, N,
};

3652
static const struct group_dual group7 = { {
3653 3654
	II(Mov | DstMem,			em_sgdt, sgdt),
	II(Mov | DstMem,			em_sidt, sidt),
3655 3656 3657 3658 3659
	II(SrcMem | Priv,			em_lgdt, lgdt),
	II(SrcMem | Priv,			em_lidt, lidt),
	II(SrcNone | DstMem | Mov,		em_smsw, smsw), N,
	II(SrcMem16 | Mov | Priv,		em_lmsw, lmsw),
	II(SrcMem | ByteOp | Priv | NoAccess,	em_invlpg, invlpg),
3660
}, {
3661
	I(SrcNone | Priv | EmulateOnUD,	em_vmcall),
3662
	EXT(0, group7_rm1),
3663
	N, EXT(0, group7_rm3),
3664 3665 3666
	II(SrcNone | DstMem | Mov,		em_smsw, smsw), N,
	II(SrcMem16 | Mov | Priv,		em_lmsw, lmsw),
	EXT(0, group7_rm7),
3667 3668
} };

3669
static const struct opcode group8[] = {
3670
	N, N, N, N,
3671 3672 3673 3674
	F(DstMem | SrcImmByte | NoWrite,		em_bt),
	F(DstMem | SrcImmByte | Lock | PageTable,	em_bts),
	F(DstMem | SrcImmByte | Lock,			em_btr),
	F(DstMem | SrcImmByte | Lock | PageTable,	em_btc),
3675 3676
};

3677
static const struct group_dual group9 = { {
3678
	N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
3679 3680 3681 3682
}, {
	N, N, N, N, N, N, N, N,
} };

3683
static const struct opcode group11[] = {
3684
	I(DstMem | SrcImm | Mov | PageTable, em_mov),
3685
	X7(D(Undefined)),
3686 3687
};

3688
static const struct gprefix pfx_0f_6f_0f_7f = {
3689
	I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
3690 3691
};

3692
static const struct gprefix pfx_vmovntpx = {
3693 3694 3695
	I(0, em_mov), N, N, N,
};

3696
static const struct gprefix pfx_0f_28_0f_29 = {
3697
	I(Aligned, em_mov), I(Aligned, em_mov), N, N,
3698 3699
};

3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759 3760 3761 3762
static const struct escape escape_d9 = { {
	N, N, N, N, N, N, N, I(DstMem, em_fnstcw),
}, {
	/* 0xC0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xC8 - 0xCF */
	N, N, N, N, N, N, N, N,
	/* 0xD0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xD8 - 0xDF */
	N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xE7 */
	N, N, N, N, N, N, N, N,
	/* 0xE8 - 0xEF */
	N, N, N, N, N, N, N, N,
	/* 0xF0 - 0xF7 */
	N, N, N, N, N, N, N, N,
	/* 0xF8 - 0xFF */
	N, N, N, N, N, N, N, N,
} };

static const struct escape escape_db = { {
	N, N, N, N, N, N, N, N,
}, {
	/* 0xC0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xC8 - 0xCF */
	N, N, N, N, N, N, N, N,
	/* 0xD0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xD8 - 0xDF */
	N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xE7 */
	N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
	/* 0xE8 - 0xEF */
	N, N, N, N, N, N, N, N,
	/* 0xF0 - 0xF7 */
	N, N, N, N, N, N, N, N,
	/* 0xF8 - 0xFF */
	N, N, N, N, N, N, N, N,
} };

static const struct escape escape_dd = { {
	N, N, N, N, N, N, N, I(DstMem, em_fnstsw),
}, {
	/* 0xC0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xC8 - 0xCF */
	N, N, N, N, N, N, N, N,
	/* 0xD0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xD8 - 0xDF */
	N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xE7 */
	N, N, N, N, N, N, N, N,
	/* 0xE8 - 0xEF */
	N, N, N, N, N, N, N, N,
	/* 0xF0 - 0xF7 */
	N, N, N, N, N, N, N, N,
	/* 0xF8 - 0xFF */
	N, N, N, N, N, N, N, N,
} };

3763
static const struct opcode opcode_table[256] = {
3764
	/* 0x00 - 0x07 */
3765
	F6ALU(Lock, em_add),
3766 3767
	I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
	I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
3768
	/* 0x08 - 0x0F */
3769
	F6ALU(Lock | PageTable, em_or),
3770 3771
	I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
	N,
3772
	/* 0x10 - 0x17 */
3773
	F6ALU(Lock, em_adc),
3774 3775
	I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
	I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
3776
	/* 0x18 - 0x1F */
3777
	F6ALU(Lock, em_sbb),
3778 3779
	I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
	I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
3780
	/* 0x20 - 0x27 */
3781
	F6ALU(Lock | PageTable, em_and), N, N,
3782
	/* 0x28 - 0x2F */
3783
	F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
3784
	/* 0x30 - 0x37 */
3785
	F6ALU(Lock, em_xor), N, N,
3786
	/* 0x38 - 0x3F */
3787
	F6ALU(NoWrite, em_cmp), N, N,
3788
	/* 0x40 - 0x4F */
3789
	X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
3790
	/* 0x50 - 0x57 */
3791
	X8(I(SrcReg | Stack, em_push)),
3792
	/* 0x58 - 0x5F */
3793
	X8(I(DstReg | Stack, em_pop)),
3794
	/* 0x60 - 0x67 */
3795 3796
	I(ImplicitOps | Stack | No64, em_pusha),
	I(ImplicitOps | Stack | No64, em_popa),
3797 3798 3799
	N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
	N, N, N, N,
	/* 0x68 - 0x6F */
3800 3801
	I(SrcImm | Mov | Stack, em_push),
	I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
3802 3803
	I(SrcImmByte | Mov | Stack, em_push),
	I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
3804
	I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
3805
	I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
3806 3807 3808
	/* 0x70 - 0x7F */
	X16(D(SrcImmByte)),
	/* 0x80 - 0x87 */
3809 3810 3811 3812
	G(ByteOp | DstMem | SrcImm, group1),
	G(DstMem | SrcImm, group1),
	G(ByteOp | DstMem | SrcImm | No64, group1),
	G(DstMem | SrcImmByte, group1),
3813
	F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
3814
	I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
3815
	/* 0x88 - 0x8F */
3816
	I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
3817
	I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
3818
	I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
3819 3820 3821
	D(ModRM | SrcMem | NoAccess | DstReg),
	I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
	G(0, group1A),
3822
	/* 0x90 - 0x97 */
3823
	DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
3824
	/* 0x98 - 0x9F */
3825
	D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
3826
	I(SrcImmFAddr | No64, em_call_far), N,
3827
	II(ImplicitOps | Stack, em_pushf, pushf),
P
Paolo Bonzini 已提交
3828 3829
	II(ImplicitOps | Stack, em_popf, popf),
	I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
3830
	/* 0xA0 - 0xA7 */
3831
	I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
3832
	I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
3833
	I2bv(SrcSI | DstDI | Mov | String, em_mov),
3834
	F2bv(SrcSI | DstDI | String | NoWrite, em_cmp),
3835
	/* 0xA8 - 0xAF */
3836
	F2bv(DstAcc | SrcImm | NoWrite, em_test),
3837 3838
	I2bv(SrcAcc | DstDI | Mov | String, em_mov),
	I2bv(SrcSI | DstAcc | Mov | String, em_mov),
3839
	F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp),
3840
	/* 0xB0 - 0xB7 */
3841
	X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
3842
	/* 0xB8 - 0xBF */
3843
	X8(I(DstReg | SrcImm64 | Mov, em_mov)),
3844
	/* 0xC0 - 0xC7 */
3845
	G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
3846
	I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
3847
	I(ImplicitOps | Stack, em_ret),
3848 3849
	I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
	I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
3850
	G(ByteOp, group11), G(0, group11),
3851
	/* 0xC8 - 0xCF */
A
Avi Kivity 已提交
3852
	I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
3853 3854
	I(ImplicitOps | Stack | SrcImmU16, em_ret_far_imm),
	I(ImplicitOps | Stack, em_ret_far),
3855
	D(ImplicitOps), DI(SrcImmByte, intn),
3856
	D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
3857
	/* 0xD0 - 0xD7 */
3858 3859
	G(Src2One | ByteOp, group2), G(Src2One, group2),
	G(Src2CL | ByteOp, group2), G(Src2CL, group2),
P
Paolo Bonzini 已提交
3860
	I(DstAcc | SrcImmUByte | No64, em_aam),
P
Paolo Bonzini 已提交
3861 3862
	I(DstAcc | SrcImmUByte | No64, em_aad),
	F(DstAcc | ByteOp | No64, em_salc),
P
Paolo Bonzini 已提交
3863
	I(DstAcc | SrcXLat | ByteOp, em_mov),
3864
	/* 0xD8 - 0xDF */
3865
	N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
3866
	/* 0xE0 - 0xE7 */
3867 3868
	X3(I(SrcImmByte, em_loop)),
	I(SrcImmByte, em_jcxz),
3869 3870
	I2bvIP(SrcImmUByte | DstAcc, em_in,  in,  check_perm_in),
	I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
3871
	/* 0xE8 - 0xEF */
3872
	I(SrcImm | Stack, em_call), D(SrcImm | ImplicitOps),
3873
	I(SrcImmFAddr | No64, em_jmp_far), D(SrcImmByte | ImplicitOps),
3874 3875
	I2bvIP(SrcDX | DstAcc, em_in,  in,  check_perm_in),
	I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
3876
	/* 0xF0 - 0xF7 */
3877
	N, DI(ImplicitOps, icebp), N, N,
3878 3879
	DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
	G(ByteOp, group3), G(0, group3),
3880
	/* 0xF8 - 0xFF */
3881 3882
	D(ImplicitOps), D(ImplicitOps),
	I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
3883 3884 3885
	D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
};

3886
static const struct opcode twobyte_table[256] = {
3887
	/* 0x00 - 0x0F */
3888
	G(0, group6), GD(0, &group7), N, N,
3889
	N, I(ImplicitOps | EmulateOnUD, em_syscall),
3890
	II(ImplicitOps | Priv, em_clts, clts), N,
3891
	DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3892 3893
	N, D(ImplicitOps | ModRM), N, N,
	/* 0x10 - 0x1F */
P
Paolo Bonzini 已提交
3894 3895
	N, N, N, N, N, N, N, N,
	D(ImplicitOps | ModRM), N, N, N, N, N, N, D(ImplicitOps | ModRM),
3896
	/* 0x20 - 0x2F */
3897 3898 3899 3900 3901 3902
	DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
	DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
	IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
						check_cr_write),
	IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
						check_dr_write),
3903
	N, N, N, N,
3904 3905 3906
	GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
	GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
	N, GP(ModRM | DstMem | SrcReg | Sse | Mov | Aligned, &pfx_vmovntpx),
3907
	N, N, N, N,
3908
	/* 0x30 - 0x3F */
3909
	II(ImplicitOps | Priv, em_wrmsr, wrmsr),
3910
	IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
3911
	II(ImplicitOps | Priv, em_rdmsr, rdmsr),
3912
	IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
3913 3914
	I(ImplicitOps | EmulateOnUD, em_sysenter),
	I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
3915
	N, N,
3916 3917
	N, N, N, N, N, N, N, N,
	/* 0x40 - 0x4F */
3918
	X16(D(DstReg | SrcMem | ModRM)),
3919 3920 3921
	/* 0x50 - 0x5F */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0x60 - 0x6F */
3922 3923 3924 3925
	N, N, N, N,
	N, N, N, N,
	N, N, N, N,
	N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
3926
	/* 0x70 - 0x7F */
3927 3928 3929 3930
	N, N, N, N,
	N, N, N, N,
	N, N, N, N,
	N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
3931 3932 3933
	/* 0x80 - 0x8F */
	X16(D(SrcImm)),
	/* 0x90 - 0x9F */
3934
	X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
3935
	/* 0xA0 - 0xA7 */
3936
	I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
3937 3938
	II(ImplicitOps, em_cpuid, cpuid),
	F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
3939 3940
	F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
	F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
3941
	/* 0xA8 - 0xAF */
3942
	I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
3943
	DI(ImplicitOps, rsm),
3944
	F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
3945 3946
	F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
	F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
3947
	D(ModRM), F(DstReg | SrcMem | ModRM, em_imul),
3948
	/* 0xB0 - 0xB7 */
3949
	I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_cmpxchg),
3950
	I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
3951
	F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
3952 3953
	I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
	I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
3954
	D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3955 3956
	/* 0xB8 - 0xBF */
	N, N,
3957
	G(BitOp, group8),
3958 3959
	F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
	F(DstReg | SrcMem | ModRM, em_bsf), F(DstReg | SrcMem | ModRM, em_bsr),
3960
	D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
A
Avi Kivity 已提交
3961
	/* 0xC0 - 0xC7 */
3962
	F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
3963
	N, D(DstMem | SrcReg | ModRM | Mov),
3964
	N, N, N, GD(0, &group9),
A
Avi Kivity 已提交
3965 3966
	/* 0xC8 - 0xCF */
	X8(I(DstReg, em_bswap)),
3967 3968 3969 3970 3971 3972 3973 3974
	/* 0xD0 - 0xDF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xEF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0xF0 - 0xFF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
};

3975
static const struct gprefix three_byte_0f_38_f0 = {
B
Borislav Petkov 已提交
3976
	I(DstReg | SrcMem | Mov, em_movbe), N, N, N
3977 3978 3979
};

static const struct gprefix three_byte_0f_38_f1 = {
B
Borislav Petkov 已提交
3980
	I(DstMem | SrcReg | Mov, em_movbe), N, N, N
3981 3982 3983 3984 3985 3986 3987 3988 3989
};

/*
 * Insns below are selected by the prefix which indexed by the third opcode
 * byte.
 */
static const struct opcode opcode_map_0f_38[256] = {
	/* 0x00 - 0x7f */
	X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
B
Borislav Petkov 已提交
3990 3991 3992 3993 3994 3995 3996
	/* 0x80 - 0xef */
	X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
	/* 0xf0 - 0xf1 */
	GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f0),
	GP(EmulateOnUD | ModRM | Prefix, &three_byte_0f_38_f1),
	/* 0xf2 - 0xff */
	N, N, X4(N), X8(N)
3997 3998
};

3999 4000 4001 4002 4003
#undef D
#undef N
#undef G
#undef GD
#undef I
4004
#undef GP
4005
#undef EXT
4006

4007
#undef D2bv
4008
#undef D2bvIP
4009
#undef I2bv
4010
#undef I2bvIP
4011
#undef I6ALU
4012

4013
static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
4014 4015 4016
{
	unsigned size;

4017
	size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029
	if (size == 8)
		size = 4;
	return size;
}

static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
		      unsigned size, bool sign_extension)
{
	int rc = X86EMUL_CONTINUE;

	op->type = OP_IMM;
	op->bytes = size;
4030
	op->addr.mem.ea = ctxt->_eip;
4031 4032 4033
	/* NB. Immediates are sign-extended as necessary. */
	switch (op->bytes) {
	case 1:
4034
		op->val = insn_fetch(s8, ctxt);
4035 4036
		break;
	case 2:
4037
		op->val = insn_fetch(s16, ctxt);
4038 4039
		break;
	case 4:
4040
		op->val = insn_fetch(s32, ctxt);
4041
		break;
4042 4043 4044
	case 8:
		op->val = insn_fetch(s64, ctxt);
		break;
4045 4046 4047 4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062
	}
	if (!sign_extension) {
		switch (op->bytes) {
		case 1:
			op->val &= 0xff;
			break;
		case 2:
			op->val &= 0xffff;
			break;
		case 4:
			op->val &= 0xffffffff;
			break;
		}
	}
done:
	return rc;
}

4063 4064 4065 4066 4067 4068 4069
static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
			  unsigned d)
{
	int rc = X86EMUL_CONTINUE;

	switch (d) {
	case OpReg:
4070
		decode_register_operand(ctxt, op);
4071 4072
		break;
	case OpImmUByte:
4073
		rc = decode_imm(ctxt, op, 1, false);
4074 4075
		break;
	case OpMem:
4076
		ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4077 4078 4079
	mem_common:
		*op = ctxt->memop;
		ctxt->memopp = op;
4080
		if (ctxt->d & BitOp)
4081 4082 4083
			fetch_bit_operand(ctxt);
		op->orig_val = op->val;
		break;
4084
	case OpMem64:
4085
		ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
4086
		goto mem_common;
4087 4088 4089
	case OpAcc:
		op->type = OP_REG;
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4090
		op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4091 4092 4093
		fetch_register_operand(op);
		op->orig_val = op->val;
		break;
4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111
	case OpAccLo:
		op->type = OP_REG;
		op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
		op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
		fetch_register_operand(op);
		op->orig_val = op->val;
		break;
	case OpAccHi:
		if (ctxt->d & ByteOp) {
			op->type = OP_NONE;
			break;
		}
		op->type = OP_REG;
		op->bytes = ctxt->op_bytes;
		op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
		fetch_register_operand(op);
		op->orig_val = op->val;
		break;
4112 4113 4114 4115
	case OpDI:
		op->type = OP_MEM;
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		op->addr.mem.ea =
4116
			register_address(ctxt, reg_read(ctxt, VCPU_REGS_RDI));
4117 4118
		op->addr.mem.seg = VCPU_SREG_ES;
		op->val = 0;
4119
		op->count = 1;
4120 4121 4122 4123
		break;
	case OpDX:
		op->type = OP_REG;
		op->bytes = 2;
4124
		op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4125 4126
		fetch_register_operand(op);
		break;
4127 4128
	case OpCL:
		op->bytes = 1;
4129
		op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4130 4131 4132 4133 4134 4135 4136 4137 4138 4139 4140
		break;
	case OpImmByte:
		rc = decode_imm(ctxt, op, 1, true);
		break;
	case OpOne:
		op->bytes = 1;
		op->val = 1;
		break;
	case OpImm:
		rc = decode_imm(ctxt, op, imm_size(ctxt), true);
		break;
4141 4142 4143
	case OpImm64:
		rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
		break;
4144 4145
	case OpMem8:
		ctxt->memop.bytes = 1;
4146
		if (ctxt->memop.type == OP_REG) {
4147 4148
			ctxt->memop.addr.reg = decode_register(ctxt,
					ctxt->modrm_rm, true);
4149 4150
			fetch_register_operand(&ctxt->memop);
		}
4151
		goto mem_common;
4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162 4163 4164 4165 4166 4167
	case OpMem16:
		ctxt->memop.bytes = 2;
		goto mem_common;
	case OpMem32:
		ctxt->memop.bytes = 4;
		goto mem_common;
	case OpImmU16:
		rc = decode_imm(ctxt, op, 2, false);
		break;
	case OpImmU:
		rc = decode_imm(ctxt, op, imm_size(ctxt), false);
		break;
	case OpSI:
		op->type = OP_MEM;
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		op->addr.mem.ea =
4168
			register_address(ctxt, reg_read(ctxt, VCPU_REGS_RSI));
B
Bandan Das 已提交
4169
		op->addr.mem.seg = ctxt->seg_override;
4170
		op->val = 0;
4171
		op->count = 1;
4172
		break;
P
Paolo Bonzini 已提交
4173 4174 4175 4176 4177 4178 4179
	case OpXLat:
		op->type = OP_MEM;
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		op->addr.mem.ea =
			register_address(ctxt,
				reg_read(ctxt, VCPU_REGS_RBX) +
				(reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
B
Bandan Das 已提交
4180
		op->addr.mem.seg = ctxt->seg_override;
P
Paolo Bonzini 已提交
4181 4182
		op->val = 0;
		break;
4183 4184 4185 4186 4187 4188 4189 4190 4191
	case OpImmFAddr:
		op->type = OP_IMM;
		op->addr.mem.ea = ctxt->_eip;
		op->bytes = ctxt->op_bytes + 2;
		insn_fetch_arr(op->valptr, op->bytes, ctxt);
		break;
	case OpMemFAddr:
		ctxt->memop.bytes = ctxt->op_bytes + 2;
		goto mem_common;
4192 4193 4194 4195 4196 4197 4198 4199 4200 4201 4202 4203 4204 4205 4206 4207 4208 4209
	case OpES:
		op->val = VCPU_SREG_ES;
		break;
	case OpCS:
		op->val = VCPU_SREG_CS;
		break;
	case OpSS:
		op->val = VCPU_SREG_SS;
		break;
	case OpDS:
		op->val = VCPU_SREG_DS;
		break;
	case OpFS:
		op->val = VCPU_SREG_FS;
		break;
	case OpGS:
		op->val = VCPU_SREG_GS;
		break;
4210 4211 4212 4213 4214 4215 4216 4217 4218 4219 4220
	case OpImplicit:
		/* Special instructions do their own operand decoding. */
	default:
		op->type = OP_NONE; /* Disable writeback. */
		break;
	}

done:
	return rc;
}

4221
int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
4222 4223 4224
{
	int rc = X86EMUL_CONTINUE;
	int mode = ctxt->mode;
4225
	int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
4226
	bool op_prefix = false;
B
Bandan Das 已提交
4227
	bool has_seg_override = false;
4228
	struct opcode opcode;
4229

4230 4231
	ctxt->memop.type = OP_NONE;
	ctxt->memopp = NULL;
4232 4233 4234
	ctxt->_eip = ctxt->eip;
	ctxt->fetch.start = ctxt->_eip;
	ctxt->fetch.end = ctxt->fetch.start + insn_len;
B
Borislav Petkov 已提交
4235
	ctxt->opcode_len = 1;
4236
	if (insn_len > 0)
4237
		memcpy(ctxt->fetch.data, insn, insn_len);
4238
	else {
4239
		rc = do_insn_fetch_bytes(ctxt, 1);
4240 4241 4242
		if (rc != X86EMUL_CONTINUE)
			return rc;
	}
4243 4244 4245 4246 4247 4248 4249 4250 4251 4252 4253 4254 4255 4256 4257 4258 4259

	switch (mode) {
	case X86EMUL_MODE_REAL:
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
		def_op_bytes = def_ad_bytes = 2;
		break;
	case X86EMUL_MODE_PROT32:
		def_op_bytes = def_ad_bytes = 4;
		break;
#ifdef CONFIG_X86_64
	case X86EMUL_MODE_PROT64:
		def_op_bytes = 4;
		def_ad_bytes = 8;
		break;
#endif
	default:
4260
		return EMULATION_FAILED;
4261 4262
	}

4263 4264
	ctxt->op_bytes = def_op_bytes;
	ctxt->ad_bytes = def_ad_bytes;
4265 4266 4267

	/* Legacy prefixes. */
	for (;;) {
4268
		switch (ctxt->b = insn_fetch(u8, ctxt)) {
4269
		case 0x66:	/* operand-size override */
4270
			op_prefix = true;
4271
			/* switch between 2/4 bytes */
4272
			ctxt->op_bytes = def_op_bytes ^ 6;
4273 4274 4275 4276
			break;
		case 0x67:	/* address-size override */
			if (mode == X86EMUL_MODE_PROT64)
				/* switch between 4/8 bytes */
4277
				ctxt->ad_bytes = def_ad_bytes ^ 12;
4278 4279
			else
				/* switch between 2/4 bytes */
4280
				ctxt->ad_bytes = def_ad_bytes ^ 6;
4281 4282 4283 4284 4285
			break;
		case 0x26:	/* ES override */
		case 0x2e:	/* CS override */
		case 0x36:	/* SS override */
		case 0x3e:	/* DS override */
B
Bandan Das 已提交
4286 4287
			has_seg_override = true;
			ctxt->seg_override = (ctxt->b >> 3) & 3;
4288 4289 4290
			break;
		case 0x64:	/* FS override */
		case 0x65:	/* GS override */
B
Bandan Das 已提交
4291 4292
			has_seg_override = true;
			ctxt->seg_override = ctxt->b & 7;
4293 4294 4295 4296
			break;
		case 0x40 ... 0x4f: /* REX */
			if (mode != X86EMUL_MODE_PROT64)
				goto done_prefixes;
4297
			ctxt->rex_prefix = ctxt->b;
4298 4299
			continue;
		case 0xf0:	/* LOCK */
4300
			ctxt->lock_prefix = 1;
4301 4302 4303
			break;
		case 0xf2:	/* REPNE/REPNZ */
		case 0xf3:	/* REP/REPE/REPZ */
4304
			ctxt->rep_prefix = ctxt->b;
4305 4306 4307 4308 4309 4310 4311
			break;
		default:
			goto done_prefixes;
		}

		/* Any legacy prefix after a REX prefix nullifies its effect. */

4312
		ctxt->rex_prefix = 0;
4313 4314 4315 4316 4317
	}

done_prefixes:

	/* REX prefix. */
4318 4319
	if (ctxt->rex_prefix & 8)
		ctxt->op_bytes = 8;	/* REX.W */
4320 4321

	/* Opcode byte(s). */
4322
	opcode = opcode_table[ctxt->b];
4323
	/* Two-byte opcode? */
4324
	if (ctxt->b == 0x0f) {
B
Borislav Petkov 已提交
4325
		ctxt->opcode_len = 2;
4326
		ctxt->b = insn_fetch(u8, ctxt);
4327
		opcode = twobyte_table[ctxt->b];
4328 4329 4330 4331 4332 4333 4334

		/* 0F_38 opcode map */
		if (ctxt->b == 0x38) {
			ctxt->opcode_len = 3;
			ctxt->b = insn_fetch(u8, ctxt);
			opcode = opcode_map_0f_38[ctxt->b];
		}
4335
	}
4336
	ctxt->d = opcode.flags;
4337

4338 4339 4340
	if (ctxt->d & ModRM)
		ctxt->modrm = insn_fetch(u8, ctxt);

4341 4342 4343 4344 4345 4346 4347
	/* vex-prefix instructions are not implemented */
	if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
	    (mode == X86EMUL_MODE_PROT64 ||
	    (mode >= X86EMUL_MODE_PROT16 && (ctxt->modrm & 0x80)))) {
		ctxt->d = NotImpl;
	}

4348 4349
	while (ctxt->d & GroupMask) {
		switch (ctxt->d & GroupMask) {
4350
		case Group:
4351
			goffset = (ctxt->modrm >> 3) & 7;
4352 4353 4354
			opcode = opcode.u.group[goffset];
			break;
		case GroupDual:
4355 4356
			goffset = (ctxt->modrm >> 3) & 7;
			if ((ctxt->modrm >> 6) == 3)
4357 4358 4359 4360 4361
				opcode = opcode.u.gdual->mod3[goffset];
			else
				opcode = opcode.u.gdual->mod012[goffset];
			break;
		case RMExt:
4362
			goffset = ctxt->modrm & 7;
4363
			opcode = opcode.u.group[goffset];
4364 4365
			break;
		case Prefix:
4366
			if (ctxt->rep_prefix && op_prefix)
4367
				return EMULATION_FAILED;
4368
			simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
4369 4370 4371 4372 4373 4374 4375
			switch (simd_prefix) {
			case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
			case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
			case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
			case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
			}
			break;
4376 4377 4378 4379 4380 4381
		case Escape:
			if (ctxt->modrm > 0xbf)
				opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
			else
				opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
			break;
4382
		default:
4383
			return EMULATION_FAILED;
4384
		}
4385

4386
		ctxt->d &= ~(u64)GroupMask;
4387
		ctxt->d |= opcode.flags;
4388 4389
	}

4390 4391 4392 4393
	/* Unrecognised? */
	if (ctxt->d == 0)
		return EMULATION_FAILED;

4394
	ctxt->execute = opcode.u.execute;
4395

4396 4397 4398 4399 4400 4401 4402 4403
	if (unlikely(ctxt->d &
		     (NotImpl|EmulateOnUD|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm))) {
		/*
		 * These are copied unconditionally here, and checked unconditionally
		 * in x86_emulate_insn.
		 */
		ctxt->check_perm = opcode.check_perm;
		ctxt->intercept = opcode.intercept;
4404

4405 4406
		if (ctxt->d & NotImpl)
			return EMULATION_FAILED;
4407

4408 4409
		if (!(ctxt->d & EmulateOnUD) && ctxt->ud)
			return EMULATION_FAILED;
4410

4411
		if (mode == X86EMUL_MODE_PROT64 && (ctxt->d & Stack))
4412
			ctxt->op_bytes = 8;
4413

4414 4415 4416 4417 4418 4419 4420 4421 4422 4423 4424 4425
		if (ctxt->d & Op3264) {
			if (mode == X86EMUL_MODE_PROT64)
				ctxt->op_bytes = 8;
			else
				ctxt->op_bytes = 4;
		}

		if (ctxt->d & Sse)
			ctxt->op_bytes = 16;
		else if (ctxt->d & Mmx)
			ctxt->op_bytes = 8;
	}
A
Avi Kivity 已提交
4426

4427
	/* ModRM and SIB bytes. */
4428
	if (ctxt->d & ModRM) {
4429
		rc = decode_modrm(ctxt, &ctxt->memop);
B
Bandan Das 已提交
4430 4431 4432 4433
		if (!has_seg_override) {
			has_seg_override = true;
			ctxt->seg_override = ctxt->modrm_seg;
		}
4434
	} else if (ctxt->d & MemAbs)
4435
		rc = decode_abs(ctxt, &ctxt->memop);
4436 4437 4438
	if (rc != X86EMUL_CONTINUE)
		goto done;

B
Bandan Das 已提交
4439 4440
	if (!has_seg_override)
		ctxt->seg_override = VCPU_SREG_DS;
4441

B
Bandan Das 已提交
4442
	ctxt->memop.addr.mem.seg = ctxt->seg_override;
4443 4444 4445 4446 4447

	/*
	 * Decode and fetch the source operand: register, memory
	 * or immediate.
	 */
4448
	rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
4449 4450 4451
	if (rc != X86EMUL_CONTINUE)
		goto done;

4452 4453 4454 4455
	/*
	 * Decode and fetch the second source operand: register, memory
	 * or immediate.
	 */
4456
	rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
4457 4458 4459
	if (rc != X86EMUL_CONTINUE)
		goto done;

4460
	/* Decode and fetch the destination operand: register or memory. */
4461
	rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
4462 4463

done:
4464
	if (ctxt->rip_relative)
4465
		ctxt->memopp->addr.mem.ea += ctxt->_eip;
4466

4467
	return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
4468 4469
}

4470 4471 4472 4473 4474
bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
{
	return ctxt->d & PageTable;
}

4475 4476 4477 4478 4479 4480 4481 4482 4483
static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
{
	/* The second termination condition only applies for REPE
	 * and REPNE. Test if the repeat string operation prefix is
	 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
	 * corresponding termination condition according to:
	 * 	- if REPE/REPZ and ZF = 0 then done
	 * 	- if REPNE/REPNZ and ZF = 1 then done
	 */
4484 4485 4486
	if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
	     (ctxt->b == 0xae) || (ctxt->b == 0xaf))
	    && (((ctxt->rep_prefix == REPE_PREFIX) &&
4487
		 ((ctxt->eflags & EFLG_ZF) == 0))
4488
		|| ((ctxt->rep_prefix == REPNE_PREFIX) &&
4489 4490 4491 4492 4493 4494
		    ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
		return true;

	return false;
}

A
Avi Kivity 已提交
4495 4496 4497 4498 4499 4500 4501 4502 4503 4504 4505 4506 4507
static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
{
	bool fault = false;

	ctxt->ops->get_fpu(ctxt);
	asm volatile("1: fwait \n\t"
		     "2: \n\t"
		     ".pushsection .fixup,\"ax\" \n\t"
		     "3: \n\t"
		     "movb $1, %[fault] \n\t"
		     "jmp 2b \n\t"
		     ".popsection \n\t"
		     _ASM_EXTABLE(1b, 3b)
4508
		     : [fault]"+qm"(fault));
A
Avi Kivity 已提交
4509 4510 4511 4512 4513 4514 4515 4516 4517 4518 4519 4520 4521 4522 4523
	ctxt->ops->put_fpu(ctxt);

	if (unlikely(fault))
		return emulate_exception(ctxt, MF_VECTOR, 0, false);

	return X86EMUL_CONTINUE;
}

static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
				       struct operand *op)
{
	if (op->type == OP_MM)
		read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
}

4524 4525 4526
static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
{
	ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
4527 4528
	if (!(ctxt->d & ByteOp))
		fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
4529
	asm("push %[flags]; popf; call *%[fastop]; pushf; pop %[flags]\n"
4530 4531 4532
	    : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
	      [fastop]"+S"(fop)
	    : "c"(ctxt->src2.val));
4533
	ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
4534 4535
	if (!fop) /* exception is returned in fop variable */
		return emulate_de(ctxt);
4536 4537
	return X86EMUL_CONTINUE;
}
4538

4539 4540
void init_decode_cache(struct x86_emulate_ctxt *ctxt)
{
B
Bandan Das 已提交
4541 4542
	memset(&ctxt->rip_relative, 0,
	       (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
4543 4544 4545 4546 4547 4548

	ctxt->io_read.pos = 0;
	ctxt->io_read.end = 0;
	ctxt->mem_read.end = 0;
}

4549
int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
4550
{
4551
	const struct x86_emulate_ops *ops = ctxt->ops;
4552
	int rc = X86EMUL_CONTINUE;
4553
	int saved_dst_type = ctxt->dst.type;
4554

4555
	ctxt->mem_read.pos = 0;
4556

4557 4558
	/* LOCK prefix is allowed only with some instructions */
	if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
4559
		rc = emulate_ud(ctxt);
4560 4561 4562
		goto done;
	}

4563
	if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
4564
		rc = emulate_ud(ctxt);
4565 4566 4567
		goto done;
	}

4568 4569 4570 4571 4572 4573 4574
	if (unlikely(ctxt->d &
		     (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
		if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
				(ctxt->d & Undefined)) {
			rc = emulate_ud(ctxt);
			goto done;
		}
A
Avi Kivity 已提交
4575

4576 4577 4578
		if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
		    || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
			rc = emulate_ud(ctxt);
A
Avi Kivity 已提交
4579
			goto done;
4580
		}
A
Avi Kivity 已提交
4581

4582 4583
		if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
			rc = emulate_nm(ctxt);
4584
			goto done;
4585
		}
4586

4587 4588 4589 4590 4591 4592 4593 4594 4595 4596 4597 4598 4599
		if (ctxt->d & Mmx) {
			rc = flush_pending_x87_faults(ctxt);
			if (rc != X86EMUL_CONTINUE)
				goto done;
			/*
			 * Now that we know the fpu is exception safe, we can fetch
			 * operands from it.
			 */
			fetch_possible_mmx_operand(ctxt, &ctxt->src);
			fetch_possible_mmx_operand(ctxt, &ctxt->src2);
			if (!(ctxt->d & Mov))
				fetch_possible_mmx_operand(ctxt, &ctxt->dst);
		}
4600

4601
		if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
4602 4603 4604 4605 4606
			rc = emulator_check_intercept(ctxt, ctxt->intercept,
						      X86_ICPT_PRE_EXCEPT);
			if (rc != X86EMUL_CONTINUE)
				goto done;
		}
4607

4608 4609 4610
		/* Privileged instruction can be executed only in CPL=0 */
		if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
			rc = emulate_gp(ctxt, 0);
4611
			goto done;
4612
		}
4613

4614 4615 4616
		/* Instruction can only be executed in protected mode */
		if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
			rc = emulate_ud(ctxt);
4617
			goto done;
4618
		}
4619

4620
		/* Do instruction specific permission checks */
4621
		if (ctxt->d & CheckPerm) {
4622 4623 4624 4625 4626
			rc = ctxt->check_perm(ctxt);
			if (rc != X86EMUL_CONTINUE)
				goto done;
		}

4627
		if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
4628 4629 4630 4631 4632 4633 4634 4635 4636 4637 4638 4639
			rc = emulator_check_intercept(ctxt, ctxt->intercept,
						      X86_ICPT_POST_EXCEPT);
			if (rc != X86EMUL_CONTINUE)
				goto done;
		}

		if (ctxt->rep_prefix && (ctxt->d & String)) {
			/* All REP prefixes have the same first termination condition */
			if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
				ctxt->eip = ctxt->_eip;
				goto done;
			}
4640 4641 4642
		}
	}

4643 4644 4645
	if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
		rc = segmented_read(ctxt, ctxt->src.addr.mem,
				    ctxt->src.valptr, ctxt->src.bytes);
4646
		if (rc != X86EMUL_CONTINUE)
4647
			goto done;
4648
		ctxt->src.orig_val64 = ctxt->src.val64;
4649 4650
	}

4651 4652 4653
	if (ctxt->src2.type == OP_MEM) {
		rc = segmented_read(ctxt, ctxt->src2.addr.mem,
				    &ctxt->src2.val, ctxt->src2.bytes);
4654 4655 4656 4657
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

4658
	if ((ctxt->d & DstMask) == ImplicitOps)
4659 4660 4661
		goto special_insn;


4662
	if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
4663
		/* optimisation - avoid slow emulated read if Mov */
4664 4665
		rc = segmented_read(ctxt, ctxt->dst.addr.mem,
				   &ctxt->dst.val, ctxt->dst.bytes);
4666 4667
		if (rc != X86EMUL_CONTINUE)
			goto done;
4668
	}
4669
	ctxt->dst.orig_val = ctxt->dst.val;
4670

4671 4672
special_insn:

4673
	if (unlikely(ctxt->guest_mode) && (ctxt->d & Intercept)) {
4674
		rc = emulator_check_intercept(ctxt, ctxt->intercept,
4675
					      X86_ICPT_POST_MEMACCESS);
4676 4677 4678 4679
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

4680
	if (ctxt->execute) {
4681 4682 4683 4684 4685 4686 4687
		if (ctxt->d & Fastop) {
			void (*fop)(struct fastop *) = (void *)ctxt->execute;
			rc = fastop(ctxt, fop);
			if (rc != X86EMUL_CONTINUE)
				goto done;
			goto writeback;
		}
4688
		rc = ctxt->execute(ctxt);
4689 4690 4691 4692 4693
		if (rc != X86EMUL_CONTINUE)
			goto done;
		goto writeback;
	}

B
Borislav Petkov 已提交
4694
	if (ctxt->opcode_len == 2)
A
Avi Kivity 已提交
4695
		goto twobyte_insn;
4696 4697
	else if (ctxt->opcode_len == 3)
		goto threebyte_insn;
A
Avi Kivity 已提交
4698

4699
	switch (ctxt->b) {
A
Avi Kivity 已提交
4700
	case 0x63:		/* movsxd */
4701
		if (ctxt->mode != X86EMUL_MODE_PROT64)
A
Avi Kivity 已提交
4702
			goto cannot_emulate;
4703
		ctxt->dst.val = (s32) ctxt->src.val;
A
Avi Kivity 已提交
4704
		break;
4705
	case 0x70 ... 0x7f: /* jcc (short) */
4706 4707
		if (test_cc(ctxt->b, ctxt->eflags))
			jmp_rel(ctxt, ctxt->src.val);
4708
		break;
N
Nitin A Kamble 已提交
4709
	case 0x8d: /* lea r16/r32, m */
4710
		ctxt->dst.val = ctxt->src.addr.mem.ea;
N
Nitin A Kamble 已提交
4711
		break;
4712
	case 0x90 ... 0x97: /* nop / xchg reg, rax */
4713
		if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
4714 4715 4716
			ctxt->dst.type = OP_NONE;
		else
			rc = em_xchg(ctxt);
4717
		break;
4718
	case 0x98: /* cbw/cwde/cdqe */
4719 4720 4721 4722
		switch (ctxt->op_bytes) {
		case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
		case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
		case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
4723 4724
		}
		break;
4725
	case 0xcc:		/* int3 */
4726 4727
		rc = emulate_int(ctxt, 3);
		break;
4728
	case 0xcd:		/* int n */
4729
		rc = emulate_int(ctxt, ctxt->src.val);
4730 4731
		break;
	case 0xce:		/* into */
4732 4733
		if (ctxt->eflags & EFLG_OF)
			rc = emulate_int(ctxt, 4);
4734
		break;
4735
	case 0xe9: /* jmp rel */
4736
	case 0xeb: /* jmp rel short */
4737 4738
		jmp_rel(ctxt, ctxt->src.val);
		ctxt->dst.type = OP_NONE; /* Disable writeback. */
4739
		break;
4740
	case 0xf4:              /* hlt */
4741
		ctxt->ops->halt(ctxt);
4742
		break;
4743 4744 4745 4746 4747 4748 4749
	case 0xf5:	/* cmc */
		/* complement carry flag from eflags reg */
		ctxt->eflags ^= EFLG_CF;
		break;
	case 0xf8: /* clc */
		ctxt->eflags &= ~EFLG_CF;
		break;
4750 4751 4752
	case 0xf9: /* stc */
		ctxt->eflags |= EFLG_CF;
		break;
4753 4754 4755 4756 4757 4758
	case 0xfc: /* cld */
		ctxt->eflags &= ~EFLG_DF;
		break;
	case 0xfd: /* std */
		ctxt->eflags |= EFLG_DF;
		break;
4759 4760
	default:
		goto cannot_emulate;
A
Avi Kivity 已提交
4761
	}
4762

4763 4764 4765
	if (rc != X86EMUL_CONTINUE)
		goto done;

4766
writeback:
4767 4768 4769 4770 4771 4772
	if (ctxt->d & SrcWrite) {
		BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
		rc = writeback(ctxt, &ctxt->src);
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}
4773 4774 4775 4776 4777
	if (!(ctxt->d & NoWrite)) {
		rc = writeback(ctxt, &ctxt->dst);
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}
4778

4779 4780 4781 4782
	/*
	 * restore dst type in case the decoding will be reused
	 * (happens for string instruction )
	 */
4783
	ctxt->dst.type = saved_dst_type;
4784

4785
	if ((ctxt->d & SrcMask) == SrcSI)
4786
		string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
4787

4788
	if ((ctxt->d & DstMask) == DstDI)
4789
		string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
4790

4791
	if (ctxt->rep_prefix && (ctxt->d & String)) {
4792
		unsigned int count;
4793
		struct read_cache *r = &ctxt->io_read;
4794 4795 4796 4797 4798 4799
		if ((ctxt->d & SrcMask) == SrcSI)
			count = ctxt->src.count;
		else
			count = ctxt->dst.count;
		register_address_increment(ctxt, reg_rmw(ctxt, VCPU_REGS_RCX),
				-count);
4800

4801 4802 4803 4804 4805
		if (!string_insn_completed(ctxt)) {
			/*
			 * Re-enter guest when pio read ahead buffer is empty
			 * or, if it is not used, after each 1024 iteration.
			 */
4806
			if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
4807 4808 4809 4810 4811 4812
			    (r->end == 0 || r->end != r->pos)) {
				/*
				 * Reset read cache. Usually happens before
				 * decode, but since instruction is restarted
				 * we have to do it here.
				 */
4813
				ctxt->mem_read.end = 0;
4814
				writeback_registers(ctxt);
4815 4816 4817
				return EMULATION_RESTART;
			}
			goto done; /* skip rip writeback */
4818
		}
4819
	}
4820

4821
	ctxt->eip = ctxt->_eip;
4822 4823

done:
4824 4825
	if (rc == X86EMUL_PROPAGATE_FAULT)
		ctxt->have_exception = true;
4826 4827 4828
	if (rc == X86EMUL_INTERCEPTED)
		return EMULATION_INTERCEPTED;

4829 4830 4831
	if (rc == X86EMUL_CONTINUE)
		writeback_registers(ctxt);

4832
	return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
A
Avi Kivity 已提交
4833 4834

twobyte_insn:
4835
	switch (ctxt->b) {
4836
	case 0x09:		/* wbinvd */
4837
		(ctxt->ops->wbinvd)(ctxt);
4838 4839
		break;
	case 0x08:		/* invd */
4840 4841
	case 0x0d:		/* GrpP (prefetch) */
	case 0x18:		/* Grp16 (prefetch/nop) */
P
Paolo Bonzini 已提交
4842
	case 0x1f:		/* nop */
4843 4844
		break;
	case 0x20: /* mov cr, reg */
4845
		ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
4846
		break;
A
Avi Kivity 已提交
4847
	case 0x21: /* mov from dr to reg */
4848
		ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
A
Avi Kivity 已提交
4849 4850
		break;
	case 0x40 ... 0x4f:	/* cmov */
4851 4852 4853 4854
		if (test_cc(ctxt->b, ctxt->eflags))
			ctxt->dst.val = ctxt->src.val;
		else if (ctxt->mode != X86EMUL_MODE_PROT64 ||
			 ctxt->op_bytes != 4)
4855
			ctxt->dst.type = OP_NONE; /* no writeback */
A
Avi Kivity 已提交
4856
		break;
4857
	case 0x80 ... 0x8f: /* jnz rel, etc*/
4858 4859
		if (test_cc(ctxt->b, ctxt->eflags))
			jmp_rel(ctxt, ctxt->src.val);
4860
		break;
4861
	case 0x90 ... 0x9f:     /* setcc r/m8 */
4862
		ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
4863
		break;
4864 4865
	case 0xae:              /* clflush */
		break;
A
Avi Kivity 已提交
4866
	case 0xb6 ... 0xb7:	/* movzx */
4867
		ctxt->dst.bytes = ctxt->op_bytes;
4868
		ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
4869
						       : (u16) ctxt->src.val;
A
Avi Kivity 已提交
4870 4871
		break;
	case 0xbe ... 0xbf:	/* movsx */
4872
		ctxt->dst.bytes = ctxt->op_bytes;
4873
		ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
4874
							(s16) ctxt->src.val;
A
Avi Kivity 已提交
4875
		break;
4876
	case 0xc3:		/* movnti */
4877
		ctxt->dst.bytes = ctxt->op_bytes;
4878 4879
		ctxt->dst.val = (ctxt->op_bytes == 8) ? (u64) ctxt->src.val :
							(u32) ctxt->src.val;
4880
		break;
4881 4882
	default:
		goto cannot_emulate;
A
Avi Kivity 已提交
4883
	}
4884

4885 4886
threebyte_insn:

4887 4888 4889
	if (rc != X86EMUL_CONTINUE)
		goto done;

A
Avi Kivity 已提交
4890 4891 4892
	goto writeback;

cannot_emulate:
4893
	return EMULATION_FAILED;
A
Avi Kivity 已提交
4894
}
4895 4896 4897 4898 4899 4900 4901 4902 4903 4904

void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
{
	invalidate_registers(ctxt);
}

void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
{
	writeback_registers(ctxt);
}