emulate.c 111.4 KB
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/******************************************************************************
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 * emulate.c
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 *
 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
 *
 * Copyright (c) 2005 Keir Fraser
 *
 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
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 * privileged instructions:
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 *
 * Copyright (C) 2006 Qumranet
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 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
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 *
 *   Avi Kivity <avi@qumranet.com>
 *   Yaniv Kamay <yaniv@qumranet.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
 */

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#include <linux/kvm_host.h>
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#include "kvm_cache_regs.h"
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#include <linux/module.h>
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#include <asm/kvm_emulate.h>
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#include "x86.h"
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#include "tss.h"
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/*
 * Opcode effective-address decode tables.
 * Note that we only emulate instructions that have at least one memory
 * operand (excluding implicit stack references). We assume that stack
 * references and instruction fetches will never occur in special memory
 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
 * not be handled.
 */

/* Operand sizes: 8-bit operands or specified/overridden size. */
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#define ByteOp      (1<<0)	/* 8-bit operands. */
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/* Destination operand type. */
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#define ImplicitOps (1<<1)	/* Implicit in opcode. No generic decode. */
#define DstReg      (2<<1)	/* Register operand. */
#define DstMem      (3<<1)	/* Memory operand. */
#define DstAcc      (4<<1)	/* Destination Accumulator */
#define DstDI       (5<<1)	/* Destination is in ES:(E)DI */
#define DstMem64    (6<<1)	/* 64bit memory operand */
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#define DstImmUByte (7<<1)	/* 8-bit unsigned immediate operand */
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#define DstMask     (7<<1)
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/* Source operand type. */
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#define SrcNone     (0<<4)	/* No source operand. */
#define SrcReg      (1<<4)	/* Register operand. */
#define SrcMem      (2<<4)	/* Memory operand. */
#define SrcMem16    (3<<4)	/* Memory operand (16-bit). */
#define SrcMem32    (4<<4)	/* Memory operand (32-bit). */
#define SrcImm      (5<<4)	/* Immediate operand. */
#define SrcImmByte  (6<<4)	/* 8-bit sign-extended immediate operand. */
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#define SrcOne      (7<<4)	/* Implied '1' */
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#define SrcImmUByte (8<<4)      /* 8-bit unsigned immediate operand. */
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#define SrcImmU     (9<<4)      /* Immediate operand, unsigned */
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#define SrcSI       (0xa<<4)	/* Source is in the DS:RSI */
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#define SrcImmFAddr (0xb<<4)	/* Source is immediate far address */
#define SrcMemFAddr (0xc<<4)	/* Source is far address in memory */
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#define SrcAcc      (0xd<<4)	/* Source Accumulator */
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#define SrcImmU16   (0xe<<4)    /* Immediate operand, unsigned, 16 bits */
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#define SrcMask     (0xf<<4)
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/* Generic ModRM decode. */
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#define ModRM       (1<<8)
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/* Destination is only written; never read. */
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#define Mov         (1<<9)
#define BitOp       (1<<10)
#define MemAbs      (1<<11)      /* Memory operand is absolute displacement */
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#define String      (1<<12)     /* String instruction (rep capable) */
#define Stack       (1<<13)     /* Stack instruction (push/pop) */
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#define GroupMask   (7<<14)     /* Opcode uses one of the group mechanisms */
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#define Group       (1<<14)     /* Bits 3:5 of modrm byte extend opcode */
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#define GroupDual   (2<<14)     /* Alternate decoding of mod == 3 */
#define Prefix      (3<<14)     /* Instruction varies with 66/f2/f3 prefix */
#define RMExt       (4<<14)     /* Opcode extension in ModRM r/m if mod == 3 */
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#define Sse         (1<<17)     /* SSE Vector instruction */
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/* Misc flags */
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#define Prot        (1<<21) /* instruction generates #UD if not in prot-mode */
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#define VendorSpecific (1<<22) /* Vendor specific instruction */
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#define NoAccess    (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
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#define Op3264      (1<<24) /* Operand is 64b in long mode, 32b otherwise */
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#define Undefined   (1<<25) /* No Such Instruction */
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#define Lock        (1<<26) /* lock prefix is allowed for the instruction */
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#define Priv        (1<<27) /* instruction generates #GP if current CPL != 0 */
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#define No64	    (1<<28)
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/* Source 2 operand type */
#define Src2None    (0<<29)
#define Src2CL      (1<<29)
#define Src2ImmByte (2<<29)
#define Src2One     (3<<29)
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#define Src2Imm     (4<<29)
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#define Src2Mask    (7<<29)
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#define X2(x...) x, x
#define X3(x...) X2(x), x
#define X4(x...) X2(x), X2(x)
#define X5(x...) X4(x), x
#define X6(x...) X4(x), X2(x)
#define X7(x...) X4(x), X3(x)
#define X8(x...) X4(x), X4(x)
#define X16(x...) X8(x), X8(x)
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struct opcode {
	u32 flags;
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	u8 intercept;
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	union {
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		int (*execute)(struct x86_emulate_ctxt *ctxt);
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		struct opcode *group;
		struct group_dual *gdual;
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		struct gprefix *gprefix;
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	} u;
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	int (*check_perm)(struct x86_emulate_ctxt *ctxt);
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};

struct group_dual {
	struct opcode mod012[8];
	struct opcode mod3[8];
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};

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struct gprefix {
	struct opcode pfx_no;
	struct opcode pfx_66;
	struct opcode pfx_f2;
	struct opcode pfx_f3;
};

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/* EFLAGS bit definitions. */
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#define EFLG_ID (1<<21)
#define EFLG_VIP (1<<20)
#define EFLG_VIF (1<<19)
#define EFLG_AC (1<<18)
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#define EFLG_VM (1<<17)
#define EFLG_RF (1<<16)
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#define EFLG_IOPL (3<<12)
#define EFLG_NT (1<<14)
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#define EFLG_OF (1<<11)
#define EFLG_DF (1<<10)
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#define EFLG_IF (1<<9)
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#define EFLG_TF (1<<8)
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#define EFLG_SF (1<<7)
#define EFLG_ZF (1<<6)
#define EFLG_AF (1<<4)
#define EFLG_PF (1<<2)
#define EFLG_CF (1<<0)

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#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
#define EFLG_RESERVED_ONE_MASK 2

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/*
 * Instruction emulation:
 * Most instructions are emulated directly via a fragment of inline assembly
 * code. This allows us to save/restore EFLAGS and thus very easily pick up
 * any modified flags.
 */

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#if defined(CONFIG_X86_64)
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#define _LO32 "k"		/* force 32-bit operand */
#define _STK  "%%rsp"		/* stack pointer */
#elif defined(__i386__)
#define _LO32 ""		/* force 32-bit operand */
#define _STK  "%%esp"		/* stack pointer */
#endif

/*
 * These EFLAGS bits are restored from saved value during emulation, and
 * any changes are written back to the saved value after emulation.
 */
#define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)

/* Before executing instruction: restore necessary bits in EFLAGS. */
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#define _PRE_EFLAGS(_sav, _msk, _tmp)					\
	/* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
	"movl %"_sav",%"_LO32 _tmp"; "                                  \
	"push %"_tmp"; "                                                \
	"push %"_tmp"; "                                                \
	"movl %"_msk",%"_LO32 _tmp"; "                                  \
	"andl %"_LO32 _tmp",("_STK"); "                                 \
	"pushf; "                                                       \
	"notl %"_LO32 _tmp"; "                                          \
	"andl %"_LO32 _tmp",("_STK"); "                                 \
	"andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); "	\
	"pop  %"_tmp"; "                                                \
	"orl  %"_LO32 _tmp",("_STK"); "                                 \
	"popf; "                                                        \
	"pop  %"_sav"; "
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/* After executing instruction: write-back necessary bits in EFLAGS. */
#define _POST_EFLAGS(_sav, _msk, _tmp) \
	/* _sav |= EFLAGS & _msk; */		\
	"pushf; "				\
	"pop  %"_tmp"; "			\
	"andl %"_msk",%"_LO32 _tmp"; "		\
	"orl  %"_LO32 _tmp",%"_sav"; "

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#ifdef CONFIG_X86_64
#define ON64(x) x
#else
#define ON64(x)
#endif

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#define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
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	do {								\
		__asm__ __volatile__ (					\
			_PRE_EFLAGS("0", "4", "2")			\
			_op _suffix " %"_x"3,%1; "			\
			_POST_EFLAGS("0", "4", "2")			\
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			: "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
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			  "=&r" (_tmp)					\
			: _y ((_src).val), "i" (EFLAGS_MASK));		\
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	} while (0)
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/* Raw emulation: instruction has two explicit operands. */
#define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
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	do {								\
		unsigned long _tmp;					\
									\
		switch ((_dst).bytes) {					\
		case 2:							\
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			____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
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			break;						\
		case 4:							\
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			____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
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			break;						\
		case 8:							\
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			ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
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			break;						\
		}							\
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	} while (0)

#define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
	do {								     \
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		unsigned long _tmp;					     \
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		switch ((_dst).bytes) {				             \
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		case 1:							     \
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			____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
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			break;						     \
		default:						     \
			__emulate_2op_nobyte(_op, _src, _dst, _eflags,	     \
					     _wx, _wy, _lx, _ly, _qx, _qy);  \
			break;						     \
		}							     \
	} while (0)

/* Source operand is byte-sized and may be restricted to just %cl. */
#define emulate_2op_SrcB(_op, _src, _dst, _eflags)                      \
	__emulate_2op(_op, _src, _dst, _eflags,				\
		      "b", "c", "b", "c", "b", "c", "b", "c")

/* Source operand is byte, word, long or quad sized. */
#define emulate_2op_SrcV(_op, _src, _dst, _eflags)                      \
	__emulate_2op(_op, _src, _dst, _eflags,				\
		      "b", "q", "w", "r", _LO32, "r", "", "r")

/* Source operand is word, long or quad sized. */
#define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags)               \
	__emulate_2op_nobyte(_op, _src, _dst, _eflags,			\
			     "w", "r", _LO32, "r", "", "r")

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/* Instruction has three operands and one operand is stored in ECX register */
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#define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type)	\
	do {								\
		unsigned long _tmp;					\
		_type _clv  = (_cl).val;				\
		_type _srcv = (_src).val;				\
		_type _dstv = (_dst).val;				\
									\
		__asm__ __volatile__ (					\
			_PRE_EFLAGS("0", "5", "2")			\
			_op _suffix " %4,%1 \n"				\
			_POST_EFLAGS("0", "5", "2")			\
			: "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp)	\
			: "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK)	\
			);						\
									\
		(_cl).val  = (unsigned long) _clv;			\
		(_src).val = (unsigned long) _srcv;			\
		(_dst).val = (unsigned long) _dstv;			\
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	} while (0)

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#define emulate_2op_cl(_op, _cl, _src, _dst, _eflags)			\
	do {								\
		switch ((_dst).bytes) {					\
		case 2:							\
			__emulate_2op_cl(_op, _cl, _src, _dst, _eflags,	\
					 "w", unsigned short);         	\
			break;						\
		case 4:							\
			__emulate_2op_cl(_op, _cl, _src, _dst, _eflags,	\
					 "l", unsigned int);           	\
			break;						\
		case 8:							\
			ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
					      "q", unsigned long));	\
			break;						\
		}							\
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	} while (0)

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#define __emulate_1op(_op, _dst, _eflags, _suffix)			\
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	do {								\
		unsigned long _tmp;					\
									\
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		__asm__ __volatile__ (					\
			_PRE_EFLAGS("0", "3", "2")			\
			_op _suffix " %1; "				\
			_POST_EFLAGS("0", "3", "2")			\
			: "=m" (_eflags), "+m" ((_dst).val),		\
			  "=&r" (_tmp)					\
			: "i" (EFLAGS_MASK));				\
	} while (0)

/* Instruction has only one explicit operand (no source operand). */
#define emulate_1op(_op, _dst, _eflags)                                    \
	do {								\
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		switch ((_dst).bytes) {				        \
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		case 1:	__emulate_1op(_op, _dst, _eflags, "b"); break;	\
		case 2:	__emulate_1op(_op, _dst, _eflags, "w"); break;	\
		case 4:	__emulate_1op(_op, _dst, _eflags, "l"); break;	\
		case 8:	ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
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		}							\
	} while (0)

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#define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix)		\
	do {								\
		unsigned long _tmp;					\
									\
		__asm__ __volatile__ (					\
			_PRE_EFLAGS("0", "4", "1")			\
			_op _suffix " %5; "				\
			_POST_EFLAGS("0", "4", "1")			\
			: "=m" (_eflags), "=&r" (_tmp),			\
			  "+a" (_rax), "+d" (_rdx)			\
			: "i" (EFLAGS_MASK), "m" ((_src).val),		\
			  "a" (_rax), "d" (_rdx));			\
	} while (0)

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#define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
	do {								\
		unsigned long _tmp;					\
									\
		__asm__ __volatile__ (					\
			_PRE_EFLAGS("0", "5", "1")			\
			"1: \n\t"					\
			_op _suffix " %6; "				\
			"2: \n\t"					\
			_POST_EFLAGS("0", "5", "1")			\
			".pushsection .fixup,\"ax\" \n\t"		\
			"3: movb $1, %4 \n\t"				\
			"jmp 2b \n\t"					\
			".popsection \n\t"				\
			_ASM_EXTABLE(1b, 3b)				\
			: "=m" (_eflags), "=&r" (_tmp),			\
			  "+a" (_rax), "+d" (_rdx), "+qm"(_ex)		\
			: "i" (EFLAGS_MASK), "m" ((_src).val),		\
			  "a" (_rax), "d" (_rdx));			\
	} while (0)

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/* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
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#define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags)		\
	do {								\
		switch((_src).bytes) {					\
		case 1:							\
			__emulate_1op_rax_rdx(_op, _src, _rax, _rdx,	\
					      _eflags, "b");		\
			break;						\
		case 2:							\
			__emulate_1op_rax_rdx(_op, _src, _rax, _rdx,	\
					      _eflags, "w");		\
			break;						\
		case 4:							\
			__emulate_1op_rax_rdx(_op, _src, _rax, _rdx,	\
					      _eflags, "l");		\
			break;						\
		case 8:							\
			ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, \
						   _eflags, "q"));	\
			break;						\
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		}							\
	} while (0)

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#define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex)	\
	do {								\
		switch((_src).bytes) {					\
		case 1:							\
			__emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx,	\
						 _eflags, "b", _ex);	\
			break;						\
		case 2:							\
			__emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
						 _eflags, "w", _ex);	\
			break;						\
		case 4:							\
			__emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
						 _eflags, "l", _ex);	\
			break;						\
		case 8: ON64(						\
			__emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
						 _eflags, "q", _ex));	\
			break;						\
		}							\
	} while (0)

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/* Fetch next part of the instruction being emulated. */
#define insn_fetch(_type, _size, _eip)                                  \
({	unsigned long _x;						\
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	rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size));		\
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	if (rc != X86EMUL_CONTINUE)					\
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		goto done;						\
	(_eip) += (_size);						\
	(_type)_x;							\
})

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#define insn_fetch_arr(_arr, _size, _eip)				\
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({	rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size));		\
	if (rc != X86EMUL_CONTINUE)					\
		goto done;						\
	(_eip) += (_size);						\
})

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static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
				    enum x86_intercept intercept,
				    enum x86_intercept_stage stage)
{
	struct x86_instruction_info info = {
		.intercept  = intercept,
		.rep_prefix = ctxt->decode.rep_prefix,
		.modrm_mod  = ctxt->decode.modrm_mod,
		.modrm_reg  = ctxt->decode.modrm_reg,
		.modrm_rm   = ctxt->decode.modrm_rm,
		.src_val    = ctxt->decode.src.val64,
		.src_bytes  = ctxt->decode.src.bytes,
		.dst_bytes  = ctxt->decode.dst.bytes,
		.ad_bytes   = ctxt->decode.ad_bytes,
		.next_rip   = ctxt->eip,
	};

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	return ctxt->ops->intercept(ctxt, &info, stage);
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}

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static inline unsigned long ad_mask(struct decode_cache *c)
{
	return (1UL << (c->ad_bytes << 3)) - 1;
}

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/* Access/update address held in a register, based on addressing mode. */
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static inline unsigned long
address_mask(struct decode_cache *c, unsigned long reg)
{
	if (c->ad_bytes == sizeof(unsigned long))
		return reg;
	else
		return reg & ad_mask(c);
}

static inline unsigned long
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register_address(struct decode_cache *c, unsigned long reg)
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{
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	return address_mask(c, reg);
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}

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static inline void
register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
{
	if (c->ad_bytes == sizeof(unsigned long))
		*reg += inc;
	else
		*reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
}
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static inline void jmp_rel(struct decode_cache *c, int rel)
{
	register_address_increment(c, &c->eip, rel);
}
479

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static u32 desc_limit_scaled(struct desc_struct *desc)
{
	u32 limit = get_desc_limit(desc);

	return desc->g ? (limit << 12) | 0xfff : limit;
}

487 488 489 490 491 492
static void set_seg_override(struct decode_cache *c, int seg)
{
	c->has_seg_override = true;
	c->seg_override = seg;
}

493 494
static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
			      struct x86_emulate_ops *ops, int seg)
495 496 497 498
{
	if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
		return 0;

499
	return ops->get_cached_segment_base(ctxt, seg);
500 501
}

502 503
static unsigned seg_override(struct x86_emulate_ctxt *ctxt,
			     struct decode_cache *c)
504 505 506 507
{
	if (!c->has_seg_override)
		return 0;

508
	return c->seg_override;
509 510
}

511 512
static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
			     u32 error, bool valid)
513
{
514 515 516
	ctxt->exception.vector = vec;
	ctxt->exception.error_code = error;
	ctxt->exception.error_code_valid = valid;
517
	return X86EMUL_PROPAGATE_FAULT;
518 519
}

520 521 522 523 524
static int emulate_db(struct x86_emulate_ctxt *ctxt)
{
	return emulate_exception(ctxt, DB_VECTOR, 0, false);
}

525
static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
526
{
527
	return emulate_exception(ctxt, GP_VECTOR, err, true);
528 529
}

530 531 532 533 534
static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
{
	return emulate_exception(ctxt, SS_VECTOR, err, true);
}

535
static int emulate_ud(struct x86_emulate_ctxt *ctxt)
536
{
537
	return emulate_exception(ctxt, UD_VECTOR, 0, false);
538 539
}

540
static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
541
{
542
	return emulate_exception(ctxt, TS_VECTOR, err, true);
543 544
}

545 546
static int emulate_de(struct x86_emulate_ctxt *ctxt)
{
547
	return emulate_exception(ctxt, DE_VECTOR, 0, false);
548 549
}

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static int emulate_nm(struct x86_emulate_ctxt *ctxt)
{
	return emulate_exception(ctxt, NM_VECTOR, 0, false);
}

555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574
static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
{
	u16 selector;
	struct desc_struct desc;

	ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
	return selector;
}

static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
				 unsigned seg)
{
	u16 dummy;
	u32 base3;
	struct desc_struct desc;

	ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
	ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
}

575
static int __linearize(struct x86_emulate_ctxt *ctxt,
576
		     struct segmented_address addr,
577
		     unsigned size, bool write, bool fetch,
578 579 580
		     ulong *linear)
{
	struct decode_cache *c = &ctxt->decode;
581 582
	struct desc_struct desc;
	bool usable;
583
	ulong la;
584
	u32 lim;
585
	u16 sel;
586
	unsigned cpl, rpl;
587 588

	la = seg_base(ctxt, ctxt->ops, addr.seg) + addr.ea;
589 590 591 592 593 594 595 596
	switch (ctxt->mode) {
	case X86EMUL_MODE_REAL:
		break;
	case X86EMUL_MODE_PROT64:
		if (((signed long)la << 16) >> 16 != la)
			return emulate_gp(ctxt, 0);
		break;
	default:
597 598
		usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
						addr.seg);
599 600 601 602 603 604
		if (!usable)
			goto bad;
		/* code segment or read-only data segment */
		if (((desc.type & 8) || !(desc.type & 2)) && write)
			goto bad;
		/* unreadable code segment */
605
		if (!fetch && (desc.type & 8) && !(desc.type & 2))
606 607 608 609 610 611 612 613 614 615 616 617 618 619
			goto bad;
		lim = desc_limit_scaled(&desc);
		if ((desc.type & 8) || !(desc.type & 4)) {
			/* expand-up segment */
			if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
				goto bad;
		} else {
			/* exapand-down segment */
			if (addr.ea <= lim || (u32)(addr.ea + size - 1) <= lim)
				goto bad;
			lim = desc.d ? 0xffffffff : 0xffff;
			if (addr.ea > lim || (u32)(addr.ea + size - 1) > lim)
				goto bad;
		}
620
		cpl = ctxt->ops->cpl(ctxt);
621
		rpl = sel & 3;
622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637
		cpl = max(cpl, rpl);
		if (!(desc.type & 8)) {
			/* data segment */
			if (cpl > desc.dpl)
				goto bad;
		} else if ((desc.type & 8) && !(desc.type & 4)) {
			/* nonconforming code segment */
			if (cpl != desc.dpl)
				goto bad;
		} else if ((desc.type & 8) && (desc.type & 4)) {
			/* conforming code segment */
			if (cpl < desc.dpl)
				goto bad;
		}
		break;
	}
638
	if (fetch ? ctxt->mode != X86EMUL_MODE_PROT64 : c->ad_bytes != 8)
639 640 641
		la &= (u32)-1;
	*linear = la;
	return X86EMUL_CONTINUE;
642 643 644 645 646
bad:
	if (addr.seg == VCPU_SREG_SS)
		return emulate_ss(ctxt, addr.seg);
	else
		return emulate_gp(ctxt, addr.seg);
647 648
}

649 650 651 652 653 654 655 656 657
static int linearize(struct x86_emulate_ctxt *ctxt,
		     struct segmented_address addr,
		     unsigned size, bool write,
		     ulong *linear)
{
	return __linearize(ctxt, addr, size, write, false, linear);
}


658 659 660 661 662
static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
			      struct segmented_address addr,
			      void *data,
			      unsigned size)
{
663 664 665
	int rc;
	ulong linear;

666
	rc = linearize(ctxt, addr, size, false, &linear);
667 668
	if (rc != X86EMUL_CONTINUE)
		return rc;
669
	return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
670 671
}

672 673
static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
			      struct x86_emulate_ops *ops,
674
			      unsigned long eip, u8 *dest)
675 676 677
{
	struct fetch_cache *fc = &ctxt->decode.fetch;
	int rc;
678
	int size, cur_size;
679

680
	if (eip == fc->end) {
681 682
		unsigned long linear;
		struct segmented_address addr = { .seg=VCPU_SREG_CS, .ea=eip};
683 684
		cur_size = fc->end - fc->start;
		size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
685 686 687
		rc = __linearize(ctxt, addr, size, false, true, &linear);
		if (rc != X86EMUL_CONTINUE)
			return rc;
688 689
		rc = ops->fetch(ctxt, linear, fc->data + cur_size,
				size, &ctxt->exception);
690
		if (rc != X86EMUL_CONTINUE)
691
			return rc;
692
		fc->end += size;
693
	}
694
	*dest = fc->data[eip - fc->start];
695
	return X86EMUL_CONTINUE;
696 697 698 699 700 701
}

static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
			 struct x86_emulate_ops *ops,
			 unsigned long eip, void *dest, unsigned size)
{
702
	int rc;
703

704
	/* x86 instructions are limited to 15 bytes. */
705
	if (eip + size - ctxt->eip > 15)
706
		return X86EMUL_UNHANDLEABLE;
707 708
	while (size--) {
		rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
709
		if (rc != X86EMUL_CONTINUE)
710 711
			return rc;
	}
712
	return X86EMUL_CONTINUE;
713 714
}

715 716 717 718 719 720 721
/*
 * Given the 'reg' portion of a ModRM byte, and a register block, return a
 * pointer into the block that addresses the relevant register.
 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
 */
static void *decode_register(u8 modrm_reg, unsigned long *regs,
			     int highbyte_regs)
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{
	void *p;

	p = &regs[modrm_reg];
	if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
		p = (unsigned char *)&regs[modrm_reg & 3] + 1;
	return p;
}

static int read_descriptor(struct x86_emulate_ctxt *ctxt,
732
			   struct segmented_address addr,
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			   u16 *size, unsigned long *address, int op_bytes)
{
	int rc;

	if (op_bytes == 2)
		op_bytes = 3;
	*address = 0;
740
	rc = segmented_read_std(ctxt, addr, size, 2);
741
	if (rc != X86EMUL_CONTINUE)
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742
		return rc;
743
	addr.ea += 2;
744
	rc = segmented_read_std(ctxt, addr, address, op_bytes);
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745 746 747
	return rc;
}

748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782
static int test_cc(unsigned int condition, unsigned int flags)
{
	int rc = 0;

	switch ((condition & 15) >> 1) {
	case 0: /* o */
		rc |= (flags & EFLG_OF);
		break;
	case 1: /* b/c/nae */
		rc |= (flags & EFLG_CF);
		break;
	case 2: /* z/e */
		rc |= (flags & EFLG_ZF);
		break;
	case 3: /* be/na */
		rc |= (flags & (EFLG_CF|EFLG_ZF));
		break;
	case 4: /* s */
		rc |= (flags & EFLG_SF);
		break;
	case 5: /* p/pe */
		rc |= (flags & EFLG_PF);
		break;
	case 7: /* le/ng */
		rc |= (flags & EFLG_ZF);
		/* fall through */
	case 6: /* l/nge */
		rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
		break;
	}

	/* Odd condition identifiers (lsb == 1) have inverted sense. */
	return (!!rc ^ (condition & 1));
}

783 784 785 786 787 788 789 790 791 792 793 794 795 796 797 798 799 800
static void fetch_register_operand(struct operand *op)
{
	switch (op->bytes) {
	case 1:
		op->val = *(u8 *)op->addr.reg;
		break;
	case 2:
		op->val = *(u16 *)op->addr.reg;
		break;
	case 4:
		op->val = *(u32 *)op->addr.reg;
		break;
	case 8:
		op->val = *(u64 *)op->addr.reg;
		break;
	}
}

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static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
{
	ctxt->ops->get_fpu(ctxt);
	switch (reg) {
	case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
	case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
	case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
	case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
	case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
	case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
	case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
	case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
#ifdef CONFIG_X86_64
	case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
	case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
	case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
	case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
	case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
	case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
	case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
	case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
#endif
	default: BUG();
	}
	ctxt->ops->put_fpu(ctxt);
}

static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
			  int reg)
{
	ctxt->ops->get_fpu(ctxt);
	switch (reg) {
	case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
	case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
	case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
	case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
	case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
	case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
	case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
	case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
#ifdef CONFIG_X86_64
	case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
	case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
	case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
	case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
	case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
	case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
	case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
	case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
#endif
	default: BUG();
	}
	ctxt->ops->put_fpu(ctxt);
}

static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
				    struct operand *op,
858 859 860
				    struct decode_cache *c,
				    int inhibit_bytereg)
{
861
	unsigned reg = c->modrm_reg;
862
	int highbyte_regs = c->rex_prefix == 0;
863 864 865

	if (!(c->d & ModRM))
		reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
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866 867 868 869 870 871 872 873 874

	if (c->d & Sse) {
		op->type = OP_XMM;
		op->bytes = 16;
		op->addr.xmm = reg;
		read_sse_reg(ctxt, &op->vec_val, reg);
		return;
	}

875 876
	op->type = OP_REG;
	if ((c->d & ByteOp) && !inhibit_bytereg) {
877
		op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
878 879
		op->bytes = 1;
	} else {
880
		op->addr.reg = decode_register(reg, c->regs, 0);
881 882
		op->bytes = c->op_bytes;
	}
883
	fetch_register_operand(op);
884 885 886
	op->orig_val = op->val;
}

887
static int decode_modrm(struct x86_emulate_ctxt *ctxt,
888 889
			struct x86_emulate_ops *ops,
			struct operand *op)
890 891 892
{
	struct decode_cache *c = &ctxt->decode;
	u8 sib;
893
	int index_reg = 0, base_reg = 0, scale;
894
	int rc = X86EMUL_CONTINUE;
895
	ulong modrm_ea = 0;
896 897 898 899 900 901 902 903 904 905 906

	if (c->rex_prefix) {
		c->modrm_reg = (c->rex_prefix & 4) << 1;	/* REX.R */
		index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
		c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
	}

	c->modrm = insn_fetch(u8, 1, c->eip);
	c->modrm_mod |= (c->modrm & 0xc0) >> 6;
	c->modrm_reg |= (c->modrm & 0x38) >> 3;
	c->modrm_rm |= (c->modrm & 0x07);
907
	c->modrm_seg = VCPU_SREG_DS;
908 909

	if (c->modrm_mod == 3) {
910 911 912
		op->type = OP_REG;
		op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
		op->addr.reg = decode_register(c->modrm_rm,
913
					       c->regs, c->d & ByteOp);
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Avi Kivity 已提交
914 915 916 917 918 919 920
		if (c->d & Sse) {
			op->type = OP_XMM;
			op->bytes = 16;
			op->addr.xmm = c->modrm_rm;
			read_sse_reg(ctxt, &op->vec_val, c->modrm_rm);
			return rc;
		}
921
		fetch_register_operand(op);
922 923 924
		return rc;
	}

925 926
	op->type = OP_MEM;

927 928 929 930 931 932 933 934 935 936
	if (c->ad_bytes == 2) {
		unsigned bx = c->regs[VCPU_REGS_RBX];
		unsigned bp = c->regs[VCPU_REGS_RBP];
		unsigned si = c->regs[VCPU_REGS_RSI];
		unsigned di = c->regs[VCPU_REGS_RDI];

		/* 16-bit ModR/M decode. */
		switch (c->modrm_mod) {
		case 0:
			if (c->modrm_rm == 6)
937
				modrm_ea += insn_fetch(u16, 2, c->eip);
938 939
			break;
		case 1:
940
			modrm_ea += insn_fetch(s8, 1, c->eip);
941 942
			break;
		case 2:
943
			modrm_ea += insn_fetch(u16, 2, c->eip);
944 945 946 947
			break;
		}
		switch (c->modrm_rm) {
		case 0:
948
			modrm_ea += bx + si;
949 950
			break;
		case 1:
951
			modrm_ea += bx + di;
952 953
			break;
		case 2:
954
			modrm_ea += bp + si;
955 956
			break;
		case 3:
957
			modrm_ea += bp + di;
958 959
			break;
		case 4:
960
			modrm_ea += si;
961 962
			break;
		case 5:
963
			modrm_ea += di;
964 965 966
			break;
		case 6:
			if (c->modrm_mod != 0)
967
				modrm_ea += bp;
968 969
			break;
		case 7:
970
			modrm_ea += bx;
971 972 973 974
			break;
		}
		if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
		    (c->modrm_rm == 6 && c->modrm_mod != 0))
975
			c->modrm_seg = VCPU_SREG_SS;
976
		modrm_ea = (u16)modrm_ea;
977 978
	} else {
		/* 32/64-bit ModR/M decode. */
979
		if ((c->modrm_rm & 7) == 4) {
980 981 982 983 984
			sib = insn_fetch(u8, 1, c->eip);
			index_reg |= (sib >> 3) & 7;
			base_reg |= sib & 7;
			scale = sib >> 6;

985
			if ((base_reg & 7) == 5 && c->modrm_mod == 0)
986
				modrm_ea += insn_fetch(s32, 4, c->eip);
987
			else
988
				modrm_ea += c->regs[base_reg];
989
			if (index_reg != 4)
990
				modrm_ea += c->regs[index_reg] << scale;
991 992
		} else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
			if (ctxt->mode == X86EMUL_MODE_PROT64)
993
				c->rip_relative = 1;
994
		} else
995
			modrm_ea += c->regs[c->modrm_rm];
996 997 998
		switch (c->modrm_mod) {
		case 0:
			if (c->modrm_rm == 5)
999
				modrm_ea += insn_fetch(s32, 4, c->eip);
1000 1001
			break;
		case 1:
1002
			modrm_ea += insn_fetch(s8, 1, c->eip);
1003 1004
			break;
		case 2:
1005
			modrm_ea += insn_fetch(s32, 4, c->eip);
1006 1007 1008
			break;
		}
	}
1009
	op->addr.mem.ea = modrm_ea;
1010 1011 1012 1013 1014
done:
	return rc;
}

static int decode_abs(struct x86_emulate_ctxt *ctxt,
1015 1016
		      struct x86_emulate_ops *ops,
		      struct operand *op)
1017 1018
{
	struct decode_cache *c = &ctxt->decode;
1019
	int rc = X86EMUL_CONTINUE;
1020

1021
	op->type = OP_MEM;
1022 1023
	switch (c->ad_bytes) {
	case 2:
1024
		op->addr.mem.ea = insn_fetch(u16, 2, c->eip);
1025 1026
		break;
	case 4:
1027
		op->addr.mem.ea = insn_fetch(u32, 4, c->eip);
1028 1029
		break;
	case 8:
1030
		op->addr.mem.ea = insn_fetch(u64, 8, c->eip);
1031 1032 1033 1034 1035 1036
		break;
	}
done:
	return rc;
}

1037 1038
static void fetch_bit_operand(struct decode_cache *c)
{
1039
	long sv = 0, mask;
1040

1041
	if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
1042 1043 1044 1045 1046 1047 1048
		mask = ~(c->dst.bytes * 8 - 1);

		if (c->src.bytes == 2)
			sv = (s16)c->src.val & (s16)mask;
		else if (c->src.bytes == 4)
			sv = (s32)c->src.val & (s32)mask;

1049
		c->dst.addr.mem.ea += (sv >> 3);
1050
	}
1051 1052 1053

	/* only subword offset */
	c->src.val &= (c->dst.bytes << 3) - 1;
1054 1055
}

1056 1057 1058
static int read_emulated(struct x86_emulate_ctxt *ctxt,
			 struct x86_emulate_ops *ops,
			 unsigned long addr, void *dest, unsigned size)
A
Avi Kivity 已提交
1059
{
1060 1061
	int rc;
	struct read_cache *mc = &ctxt->decode.mem_read;
A
Avi Kivity 已提交
1062

1063 1064 1065 1066 1067
	while (size) {
		int n = min(size, 8u);
		size -= n;
		if (mc->pos < mc->end)
			goto read_cached;
1068

1069 1070
		rc = ops->read_emulated(ctxt, addr, mc->data + mc->end, n,
					&ctxt->exception);
1071 1072 1073
		if (rc != X86EMUL_CONTINUE)
			return rc;
		mc->end += n;
A
Avi Kivity 已提交
1074

1075 1076 1077 1078 1079
	read_cached:
		memcpy(dest, mc->data + mc->pos, n);
		mc->pos += n;
		dest += n;
		addr += n;
A
Avi Kivity 已提交
1080
	}
1081 1082
	return X86EMUL_CONTINUE;
}
A
Avi Kivity 已提交
1083

1084 1085 1086 1087 1088
static int segmented_read(struct x86_emulate_ctxt *ctxt,
			  struct segmented_address addr,
			  void *data,
			  unsigned size)
{
1089 1090 1091
	int rc;
	ulong linear;

1092
	rc = linearize(ctxt, addr, size, false, &linear);
1093 1094 1095
	if (rc != X86EMUL_CONTINUE)
		return rc;
	return read_emulated(ctxt, ctxt->ops, linear, data, size);
1096 1097 1098 1099 1100 1101 1102
}

static int segmented_write(struct x86_emulate_ctxt *ctxt,
			   struct segmented_address addr,
			   const void *data,
			   unsigned size)
{
1103 1104 1105
	int rc;
	ulong linear;

1106
	rc = linearize(ctxt, addr, size, true, &linear);
1107 1108
	if (rc != X86EMUL_CONTINUE)
		return rc;
1109 1110
	return ctxt->ops->write_emulated(ctxt, linear, data, size,
					 &ctxt->exception);
1111 1112 1113 1114 1115 1116 1117
}

static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
			     struct segmented_address addr,
			     const void *orig_data, const void *data,
			     unsigned size)
{
1118 1119 1120
	int rc;
	ulong linear;

1121
	rc = linearize(ctxt, addr, size, true, &linear);
1122 1123
	if (rc != X86EMUL_CONTINUE)
		return rc;
1124 1125
	return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
					   size, &ctxt->exception);
1126 1127
}

1128 1129 1130 1131 1132 1133
static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
			   struct x86_emulate_ops *ops,
			   unsigned int size, unsigned short port,
			   void *dest)
{
	struct read_cache *rc = &ctxt->decode.io_read;
1134

1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147
	if (rc->pos == rc->end) { /* refill pio read ahead */
		struct decode_cache *c = &ctxt->decode;
		unsigned int in_page, n;
		unsigned int count = c->rep_prefix ?
			address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
		in_page = (ctxt->eflags & EFLG_DF) ?
			offset_in_page(c->regs[VCPU_REGS_RDI]) :
			PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
		n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
			count);
		if (n == 0)
			n = 1;
		rc->pos = rc->end = 0;
1148
		if (!ops->pio_in_emulated(ctxt, size, port, rc->data, n))
1149 1150
			return 0;
		rc->end = n * size;
A
Avi Kivity 已提交
1151 1152
	}

1153 1154 1155 1156
	memcpy(dest, rc->data + rc->pos, size);
	rc->pos += size;
	return 1;
}
A
Avi Kivity 已提交
1157

1158 1159 1160 1161 1162 1163
static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
				     struct x86_emulate_ops *ops,
				     u16 selector, struct desc_ptr *dt)
{
	if (selector & 1 << 2) {
		struct desc_struct desc;
1164 1165
		u16 sel;

1166
		memset (dt, 0, sizeof *dt);
1167
		if (!ops->get_segment(ctxt, &sel, &desc, NULL, VCPU_SREG_LDTR))
1168
			return;
1169

1170 1171 1172
		dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
		dt->address = get_desc_base(&desc);
	} else
1173
		ops->get_gdt(ctxt, dt);
1174
}
1175

1176 1177 1178 1179 1180 1181 1182 1183 1184
/* allowed just for 8 bytes segments */
static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				   struct x86_emulate_ops *ops,
				   u16 selector, struct desc_struct *desc)
{
	struct desc_ptr dt;
	u16 index = selector >> 3;
	int ret;
	ulong addr;
1185

1186
	get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1187

1188 1189
	if (dt.size < index * 8 + 7)
		return emulate_gp(ctxt, selector & 0xfffc);
1190
	addr = dt.address + index * 8;
1191
	ret = ops->read_std(ctxt, addr, desc, sizeof *desc, &ctxt->exception);
1192

1193 1194
       return ret;
}
1195

1196 1197 1198 1199 1200 1201 1202 1203 1204
/* allowed just for 8 bytes segments */
static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				    struct x86_emulate_ops *ops,
				    u16 selector, struct desc_struct *desc)
{
	struct desc_ptr dt;
	u16 index = selector >> 3;
	ulong addr;
	int ret;
A
Avi Kivity 已提交
1205

1206
	get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1207

1208 1209
	if (dt.size < index * 8 + 7)
		return emulate_gp(ctxt, selector & 0xfffc);
A
Avi Kivity 已提交
1210

1211
	addr = dt.address + index * 8;
1212
	ret = ops->write_std(ctxt, addr, desc, sizeof *desc, &ctxt->exception);
1213

1214 1215
	return ret;
}
1216

1217
/* Does not support long mode */
1218 1219 1220 1221 1222 1223 1224 1225 1226 1227
static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				   struct x86_emulate_ops *ops,
				   u16 selector, int seg)
{
	struct desc_struct seg_desc;
	u8 dpl, rpl, cpl;
	unsigned err_vec = GP_VECTOR;
	u32 err_code = 0;
	bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
	int ret;
1228

1229
	memset(&seg_desc, 0, sizeof seg_desc);
1230

1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271
	if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
	    || ctxt->mode == X86EMUL_MODE_REAL) {
		/* set real mode segment descriptor */
		set_desc_base(&seg_desc, selector << 4);
		set_desc_limit(&seg_desc, 0xffff);
		seg_desc.type = 3;
		seg_desc.p = 1;
		seg_desc.s = 1;
		goto load;
	}

	/* NULL selector is not valid for TR, CS and SS */
	if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
	    && null_selector)
		goto exception;

	/* TR should be in GDT only */
	if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
		goto exception;

	if (null_selector) /* for NULL selector skip all following checks */
		goto load;

	ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
	if (ret != X86EMUL_CONTINUE)
		return ret;

	err_code = selector & 0xfffc;
	err_vec = GP_VECTOR;

	/* can't load system descriptor into segment selecor */
	if (seg <= VCPU_SREG_GS && !seg_desc.s)
		goto exception;

	if (!seg_desc.p) {
		err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
		goto exception;
	}

	rpl = selector & 3;
	dpl = seg_desc.dpl;
1272
	cpl = ops->cpl(ctxt);
1273 1274 1275 1276 1277 1278 1279 1280 1281

	switch (seg) {
	case VCPU_SREG_SS:
		/*
		 * segment is not a writable data segment or segment
		 * selector's RPL != CPL or segment selector's RPL != CPL
		 */
		if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
			goto exception;
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Avi Kivity 已提交
1282
		break;
1283 1284 1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297
	case VCPU_SREG_CS:
		if (!(seg_desc.type & 8))
			goto exception;

		if (seg_desc.type & 4) {
			/* conforming */
			if (dpl > cpl)
				goto exception;
		} else {
			/* nonconforming */
			if (rpl > cpl || dpl != cpl)
				goto exception;
		}
		/* CS(RPL) <- CPL */
		selector = (selector & 0xfffc) | cpl;
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1298
		break;
1299 1300 1301 1302 1303 1304 1305 1306 1307
	case VCPU_SREG_TR:
		if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
			goto exception;
		break;
	case VCPU_SREG_LDTR:
		if (seg_desc.s || seg_desc.type != 2)
			goto exception;
		break;
	default: /*  DS, ES, FS, or GS */
1308
		/*
1309 1310 1311
		 * segment is not a data or readable code segment or
		 * ((segment is a data or nonconforming code segment)
		 * and (both RPL and CPL > DPL))
1312
		 */
1313 1314 1315 1316
		if ((seg_desc.type & 0xa) == 0x8 ||
		    (((seg_desc.type & 0xc) != 0xc) &&
		     (rpl > dpl && cpl > dpl)))
			goto exception;
A
Avi Kivity 已提交
1317
		break;
1318 1319 1320 1321 1322 1323 1324 1325 1326 1327
	}

	if (seg_desc.s) {
		/* mark segment as accessed */
		seg_desc.type |= 1;
		ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
		if (ret != X86EMUL_CONTINUE)
			return ret;
	}
load:
1328
	ops->set_segment(ctxt, selector, &seg_desc, 0, seg);
1329 1330 1331 1332 1333 1334
	return X86EMUL_CONTINUE;
exception:
	emulate_exception(ctxt, err_vec, err_code, true);
	return X86EMUL_PROPAGATE_FAULT;
}

1335 1336 1337 1338 1339 1340 1341 1342 1343 1344 1345 1346 1347 1348 1349 1350 1351 1352 1353
static void write_register_operand(struct operand *op)
{
	/* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
	switch (op->bytes) {
	case 1:
		*(u8 *)op->addr.reg = (u8)op->val;
		break;
	case 2:
		*(u16 *)op->addr.reg = (u16)op->val;
		break;
	case 4:
		*op->addr.reg = (u32)op->val;
		break;	/* 64b: zero-extend */
	case 8:
		*op->addr.reg = op->val;
		break;
	}
}

1354
static int writeback(struct x86_emulate_ctxt *ctxt)
1355 1356 1357 1358 1359 1360
{
	int rc;
	struct decode_cache *c = &ctxt->decode;

	switch (c->dst.type) {
	case OP_REG:
1361
		write_register_operand(&c->dst);
A
Avi Kivity 已提交
1362
		break;
1363 1364
	case OP_MEM:
		if (c->lock_prefix)
1365 1366 1367 1368 1369
			rc = segmented_cmpxchg(ctxt,
					       c->dst.addr.mem,
					       &c->dst.orig_val,
					       &c->dst.val,
					       c->dst.bytes);
1370
		else
1371 1372 1373 1374
			rc = segmented_write(ctxt,
					     c->dst.addr.mem,
					     &c->dst.val,
					     c->dst.bytes);
1375 1376
		if (rc != X86EMUL_CONTINUE)
			return rc;
1377
		break;
A
Avi Kivity 已提交
1378 1379 1380
	case OP_XMM:
		write_sse_reg(ctxt, &c->dst.vec_val, c->dst.addr.xmm);
		break;
1381 1382
	case OP_NONE:
		/* no writeback */
1383
		break;
1384
	default:
1385
		break;
A
Avi Kivity 已提交
1386
	}
1387 1388
	return X86EMUL_CONTINUE;
}
A
Avi Kivity 已提交
1389

1390
static int em_push(struct x86_emulate_ctxt *ctxt)
1391 1392
{
	struct decode_cache *c = &ctxt->decode;
1393
	struct segmented_address addr;
1394

1395
	register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1396 1397 1398 1399 1400 1401
	addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
	addr.seg = VCPU_SREG_SS;

	/* Disable writeback. */
	c->dst.type = OP_NONE;
	return segmented_write(ctxt, addr, &c->src.val, c->op_bytes);
1402
}
1403

1404 1405 1406 1407 1408
static int emulate_pop(struct x86_emulate_ctxt *ctxt,
		       void *dest, int len)
{
	struct decode_cache *c = &ctxt->decode;
	int rc;
1409
	struct segmented_address addr;
1410

1411 1412
	addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
	addr.seg = VCPU_SREG_SS;
1413
	rc = segmented_read(ctxt, addr, dest, len);
1414 1415 1416 1417 1418
	if (rc != X86EMUL_CONTINUE)
		return rc;

	register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
	return rc;
1419 1420
}

1421 1422 1423 1424
static int em_pop(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

1425
	return emulate_pop(ctxt, &c->dst.val, c->op_bytes);
1426 1427
}

1428 1429 1430
static int emulate_popf(struct x86_emulate_ctxt *ctxt,
		       struct x86_emulate_ops *ops,
		       void *dest, int len)
1431 1432
{
	int rc;
1433 1434
	unsigned long val, change_mask;
	int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1435
	int cpl = ops->cpl(ctxt);
1436

1437
	rc = emulate_pop(ctxt, &val, len);
1438 1439
	if (rc != X86EMUL_CONTINUE)
		return rc;
1440

1441 1442
	change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
		| EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1443

1444 1445 1446 1447 1448 1449 1450 1451 1452 1453
	switch(ctxt->mode) {
	case X86EMUL_MODE_PROT64:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT16:
		if (cpl == 0)
			change_mask |= EFLG_IOPL;
		if (cpl <= iopl)
			change_mask |= EFLG_IF;
		break;
	case X86EMUL_MODE_VM86:
1454 1455
		if (iopl < 3)
			return emulate_gp(ctxt, 0);
1456 1457 1458 1459 1460
		change_mask |= EFLG_IF;
		break;
	default: /* real mode */
		change_mask |= (EFLG_IOPL | EFLG_IF);
		break;
1461
	}
1462 1463 1464 1465 1466

	*(unsigned long *)dest =
		(ctxt->eflags & ~change_mask) | (val & change_mask);

	return rc;
1467 1468
}

1469 1470 1471 1472 1473 1474 1475 1476 1477 1478
static int em_popf(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	c->dst.type = OP_REG;
	c->dst.addr.reg = &ctxt->eflags;
	c->dst.bytes = c->op_bytes;
	return emulate_popf(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
}

1479 1480
static int emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
			     struct x86_emulate_ops *ops, int seg)
1481
{
1482
	struct decode_cache *c = &ctxt->decode;
1483

1484
	c->src.val = get_segment_selector(ctxt, seg);
1485

1486
	return em_push(ctxt);
1487 1488
}

1489 1490
static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
			     struct x86_emulate_ops *ops, int seg)
1491
{
1492 1493 1494
	struct decode_cache *c = &ctxt->decode;
	unsigned long selector;
	int rc;
1495

1496
	rc = emulate_pop(ctxt, &selector, c->op_bytes);
1497 1498 1499 1500 1501
	if (rc != X86EMUL_CONTINUE)
		return rc;

	rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
	return rc;
1502 1503
}

1504
static int em_pusha(struct x86_emulate_ctxt *ctxt)
1505
{
1506 1507 1508 1509
	struct decode_cache *c = &ctxt->decode;
	unsigned long old_esp = c->regs[VCPU_REGS_RSP];
	int rc = X86EMUL_CONTINUE;
	int reg = VCPU_REGS_RAX;
1510

1511 1512 1513
	while (reg <= VCPU_REGS_RDI) {
		(reg == VCPU_REGS_RSP) ?
		(c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1514

1515
		rc = em_push(ctxt);
1516 1517
		if (rc != X86EMUL_CONTINUE)
			return rc;
1518

1519
		++reg;
1520 1521
	}

1522
	return rc;
1523 1524
}

1525 1526 1527 1528 1529 1530 1531 1532
static int em_pushf(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	c->src.val =  (unsigned long)ctxt->eflags;
	return em_push(ctxt);
}

1533
static int em_popa(struct x86_emulate_ctxt *ctxt)
1534
{
1535 1536 1537
	struct decode_cache *c = &ctxt->decode;
	int rc = X86EMUL_CONTINUE;
	int reg = VCPU_REGS_RDI;
1538

1539 1540 1541 1542 1543 1544
	while (reg >= VCPU_REGS_RAX) {
		if (reg == VCPU_REGS_RSP) {
			register_address_increment(c, &c->regs[VCPU_REGS_RSP],
							c->op_bytes);
			--reg;
		}
1545

1546
		rc = emulate_pop(ctxt, &c->regs[reg], c->op_bytes);
1547 1548 1549
		if (rc != X86EMUL_CONTINUE)
			break;
		--reg;
1550
	}
1551
	return rc;
1552 1553
}

1554 1555 1556 1557
int emulate_int_real(struct x86_emulate_ctxt *ctxt,
			       struct x86_emulate_ops *ops, int irq)
{
	struct decode_cache *c = &ctxt->decode;
1558
	int rc;
1559 1560 1561 1562 1563 1564 1565
	struct desc_ptr dt;
	gva_t cs_addr;
	gva_t eip_addr;
	u16 cs, eip;

	/* TODO: Add limit checks */
	c->src.val = ctxt->eflags;
1566
	rc = em_push(ctxt);
1567 1568
	if (rc != X86EMUL_CONTINUE)
		return rc;
1569 1570 1571

	ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);

1572
	c->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
1573
	rc = em_push(ctxt);
1574 1575
	if (rc != X86EMUL_CONTINUE)
		return rc;
1576 1577

	c->src.val = c->eip;
1578
	rc = em_push(ctxt);
1579 1580 1581
	if (rc != X86EMUL_CONTINUE)
		return rc;

1582
	ops->get_idt(ctxt, &dt);
1583 1584 1585 1586

	eip_addr = dt.address + (irq << 2);
	cs_addr = dt.address + (irq << 2) + 2;

1587
	rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
1588 1589 1590
	if (rc != X86EMUL_CONTINUE)
		return rc;

1591
	rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
1592 1593 1594 1595 1596 1597 1598 1599 1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610 1611 1612 1613 1614 1615 1616 1617 1618 1619
	if (rc != X86EMUL_CONTINUE)
		return rc;

	rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	c->eip = eip;

	return rc;
}

static int emulate_int(struct x86_emulate_ctxt *ctxt,
		       struct x86_emulate_ops *ops, int irq)
{
	switch(ctxt->mode) {
	case X86EMUL_MODE_REAL:
		return emulate_int_real(ctxt, ops, irq);
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT64:
	default:
		/* Protected mode interrupts unimplemented yet */
		return X86EMUL_UNHANDLEABLE;
	}
}

1620 1621
static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
			     struct x86_emulate_ops *ops)
1622
{
1623 1624 1625 1626 1627 1628 1629 1630 1631
	struct decode_cache *c = &ctxt->decode;
	int rc = X86EMUL_CONTINUE;
	unsigned long temp_eip = 0;
	unsigned long temp_eflags = 0;
	unsigned long cs = 0;
	unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
			     EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
			     EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
	unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1632

1633
	/* TODO: Add stack limit check */
1634

1635
	rc = emulate_pop(ctxt, &temp_eip, c->op_bytes);
1636

1637 1638
	if (rc != X86EMUL_CONTINUE)
		return rc;
1639

1640 1641
	if (temp_eip & ~0xffff)
		return emulate_gp(ctxt, 0);
1642

1643
	rc = emulate_pop(ctxt, &cs, c->op_bytes);
1644

1645 1646
	if (rc != X86EMUL_CONTINUE)
		return rc;
1647

1648
	rc = emulate_pop(ctxt, &temp_eflags, c->op_bytes);
1649

1650 1651
	if (rc != X86EMUL_CONTINUE)
		return rc;
1652

1653
	rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1654

1655 1656
	if (rc != X86EMUL_CONTINUE)
		return rc;
1657

1658
	c->eip = temp_eip;
1659 1660


1661 1662 1663 1664 1665
	if (c->op_bytes == 4)
		ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
	else if (c->op_bytes == 2) {
		ctxt->eflags &= ~0xffff;
		ctxt->eflags |= temp_eflags;
1666
	}
1667 1668 1669 1670 1671

	ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
	ctxt->eflags |= EFLG_RESERVED_ONE_MASK;

	return rc;
1672 1673
}

1674 1675
static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
				    struct x86_emulate_ops* ops)
1676
{
1677 1678 1679 1680 1681 1682 1683
	switch(ctxt->mode) {
	case X86EMUL_MODE_REAL:
		return emulate_iret_real(ctxt, ops);
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT64:
1684
	default:
1685 1686
		/* iret from protected mode unimplemented yet */
		return X86EMUL_UNHANDLEABLE;
1687 1688 1689
	}
}

1690 1691 1692 1693 1694 1695 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 1706
static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	int rc;
	unsigned short sel;

	memcpy(&sel, c->src.valptr + c->op_bytes, 2);

	rc = load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	c->eip = 0;
	memcpy(&c->eip, c->src.valptr, c->op_bytes);
	return X86EMUL_CONTINUE;
}

1707
static int em_grp1a(struct x86_emulate_ctxt *ctxt)
1708 1709 1710
{
	struct decode_cache *c = &ctxt->decode;

1711
	return emulate_pop(ctxt, &c->dst.val, c->dst.bytes);
1712 1713
}

1714
static int em_grp2(struct x86_emulate_ctxt *ctxt)
1715
{
1716
	struct decode_cache *c = &ctxt->decode;
1717 1718
	switch (c->modrm_reg) {
	case 0:	/* rol */
1719
		emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1720 1721
		break;
	case 1:	/* ror */
1722
		emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1723 1724
		break;
	case 2:	/* rcl */
1725
		emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1726 1727
		break;
	case 3:	/* rcr */
1728
		emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1729 1730 1731
		break;
	case 4:	/* sal/shl */
	case 6:	/* sal/shl */
1732
		emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1733 1734
		break;
	case 5:	/* shr */
1735
		emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1736 1737
		break;
	case 7:	/* sar */
1738
		emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1739 1740
		break;
	}
1741
	return X86EMUL_CONTINUE;
1742 1743
}

1744
static int em_grp3(struct x86_emulate_ctxt *ctxt)
1745 1746
{
	struct decode_cache *c = &ctxt->decode;
1747 1748
	unsigned long *rax = &c->regs[VCPU_REGS_RAX];
	unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
1749
	u8 de = 0;
1750 1751 1752

	switch (c->modrm_reg) {
	case 0 ... 1:	/* test */
1753
		emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1754 1755 1756 1757 1758
		break;
	case 2:	/* not */
		c->dst.val = ~c->dst.val;
		break;
	case 3:	/* neg */
1759
		emulate_1op("neg", c->dst, ctxt->eflags);
1760
		break;
1761 1762 1763 1764 1765 1766 1767
	case 4: /* mul */
		emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
		break;
	case 5: /* imul */
		emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
		break;
	case 6: /* div */
1768 1769
		emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx,
				       ctxt->eflags, de);
1770 1771
		break;
	case 7: /* idiv */
1772 1773
		emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx,
				       ctxt->eflags, de);
1774
		break;
1775
	default:
1776
		return X86EMUL_UNHANDLEABLE;
1777
	}
1778 1779
	if (de)
		return emulate_de(ctxt);
1780
	return X86EMUL_CONTINUE;
1781 1782
}

1783
static int em_grp45(struct x86_emulate_ctxt *ctxt)
1784 1785
{
	struct decode_cache *c = &ctxt->decode;
1786
	int rc = X86EMUL_CONTINUE;
1787 1788 1789

	switch (c->modrm_reg) {
	case 0:	/* inc */
1790
		emulate_1op("inc", c->dst, ctxt->eflags);
1791 1792
		break;
	case 1:	/* dec */
1793
		emulate_1op("dec", c->dst, ctxt->eflags);
1794
		break;
1795 1796 1797 1798 1799
	case 2: /* call near abs */ {
		long int old_eip;
		old_eip = c->eip;
		c->eip = c->src.val;
		c->src.val = old_eip;
1800
		rc = em_push(ctxt);
1801 1802
		break;
	}
1803
	case 4: /* jmp abs */
1804
		c->eip = c->src.val;
1805
		break;
1806 1807 1808
	case 5: /* jmp far */
		rc = em_jmp_far(ctxt);
		break;
1809
	case 6:	/* push */
1810
		rc = em_push(ctxt);
1811 1812
		break;
	}
1813
	return rc;
1814 1815
}

1816
static int em_grp9(struct x86_emulate_ctxt *ctxt)
1817 1818
{
	struct decode_cache *c = &ctxt->decode;
1819
	u64 old = c->dst.orig_val64;
1820 1821 1822 1823 1824

	if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
	    ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
		c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
		c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1825
		ctxt->eflags &= ~EFLG_ZF;
1826
	} else {
1827 1828
		c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
			(u32) c->regs[VCPU_REGS_RBX];
1829

1830
		ctxt->eflags |= EFLG_ZF;
1831
	}
1832
	return X86EMUL_CONTINUE;
1833 1834
}

1835 1836 1837 1838 1839 1840 1841
static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
			   struct x86_emulate_ops *ops)
{
	struct decode_cache *c = &ctxt->decode;
	int rc;
	unsigned long cs;

1842
	rc = emulate_pop(ctxt, &c->eip, c->op_bytes);
1843
	if (rc != X86EMUL_CONTINUE)
1844 1845 1846
		return rc;
	if (c->op_bytes == 4)
		c->eip = (u32)c->eip;
1847
	rc = emulate_pop(ctxt, &cs, c->op_bytes);
1848
	if (rc != X86EMUL_CONTINUE)
1849
		return rc;
1850
	rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1851 1852 1853
	return rc;
}

1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870
static int emulate_load_segment(struct x86_emulate_ctxt *ctxt,
			   struct x86_emulate_ops *ops, int seg)
{
	struct decode_cache *c = &ctxt->decode;
	unsigned short sel;
	int rc;

	memcpy(&sel, c->src.valptr + c->op_bytes, 2);

	rc = load_segment_descriptor(ctxt, ops, sel, seg);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	c->dst.val = c->src.val;
	return rc;
}

1871 1872
static inline void
setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1873 1874
			struct x86_emulate_ops *ops, struct desc_struct *cs,
			struct desc_struct *ss)
1875
{
1876 1877
	u16 selector;

1878
	memset(cs, 0, sizeof(struct desc_struct));
1879
	ops->get_segment(ctxt, &selector, cs, NULL, VCPU_SREG_CS);
1880
	memset(ss, 0, sizeof(struct desc_struct));
1881 1882

	cs->l = 0;		/* will be adjusted later */
1883
	set_desc_base(cs, 0);	/* flat segment */
1884
	cs->g = 1;		/* 4kb granularity */
1885
	set_desc_limit(cs, 0xfffff);	/* 4GB limit */
1886 1887 1888
	cs->type = 0x0b;	/* Read, Execute, Accessed */
	cs->s = 1;
	cs->dpl = 0;		/* will be adjusted later */
1889 1890
	cs->p = 1;
	cs->d = 1;
1891

1892 1893
	set_desc_base(ss, 0);	/* flat segment */
	set_desc_limit(ss, 0xfffff);	/* 4GB limit */
1894 1895 1896
	ss->g = 1;		/* 4kb granularity */
	ss->s = 1;
	ss->type = 0x03;	/* Read/Write, Accessed */
1897
	ss->d = 1;		/* 32bit stack segment */
1898
	ss->dpl = 0;
1899
	ss->p = 1;
1900 1901 1902
}

static int
1903
emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1904 1905
{
	struct decode_cache *c = &ctxt->decode;
1906
	struct desc_struct cs, ss;
1907
	u64 msr_data;
1908
	u16 cs_sel, ss_sel;
1909
	u64 efer = 0;
1910 1911

	/* syscall is not available in real mode */
1912
	if (ctxt->mode == X86EMUL_MODE_REAL ||
1913 1914
	    ctxt->mode == X86EMUL_MODE_VM86)
		return emulate_ud(ctxt);
1915

1916
	ops->get_msr(ctxt, MSR_EFER, &efer);
1917
	setup_syscalls_segments(ctxt, ops, &cs, &ss);
1918

1919
	ops->get_msr(ctxt, MSR_STAR, &msr_data);
1920
	msr_data >>= 32;
1921 1922
	cs_sel = (u16)(msr_data & 0xfffc);
	ss_sel = (u16)(msr_data + 8);
1923

1924
	if (efer & EFER_LMA) {
1925
		cs.d = 0;
1926 1927
		cs.l = 1;
	}
1928 1929
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
1930 1931

	c->regs[VCPU_REGS_RCX] = c->eip;
1932
	if (efer & EFER_LMA) {
1933 1934 1935
#ifdef CONFIG_X86_64
		c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;

1936
		ops->get_msr(ctxt,
1937 1938
			     ctxt->mode == X86EMUL_MODE_PROT64 ?
			     MSR_LSTAR : MSR_CSTAR, &msr_data);
1939 1940
		c->eip = msr_data;

1941
		ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
1942 1943 1944 1945
		ctxt->eflags &= ~(msr_data | EFLG_RF);
#endif
	} else {
		/* legacy mode */
1946
		ops->get_msr(ctxt, MSR_STAR, &msr_data);
1947 1948 1949 1950 1951
		c->eip = (u32)msr_data;

		ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
	}

1952
	return X86EMUL_CONTINUE;
1953 1954
}

1955
static int
1956
emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1957 1958
{
	struct decode_cache *c = &ctxt->decode;
1959
	struct desc_struct cs, ss;
1960
	u64 msr_data;
1961
	u16 cs_sel, ss_sel;
1962
	u64 efer = 0;
1963

1964
	ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
1965
	/* inject #GP if in real mode */
1966 1967
	if (ctxt->mode == X86EMUL_MODE_REAL)
		return emulate_gp(ctxt, 0);
1968 1969 1970 1971

	/* XXX sysenter/sysexit have not been tested in 64bit mode.
	* Therefore, we inject an #UD.
	*/
1972 1973
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		return emulate_ud(ctxt);
1974

1975
	setup_syscalls_segments(ctxt, ops, &cs, &ss);
1976

1977
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
1978 1979
	switch (ctxt->mode) {
	case X86EMUL_MODE_PROT32:
1980 1981
		if ((msr_data & 0xfffc) == 0x0)
			return emulate_gp(ctxt, 0);
1982 1983
		break;
	case X86EMUL_MODE_PROT64:
1984 1985
		if (msr_data == 0x0)
			return emulate_gp(ctxt, 0);
1986 1987 1988 1989
		break;
	}

	ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1990 1991 1992 1993
	cs_sel = (u16)msr_data;
	cs_sel &= ~SELECTOR_RPL_MASK;
	ss_sel = cs_sel + 8;
	ss_sel &= ~SELECTOR_RPL_MASK;
1994
	if (ctxt->mode == X86EMUL_MODE_PROT64 || (efer & EFER_LMA)) {
1995
		cs.d = 0;
1996 1997 1998
		cs.l = 1;
	}

1999 2000
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2001

2002
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
2003 2004
	c->eip = msr_data;

2005
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
2006 2007
	c->regs[VCPU_REGS_RSP] = msr_data;

2008
	return X86EMUL_CONTINUE;
2009 2010
}

2011
static int
2012
emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
2013 2014
{
	struct decode_cache *c = &ctxt->decode;
2015
	struct desc_struct cs, ss;
2016 2017
	u64 msr_data;
	int usermode;
2018
	u16 cs_sel, ss_sel;
2019

2020 2021
	/* inject #GP if in real mode or Virtual 8086 mode */
	if (ctxt->mode == X86EMUL_MODE_REAL ||
2022 2023
	    ctxt->mode == X86EMUL_MODE_VM86)
		return emulate_gp(ctxt, 0);
2024

2025
	setup_syscalls_segments(ctxt, ops, &cs, &ss);
2026 2027 2028 2029 2030 2031 2032 2033

	if ((c->rex_prefix & 0x8) != 0x0)
		usermode = X86EMUL_MODE_PROT64;
	else
		usermode = X86EMUL_MODE_PROT32;

	cs.dpl = 3;
	ss.dpl = 3;
2034
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2035 2036
	switch (usermode) {
	case X86EMUL_MODE_PROT32:
2037
		cs_sel = (u16)(msr_data + 16);
2038 2039
		if ((msr_data & 0xfffc) == 0x0)
			return emulate_gp(ctxt, 0);
2040
		ss_sel = (u16)(msr_data + 24);
2041 2042
		break;
	case X86EMUL_MODE_PROT64:
2043
		cs_sel = (u16)(msr_data + 32);
2044 2045
		if (msr_data == 0x0)
			return emulate_gp(ctxt, 0);
2046 2047
		ss_sel = cs_sel + 8;
		cs.d = 0;
2048 2049 2050
		cs.l = 1;
		break;
	}
2051 2052
	cs_sel |= SELECTOR_RPL_MASK;
	ss_sel |= SELECTOR_RPL_MASK;
2053

2054 2055
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2056

2057 2058
	c->eip = c->regs[VCPU_REGS_RDX];
	c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
2059

2060
	return X86EMUL_CONTINUE;
2061 2062
}

2063 2064
static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
			      struct x86_emulate_ops *ops)
2065 2066 2067 2068 2069 2070 2071
{
	int iopl;
	if (ctxt->mode == X86EMUL_MODE_REAL)
		return false;
	if (ctxt->mode == X86EMUL_MODE_VM86)
		return true;
	iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
2072
	return ops->cpl(ctxt) > iopl;
2073 2074 2075 2076 2077 2078
}

static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
					    struct x86_emulate_ops *ops,
					    u16 port, u16 len)
{
2079
	struct desc_struct tr_seg;
2080
	u32 base3;
2081
	int r;
2082
	u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
2083
	unsigned mask = (1 << len) - 1;
2084
	unsigned long base;
2085

2086
	ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
2087
	if (!tr_seg.p)
2088
		return false;
2089
	if (desc_limit_scaled(&tr_seg) < 103)
2090
		return false;
2091 2092 2093 2094
	base = get_desc_base(&tr_seg);
#ifdef CONFIG_X86_64
	base |= ((u64)base3) << 32;
#endif
2095
	r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
2096 2097
	if (r != X86EMUL_CONTINUE)
		return false;
2098
	if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
2099
		return false;
2100
	r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111
	if (r != X86EMUL_CONTINUE)
		return false;
	if ((perm >> bit_idx) & mask)
		return false;
	return true;
}

static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
				 struct x86_emulate_ops *ops,
				 u16 port, u16 len)
{
2112 2113 2114
	if (ctxt->perm_ok)
		return true;

2115
	if (emulator_bad_iopl(ctxt, ops))
2116 2117
		if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
			return false;
2118 2119 2120

	ctxt->perm_ok = true;

2121 2122 2123
	return true;
}

2124 2125 2126 2127 2128 2129 2130 2131 2132 2133 2134 2135 2136 2137 2138 2139 2140
static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
				struct x86_emulate_ops *ops,
				struct tss_segment_16 *tss)
{
	struct decode_cache *c = &ctxt->decode;

	tss->ip = c->eip;
	tss->flag = ctxt->eflags;
	tss->ax = c->regs[VCPU_REGS_RAX];
	tss->cx = c->regs[VCPU_REGS_RCX];
	tss->dx = c->regs[VCPU_REGS_RDX];
	tss->bx = c->regs[VCPU_REGS_RBX];
	tss->sp = c->regs[VCPU_REGS_RSP];
	tss->bp = c->regs[VCPU_REGS_RBP];
	tss->si = c->regs[VCPU_REGS_RSI];
	tss->di = c->regs[VCPU_REGS_RDI];

2141 2142 2143 2144 2145
	tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
	tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
	tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
	tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
	tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2146 2147 2148 2149 2150 2151 2152 2153 2154 2155 2156 2157 2158 2159 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169
}

static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
				 struct x86_emulate_ops *ops,
				 struct tss_segment_16 *tss)
{
	struct decode_cache *c = &ctxt->decode;
	int ret;

	c->eip = tss->ip;
	ctxt->eflags = tss->flag | 2;
	c->regs[VCPU_REGS_RAX] = tss->ax;
	c->regs[VCPU_REGS_RCX] = tss->cx;
	c->regs[VCPU_REGS_RDX] = tss->dx;
	c->regs[VCPU_REGS_RBX] = tss->bx;
	c->regs[VCPU_REGS_RSP] = tss->sp;
	c->regs[VCPU_REGS_RBP] = tss->bp;
	c->regs[VCPU_REGS_RSI] = tss->si;
	c->regs[VCPU_REGS_RDI] = tss->di;

	/*
	 * SDM says that segment selectors are loaded before segment
	 * descriptors
	 */
2170 2171 2172 2173 2174
	set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
	set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
	set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
	set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
	set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
2175 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204 2205

	/*
	 * Now load segment descriptors. If fault happenes at this stage
	 * it is handled in a context of new task
	 */
	ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
	if (ret != X86EMUL_CONTINUE)
		return ret;
	ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
	if (ret != X86EMUL_CONTINUE)
		return ret;
	ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
	if (ret != X86EMUL_CONTINUE)
		return ret;
	ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
	if (ret != X86EMUL_CONTINUE)
		return ret;
	ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
	if (ret != X86EMUL_CONTINUE)
		return ret;

	return X86EMUL_CONTINUE;
}

static int task_switch_16(struct x86_emulate_ctxt *ctxt,
			  struct x86_emulate_ops *ops,
			  u16 tss_selector, u16 old_tss_sel,
			  ulong old_tss_base, struct desc_struct *new_desc)
{
	struct tss_segment_16 tss_seg;
	int ret;
2206
	u32 new_tss_base = get_desc_base(new_desc);
2207

2208
	ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2209
			    &ctxt->exception);
2210
	if (ret != X86EMUL_CONTINUE)
2211 2212 2213 2214 2215
		/* FIXME: need to provide precise fault address */
		return ret;

	save_state_to_tss16(ctxt, ops, &tss_seg);

2216
	ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2217
			     &ctxt->exception);
2218
	if (ret != X86EMUL_CONTINUE)
2219 2220 2221
		/* FIXME: need to provide precise fault address */
		return ret;

2222
	ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2223
			    &ctxt->exception);
2224
	if (ret != X86EMUL_CONTINUE)
2225 2226 2227 2228 2229 2230
		/* FIXME: need to provide precise fault address */
		return ret;

	if (old_tss_sel != 0xffff) {
		tss_seg.prev_task_link = old_tss_sel;

2231
		ret = ops->write_std(ctxt, new_tss_base,
2232 2233
				     &tss_seg.prev_task_link,
				     sizeof tss_seg.prev_task_link,
2234
				     &ctxt->exception);
2235
		if (ret != X86EMUL_CONTINUE)
2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248
			/* FIXME: need to provide precise fault address */
			return ret;
	}

	return load_state_from_tss16(ctxt, ops, &tss_seg);
}

static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
				struct x86_emulate_ops *ops,
				struct tss_segment_32 *tss)
{
	struct decode_cache *c = &ctxt->decode;

2249
	tss->cr3 = ops->get_cr(ctxt, 3);
2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260
	tss->eip = c->eip;
	tss->eflags = ctxt->eflags;
	tss->eax = c->regs[VCPU_REGS_RAX];
	tss->ecx = c->regs[VCPU_REGS_RCX];
	tss->edx = c->regs[VCPU_REGS_RDX];
	tss->ebx = c->regs[VCPU_REGS_RBX];
	tss->esp = c->regs[VCPU_REGS_RSP];
	tss->ebp = c->regs[VCPU_REGS_RBP];
	tss->esi = c->regs[VCPU_REGS_RSI];
	tss->edi = c->regs[VCPU_REGS_RDI];

2261 2262 2263 2264 2265 2266 2267
	tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
	tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
	tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
	tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
	tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
	tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
	tss->ldt_selector = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2268 2269 2270 2271 2272 2273 2274 2275 2276
}

static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
				 struct x86_emulate_ops *ops,
				 struct tss_segment_32 *tss)
{
	struct decode_cache *c = &ctxt->decode;
	int ret;

2277
	if (ops->set_cr(ctxt, 3, tss->cr3))
2278
		return emulate_gp(ctxt, 0);
2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292 2293
	c->eip = tss->eip;
	ctxt->eflags = tss->eflags | 2;
	c->regs[VCPU_REGS_RAX] = tss->eax;
	c->regs[VCPU_REGS_RCX] = tss->ecx;
	c->regs[VCPU_REGS_RDX] = tss->edx;
	c->regs[VCPU_REGS_RBX] = tss->ebx;
	c->regs[VCPU_REGS_RSP] = tss->esp;
	c->regs[VCPU_REGS_RBP] = tss->ebp;
	c->regs[VCPU_REGS_RSI] = tss->esi;
	c->regs[VCPU_REGS_RDI] = tss->edi;

	/*
	 * SDM says that segment selectors are loaded before segment
	 * descriptors
	 */
2294 2295 2296 2297 2298 2299 2300
	set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
	set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
	set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
	set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
	set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
	set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
	set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
2301 2302 2303 2304 2305 2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337

	/*
	 * Now load segment descriptors. If fault happenes at this stage
	 * it is handled in a context of new task
	 */
	ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
	if (ret != X86EMUL_CONTINUE)
		return ret;
	ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
	if (ret != X86EMUL_CONTINUE)
		return ret;
	ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
	if (ret != X86EMUL_CONTINUE)
		return ret;
	ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
	if (ret != X86EMUL_CONTINUE)
		return ret;
	ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
	if (ret != X86EMUL_CONTINUE)
		return ret;
	ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
	if (ret != X86EMUL_CONTINUE)
		return ret;
	ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
	if (ret != X86EMUL_CONTINUE)
		return ret;

	return X86EMUL_CONTINUE;
}

static int task_switch_32(struct x86_emulate_ctxt *ctxt,
			  struct x86_emulate_ops *ops,
			  u16 tss_selector, u16 old_tss_sel,
			  ulong old_tss_base, struct desc_struct *new_desc)
{
	struct tss_segment_32 tss_seg;
	int ret;
2338
	u32 new_tss_base = get_desc_base(new_desc);
2339

2340
	ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2341
			    &ctxt->exception);
2342
	if (ret != X86EMUL_CONTINUE)
2343 2344 2345 2346 2347
		/* FIXME: need to provide precise fault address */
		return ret;

	save_state_to_tss32(ctxt, ops, &tss_seg);

2348
	ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
2349
			     &ctxt->exception);
2350
	if (ret != X86EMUL_CONTINUE)
2351 2352 2353
		/* FIXME: need to provide precise fault address */
		return ret;

2354
	ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
2355
			    &ctxt->exception);
2356
	if (ret != X86EMUL_CONTINUE)
2357 2358 2359 2360 2361 2362
		/* FIXME: need to provide precise fault address */
		return ret;

	if (old_tss_sel != 0xffff) {
		tss_seg.prev_task_link = old_tss_sel;

2363
		ret = ops->write_std(ctxt, new_tss_base,
2364 2365
				     &tss_seg.prev_task_link,
				     sizeof tss_seg.prev_task_link,
2366
				     &ctxt->exception);
2367
		if (ret != X86EMUL_CONTINUE)
2368 2369 2370 2371 2372 2373 2374 2375
			/* FIXME: need to provide precise fault address */
			return ret;
	}

	return load_state_from_tss32(ctxt, ops, &tss_seg);
}

static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2376 2377 2378
				   struct x86_emulate_ops *ops,
				   u16 tss_selector, int reason,
				   bool has_error_code, u32 error_code)
2379 2380 2381
{
	struct desc_struct curr_tss_desc, next_tss_desc;
	int ret;
2382
	u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
2383
	ulong old_tss_base =
2384
		ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
2385
	u32 desc_limit;
2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399

	/* FIXME: old_tss_base == ~0 ? */

	ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
	if (ret != X86EMUL_CONTINUE)
		return ret;
	ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
	if (ret != X86EMUL_CONTINUE)
		return ret;

	/* FIXME: check that next_tss_desc is tss */

	if (reason != TASK_SWITCH_IRET) {
		if ((tss_selector & 3) > next_tss_desc.dpl ||
2400
		    ops->cpl(ctxt) > next_tss_desc.dpl)
2401
			return emulate_gp(ctxt, 0);
2402 2403
	}

2404 2405 2406 2407
	desc_limit = desc_limit_scaled(&next_tss_desc);
	if (!next_tss_desc.p ||
	    ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
	     desc_limit < 0x2b)) {
2408
		emulate_ts(ctxt, tss_selector & 0xfffc);
2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431
		return X86EMUL_PROPAGATE_FAULT;
	}

	if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
		curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
		write_segment_descriptor(ctxt, ops, old_tss_sel,
					 &curr_tss_desc);
	}

	if (reason == TASK_SWITCH_IRET)
		ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;

	/* set back link to prev task only if NT bit is set in eflags
	   note that old_tss_sel is not used afetr this point */
	if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
		old_tss_sel = 0xffff;

	if (next_tss_desc.type & 8)
		ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
				     old_tss_base, &next_tss_desc);
	else
		ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
				     old_tss_base, &next_tss_desc);
2432 2433
	if (ret != X86EMUL_CONTINUE)
		return ret;
2434 2435 2436 2437 2438 2439 2440 2441 2442 2443

	if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
		ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;

	if (reason != TASK_SWITCH_IRET) {
		next_tss_desc.type |= (1 << 1); /* set busy flag */
		write_segment_descriptor(ctxt, ops, tss_selector,
					 &next_tss_desc);
	}

2444
	ops->set_cr(ctxt, 0,  ops->get_cr(ctxt, 0) | X86_CR0_TS);
2445
	ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
2446

2447 2448 2449 2450 2451 2452
	if (has_error_code) {
		struct decode_cache *c = &ctxt->decode;

		c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
		c->lock_prefix = 0;
		c->src.val = (unsigned long) error_code;
2453
		ret = em_push(ctxt);
2454 2455
	}

2456 2457 2458 2459
	return ret;
}

int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2460 2461
			 u16 tss_selector, int reason,
			 bool has_error_code, u32 error_code)
2462
{
2463
	struct x86_emulate_ops *ops = ctxt->ops;
2464 2465 2466 2467
	struct decode_cache *c = &ctxt->decode;
	int rc;

	c->eip = ctxt->eip;
2468
	c->dst.type = OP_NONE;
2469

2470 2471
	rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
				     has_error_code, error_code);
2472

2473 2474
	if (rc == X86EMUL_CONTINUE)
		ctxt->eip = c->eip;
2475

2476
	return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
2477 2478
}

2479
static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
2480
			    int reg, struct operand *op)
2481 2482 2483 2484
{
	struct decode_cache *c = &ctxt->decode;
	int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;

2485
	register_address_increment(c, &c->regs[reg], df * op->bytes);
2486 2487
	op->addr.mem.ea = register_address(c, c->regs[reg]);
	op->addr.mem.seg = seg;
2488 2489
}

2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528
static int em_das(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	u8 al, old_al;
	bool af, cf, old_cf;

	cf = ctxt->eflags & X86_EFLAGS_CF;
	al = c->dst.val;

	old_al = al;
	old_cf = cf;
	cf = false;
	af = ctxt->eflags & X86_EFLAGS_AF;
	if ((al & 0x0f) > 9 || af) {
		al -= 6;
		cf = old_cf | (al >= 250);
		af = true;
	} else {
		af = false;
	}
	if (old_al > 0x99 || old_cf) {
		al -= 0x60;
		cf = true;
	}

	c->dst.val = al;
	/* Set PF, ZF, SF */
	c->src.type = OP_IMM;
	c->src.val = 0;
	c->src.bytes = 1;
	emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
	ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
	if (cf)
		ctxt->eflags |= X86_EFLAGS_CF;
	if (af)
		ctxt->eflags |= X86_EFLAGS_AF;
	return X86EMUL_CONTINUE;
}

2529 2530 2531 2532 2533 2534 2535
static int em_call_far(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	u16 sel, old_cs;
	ulong old_eip;
	int rc;

2536
	old_cs = get_segment_selector(ctxt, VCPU_SREG_CS);
2537 2538 2539 2540 2541 2542 2543 2544 2545 2546
	old_eip = c->eip;

	memcpy(&sel, c->src.valptr + c->op_bytes, 2);
	if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
		return X86EMUL_CONTINUE;

	c->eip = 0;
	memcpy(&c->eip, c->src.valptr, c->op_bytes);

	c->src.val = old_cs;
2547
	rc = em_push(ctxt);
2548 2549 2550 2551
	if (rc != X86EMUL_CONTINUE)
		return rc;

	c->src.val = old_eip;
2552
	return em_push(ctxt);
2553 2554
}

2555 2556 2557 2558 2559 2560 2561 2562
static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	int rc;

	c->dst.type = OP_REG;
	c->dst.addr.reg = &c->eip;
	c->dst.bytes = c->op_bytes;
2563
	rc = emulate_pop(ctxt, &c->dst.val, c->op_bytes);
2564 2565 2566 2567 2568 2569
	if (rc != X86EMUL_CONTINUE)
		return rc;
	register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
	return X86EMUL_CONTINUE;
}

2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635
static int em_add(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
	return X86EMUL_CONTINUE;
}

static int em_or(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
	return X86EMUL_CONTINUE;
}

static int em_adc(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
	return X86EMUL_CONTINUE;
}

static int em_sbb(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
	return X86EMUL_CONTINUE;
}

static int em_and(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
	return X86EMUL_CONTINUE;
}

static int em_sub(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
	return X86EMUL_CONTINUE;
}

static int em_xor(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
	return X86EMUL_CONTINUE;
}

static int em_cmp(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
	/* Disable writeback. */
	c->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

2636
static int em_imul(struct x86_emulate_ctxt *ctxt)
2637 2638 2639 2640 2641 2642 2643
{
	struct decode_cache *c = &ctxt->decode;

	emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
	return X86EMUL_CONTINUE;
}

2644 2645 2646 2647 2648 2649 2650 2651
static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	c->dst.val = c->src2.val;
	return em_imul(ctxt);
}

2652 2653 2654 2655 2656 2657 2658 2659 2660 2661 2662 2663
static int em_cwd(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	c->dst.type = OP_REG;
	c->dst.bytes = c->src.bytes;
	c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
	c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);

	return X86EMUL_CONTINUE;
}

2664 2665 2666 2667 2668
static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	u64 tsc = 0;

2669
	ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
2670 2671 2672 2673 2674
	c->regs[VCPU_REGS_RAX] = (u32)tsc;
	c->regs[VCPU_REGS_RDX] = tsc >> 32;
	return X86EMUL_CONTINUE;
}

2675 2676 2677 2678 2679 2680 2681
static int em_mov(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	c->dst.val = c->src.val;
	return X86EMUL_CONTINUE;
}

2682 2683 2684 2685 2686 2687 2688
static int em_movdqu(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	memcpy(&c->dst.vec_val, &c->src.vec_val, c->op_bytes);
	return X86EMUL_CONTINUE;
}

2689 2690 2691
static int em_invlpg(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
2692 2693 2694
	int rc;
	ulong linear;

2695
	rc = linearize(ctxt, c->src.addr.mem, 1, false, &linear);
2696
	if (rc == X86EMUL_CONTINUE)
2697
		ctxt->ops->invlpg(ctxt, linear);
2698 2699 2700 2701 2702
	/* Disable writeback. */
	c->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

2703 2704 2705 2706 2707 2708 2709 2710 2711 2712
static int em_clts(struct x86_emulate_ctxt *ctxt)
{
	ulong cr0;

	cr0 = ctxt->ops->get_cr(ctxt, 0);
	cr0 &= ~X86_CR0_TS;
	ctxt->ops->set_cr(ctxt, 0, cr0);
	return X86EMUL_CONTINUE;
}

2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737
static int em_vmcall(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	int rc;

	if (c->modrm_mod != 3 || c->modrm_rm != 1)
		return X86EMUL_UNHANDLEABLE;

	rc = ctxt->ops->fix_hypercall(ctxt);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	/* Let the processor re-execute the fixed hypercall */
	c->eip = ctxt->eip;
	/* Disable writeback. */
	c->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

static int em_lgdt(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	struct desc_ptr desc_ptr;
	int rc;

2738
	rc = read_descriptor(ctxt, c->src.addr.mem,
2739 2740 2741 2742 2743 2744 2745 2746 2747 2748
			     &desc_ptr.size, &desc_ptr.address,
			     c->op_bytes);
	if (rc != X86EMUL_CONTINUE)
		return rc;
	ctxt->ops->set_gdt(ctxt, &desc_ptr);
	/* Disable writeback. */
	c->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

2749
static int em_vmmcall(struct x86_emulate_ctxt *ctxt)
2750 2751 2752 2753
{
	struct decode_cache *c = &ctxt->decode;
	int rc;

2754 2755
	rc = ctxt->ops->fix_hypercall(ctxt);

2756 2757 2758 2759 2760 2761 2762 2763 2764 2765 2766
	/* Disable writeback. */
	c->dst.type = OP_NONE;
	return rc;
}

static int em_lidt(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	struct desc_ptr desc_ptr;
	int rc;

2767 2768
	rc = read_descriptor(ctxt, c->src.addr.mem,
			     &desc_ptr.size, &desc_ptr.address,
2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783 2784 2785 2786 2787 2788 2789 2790 2791 2792 2793 2794 2795
			     c->op_bytes);
	if (rc != X86EMUL_CONTINUE)
		return rc;
	ctxt->ops->set_idt(ctxt, &desc_ptr);
	/* Disable writeback. */
	c->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

static int em_smsw(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	c->dst.bytes = 2;
	c->dst.val = ctxt->ops->get_cr(ctxt, 0);
	return X86EMUL_CONTINUE;
}

static int em_lmsw(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
			  | (c->src.val & 0x0f));
	c->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810 2811 2812 2813 2814 2815 2816 2817 2818 2819 2820 2821 2822
static bool valid_cr(int nr)
{
	switch (nr) {
	case 0:
	case 2 ... 4:
	case 8:
		return true;
	default:
		return false;
	}
}

static int check_cr_read(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	if (!valid_cr(c->modrm_reg))
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_cr_write(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	u64 new_val = c->src.val64;
	int cr = c->modrm_reg;
2823
	u64 efer = 0;
2824 2825 2826 2827 2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838 2839 2840

	static u64 cr_reserved_bits[] = {
		0xffffffff00000000ULL,
		0, 0, 0, /* CR3 checked later */
		CR4_RESERVED_BITS,
		0, 0, 0,
		CR8_RESERVED_BITS,
	};

	if (!valid_cr(cr))
		return emulate_ud(ctxt);

	if (new_val & cr_reserved_bits[cr])
		return emulate_gp(ctxt, 0);

	switch (cr) {
	case 0: {
2841
		u64 cr4;
2842 2843 2844 2845
		if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
		    ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
			return emulate_gp(ctxt, 0);

2846 2847
		cr4 = ctxt->ops->get_cr(ctxt, 4);
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2848 2849 2850 2851 2852 2853 2854 2855 2856 2857

		if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
		    !(cr4 & X86_CR4_PAE))
			return emulate_gp(ctxt, 0);

		break;
		}
	case 3: {
		u64 rsvd = 0;

2858 2859
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
		if (efer & EFER_LMA)
2860
			rsvd = CR3_L_MODE_RESERVED_BITS;
2861
		else if (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_PAE)
2862
			rsvd = CR3_PAE_RESERVED_BITS;
2863
		else if (ctxt->ops->get_cr(ctxt, 0) & X86_CR0_PG)
2864 2865 2866 2867 2868 2869 2870 2871
			rsvd = CR3_NONPAE_RESERVED_BITS;

		if (new_val & rsvd)
			return emulate_gp(ctxt, 0);

		break;
		}
	case 4: {
2872
		u64 cr4;
2873

2874 2875
		cr4 = ctxt->ops->get_cr(ctxt, 4);
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886

		if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
			return emulate_gp(ctxt, 0);

		break;
		}
	}

	return X86EMUL_CONTINUE;
}

2887 2888 2889 2890
static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
{
	unsigned long dr7;

2891
	ctxt->ops->get_dr(ctxt, 7, &dr7);
2892 2893 2894 2895 2896 2897 2898 2899 2900 2901 2902 2903 2904 2905

	/* Check if DR7.Global_Enable is set */
	return dr7 & (1 << 13);
}

static int check_dr_read(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	int dr = c->modrm_reg;
	u64 cr4;

	if (dr > 7)
		return emulate_ud(ctxt);

2906
	cr4 = ctxt->ops->get_cr(ctxt, 4);
2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 2927
	if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
		return emulate_ud(ctxt);

	if (check_dr7_gd(ctxt))
		return emulate_db(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_dr_write(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;
	u64 new_val = c->src.val64;
	int dr = c->modrm_reg;

	if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
		return emulate_gp(ctxt, 0);

	return check_dr_read(ctxt);
}

2928 2929 2930 2931
static int check_svme(struct x86_emulate_ctxt *ctxt)
{
	u64 efer;

2932
	ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
2933 2934 2935 2936 2937 2938 2939 2940 2941

	if (!(efer & EFER_SVME))
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
{
2942
	u64 rax = ctxt->decode.regs[VCPU_REGS_RAX];
2943 2944

	/* Valid physical address? */
2945
	if (rax & 0xffff000000000000ULL)
2946 2947 2948 2949 2950
		return emulate_gp(ctxt, 0);

	return check_svme(ctxt);
}

2951 2952
static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
{
2953
	u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
2954

2955
	if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
2956 2957 2958 2959 2960
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

2961 2962
static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
{
2963
	u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
2964
	u64 rcx = ctxt->decode.regs[VCPU_REGS_RCX];
2965

2966
	if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
2967 2968 2969 2970 2971 2972
	    (rcx > 3))
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

2973 2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985 2986 2987 2988 2989 2990 2991 2992 2993 2994
static int check_perm_in(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	c->dst.bytes = min(c->dst.bytes, 4u);
	if (!emulator_io_permited(ctxt, ctxt->ops, c->src.val, c->dst.bytes))
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

static int check_perm_out(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	c->src.bytes = min(c->src.bytes, 4u);
	if (!emulator_io_permited(ctxt, ctxt->ops, c->dst.val, c->src.bytes))
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

2995
#define D(_y) { .flags = (_y) }
2996
#define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
2997 2998
#define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
		      .check_perm = (_p) }
2999
#define N    D(0)
3000
#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
3001
#define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
3002
#define GD(_f, _g) { .flags = ((_f) | GroupDual), .u.gdual = (_g) }
3003
#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
3004 3005
#define II(_f, _e, _i) \
	{ .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
3006 3007 3008
#define IIP(_f, _e, _i, _p) \
	{ .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
	  .check_perm = (_p) }
3009
#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
3010

3011
#define D2bv(_f)      D((_f) | ByteOp), D(_f)
3012
#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
3013 3014
#define I2bv(_f, _e)  I((_f) | ByteOp, _e), I(_f, _e)

3015 3016 3017
#define I6ALU(_f, _e) I2bv((_f) | DstMem | SrcReg | ModRM, _e),		\
		I2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e),	\
		I2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
3018

3019 3020 3021 3022 3023 3024
static struct opcode group7_rm1[] = {
	DI(SrcNone | ModRM | Priv, monitor),
	DI(SrcNone | ModRM | Priv, mwait),
	N, N, N, N, N, N,
};

3025 3026
static struct opcode group7_rm3[] = {
	DIP(SrcNone | ModRM | Prot | Priv, vmrun,   check_svme_pa),
3027
	II(SrcNone | ModRM | Prot | VendorSpecific, em_vmmcall, vmmcall),
3028 3029 3030 3031 3032 3033 3034
	DIP(SrcNone | ModRM | Prot | Priv, vmload,  check_svme_pa),
	DIP(SrcNone | ModRM | Prot | Priv, vmsave,  check_svme_pa),
	DIP(SrcNone | ModRM | Prot | Priv, stgi,    check_svme),
	DIP(SrcNone | ModRM | Prot | Priv, clgi,    check_svme),
	DIP(SrcNone | ModRM | Prot | Priv, skinit,  check_svme),
	DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
};
3035

3036 3037 3038 3039 3040
static struct opcode group7_rm7[] = {
	N,
	DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
	N, N, N, N, N, N,
};
3041

3042
static struct opcode group1[] = {
3043 3044 3045 3046 3047 3048 3049 3050
	I(Lock, em_add),
	I(Lock, em_or),
	I(Lock, em_adc),
	I(Lock, em_sbb),
	I(Lock, em_and),
	I(Lock, em_sub),
	I(Lock, em_xor),
	I(0, em_cmp),
3051 3052 3053 3054 3055 3056 3057 3058 3059
};

static struct opcode group1A[] = {
	D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
};

static struct opcode group3[] = {
	D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
	D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3060
	X4(D(SrcMem | ModRM)),
3061 3062 3063 3064 3065 3066 3067 3068 3069
};

static struct opcode group4[] = {
	D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
	N, N, N, N, N, N,
};

static struct opcode group5[] = {
	D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
3070 3071
	D(SrcMem | ModRM | Stack),
	I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
3072 3073 3074 3075
	D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
	D(SrcMem | ModRM | Stack), N,
};

3076 3077 3078 3079 3080 3081 3082 3083
static struct opcode group6[] = {
	DI(ModRM | Prot,        sldt),
	DI(ModRM | Prot,        str),
	DI(ModRM | Prot | Priv, lldt),
	DI(ModRM | Prot | Priv, ltr),
	N, N, N, N,
};

3084
static struct group_dual group7 = { {
3085 3086
	DI(ModRM | Mov | DstMem | Priv, sgdt),
	DI(ModRM | Mov | DstMem | Priv, sidt),
3087 3088 3089 3090 3091
	II(ModRM | SrcMem | Priv, em_lgdt, lgdt),
	II(ModRM | SrcMem | Priv, em_lidt, lidt),
	II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
	II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw),
	II(SrcMem | ModRM | ByteOp | Priv | NoAccess, em_invlpg, invlpg),
3092
}, {
3093 3094
	I(SrcNone | ModRM | Priv | VendorSpecific, em_vmcall),
	EXT(0, group7_rm1),
3095
	N, EXT(0, group7_rm3),
3096 3097
	II(SrcNone | ModRM | DstMem | Mov, em_smsw, smsw), N,
	II(SrcMem16 | ModRM | Mov | Priv, em_lmsw, lmsw), EXT(0, group7_rm7),
3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111
} };

static struct opcode group8[] = {
	N, N, N, N,
	D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
	D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
};

static struct group_dual group9 = { {
	N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
}, {
	N, N, N, N, N, N, N, N,
} };

3112 3113 3114 3115
static struct opcode group11[] = {
	I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
};

3116 3117 3118 3119
static struct gprefix pfx_0f_6f_0f_7f = {
	N, N, N, I(Sse, em_movdqu),
};

3120 3121
static struct opcode opcode_table[256] = {
	/* 0x00 - 0x07 */
3122
	I6ALU(Lock, em_add),
3123 3124
	D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
	/* 0x08 - 0x0F */
3125
	I6ALU(Lock, em_or),
3126 3127
	D(ImplicitOps | Stack | No64), N,
	/* 0x10 - 0x17 */
3128
	I6ALU(Lock, em_adc),
3129 3130
	D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
	/* 0x18 - 0x1F */
3131
	I6ALU(Lock, em_sbb),
3132 3133
	D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
	/* 0x20 - 0x27 */
3134
	I6ALU(Lock, em_and), N, N,
3135
	/* 0x28 - 0x2F */
3136
	I6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
3137
	/* 0x30 - 0x37 */
3138
	I6ALU(Lock, em_xor), N, N,
3139
	/* 0x38 - 0x3F */
3140
	I6ALU(0, em_cmp), N, N,
3141 3142 3143
	/* 0x40 - 0x4F */
	X16(D(DstReg)),
	/* 0x50 - 0x57 */
3144
	X8(I(SrcReg | Stack, em_push)),
3145
	/* 0x58 - 0x5F */
3146
	X8(I(DstReg | Stack, em_pop)),
3147
	/* 0x60 - 0x67 */
3148 3149
	I(ImplicitOps | Stack | No64, em_pusha),
	I(ImplicitOps | Stack | No64, em_popa),
3150 3151 3152
	N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
	N, N, N, N,
	/* 0x68 - 0x6F */
3153 3154
	I(SrcImm | Mov | Stack, em_push),
	I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
3155 3156
	I(SrcImmByte | Mov | Stack, em_push),
	I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
3157 3158
	D2bvIP(DstDI | Mov | String, ins, check_perm_in), /* insb, insw/insd */
	D2bvIP(SrcSI | ImplicitOps | String, outs, check_perm_out), /* outsb, outsw/outsd */
3159 3160 3161 3162 3163 3164 3165
	/* 0x70 - 0x7F */
	X16(D(SrcImmByte)),
	/* 0x80 - 0x87 */
	G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
	G(DstMem | SrcImm | ModRM | Group, group1),
	G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
	G(DstMem | SrcImmByte | ModRM | Group, group1),
3166
	D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock),
3167
	/* 0x88 - 0x8F */
3168 3169
	I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
	I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
3170
	D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
3171 3172
	D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
	/* 0x90 - 0x97 */
3173
	DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
3174
	/* 0x98 - 0x9F */
3175
	D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
3176
	I(SrcImmFAddr | No64, em_call_far), N,
3177 3178
	II(ImplicitOps | Stack, em_pushf, pushf),
	II(ImplicitOps | Stack, em_popf, popf), N, N,
3179
	/* 0xA0 - 0xA7 */
3180 3181 3182
	I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
	I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
	I2bv(SrcSI | DstDI | Mov | String, em_mov),
3183
	I2bv(SrcSI | DstDI | String, em_cmp),
3184
	/* 0xA8 - 0xAF */
3185
	D2bv(DstAcc | SrcImm),
3186 3187
	I2bv(SrcAcc | DstDI | Mov | String, em_mov),
	I2bv(SrcSI | DstAcc | Mov | String, em_mov),
3188
	I2bv(SrcAcc | DstDI | String, em_cmp),
3189
	/* 0xB0 - 0xB7 */
3190
	X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
3191
	/* 0xB8 - 0xBF */
3192
	X8(I(DstReg | SrcImm | Mov, em_mov)),
3193
	/* 0xC0 - 0xC7 */
3194
	D2bv(DstMem | SrcImmByte | ModRM),
3195 3196
	I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
	D(ImplicitOps | Stack),
3197
	D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
3198
	G(ByteOp, group11), G(0, group11),
3199 3200
	/* 0xC8 - 0xCF */
	N, N, N, D(ImplicitOps | Stack),
3201 3202
	D(ImplicitOps), DI(SrcImmByte, intn),
	D(ImplicitOps | No64), DI(ImplicitOps, iret),
3203
	/* 0xD0 - 0xD7 */
3204
	D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
3205 3206 3207 3208
	N, N, N, N,
	/* 0xD8 - 0xDF */
	N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xE7 */
3209
	X4(D(SrcImmByte)),
3210 3211
	D2bvIP(SrcImmUByte | DstAcc, in,  check_perm_in),
	D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
3212 3213 3214
	/* 0xE8 - 0xEF */
	D(SrcImm | Stack), D(SrcImm | ImplicitOps),
	D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
3215 3216
	D2bvIP(SrcNone | DstAcc,     in,  check_perm_in),
	D2bvIP(SrcAcc | ImplicitOps, out, check_perm_out),
3217
	/* 0xF0 - 0xF7 */
3218
	N, DI(ImplicitOps, icebp), N, N,
3219 3220
	DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
	G(ByteOp, group3), G(0, group3),
3221
	/* 0xF8 - 0xFF */
3222
	D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
3223 3224 3225 3226 3227
	D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
};

static struct opcode twobyte_table[256] = {
	/* 0x00 - 0x0F */
3228
	G(0, group6), GD(0, &group7), N, N,
3229
	N, D(ImplicitOps | VendorSpecific), DI(ImplicitOps | Priv, clts), N,
3230
	DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
3231 3232 3233 3234
	N, D(ImplicitOps | ModRM), N, N,
	/* 0x10 - 0x1F */
	N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
	/* 0x20 - 0x2F */
3235
	DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
3236
	DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
3237
	DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
3238
	DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
3239 3240 3241
	N, N, N, N,
	N, N, N, N, N, N, N, N,
	/* 0x30 - 0x3F */
3242 3243 3244 3245
	DI(ImplicitOps | Priv, wrmsr),
	IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
	DI(ImplicitOps | Priv, rdmsr),
	DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
3246 3247
	D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv | VendorSpecific),
	N, N,
3248 3249 3250 3251 3252 3253
	N, N, N, N, N, N, N, N,
	/* 0x40 - 0x4F */
	X16(D(DstReg | SrcMem | ModRM | Mov)),
	/* 0x50 - 0x5F */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0x60 - 0x6F */
3254 3255 3256 3257
	N, N, N, N,
	N, N, N, N,
	N, N, N, N,
	N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
3258
	/* 0x70 - 0x7F */
3259 3260 3261 3262
	N, N, N, N,
	N, N, N, N,
	N, N, N, N,
	N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
3263 3264 3265
	/* 0x80 - 0x8F */
	X16(D(SrcImm)),
	/* 0x90 - 0x9F */
3266
	X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
3267 3268
	/* 0xA0 - 0xA7 */
	D(ImplicitOps | Stack), D(ImplicitOps | Stack),
3269
	DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
3270 3271 3272 3273
	D(DstMem | SrcReg | Src2ImmByte | ModRM),
	D(DstMem | SrcReg | Src2CL | ModRM), N, N,
	/* 0xA8 - 0xAF */
	D(ImplicitOps | Stack), D(ImplicitOps | Stack),
3274
	DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3275 3276
	D(DstMem | SrcReg | Src2ImmByte | ModRM),
	D(DstMem | SrcReg | Src2CL | ModRM),
3277
	D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
3278
	/* 0xB0 - 0xB7 */
3279
	D2bv(DstMem | SrcReg | ModRM | Lock),
3280 3281 3282
	D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
	D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
	D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3283 3284
	/* 0xB8 - 0xBF */
	N, N,
3285
	G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
3286 3287
	D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
	D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
3288
	/* 0xC0 - 0xCF */
3289
	D2bv(DstMem | SrcReg | ModRM | Lock),
3290
	N, D(DstMem | SrcReg | ModRM | Mov),
3291 3292 3293 3294 3295 3296 3297 3298 3299 3300 3301 3302 3303 3304 3305
	N, N, N, GD(0, &group9),
	N, N, N, N, N, N, N, N,
	/* 0xD0 - 0xDF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xEF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0xF0 - 0xFF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
};

#undef D
#undef N
#undef G
#undef GD
#undef I
3306
#undef GP
3307
#undef EXT
3308

3309
#undef D2bv
3310
#undef D2bvIP
3311
#undef I2bv
3312
#undef I6ALU
3313

3314 3315 3316 3317 3318 3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332
static unsigned imm_size(struct decode_cache *c)
{
	unsigned size;

	size = (c->d & ByteOp) ? 1 : c->op_bytes;
	if (size == 8)
		size = 4;
	return size;
}

static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
		      unsigned size, bool sign_extension)
{
	struct decode_cache *c = &ctxt->decode;
	struct x86_emulate_ops *ops = ctxt->ops;
	int rc = X86EMUL_CONTINUE;

	op->type = OP_IMM;
	op->bytes = size;
3333
	op->addr.mem.ea = c->eip;
3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351 3352 3353 3354 3355 3356 3357 3358 3359 3360 3361 3362
	/* NB. Immediates are sign-extended as necessary. */
	switch (op->bytes) {
	case 1:
		op->val = insn_fetch(s8, 1, c->eip);
		break;
	case 2:
		op->val = insn_fetch(s16, 2, c->eip);
		break;
	case 4:
		op->val = insn_fetch(s32, 4, c->eip);
		break;
	}
	if (!sign_extension) {
		switch (op->bytes) {
		case 1:
			op->val &= 0xff;
			break;
		case 2:
			op->val &= 0xffff;
			break;
		case 4:
			op->val &= 0xffffffff;
			break;
		}
	}
done:
	return rc;
}

3363
int
3364
x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
3365 3366 3367 3368 3369
{
	struct x86_emulate_ops *ops = ctxt->ops;
	struct decode_cache *c = &ctxt->decode;
	int rc = X86EMUL_CONTINUE;
	int mode = ctxt->mode;
3370
	int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
3371
	bool op_prefix = false;
3372
	struct opcode opcode;
3373
	struct operand memop = { .type = OP_NONE };
3374 3375

	c->eip = ctxt->eip;
3376 3377 3378 3379
	c->fetch.start = c->eip;
	c->fetch.end = c->fetch.start + insn_len;
	if (insn_len > 0)
		memcpy(c->fetch.data, insn, insn_len);
3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398 3399 3400 3401 3402 3403 3404 3405 3406

	switch (mode) {
	case X86EMUL_MODE_REAL:
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
		def_op_bytes = def_ad_bytes = 2;
		break;
	case X86EMUL_MODE_PROT32:
		def_op_bytes = def_ad_bytes = 4;
		break;
#ifdef CONFIG_X86_64
	case X86EMUL_MODE_PROT64:
		def_op_bytes = 4;
		def_ad_bytes = 8;
		break;
#endif
	default:
		return -1;
	}

	c->op_bytes = def_op_bytes;
	c->ad_bytes = def_ad_bytes;

	/* Legacy prefixes. */
	for (;;) {
		switch (c->b = insn_fetch(u8, 1, c->eip)) {
		case 0x66:	/* operand-size override */
3407
			op_prefix = true;
3408 3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430 3431 3432 3433 3434 3435 3436 3437 3438
			/* switch between 2/4 bytes */
			c->op_bytes = def_op_bytes ^ 6;
			break;
		case 0x67:	/* address-size override */
			if (mode == X86EMUL_MODE_PROT64)
				/* switch between 4/8 bytes */
				c->ad_bytes = def_ad_bytes ^ 12;
			else
				/* switch between 2/4 bytes */
				c->ad_bytes = def_ad_bytes ^ 6;
			break;
		case 0x26:	/* ES override */
		case 0x2e:	/* CS override */
		case 0x36:	/* SS override */
		case 0x3e:	/* DS override */
			set_seg_override(c, (c->b >> 3) & 3);
			break;
		case 0x64:	/* FS override */
		case 0x65:	/* GS override */
			set_seg_override(c, c->b & 7);
			break;
		case 0x40 ... 0x4f: /* REX */
			if (mode != X86EMUL_MODE_PROT64)
				goto done_prefixes;
			c->rex_prefix = c->b;
			continue;
		case 0xf0:	/* LOCK */
			c->lock_prefix = 1;
			break;
		case 0xf2:	/* REPNE/REPNZ */
		case 0xf3:	/* REP/REPE/REPZ */
3439
			c->rep_prefix = c->b;
3440 3441 3442 3443 3444 3445 3446 3447 3448 3449 3450 3451 3452
			break;
		default:
			goto done_prefixes;
		}

		/* Any legacy prefix after a REX prefix nullifies its effect. */

		c->rex_prefix = 0;
	}

done_prefixes:

	/* REX prefix. */
3453 3454
	if (c->rex_prefix & 8)
		c->op_bytes = 8;	/* REX.W */
3455 3456 3457

	/* Opcode byte(s). */
	opcode = opcode_table[c->b];
3458 3459 3460 3461 3462
	/* Two-byte opcode? */
	if (c->b == 0x0f) {
		c->twobyte = 1;
		c->b = insn_fetch(u8, 1, c->eip);
		opcode = twobyte_table[c->b];
3463 3464 3465
	}
	c->d = opcode.flags;

3466 3467 3468 3469 3470 3471 3472 3473 3474 3475 3476 3477 3478 3479 3480 3481 3482 3483
	while (c->d & GroupMask) {
		switch (c->d & GroupMask) {
		case Group:
			c->modrm = insn_fetch(u8, 1, c->eip);
			--c->eip;
			goffset = (c->modrm >> 3) & 7;
			opcode = opcode.u.group[goffset];
			break;
		case GroupDual:
			c->modrm = insn_fetch(u8, 1, c->eip);
			--c->eip;
			goffset = (c->modrm >> 3) & 7;
			if ((c->modrm >> 6) == 3)
				opcode = opcode.u.gdual->mod3[goffset];
			else
				opcode = opcode.u.gdual->mod012[goffset];
			break;
		case RMExt:
3484 3485
			goffset = c->modrm & 7;
			opcode = opcode.u.group[goffset];
3486 3487 3488 3489 3490 3491 3492 3493 3494 3495 3496 3497 3498
			break;
		case Prefix:
			if (c->rep_prefix && op_prefix)
				return X86EMUL_UNHANDLEABLE;
			simd_prefix = op_prefix ? 0x66 : c->rep_prefix;
			switch (simd_prefix) {
			case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
			case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
			case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
			case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
			}
			break;
		default:
3499 3500
			return X86EMUL_UNHANDLEABLE;
		}
3501 3502

		c->d &= ~GroupMask;
3503 3504 3505
		c->d |= opcode.flags;
	}

3506
	c->execute = opcode.u.execute;
3507
	c->check_perm = opcode.check_perm;
3508
	c->intercept = opcode.intercept;
3509 3510

	/* Unrecognised? */
A
Avi Kivity 已提交
3511
	if (c->d == 0 || (c->d & Undefined))
3512 3513
		return -1;

3514 3515 3516
	if (!(c->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
		return -1;

3517 3518 3519
	if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
		c->op_bytes = 8;

3520 3521 3522 3523 3524 3525 3526
	if (c->d & Op3264) {
		if (mode == X86EMUL_MODE_PROT64)
			c->op_bytes = 8;
		else
			c->op_bytes = 4;
	}

A
Avi Kivity 已提交
3527 3528 3529
	if (c->d & Sse)
		c->op_bytes = 16;

3530
	/* ModRM and SIB bytes. */
3531
	if (c->d & ModRM) {
3532
		rc = decode_modrm(ctxt, ops, &memop);
3533 3534 3535
		if (!c->has_seg_override)
			set_seg_override(c, c->modrm_seg);
	} else if (c->d & MemAbs)
3536
		rc = decode_abs(ctxt, ops, &memop);
3537 3538 3539 3540 3541 3542
	if (rc != X86EMUL_CONTINUE)
		goto done;

	if (!c->has_seg_override)
		set_seg_override(c, VCPU_SREG_DS);

3543
	memop.addr.mem.seg = seg_override(ctxt, c);
3544

3545
	if (memop.type == OP_MEM && c->ad_bytes != 8)
3546
		memop.addr.mem.ea = (u32)memop.addr.mem.ea;
3547

3548
	if (memop.type == OP_MEM && c->rip_relative)
3549
		memop.addr.mem.ea += c->eip;
3550 3551 3552 3553 3554 3555 3556 3557 3558

	/*
	 * Decode and fetch the source operand: register, memory
	 * or immediate.
	 */
	switch (c->d & SrcMask) {
	case SrcNone:
		break;
	case SrcReg:
A
Avi Kivity 已提交
3559
		decode_register_operand(ctxt, &c->src, c, 0);
3560 3561
		break;
	case SrcMem16:
3562
		memop.bytes = 2;
3563 3564
		goto srcmem_common;
	case SrcMem32:
3565
		memop.bytes = 4;
3566 3567
		goto srcmem_common;
	case SrcMem:
3568
		memop.bytes = (c->d & ByteOp) ? 1 :
3569 3570
							   c->op_bytes;
	srcmem_common:
3571
		c->src = memop;
3572
		break;
3573
	case SrcImmU16:
3574 3575
		rc = decode_imm(ctxt, &c->src, 2, false);
		break;
3576
	case SrcImm:
3577 3578
		rc = decode_imm(ctxt, &c->src, imm_size(c), true);
		break;
3579
	case SrcImmU:
3580
		rc = decode_imm(ctxt, &c->src, imm_size(c), false);
3581 3582
		break;
	case SrcImmByte:
3583 3584
		rc = decode_imm(ctxt, &c->src, 1, true);
		break;
3585
	case SrcImmUByte:
3586
		rc = decode_imm(ctxt, &c->src, 1, false);
3587 3588 3589 3590
		break;
	case SrcAcc:
		c->src.type = OP_REG;
		c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3591
		c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
3592
		fetch_register_operand(&c->src);
3593 3594 3595 3596 3597 3598 3599 3600
		break;
	case SrcOne:
		c->src.bytes = 1;
		c->src.val = 1;
		break;
	case SrcSI:
		c->src.type = OP_MEM;
		c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3601 3602
		c->src.addr.mem.ea =
			register_address(c, c->regs[VCPU_REGS_RSI]);
3603
		c->src.addr.mem.seg = seg_override(ctxt, c);
3604 3605 3606 3607
		c->src.val = 0;
		break;
	case SrcImmFAddr:
		c->src.type = OP_IMM;
3608
		c->src.addr.mem.ea = c->eip;
3609 3610 3611 3612
		c->src.bytes = c->op_bytes + 2;
		insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
		break;
	case SrcMemFAddr:
3613 3614
		memop.bytes = c->op_bytes + 2;
		goto srcmem_common;
3615 3616 3617
		break;
	}

3618 3619 3620
	if (rc != X86EMUL_CONTINUE)
		goto done;

3621 3622 3623 3624 3625 3626 3627 3628 3629 3630 3631 3632
	/*
	 * Decode and fetch the second source operand: register, memory
	 * or immediate.
	 */
	switch (c->d & Src2Mask) {
	case Src2None:
		break;
	case Src2CL:
		c->src2.bytes = 1;
		c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
		break;
	case Src2ImmByte:
3633
		rc = decode_imm(ctxt, &c->src2, 1, true);
3634 3635 3636 3637 3638
		break;
	case Src2One:
		c->src2.bytes = 1;
		c->src2.val = 1;
		break;
3639 3640 3641
	case Src2Imm:
		rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
		break;
3642 3643
	}

3644 3645 3646
	if (rc != X86EMUL_CONTINUE)
		goto done;

3647 3648 3649
	/* Decode and fetch the destination operand: register or memory. */
	switch (c->d & DstMask) {
	case DstReg:
A
Avi Kivity 已提交
3650
		decode_register_operand(ctxt, &c->dst, c,
3651 3652
			 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
		break;
3653 3654
	case DstImmUByte:
		c->dst.type = OP_IMM;
3655
		c->dst.addr.mem.ea = c->eip;
3656 3657 3658
		c->dst.bytes = 1;
		c->dst.val = insn_fetch(u8, 1, c->eip);
		break;
3659 3660
	case DstMem:
	case DstMem64:
3661
		c->dst = memop;
3662 3663 3664 3665
		if ((c->d & DstMask) == DstMem64)
			c->dst.bytes = 8;
		else
			c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3666 3667
		if (c->d & BitOp)
			fetch_bit_operand(c);
3668
		c->dst.orig_val = c->dst.val;
3669 3670 3671 3672
		break;
	case DstAcc:
		c->dst.type = OP_REG;
		c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3673
		c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
3674
		fetch_register_operand(&c->dst);
3675 3676 3677 3678 3679
		c->dst.orig_val = c->dst.val;
		break;
	case DstDI:
		c->dst.type = OP_MEM;
		c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3680 3681 3682
		c->dst.addr.mem.ea =
			register_address(c, c->regs[VCPU_REGS_RDI]);
		c->dst.addr.mem.seg = VCPU_SREG_ES;
3683 3684
		c->dst.val = 0;
		break;
3685 3686 3687 3688 3689
	case ImplicitOps:
		/* Special instructions do their own operand decoding. */
	default:
		c->dst.type = OP_NONE; /* Disable writeback. */
		return 0;
3690 3691 3692
	}

done:
3693
	return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
3694 3695
}

3696 3697 3698 3699 3700 3701 3702 3703 3704 3705 3706 3707 3708 3709 3710 3711 3712 3713 3714 3715 3716 3717
static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
{
	struct decode_cache *c = &ctxt->decode;

	/* The second termination condition only applies for REPE
	 * and REPNE. Test if the repeat string operation prefix is
	 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
	 * corresponding termination condition according to:
	 * 	- if REPE/REPZ and ZF = 0 then done
	 * 	- if REPNE/REPNZ and ZF = 1 then done
	 */
	if (((c->b == 0xa6) || (c->b == 0xa7) ||
	     (c->b == 0xae) || (c->b == 0xaf))
	    && (((c->rep_prefix == REPE_PREFIX) &&
		 ((ctxt->eflags & EFLG_ZF) == 0))
		|| ((c->rep_prefix == REPNE_PREFIX) &&
		    ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
		return true;

	return false;
}

3718
int
3719
x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
3720
{
3721
	struct x86_emulate_ops *ops = ctxt->ops;
3722 3723
	u64 msr_data;
	struct decode_cache *c = &ctxt->decode;
3724
	int rc = X86EMUL_CONTINUE;
3725
	int saved_dst_type = c->dst.type;
3726
	int irq; /* Used for int 3, int, and into */
3727

3728
	ctxt->decode.mem_read.pos = 0;
3729

3730
	if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
3731
		rc = emulate_ud(ctxt);
3732 3733 3734
		goto done;
	}

3735
	/* LOCK prefix is allowed only with some instructions */
3736
	if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
3737
		rc = emulate_ud(ctxt);
3738 3739 3740
		goto done;
	}

3741
	if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
3742
		rc = emulate_ud(ctxt);
3743 3744 3745
		goto done;
	}

A
Avi Kivity 已提交
3746
	if ((c->d & Sse)
3747 3748
	    && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)
		|| !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
A
Avi Kivity 已提交
3749 3750 3751 3752
		rc = emulate_ud(ctxt);
		goto done;
	}

3753
	if ((c->d & Sse) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
A
Avi Kivity 已提交
3754 3755 3756 3757
		rc = emulate_nm(ctxt);
		goto done;
	}

3758
	if (unlikely(ctxt->guest_mode) && c->intercept) {
3759 3760
		rc = emulator_check_intercept(ctxt, c->intercept,
					      X86_ICPT_PRE_EXCEPT);
3761 3762 3763 3764
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

3765
	/* Privileged instruction can be executed only in CPL=0 */
3766
	if ((c->d & Priv) && ops->cpl(ctxt)) {
3767
		rc = emulate_gp(ctxt, 0);
3768 3769 3770
		goto done;
	}

3771 3772 3773 3774 3775 3776
	/* Instruction can only be executed in protected mode */
	if ((c->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
		rc = emulate_ud(ctxt);
		goto done;
	}

3777 3778 3779 3780 3781 3782 3783
	/* Do instruction specific permission checks */
	if (c->check_perm) {
		rc = c->check_perm(ctxt);
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

3784
	if (unlikely(ctxt->guest_mode) && c->intercept) {
3785 3786
		rc = emulator_check_intercept(ctxt, c->intercept,
					      X86_ICPT_POST_EXCEPT);
3787 3788 3789 3790
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

3791 3792
	if (c->rep_prefix && (c->d & String)) {
		/* All REP prefixes have the same first termination condition */
3793
		if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
3794
			ctxt->eip = c->eip;
3795 3796 3797 3798
			goto done;
		}
	}

3799
	if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
3800 3801
		rc = segmented_read(ctxt, c->src.addr.mem,
				    c->src.valptr, c->src.bytes);
3802
		if (rc != X86EMUL_CONTINUE)
3803
			goto done;
3804
		c->src.orig_val64 = c->src.val64;
3805 3806
	}

3807
	if (c->src2.type == OP_MEM) {
3808 3809
		rc = segmented_read(ctxt, c->src2.addr.mem,
				    &c->src2.val, c->src2.bytes);
3810 3811 3812 3813
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

3814 3815 3816 3817
	if ((c->d & DstMask) == ImplicitOps)
		goto special_insn;


3818 3819
	if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
		/* optimisation - avoid slow emulated read if Mov */
3820
		rc = segmented_read(ctxt, c->dst.addr.mem,
3821
				   &c->dst.val, c->dst.bytes);
3822 3823
		if (rc != X86EMUL_CONTINUE)
			goto done;
3824
	}
3825
	c->dst.orig_val = c->dst.val;
3826

3827 3828
special_insn:

3829
	if (unlikely(ctxt->guest_mode) && c->intercept) {
3830 3831
		rc = emulator_check_intercept(ctxt, c->intercept,
					      X86_ICPT_POST_MEMACCESS);
3832 3833 3834 3835
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

3836 3837 3838 3839 3840 3841 3842
	if (c->execute) {
		rc = c->execute(ctxt);
		if (rc != X86EMUL_CONTINUE)
			goto done;
		goto writeback;
	}

3843
	if (c->twobyte)
A
Avi Kivity 已提交
3844 3845
		goto twobyte_insn;

3846
	switch (c->b) {
3847
	case 0x06:		/* push es */
3848
		rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
3849 3850 3851 3852 3853
		break;
	case 0x07:		/* pop es */
		rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
		break;
	case 0x0e:		/* push cs */
3854
		rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
3855 3856
		break;
	case 0x16:		/* push ss */
3857
		rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
3858 3859 3860 3861 3862
		break;
	case 0x17:		/* pop ss */
		rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
		break;
	case 0x1e:		/* push ds */
3863
		rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
3864 3865 3866 3867
		break;
	case 0x1f:		/* pop ds */
		rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
		break;
3868 3869 3870 3871 3872 3873
	case 0x40 ... 0x47: /* inc r16/r32 */
		emulate_1op("inc", c->dst, ctxt->eflags);
		break;
	case 0x48 ... 0x4f: /* dec r16/r32 */
		emulate_1op("dec", c->dst, ctxt->eflags);
		break;
A
Avi Kivity 已提交
3874
	case 0x63:		/* movsxd */
3875
		if (ctxt->mode != X86EMUL_MODE_PROT64)
A
Avi Kivity 已提交
3876
			goto cannot_emulate;
3877
		c->dst.val = (s32) c->src.val;
A
Avi Kivity 已提交
3878
		break;
3879 3880
	case 0x6c:		/* insb */
	case 0x6d:		/* insw/insd */
3881 3882
		c->src.val = c->regs[VCPU_REGS_RDX];
		goto do_io_in;
3883 3884
	case 0x6e:		/* outsb */
	case 0x6f:		/* outsw/outsd */
3885 3886
		c->dst.val = c->regs[VCPU_REGS_RDX];
		goto do_io_out;
3887
		break;
3888
	case 0x70 ... 0x7f: /* jcc (short) */
3889
		if (test_cc(c->b, ctxt->eflags))
3890
			jmp_rel(c, c->src.val);
3891
		break;
A
Avi Kivity 已提交
3892
	case 0x84 ... 0x85:
3893
	test:
3894
		emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
A
Avi Kivity 已提交
3895 3896
		break;
	case 0x86 ... 0x87:	/* xchg */
3897
	xchg:
A
Avi Kivity 已提交
3898
		/* Write back the register source. */
3899 3900
		c->src.val = c->dst.val;
		write_register_operand(&c->src);
A
Avi Kivity 已提交
3901 3902 3903 3904
		/*
		 * Write back the memory destination with implicit LOCK
		 * prefix.
		 */
3905
		c->dst.val = c->src.orig_val;
3906
		c->lock_prefix = 1;
A
Avi Kivity 已提交
3907
		break;
3908 3909
	case 0x8c:  /* mov r/m, sreg */
		if (c->modrm_reg > VCPU_SREG_GS) {
3910
			rc = emulate_ud(ctxt);
3911
			goto done;
3912
		}
3913
		c->dst.val = get_segment_selector(ctxt, c->modrm_reg);
3914
		break;
N
Nitin A Kamble 已提交
3915
	case 0x8d: /* lea r16/r32, m */
3916
		c->dst.val = c->src.addr.mem.ea;
N
Nitin A Kamble 已提交
3917
		break;
3918 3919 3920 3921
	case 0x8e: { /* mov seg, r/m16 */
		uint16_t sel;

		sel = c->src.val;
3922

3923 3924
		if (c->modrm_reg == VCPU_SREG_CS ||
		    c->modrm_reg > VCPU_SREG_GS) {
3925
			rc = emulate_ud(ctxt);
3926 3927 3928
			goto done;
		}

3929
		if (c->modrm_reg == VCPU_SREG_SS)
3930
			ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3931

3932
		rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
3933 3934 3935 3936

		c->dst.type = OP_NONE;  /* Disable writeback. */
		break;
	}
A
Avi Kivity 已提交
3937
	case 0x8f:		/* pop (sole member of Grp1a) */
3938
		rc = em_grp1a(ctxt);
A
Avi Kivity 已提交
3939
		break;
3940 3941
	case 0x90 ... 0x97: /* nop / xchg reg, rax */
		if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
3942
			break;
3943
		goto xchg;
3944 3945 3946 3947 3948 3949 3950
	case 0x98: /* cbw/cwde/cdqe */
		switch (c->op_bytes) {
		case 2: c->dst.val = (s8)c->dst.val; break;
		case 4: c->dst.val = (s16)c->dst.val; break;
		case 8: c->dst.val = (s32)c->dst.val; break;
		}
		break;
3951 3952
	case 0xa8 ... 0xa9:	/* test ax, imm */
		goto test;
3953
	case 0xc0 ... 0xc1:
3954
		rc = em_grp2(ctxt);
3955
		break;
3956
	case 0xc3: /* ret */
A
Avi Kivity 已提交
3957
		c->dst.type = OP_REG;
3958
		c->dst.addr.reg = &c->eip;
A
Avi Kivity 已提交
3959
		c->dst.bytes = c->op_bytes;
3960 3961
		rc = em_pop(ctxt);
		break;
3962 3963 3964 3965 3966 3967
	case 0xc4:		/* les */
		rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES);
		break;
	case 0xc5:		/* lds */
		rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS);
		break;
3968 3969
	case 0xcb:		/* ret far */
		rc = emulate_ret_far(ctxt, ops);
3970
		break;
3971 3972 3973 3974 3975 3976 3977 3978 3979 3980 3981 3982 3983 3984
	case 0xcc:		/* int3 */
		irq = 3;
		goto do_interrupt;
	case 0xcd:		/* int n */
		irq = c->src.val;
	do_interrupt:
		rc = emulate_int(ctxt, ops, irq);
		break;
	case 0xce:		/* into */
		if (ctxt->eflags & EFLG_OF) {
			irq = 4;
			goto do_interrupt;
		}
		break;
3985 3986
	case 0xcf:		/* iret */
		rc = emulate_iret(ctxt, ops);
3987
		break;
3988
	case 0xd0 ... 0xd1:	/* Grp2 */
3989
		rc = em_grp2(ctxt);
3990 3991 3992
		break;
	case 0xd2 ... 0xd3:	/* Grp2 */
		c->src.val = c->regs[VCPU_REGS_RCX];
3993
		rc = em_grp2(ctxt);
3994
		break;
3995 3996 3997 3998 3999 4000
	case 0xe0 ... 0xe2:	/* loop/loopz/loopnz */
		register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
		if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
		    (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
			jmp_rel(c, c->src.val);
		break;
4001 4002 4003 4004
	case 0xe3:	/* jcxz/jecxz/jrcxz */
		if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
			jmp_rel(c, c->src.val);
		break;
4005 4006
	case 0xe4: 	/* inb */
	case 0xe5: 	/* in */
4007
		goto do_io_in;
4008 4009
	case 0xe6: /* outb */
	case 0xe7: /* out */
4010
		goto do_io_out;
4011
	case 0xe8: /* call (near) */ {
4012
		long int rel = c->src.val;
4013
		c->src.val = (unsigned long) c->eip;
4014
		jmp_rel(c, rel);
4015
		rc = em_push(ctxt);
4016
		break;
4017 4018
	}
	case 0xe9: /* jmp rel */
4019
		goto jmp;
4020 4021
	case 0xea: /* jmp far */
		rc = em_jmp_far(ctxt);
4022 4023 4024
		break;
	case 0xeb:
	      jmp:		/* jmp rel short */
4025
		jmp_rel(c, c->src.val);
4026
		c->dst.type = OP_NONE; /* Disable writeback. */
4027
		break;
4028 4029
	case 0xec: /* in al,dx */
	case 0xed: /* in (e/r)ax,dx */
4030 4031
		c->src.val = c->regs[VCPU_REGS_RDX];
	do_io_in:
4032 4033
		if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
				     &c->dst.val))
4034 4035
			goto done; /* IO is needed */
		break;
4036 4037
	case 0xee: /* out dx,al */
	case 0xef: /* out dx,(e/r)ax */
4038
		c->dst.val = c->regs[VCPU_REGS_RDX];
4039
	do_io_out:
4040 4041
		ops->pio_out_emulated(ctxt, c->src.bytes, c->dst.val,
				      &c->src.val, 1);
4042
		c->dst.type = OP_NONE;	/* Disable writeback. */
4043
		break;
4044
	case 0xf4:              /* hlt */
4045
		ctxt->ops->halt(ctxt);
4046
		break;
4047 4048 4049 4050
	case 0xf5:	/* cmc */
		/* complement carry flag from eflags reg */
		ctxt->eflags ^= EFLG_CF;
		break;
4051
	case 0xf6 ... 0xf7:	/* Grp3 */
4052
		rc = em_grp3(ctxt);
4053
		break;
4054 4055 4056
	case 0xf8: /* clc */
		ctxt->eflags &= ~EFLG_CF;
		break;
4057 4058 4059
	case 0xf9: /* stc */
		ctxt->eflags |= EFLG_CF;
		break;
4060
	case 0xfa: /* cli */
4061
		if (emulator_bad_iopl(ctxt, ops)) {
4062
			rc = emulate_gp(ctxt, 0);
4063
			goto done;
4064
		} else
4065
			ctxt->eflags &= ~X86_EFLAGS_IF;
4066 4067
		break;
	case 0xfb: /* sti */
4068
		if (emulator_bad_iopl(ctxt, ops)) {
4069
			rc = emulate_gp(ctxt, 0);
4070 4071
			goto done;
		} else {
4072
			ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
4073 4074
			ctxt->eflags |= X86_EFLAGS_IF;
		}
4075
		break;
4076 4077 4078 4079 4080 4081
	case 0xfc: /* cld */
		ctxt->eflags &= ~EFLG_DF;
		break;
	case 0xfd: /* std */
		ctxt->eflags |= EFLG_DF;
		break;
4082
	case 0xfe: /* Grp4 */
4083
		rc = em_grp45(ctxt);
4084
		break;
4085
	case 0xff: /* Grp5 */
4086 4087
		rc = em_grp45(ctxt);
		break;
4088 4089
	default:
		goto cannot_emulate;
A
Avi Kivity 已提交
4090
	}
4091

4092 4093 4094
	if (rc != X86EMUL_CONTINUE)
		goto done;

4095
writeback:
4096
	rc = writeback(ctxt);
4097
	if (rc != X86EMUL_CONTINUE)
4098 4099
		goto done;

4100 4101 4102 4103 4104 4105
	/*
	 * restore dst type in case the decoding will be reused
	 * (happens for string instruction )
	 */
	c->dst.type = saved_dst_type;

4106
	if ((c->d & SrcMask) == SrcSI)
4107
		string_addr_inc(ctxt, seg_override(ctxt, c),
4108
				VCPU_REGS_RSI, &c->src);
4109 4110

	if ((c->d & DstMask) == DstDI)
4111
		string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
4112
				&c->dst);
4113

4114
	if (c->rep_prefix && (c->d & String)) {
4115
		struct read_cache *r = &ctxt->decode.io_read;
4116
		register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
4117

4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131 4132 4133
		if (!string_insn_completed(ctxt)) {
			/*
			 * Re-enter guest when pio read ahead buffer is empty
			 * or, if it is not used, after each 1024 iteration.
			 */
			if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
			    (r->end == 0 || r->end != r->pos)) {
				/*
				 * Reset read cache. Usually happens before
				 * decode, but since instruction is restarted
				 * we have to do it here.
				 */
				ctxt->decode.mem_read.end = 0;
				return EMULATION_RESTART;
			}
			goto done; /* skip rip writeback */
4134
		}
4135
	}
4136 4137

	ctxt->eip = c->eip;
4138 4139

done:
4140 4141
	if (rc == X86EMUL_PROPAGATE_FAULT)
		ctxt->have_exception = true;
4142 4143 4144
	if (rc == X86EMUL_INTERCEPTED)
		return EMULATION_INTERCEPTED;

4145
	return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
A
Avi Kivity 已提交
4146 4147

twobyte_insn:
4148
	switch (c->b) {
4149
	case 0x05: 		/* syscall */
4150
		rc = emulate_syscall(ctxt, ops);
4151
		break;
4152
	case 0x06:
4153
		rc = em_clts(ctxt);
4154 4155
		break;
	case 0x09:		/* wbinvd */
4156
		(ctxt->ops->wbinvd)(ctxt);
4157 4158
		break;
	case 0x08:		/* invd */
4159 4160 4161 4162
	case 0x0d:		/* GrpP (prefetch) */
	case 0x18:		/* Grp16 (prefetch/nop) */
		break;
	case 0x20: /* mov cr, reg */
4163
		c->dst.val = ops->get_cr(ctxt, c->modrm_reg);
4164
		break;
A
Avi Kivity 已提交
4165
	case 0x21: /* mov from dr to reg */
4166
		ops->get_dr(ctxt, c->modrm_reg, &c->dst.val);
A
Avi Kivity 已提交
4167
		break;
4168
	case 0x22: /* mov reg, cr */
4169
		if (ops->set_cr(ctxt, c->modrm_reg, c->src.val)) {
4170
			emulate_gp(ctxt, 0);
4171
			rc = X86EMUL_PROPAGATE_FAULT;
4172 4173
			goto done;
		}
4174 4175
		c->dst.type = OP_NONE;
		break;
A
Avi Kivity 已提交
4176
	case 0x23: /* mov from reg to dr */
4177
		if (ops->set_dr(ctxt, c->modrm_reg, c->src.val &
4178
				((ctxt->mode == X86EMUL_MODE_PROT64) ?
4179
				 ~0ULL : ~0U)) < 0) {
4180
			/* #UD condition is already handled by the code above */
4181
			emulate_gp(ctxt, 0);
4182
			rc = X86EMUL_PROPAGATE_FAULT;
4183 4184 4185
			goto done;
		}

4186
		c->dst.type = OP_NONE;	/* no writeback */
A
Avi Kivity 已提交
4187
		break;
4188 4189 4190 4191
	case 0x30:
		/* wrmsr */
		msr_data = (u32)c->regs[VCPU_REGS_RAX]
			| ((u64)c->regs[VCPU_REGS_RDX] << 32);
4192
		if (ops->set_msr(ctxt, c->regs[VCPU_REGS_RCX], msr_data)) {
4193
			emulate_gp(ctxt, 0);
4194
			rc = X86EMUL_PROPAGATE_FAULT;
4195
			goto done;
4196 4197 4198 4199 4200
		}
		rc = X86EMUL_CONTINUE;
		break;
	case 0x32:
		/* rdmsr */
4201
		if (ops->get_msr(ctxt, c->regs[VCPU_REGS_RCX], &msr_data)) {
4202
			emulate_gp(ctxt, 0);
4203
			rc = X86EMUL_PROPAGATE_FAULT;
4204
			goto done;
4205 4206 4207 4208 4209 4210
		} else {
			c->regs[VCPU_REGS_RAX] = (u32)msr_data;
			c->regs[VCPU_REGS_RDX] = msr_data >> 32;
		}
		rc = X86EMUL_CONTINUE;
		break;
4211
	case 0x34:		/* sysenter */
4212
		rc = emulate_sysenter(ctxt, ops);
4213 4214
		break;
	case 0x35:		/* sysexit */
4215
		rc = emulate_sysexit(ctxt, ops);
4216
		break;
A
Avi Kivity 已提交
4217
	case 0x40 ... 0x4f:	/* cmov */
4218
		c->dst.val = c->dst.orig_val = c->src.val;
4219 4220
		if (!test_cc(c->b, ctxt->eflags))
			c->dst.type = OP_NONE; /* no writeback */
A
Avi Kivity 已提交
4221
		break;
4222
	case 0x80 ... 0x8f: /* jnz rel, etc*/
4223
		if (test_cc(c->b, ctxt->eflags))
4224
			jmp_rel(c, c->src.val);
4225
		break;
4226 4227 4228
	case 0x90 ... 0x9f:     /* setcc r/m8 */
		c->dst.val = test_cc(c->b, ctxt->eflags);
		break;
4229
	case 0xa0:	  /* push fs */
4230
		rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
4231 4232 4233 4234
		break;
	case 0xa1:	 /* pop fs */
		rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
		break;
4235 4236
	case 0xa3:
	      bt:		/* bt */
Q
Qing He 已提交
4237
		c->dst.type = OP_NONE;
4238 4239
		/* only subword offset */
		c->src.val &= (c->dst.bytes << 3) - 1;
4240
		emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
4241
		break;
4242 4243 4244 4245
	case 0xa4: /* shld imm8, r, r/m */
	case 0xa5: /* shld cl, r, r/m */
		emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
		break;
4246
	case 0xa8:	/* push gs */
4247
		rc = emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
4248 4249 4250 4251
		break;
	case 0xa9:	/* pop gs */
		rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
		break;
4252 4253
	case 0xab:
	      bts:		/* bts */
4254
		emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
4255
		break;
4256 4257 4258 4259
	case 0xac: /* shrd imm8, r, r/m */
	case 0xad: /* shrd cl, r, r/m */
		emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
		break;
4260 4261
	case 0xae:              /* clflush */
		break;
A
Avi Kivity 已提交
4262 4263 4264 4265 4266
	case 0xb0 ... 0xb1:	/* cmpxchg */
		/*
		 * Save real source value, then compare EAX against
		 * destination.
		 */
4267 4268
		c->src.orig_val = c->src.val;
		c->src.val = c->regs[VCPU_REGS_RAX];
4269 4270
		emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
		if (ctxt->eflags & EFLG_ZF) {
A
Avi Kivity 已提交
4271
			/* Success: write back to memory. */
4272
			c->dst.val = c->src.orig_val;
A
Avi Kivity 已提交
4273 4274
		} else {
			/* Failure: write the value we saw to EAX. */
4275
			c->dst.type = OP_REG;
4276
			c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
A
Avi Kivity 已提交
4277 4278
		}
		break;
4279 4280 4281
	case 0xb2:		/* lss */
		rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS);
		break;
A
Avi Kivity 已提交
4282 4283
	case 0xb3:
	      btr:		/* btr */
4284
		emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
A
Avi Kivity 已提交
4285
		break;
4286 4287 4288 4289 4290 4291
	case 0xb4:		/* lfs */
		rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS);
		break;
	case 0xb5:		/* lgs */
		rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS);
		break;
A
Avi Kivity 已提交
4292
	case 0xb6 ... 0xb7:	/* movzx */
4293 4294 4295
		c->dst.bytes = c->op_bytes;
		c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
						       : (u16) c->src.val;
A
Avi Kivity 已提交
4296 4297
		break;
	case 0xba:		/* Grp8 */
4298
		switch (c->modrm_reg & 3) {
A
Avi Kivity 已提交
4299 4300 4301 4302 4303 4304 4305 4306 4307 4308
		case 0:
			goto bt;
		case 1:
			goto bts;
		case 2:
			goto btr;
		case 3:
			goto btc;
		}
		break;
4309 4310
	case 0xbb:
	      btc:		/* btc */
4311
		emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
4312
		break;
4313 4314 4315 4316 4317 4318 4319 4320 4321 4322 4323 4324 4325 4326 4327 4328 4329 4330 4331 4332 4333 4334 4335 4336
	case 0xbc: {		/* bsf */
		u8 zf;
		__asm__ ("bsf %2, %0; setz %1"
			 : "=r"(c->dst.val), "=q"(zf)
			 : "r"(c->src.val));
		ctxt->eflags &= ~X86_EFLAGS_ZF;
		if (zf) {
			ctxt->eflags |= X86_EFLAGS_ZF;
			c->dst.type = OP_NONE;	/* Disable writeback. */
		}
		break;
	}
	case 0xbd: {		/* bsr */
		u8 zf;
		__asm__ ("bsr %2, %0; setz %1"
			 : "=r"(c->dst.val), "=q"(zf)
			 : "r"(c->src.val));
		ctxt->eflags &= ~X86_EFLAGS_ZF;
		if (zf) {
			ctxt->eflags |= X86_EFLAGS_ZF;
			c->dst.type = OP_NONE;	/* Disable writeback. */
		}
		break;
	}
A
Avi Kivity 已提交
4337
	case 0xbe ... 0xbf:	/* movsx */
4338 4339 4340
		c->dst.bytes = c->op_bytes;
		c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
							(s16) c->src.val;
A
Avi Kivity 已提交
4341
		break;
4342 4343 4344 4345 4346 4347
	case 0xc0 ... 0xc1:	/* xadd */
		emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
		/* Write back the register source. */
		c->src.val = c->dst.orig_val;
		write_register_operand(&c->src);
		break;
4348
	case 0xc3:		/* movnti */
4349 4350 4351
		c->dst.bytes = c->op_bytes;
		c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
							(u64) c->src.val;
4352
		break;
A
Avi Kivity 已提交
4353
	case 0xc7:		/* Grp9 (cmpxchg8b) */
4354
		rc = em_grp9(ctxt);
4355
		break;
4356 4357
	default:
		goto cannot_emulate;
A
Avi Kivity 已提交
4358
	}
4359 4360 4361 4362

	if (rc != X86EMUL_CONTINUE)
		goto done;

A
Avi Kivity 已提交
4363 4364 4365
	goto writeback;

cannot_emulate:
4366
	return EMULATION_FAILED;
A
Avi Kivity 已提交
4367
}