emulate.c 149.8 KB
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/******************************************************************************
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 * emulate.c
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 *
 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
 *
 * Copyright (c) 2005 Keir Fraser
 *
 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
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 * privileged instructions:
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 *
 * Copyright (C) 2006 Qumranet
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 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
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 *
 *   Avi Kivity <avi@qumranet.com>
 *   Yaniv Kamay <yaniv@qumranet.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
 */

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#include <linux/kvm_host.h>
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#include "kvm_cache_regs.h"
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#include <asm/kvm_emulate.h>
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#include <linux/stringify.h>
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#include <asm/debugreg.h>
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#include <asm/nospec-branch.h>
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#include "x86.h"
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#include "tss.h"
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#include "mmu.h"
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#include "pmu.h"
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/*
 * Operand types
 */
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#define OpNone             0ull
#define OpImplicit         1ull  /* No generic decode */
#define OpReg              2ull  /* Register */
#define OpMem              3ull  /* Memory */
#define OpAcc              4ull  /* Accumulator: AL/AX/EAX/RAX */
#define OpDI               5ull  /* ES:DI/EDI/RDI */
#define OpMem64            6ull  /* Memory, 64-bit */
#define OpImmUByte         7ull  /* Zero-extended 8-bit immediate */
#define OpDX               8ull  /* DX register */
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#define OpCL               9ull  /* CL register (for shifts) */
#define OpImmByte         10ull  /* 8-bit sign extended immediate */
#define OpOne             11ull  /* Implied 1 */
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#define OpImm             12ull  /* Sign extended up to 32-bit immediate */
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#define OpMem16           13ull  /* Memory operand (16-bit). */
#define OpMem32           14ull  /* Memory operand (32-bit). */
#define OpImmU            15ull  /* Immediate operand, zero extended */
#define OpSI              16ull  /* SI/ESI/RSI */
#define OpImmFAddr        17ull  /* Immediate far address */
#define OpMemFAddr        18ull  /* Far address in memory */
#define OpImmU16          19ull  /* Immediate operand, 16 bits, zero extended */
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#define OpES              20ull  /* ES */
#define OpCS              21ull  /* CS */
#define OpSS              22ull  /* SS */
#define OpDS              23ull  /* DS */
#define OpFS              24ull  /* FS */
#define OpGS              25ull  /* GS */
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#define OpMem8            26ull  /* 8-bit zero extended memory operand */
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#define OpImm64           27ull  /* Sign extended 16/32/64-bit immediate */
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#define OpXLat            28ull  /* memory at BX/EBX/RBX + zero-extended AL */
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#define OpAccLo           29ull  /* Low part of extended acc (AX/AX/EAX/RAX) */
#define OpAccHi           30ull  /* High part of extended acc (-/DX/EDX/RDX) */
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#define OpBits             5  /* Width of operand field */
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#define OpMask             ((1ull << OpBits) - 1)
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/*
 * Opcode effective-address decode tables.
 * Note that we only emulate instructions that have at least one memory
 * operand (excluding implicit stack references). We assume that stack
 * references and instruction fetches will never occur in special memory
 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
 * not be handled.
 */

/* Operand sizes: 8-bit operands or specified/overridden size. */
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#define ByteOp      (1<<0)	/* 8-bit operands. */
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/* Destination operand type. */
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#define DstShift    1
#define ImplicitOps (OpImplicit << DstShift)
#define DstReg      (OpReg << DstShift)
#define DstMem      (OpMem << DstShift)
#define DstAcc      (OpAcc << DstShift)
#define DstDI       (OpDI << DstShift)
#define DstMem64    (OpMem64 << DstShift)
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#define DstMem16    (OpMem16 << DstShift)
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#define DstImmUByte (OpImmUByte << DstShift)
#define DstDX       (OpDX << DstShift)
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#define DstAccLo    (OpAccLo << DstShift)
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#define DstMask     (OpMask << DstShift)
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/* Source operand type. */
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#define SrcShift    6
#define SrcNone     (OpNone << SrcShift)
#define SrcReg      (OpReg << SrcShift)
#define SrcMem      (OpMem << SrcShift)
#define SrcMem16    (OpMem16 << SrcShift)
#define SrcMem32    (OpMem32 << SrcShift)
#define SrcImm      (OpImm << SrcShift)
#define SrcImmByte  (OpImmByte << SrcShift)
#define SrcOne      (OpOne << SrcShift)
#define SrcImmUByte (OpImmUByte << SrcShift)
#define SrcImmU     (OpImmU << SrcShift)
#define SrcSI       (OpSI << SrcShift)
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#define SrcXLat     (OpXLat << SrcShift)
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#define SrcImmFAddr (OpImmFAddr << SrcShift)
#define SrcMemFAddr (OpMemFAddr << SrcShift)
#define SrcAcc      (OpAcc << SrcShift)
#define SrcImmU16   (OpImmU16 << SrcShift)
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#define SrcImm64    (OpImm64 << SrcShift)
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#define SrcDX       (OpDX << SrcShift)
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#define SrcMem8     (OpMem8 << SrcShift)
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#define SrcAccHi    (OpAccHi << SrcShift)
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#define SrcMask     (OpMask << SrcShift)
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#define BitOp       (1<<11)
#define MemAbs      (1<<12)      /* Memory operand is absolute displacement */
#define String      (1<<13)     /* String instruction (rep capable) */
#define Stack       (1<<14)     /* Stack instruction (push/pop) */
#define GroupMask   (7<<15)     /* Opcode uses one of the group mechanisms */
#define Group       (1<<15)     /* Bits 3:5 of modrm byte extend opcode */
#define GroupDual   (2<<15)     /* Alternate decoding of mod == 3 */
#define Prefix      (3<<15)     /* Instruction varies with 66/f2/f3 prefix */
#define RMExt       (4<<15)     /* Opcode extension in ModRM r/m if mod == 3 */
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#define Escape      (5<<15)     /* Escape to coprocessor instruction */
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#define InstrDual   (6<<15)     /* Alternate instruction decoding of mod == 3 */
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#define ModeDual    (7<<15)     /* Different instruction for 32/64 bit */
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#define Sse         (1<<18)     /* SSE Vector instruction */
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/* Generic ModRM decode. */
#define ModRM       (1<<19)
/* Destination is only written; never read. */
#define Mov         (1<<20)
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/* Misc flags */
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#define Prot        (1<<21) /* instruction generates #UD if not in prot-mode */
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#define EmulateOnUD (1<<22) /* Emulate if unsupported by the host */
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#define NoAccess    (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
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#define Op3264      (1<<24) /* Operand is 64b in long mode, 32b otherwise */
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#define Undefined   (1<<25) /* No Such Instruction */
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#define Lock        (1<<26) /* lock prefix is allowed for the instruction */
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#define Priv        (1<<27) /* instruction generates #GP if current CPL != 0 */
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#define No64	    (1<<28)
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#define PageTable   (1 << 29)   /* instruction used to write page table */
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#define NotImpl     (1 << 30)   /* instruction is not implemented */
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/* Source 2 operand type */
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#define Src2Shift   (31)
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#define Src2None    (OpNone << Src2Shift)
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#define Src2Mem     (OpMem << Src2Shift)
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#define Src2CL      (OpCL << Src2Shift)
#define Src2ImmByte (OpImmByte << Src2Shift)
#define Src2One     (OpOne << Src2Shift)
#define Src2Imm     (OpImm << Src2Shift)
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#define Src2ES      (OpES << Src2Shift)
#define Src2CS      (OpCS << Src2Shift)
#define Src2SS      (OpSS << Src2Shift)
#define Src2DS      (OpDS << Src2Shift)
#define Src2FS      (OpFS << Src2Shift)
#define Src2GS      (OpGS << Src2Shift)
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#define Src2Mask    (OpMask << Src2Shift)
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#define Mmx         ((u64)1 << 40)  /* MMX Vector instruction */
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#define AlignMask   ((u64)7 << 41)
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#define Aligned     ((u64)1 << 41)  /* Explicitly aligned (e.g. MOVDQA) */
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#define Unaligned   ((u64)2 << 41)  /* Explicitly unaligned (e.g. MOVDQU) */
#define Avx         ((u64)3 << 41)  /* Advanced Vector Extensions */
#define Aligned16   ((u64)4 << 41)  /* Aligned to 16 byte boundary (e.g. FXSAVE) */
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#define Fastop      ((u64)1 << 44)  /* Use opcode::u.fastop */
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#define NoWrite     ((u64)1 << 45)  /* No writeback */
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#define SrcWrite    ((u64)1 << 46)  /* Write back src operand */
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#define NoMod	    ((u64)1 << 47)  /* Mod field is ignored */
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#define Intercept   ((u64)1 << 48)  /* Has valid intercept field */
#define CheckPerm   ((u64)1 << 49)  /* Has valid check_perm field */
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#define PrivUD      ((u64)1 << 51)  /* #UD instead of #GP on CPL > 0 */
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#define NearBranch  ((u64)1 << 52)  /* Near branches */
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#define No16	    ((u64)1 << 53)  /* No 16 bit operand */
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#define IncSP       ((u64)1 << 54)  /* SP is incremented before ModRM calc */
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#define TwoMemOp    ((u64)1 << 55)  /* Instruction has two memory operand */
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#define DstXacc     (DstAccLo | SrcAccHi | SrcWrite)
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#define X2(x...) x, x
#define X3(x...) X2(x), x
#define X4(x...) X2(x), X2(x)
#define X5(x...) X4(x), x
#define X6(x...) X4(x), X2(x)
#define X7(x...) X4(x), X3(x)
#define X8(x...) X4(x), X4(x)
#define X16(x...) X8(x), X8(x)
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#define NR_FASTOP (ilog2(sizeof(ulong)) + 1)
#define FASTOP_SIZE 8

/*
 * fastop functions have a special calling convention:
 *
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 * dst:    rax        (in/out)
 * src:    rdx        (in/out)
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 * src2:   rcx        (in)
 * flags:  rflags     (in/out)
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 * ex:     rsi        (in:fastop pointer, out:zero if exception)
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 *
 * Moreover, they are all exactly FASTOP_SIZE bytes long, so functions for
 * different operand sizes can be reached by calculation, rather than a jump
 * table (which would be bigger than the code).
 *
 * fastop functions are declared as taking a never-defined fastop parameter,
 * so they can't be called from C directly.
 */

struct fastop;

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struct opcode {
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	u64 flags : 56;
	u64 intercept : 8;
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	union {
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		int (*execute)(struct x86_emulate_ctxt *ctxt);
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		const struct opcode *group;
		const struct group_dual *gdual;
		const struct gprefix *gprefix;
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		const struct escape *esc;
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		const struct instr_dual *idual;
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		const struct mode_dual *mdual;
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		void (*fastop)(struct fastop *fake);
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	} u;
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	int (*check_perm)(struct x86_emulate_ctxt *ctxt);
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};

struct group_dual {
	struct opcode mod012[8];
	struct opcode mod3[8];
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};

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struct gprefix {
	struct opcode pfx_no;
	struct opcode pfx_66;
	struct opcode pfx_f2;
	struct opcode pfx_f3;
};

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struct escape {
	struct opcode op[8];
	struct opcode high[64];
};

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struct instr_dual {
	struct opcode mod012;
	struct opcode mod3;
};

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struct mode_dual {
	struct opcode mode32;
	struct opcode mode64;
};

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#define EFLG_RESERVED_ZEROS_MASK 0xffc0802a

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enum x86_transfer_type {
	X86_TRANSFER_NONE,
	X86_TRANSFER_CALL_JMP,
	X86_TRANSFER_RET,
	X86_TRANSFER_TASK_SWITCH,
};

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static ulong reg_read(struct x86_emulate_ctxt *ctxt, unsigned nr)
{
	if (!(ctxt->regs_valid & (1 << nr))) {
		ctxt->regs_valid |= 1 << nr;
		ctxt->_regs[nr] = ctxt->ops->read_gpr(ctxt, nr);
	}
	return ctxt->_regs[nr];
}

static ulong *reg_write(struct x86_emulate_ctxt *ctxt, unsigned nr)
{
	ctxt->regs_valid |= 1 << nr;
	ctxt->regs_dirty |= 1 << nr;
	return &ctxt->_regs[nr];
}

static ulong *reg_rmw(struct x86_emulate_ctxt *ctxt, unsigned nr)
{
	reg_read(ctxt, nr);
	return reg_write(ctxt, nr);
}

static void writeback_registers(struct x86_emulate_ctxt *ctxt)
{
	unsigned reg;

	for_each_set_bit(reg, (ulong *)&ctxt->regs_dirty, 16)
		ctxt->ops->write_gpr(ctxt, reg, ctxt->_regs[reg]);
}

static void invalidate_registers(struct x86_emulate_ctxt *ctxt)
{
	ctxt->regs_dirty = 0;
	ctxt->regs_valid = 0;
}

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/*
 * These EFLAGS bits are restored from saved value during emulation, and
 * any changes are written back to the saved value after emulation.
 */
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#define EFLAGS_MASK (X86_EFLAGS_OF|X86_EFLAGS_SF|X86_EFLAGS_ZF|X86_EFLAGS_AF|\
		     X86_EFLAGS_PF|X86_EFLAGS_CF)
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#ifdef CONFIG_X86_64
#define ON64(x) x
#else
#define ON64(x)
#endif

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static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *));

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#define FOP_FUNC(name) \
	".align " __stringify(FASTOP_SIZE) " \n\t" \
	".type " name ", @function \n\t" \
	name ":\n\t"

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#define FOP_RET   "ret \n\t"

#define FOP_START(op) \
	extern void em_##op(struct fastop *fake); \
	asm(".pushsection .text, \"ax\" \n\t" \
	    ".global em_" #op " \n\t" \
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	    FOP_FUNC("em_" #op)
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#define FOP_END \
	    ".popsection")

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#define FOPNOP() \
	FOP_FUNC(__stringify(__UNIQUE_ID(nop))) \
	FOP_RET
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#define FOP1E(op,  dst) \
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	FOP_FUNC(#op "_" #dst) \
	"10: " #op " %" #dst " \n\t" FOP_RET
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#define FOP1EEX(op,  dst) \
	FOP1E(op, dst) _ASM_EXTABLE(10b, kvm_fastop_exception)
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#define FASTOP1(op) \
	FOP_START(op) \
	FOP1E(op##b, al) \
	FOP1E(op##w, ax) \
	FOP1E(op##l, eax) \
	ON64(FOP1E(op##q, rax))	\
	FOP_END

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/* 1-operand, using src2 (for MUL/DIV r/m) */
#define FASTOP1SRC2(op, name) \
	FOP_START(name) \
	FOP1E(op, cl) \
	FOP1E(op, cx) \
	FOP1E(op, ecx) \
	ON64(FOP1E(op, rcx)) \
	FOP_END

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/* 1-operand, using src2 (for MUL/DIV r/m), with exceptions */
#define FASTOP1SRC2EX(op, name) \
	FOP_START(name) \
	FOP1EEX(op, cl) \
	FOP1EEX(op, cx) \
	FOP1EEX(op, ecx) \
	ON64(FOP1EEX(op, rcx)) \
	FOP_END

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#define FOP2E(op,  dst, src)	   \
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	FOP_FUNC(#op "_" #dst "_" #src) \
	#op " %" #src ", %" #dst " \n\t" FOP_RET
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#define FASTOP2(op) \
	FOP_START(op) \
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	FOP2E(op##b, al, dl) \
	FOP2E(op##w, ax, dx) \
	FOP2E(op##l, eax, edx) \
	ON64(FOP2E(op##q, rax, rdx)) \
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	FOP_END

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/* 2 operand, word only */
#define FASTOP2W(op) \
	FOP_START(op) \
	FOPNOP() \
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	FOP2E(op##w, ax, dx) \
	FOP2E(op##l, eax, edx) \
	ON64(FOP2E(op##q, rax, rdx)) \
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	FOP_END

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/* 2 operand, src is CL */
#define FASTOP2CL(op) \
	FOP_START(op) \
	FOP2E(op##b, al, cl) \
	FOP2E(op##w, ax, cl) \
	FOP2E(op##l, eax, cl) \
	ON64(FOP2E(op##q, rax, cl)) \
	FOP_END

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/* 2 operand, src and dest are reversed */
#define FASTOP2R(op, name) \
	FOP_START(name) \
	FOP2E(op##b, dl, al) \
	FOP2E(op##w, dx, ax) \
	FOP2E(op##l, edx, eax) \
	ON64(FOP2E(op##q, rdx, rax)) \
	FOP_END

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#define FOP3E(op,  dst, src, src2) \
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	FOP_FUNC(#op "_" #dst "_" #src "_" #src2) \
	#op " %" #src2 ", %" #src ", %" #dst " \n\t" FOP_RET
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/* 3-operand, word-only, src2=cl */
#define FASTOP3WCL(op) \
	FOP_START(op) \
	FOPNOP() \
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	FOP3E(op##w, ax, dx, cl) \
	FOP3E(op##l, eax, edx, cl) \
	ON64(FOP3E(op##q, rax, rdx, cl)) \
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	FOP_END

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/* Special case for SETcc - 1 instruction per cc */
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#define FOP_SETCC(op) \
	".align 4 \n\t" \
	".type " #op ", @function \n\t" \
	#op ": \n\t" \
	#op " %al \n\t" \
	FOP_RET
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asm(".pushsection .fixup, \"ax\"\n"
    ".global kvm_fastop_exception \n"
    "kvm_fastop_exception: xor %esi, %esi; ret\n"
    ".popsection");
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FOP_START(setcc)
FOP_SETCC(seto)
FOP_SETCC(setno)
FOP_SETCC(setc)
FOP_SETCC(setnc)
FOP_SETCC(setz)
FOP_SETCC(setnz)
FOP_SETCC(setbe)
FOP_SETCC(setnbe)
FOP_SETCC(sets)
FOP_SETCC(setns)
FOP_SETCC(setp)
FOP_SETCC(setnp)
FOP_SETCC(setl)
FOP_SETCC(setnl)
FOP_SETCC(setle)
FOP_SETCC(setnle)
FOP_END;

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FOP_START(salc) "pushf; sbb %al, %al; popf \n\t" FOP_RET
FOP_END;

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/*
 * XXX: inoutclob user must know where the argument is being expanded.
 *      Relying on CC_HAVE_ASM_GOTO would allow us to remove _fault.
 */
#define asm_safe(insn, inoutclob...) \
({ \
	int _fault = 0; \
 \
	asm volatile("1:" insn "\n" \
	             "2:\n" \
	             ".pushsection .fixup, \"ax\"\n" \
	             "3: movl $1, %[_fault]\n" \
	             "   jmp  2b\n" \
	             ".popsection\n" \
	             _ASM_EXTABLE(1b, 3b) \
	             : [_fault] "+qm"(_fault) inoutclob ); \
 \
	_fault ? X86EMUL_UNHANDLEABLE : X86EMUL_CONTINUE; \
})

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static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
				    enum x86_intercept intercept,
				    enum x86_intercept_stage stage)
{
	struct x86_instruction_info info = {
		.intercept  = intercept,
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		.rep_prefix = ctxt->rep_prefix,
		.modrm_mod  = ctxt->modrm_mod,
		.modrm_reg  = ctxt->modrm_reg,
		.modrm_rm   = ctxt->modrm_rm,
		.src_val    = ctxt->src.val64,
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		.dst_val    = ctxt->dst.val64,
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		.src_bytes  = ctxt->src.bytes,
		.dst_bytes  = ctxt->dst.bytes,
		.ad_bytes   = ctxt->ad_bytes,
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		.next_rip   = ctxt->eip,
	};

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	return ctxt->ops->intercept(ctxt, &info, stage);
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}

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static void assign_masked(ulong *dest, ulong src, ulong mask)
{
	*dest = (*dest & ~mask) | (src & mask);
}

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static void assign_register(unsigned long *reg, u64 val, int bytes)
{
	/* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
	switch (bytes) {
	case 1:
		*(u8 *)reg = (u8)val;
		break;
	case 2:
		*(u16 *)reg = (u16)val;
		break;
	case 4:
		*reg = (u32)val;
		break;	/* 64b: zero-extend */
	case 8:
		*reg = val;
		break;
	}
}

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static inline unsigned long ad_mask(struct x86_emulate_ctxt *ctxt)
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{
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	return (1UL << (ctxt->ad_bytes << 3)) - 1;
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}

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static ulong stack_mask(struct x86_emulate_ctxt *ctxt)
{
	u16 sel;
	struct desc_struct ss;

	if (ctxt->mode == X86EMUL_MODE_PROT64)
		return ~0UL;
	ctxt->ops->get_segment(ctxt, &sel, &ss, NULL, VCPU_SREG_SS);
	return ~0U >> ((ss.d ^ 1) * 16);  /* d=0: 0xffff; d=1: 0xffffffff */
}

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static int stack_size(struct x86_emulate_ctxt *ctxt)
{
	return (__fls(stack_mask(ctxt)) + 1) >> 3;
}

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/* Access/update address held in a register, based on addressing mode. */
544
static inline unsigned long
545
address_mask(struct x86_emulate_ctxt *ctxt, unsigned long reg)
546
{
547
	if (ctxt->ad_bytes == sizeof(unsigned long))
548 549
		return reg;
	else
550
		return reg & ad_mask(ctxt);
551 552 553
}

static inline unsigned long
554
register_address(struct x86_emulate_ctxt *ctxt, int reg)
555
{
556
	return address_mask(ctxt, reg_read(ctxt, reg));
557 558
}

559 560 561 562 563
static void masked_increment(ulong *reg, ulong mask, int inc)
{
	assign_masked(reg, *reg + inc, mask);
}

564
static inline void
565
register_address_increment(struct x86_emulate_ctxt *ctxt, int reg, int inc)
566
{
567
	ulong *preg = reg_rmw(ctxt, reg);
568

569
	assign_register(preg, *preg + inc, ctxt->ad_bytes);
570 571 572 573
}

static void rsp_increment(struct x86_emulate_ctxt *ctxt, int inc)
{
574
	masked_increment(reg_rmw(ctxt, VCPU_REGS_RSP), stack_mask(ctxt), inc);
575
}
A
Avi Kivity 已提交
576

577 578 579 580 581 582 583
static u32 desc_limit_scaled(struct desc_struct *desc)
{
	u32 limit = get_desc_limit(desc);

	return desc->g ? (limit << 12) | 0xfff : limit;
}

584
static unsigned long seg_base(struct x86_emulate_ctxt *ctxt, int seg)
585 586 587 588
{
	if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
		return 0;

589
	return ctxt->ops->get_cached_segment_base(ctxt, seg);
590 591
}

592 593
static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
			     u32 error, bool valid)
594
{
595
	WARN_ON(vec > 0x1f);
596 597 598
	ctxt->exception.vector = vec;
	ctxt->exception.error_code = error;
	ctxt->exception.error_code_valid = valid;
599
	return X86EMUL_PROPAGATE_FAULT;
600 601
}

602 603 604 605 606
static int emulate_db(struct x86_emulate_ctxt *ctxt)
{
	return emulate_exception(ctxt, DB_VECTOR, 0, false);
}

607
static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
608
{
609
	return emulate_exception(ctxt, GP_VECTOR, err, true);
610 611
}

612 613 614 615 616
static int emulate_ss(struct x86_emulate_ctxt *ctxt, int err)
{
	return emulate_exception(ctxt, SS_VECTOR, err, true);
}

617
static int emulate_ud(struct x86_emulate_ctxt *ctxt)
618
{
619
	return emulate_exception(ctxt, UD_VECTOR, 0, false);
620 621
}

622
static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
623
{
624
	return emulate_exception(ctxt, TS_VECTOR, err, true);
625 626
}

627 628
static int emulate_de(struct x86_emulate_ctxt *ctxt)
{
629
	return emulate_exception(ctxt, DE_VECTOR, 0, false);
630 631
}

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632 633 634 635 636
static int emulate_nm(struct x86_emulate_ctxt *ctxt)
{
	return emulate_exception(ctxt, NM_VECTOR, 0, false);
}

637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656
static u16 get_segment_selector(struct x86_emulate_ctxt *ctxt, unsigned seg)
{
	u16 selector;
	struct desc_struct desc;

	ctxt->ops->get_segment(ctxt, &selector, &desc, NULL, seg);
	return selector;
}

static void set_segment_selector(struct x86_emulate_ctxt *ctxt, u16 selector,
				 unsigned seg)
{
	u16 dummy;
	u32 base3;
	struct desc_struct desc;

	ctxt->ops->get_segment(ctxt, &dummy, &desc, &base3, seg);
	ctxt->ops->set_segment(ctxt, selector, &desc, base3, seg);
}

657 658 659 660 661 662
/*
 * x86 defines three classes of vector instructions: explicitly
 * aligned, explicitly unaligned, and the rest, which change behaviour
 * depending on whether they're AVX encoded or not.
 *
 * Also included is CMPXCHG16B which is not a vector instruction, yet it is
663 664
 * subject to the same check.  FXSAVE and FXRSTOR are checked here too as their
 * 512 bytes of data must be aligned to a 16 byte boundary.
665
 */
666
static unsigned insn_alignment(struct x86_emulate_ctxt *ctxt, unsigned size)
667
{
668
	u64 alignment = ctxt->d & AlignMask;
669 670

	if (likely(size < 16))
671
		return 1;
672

673 674 675
	switch (alignment) {
	case Unaligned:
	case Avx:
676
		return 1;
677
	case Aligned16:
678
		return 16;
679 680
	case Aligned:
	default:
681
		return size;
682
	}
683 684
}

685 686 687 688
static __always_inline int __linearize(struct x86_emulate_ctxt *ctxt,
				       struct segmented_address addr,
				       unsigned *max_size, unsigned size,
				       bool write, bool fetch,
689
				       enum x86emul_mode mode, ulong *linear)
690
{
691 692
	struct desc_struct desc;
	bool usable;
693
	ulong la;
694
	u32 lim;
695
	u16 sel;
696
	u8  va_bits;
697

698
	la = seg_base(ctxt, addr.seg) + addr.ea;
699
	*max_size = 0;
700
	switch (mode) {
701
	case X86EMUL_MODE_PROT64:
702
		*linear = la;
703 704
		va_bits = ctxt_virt_addr_bits(ctxt);
		if (get_canonical(la, va_bits) != la)
705
			goto bad;
706

707
		*max_size = min_t(u64, ~0u, (1ull << va_bits) - la);
708 709
		if (size > *max_size)
			goto bad;
710 711
		break;
	default:
712
		*linear = la = (u32)la;
713 714
		usable = ctxt->ops->get_segment(ctxt, &sel, &desc, NULL,
						addr.seg);
715 716
		if (!usable)
			goto bad;
717 718 719
		/* code segment in protected mode or read-only data segment */
		if ((((ctxt->mode != X86EMUL_MODE_REAL) && (desc.type & 8))
					|| !(desc.type & 2)) && write)
720 721
			goto bad;
		/* unreadable code segment */
722
		if (!fetch && (desc.type & 8) && !(desc.type & 2))
723 724
			goto bad;
		lim = desc_limit_scaled(&desc);
725
		if (!(desc.type & 8) && (desc.type & 4)) {
G
Guo Chao 已提交
726
			/* expand-down segment */
727
			if (addr.ea <= lim)
728 729 730
				goto bad;
			lim = desc.d ? 0xffffffff : 0xffff;
		}
731 732
		if (addr.ea > lim)
			goto bad;
733 734 735 736 737 738 739
		if (lim == 0xffffffff)
			*max_size = ~0u;
		else {
			*max_size = (u64)lim + 1 - addr.ea;
			if (size > *max_size)
				goto bad;
		}
740 741
		break;
	}
742
	if (la & (insn_alignment(ctxt, size) - 1))
743
		return emulate_gp(ctxt, 0);
744
	return X86EMUL_CONTINUE;
745 746
bad:
	if (addr.seg == VCPU_SREG_SS)
747
		return emulate_ss(ctxt, 0);
748
	else
749
		return emulate_gp(ctxt, 0);
750 751
}

752 753 754 755 756
static int linearize(struct x86_emulate_ctxt *ctxt,
		     struct segmented_address addr,
		     unsigned size, bool write,
		     ulong *linear)
{
757
	unsigned max_size;
758 759
	return __linearize(ctxt, addr, &max_size, size, write, false,
			   ctxt->mode, linear);
760 761
}

762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781
static inline int assign_eip(struct x86_emulate_ctxt *ctxt, ulong dst,
			     enum x86emul_mode mode)
{
	ulong linear;
	int rc;
	unsigned max_size;
	struct segmented_address addr = { .seg = VCPU_SREG_CS,
					   .ea = dst };

	if (ctxt->op_bytes != sizeof(unsigned long))
		addr.ea = dst & ((1UL << (ctxt->op_bytes << 3)) - 1);
	rc = __linearize(ctxt, addr, &max_size, 1, false, true, mode, &linear);
	if (rc == X86EMUL_CONTINUE)
		ctxt->_eip = addr.ea;
	return rc;
}

static inline int assign_eip_near(struct x86_emulate_ctxt *ctxt, ulong dst)
{
	return assign_eip(ctxt, dst, ctxt->mode);
782 783
}

784 785 786 787
static int assign_eip_far(struct x86_emulate_ctxt *ctxt, ulong dst,
			  const struct desc_struct *cs_desc)
{
	enum x86emul_mode mode = ctxt->mode;
788
	int rc;
789 790

#ifdef CONFIG_X86_64
791 792 793
	if (ctxt->mode >= X86EMUL_MODE_PROT16) {
		if (cs_desc->l) {
			u64 efer = 0;
794

795 796 797 798 799
			ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
			if (efer & EFER_LMA)
				mode = X86EMUL_MODE_PROT64;
		} else
			mode = X86EMUL_MODE_PROT32; /* temporary value */
800 801 802 803
	}
#endif
	if (mode == X86EMUL_MODE_PROT16 || mode == X86EMUL_MODE_PROT32)
		mode = cs_desc->d ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
804 805 806 807
	rc = assign_eip(ctxt, dst, mode);
	if (rc == X86EMUL_CONTINUE)
		ctxt->mode = mode;
	return rc;
808 809 810 811 812 813
}

static inline int jmp_rel(struct x86_emulate_ctxt *ctxt, int rel)
{
	return assign_eip_near(ctxt, ctxt->_eip + rel);
}
814

815 816 817 818 819
static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
			      struct segmented_address addr,
			      void *data,
			      unsigned size)
{
820 821 822
	int rc;
	ulong linear;

823
	rc = linearize(ctxt, addr, size, false, &linear);
824 825
	if (rc != X86EMUL_CONTINUE)
		return rc;
826
	return ctxt->ops->read_std(ctxt, linear, data, size, &ctxt->exception);
827 828
}

829 830 831 832 833 834 835 836 837 838 839 840 841 842
static int segmented_write_std(struct x86_emulate_ctxt *ctxt,
			       struct segmented_address addr,
			       void *data,
			       unsigned int size)
{
	int rc;
	ulong linear;

	rc = linearize(ctxt, addr, size, true, &linear);
	if (rc != X86EMUL_CONTINUE)
		return rc;
	return ctxt->ops->write_std(ctxt, linear, data, size, &ctxt->exception);
}

843
/*
844
 * Prefetch the remaining bytes of the instruction without crossing page
845 846
 * boundary if they are not in fetch_cache yet.
 */
847
static int __do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt, int op_size)
848 849
{
	int rc;
850
	unsigned size, max_size;
851
	unsigned long linear;
852
	int cur_size = ctxt->fetch.end - ctxt->fetch.data;
853
	struct segmented_address addr = { .seg = VCPU_SREG_CS,
854 855
					   .ea = ctxt->eip + cur_size };

856 857 858 859 860 861 862 863 864 865
	/*
	 * We do not know exactly how many bytes will be needed, and
	 * __linearize is expensive, so fetch as much as possible.  We
	 * just have to avoid going beyond the 15 byte limit, the end
	 * of the segment, or the end of the page.
	 *
	 * __linearize is called with size 0 so that it does not do any
	 * boundary check itself.  Instead, we use max_size to check
	 * against op_size.
	 */
866 867
	rc = __linearize(ctxt, addr, &max_size, 0, false, true, ctxt->mode,
			 &linear);
868 869 870
	if (unlikely(rc != X86EMUL_CONTINUE))
		return rc;

871
	size = min_t(unsigned, 15UL ^ cur_size, max_size);
872
	size = min_t(unsigned, size, PAGE_SIZE - offset_in_page(linear));
873 874 875 876 877 878 879 880

	/*
	 * One instruction can only straddle two pages,
	 * and one has been loaded at the beginning of
	 * x86_decode_insn.  So, if not enough bytes
	 * still, we must have hit the 15-byte boundary.
	 */
	if (unlikely(size < op_size))
881 882
		return emulate_gp(ctxt, 0);

883
	rc = ctxt->ops->fetch(ctxt, linear, ctxt->fetch.end,
884 885 886
			      size, &ctxt->exception);
	if (unlikely(rc != X86EMUL_CONTINUE))
		return rc;
887
	ctxt->fetch.end += size;
888
	return X86EMUL_CONTINUE;
889 890
}

891 892
static __always_inline int do_insn_fetch_bytes(struct x86_emulate_ctxt *ctxt,
					       unsigned size)
893
{
894 895 896 897
	unsigned done_size = ctxt->fetch.end - ctxt->fetch.ptr;

	if (unlikely(done_size < size))
		return __do_insn_fetch_bytes(ctxt, size - done_size);
898 899
	else
		return X86EMUL_CONTINUE;
900 901
}

902
/* Fetch next part of the instruction being emulated. */
903
#define insn_fetch(_type, _ctxt)					\
904 905 906
({	_type _x;							\
									\
	rc = do_insn_fetch_bytes(_ctxt, sizeof(_type));			\
907 908
	if (rc != X86EMUL_CONTINUE)					\
		goto done;						\
909
	ctxt->_eip += sizeof(_type);					\
910
	memcpy(&_x, ctxt->fetch.ptr, sizeof(_type));			\
911
	ctxt->fetch.ptr += sizeof(_type);				\
912
	_x;								\
913 914
})

915
#define insn_fetch_arr(_arr, _size, _ctxt)				\
916 917
({									\
	rc = do_insn_fetch_bytes(_ctxt, _size);				\
918 919
	if (rc != X86EMUL_CONTINUE)					\
		goto done;						\
920
	ctxt->_eip += (_size);						\
921 922
	memcpy(_arr, ctxt->fetch.ptr, _size);				\
	ctxt->fetch.ptr += (_size);					\
923 924
})

925 926 927 928 929
/*
 * Given the 'reg' portion of a ModRM byte, and a register block, return a
 * pointer into the block that addresses the relevant register.
 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
 */
930
static void *decode_register(struct x86_emulate_ctxt *ctxt, u8 modrm_reg,
931
			     int byteop)
A
Avi Kivity 已提交
932 933
{
	void *p;
934
	int highbyte_regs = (ctxt->rex_prefix == 0) && byteop;
A
Avi Kivity 已提交
935 936

	if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
937 938 939
		p = (unsigned char *)reg_rmw(ctxt, modrm_reg & 3) + 1;
	else
		p = reg_rmw(ctxt, modrm_reg);
A
Avi Kivity 已提交
940 941 942 943
	return p;
}

static int read_descriptor(struct x86_emulate_ctxt *ctxt,
944
			   struct segmented_address addr,
A
Avi Kivity 已提交
945 946 947 948 949 950 951
			   u16 *size, unsigned long *address, int op_bytes)
{
	int rc;

	if (op_bytes == 2)
		op_bytes = 3;
	*address = 0;
952
	rc = segmented_read_std(ctxt, addr, size, 2);
953
	if (rc != X86EMUL_CONTINUE)
A
Avi Kivity 已提交
954
		return rc;
955
	addr.ea += 2;
956
	rc = segmented_read_std(ctxt, addr, address, op_bytes);
A
Avi Kivity 已提交
957 958 959
	return rc;
}

960 961 962 963 964 965 966 967 968 969
FASTOP2(add);
FASTOP2(or);
FASTOP2(adc);
FASTOP2(sbb);
FASTOP2(and);
FASTOP2(sub);
FASTOP2(xor);
FASTOP2(cmp);
FASTOP2(test);

970 971
FASTOP1SRC2(mul, mul_ex);
FASTOP1SRC2(imul, imul_ex);
972 973
FASTOP1SRC2EX(div, div_ex);
FASTOP1SRC2EX(idiv, idiv_ex);
974

975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999
FASTOP3WCL(shld);
FASTOP3WCL(shrd);

FASTOP2W(imul);

FASTOP1(not);
FASTOP1(neg);
FASTOP1(inc);
FASTOP1(dec);

FASTOP2CL(rol);
FASTOP2CL(ror);
FASTOP2CL(rcl);
FASTOP2CL(rcr);
FASTOP2CL(shl);
FASTOP2CL(shr);
FASTOP2CL(sar);

FASTOP2W(bsf);
FASTOP2W(bsr);
FASTOP2W(bt);
FASTOP2W(bts);
FASTOP2W(btr);
FASTOP2W(btc);

1000 1001
FASTOP2(xadd);

1002 1003
FASTOP2R(cmp, cmp_r);

1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019
static int em_bsf_c(struct x86_emulate_ctxt *ctxt)
{
	/* If src is zero, do not writeback, but update flags */
	if (ctxt->src.val == 0)
		ctxt->dst.type = OP_NONE;
	return fastop(ctxt, em_bsf);
}

static int em_bsr_c(struct x86_emulate_ctxt *ctxt)
{
	/* If src is zero, do not writeback, but update flags */
	if (ctxt->src.val == 0)
		ctxt->dst.type = OP_NONE;
	return fastop(ctxt, em_bsr);
}

1020
static __always_inline u8 test_cc(unsigned int condition, unsigned long flags)
1021
{
1022 1023
	u8 rc;
	void (*fop)(void) = (void *)em_setcc + 4 * (condition & 0xf);
1024

1025
	flags = (flags & EFLAGS_MASK) | X86_EFLAGS_IF;
1026 1027
	asm("push %[flags]; popf; " CALL_NOSPEC
	    : "=a"(rc) : [thunk_target]"r"(fop), [flags]"r"(flags));
1028
	return rc;
1029 1030
}

1031 1032 1033 1034 1035 1036 1037 1038 1039 1040 1041 1042 1043 1044 1045 1046 1047 1048
static void fetch_register_operand(struct operand *op)
{
	switch (op->bytes) {
	case 1:
		op->val = *(u8 *)op->addr.reg;
		break;
	case 2:
		op->val = *(u16 *)op->addr.reg;
		break;
	case 4:
		op->val = *(u32 *)op->addr.reg;
		break;
	case 8:
		op->val = *(u64 *)op->addr.reg;
		break;
	}
}

A
Avi Kivity 已提交
1049 1050 1051
static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
{
	switch (reg) {
1052 1053 1054 1055 1056 1057 1058 1059
	case 0: asm("movdqa %%xmm0, %0" : "=m"(*data)); break;
	case 1: asm("movdqa %%xmm1, %0" : "=m"(*data)); break;
	case 2: asm("movdqa %%xmm2, %0" : "=m"(*data)); break;
	case 3: asm("movdqa %%xmm3, %0" : "=m"(*data)); break;
	case 4: asm("movdqa %%xmm4, %0" : "=m"(*data)); break;
	case 5: asm("movdqa %%xmm5, %0" : "=m"(*data)); break;
	case 6: asm("movdqa %%xmm6, %0" : "=m"(*data)); break;
	case 7: asm("movdqa %%xmm7, %0" : "=m"(*data)); break;
A
Avi Kivity 已提交
1060
#ifdef CONFIG_X86_64
1061 1062 1063 1064 1065 1066 1067 1068
	case 8: asm("movdqa %%xmm8, %0" : "=m"(*data)); break;
	case 9: asm("movdqa %%xmm9, %0" : "=m"(*data)); break;
	case 10: asm("movdqa %%xmm10, %0" : "=m"(*data)); break;
	case 11: asm("movdqa %%xmm11, %0" : "=m"(*data)); break;
	case 12: asm("movdqa %%xmm12, %0" : "=m"(*data)); break;
	case 13: asm("movdqa %%xmm13, %0" : "=m"(*data)); break;
	case 14: asm("movdqa %%xmm14, %0" : "=m"(*data)); break;
	case 15: asm("movdqa %%xmm15, %0" : "=m"(*data)); break;
A
Avi Kivity 已提交
1069 1070 1071 1072 1073 1074 1075 1076 1077
#endif
	default: BUG();
	}
}

static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
			  int reg)
{
	switch (reg) {
1078 1079 1080 1081 1082 1083 1084 1085
	case 0: asm("movdqa %0, %%xmm0" : : "m"(*data)); break;
	case 1: asm("movdqa %0, %%xmm1" : : "m"(*data)); break;
	case 2: asm("movdqa %0, %%xmm2" : : "m"(*data)); break;
	case 3: asm("movdqa %0, %%xmm3" : : "m"(*data)); break;
	case 4: asm("movdqa %0, %%xmm4" : : "m"(*data)); break;
	case 5: asm("movdqa %0, %%xmm5" : : "m"(*data)); break;
	case 6: asm("movdqa %0, %%xmm6" : : "m"(*data)); break;
	case 7: asm("movdqa %0, %%xmm7" : : "m"(*data)); break;
A
Avi Kivity 已提交
1086
#ifdef CONFIG_X86_64
1087 1088 1089 1090 1091 1092 1093 1094
	case 8: asm("movdqa %0, %%xmm8" : : "m"(*data)); break;
	case 9: asm("movdqa %0, %%xmm9" : : "m"(*data)); break;
	case 10: asm("movdqa %0, %%xmm10" : : "m"(*data)); break;
	case 11: asm("movdqa %0, %%xmm11" : : "m"(*data)); break;
	case 12: asm("movdqa %0, %%xmm12" : : "m"(*data)); break;
	case 13: asm("movdqa %0, %%xmm13" : : "m"(*data)); break;
	case 14: asm("movdqa %0, %%xmm14" : : "m"(*data)); break;
	case 15: asm("movdqa %0, %%xmm15" : : "m"(*data)); break;
A
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1095 1096 1097 1098 1099
#endif
	default: BUG();
	}
}

A
Avi Kivity 已提交
1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129
static void read_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
{
	switch (reg) {
	case 0: asm("movq %%mm0, %0" : "=m"(*data)); break;
	case 1: asm("movq %%mm1, %0" : "=m"(*data)); break;
	case 2: asm("movq %%mm2, %0" : "=m"(*data)); break;
	case 3: asm("movq %%mm3, %0" : "=m"(*data)); break;
	case 4: asm("movq %%mm4, %0" : "=m"(*data)); break;
	case 5: asm("movq %%mm5, %0" : "=m"(*data)); break;
	case 6: asm("movq %%mm6, %0" : "=m"(*data)); break;
	case 7: asm("movq %%mm7, %0" : "=m"(*data)); break;
	default: BUG();
	}
}

static void write_mmx_reg(struct x86_emulate_ctxt *ctxt, u64 *data, int reg)
{
	switch (reg) {
	case 0: asm("movq %0, %%mm0" : : "m"(*data)); break;
	case 1: asm("movq %0, %%mm1" : : "m"(*data)); break;
	case 2: asm("movq %0, %%mm2" : : "m"(*data)); break;
	case 3: asm("movq %0, %%mm3" : : "m"(*data)); break;
	case 4: asm("movq %0, %%mm4" : : "m"(*data)); break;
	case 5: asm("movq %0, %%mm5" : : "m"(*data)); break;
	case 6: asm("movq %0, %%mm6" : : "m"(*data)); break;
	case 7: asm("movq %0, %%mm7" : : "m"(*data)); break;
	default: BUG();
	}
}

1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166
static int em_fninit(struct x86_emulate_ctxt *ctxt)
{
	if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
		return emulate_nm(ctxt);

	asm volatile("fninit");
	return X86EMUL_CONTINUE;
}

static int em_fnstcw(struct x86_emulate_ctxt *ctxt)
{
	u16 fcw;

	if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
		return emulate_nm(ctxt);

	asm volatile("fnstcw %0": "+m"(fcw));

	ctxt->dst.val = fcw;

	return X86EMUL_CONTINUE;
}

static int em_fnstsw(struct x86_emulate_ctxt *ctxt)
{
	u16 fsw;

	if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
		return emulate_nm(ctxt);

	asm volatile("fnstsw %0": "+m"(fsw));

	ctxt->dst.val = fsw;

	return X86EMUL_CONTINUE;
}

A
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1167
static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
1168
				    struct operand *op)
1169
{
1170
	unsigned reg = ctxt->modrm_reg;
1171

1172 1173
	if (!(ctxt->d & ModRM))
		reg = (ctxt->b & 7) | ((ctxt->rex_prefix & 1) << 3);
A
Avi Kivity 已提交
1174

1175
	if (ctxt->d & Sse) {
A
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1176 1177 1178 1179 1180 1181
		op->type = OP_XMM;
		op->bytes = 16;
		op->addr.xmm = reg;
		read_sse_reg(ctxt, &op->vec_val, reg);
		return;
	}
A
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1182 1183 1184 1185 1186 1187 1188
	if (ctxt->d & Mmx) {
		reg &= 7;
		op->type = OP_MM;
		op->bytes = 8;
		op->addr.mm = reg;
		return;
	}
A
Avi Kivity 已提交
1189

1190
	op->type = OP_REG;
1191 1192 1193
	op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
	op->addr.reg = decode_register(ctxt, reg, ctxt->d & ByteOp);

1194
	fetch_register_operand(op);
1195 1196 1197
	op->orig_val = op->val;
}

1198 1199 1200 1201 1202 1203
static void adjust_modrm_seg(struct x86_emulate_ctxt *ctxt, int base_reg)
{
	if (base_reg == VCPU_REGS_RSP || base_reg == VCPU_REGS_RBP)
		ctxt->modrm_seg = VCPU_SREG_SS;
}

1204
static int decode_modrm(struct x86_emulate_ctxt *ctxt,
1205
			struct operand *op)
1206 1207
{
	u8 sib;
B
Bandan Das 已提交
1208
	int index_reg, base_reg, scale;
1209
	int rc = X86EMUL_CONTINUE;
1210
	ulong modrm_ea = 0;
1211

B
Bandan Das 已提交
1212 1213 1214
	ctxt->modrm_reg = ((ctxt->rex_prefix << 1) & 8); /* REX.R */
	index_reg = (ctxt->rex_prefix << 2) & 8; /* REX.X */
	base_reg = (ctxt->rex_prefix << 3) & 8; /* REX.B */
1215

B
Bandan Das 已提交
1216
	ctxt->modrm_mod = (ctxt->modrm & 0xc0) >> 6;
1217
	ctxt->modrm_reg |= (ctxt->modrm & 0x38) >> 3;
B
Bandan Das 已提交
1218
	ctxt->modrm_rm = base_reg | (ctxt->modrm & 0x07);
1219
	ctxt->modrm_seg = VCPU_SREG_DS;
1220

1221
	if (ctxt->modrm_mod == 3 || (ctxt->d & NoMod)) {
1222
		op->type = OP_REG;
1223
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
1224
		op->addr.reg = decode_register(ctxt, ctxt->modrm_rm,
1225
				ctxt->d & ByteOp);
1226
		if (ctxt->d & Sse) {
A
Avi Kivity 已提交
1227 1228
			op->type = OP_XMM;
			op->bytes = 16;
1229 1230
			op->addr.xmm = ctxt->modrm_rm;
			read_sse_reg(ctxt, &op->vec_val, ctxt->modrm_rm);
A
Avi Kivity 已提交
1231 1232
			return rc;
		}
A
Avi Kivity 已提交
1233 1234 1235
		if (ctxt->d & Mmx) {
			op->type = OP_MM;
			op->bytes = 8;
1236
			op->addr.mm = ctxt->modrm_rm & 7;
A
Avi Kivity 已提交
1237 1238
			return rc;
		}
1239
		fetch_register_operand(op);
1240 1241 1242
		return rc;
	}

1243 1244
	op->type = OP_MEM;

1245
	if (ctxt->ad_bytes == 2) {
1246 1247 1248 1249
		unsigned bx = reg_read(ctxt, VCPU_REGS_RBX);
		unsigned bp = reg_read(ctxt, VCPU_REGS_RBP);
		unsigned si = reg_read(ctxt, VCPU_REGS_RSI);
		unsigned di = reg_read(ctxt, VCPU_REGS_RDI);
1250 1251

		/* 16-bit ModR/M decode. */
1252
		switch (ctxt->modrm_mod) {
1253
		case 0:
1254
			if (ctxt->modrm_rm == 6)
1255
				modrm_ea += insn_fetch(u16, ctxt);
1256 1257
			break;
		case 1:
1258
			modrm_ea += insn_fetch(s8, ctxt);
1259 1260
			break;
		case 2:
1261
			modrm_ea += insn_fetch(u16, ctxt);
1262 1263
			break;
		}
1264
		switch (ctxt->modrm_rm) {
1265
		case 0:
1266
			modrm_ea += bx + si;
1267 1268
			break;
		case 1:
1269
			modrm_ea += bx + di;
1270 1271
			break;
		case 2:
1272
			modrm_ea += bp + si;
1273 1274
			break;
		case 3:
1275
			modrm_ea += bp + di;
1276 1277
			break;
		case 4:
1278
			modrm_ea += si;
1279 1280
			break;
		case 5:
1281
			modrm_ea += di;
1282 1283
			break;
		case 6:
1284
			if (ctxt->modrm_mod != 0)
1285
				modrm_ea += bp;
1286 1287
			break;
		case 7:
1288
			modrm_ea += bx;
1289 1290
			break;
		}
1291 1292 1293
		if (ctxt->modrm_rm == 2 || ctxt->modrm_rm == 3 ||
		    (ctxt->modrm_rm == 6 && ctxt->modrm_mod != 0))
			ctxt->modrm_seg = VCPU_SREG_SS;
1294
		modrm_ea = (u16)modrm_ea;
1295 1296
	} else {
		/* 32/64-bit ModR/M decode. */
1297
		if ((ctxt->modrm_rm & 7) == 4) {
1298
			sib = insn_fetch(u8, ctxt);
1299 1300 1301 1302
			index_reg |= (sib >> 3) & 7;
			base_reg |= sib & 7;
			scale = sib >> 6;

1303
			if ((base_reg & 7) == 5 && ctxt->modrm_mod == 0)
1304
				modrm_ea += insn_fetch(s32, ctxt);
1305
			else {
1306
				modrm_ea += reg_read(ctxt, base_reg);
1307
				adjust_modrm_seg(ctxt, base_reg);
1308 1309 1310 1311
				/* Increment ESP on POP [ESP] */
				if ((ctxt->d & IncSP) &&
				    base_reg == VCPU_REGS_RSP)
					modrm_ea += ctxt->op_bytes;
1312
			}
1313
			if (index_reg != 4)
1314
				modrm_ea += reg_read(ctxt, index_reg) << scale;
1315
		} else if ((ctxt->modrm_rm & 7) == 5 && ctxt->modrm_mod == 0) {
1316
			modrm_ea += insn_fetch(s32, ctxt);
1317
			if (ctxt->mode == X86EMUL_MODE_PROT64)
1318
				ctxt->rip_relative = 1;
1319 1320
		} else {
			base_reg = ctxt->modrm_rm;
1321
			modrm_ea += reg_read(ctxt, base_reg);
1322 1323
			adjust_modrm_seg(ctxt, base_reg);
		}
1324
		switch (ctxt->modrm_mod) {
1325
		case 1:
1326
			modrm_ea += insn_fetch(s8, ctxt);
1327 1328
			break;
		case 2:
1329
			modrm_ea += insn_fetch(s32, ctxt);
1330 1331 1332
			break;
		}
	}
1333
	op->addr.mem.ea = modrm_ea;
1334 1335 1336
	if (ctxt->ad_bytes != 8)
		ctxt->memop.addr.mem.ea = (u32)ctxt->memop.addr.mem.ea;

1337 1338 1339 1340 1341
done:
	return rc;
}

static int decode_abs(struct x86_emulate_ctxt *ctxt,
1342
		      struct operand *op)
1343
{
1344
	int rc = X86EMUL_CONTINUE;
1345

1346
	op->type = OP_MEM;
1347
	switch (ctxt->ad_bytes) {
1348
	case 2:
1349
		op->addr.mem.ea = insn_fetch(u16, ctxt);
1350 1351
		break;
	case 4:
1352
		op->addr.mem.ea = insn_fetch(u32, ctxt);
1353 1354
		break;
	case 8:
1355
		op->addr.mem.ea = insn_fetch(u64, ctxt);
1356 1357 1358 1359 1360 1361
		break;
	}
done:
	return rc;
}

1362
static void fetch_bit_operand(struct x86_emulate_ctxt *ctxt)
1363
{
1364
	long sv = 0, mask;
1365

1366
	if (ctxt->dst.type == OP_MEM && ctxt->src.type == OP_REG) {
1367
		mask = ~((long)ctxt->dst.bytes * 8 - 1);
1368

1369 1370 1371 1372
		if (ctxt->src.bytes == 2)
			sv = (s16)ctxt->src.val & (s16)mask;
		else if (ctxt->src.bytes == 4)
			sv = (s32)ctxt->src.val & (s32)mask;
1373 1374
		else
			sv = (s64)ctxt->src.val & (s64)mask;
1375

1376 1377
		ctxt->dst.addr.mem.ea = address_mask(ctxt,
					   ctxt->dst.addr.mem.ea + (sv >> 3));
1378
	}
1379 1380

	/* only subword offset */
1381
	ctxt->src.val &= (ctxt->dst.bytes << 3) - 1;
1382 1383
}

1384 1385
static int read_emulated(struct x86_emulate_ctxt *ctxt,
			 unsigned long addr, void *dest, unsigned size)
A
Avi Kivity 已提交
1386
{
1387
	int rc;
1388
	struct read_cache *mc = &ctxt->mem_read;
A
Avi Kivity 已提交
1389

1390 1391
	if (mc->pos < mc->end)
		goto read_cached;
A
Avi Kivity 已提交
1392

1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404
	WARN_ON((mc->end + size) >= sizeof(mc->data));

	rc = ctxt->ops->read_emulated(ctxt, addr, mc->data + mc->end, size,
				      &ctxt->exception);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	mc->end += size;

read_cached:
	memcpy(dest, mc->data + mc->pos, size);
	mc->pos += size;
1405 1406
	return X86EMUL_CONTINUE;
}
A
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1407

1408 1409 1410 1411 1412
static int segmented_read(struct x86_emulate_ctxt *ctxt,
			  struct segmented_address addr,
			  void *data,
			  unsigned size)
{
1413 1414 1415
	int rc;
	ulong linear;

1416
	rc = linearize(ctxt, addr, size, false, &linear);
1417 1418
	if (rc != X86EMUL_CONTINUE)
		return rc;
1419
	return read_emulated(ctxt, linear, data, size);
1420 1421 1422 1423 1424 1425 1426
}

static int segmented_write(struct x86_emulate_ctxt *ctxt,
			   struct segmented_address addr,
			   const void *data,
			   unsigned size)
{
1427 1428 1429
	int rc;
	ulong linear;

1430
	rc = linearize(ctxt, addr, size, true, &linear);
1431 1432
	if (rc != X86EMUL_CONTINUE)
		return rc;
1433 1434
	return ctxt->ops->write_emulated(ctxt, linear, data, size,
					 &ctxt->exception);
1435 1436 1437 1438 1439 1440 1441
}

static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
			     struct segmented_address addr,
			     const void *orig_data, const void *data,
			     unsigned size)
{
1442 1443 1444
	int rc;
	ulong linear;

1445
	rc = linearize(ctxt, addr, size, true, &linear);
1446 1447
	if (rc != X86EMUL_CONTINUE)
		return rc;
1448 1449
	return ctxt->ops->cmpxchg_emulated(ctxt, linear, orig_data, data,
					   size, &ctxt->exception);
1450 1451
}

1452 1453 1454 1455
static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
			   unsigned int size, unsigned short port,
			   void *dest)
{
1456
	struct read_cache *rc = &ctxt->io_read;
1457

1458 1459
	if (rc->pos == rc->end) { /* refill pio read ahead */
		unsigned int in_page, n;
1460
		unsigned int count = ctxt->rep_prefix ?
1461
			address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) : 1;
1462
		in_page = (ctxt->eflags & X86_EFLAGS_DF) ?
1463 1464
			offset_in_page(reg_read(ctxt, VCPU_REGS_RDI)) :
			PAGE_SIZE - offset_in_page(reg_read(ctxt, VCPU_REGS_RDI));
1465
		n = min3(in_page, (unsigned int)sizeof(rc->data) / size, count);
1466 1467 1468
		if (n == 0)
			n = 1;
		rc->pos = rc->end = 0;
1469
		if (!ctxt->ops->pio_in_emulated(ctxt, size, port, rc->data, n))
1470 1471
			return 0;
		rc->end = n * size;
A
Avi Kivity 已提交
1472 1473
	}

1474
	if (ctxt->rep_prefix && (ctxt->d & String) &&
1475
	    !(ctxt->eflags & X86_EFLAGS_DF)) {
1476 1477 1478 1479 1480 1481 1482 1483
		ctxt->dst.data = rc->data + rc->pos;
		ctxt->dst.type = OP_MEM_STR;
		ctxt->dst.count = (rc->end - rc->pos) / size;
		rc->pos = rc->end;
	} else {
		memcpy(dest, rc->data + rc->pos, size);
		rc->pos += size;
	}
1484 1485
	return 1;
}
A
Avi Kivity 已提交
1486

1487 1488 1489 1490 1491 1492 1493 1494 1495 1496 1497 1498 1499 1500 1501 1502
static int read_interrupt_descriptor(struct x86_emulate_ctxt *ctxt,
				     u16 index, struct desc_struct *desc)
{
	struct desc_ptr dt;
	ulong addr;

	ctxt->ops->get_idt(ctxt, &dt);

	if (dt.size < index * 8 + 7)
		return emulate_gp(ctxt, index << 3 | 0x2);

	addr = dt.address + index * 8;
	return ctxt->ops->read_std(ctxt, addr, desc, sizeof *desc,
				   &ctxt->exception);
}

1503 1504 1505
static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
				     u16 selector, struct desc_ptr *dt)
{
1506
	const struct x86_emulate_ops *ops = ctxt->ops;
1507
	u32 base3 = 0;
1508

1509 1510
	if (selector & 1 << 2) {
		struct desc_struct desc;
1511 1512
		u16 sel;

1513
		memset (dt, 0, sizeof *dt);
1514 1515
		if (!ops->get_segment(ctxt, &sel, &desc, &base3,
				      VCPU_SREG_LDTR))
1516
			return;
1517

1518
		dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1519
		dt->address = get_desc_base(&desc) | ((u64)base3 << 32);
1520
	} else
1521
		ops->get_gdt(ctxt, dt);
1522
}
1523

1524 1525
static int get_descriptor_ptr(struct x86_emulate_ctxt *ctxt,
			      u16 selector, ulong *desc_addr_p)
1526 1527 1528 1529
{
	struct desc_ptr dt;
	u16 index = selector >> 3;
	ulong addr;
1530

1531
	get_descriptor_table_ptr(ctxt, selector, &dt);
1532

1533 1534
	if (dt.size < index * 8 + 7)
		return emulate_gp(ctxt, selector & 0xfffc);
1535

1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550 1551 1552 1553 1554 1555 1556 1557 1558 1559 1560 1561 1562 1563
	addr = dt.address + index * 8;

#ifdef CONFIG_X86_64
	if (addr >> 32 != 0) {
		u64 efer = 0;

		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
		if (!(efer & EFER_LMA))
			addr &= (u32)-1;
	}
#endif

	*desc_addr_p = addr;
	return X86EMUL_CONTINUE;
}

/* allowed just for 8 bytes segments */
static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				   u16 selector, struct desc_struct *desc,
				   ulong *desc_addr_p)
{
	int rc;

	rc = get_descriptor_ptr(ctxt, selector, desc_addr_p);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	return ctxt->ops->read_std(ctxt, *desc_addr_p, desc, sizeof(*desc),
1564
				   &ctxt->exception);
1565
}
1566

1567 1568 1569 1570
/* allowed just for 8 bytes segments */
static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				    u16 selector, struct desc_struct *desc)
{
1571
	int rc;
1572
	ulong addr;
A
Avi Kivity 已提交
1573

1574 1575 1576
	rc = get_descriptor_ptr(ctxt, selector, &addr);
	if (rc != X86EMUL_CONTINUE)
		return rc;
A
Avi Kivity 已提交
1577

1578 1579
	return ctxt->ops->write_std(ctxt, addr, desc, sizeof *desc,
				    &ctxt->exception);
1580
}
1581

1582
static int __load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1583
				     u16 selector, int seg, u8 cpl,
1584
				     enum x86_transfer_type transfer,
1585
				     struct desc_struct *desc)
1586
{
1587
	struct desc_struct seg_desc, old_desc;
1588
	u8 dpl, rpl;
1589 1590 1591
	unsigned err_vec = GP_VECTOR;
	u32 err_code = 0;
	bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1592
	ulong desc_addr;
1593
	int ret;
1594
	u16 dummy;
1595
	u32 base3 = 0;
1596

1597
	memset(&seg_desc, 0, sizeof seg_desc);
1598

1599 1600 1601
	if (ctxt->mode == X86EMUL_MODE_REAL) {
		/* set real mode segment descriptor (keep limit etc. for
		 * unreal mode) */
1602
		ctxt->ops->get_segment(ctxt, &dummy, &seg_desc, NULL, seg);
1603 1604
		set_desc_base(&seg_desc, selector << 4);
		goto load;
1605 1606 1607 1608 1609 1610 1611 1612 1613
	} else if (seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86) {
		/* VM86 needs a clean new segment descriptor */
		set_desc_base(&seg_desc, selector << 4);
		set_desc_limit(&seg_desc, 0xffff);
		seg_desc.type = 3;
		seg_desc.p = 1;
		seg_desc.s = 1;
		seg_desc.dpl = 3;
		goto load;
1614 1615
	}

1616 1617
	rpl = selector & 3;

1618 1619 1620 1621
	/* TR should be in GDT only */
	if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
		goto exception;

1622 1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633 1634 1635 1636 1637 1638 1639 1640 1641 1642 1643
	/* NULL selector is not valid for TR, CS and (except for long mode) SS */
	if (null_selector) {
		if (seg == VCPU_SREG_CS || seg == VCPU_SREG_TR)
			goto exception;

		if (seg == VCPU_SREG_SS) {
			if (ctxt->mode != X86EMUL_MODE_PROT64 || rpl != cpl)
				goto exception;

			/*
			 * ctxt->ops->set_segment expects the CPL to be in
			 * SS.DPL, so fake an expand-up 32-bit data segment.
			 */
			seg_desc.type = 3;
			seg_desc.p = 1;
			seg_desc.s = 1;
			seg_desc.dpl = cpl;
			seg_desc.d = 1;
			seg_desc.g = 1;
		}

		/* Skip all following checks */
1644
		goto load;
1645
	}
1646

1647
	ret = read_segment_descriptor(ctxt, selector, &seg_desc, &desc_addr);
1648 1649 1650 1651
	if (ret != X86EMUL_CONTINUE)
		return ret;

	err_code = selector & 0xfffc;
1652 1653
	err_vec = (transfer == X86_TRANSFER_TASK_SWITCH) ? TS_VECTOR :
							   GP_VECTOR;
1654

G
Guo Chao 已提交
1655
	/* can't load system descriptor into segment selector */
1656 1657 1658
	if (seg <= VCPU_SREG_GS && !seg_desc.s) {
		if (transfer == X86_TRANSFER_CALL_JMP)
			return X86EMUL_UNHANDLEABLE;
1659
		goto exception;
1660
	}
1661 1662 1663 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674 1675 1676

	if (!seg_desc.p) {
		err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
		goto exception;
	}

	dpl = seg_desc.dpl;

	switch (seg) {
	case VCPU_SREG_SS:
		/*
		 * segment is not a writable data segment or segment
		 * selector's RPL != CPL or segment selector's RPL != CPL
		 */
		if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
			goto exception;
A
Avi Kivity 已提交
1677
		break;
1678 1679 1680 1681 1682 1683 1684 1685 1686 1687 1688 1689 1690
	case VCPU_SREG_CS:
		if (!(seg_desc.type & 8))
			goto exception;

		if (seg_desc.type & 4) {
			/* conforming */
			if (dpl > cpl)
				goto exception;
		} else {
			/* nonconforming */
			if (rpl > cpl || dpl != cpl)
				goto exception;
		}
1691 1692 1693 1694 1695 1696 1697 1698 1699
		/* in long-mode d/b must be clear if l is set */
		if (seg_desc.d && seg_desc.l) {
			u64 efer = 0;

			ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
			if (efer & EFER_LMA)
				goto exception;
		}

1700 1701
		/* CS(RPL) <- CPL */
		selector = (selector & 0xfffc) | cpl;
A
Avi Kivity 已提交
1702
		break;
1703 1704 1705
	case VCPU_SREG_TR:
		if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
			goto exception;
1706 1707 1708 1709 1710 1711
		old_desc = seg_desc;
		seg_desc.type |= 2; /* busy */
		ret = ctxt->ops->cmpxchg_emulated(ctxt, desc_addr, &old_desc, &seg_desc,
						  sizeof(seg_desc), &ctxt->exception);
		if (ret != X86EMUL_CONTINUE)
			return ret;
1712 1713 1714 1715 1716 1717
		break;
	case VCPU_SREG_LDTR:
		if (seg_desc.s || seg_desc.type != 2)
			goto exception;
		break;
	default: /*  DS, ES, FS, or GS */
1718
		/*
1719 1720 1721
		 * segment is not a data or readable code segment or
		 * ((segment is a data or nonconforming code segment)
		 * and (both RPL and CPL > DPL))
1722
		 */
1723 1724 1725 1726
		if ((seg_desc.type & 0xa) == 0x8 ||
		    (((seg_desc.type & 0xc) != 0xc) &&
		     (rpl > dpl && cpl > dpl)))
			goto exception;
A
Avi Kivity 已提交
1727
		break;
1728 1729 1730 1731
	}

	if (seg_desc.s) {
		/* mark segment as accessed */
1732 1733 1734 1735 1736 1737 1738
		if (!(seg_desc.type & 1)) {
			seg_desc.type |= 1;
			ret = write_segment_descriptor(ctxt, selector,
						       &seg_desc);
			if (ret != X86EMUL_CONTINUE)
				return ret;
		}
1739 1740 1741 1742 1743
	} else if (ctxt->mode == X86EMUL_MODE_PROT64) {
		ret = ctxt->ops->read_std(ctxt, desc_addr+8, &base3,
				sizeof(base3), &ctxt->exception);
		if (ret != X86EMUL_CONTINUE)
			return ret;
1744 1745
		if (emul_is_noncanonical_address(get_desc_base(&seg_desc) |
				((u64)base3 << 32), ctxt))
1746
			return emulate_gp(ctxt, 0);
1747 1748
	}
load:
1749
	ctxt->ops->set_segment(ctxt, selector, &seg_desc, base3, seg);
1750 1751
	if (desc)
		*desc = seg_desc;
1752 1753
	return X86EMUL_CONTINUE;
exception:
1754
	return emulate_exception(ctxt, err_vec, err_code, true);
1755 1756
}

1757 1758 1759 1760
static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
				   u16 selector, int seg)
{
	u8 cpl = ctxt->ops->cpl(ctxt);
1761 1762 1763 1764 1765 1766 1767 1768 1769 1770 1771 1772 1773 1774 1775

	/*
	 * None of MOV, POP and LSS can load a NULL selector in CPL=3, but
	 * they can load it at CPL<3 (Intel's manual says only LSS can,
	 * but it's wrong).
	 *
	 * However, the Intel manual says that putting IST=1/DPL=3 in
	 * an interrupt gate will result in SS=3 (the AMD manual instead
	 * says it doesn't), so allow SS=3 in __load_segment_descriptor
	 * and only forbid it here.
	 */
	if (seg == VCPU_SREG_SS && selector == 3 &&
	    ctxt->mode == X86EMUL_MODE_PROT64)
		return emulate_exception(ctxt, GP_VECTOR, 0, true);

1776 1777
	return __load_segment_descriptor(ctxt, selector, seg, cpl,
					 X86_TRANSFER_NONE, NULL);
1778 1779
}

1780 1781
static void write_register_operand(struct operand *op)
{
1782
	return assign_register(op->addr.reg, op->val, op->bytes);
1783 1784
}

1785
static int writeback(struct x86_emulate_ctxt *ctxt, struct operand *op)
1786
{
1787
	switch (op->type) {
1788
	case OP_REG:
1789
		write_register_operand(op);
A
Avi Kivity 已提交
1790
		break;
1791
	case OP_MEM:
1792
		if (ctxt->lock_prefix)
P
Paolo Bonzini 已提交
1793 1794 1795 1796 1797 1798 1799
			return segmented_cmpxchg(ctxt,
						 op->addr.mem,
						 &op->orig_val,
						 &op->val,
						 op->bytes);
		else
			return segmented_write(ctxt,
1800 1801 1802
					       op->addr.mem,
					       &op->val,
					       op->bytes);
1803
		break;
1804
	case OP_MEM_STR:
P
Paolo Bonzini 已提交
1805 1806 1807 1808
		return segmented_write(ctxt,
				       op->addr.mem,
				       op->data,
				       op->bytes * op->count);
1809
		break;
A
Avi Kivity 已提交
1810
	case OP_XMM:
1811
		write_sse_reg(ctxt, &op->vec_val, op->addr.xmm);
A
Avi Kivity 已提交
1812
		break;
A
Avi Kivity 已提交
1813
	case OP_MM:
1814
		write_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
A
Avi Kivity 已提交
1815
		break;
1816 1817
	case OP_NONE:
		/* no writeback */
1818
		break;
1819
	default:
1820
		break;
A
Avi Kivity 已提交
1821
	}
1822 1823
	return X86EMUL_CONTINUE;
}
A
Avi Kivity 已提交
1824

1825
static int push(struct x86_emulate_ctxt *ctxt, void *data, int bytes)
1826
{
1827
	struct segmented_address addr;
1828

1829
	rsp_increment(ctxt, -bytes);
1830
	addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1831 1832
	addr.seg = VCPU_SREG_SS;

1833 1834 1835 1836 1837
	return segmented_write(ctxt, addr, data, bytes);
}

static int em_push(struct x86_emulate_ctxt *ctxt)
{
1838
	/* Disable writeback. */
1839
	ctxt->dst.type = OP_NONE;
1840
	return push(ctxt, &ctxt->src.val, ctxt->op_bytes);
1841
}
1842

1843 1844 1845 1846
static int emulate_pop(struct x86_emulate_ctxt *ctxt,
		       void *dest, int len)
{
	int rc;
1847
	struct segmented_address addr;
1848

1849
	addr.ea = reg_read(ctxt, VCPU_REGS_RSP) & stack_mask(ctxt);
1850
	addr.seg = VCPU_SREG_SS;
1851
	rc = segmented_read(ctxt, addr, dest, len);
1852 1853 1854
	if (rc != X86EMUL_CONTINUE)
		return rc;

1855
	rsp_increment(ctxt, len);
1856
	return rc;
1857 1858
}

1859 1860
static int em_pop(struct x86_emulate_ctxt *ctxt)
{
1861
	return emulate_pop(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1862 1863
}

1864
static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1865
			void *dest, int len)
1866 1867
{
	int rc;
1868
	unsigned long val, change_mask;
1869
	int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
1870
	int cpl = ctxt->ops->cpl(ctxt);
1871

1872
	rc = emulate_pop(ctxt, &val, len);
1873 1874
	if (rc != X86EMUL_CONTINUE)
		return rc;
1875

1876 1877 1878 1879
	change_mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
		      X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF |
		      X86_EFLAGS_TF | X86_EFLAGS_DF | X86_EFLAGS_NT |
		      X86_EFLAGS_AC | X86_EFLAGS_ID;
1880

1881 1882 1883 1884 1885
	switch(ctxt->mode) {
	case X86EMUL_MODE_PROT64:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT16:
		if (cpl == 0)
1886
			change_mask |= X86_EFLAGS_IOPL;
1887
		if (cpl <= iopl)
1888
			change_mask |= X86_EFLAGS_IF;
1889 1890
		break;
	case X86EMUL_MODE_VM86:
1891 1892
		if (iopl < 3)
			return emulate_gp(ctxt, 0);
1893
		change_mask |= X86_EFLAGS_IF;
1894 1895
		break;
	default: /* real mode */
1896
		change_mask |= (X86_EFLAGS_IOPL | X86_EFLAGS_IF);
1897
		break;
1898
	}
1899 1900 1901 1902 1903

	*(unsigned long *)dest =
		(ctxt->eflags & ~change_mask) | (val & change_mask);

	return rc;
1904 1905
}

1906 1907
static int em_popf(struct x86_emulate_ctxt *ctxt)
{
1908 1909 1910 1911
	ctxt->dst.type = OP_REG;
	ctxt->dst.addr.reg = &ctxt->eflags;
	ctxt->dst.bytes = ctxt->op_bytes;
	return emulate_popf(ctxt, &ctxt->dst.val, ctxt->op_bytes);
1912 1913
}

A
Avi Kivity 已提交
1914 1915 1916 1917 1918
static int em_enter(struct x86_emulate_ctxt *ctxt)
{
	int rc;
	unsigned frame_size = ctxt->src.val;
	unsigned nesting_level = ctxt->src2.val & 31;
1919
	ulong rbp;
A
Avi Kivity 已提交
1920 1921 1922 1923

	if (nesting_level)
		return X86EMUL_UNHANDLEABLE;

1924 1925
	rbp = reg_read(ctxt, VCPU_REGS_RBP);
	rc = push(ctxt, &rbp, stack_size(ctxt));
A
Avi Kivity 已提交
1926 1927
	if (rc != X86EMUL_CONTINUE)
		return rc;
1928
	assign_masked(reg_rmw(ctxt, VCPU_REGS_RBP), reg_read(ctxt, VCPU_REGS_RSP),
A
Avi Kivity 已提交
1929
		      stack_mask(ctxt));
1930 1931
	assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP),
		      reg_read(ctxt, VCPU_REGS_RSP) - frame_size,
A
Avi Kivity 已提交
1932 1933 1934 1935
		      stack_mask(ctxt));
	return X86EMUL_CONTINUE;
}

A
Avi Kivity 已提交
1936 1937
static int em_leave(struct x86_emulate_ctxt *ctxt)
{
1938
	assign_masked(reg_rmw(ctxt, VCPU_REGS_RSP), reg_read(ctxt, VCPU_REGS_RBP),
A
Avi Kivity 已提交
1939
		      stack_mask(ctxt));
1940
	return emulate_pop(ctxt, reg_rmw(ctxt, VCPU_REGS_RBP), ctxt->op_bytes);
A
Avi Kivity 已提交
1941 1942
}

1943
static int em_push_sreg(struct x86_emulate_ctxt *ctxt)
1944
{
1945 1946
	int seg = ctxt->src2.val;

1947
	ctxt->src.val = get_segment_selector(ctxt, seg);
1948 1949 1950 1951
	if (ctxt->op_bytes == 4) {
		rsp_increment(ctxt, -2);
		ctxt->op_bytes = 2;
	}
1952

1953
	return em_push(ctxt);
1954 1955
}

1956
static int em_pop_sreg(struct x86_emulate_ctxt *ctxt)
1957
{
1958
	int seg = ctxt->src2.val;
1959 1960
	unsigned long selector;
	int rc;
1961

1962
	rc = emulate_pop(ctxt, &selector, 2);
1963 1964 1965
	if (rc != X86EMUL_CONTINUE)
		return rc;

1966 1967
	if (ctxt->modrm_reg == VCPU_SREG_SS)
		ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
1968 1969
	if (ctxt->op_bytes > 2)
		rsp_increment(ctxt, ctxt->op_bytes - 2);
1970

1971
	rc = load_segment_descriptor(ctxt, (u16)selector, seg);
1972
	return rc;
1973 1974
}

1975
static int em_pusha(struct x86_emulate_ctxt *ctxt)
1976
{
1977
	unsigned long old_esp = reg_read(ctxt, VCPU_REGS_RSP);
1978 1979
	int rc = X86EMUL_CONTINUE;
	int reg = VCPU_REGS_RAX;
1980

1981 1982
	while (reg <= VCPU_REGS_RDI) {
		(reg == VCPU_REGS_RSP) ?
1983
		(ctxt->src.val = old_esp) : (ctxt->src.val = reg_read(ctxt, reg));
1984

1985
		rc = em_push(ctxt);
1986 1987
		if (rc != X86EMUL_CONTINUE)
			return rc;
1988

1989
		++reg;
1990 1991
	}

1992
	return rc;
1993 1994
}

1995 1996
static int em_pushf(struct x86_emulate_ctxt *ctxt)
{
1997
	ctxt->src.val = (unsigned long)ctxt->eflags & ~X86_EFLAGS_VM;
1998 1999 2000
	return em_push(ctxt);
}

2001
static int em_popa(struct x86_emulate_ctxt *ctxt)
2002
{
2003 2004
	int rc = X86EMUL_CONTINUE;
	int reg = VCPU_REGS_RDI;
2005
	u32 val;
2006

2007 2008
	while (reg >= VCPU_REGS_RAX) {
		if (reg == VCPU_REGS_RSP) {
2009
			rsp_increment(ctxt, ctxt->op_bytes);
2010 2011
			--reg;
		}
2012

2013
		rc = emulate_pop(ctxt, &val, ctxt->op_bytes);
2014 2015
		if (rc != X86EMUL_CONTINUE)
			break;
2016
		assign_register(reg_rmw(ctxt, reg), val, ctxt->op_bytes);
2017
		--reg;
2018
	}
2019
	return rc;
2020 2021
}

2022
static int __emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
2023
{
2024
	const struct x86_emulate_ops *ops = ctxt->ops;
2025
	int rc;
2026 2027 2028 2029 2030 2031
	struct desc_ptr dt;
	gva_t cs_addr;
	gva_t eip_addr;
	u16 cs, eip;

	/* TODO: Add limit checks */
2032
	ctxt->src.val = ctxt->eflags;
2033
	rc = em_push(ctxt);
2034 2035
	if (rc != X86EMUL_CONTINUE)
		return rc;
2036

2037
	ctxt->eflags &= ~(X86_EFLAGS_IF | X86_EFLAGS_TF | X86_EFLAGS_AC);
2038

2039
	ctxt->src.val = get_segment_selector(ctxt, VCPU_SREG_CS);
2040
	rc = em_push(ctxt);
2041 2042
	if (rc != X86EMUL_CONTINUE)
		return rc;
2043

2044
	ctxt->src.val = ctxt->_eip;
2045
	rc = em_push(ctxt);
2046 2047 2048
	if (rc != X86EMUL_CONTINUE)
		return rc;

2049
	ops->get_idt(ctxt, &dt);
2050 2051 2052 2053

	eip_addr = dt.address + (irq << 2);
	cs_addr = dt.address + (irq << 2) + 2;

2054
	rc = ops->read_std(ctxt, cs_addr, &cs, 2, &ctxt->exception);
2055 2056 2057
	if (rc != X86EMUL_CONTINUE)
		return rc;

2058
	rc = ops->read_std(ctxt, eip_addr, &eip, 2, &ctxt->exception);
2059 2060 2061
	if (rc != X86EMUL_CONTINUE)
		return rc;

2062
	rc = load_segment_descriptor(ctxt, cs, VCPU_SREG_CS);
2063 2064 2065
	if (rc != X86EMUL_CONTINUE)
		return rc;

2066
	ctxt->_eip = eip;
2067 2068 2069 2070

	return rc;
}

2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081
int emulate_int_real(struct x86_emulate_ctxt *ctxt, int irq)
{
	int rc;

	invalidate_registers(ctxt);
	rc = __emulate_int_real(ctxt, irq);
	if (rc == X86EMUL_CONTINUE)
		writeback_registers(ctxt);
	return rc;
}

2082
static int emulate_int(struct x86_emulate_ctxt *ctxt, int irq)
2083 2084 2085
{
	switch(ctxt->mode) {
	case X86EMUL_MODE_REAL:
2086
		return __emulate_int_real(ctxt, irq);
2087 2088 2089 2090 2091 2092 2093 2094 2095 2096
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT64:
	default:
		/* Protected mode interrupts unimplemented yet */
		return X86EMUL_UNHANDLEABLE;
	}
}

2097
static int emulate_iret_real(struct x86_emulate_ctxt *ctxt)
2098
{
2099 2100 2101 2102
	int rc = X86EMUL_CONTINUE;
	unsigned long temp_eip = 0;
	unsigned long temp_eflags = 0;
	unsigned long cs = 0;
2103 2104 2105 2106 2107
	unsigned long mask = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
			     X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_TF |
			     X86_EFLAGS_IF | X86_EFLAGS_DF | X86_EFLAGS_OF |
			     X86_EFLAGS_IOPL | X86_EFLAGS_NT | X86_EFLAGS_RF |
			     X86_EFLAGS_AC | X86_EFLAGS_ID |
W
Wanpeng Li 已提交
2108
			     X86_EFLAGS_FIXED;
2109 2110
	unsigned long vm86_mask = X86_EFLAGS_VM | X86_EFLAGS_VIF |
				  X86_EFLAGS_VIP;
2111

2112
	/* TODO: Add stack limit check */
2113

2114
	rc = emulate_pop(ctxt, &temp_eip, ctxt->op_bytes);
2115

2116 2117
	if (rc != X86EMUL_CONTINUE)
		return rc;
2118

2119 2120
	if (temp_eip & ~0xffff)
		return emulate_gp(ctxt, 0);
2121

2122
	rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
2123

2124 2125
	if (rc != X86EMUL_CONTINUE)
		return rc;
2126

2127
	rc = emulate_pop(ctxt, &temp_eflags, ctxt->op_bytes);
2128

2129 2130
	if (rc != X86EMUL_CONTINUE)
		return rc;
2131

2132
	rc = load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS);
2133

2134 2135
	if (rc != X86EMUL_CONTINUE)
		return rc;
2136

2137
	ctxt->_eip = temp_eip;
2138

2139
	if (ctxt->op_bytes == 4)
2140
		ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
2141
	else if (ctxt->op_bytes == 2) {
2142 2143
		ctxt->eflags &= ~0xffff;
		ctxt->eflags |= temp_eflags;
2144
	}
2145 2146

	ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
W
Wanpeng Li 已提交
2147
	ctxt->eflags |= X86_EFLAGS_FIXED;
2148
	ctxt->ops->set_nmi_mask(ctxt, false);
2149 2150

	return rc;
2151 2152
}

2153
static int em_iret(struct x86_emulate_ctxt *ctxt)
2154
{
2155 2156
	switch(ctxt->mode) {
	case X86EMUL_MODE_REAL:
2157
		return emulate_iret_real(ctxt);
2158 2159 2160 2161
	case X86EMUL_MODE_VM86:
	case X86EMUL_MODE_PROT16:
	case X86EMUL_MODE_PROT32:
	case X86EMUL_MODE_PROT64:
2162
	default:
2163 2164
		/* iret from protected mode unimplemented yet */
		return X86EMUL_UNHANDLEABLE;
2165 2166 2167
	}
}

2168 2169 2170
static int em_jmp_far(struct x86_emulate_ctxt *ctxt)
{
	int rc;
2171 2172
	unsigned short sel;
	struct desc_struct new_desc;
2173 2174
	u8 cpl = ctxt->ops->cpl(ctxt);

2175
	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2176

2177 2178
	rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
				       X86_TRANSFER_CALL_JMP,
2179
				       &new_desc);
2180 2181 2182
	if (rc != X86EMUL_CONTINUE)
		return rc;

2183
	rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
2184 2185 2186 2187
	/* Error handling is not implemented. */
	if (rc != X86EMUL_CONTINUE)
		return X86EMUL_UNHANDLEABLE;

2188
	return rc;
2189 2190
}

2191
static int em_jmp_abs(struct x86_emulate_ctxt *ctxt)
2192
{
2193 2194
	return assign_eip_near(ctxt, ctxt->src.val);
}
2195

2196 2197 2198 2199 2200 2201 2202 2203 2204 2205 2206
static int em_call_near_abs(struct x86_emulate_ctxt *ctxt)
{
	int rc;
	long int old_eip;

	old_eip = ctxt->_eip;
	rc = assign_eip_near(ctxt, ctxt->src.val);
	if (rc != X86EMUL_CONTINUE)
		return rc;
	ctxt->src.val = old_eip;
	rc = em_push(ctxt);
2207
	return rc;
2208 2209
}

2210
static int em_cmpxchg8b(struct x86_emulate_ctxt *ctxt)
2211
{
2212
	u64 old = ctxt->dst.orig_val64;
2213

2214 2215 2216
	if (ctxt->dst.bytes == 16)
		return X86EMUL_UNHANDLEABLE;

2217 2218 2219 2220
	if (((u32) (old >> 0) != (u32) reg_read(ctxt, VCPU_REGS_RAX)) ||
	    ((u32) (old >> 32) != (u32) reg_read(ctxt, VCPU_REGS_RDX))) {
		*reg_write(ctxt, VCPU_REGS_RAX) = (u32) (old >> 0);
		*reg_write(ctxt, VCPU_REGS_RDX) = (u32) (old >> 32);
2221
		ctxt->eflags &= ~X86_EFLAGS_ZF;
2222
	} else {
2223 2224
		ctxt->dst.val64 = ((u64)reg_read(ctxt, VCPU_REGS_RCX) << 32) |
			(u32) reg_read(ctxt, VCPU_REGS_RBX);
2225

2226
		ctxt->eflags |= X86_EFLAGS_ZF;
2227
	}
2228
	return X86EMUL_CONTINUE;
2229 2230
}

2231 2232
static int em_ret(struct x86_emulate_ctxt *ctxt)
{
2233 2234 2235 2236 2237 2238 2239 2240
	int rc;
	unsigned long eip;

	rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	return assign_eip_near(ctxt, eip);
2241 2242
}

2243
static int em_ret_far(struct x86_emulate_ctxt *ctxt)
2244 2245
{
	int rc;
2246
	unsigned long eip, cs;
2247
	int cpl = ctxt->ops->cpl(ctxt);
2248
	struct desc_struct new_desc;
2249

2250
	rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
2251
	if (rc != X86EMUL_CONTINUE)
2252
		return rc;
2253
	rc = emulate_pop(ctxt, &cs, ctxt->op_bytes);
2254
	if (rc != X86EMUL_CONTINUE)
2255
		return rc;
2256 2257 2258
	/* Outer-privilege level return is not implemented */
	if (ctxt->mode >= X86EMUL_MODE_PROT16 && (cs & 3) > cpl)
		return X86EMUL_UNHANDLEABLE;
2259 2260
	rc = __load_segment_descriptor(ctxt, (u16)cs, VCPU_SREG_CS, cpl,
				       X86_TRANSFER_RET,
2261 2262 2263
				       &new_desc);
	if (rc != X86EMUL_CONTINUE)
		return rc;
2264
	rc = assign_eip_far(ctxt, eip, &new_desc);
2265 2266 2267 2268
	/* Error handling is not implemented. */
	if (rc != X86EMUL_CONTINUE)
		return X86EMUL_UNHANDLEABLE;

2269 2270 2271
	return rc;
}

2272 2273 2274 2275 2276 2277 2278 2279 2280 2281 2282
static int em_ret_far_imm(struct x86_emulate_ctxt *ctxt)
{
        int rc;

        rc = em_ret_far(ctxt);
        if (rc != X86EMUL_CONTINUE)
                return rc;
        rsp_increment(ctxt, ctxt->src.val);
        return X86EMUL_CONTINUE;
}

2283 2284 2285
static int em_cmpxchg(struct x86_emulate_ctxt *ctxt)
{
	/* Save real source value, then compare EAX against destination. */
2286 2287
	ctxt->dst.orig_val = ctxt->dst.val;
	ctxt->dst.val = reg_read(ctxt, VCPU_REGS_RAX);
2288
	ctxt->src.orig_val = ctxt->src.val;
2289
	ctxt->src.val = ctxt->dst.orig_val;
2290
	fastop(ctxt, em_cmp);
2291

2292
	if (ctxt->eflags & X86_EFLAGS_ZF) {
2293 2294
		/* Success: write back to memory; no update of EAX */
		ctxt->src.type = OP_NONE;
2295 2296 2297
		ctxt->dst.val = ctxt->src.orig_val;
	} else {
		/* Failure: write the value we saw to EAX. */
2298 2299 2300 2301
		ctxt->src.type = OP_REG;
		ctxt->src.addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
		ctxt->src.val = ctxt->dst.orig_val;
		/* Create write-cycle to dest by writing the same value */
2302
		ctxt->dst.val = ctxt->dst.orig_val;
2303 2304 2305 2306
	}
	return X86EMUL_CONTINUE;
}

2307
static int em_lseg(struct x86_emulate_ctxt *ctxt)
2308
{
2309
	int seg = ctxt->src2.val;
2310 2311 2312
	unsigned short sel;
	int rc;

2313
	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
2314

2315
	rc = load_segment_descriptor(ctxt, sel, seg);
2316 2317 2318
	if (rc != X86EMUL_CONTINUE)
		return rc;

2319
	ctxt->dst.val = ctxt->src.val;
2320 2321 2322
	return rc;
}

2323 2324 2325 2326 2327 2328
static int emulator_has_longmode(struct x86_emulate_ctxt *ctxt)
{
	u32 eax, ebx, ecx, edx;

	eax = 0x80000001;
	ecx = 0;
2329
	ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
2330 2331 2332 2333 2334 2335
	return edx & bit(X86_FEATURE_LM);
}

#define GET_SMSTATE(type, smbase, offset)				  \
	({								  \
	 type __val;							  \
2336 2337
	 int r = ctxt->ops->read_phys(ctxt, smbase + offset, &__val,      \
				      sizeof(__val));			  \
2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394
	 if (r != X86EMUL_CONTINUE)					  \
		 return X86EMUL_UNHANDLEABLE;				  \
	 __val;								  \
	})

static void rsm_set_desc_flags(struct desc_struct *desc, u32 flags)
{
	desc->g    = (flags >> 23) & 1;
	desc->d    = (flags >> 22) & 1;
	desc->l    = (flags >> 21) & 1;
	desc->avl  = (flags >> 20) & 1;
	desc->p    = (flags >> 15) & 1;
	desc->dpl  = (flags >> 13) & 3;
	desc->s    = (flags >> 12) & 1;
	desc->type = (flags >>  8) & 15;
}

static int rsm_load_seg_32(struct x86_emulate_ctxt *ctxt, u64 smbase, int n)
{
	struct desc_struct desc;
	int offset;
	u16 selector;

	selector = GET_SMSTATE(u32, smbase, 0x7fa8 + n * 4);

	if (n < 3)
		offset = 0x7f84 + n * 12;
	else
		offset = 0x7f2c + (n - 3) * 12;

	set_desc_base(&desc,      GET_SMSTATE(u32, smbase, offset + 8));
	set_desc_limit(&desc,     GET_SMSTATE(u32, smbase, offset + 4));
	rsm_set_desc_flags(&desc, GET_SMSTATE(u32, smbase, offset));
	ctxt->ops->set_segment(ctxt, selector, &desc, 0, n);
	return X86EMUL_CONTINUE;
}

static int rsm_load_seg_64(struct x86_emulate_ctxt *ctxt, u64 smbase, int n)
{
	struct desc_struct desc;
	int offset;
	u16 selector;
	u32 base3;

	offset = 0x7e00 + n * 16;

	selector =                GET_SMSTATE(u16, smbase, offset);
	rsm_set_desc_flags(&desc, GET_SMSTATE(u16, smbase, offset + 2) << 8);
	set_desc_limit(&desc,     GET_SMSTATE(u32, smbase, offset + 4));
	set_desc_base(&desc,      GET_SMSTATE(u32, smbase, offset + 8));
	base3 =                   GET_SMSTATE(u32, smbase, offset + 12);

	ctxt->ops->set_segment(ctxt, selector, &desc, base3, n);
	return X86EMUL_CONTINUE;
}

static int rsm_enter_protected_mode(struct x86_emulate_ctxt *ctxt,
2395
				    u64 cr0, u64 cr3, u64 cr4)
2396 2397
{
	int bad;
2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409
	u64 pcid;

	/* In order to later set CR4.PCIDE, CR3[11:0] must be zero.  */
	pcid = 0;
	if (cr4 & X86_CR4_PCIDE) {
		pcid = cr3 & 0xfff;
		cr3 &= ~0xfff;
	}

	bad = ctxt->ops->set_cr(ctxt, 3, cr3);
	if (bad)
		return X86EMUL_UNHANDLEABLE;
2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427

	/*
	 * First enable PAE, long mode needs it before CR0.PG = 1 is set.
	 * Then enable protected mode.	However, PCID cannot be enabled
	 * if EFER.LMA=0, so set it separately.
	 */
	bad = ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE);
	if (bad)
		return X86EMUL_UNHANDLEABLE;

	bad = ctxt->ops->set_cr(ctxt, 0, cr0);
	if (bad)
		return X86EMUL_UNHANDLEABLE;

	if (cr4 & X86_CR4_PCIDE) {
		bad = ctxt->ops->set_cr(ctxt, 4, cr4);
		if (bad)
			return X86EMUL_UNHANDLEABLE;
2428 2429 2430 2431 2432 2433
		if (pcid) {
			bad = ctxt->ops->set_cr(ctxt, 3, cr3 | pcid);
			if (bad)
				return X86EMUL_UNHANDLEABLE;
		}

2434 2435 2436 2437 2438 2439 2440 2441 2442 2443
	}

	return X86EMUL_CONTINUE;
}

static int rsm_load_state_32(struct x86_emulate_ctxt *ctxt, u64 smbase)
{
	struct desc_struct desc;
	struct desc_ptr dt;
	u16 selector;
2444
	u32 val, cr0, cr3, cr4;
2445 2446 2447
	int i;

	cr0 =                      GET_SMSTATE(u32, smbase, 0x7ffc);
2448
	cr3 =                      GET_SMSTATE(u32, smbase, 0x7ff8);
2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489
	ctxt->eflags =             GET_SMSTATE(u32, smbase, 0x7ff4) | X86_EFLAGS_FIXED;
	ctxt->_eip =               GET_SMSTATE(u32, smbase, 0x7ff0);

	for (i = 0; i < 8; i++)
		*reg_write(ctxt, i) = GET_SMSTATE(u32, smbase, 0x7fd0 + i * 4);

	val = GET_SMSTATE(u32, smbase, 0x7fcc);
	ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1);
	val = GET_SMSTATE(u32, smbase, 0x7fc8);
	ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1);

	selector =                 GET_SMSTATE(u32, smbase, 0x7fc4);
	set_desc_base(&desc,       GET_SMSTATE(u32, smbase, 0x7f64));
	set_desc_limit(&desc,      GET_SMSTATE(u32, smbase, 0x7f60));
	rsm_set_desc_flags(&desc,  GET_SMSTATE(u32, smbase, 0x7f5c));
	ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_TR);

	selector =                 GET_SMSTATE(u32, smbase, 0x7fc0);
	set_desc_base(&desc,       GET_SMSTATE(u32, smbase, 0x7f80));
	set_desc_limit(&desc,      GET_SMSTATE(u32, smbase, 0x7f7c));
	rsm_set_desc_flags(&desc,  GET_SMSTATE(u32, smbase, 0x7f78));
	ctxt->ops->set_segment(ctxt, selector, &desc, 0, VCPU_SREG_LDTR);

	dt.address =               GET_SMSTATE(u32, smbase, 0x7f74);
	dt.size =                  GET_SMSTATE(u32, smbase, 0x7f70);
	ctxt->ops->set_gdt(ctxt, &dt);

	dt.address =               GET_SMSTATE(u32, smbase, 0x7f58);
	dt.size =                  GET_SMSTATE(u32, smbase, 0x7f54);
	ctxt->ops->set_idt(ctxt, &dt);

	for (i = 0; i < 6; i++) {
		int r = rsm_load_seg_32(ctxt, smbase, i);
		if (r != X86EMUL_CONTINUE)
			return r;
	}

	cr4 = GET_SMSTATE(u32, smbase, 0x7f14);

	ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smbase, 0x7ef8));

2490
	return rsm_enter_protected_mode(ctxt, cr0, cr3, cr4);
2491 2492 2493 2494 2495 2496
}

static int rsm_load_state_64(struct x86_emulate_ctxt *ctxt, u64 smbase)
{
	struct desc_struct desc;
	struct desc_ptr dt;
2497
	u64 val, cr0, cr3, cr4;
2498 2499
	u32 base3;
	u16 selector;
2500
	int i, r;
2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513

	for (i = 0; i < 16; i++)
		*reg_write(ctxt, i) = GET_SMSTATE(u64, smbase, 0x7ff8 - i * 8);

	ctxt->_eip   = GET_SMSTATE(u64, smbase, 0x7f78);
	ctxt->eflags = GET_SMSTATE(u32, smbase, 0x7f70) | X86_EFLAGS_FIXED;

	val = GET_SMSTATE(u32, smbase, 0x7f68);
	ctxt->ops->set_dr(ctxt, 6, (val & DR6_VOLATILE) | DR6_FIXED_1);
	val = GET_SMSTATE(u32, smbase, 0x7f60);
	ctxt->ops->set_dr(ctxt, 7, (val & DR7_VOLATILE) | DR7_FIXED_1);

	cr0 =                       GET_SMSTATE(u64, smbase, 0x7f58);
2514
	cr3 =                       GET_SMSTATE(u64, smbase, 0x7f50);
2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541
	cr4 =                       GET_SMSTATE(u64, smbase, 0x7f48);
	ctxt->ops->set_smbase(ctxt, GET_SMSTATE(u32, smbase, 0x7f00));
	val =                       GET_SMSTATE(u64, smbase, 0x7ed0);
	ctxt->ops->set_msr(ctxt, MSR_EFER, val & ~EFER_LMA);

	selector =                  GET_SMSTATE(u32, smbase, 0x7e90);
	rsm_set_desc_flags(&desc,   GET_SMSTATE(u32, smbase, 0x7e92) << 8);
	set_desc_limit(&desc,       GET_SMSTATE(u32, smbase, 0x7e94));
	set_desc_base(&desc,        GET_SMSTATE(u32, smbase, 0x7e98));
	base3 =                     GET_SMSTATE(u32, smbase, 0x7e9c);
	ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_TR);

	dt.size =                   GET_SMSTATE(u32, smbase, 0x7e84);
	dt.address =                GET_SMSTATE(u64, smbase, 0x7e88);
	ctxt->ops->set_idt(ctxt, &dt);

	selector =                  GET_SMSTATE(u32, smbase, 0x7e70);
	rsm_set_desc_flags(&desc,   GET_SMSTATE(u32, smbase, 0x7e72) << 8);
	set_desc_limit(&desc,       GET_SMSTATE(u32, smbase, 0x7e74));
	set_desc_base(&desc,        GET_SMSTATE(u32, smbase, 0x7e78));
	base3 =                     GET_SMSTATE(u32, smbase, 0x7e7c);
	ctxt->ops->set_segment(ctxt, selector, &desc, base3, VCPU_SREG_LDTR);

	dt.size =                   GET_SMSTATE(u32, smbase, 0x7e64);
	dt.address =                GET_SMSTATE(u64, smbase, 0x7e68);
	ctxt->ops->set_gdt(ctxt, &dt);

2542
	r = rsm_enter_protected_mode(ctxt, cr0, cr3, cr4);
2543 2544 2545
	if (r != X86EMUL_CONTINUE)
		return r;

2546
	for (i = 0; i < 6; i++) {
2547
		r = rsm_load_seg_64(ctxt, smbase, i);
2548 2549 2550 2551
		if (r != X86EMUL_CONTINUE)
			return r;
	}

2552
	return X86EMUL_CONTINUE;
2553 2554
}

P
Paolo Bonzini 已提交
2555 2556
static int em_rsm(struct x86_emulate_ctxt *ctxt)
{
2557 2558 2559 2560
	unsigned long cr0, cr4, efer;
	u64 smbase;
	int ret;

2561
	if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_MASK) == 0)
P
Paolo Bonzini 已提交
2562 2563
		return emulate_ud(ctxt);

2564 2565
	/*
	 * Get back to real mode, to prepare a safe state in which to load
2566 2567
	 * CR0/CR3/CR4/EFER.  It's all a bit more complicated if the vCPU
	 * supports long mode.
2568
	 */
2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586
	cr4 = ctxt->ops->get_cr(ctxt, 4);
	if (emulator_has_longmode(ctxt)) {
		struct desc_struct cs_desc;

		/* Zero CR4.PCIDE before CR0.PG.  */
		if (cr4 & X86_CR4_PCIDE) {
			ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PCIDE);
			cr4 &= ~X86_CR4_PCIDE;
		}

		/* A 32-bit code segment is required to clear EFER.LMA.  */
		memset(&cs_desc, 0, sizeof(cs_desc));
		cs_desc.type = 0xb;
		cs_desc.s = cs_desc.g = cs_desc.p = 1;
		ctxt->ops->set_segment(ctxt, 0, &cs_desc, 0, VCPU_SREG_CS);
	}

	/* For the 64-bit case, this will clear EFER.LMA.  */
2587 2588 2589
	cr0 = ctxt->ops->get_cr(ctxt, 0);
	if (cr0 & X86_CR0_PE)
		ctxt->ops->set_cr(ctxt, 0, cr0 & ~(X86_CR0_PG | X86_CR0_PE));
2590 2591

	/* Now clear CR4.PAE (which must be done before clearing EFER.LME).  */
2592 2593
	if (cr4 & X86_CR4_PAE)
		ctxt->ops->set_cr(ctxt, 4, cr4 & ~X86_CR4_PAE);
2594 2595

	/* And finally go back to 32-bit mode.  */
2596 2597 2598 2599
	efer = 0;
	ctxt->ops->set_msr(ctxt, MSR_EFER, efer);

	smbase = ctxt->ops->get_smbase(ctxt);
2600 2601 2602 2603 2604 2605 2606 2607 2608

	/*
	 * Give pre_leave_smm() a chance to make ISA-specific changes to the
	 * vCPU state (e.g. enter guest mode) before loading state from the SMM
	 * state-save area.
	 */
	if (ctxt->ops->pre_leave_smm(ctxt, smbase))
		return X86EMUL_UNHANDLEABLE;

2609 2610 2611 2612 2613 2614 2615 2616 2617 2618
	if (emulator_has_longmode(ctxt))
		ret = rsm_load_state_64(ctxt, smbase + 0x8000);
	else
		ret = rsm_load_state_32(ctxt, smbase + 0x8000);

	if (ret != X86EMUL_CONTINUE) {
		/* FIXME: should triple fault */
		return X86EMUL_UNHANDLEABLE;
	}

2619
	if ((ctxt->ops->get_hflags(ctxt) & X86EMUL_SMM_INSIDE_NMI_MASK) == 0)
2620 2621
		ctxt->ops->set_nmi_mask(ctxt, false);

2622 2623
	ctxt->ops->set_hflags(ctxt, ctxt->ops->get_hflags(ctxt) &
		~(X86EMUL_SMM_INSIDE_NMI_MASK | X86EMUL_SMM_MASK));
2624
	return X86EMUL_CONTINUE;
P
Paolo Bonzini 已提交
2625 2626
}

2627
static void
2628
setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
2629
			struct desc_struct *cs, struct desc_struct *ss)
2630 2631
{
	cs->l = 0;		/* will be adjusted later */
2632
	set_desc_base(cs, 0);	/* flat segment */
2633
	cs->g = 1;		/* 4kb granularity */
2634
	set_desc_limit(cs, 0xfffff);	/* 4GB limit */
2635 2636 2637
	cs->type = 0x0b;	/* Read, Execute, Accessed */
	cs->s = 1;
	cs->dpl = 0;		/* will be adjusted later */
2638 2639
	cs->p = 1;
	cs->d = 1;
2640
	cs->avl = 0;
2641

2642 2643
	set_desc_base(ss, 0);	/* flat segment */
	set_desc_limit(ss, 0xfffff);	/* 4GB limit */
2644 2645 2646
	ss->g = 1;		/* 4kb granularity */
	ss->s = 1;
	ss->type = 0x03;	/* Read/Write, Accessed */
2647
	ss->d = 1;		/* 32bit stack segment */
2648
	ss->dpl = 0;
2649
	ss->p = 1;
2650 2651
	ss->l = 0;
	ss->avl = 0;
2652 2653
}

2654 2655 2656 2657 2658
static bool vendor_intel(struct x86_emulate_ctxt *ctxt)
{
	u32 eax, ebx, ecx, edx;

	eax = ecx = 0;
2659
	ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
2660
	return ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx
2661 2662 2663 2664
		&& ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx
		&& edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx;
}

2665 2666
static bool em_syscall_is_enabled(struct x86_emulate_ctxt *ctxt)
{
2667
	const struct x86_emulate_ops *ops = ctxt->ops;
2668 2669 2670 2671 2672 2673 2674 2675 2676 2677 2678
	u32 eax, ebx, ecx, edx;

	/*
	 * syscall should always be enabled in longmode - so only become
	 * vendor specific (cpuid) if other modes are active...
	 */
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		return true;

	eax = 0x00000000;
	ecx = 0x00000000;
2679
	ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697 2698 2699 2700 2701 2702 2703
	/*
	 * Intel ("GenuineIntel")
	 * remark: Intel CPUs only support "syscall" in 64bit
	 * longmode. Also an 64bit guest with a
	 * 32bit compat-app running will #UD !! While this
	 * behaviour can be fixed (by emulating) into AMD
	 * response - CPUs of AMD can't behave like Intel.
	 */
	if (ebx == X86EMUL_CPUID_VENDOR_GenuineIntel_ebx &&
	    ecx == X86EMUL_CPUID_VENDOR_GenuineIntel_ecx &&
	    edx == X86EMUL_CPUID_VENDOR_GenuineIntel_edx)
		return false;

	/* AMD ("AuthenticAMD") */
	if (ebx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ebx &&
	    ecx == X86EMUL_CPUID_VENDOR_AuthenticAMD_ecx &&
	    edx == X86EMUL_CPUID_VENDOR_AuthenticAMD_edx)
		return true;

	/* AMD ("AMDisbetter!") */
	if (ebx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ebx &&
	    ecx == X86EMUL_CPUID_VENDOR_AMDisbetterI_ecx &&
	    edx == X86EMUL_CPUID_VENDOR_AMDisbetterI_edx)
		return true;
2704 2705 2706 2707 2708

	/* default: (not Intel, not AMD), apply Intel's stricter rules... */
	return false;
}

2709
static int em_syscall(struct x86_emulate_ctxt *ctxt)
2710
{
2711
	const struct x86_emulate_ops *ops = ctxt->ops;
2712
	struct desc_struct cs, ss;
2713
	u64 msr_data;
2714
	u16 cs_sel, ss_sel;
2715
	u64 efer = 0;
2716 2717

	/* syscall is not available in real mode */
2718
	if (ctxt->mode == X86EMUL_MODE_REAL ||
2719 2720
	    ctxt->mode == X86EMUL_MODE_VM86)
		return emulate_ud(ctxt);
2721

2722 2723 2724
	if (!(em_syscall_is_enabled(ctxt)))
		return emulate_ud(ctxt);

2725
	ops->get_msr(ctxt, MSR_EFER, &efer);
2726
	setup_syscalls_segments(ctxt, &cs, &ss);
2727

2728 2729 2730
	if (!(efer & EFER_SCE))
		return emulate_ud(ctxt);

2731
	ops->get_msr(ctxt, MSR_STAR, &msr_data);
2732
	msr_data >>= 32;
2733 2734
	cs_sel = (u16)(msr_data & 0xfffc);
	ss_sel = (u16)(msr_data + 8);
2735

2736
	if (efer & EFER_LMA) {
2737
		cs.d = 0;
2738 2739
		cs.l = 1;
	}
2740 2741
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2742

2743
	*reg_write(ctxt, VCPU_REGS_RCX) = ctxt->_eip;
2744
	if (efer & EFER_LMA) {
2745
#ifdef CONFIG_X86_64
2746
		*reg_write(ctxt, VCPU_REGS_R11) = ctxt->eflags;
2747

2748
		ops->get_msr(ctxt,
2749 2750
			     ctxt->mode == X86EMUL_MODE_PROT64 ?
			     MSR_LSTAR : MSR_CSTAR, &msr_data);
2751
		ctxt->_eip = msr_data;
2752

2753
		ops->get_msr(ctxt, MSR_SYSCALL_MASK, &msr_data);
2754
		ctxt->eflags &= ~msr_data;
W
Wanpeng Li 已提交
2755
		ctxt->eflags |= X86_EFLAGS_FIXED;
2756 2757 2758
#endif
	} else {
		/* legacy mode */
2759
		ops->get_msr(ctxt, MSR_STAR, &msr_data);
2760
		ctxt->_eip = (u32)msr_data;
2761

2762
		ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
2763 2764
	}

2765
	ctxt->tf = (ctxt->eflags & X86_EFLAGS_TF) != 0;
2766
	return X86EMUL_CONTINUE;
2767 2768
}

2769
static int em_sysenter(struct x86_emulate_ctxt *ctxt)
2770
{
2771
	const struct x86_emulate_ops *ops = ctxt->ops;
2772
	struct desc_struct cs, ss;
2773
	u64 msr_data;
2774
	u16 cs_sel, ss_sel;
2775
	u64 efer = 0;
2776

2777
	ops->get_msr(ctxt, MSR_EFER, &efer);
2778
	/* inject #GP if in real mode */
2779 2780
	if (ctxt->mode == X86EMUL_MODE_REAL)
		return emulate_gp(ctxt, 0);
2781

2782 2783 2784 2785
	/*
	 * Not recognized on AMD in compat mode (but is recognized in legacy
	 * mode).
	 */
2786
	if ((ctxt->mode != X86EMUL_MODE_PROT64) && (efer & EFER_LMA)
2787 2788 2789
	    && !vendor_intel(ctxt))
		return emulate_ud(ctxt);

2790
	/* sysenter/sysexit have not been tested in 64bit mode. */
2791
	if (ctxt->mode == X86EMUL_MODE_PROT64)
2792
		return X86EMUL_UNHANDLEABLE;
2793

2794
	setup_syscalls_segments(ctxt, &cs, &ss);
2795

2796
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2797 2798
	if ((msr_data & 0xfffc) == 0x0)
		return emulate_gp(ctxt, 0);
2799

2800
	ctxt->eflags &= ~(X86_EFLAGS_VM | X86_EFLAGS_IF);
2801
	cs_sel = (u16)msr_data & ~SEGMENT_RPL_MASK;
2802
	ss_sel = cs_sel + 8;
2803
	if (efer & EFER_LMA) {
2804
		cs.d = 0;
2805 2806 2807
		cs.l = 1;
	}

2808 2809
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2810

2811
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_EIP, &msr_data);
2812
	ctxt->_eip = (efer & EFER_LMA) ? msr_data : (u32)msr_data;
2813

2814
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_ESP, &msr_data);
2815 2816
	*reg_write(ctxt, VCPU_REGS_RSP) = (efer & EFER_LMA) ? msr_data :
							      (u32)msr_data;
2817

2818
	return X86EMUL_CONTINUE;
2819 2820
}

2821
static int em_sysexit(struct x86_emulate_ctxt *ctxt)
2822
{
2823
	const struct x86_emulate_ops *ops = ctxt->ops;
2824
	struct desc_struct cs, ss;
2825
	u64 msr_data, rcx, rdx;
2826
	int usermode;
X
Xiao Guangrong 已提交
2827
	u16 cs_sel = 0, ss_sel = 0;
2828

2829 2830
	/* inject #GP if in real mode or Virtual 8086 mode */
	if (ctxt->mode == X86EMUL_MODE_REAL ||
2831 2832
	    ctxt->mode == X86EMUL_MODE_VM86)
		return emulate_gp(ctxt, 0);
2833

2834
	setup_syscalls_segments(ctxt, &cs, &ss);
2835

2836
	if ((ctxt->rex_prefix & 0x8) != 0x0)
2837 2838 2839 2840
		usermode = X86EMUL_MODE_PROT64;
	else
		usermode = X86EMUL_MODE_PROT32;

2841 2842 2843
	rcx = reg_read(ctxt, VCPU_REGS_RCX);
	rdx = reg_read(ctxt, VCPU_REGS_RDX);

2844 2845
	cs.dpl = 3;
	ss.dpl = 3;
2846
	ops->get_msr(ctxt, MSR_IA32_SYSENTER_CS, &msr_data);
2847 2848
	switch (usermode) {
	case X86EMUL_MODE_PROT32:
2849
		cs_sel = (u16)(msr_data + 16);
2850 2851
		if ((msr_data & 0xfffc) == 0x0)
			return emulate_gp(ctxt, 0);
2852
		ss_sel = (u16)(msr_data + 24);
2853 2854
		rcx = (u32)rcx;
		rdx = (u32)rdx;
2855 2856
		break;
	case X86EMUL_MODE_PROT64:
2857
		cs_sel = (u16)(msr_data + 32);
2858 2859
		if (msr_data == 0x0)
			return emulate_gp(ctxt, 0);
2860 2861
		ss_sel = cs_sel + 8;
		cs.d = 0;
2862
		cs.l = 1;
2863 2864
		if (emul_is_noncanonical_address(rcx, ctxt) ||
		    emul_is_noncanonical_address(rdx, ctxt))
2865
			return emulate_gp(ctxt, 0);
2866 2867
		break;
	}
2868 2869
	cs_sel |= SEGMENT_RPL_MASK;
	ss_sel |= SEGMENT_RPL_MASK;
2870

2871 2872
	ops->set_segment(ctxt, cs_sel, &cs, 0, VCPU_SREG_CS);
	ops->set_segment(ctxt, ss_sel, &ss, 0, VCPU_SREG_SS);
2873

2874 2875
	ctxt->_eip = rdx;
	*reg_write(ctxt, VCPU_REGS_RSP) = rcx;
2876

2877
	return X86EMUL_CONTINUE;
2878 2879
}

2880
static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt)
2881 2882 2883 2884 2885 2886
{
	int iopl;
	if (ctxt->mode == X86EMUL_MODE_REAL)
		return false;
	if (ctxt->mode == X86EMUL_MODE_VM86)
		return true;
2887
	iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> X86_EFLAGS_IOPL_BIT;
2888
	return ctxt->ops->cpl(ctxt) > iopl;
2889 2890
}

2891 2892 2893
#define VMWARE_PORT_VMPORT	(0x5658)
#define VMWARE_PORT_VMRPC	(0x5659)

2894 2895 2896
static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
					    u16 port, u16 len)
{
2897
	const struct x86_emulate_ops *ops = ctxt->ops;
2898
	struct desc_struct tr_seg;
2899
	u32 base3;
2900
	int r;
2901
	u16 tr, io_bitmap_ptr, perm, bit_idx = port & 0x7;
2902
	unsigned mask = (1 << len) - 1;
2903
	unsigned long base;
2904

2905 2906 2907 2908 2909 2910 2911 2912
	/*
	 * VMware allows access to these ports even if denied
	 * by TSS I/O permission bitmap. Mimic behavior.
	 */
	if (enable_vmware_backdoor &&
	    ((port == VMWARE_PORT_VMPORT) || (port == VMWARE_PORT_VMRPC)))
		return true;

2913
	ops->get_segment(ctxt, &tr, &tr_seg, &base3, VCPU_SREG_TR);
2914
	if (!tr_seg.p)
2915
		return false;
2916
	if (desc_limit_scaled(&tr_seg) < 103)
2917
		return false;
2918 2919 2920 2921
	base = get_desc_base(&tr_seg);
#ifdef CONFIG_X86_64
	base |= ((u64)base3) << 32;
#endif
2922
	r = ops->read_std(ctxt, base + 102, &io_bitmap_ptr, 2, NULL);
2923 2924
	if (r != X86EMUL_CONTINUE)
		return false;
2925
	if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
2926
		return false;
2927
	r = ops->read_std(ctxt, base + io_bitmap_ptr + port/8, &perm, 2, NULL);
2928 2929 2930 2931 2932 2933 2934 2935 2936 2937
	if (r != X86EMUL_CONTINUE)
		return false;
	if ((perm >> bit_idx) & mask)
		return false;
	return true;
}

static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
				 u16 port, u16 len)
{
2938 2939 2940
	if (ctxt->perm_ok)
		return true;

2941 2942
	if (emulator_bad_iopl(ctxt))
		if (!emulator_io_port_access_allowed(ctxt, port, len))
2943
			return false;
2944 2945 2946

	ctxt->perm_ok = true;

2947 2948 2949
	return true;
}

2950 2951 2952 2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968 2969 2970 2971 2972 2973
static void string_registers_quirk(struct x86_emulate_ctxt *ctxt)
{
	/*
	 * Intel CPUs mask the counter and pointers in quite strange
	 * manner when ECX is zero due to REP-string optimizations.
	 */
#ifdef CONFIG_X86_64
	if (ctxt->ad_bytes != 4 || !vendor_intel(ctxt))
		return;

	*reg_write(ctxt, VCPU_REGS_RCX) = 0;

	switch (ctxt->b) {
	case 0xa4:	/* movsb */
	case 0xa5:	/* movsd/w */
		*reg_rmw(ctxt, VCPU_REGS_RSI) &= (u32)-1;
		/* fall through */
	case 0xaa:	/* stosb */
	case 0xab:	/* stosd/w */
		*reg_rmw(ctxt, VCPU_REGS_RDI) &= (u32)-1;
	}
#endif
}

2974 2975 2976
static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
				struct tss_segment_16 *tss)
{
2977
	tss->ip = ctxt->_eip;
2978
	tss->flag = ctxt->eflags;
2979 2980 2981 2982 2983 2984 2985 2986
	tss->ax = reg_read(ctxt, VCPU_REGS_RAX);
	tss->cx = reg_read(ctxt, VCPU_REGS_RCX);
	tss->dx = reg_read(ctxt, VCPU_REGS_RDX);
	tss->bx = reg_read(ctxt, VCPU_REGS_RBX);
	tss->sp = reg_read(ctxt, VCPU_REGS_RSP);
	tss->bp = reg_read(ctxt, VCPU_REGS_RBP);
	tss->si = reg_read(ctxt, VCPU_REGS_RSI);
	tss->di = reg_read(ctxt, VCPU_REGS_RDI);
2987

2988 2989 2990 2991 2992
	tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
	tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
	tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
	tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
	tss->ldt = get_segment_selector(ctxt, VCPU_SREG_LDTR);
2993 2994 2995 2996 2997 2998
}

static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
				 struct tss_segment_16 *tss)
{
	int ret;
2999
	u8 cpl;
3000

3001
	ctxt->_eip = tss->ip;
3002
	ctxt->eflags = tss->flag | 2;
3003 3004 3005 3006 3007 3008 3009 3010
	*reg_write(ctxt, VCPU_REGS_RAX) = tss->ax;
	*reg_write(ctxt, VCPU_REGS_RCX) = tss->cx;
	*reg_write(ctxt, VCPU_REGS_RDX) = tss->dx;
	*reg_write(ctxt, VCPU_REGS_RBX) = tss->bx;
	*reg_write(ctxt, VCPU_REGS_RSP) = tss->sp;
	*reg_write(ctxt, VCPU_REGS_RBP) = tss->bp;
	*reg_write(ctxt, VCPU_REGS_RSI) = tss->si;
	*reg_write(ctxt, VCPU_REGS_RDI) = tss->di;
3011 3012 3013 3014 3015

	/*
	 * SDM says that segment selectors are loaded before segment
	 * descriptors
	 */
3016 3017 3018 3019 3020
	set_segment_selector(ctxt, tss->ldt, VCPU_SREG_LDTR);
	set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
	set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
	set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
	set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
3021

3022 3023
	cpl = tss->cs & 3;

3024
	/*
G
Guo Chao 已提交
3025
	 * Now load segment descriptors. If fault happens at this stage
3026 3027
	 * it is handled in a context of new task
	 */
3028
	ret = __load_segment_descriptor(ctxt, tss->ldt, VCPU_SREG_LDTR, cpl,
3029
					X86_TRANSFER_TASK_SWITCH, NULL);
3030 3031
	if (ret != X86EMUL_CONTINUE)
		return ret;
3032
	ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3033
					X86_TRANSFER_TASK_SWITCH, NULL);
3034 3035
	if (ret != X86EMUL_CONTINUE)
		return ret;
3036
	ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3037
					X86_TRANSFER_TASK_SWITCH, NULL);
3038 3039
	if (ret != X86EMUL_CONTINUE)
		return ret;
3040
	ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3041
					X86_TRANSFER_TASK_SWITCH, NULL);
3042 3043
	if (ret != X86EMUL_CONTINUE)
		return ret;
3044
	ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3045
					X86_TRANSFER_TASK_SWITCH, NULL);
3046 3047 3048 3049 3050 3051 3052 3053 3054 3055
	if (ret != X86EMUL_CONTINUE)
		return ret;

	return X86EMUL_CONTINUE;
}

static int task_switch_16(struct x86_emulate_ctxt *ctxt,
			  u16 tss_selector, u16 old_tss_sel,
			  ulong old_tss_base, struct desc_struct *new_desc)
{
3056
	const struct x86_emulate_ops *ops = ctxt->ops;
3057 3058
	struct tss_segment_16 tss_seg;
	int ret;
3059
	u32 new_tss_base = get_desc_base(new_desc);
3060

3061
	ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
3062
			    &ctxt->exception);
3063
	if (ret != X86EMUL_CONTINUE)
3064 3065
		return ret;

3066
	save_state_to_tss16(ctxt, &tss_seg);
3067

3068
	ret = ops->write_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
3069
			     &ctxt->exception);
3070
	if (ret != X86EMUL_CONTINUE)
3071 3072
		return ret;

3073
	ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
3074
			    &ctxt->exception);
3075
	if (ret != X86EMUL_CONTINUE)
3076 3077 3078 3079 3080
		return ret;

	if (old_tss_sel != 0xffff) {
		tss_seg.prev_task_link = old_tss_sel;

3081
		ret = ops->write_std(ctxt, new_tss_base,
3082 3083
				     &tss_seg.prev_task_link,
				     sizeof tss_seg.prev_task_link,
3084
				     &ctxt->exception);
3085
		if (ret != X86EMUL_CONTINUE)
3086 3087 3088
			return ret;
	}

3089
	return load_state_from_tss16(ctxt, &tss_seg);
3090 3091 3092 3093 3094
}

static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
				struct tss_segment_32 *tss)
{
3095
	/* CR3 and ldt selector are not saved intentionally */
3096
	tss->eip = ctxt->_eip;
3097
	tss->eflags = ctxt->eflags;
3098 3099 3100 3101 3102 3103 3104 3105
	tss->eax = reg_read(ctxt, VCPU_REGS_RAX);
	tss->ecx = reg_read(ctxt, VCPU_REGS_RCX);
	tss->edx = reg_read(ctxt, VCPU_REGS_RDX);
	tss->ebx = reg_read(ctxt, VCPU_REGS_RBX);
	tss->esp = reg_read(ctxt, VCPU_REGS_RSP);
	tss->ebp = reg_read(ctxt, VCPU_REGS_RBP);
	tss->esi = reg_read(ctxt, VCPU_REGS_RSI);
	tss->edi = reg_read(ctxt, VCPU_REGS_RDI);
3106

3107 3108 3109 3110 3111 3112
	tss->es = get_segment_selector(ctxt, VCPU_SREG_ES);
	tss->cs = get_segment_selector(ctxt, VCPU_SREG_CS);
	tss->ss = get_segment_selector(ctxt, VCPU_SREG_SS);
	tss->ds = get_segment_selector(ctxt, VCPU_SREG_DS);
	tss->fs = get_segment_selector(ctxt, VCPU_SREG_FS);
	tss->gs = get_segment_selector(ctxt, VCPU_SREG_GS);
3113 3114 3115 3116 3117 3118
}

static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
				 struct tss_segment_32 *tss)
{
	int ret;
3119
	u8 cpl;
3120

3121
	if (ctxt->ops->set_cr(ctxt, 3, tss->cr3))
3122
		return emulate_gp(ctxt, 0);
3123
	ctxt->_eip = tss->eip;
3124
	ctxt->eflags = tss->eflags | 2;
3125 3126

	/* General purpose registers */
3127 3128 3129 3130 3131 3132 3133 3134
	*reg_write(ctxt, VCPU_REGS_RAX) = tss->eax;
	*reg_write(ctxt, VCPU_REGS_RCX) = tss->ecx;
	*reg_write(ctxt, VCPU_REGS_RDX) = tss->edx;
	*reg_write(ctxt, VCPU_REGS_RBX) = tss->ebx;
	*reg_write(ctxt, VCPU_REGS_RSP) = tss->esp;
	*reg_write(ctxt, VCPU_REGS_RBP) = tss->ebp;
	*reg_write(ctxt, VCPU_REGS_RSI) = tss->esi;
	*reg_write(ctxt, VCPU_REGS_RDI) = tss->edi;
3135 3136 3137

	/*
	 * SDM says that segment selectors are loaded before segment
3138 3139
	 * descriptors.  This is important because CPL checks will
	 * use CS.RPL.
3140
	 */
3141 3142 3143 3144 3145 3146 3147
	set_segment_selector(ctxt, tss->ldt_selector, VCPU_SREG_LDTR);
	set_segment_selector(ctxt, tss->es, VCPU_SREG_ES);
	set_segment_selector(ctxt, tss->cs, VCPU_SREG_CS);
	set_segment_selector(ctxt, tss->ss, VCPU_SREG_SS);
	set_segment_selector(ctxt, tss->ds, VCPU_SREG_DS);
	set_segment_selector(ctxt, tss->fs, VCPU_SREG_FS);
	set_segment_selector(ctxt, tss->gs, VCPU_SREG_GS);
3148

3149 3150 3151 3152 3153
	/*
	 * If we're switching between Protected Mode and VM86, we need to make
	 * sure to update the mode before loading the segment descriptors so
	 * that the selectors are interpreted correctly.
	 */
3154
	if (ctxt->eflags & X86_EFLAGS_VM) {
3155
		ctxt->mode = X86EMUL_MODE_VM86;
3156 3157
		cpl = 3;
	} else {
3158
		ctxt->mode = X86EMUL_MODE_PROT32;
3159 3160
		cpl = tss->cs & 3;
	}
3161

3162 3163 3164 3165
	/*
	 * Now load segment descriptors. If fault happenes at this stage
	 * it is handled in a context of new task
	 */
3166
	ret = __load_segment_descriptor(ctxt, tss->ldt_selector, VCPU_SREG_LDTR,
3167
					cpl, X86_TRANSFER_TASK_SWITCH, NULL);
3168 3169
	if (ret != X86EMUL_CONTINUE)
		return ret;
3170
	ret = __load_segment_descriptor(ctxt, tss->es, VCPU_SREG_ES, cpl,
3171
					X86_TRANSFER_TASK_SWITCH, NULL);
3172 3173
	if (ret != X86EMUL_CONTINUE)
		return ret;
3174
	ret = __load_segment_descriptor(ctxt, tss->cs, VCPU_SREG_CS, cpl,
3175
					X86_TRANSFER_TASK_SWITCH, NULL);
3176 3177
	if (ret != X86EMUL_CONTINUE)
		return ret;
3178
	ret = __load_segment_descriptor(ctxt, tss->ss, VCPU_SREG_SS, cpl,
3179
					X86_TRANSFER_TASK_SWITCH, NULL);
3180 3181
	if (ret != X86EMUL_CONTINUE)
		return ret;
3182
	ret = __load_segment_descriptor(ctxt, tss->ds, VCPU_SREG_DS, cpl,
3183
					X86_TRANSFER_TASK_SWITCH, NULL);
3184 3185
	if (ret != X86EMUL_CONTINUE)
		return ret;
3186
	ret = __load_segment_descriptor(ctxt, tss->fs, VCPU_SREG_FS, cpl,
3187
					X86_TRANSFER_TASK_SWITCH, NULL);
3188 3189
	if (ret != X86EMUL_CONTINUE)
		return ret;
3190
	ret = __load_segment_descriptor(ctxt, tss->gs, VCPU_SREG_GS, cpl,
3191
					X86_TRANSFER_TASK_SWITCH, NULL);
3192

3193
	return ret;
3194 3195 3196 3197 3198 3199
}

static int task_switch_32(struct x86_emulate_ctxt *ctxt,
			  u16 tss_selector, u16 old_tss_sel,
			  ulong old_tss_base, struct desc_struct *new_desc)
{
3200
	const struct x86_emulate_ops *ops = ctxt->ops;
3201 3202
	struct tss_segment_32 tss_seg;
	int ret;
3203
	u32 new_tss_base = get_desc_base(new_desc);
3204 3205
	u32 eip_offset = offsetof(struct tss_segment_32, eip);
	u32 ldt_sel_offset = offsetof(struct tss_segment_32, ldt_selector);
3206

3207
	ret = ops->read_std(ctxt, old_tss_base, &tss_seg, sizeof tss_seg,
3208
			    &ctxt->exception);
3209
	if (ret != X86EMUL_CONTINUE)
3210 3211
		return ret;

3212
	save_state_to_tss32(ctxt, &tss_seg);
3213

3214 3215 3216
	/* Only GP registers and segment selectors are saved */
	ret = ops->write_std(ctxt, old_tss_base + eip_offset, &tss_seg.eip,
			     ldt_sel_offset - eip_offset, &ctxt->exception);
3217
	if (ret != X86EMUL_CONTINUE)
3218 3219
		return ret;

3220
	ret = ops->read_std(ctxt, new_tss_base, &tss_seg, sizeof tss_seg,
3221
			    &ctxt->exception);
3222
	if (ret != X86EMUL_CONTINUE)
3223 3224 3225 3226 3227
		return ret;

	if (old_tss_sel != 0xffff) {
		tss_seg.prev_task_link = old_tss_sel;

3228
		ret = ops->write_std(ctxt, new_tss_base,
3229 3230
				     &tss_seg.prev_task_link,
				     sizeof tss_seg.prev_task_link,
3231
				     &ctxt->exception);
3232
		if (ret != X86EMUL_CONTINUE)
3233 3234 3235
			return ret;
	}

3236
	return load_state_from_tss32(ctxt, &tss_seg);
3237 3238 3239
}

static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
3240
				   u16 tss_selector, int idt_index, int reason,
3241
				   bool has_error_code, u32 error_code)
3242
{
3243
	const struct x86_emulate_ops *ops = ctxt->ops;
3244 3245
	struct desc_struct curr_tss_desc, next_tss_desc;
	int ret;
3246
	u16 old_tss_sel = get_segment_selector(ctxt, VCPU_SREG_TR);
3247
	ulong old_tss_base =
3248
		ops->get_cached_segment_base(ctxt, VCPU_SREG_TR);
3249
	u32 desc_limit;
3250
	ulong desc_addr, dr7;
3251 3252 3253

	/* FIXME: old_tss_base == ~0 ? */

3254
	ret = read_segment_descriptor(ctxt, tss_selector, &next_tss_desc, &desc_addr);
3255 3256
	if (ret != X86EMUL_CONTINUE)
		return ret;
3257
	ret = read_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc, &desc_addr);
3258 3259 3260 3261 3262
	if (ret != X86EMUL_CONTINUE)
		return ret;

	/* FIXME: check that next_tss_desc is tss */

3263 3264 3265 3266 3267
	/*
	 * Check privileges. The three cases are task switch caused by...
	 *
	 * 1. jmp/call/int to task gate: Check against DPL of the task gate
	 * 2. Exception/IRQ/iret: No check is performed
3268 3269
	 * 3. jmp/call to TSS/task-gate: No check is performed since the
	 *    hardware checks it before exiting.
3270 3271 3272 3273 3274 3275 3276 3277 3278 3279 3280 3281 3282 3283 3284 3285
	 */
	if (reason == TASK_SWITCH_GATE) {
		if (idt_index != -1) {
			/* Software interrupts */
			struct desc_struct task_gate_desc;
			int dpl;

			ret = read_interrupt_descriptor(ctxt, idt_index,
							&task_gate_desc);
			if (ret != X86EMUL_CONTINUE)
				return ret;

			dpl = task_gate_desc.dpl;
			if ((tss_selector & 3) > dpl || ops->cpl(ctxt) > dpl)
				return emulate_gp(ctxt, (idt_index << 3) | 0x2);
		}
3286 3287
	}

3288 3289 3290 3291
	desc_limit = desc_limit_scaled(&next_tss_desc);
	if (!next_tss_desc.p ||
	    ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
	     desc_limit < 0x2b)) {
3292
		return emulate_ts(ctxt, tss_selector & 0xfffc);
3293 3294 3295 3296
	}

	if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
		curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
3297
		write_segment_descriptor(ctxt, old_tss_sel, &curr_tss_desc);
3298 3299 3300 3301 3302 3303
	}

	if (reason == TASK_SWITCH_IRET)
		ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;

	/* set back link to prev task only if NT bit is set in eflags
G
Guo Chao 已提交
3304
	   note that old_tss_sel is not used after this point */
3305 3306 3307 3308
	if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
		old_tss_sel = 0xffff;

	if (next_tss_desc.type & 8)
3309
		ret = task_switch_32(ctxt, tss_selector, old_tss_sel,
3310 3311
				     old_tss_base, &next_tss_desc);
	else
3312
		ret = task_switch_16(ctxt, tss_selector, old_tss_sel,
3313
				     old_tss_base, &next_tss_desc);
3314 3315
	if (ret != X86EMUL_CONTINUE)
		return ret;
3316 3317 3318 3319 3320 3321

	if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
		ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;

	if (reason != TASK_SWITCH_IRET) {
		next_tss_desc.type |= (1 << 1); /* set busy flag */
3322
		write_segment_descriptor(ctxt, tss_selector, &next_tss_desc);
3323 3324
	}

3325
	ops->set_cr(ctxt, 0,  ops->get_cr(ctxt, 0) | X86_CR0_TS);
3326
	ops->set_segment(ctxt, tss_selector, &next_tss_desc, 0, VCPU_SREG_TR);
3327

3328
	if (has_error_code) {
3329 3330 3331
		ctxt->op_bytes = ctxt->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
		ctxt->lock_prefix = 0;
		ctxt->src.val = (unsigned long) error_code;
3332
		ret = em_push(ctxt);
3333 3334
	}

3335 3336 3337
	ops->get_dr(ctxt, 7, &dr7);
	ops->set_dr(ctxt, 7, dr7 & ~(DR_LOCAL_ENABLE_MASK | DR_LOCAL_SLOWDOWN));

3338 3339 3340 3341
	return ret;
}

int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
3342
			 u16 tss_selector, int idt_index, int reason,
3343
			 bool has_error_code, u32 error_code)
3344 3345 3346
{
	int rc;

3347
	invalidate_registers(ctxt);
3348 3349
	ctxt->_eip = ctxt->eip;
	ctxt->dst.type = OP_NONE;
3350

3351
	rc = emulator_do_task_switch(ctxt, tss_selector, idt_index, reason,
3352
				     has_error_code, error_code);
3353

3354
	if (rc == X86EMUL_CONTINUE) {
3355
		ctxt->eip = ctxt->_eip;
3356 3357
		writeback_registers(ctxt);
	}
3358

3359
	return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
3360 3361
}

3362 3363
static void string_addr_inc(struct x86_emulate_ctxt *ctxt, int reg,
		struct operand *op)
3364
{
3365
	int df = (ctxt->eflags & X86_EFLAGS_DF) ? -op->count : op->count;
3366

3367 3368
	register_address_increment(ctxt, reg, df * op->bytes);
	op->addr.mem.ea = register_address(ctxt, reg);
3369 3370
}

3371 3372 3373 3374 3375 3376
static int em_das(struct x86_emulate_ctxt *ctxt)
{
	u8 al, old_al;
	bool af, cf, old_cf;

	cf = ctxt->eflags & X86_EFLAGS_CF;
3377
	al = ctxt->dst.val;
3378 3379 3380 3381 3382 3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394

	old_al = al;
	old_cf = cf;
	cf = false;
	af = ctxt->eflags & X86_EFLAGS_AF;
	if ((al & 0x0f) > 9 || af) {
		al -= 6;
		cf = old_cf | (al >= 250);
		af = true;
	} else {
		af = false;
	}
	if (old_al > 0x99 || old_cf) {
		al -= 0x60;
		cf = true;
	}

3395
	ctxt->dst.val = al;
3396
	/* Set PF, ZF, SF */
3397 3398 3399
	ctxt->src.type = OP_IMM;
	ctxt->src.val = 0;
	ctxt->src.bytes = 1;
3400
	fastop(ctxt, em_or);
3401 3402 3403 3404 3405 3406 3407 3408
	ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
	if (cf)
		ctxt->eflags |= X86_EFLAGS_CF;
	if (af)
		ctxt->eflags |= X86_EFLAGS_AF;
	return X86EMUL_CONTINUE;
}

P
Paolo Bonzini 已提交
3409 3410 3411 3412 3413 3414 3415 3416 3417 3418 3419 3420 3421 3422 3423 3424 3425 3426 3427 3428 3429 3430
static int em_aam(struct x86_emulate_ctxt *ctxt)
{
	u8 al, ah;

	if (ctxt->src.val == 0)
		return emulate_de(ctxt);

	al = ctxt->dst.val & 0xff;
	ah = al / ctxt->src.val;
	al %= ctxt->src.val;

	ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al | (ah << 8);

	/* Set PF, ZF, SF */
	ctxt->src.type = OP_IMM;
	ctxt->src.val = 0;
	ctxt->src.bytes = 1;
	fastop(ctxt, em_or);

	return X86EMUL_CONTINUE;
}

3431 3432 3433 3434 3435 3436 3437 3438 3439
static int em_aad(struct x86_emulate_ctxt *ctxt)
{
	u8 al = ctxt->dst.val & 0xff;
	u8 ah = (ctxt->dst.val >> 8) & 0xff;

	al = (al + (ah * ctxt->src.val)) & 0xff;

	ctxt->dst.val = (ctxt->dst.val & 0xffff0000) | al;

3440 3441 3442 3443 3444
	/* Set PF, ZF, SF */
	ctxt->src.type = OP_IMM;
	ctxt->src.val = 0;
	ctxt->src.bytes = 1;
	fastop(ctxt, em_or);
3445 3446 3447 3448

	return X86EMUL_CONTINUE;
}

3449 3450
static int em_call(struct x86_emulate_ctxt *ctxt)
{
3451
	int rc;
3452 3453 3454
	long rel = ctxt->src.val;

	ctxt->src.val = (unsigned long)ctxt->_eip;
3455 3456 3457
	rc = jmp_rel(ctxt, rel);
	if (rc != X86EMUL_CONTINUE)
		return rc;
3458 3459 3460
	return em_push(ctxt);
}

3461 3462 3463 3464 3465
static int em_call_far(struct x86_emulate_ctxt *ctxt)
{
	u16 sel, old_cs;
	ulong old_eip;
	int rc;
3466 3467 3468
	struct desc_struct old_desc, new_desc;
	const struct x86_emulate_ops *ops = ctxt->ops;
	int cpl = ctxt->ops->cpl(ctxt);
3469
	enum x86emul_mode prev_mode = ctxt->mode;
3470

3471
	old_eip = ctxt->_eip;
3472
	ops->get_segment(ctxt, &old_cs, &old_desc, NULL, VCPU_SREG_CS);
3473

3474
	memcpy(&sel, ctxt->src.valptr + ctxt->op_bytes, 2);
3475 3476
	rc = __load_segment_descriptor(ctxt, sel, VCPU_SREG_CS, cpl,
				       X86_TRANSFER_CALL_JMP, &new_desc);
3477
	if (rc != X86EMUL_CONTINUE)
3478
		return rc;
3479

3480
	rc = assign_eip_far(ctxt, ctxt->src.val, &new_desc);
3481 3482
	if (rc != X86EMUL_CONTINUE)
		goto fail;
3483

3484
	ctxt->src.val = old_cs;
3485
	rc = em_push(ctxt);
3486
	if (rc != X86EMUL_CONTINUE)
3487
		goto fail;
3488

3489
	ctxt->src.val = old_eip;
3490 3491 3492
	rc = em_push(ctxt);
	/* If we failed, we tainted the memory, but the very least we should
	   restore cs */
3493 3494
	if (rc != X86EMUL_CONTINUE) {
		pr_warn_once("faulting far call emulation tainted memory\n");
3495
		goto fail;
3496
	}
3497 3498 3499
	return rc;
fail:
	ops->set_segment(ctxt, old_cs, &old_desc, 0, VCPU_SREG_CS);
3500
	ctxt->mode = prev_mode;
3501 3502
	return rc;

3503 3504
}

3505 3506 3507
static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
{
	int rc;
3508
	unsigned long eip;
3509

3510 3511 3512 3513
	rc = emulate_pop(ctxt, &eip, ctxt->op_bytes);
	if (rc != X86EMUL_CONTINUE)
		return rc;
	rc = assign_eip_near(ctxt, eip);
3514 3515
	if (rc != X86EMUL_CONTINUE)
		return rc;
3516
	rsp_increment(ctxt, ctxt->src.val);
3517 3518 3519
	return X86EMUL_CONTINUE;
}

3520 3521 3522
static int em_xchg(struct x86_emulate_ctxt *ctxt)
{
	/* Write back the register source. */
3523 3524
	ctxt->src.val = ctxt->dst.val;
	write_register_operand(&ctxt->src);
3525 3526

	/* Write back the memory destination with implicit LOCK prefix. */
3527 3528
	ctxt->dst.val = ctxt->src.orig_val;
	ctxt->lock_prefix = 1;
3529 3530 3531
	return X86EMUL_CONTINUE;
}

3532 3533
static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
{
3534
	ctxt->dst.val = ctxt->src2.val;
3535
	return fastop(ctxt, em_imul);
3536 3537
}

3538 3539
static int em_cwd(struct x86_emulate_ctxt *ctxt)
{
3540 3541
	ctxt->dst.type = OP_REG;
	ctxt->dst.bytes = ctxt->src.bytes;
3542
	ctxt->dst.addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
3543
	ctxt->dst.val = ~((ctxt->src.val >> (ctxt->src.bytes * 8 - 1)) - 1);
3544 3545 3546 3547

	return X86EMUL_CONTINUE;
}

P
Paolo Bonzini 已提交
3548 3549 3550 3551 3552 3553 3554 3555 3556 3557
static int em_rdpid(struct x86_emulate_ctxt *ctxt)
{
	u64 tsc_aux = 0;

	if (ctxt->ops->get_msr(ctxt, MSR_TSC_AUX, &tsc_aux))
		return emulate_gp(ctxt, 0);
	ctxt->dst.val = tsc_aux;
	return X86EMUL_CONTINUE;
}

3558 3559 3560 3561
static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
{
	u64 tsc = 0;

3562
	ctxt->ops->get_msr(ctxt, MSR_IA32_TSC, &tsc);
3563 3564
	*reg_write(ctxt, VCPU_REGS_RAX) = (u32)tsc;
	*reg_write(ctxt, VCPU_REGS_RDX) = tsc >> 32;
3565 3566 3567
	return X86EMUL_CONTINUE;
}

3568 3569 3570 3571
static int em_rdpmc(struct x86_emulate_ctxt *ctxt)
{
	u64 pmc;

3572
	if (ctxt->ops->read_pmc(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &pmc))
3573
		return emulate_gp(ctxt, 0);
3574 3575
	*reg_write(ctxt, VCPU_REGS_RAX) = (u32)pmc;
	*reg_write(ctxt, VCPU_REGS_RDX) = pmc >> 32;
3576 3577 3578
	return X86EMUL_CONTINUE;
}

3579 3580
static int em_mov(struct x86_emulate_ctxt *ctxt)
{
3581
	memcpy(ctxt->dst.valptr, ctxt->src.valptr, sizeof(ctxt->src.valptr));
3582 3583 3584
	return X86EMUL_CONTINUE;
}

B
Borislav Petkov 已提交
3585 3586 3587 3588 3589 3590 3591 3592 3593 3594
#define FFL(x) bit(X86_FEATURE_##x)

static int em_movbe(struct x86_emulate_ctxt *ctxt)
{
	u32 ebx, ecx, edx, eax = 1;
	u16 tmp;

	/*
	 * Check MOVBE is set in the guest-visible CPUID leaf.
	 */
3595
	ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
B
Borislav Petkov 已提交
3596 3597 3598 3599 3600 3601 3602 3603 3604 3605 3606 3607 3608 3609 3610 3611 3612 3613 3614 3615 3616 3617 3618 3619
	if (!(ecx & FFL(MOVBE)))
		return emulate_ud(ctxt);

	switch (ctxt->op_bytes) {
	case 2:
		/*
		 * From MOVBE definition: "...When the operand size is 16 bits,
		 * the upper word of the destination register remains unchanged
		 * ..."
		 *
		 * Both casting ->valptr and ->val to u16 breaks strict aliasing
		 * rules so we have to do the operation almost per hand.
		 */
		tmp = (u16)ctxt->src.val;
		ctxt->dst.val &= ~0xffffUL;
		ctxt->dst.val |= (unsigned long)swab16(tmp);
		break;
	case 4:
		ctxt->dst.val = swab32((u32)ctxt->src.val);
		break;
	case 8:
		ctxt->dst.val = swab64(ctxt->src.val);
		break;
	default:
3620
		BUG();
B
Borislav Petkov 已提交
3621 3622 3623 3624
	}
	return X86EMUL_CONTINUE;
}

3625 3626 3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643 3644 3645 3646 3647 3648 3649 3650 3651 3652
static int em_cr_write(struct x86_emulate_ctxt *ctxt)
{
	if (ctxt->ops->set_cr(ctxt, ctxt->modrm_reg, ctxt->src.val))
		return emulate_gp(ctxt, 0);

	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

static int em_dr_write(struct x86_emulate_ctxt *ctxt)
{
	unsigned long val;

	if (ctxt->mode == X86EMUL_MODE_PROT64)
		val = ctxt->src.val & ~0ULL;
	else
		val = ctxt->src.val & ~0U;

	/* #UD condition is already handled. */
	if (ctxt->ops->set_dr(ctxt, ctxt->modrm_reg, val) < 0)
		return emulate_gp(ctxt, 0);

	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

3653 3654 3655 3656
static int em_wrmsr(struct x86_emulate_ctxt *ctxt)
{
	u64 msr_data;

3657 3658 3659
	msr_data = (u32)reg_read(ctxt, VCPU_REGS_RAX)
		| ((u64)reg_read(ctxt, VCPU_REGS_RDX) << 32);
	if (ctxt->ops->set_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), msr_data))
3660 3661 3662 3663 3664 3665 3666 3667 3668
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

static int em_rdmsr(struct x86_emulate_ctxt *ctxt)
{
	u64 msr_data;

3669
	if (ctxt->ops->get_msr(ctxt, reg_read(ctxt, VCPU_REGS_RCX), &msr_data))
3670 3671
		return emulate_gp(ctxt, 0);

3672 3673
	*reg_write(ctxt, VCPU_REGS_RAX) = (u32)msr_data;
	*reg_write(ctxt, VCPU_REGS_RDX) = msr_data >> 32;
3674 3675 3676
	return X86EMUL_CONTINUE;
}

P
Paolo Bonzini 已提交
3677
static int em_store_sreg(struct x86_emulate_ctxt *ctxt, int segment)
3678
{
P
Paolo Bonzini 已提交
3679 3680 3681 3682
	if (segment > VCPU_SREG_GS &&
	    (ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) &&
	    ctxt->ops->cpl(ctxt) > 0)
		return emulate_gp(ctxt, 0);
3683

P
Paolo Bonzini 已提交
3684
	ctxt->dst.val = get_segment_selector(ctxt, segment);
3685 3686
	if (ctxt->dst.bytes == 4 && ctxt->dst.type == OP_MEM)
		ctxt->dst.bytes = 2;
3687 3688 3689
	return X86EMUL_CONTINUE;
}

P
Paolo Bonzini 已提交
3690 3691 3692 3693 3694 3695 3696 3697
static int em_mov_rm_sreg(struct x86_emulate_ctxt *ctxt)
{
	if (ctxt->modrm_reg > VCPU_SREG_GS)
		return emulate_ud(ctxt);

	return em_store_sreg(ctxt, ctxt->modrm_reg);
}

3698 3699
static int em_mov_sreg_rm(struct x86_emulate_ctxt *ctxt)
{
3700
	u16 sel = ctxt->src.val;
3701

3702
	if (ctxt->modrm_reg == VCPU_SREG_CS || ctxt->modrm_reg > VCPU_SREG_GS)
3703 3704
		return emulate_ud(ctxt);

3705
	if (ctxt->modrm_reg == VCPU_SREG_SS)
3706 3707 3708
		ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;

	/* Disable writeback. */
3709 3710
	ctxt->dst.type = OP_NONE;
	return load_segment_descriptor(ctxt, sel, ctxt->modrm_reg);
3711 3712
}

P
Paolo Bonzini 已提交
3713 3714 3715 3716 3717
static int em_sldt(struct x86_emulate_ctxt *ctxt)
{
	return em_store_sreg(ctxt, VCPU_SREG_LDTR);
}

A
Avi Kivity 已提交
3718 3719 3720 3721 3722 3723 3724 3725 3726
static int em_lldt(struct x86_emulate_ctxt *ctxt)
{
	u16 sel = ctxt->src.val;

	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return load_segment_descriptor(ctxt, sel, VCPU_SREG_LDTR);
}

P
Paolo Bonzini 已提交
3727 3728 3729 3730 3731
static int em_str(struct x86_emulate_ctxt *ctxt)
{
	return em_store_sreg(ctxt, VCPU_SREG_TR);
}

A
Avi Kivity 已提交
3732 3733 3734 3735 3736 3737 3738 3739 3740
static int em_ltr(struct x86_emulate_ctxt *ctxt)
{
	u16 sel = ctxt->src.val;

	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return load_segment_descriptor(ctxt, sel, VCPU_SREG_TR);
}

3741 3742
static int em_invlpg(struct x86_emulate_ctxt *ctxt)
{
3743 3744 3745
	int rc;
	ulong linear;

3746
	rc = linearize(ctxt, ctxt->src.addr.mem, 1, false, &linear);
3747
	if (rc == X86EMUL_CONTINUE)
3748
		ctxt->ops->invlpg(ctxt, linear);
3749
	/* Disable writeback. */
3750
	ctxt->dst.type = OP_NONE;
3751 3752 3753
	return X86EMUL_CONTINUE;
}

3754 3755 3756 3757 3758 3759 3760 3761 3762 3763
static int em_clts(struct x86_emulate_ctxt *ctxt)
{
	ulong cr0;

	cr0 = ctxt->ops->get_cr(ctxt, 0);
	cr0 &= ~X86_CR0_TS;
	ctxt->ops->set_cr(ctxt, 0, cr0);
	return X86EMUL_CONTINUE;
}

3764
static int em_hypercall(struct x86_emulate_ctxt *ctxt)
3765
{
3766
	int rc = ctxt->ops->fix_hypercall(ctxt);
3767 3768 3769 3770 3771

	if (rc != X86EMUL_CONTINUE)
		return rc;

	/* Let the processor re-execute the fixed hypercall */
3772
	ctxt->_eip = ctxt->eip;
3773
	/* Disable writeback. */
3774
	ctxt->dst.type = OP_NONE;
3775 3776 3777
	return X86EMUL_CONTINUE;
}

3778 3779 3780 3781 3782 3783
static int emulate_store_desc_ptr(struct x86_emulate_ctxt *ctxt,
				  void (*get)(struct x86_emulate_ctxt *ctxt,
					      struct desc_ptr *ptr))
{
	struct desc_ptr desc_ptr;

P
Paolo Bonzini 已提交
3784 3785 3786 3787
	if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) &&
	    ctxt->ops->cpl(ctxt) > 0)
		return emulate_gp(ctxt, 0);

3788 3789 3790 3791 3792 3793 3794 3795 3796
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		ctxt->op_bytes = 8;
	get(ctxt, &desc_ptr);
	if (ctxt->op_bytes == 2) {
		ctxt->op_bytes = 4;
		desc_ptr.address &= 0x00ffffff;
	}
	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
3797 3798
	return segmented_write_std(ctxt, ctxt->dst.addr.mem,
				   &desc_ptr, 2 + ctxt->op_bytes);
3799 3800 3801 3802 3803 3804 3805 3806 3807 3808 3809 3810
}

static int em_sgdt(struct x86_emulate_ctxt *ctxt)
{
	return emulate_store_desc_ptr(ctxt, ctxt->ops->get_gdt);
}

static int em_sidt(struct x86_emulate_ctxt *ctxt)
{
	return emulate_store_desc_ptr(ctxt, ctxt->ops->get_idt);
}

3811
static int em_lgdt_lidt(struct x86_emulate_ctxt *ctxt, bool lgdt)
3812 3813 3814 3815
{
	struct desc_ptr desc_ptr;
	int rc;

3816 3817
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		ctxt->op_bytes = 8;
3818
	rc = read_descriptor(ctxt, ctxt->src.addr.mem,
3819
			     &desc_ptr.size, &desc_ptr.address,
3820
			     ctxt->op_bytes);
3821 3822
	if (rc != X86EMUL_CONTINUE)
		return rc;
3823
	if (ctxt->mode == X86EMUL_MODE_PROT64 &&
3824
	    emul_is_noncanonical_address(desc_ptr.address, ctxt))
3825
		return emulate_gp(ctxt, 0);
3826 3827 3828 3829
	if (lgdt)
		ctxt->ops->set_gdt(ctxt, &desc_ptr);
	else
		ctxt->ops->set_idt(ctxt, &desc_ptr);
3830
	/* Disable writeback. */
3831
	ctxt->dst.type = OP_NONE;
3832 3833 3834
	return X86EMUL_CONTINUE;
}

3835 3836 3837 3838 3839
static int em_lgdt(struct x86_emulate_ctxt *ctxt)
{
	return em_lgdt_lidt(ctxt, true);
}

3840 3841
static int em_lidt(struct x86_emulate_ctxt *ctxt)
{
3842
	return em_lgdt_lidt(ctxt, false);
3843 3844 3845 3846
}

static int em_smsw(struct x86_emulate_ctxt *ctxt)
{
P
Paolo Bonzini 已提交
3847 3848 3849 3850
	if ((ctxt->ops->get_cr(ctxt, 4) & X86_CR4_UMIP) &&
	    ctxt->ops->cpl(ctxt) > 0)
		return emulate_gp(ctxt, 0);

3851 3852
	if (ctxt->dst.type == OP_MEM)
		ctxt->dst.bytes = 2;
3853
	ctxt->dst.val = ctxt->ops->get_cr(ctxt, 0);
3854 3855 3856 3857 3858 3859
	return X86EMUL_CONTINUE;
}

static int em_lmsw(struct x86_emulate_ctxt *ctxt)
{
	ctxt->ops->set_cr(ctxt, 0, (ctxt->ops->get_cr(ctxt, 0) & ~0x0eul)
3860 3861
			  | (ctxt->src.val & 0x0f));
	ctxt->dst.type = OP_NONE;
3862 3863 3864
	return X86EMUL_CONTINUE;
}

3865 3866
static int em_loop(struct x86_emulate_ctxt *ctxt)
{
3867 3868
	int rc = X86EMUL_CONTINUE;

3869
	register_address_increment(ctxt, VCPU_REGS_RCX, -1);
3870
	if ((address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) != 0) &&
3871
	    (ctxt->b == 0xe2 || test_cc(ctxt->b ^ 0x5, ctxt->eflags)))
3872
		rc = jmp_rel(ctxt, ctxt->src.val);
3873

3874
	return rc;
3875 3876 3877 3878
}

static int em_jcxz(struct x86_emulate_ctxt *ctxt)
{
3879 3880
	int rc = X86EMUL_CONTINUE;

3881
	if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0)
3882
		rc = jmp_rel(ctxt, ctxt->src.val);
3883

3884
	return rc;
3885 3886
}

3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903 3904
static int em_in(struct x86_emulate_ctxt *ctxt)
{
	if (!pio_in_emulated(ctxt, ctxt->dst.bytes, ctxt->src.val,
			     &ctxt->dst.val))
		return X86EMUL_IO_NEEDED;

	return X86EMUL_CONTINUE;
}

static int em_out(struct x86_emulate_ctxt *ctxt)
{
	ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
				    &ctxt->src.val, 1);
	/* Disable writeback. */
	ctxt->dst.type = OP_NONE;
	return X86EMUL_CONTINUE;
}

3905 3906 3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922 3923
static int em_cli(struct x86_emulate_ctxt *ctxt)
{
	if (emulator_bad_iopl(ctxt))
		return emulate_gp(ctxt, 0);

	ctxt->eflags &= ~X86_EFLAGS_IF;
	return X86EMUL_CONTINUE;
}

static int em_sti(struct x86_emulate_ctxt *ctxt)
{
	if (emulator_bad_iopl(ctxt))
		return emulate_gp(ctxt, 0);

	ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
	ctxt->eflags |= X86_EFLAGS_IF;
	return X86EMUL_CONTINUE;
}

A
Avi Kivity 已提交
3924 3925 3926
static int em_cpuid(struct x86_emulate_ctxt *ctxt)
{
	u32 eax, ebx, ecx, edx;
K
Kyle Huey 已提交
3927 3928 3929 3930 3931 3932 3933
	u64 msr = 0;

	ctxt->ops->get_msr(ctxt, MSR_MISC_FEATURES_ENABLES, &msr);
	if (msr & MSR_MISC_FEATURES_ENABLES_CPUID_FAULT &&
	    ctxt->ops->cpl(ctxt)) {
		return emulate_gp(ctxt, 0);
	}
A
Avi Kivity 已提交
3934

3935 3936
	eax = reg_read(ctxt, VCPU_REGS_RAX);
	ecx = reg_read(ctxt, VCPU_REGS_RCX);
3937
	ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, true);
3938 3939 3940 3941
	*reg_write(ctxt, VCPU_REGS_RAX) = eax;
	*reg_write(ctxt, VCPU_REGS_RBX) = ebx;
	*reg_write(ctxt, VCPU_REGS_RCX) = ecx;
	*reg_write(ctxt, VCPU_REGS_RDX) = edx;
A
Avi Kivity 已提交
3942 3943 3944
	return X86EMUL_CONTINUE;
}

P
Paolo Bonzini 已提交
3945 3946 3947 3948
static int em_sahf(struct x86_emulate_ctxt *ctxt)
{
	u32 flags;

3949 3950
	flags = X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
		X86_EFLAGS_SF;
P
Paolo Bonzini 已提交
3951 3952 3953 3954 3955 3956 3957
	flags &= *reg_rmw(ctxt, VCPU_REGS_RAX) >> 8;

	ctxt->eflags &= ~0xffUL;
	ctxt->eflags |= flags | X86_EFLAGS_FIXED;
	return X86EMUL_CONTINUE;
}

A
Avi Kivity 已提交
3958 3959
static int em_lahf(struct x86_emulate_ctxt *ctxt)
{
3960 3961
	*reg_rmw(ctxt, VCPU_REGS_RAX) &= ~0xff00UL;
	*reg_rmw(ctxt, VCPU_REGS_RAX) |= (ctxt->eflags & 0xff) << 8;
A
Avi Kivity 已提交
3962 3963 3964
	return X86EMUL_CONTINUE;
}

A
Avi Kivity 已提交
3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979
static int em_bswap(struct x86_emulate_ctxt *ctxt)
{
	switch (ctxt->op_bytes) {
#ifdef CONFIG_X86_64
	case 8:
		asm("bswap %0" : "+r"(ctxt->dst.val));
		break;
#endif
	default:
		asm("bswap %0" : "+r"(*(u32 *)&ctxt->dst.val));
		break;
	}
	return X86EMUL_CONTINUE;
}

3980 3981 3982 3983 3984 3985
static int em_clflush(struct x86_emulate_ctxt *ctxt)
{
	/* emulating clflush regardless of cpuid */
	return X86EMUL_CONTINUE;
}

3986 3987 3988 3989 3990 3991
static int em_movsxd(struct x86_emulate_ctxt *ctxt)
{
	ctxt->dst.val = (s32) ctxt->src.val;
	return X86EMUL_CONTINUE;
}

3992 3993 3994 3995
static int check_fxsr(struct x86_emulate_ctxt *ctxt)
{
	u32 eax = 1, ebx, ecx = 0, edx;

3996
	ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx, &edx, false);
3997 3998 3999 4000 4001 4002 4003 4004 4005 4006 4007 4008 4009 4010 4011 4012
	if (!(edx & FFL(FXSR)))
		return emulate_ud(ctxt);

	if (ctxt->ops->get_cr(ctxt, 0) & (X86_CR0_TS | X86_CR0_EM))
		return emulate_nm(ctxt);

	/*
	 * Don't emulate a case that should never be hit, instead of working
	 * around a lack of fxsave64/fxrstor64 on old compilers.
	 */
	if (ctxt->mode >= X86EMUL_MODE_PROT64)
		return X86EMUL_UNHANDLEABLE;

	return X86EMUL_CONTINUE;
}

4013 4014 4015 4016 4017 4018 4019 4020 4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031
/*
 * Hardware doesn't save and restore XMM 0-7 without CR4.OSFXSR, but does save
 * and restore MXCSR.
 */
static size_t __fxstate_size(int nregs)
{
	return offsetof(struct fxregs_state, xmm_space[0]) + nregs * 16;
}

static inline size_t fxstate_size(struct x86_emulate_ctxt *ctxt)
{
	bool cr4_osfxsr;
	if (ctxt->mode == X86EMUL_MODE_PROT64)
		return __fxstate_size(16);

	cr4_osfxsr = ctxt->ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR;
	return __fxstate_size(cr4_osfxsr ? 8 : 0);
}

4032 4033 4034 4035 4036 4037 4038 4039 4040 4041 4042 4043 4044 4045 4046 4047 4048 4049 4050 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4061 4062 4063
/*
 * FXSAVE and FXRSTOR have 4 different formats depending on execution mode,
 *  1) 16 bit mode
 *  2) 32 bit mode
 *     - like (1), but FIP and FDP (foo) are only 16 bit.  At least Intel CPUs
 *       preserve whole 32 bit values, though, so (1) and (2) are the same wrt.
 *       save and restore
 *  3) 64-bit mode with REX.W prefix
 *     - like (2), but XMM 8-15 are being saved and restored
 *  4) 64-bit mode without REX.W prefix
 *     - like (3), but FIP and FDP are 64 bit
 *
 * Emulation uses (3) for (1) and (2) and preserves XMM 8-15 to reach the
 * desired result.  (4) is not emulated.
 *
 * Note: Guest and host CPUID.(EAX=07H,ECX=0H):EBX[bit 13] (deprecate FPU CS
 * and FPU DS) should match.
 */
static int em_fxsave(struct x86_emulate_ctxt *ctxt)
{
	struct fxregs_state fx_state;
	int rc;

	rc = check_fxsr(ctxt);
	if (rc != X86EMUL_CONTINUE)
		return rc;

	rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_state));

	if (rc != X86EMUL_CONTINUE)
		return rc;

4064 4065
	return segmented_write_std(ctxt, ctxt->memop.addr.mem, &fx_state,
		                   fxstate_size(ctxt));
4066 4067
}

4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085 4086 4087
/*
 * FXRSTOR might restore XMM registers not provided by the guest. Fill
 * in the host registers (via FXSAVE) instead, so they won't be modified.
 * (preemption has to stay disabled until FXRSTOR).
 *
 * Use noinline to keep the stack for other functions called by callers small.
 */
static noinline int fxregs_fixup(struct fxregs_state *fx_state,
				 const size_t used_size)
{
	struct fxregs_state fx_tmp;
	int rc;

	rc = asm_safe("fxsave %[fx]", , [fx] "+m"(fx_tmp));
	memcpy((void *)fx_state + used_size, (void *)&fx_tmp + used_size,
	       __fxstate_size(16) - used_size);

	return rc;
}

4088 4089 4090 4091
static int em_fxrstor(struct x86_emulate_ctxt *ctxt)
{
	struct fxregs_state fx_state;
	int rc;
4092
	size_t size;
4093 4094 4095 4096 4097

	rc = check_fxsr(ctxt);
	if (rc != X86EMUL_CONTINUE)
		return rc;

4098 4099 4100 4101 4102
	size = fxstate_size(ctxt);
	rc = segmented_read_std(ctxt, ctxt->memop.addr.mem, &fx_state, size);
	if (rc != X86EMUL_CONTINUE)
		return rc;

4103
	if (size < __fxstate_size(16)) {
4104
		rc = fxregs_fixup(&fx_state, size);
4105 4106 4107
		if (rc != X86EMUL_CONTINUE)
			goto out;
	}
4108

4109 4110 4111 4112
	if (fx_state.mxcsr >> 16) {
		rc = emulate_gp(ctxt, 0);
		goto out;
	}
4113 4114 4115 4116

	if (rc == X86EMUL_CONTINUE)
		rc = asm_safe("fxrstor %[fx]", : [fx] "m"(fx_state));

4117
out:
4118 4119 4120
	return rc;
}

4121 4122 4123 4124 4125 4126 4127 4128 4129 4130 4131 4132 4133 4134
static bool valid_cr(int nr)
{
	switch (nr) {
	case 0:
	case 2 ... 4:
	case 8:
		return true;
	default:
		return false;
	}
}

static int check_cr_read(struct x86_emulate_ctxt *ctxt)
{
4135
	if (!valid_cr(ctxt->modrm_reg))
4136 4137 4138 4139 4140 4141 4142
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_cr_write(struct x86_emulate_ctxt *ctxt)
{
4143 4144
	u64 new_val = ctxt->src.val64;
	int cr = ctxt->modrm_reg;
4145
	u64 efer = 0;
4146 4147 4148 4149 4150 4151 4152 4153 4154 4155 4156 4157 4158 4159 4160 4161 4162

	static u64 cr_reserved_bits[] = {
		0xffffffff00000000ULL,
		0, 0, 0, /* CR3 checked later */
		CR4_RESERVED_BITS,
		0, 0, 0,
		CR8_RESERVED_BITS,
	};

	if (!valid_cr(cr))
		return emulate_ud(ctxt);

	if (new_val & cr_reserved_bits[cr])
		return emulate_gp(ctxt, 0);

	switch (cr) {
	case 0: {
4163
		u64 cr4;
4164 4165 4166 4167
		if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
		    ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
			return emulate_gp(ctxt, 0);

4168 4169
		cr4 = ctxt->ops->get_cr(ctxt, 4);
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
4170 4171 4172 4173 4174 4175 4176 4177 4178 4179

		if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
		    !(cr4 & X86_CR4_PAE))
			return emulate_gp(ctxt, 0);

		break;
		}
	case 3: {
		u64 rsvd = 0;

4180
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
4181 4182
		if (efer & EFER_LMA) {
			u64 maxphyaddr;
4183
			u32 eax, ebx, ecx, edx;
4184

4185 4186 4187 4188
			eax = 0x80000008;
			ecx = 0;
			if (ctxt->ops->get_cpuid(ctxt, &eax, &ebx, &ecx,
						 &edx, false))
4189 4190 4191 4192 4193
				maxphyaddr = eax & 0xff;
			else
				maxphyaddr = 36;
			rsvd = rsvd_bits(maxphyaddr, 62);
		}
4194 4195 4196 4197 4198 4199 4200

		if (new_val & rsvd)
			return emulate_gp(ctxt, 0);

		break;
		}
	case 4: {
4201
		ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
4202 4203 4204 4205 4206 4207 4208 4209 4210 4211 4212

		if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
			return emulate_gp(ctxt, 0);

		break;
		}
	}

	return X86EMUL_CONTINUE;
}

4213 4214 4215 4216
static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
{
	unsigned long dr7;

4217
	ctxt->ops->get_dr(ctxt, 7, &dr7);
4218 4219 4220 4221 4222 4223 4224

	/* Check if DR7.Global_Enable is set */
	return dr7 & (1 << 13);
}

static int check_dr_read(struct x86_emulate_ctxt *ctxt)
{
4225
	int dr = ctxt->modrm_reg;
4226 4227 4228 4229 4230
	u64 cr4;

	if (dr > 7)
		return emulate_ud(ctxt);

4231
	cr4 = ctxt->ops->get_cr(ctxt, 4);
4232 4233 4234
	if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
		return emulate_ud(ctxt);

4235 4236 4237 4238 4239 4240 4241
	if (check_dr7_gd(ctxt)) {
		ulong dr6;

		ctxt->ops->get_dr(ctxt, 6, &dr6);
		dr6 &= ~15;
		dr6 |= DR6_BD | DR6_RTM;
		ctxt->ops->set_dr(ctxt, 6, dr6);
4242
		return emulate_db(ctxt);
4243
	}
4244 4245 4246 4247 4248 4249

	return X86EMUL_CONTINUE;
}

static int check_dr_write(struct x86_emulate_ctxt *ctxt)
{
4250 4251
	u64 new_val = ctxt->src.val64;
	int dr = ctxt->modrm_reg;
4252 4253 4254 4255 4256 4257 4258

	if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
		return emulate_gp(ctxt, 0);

	return check_dr_read(ctxt);
}

4259 4260
static int check_svme(struct x86_emulate_ctxt *ctxt)
{
4261
	u64 efer = 0;
4262

4263
	ctxt->ops->get_msr(ctxt, MSR_EFER, &efer);
4264 4265 4266 4267 4268 4269 4270 4271 4272

	if (!(efer & EFER_SVME))
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
{
4273
	u64 rax = reg_read(ctxt, VCPU_REGS_RAX);
4274 4275

	/* Valid physical address? */
4276
	if (rax & 0xffff000000000000ULL)
4277 4278 4279 4280 4281
		return emulate_gp(ctxt, 0);

	return check_svme(ctxt);
}

4282 4283
static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
{
4284
	u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
4285

4286
	if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt))
4287 4288 4289 4290 4291
		return emulate_ud(ctxt);

	return X86EMUL_CONTINUE;
}

4292 4293
static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
{
4294
	u64 cr4 = ctxt->ops->get_cr(ctxt, 4);
4295
	u64 rcx = reg_read(ctxt, VCPU_REGS_RCX);
4296

4297 4298 4299 4300 4301 4302 4303
	/*
	 * VMware allows access to these Pseduo-PMCs even when read via RDPMC
	 * in Ring3 when CR4.PCE=0.
	 */
	if (enable_vmware_backdoor && is_vmware_backdoor_pmc(rcx))
		return X86EMUL_CONTINUE;

4304
	if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt)) ||
4305
	    ctxt->ops->check_pmc(ctxt, rcx))
4306 4307 4308 4309 4310
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

4311 4312
static int check_perm_in(struct x86_emulate_ctxt *ctxt)
{
4313 4314
	ctxt->dst.bytes = min(ctxt->dst.bytes, 4u);
	if (!emulator_io_permited(ctxt, ctxt->src.val, ctxt->dst.bytes))
4315 4316 4317 4318 4319 4320 4321
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

static int check_perm_out(struct x86_emulate_ctxt *ctxt)
{
4322 4323
	ctxt->src.bytes = min(ctxt->src.bytes, 4u);
	if (!emulator_io_permited(ctxt, ctxt->dst.val, ctxt->src.bytes))
4324 4325 4326 4327 4328
		return emulate_gp(ctxt, 0);

	return X86EMUL_CONTINUE;
}

4329
#define D(_y) { .flags = (_y) }
4330 4331 4332
#define DI(_y, _i) { .flags = (_y)|Intercept, .intercept = x86_intercept_##_i }
#define DIP(_y, _i, _p) { .flags = (_y)|Intercept|CheckPerm, \
		      .intercept = x86_intercept_##_i, .check_perm = (_p) }
4333
#define N    D(NotImpl)
4334
#define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
4335 4336
#define G(_f, _g) { .flags = ((_f) | Group | ModRM), .u.group = (_g) }
#define GD(_f, _g) { .flags = ((_f) | GroupDual | ModRM), .u.gdual = (_g) }
4337
#define ID(_f, _i) { .flags = ((_f) | InstrDual | ModRM), .u.idual = (_i) }
4338
#define MD(_f, _m) { .flags = ((_f) | ModeDual), .u.mdual = (_m) }
4339
#define E(_f, _e) { .flags = ((_f) | Escape | ModRM), .u.esc = (_e) }
4340
#define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
4341
#define F(_f, _e) { .flags = (_f) | Fastop, .u.fastop = (_e) }
4342
#define II(_f, _e, _i) \
4343
	{ .flags = (_f)|Intercept, .u.execute = (_e), .intercept = x86_intercept_##_i }
4344
#define IIP(_f, _e, _i, _p) \
4345 4346
	{ .flags = (_f)|Intercept|CheckPerm, .u.execute = (_e), \
	  .intercept = x86_intercept_##_i, .check_perm = (_p) }
4347
#define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
4348

4349
#define D2bv(_f)      D((_f) | ByteOp), D(_f)
4350
#define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
4351
#define I2bv(_f, _e)  I((_f) | ByteOp, _e), I(_f, _e)
4352
#define F2bv(_f, _e)  F((_f) | ByteOp, _e), F(_f, _e)
4353 4354
#define I2bvIP(_f, _e, _i, _p) \
	IIP((_f) | ByteOp, _e, _i, _p), IIP(_f, _e, _i, _p)
4355

4356 4357 4358
#define F6ALU(_f, _e) F2bv((_f) | DstMem | SrcReg | ModRM, _e),		\
		F2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock, _e),	\
		F2bv(((_f) & ~Lock) | DstAcc | SrcImm, _e)
4359

4360 4361
static const struct opcode group7_rm0[] = {
	N,
4362
	I(SrcNone | Priv | EmulateOnUD,	em_hypercall),
4363 4364 4365
	N, N, N, N, N, N,
};

4366
static const struct opcode group7_rm1[] = {
4367 4368
	DI(SrcNone | Priv, monitor),
	DI(SrcNone | Priv, mwait),
4369 4370 4371
	N, N, N, N, N, N,
};

4372
static const struct opcode group7_rm3[] = {
4373
	DIP(SrcNone | Prot | Priv,		vmrun,		check_svme_pa),
4374
	II(SrcNone  | Prot | EmulateOnUD,	em_hypercall,	vmmcall),
4375 4376 4377 4378 4379 4380
	DIP(SrcNone | Prot | Priv,		vmload,		check_svme_pa),
	DIP(SrcNone | Prot | Priv,		vmsave,		check_svme_pa),
	DIP(SrcNone | Prot | Priv,		stgi,		check_svme),
	DIP(SrcNone | Prot | Priv,		clgi,		check_svme),
	DIP(SrcNone | Prot | Priv,		skinit,		check_svme),
	DIP(SrcNone | Prot | Priv,		invlpga,	check_svme),
4381
};
4382

4383
static const struct opcode group7_rm7[] = {
4384
	N,
4385
	DIP(SrcNone, rdtscp, check_rdtsc),
4386 4387
	N, N, N, N, N, N,
};
4388

4389
static const struct opcode group1[] = {
4390 4391 4392 4393 4394 4395 4396 4397
	F(Lock, em_add),
	F(Lock | PageTable, em_or),
	F(Lock, em_adc),
	F(Lock, em_sbb),
	F(Lock | PageTable, em_and),
	F(Lock, em_sub),
	F(Lock, em_xor),
	F(NoWrite, em_cmp),
4398 4399
};

4400
static const struct opcode group1A[] = {
4401
	I(DstMem | SrcNone | Mov | Stack | IncSP | TwoMemOp, em_pop), N, N, N, N, N, N, N,
4402 4403
};

4404 4405 4406 4407 4408 4409 4410 4411 4412 4413 4414
static const struct opcode group2[] = {
	F(DstMem | ModRM, em_rol),
	F(DstMem | ModRM, em_ror),
	F(DstMem | ModRM, em_rcl),
	F(DstMem | ModRM, em_rcr),
	F(DstMem | ModRM, em_shl),
	F(DstMem | ModRM, em_shr),
	F(DstMem | ModRM, em_shl),
	F(DstMem | ModRM, em_sar),
};

4415
static const struct opcode group3[] = {
4416 4417
	F(DstMem | SrcImm | NoWrite, em_test),
	F(DstMem | SrcImm | NoWrite, em_test),
4418 4419
	F(DstMem | SrcNone | Lock, em_not),
	F(DstMem | SrcNone | Lock, em_neg),
4420 4421
	F(DstXacc | Src2Mem, em_mul_ex),
	F(DstXacc | Src2Mem, em_imul_ex),
4422 4423
	F(DstXacc | Src2Mem, em_div_ex),
	F(DstXacc | Src2Mem, em_idiv_ex),
4424 4425
};

4426
static const struct opcode group4[] = {
4427 4428
	F(ByteOp | DstMem | SrcNone | Lock, em_inc),
	F(ByteOp | DstMem | SrcNone | Lock, em_dec),
4429 4430 4431
	N, N, N, N, N, N,
};

4432
static const struct opcode group5[] = {
4433 4434
	F(DstMem | SrcNone | Lock,		em_inc),
	F(DstMem | SrcNone | Lock,		em_dec),
4435
	I(SrcMem | NearBranch,			em_call_near_abs),
4436
	I(SrcMemFAddr | ImplicitOps,		em_call_far),
4437
	I(SrcMem | NearBranch,			em_jmp_abs),
4438
	I(SrcMemFAddr | ImplicitOps,		em_jmp_far),
4439
	I(SrcMem | Stack | TwoMemOp,		em_push), D(Undefined),
4440 4441
};

4442
static const struct opcode group6[] = {
P
Paolo Bonzini 已提交
4443 4444
	II(Prot | DstMem,	   em_sldt, sldt),
	II(Prot | DstMem,	   em_str, str),
A
Avi Kivity 已提交
4445
	II(Prot | Priv | SrcMem16, em_lldt, lldt),
A
Avi Kivity 已提交
4446
	II(Prot | Priv | SrcMem16, em_ltr, ltr),
4447 4448 4449
	N, N, N, N,
};

4450
static const struct group_dual group7 = { {
4451 4452
	II(Mov | DstMem,			em_sgdt, sgdt),
	II(Mov | DstMem,			em_sidt, sidt),
4453 4454 4455 4456 4457
	II(SrcMem | Priv,			em_lgdt, lgdt),
	II(SrcMem | Priv,			em_lidt, lidt),
	II(SrcNone | DstMem | Mov,		em_smsw, smsw), N,
	II(SrcMem16 | Mov | Priv,		em_lmsw, lmsw),
	II(SrcMem | ByteOp | Priv | NoAccess,	em_invlpg, invlpg),
4458
}, {
4459
	EXT(0, group7_rm0),
4460
	EXT(0, group7_rm1),
4461
	N, EXT(0, group7_rm3),
4462 4463 4464
	II(SrcNone | DstMem | Mov,		em_smsw, smsw), N,
	II(SrcMem16 | Mov | Priv,		em_lmsw, lmsw),
	EXT(0, group7_rm7),
4465 4466
} };

4467
static const struct opcode group8[] = {
4468
	N, N, N, N,
4469 4470 4471 4472
	F(DstMem | SrcImmByte | NoWrite,		em_bt),
	F(DstMem | SrcImmByte | Lock | PageTable,	em_bts),
	F(DstMem | SrcImmByte | Lock,			em_btr),
	F(DstMem | SrcImmByte | Lock | PageTable,	em_btc),
4473 4474
};

P
Paolo Bonzini 已提交
4475 4476 4477 4478 4479 4480 4481 4482 4483
/*
 * The "memory" destination is actually always a register, since we come
 * from the register case of group9.
 */
static const struct gprefix pfx_0f_c7_7 = {
	N, N, N, II(DstMem | ModRM | Op3264 | EmulateOnUD, em_rdpid, rdtscp),
};


4484
static const struct group_dual group9 = { {
4485
	N, I(DstMem64 | Lock | PageTable, em_cmpxchg8b), N, N, N, N, N, N,
4486
}, {
P
Paolo Bonzini 已提交
4487 4488
	N, N, N, N, N, N, N,
	GP(0, &pfx_0f_c7_7),
4489 4490
} };

4491
static const struct opcode group11[] = {
4492
	I(DstMem | SrcImm | Mov | PageTable, em_mov),
4493
	X7(D(Undefined)),
4494 4495
};

4496
static const struct gprefix pfx_0f_ae_7 = {
4497
	I(SrcMem | ByteOp, em_clflush), N, N, N,
4498 4499 4500
};

static const struct group_dual group15 = { {
4501 4502 4503
	I(ModRM | Aligned16, em_fxsave),
	I(ModRM | Aligned16, em_fxrstor),
	N, N, N, N, N, GP(0, &pfx_0f_ae_7),
4504 4505 4506 4507
}, {
	N, N, N, N, N, N, N, N,
} };

4508
static const struct gprefix pfx_0f_6f_0f_7f = {
4509
	I(Mmx, em_mov), I(Sse | Aligned, em_mov), N, I(Sse | Unaligned, em_mov),
4510 4511
};

4512 4513 4514 4515
static const struct instr_dual instr_dual_0f_2b = {
	I(0, em_mov), N
};

4516
static const struct gprefix pfx_0f_2b = {
4517
	ID(0, &instr_dual_0f_2b), ID(0, &instr_dual_0f_2b), N, N,
4518 4519
};

4520 4521 4522 4523
static const struct gprefix pfx_0f_10_0f_11 = {
	I(Unaligned, em_mov), I(Unaligned, em_mov), N, N,
};

4524
static const struct gprefix pfx_0f_28_0f_29 = {
4525
	I(Aligned, em_mov), I(Aligned, em_mov), N, N,
4526 4527
};

4528 4529 4530 4531
static const struct gprefix pfx_0f_e7 = {
	N, I(Sse, em_mov), N, N,
};

4532
static const struct escape escape_d9 = { {
4533
	N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstcw),
4534 4535 4536 4537 4538 4539 4540 4541 4542 4543 4544 4545 4546 4547 4548 4549 4550 4551 4552 4553 4554 4555 4556 4557 4558 4559 4560 4561 4562 4563 4564 4565 4566 4567 4568 4569 4570 4571 4572 4573 4574
}, {
	/* 0xC0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xC8 - 0xCF */
	N, N, N, N, N, N, N, N,
	/* 0xD0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xD8 - 0xDF */
	N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xE7 */
	N, N, N, N, N, N, N, N,
	/* 0xE8 - 0xEF */
	N, N, N, N, N, N, N, N,
	/* 0xF0 - 0xF7 */
	N, N, N, N, N, N, N, N,
	/* 0xF8 - 0xFF */
	N, N, N, N, N, N, N, N,
} };

static const struct escape escape_db = { {
	N, N, N, N, N, N, N, N,
}, {
	/* 0xC0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xC8 - 0xCF */
	N, N, N, N, N, N, N, N,
	/* 0xD0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xD8 - 0xDF */
	N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xE7 */
	N, N, N, I(ImplicitOps, em_fninit), N, N, N, N,
	/* 0xE8 - 0xEF */
	N, N, N, N, N, N, N, N,
	/* 0xF0 - 0xF7 */
	N, N, N, N, N, N, N, N,
	/* 0xF8 - 0xFF */
	N, N, N, N, N, N, N, N,
} };

static const struct escape escape_dd = { {
4575
	N, N, N, N, N, N, N, I(DstMem16 | Mov, em_fnstsw),
4576 4577 4578 4579 4580 4581 4582 4583 4584 4585 4586 4587 4588 4589 4590 4591 4592 4593 4594
}, {
	/* 0xC0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xC8 - 0xCF */
	N, N, N, N, N, N, N, N,
	/* 0xD0 - 0xC7 */
	N, N, N, N, N, N, N, N,
	/* 0xD8 - 0xDF */
	N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xE7 */
	N, N, N, N, N, N, N, N,
	/* 0xE8 - 0xEF */
	N, N, N, N, N, N, N, N,
	/* 0xF0 - 0xF7 */
	N, N, N, N, N, N, N, N,
	/* 0xF8 - 0xFF */
	N, N, N, N, N, N, N, N,
} };

4595 4596 4597 4598
static const struct instr_dual instr_dual_0f_c3 = {
	I(DstMem | SrcReg | ModRM | No16 | Mov, em_mov), N
};

4599 4600 4601 4602
static const struct mode_dual mode_dual_63 = {
	N, I(DstReg | SrcMem32 | ModRM | Mov, em_movsxd)
};

4603
static const struct opcode opcode_table[256] = {
4604
	/* 0x00 - 0x07 */
4605
	F6ALU(Lock, em_add),
4606 4607
	I(ImplicitOps | Stack | No64 | Src2ES, em_push_sreg),
	I(ImplicitOps | Stack | No64 | Src2ES, em_pop_sreg),
4608
	/* 0x08 - 0x0F */
4609
	F6ALU(Lock | PageTable, em_or),
4610 4611
	I(ImplicitOps | Stack | No64 | Src2CS, em_push_sreg),
	N,
4612
	/* 0x10 - 0x17 */
4613
	F6ALU(Lock, em_adc),
4614 4615
	I(ImplicitOps | Stack | No64 | Src2SS, em_push_sreg),
	I(ImplicitOps | Stack | No64 | Src2SS, em_pop_sreg),
4616
	/* 0x18 - 0x1F */
4617
	F6ALU(Lock, em_sbb),
4618 4619
	I(ImplicitOps | Stack | No64 | Src2DS, em_push_sreg),
	I(ImplicitOps | Stack | No64 | Src2DS, em_pop_sreg),
4620
	/* 0x20 - 0x27 */
4621
	F6ALU(Lock | PageTable, em_and), N, N,
4622
	/* 0x28 - 0x2F */
4623
	F6ALU(Lock, em_sub), N, I(ByteOp | DstAcc | No64, em_das),
4624
	/* 0x30 - 0x37 */
4625
	F6ALU(Lock, em_xor), N, N,
4626
	/* 0x38 - 0x3F */
4627
	F6ALU(NoWrite, em_cmp), N, N,
4628
	/* 0x40 - 0x4F */
4629
	X8(F(DstReg, em_inc)), X8(F(DstReg, em_dec)),
4630
	/* 0x50 - 0x57 */
4631
	X8(I(SrcReg | Stack, em_push)),
4632
	/* 0x58 - 0x5F */
4633
	X8(I(DstReg | Stack, em_pop)),
4634
	/* 0x60 - 0x67 */
4635 4636
	I(ImplicitOps | Stack | No64, em_pusha),
	I(ImplicitOps | Stack | No64, em_popa),
4637
	N, MD(ModRM, &mode_dual_63),
4638 4639
	N, N, N, N,
	/* 0x68 - 0x6F */
4640 4641
	I(SrcImm | Mov | Stack, em_push),
	I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
4642 4643
	I(SrcImmByte | Mov | Stack, em_push),
	I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
4644
	I2bvIP(DstDI | SrcDX | Mov | String | Unaligned, em_in, ins, check_perm_in), /* insb, insw/insd */
4645
	I2bvIP(SrcSI | DstDX | String, em_out, outs, check_perm_out), /* outsb, outsw/outsd */
4646
	/* 0x70 - 0x7F */
4647
	X16(D(SrcImmByte | NearBranch)),
4648
	/* 0x80 - 0x87 */
4649 4650 4651 4652
	G(ByteOp | DstMem | SrcImm, group1),
	G(DstMem | SrcImm, group1),
	G(ByteOp | DstMem | SrcImm | No64, group1),
	G(DstMem | SrcImmByte, group1),
4653
	F2bv(DstMem | SrcReg | ModRM | NoWrite, em_test),
4654
	I2bv(DstMem | SrcReg | ModRM | Lock | PageTable, em_xchg),
4655
	/* 0x88 - 0x8F */
4656
	I2bv(DstMem | SrcReg | ModRM | Mov | PageTable, em_mov),
4657
	I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
4658
	I(DstMem | SrcNone | ModRM | Mov | PageTable, em_mov_rm_sreg),
4659 4660 4661
	D(ModRM | SrcMem | NoAccess | DstReg),
	I(ImplicitOps | SrcMem16 | ModRM, em_mov_sreg_rm),
	G(0, group1A),
4662
	/* 0x90 - 0x97 */
4663
	DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
4664
	/* 0x98 - 0x9F */
4665
	D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
4666
	I(SrcImmFAddr | No64, em_call_far), N,
4667
	II(ImplicitOps | Stack, em_pushf, pushf),
P
Paolo Bonzini 已提交
4668 4669
	II(ImplicitOps | Stack, em_popf, popf),
	I(ImplicitOps, em_sahf), I(ImplicitOps, em_lahf),
4670
	/* 0xA0 - 0xA7 */
4671
	I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
4672
	I2bv(DstMem | SrcAcc | Mov | MemAbs | PageTable, em_mov),
4673 4674
	I2bv(SrcSI | DstDI | Mov | String | TwoMemOp, em_mov),
	F2bv(SrcSI | DstDI | String | NoWrite | TwoMemOp, em_cmp_r),
4675
	/* 0xA8 - 0xAF */
4676
	F2bv(DstAcc | SrcImm | NoWrite, em_test),
4677 4678
	I2bv(SrcAcc | DstDI | Mov | String, em_mov),
	I2bv(SrcSI | DstAcc | Mov | String, em_mov),
4679
	F2bv(SrcAcc | DstDI | String | NoWrite, em_cmp_r),
4680
	/* 0xB0 - 0xB7 */
4681
	X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
4682
	/* 0xB8 - 0xBF */
4683
	X8(I(DstReg | SrcImm64 | Mov, em_mov)),
4684
	/* 0xC0 - 0xC7 */
4685
	G(ByteOp | Src2ImmByte, group2), G(Src2ImmByte, group2),
4686 4687
	I(ImplicitOps | NearBranch | SrcImmU16, em_ret_near_imm),
	I(ImplicitOps | NearBranch, em_ret),
4688 4689
	I(DstReg | SrcMemFAddr | ModRM | No64 | Src2ES, em_lseg),
	I(DstReg | SrcMemFAddr | ModRM | No64 | Src2DS, em_lseg),
4690
	G(ByteOp, group11), G(0, group11),
4691
	/* 0xC8 - 0xCF */
A
Avi Kivity 已提交
4692
	I(Stack | SrcImmU16 | Src2ImmByte, em_enter), I(Stack, em_leave),
4693 4694
	I(ImplicitOps | SrcImmU16, em_ret_far_imm),
	I(ImplicitOps, em_ret_far),
4695
	D(ImplicitOps), DI(SrcImmByte, intn),
4696
	D(ImplicitOps | No64), II(ImplicitOps, em_iret, iret),
4697
	/* 0xD0 - 0xD7 */
4698 4699
	G(Src2One | ByteOp, group2), G(Src2One, group2),
	G(Src2CL | ByteOp, group2), G(Src2CL, group2),
P
Paolo Bonzini 已提交
4700
	I(DstAcc | SrcImmUByte | No64, em_aam),
P
Paolo Bonzini 已提交
4701 4702
	I(DstAcc | SrcImmUByte | No64, em_aad),
	F(DstAcc | ByteOp | No64, em_salc),
P
Paolo Bonzini 已提交
4703
	I(DstAcc | SrcXLat | ByteOp, em_mov),
4704
	/* 0xD8 - 0xDF */
4705
	N, E(0, &escape_d9), N, E(0, &escape_db), N, E(0, &escape_dd), N, N,
4706
	/* 0xE0 - 0xE7 */
4707 4708
	X3(I(SrcImmByte | NearBranch, em_loop)),
	I(SrcImmByte | NearBranch, em_jcxz),
4709 4710
	I2bvIP(SrcImmUByte | DstAcc, em_in,  in,  check_perm_in),
	I2bvIP(SrcAcc | DstImmUByte, em_out, out, check_perm_out),
4711
	/* 0xE8 - 0xEF */
4712 4713 4714
	I(SrcImm | NearBranch, em_call), D(SrcImm | ImplicitOps | NearBranch),
	I(SrcImmFAddr | No64, em_jmp_far),
	D(SrcImmByte | ImplicitOps | NearBranch),
4715 4716
	I2bvIP(SrcDX | DstAcc, em_in,  in,  check_perm_in),
	I2bvIP(SrcAcc | DstDX, em_out, out, check_perm_out),
4717
	/* 0xF0 - 0xF7 */
4718
	N, DI(ImplicitOps, icebp), N, N,
4719 4720
	DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
	G(ByteOp, group3), G(0, group3),
4721
	/* 0xF8 - 0xFF */
4722 4723
	D(ImplicitOps), D(ImplicitOps),
	I(ImplicitOps, em_cli), I(ImplicitOps, em_sti),
4724 4725 4726
	D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
};

4727
static const struct opcode twobyte_table[256] = {
4728
	/* 0x00 - 0x0F */
4729
	G(0, group6), GD(0, &group7), N, N,
4730
	N, I(ImplicitOps | EmulateOnUD, em_syscall),
4731
	II(ImplicitOps | Priv, em_clts, clts), N,
4732
	DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
4733
	N, D(ImplicitOps | ModRM | SrcMem | NoAccess), N, N,
4734
	/* 0x10 - 0x1F */
4735 4736 4737
	GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_10_0f_11),
	GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_10_0f_11),
	N, N, N, N, N, N,
4738 4739
	D(ImplicitOps | ModRM | SrcMem | NoAccess),
	N, N, N, N, N, N, D(ImplicitOps | ModRM | SrcMem | NoAccess),
4740
	/* 0x20 - 0x2F */
4741 4742 4743 4744 4745 4746
	DIP(ModRM | DstMem | Priv | Op3264 | NoMod, cr_read, check_cr_read),
	DIP(ModRM | DstMem | Priv | Op3264 | NoMod, dr_read, check_dr_read),
	IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_cr_write, cr_write,
						check_cr_write),
	IIP(ModRM | SrcMem | Priv | Op3264 | NoMod, em_dr_write, dr_write,
						check_dr_write),
4747
	N, N, N, N,
4748 4749
	GP(ModRM | DstReg | SrcMem | Mov | Sse, &pfx_0f_28_0f_29),
	GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_28_0f_29),
4750
	N, GP(ModRM | DstMem | SrcReg | Mov | Sse, &pfx_0f_2b),
4751
	N, N, N, N,
4752
	/* 0x30 - 0x3F */
4753
	II(ImplicitOps | Priv, em_wrmsr, wrmsr),
4754
	IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
4755
	II(ImplicitOps | Priv, em_rdmsr, rdmsr),
4756
	IIP(ImplicitOps, em_rdpmc, rdpmc, check_rdpmc),
4757 4758
	I(ImplicitOps | EmulateOnUD, em_sysenter),
	I(ImplicitOps | Priv | EmulateOnUD, em_sysexit),
4759
	N, N,
4760 4761
	N, N, N, N, N, N, N, N,
	/* 0x40 - 0x4F */
4762
	X16(D(DstReg | SrcMem | ModRM)),
4763 4764 4765
	/* 0x50 - 0x5F */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0x60 - 0x6F */
4766 4767 4768 4769
	N, N, N, N,
	N, N, N, N,
	N, N, N, N,
	N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
4770
	/* 0x70 - 0x7F */
4771 4772 4773 4774
	N, N, N, N,
	N, N, N, N,
	N, N, N, N,
	N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
4775
	/* 0x80 - 0x8F */
4776
	X16(D(SrcImm | NearBranch)),
4777
	/* 0x90 - 0x9F */
4778
	X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
4779
	/* 0xA0 - 0xA7 */
4780
	I(Stack | Src2FS, em_push_sreg), I(Stack | Src2FS, em_pop_sreg),
4781 4782
	II(ImplicitOps, em_cpuid, cpuid),
	F(DstMem | SrcReg | ModRM | BitOp | NoWrite, em_bt),
4783 4784
	F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shld),
	F(DstMem | SrcReg | Src2CL | ModRM, em_shld), N, N,
4785
	/* 0xA8 - 0xAF */
4786
	I(Stack | Src2GS, em_push_sreg), I(Stack | Src2GS, em_pop_sreg),
4787
	II(EmulateOnUD | ImplicitOps, em_rsm, rsm),
4788
	F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_bts),
4789 4790
	F(DstMem | SrcReg | Src2ImmByte | ModRM, em_shrd),
	F(DstMem | SrcReg | Src2CL | ModRM, em_shrd),
4791
	GD(0, &group15), F(DstReg | SrcMem | ModRM, em_imul),
4792
	/* 0xB0 - 0xB7 */
4793
	I2bv(DstMem | SrcReg | ModRM | Lock | PageTable | SrcWrite, em_cmpxchg),
4794
	I(DstReg | SrcMemFAddr | ModRM | Src2SS, em_lseg),
4795
	F(DstMem | SrcReg | ModRM | BitOp | Lock, em_btr),
4796 4797
	I(DstReg | SrcMemFAddr | ModRM | Src2FS, em_lseg),
	I(DstReg | SrcMemFAddr | ModRM | Src2GS, em_lseg),
4798
	D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
4799 4800
	/* 0xB8 - 0xBF */
	N, N,
4801
	G(BitOp, group8),
4802
	F(DstMem | SrcReg | ModRM | BitOp | Lock | PageTable, em_btc),
4803 4804
	I(DstReg | SrcMem | ModRM, em_bsf_c),
	I(DstReg | SrcMem | ModRM, em_bsr_c),
4805
	D(DstReg | SrcMem8 | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
A
Avi Kivity 已提交
4806
	/* 0xC0 - 0xC7 */
4807
	F2bv(DstMem | SrcReg | ModRM | SrcWrite | Lock, em_xadd),
4808
	N, ID(0, &instr_dual_0f_c3),
4809
	N, N, N, GD(0, &group9),
A
Avi Kivity 已提交
4810 4811
	/* 0xC8 - 0xCF */
	X8(I(DstReg, em_bswap)),
4812 4813 4814
	/* 0xD0 - 0xDF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
	/* 0xE0 - 0xEF */
4815 4816
	N, N, N, N, N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_e7),
	N, N, N, N, N, N, N, N,
4817 4818 4819 4820
	/* 0xF0 - 0xFF */
	N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
};

4821 4822 4823 4824 4825 4826 4827 4828
static const struct instr_dual instr_dual_0f_38_f0 = {
	I(DstReg | SrcMem | Mov, em_movbe), N
};

static const struct instr_dual instr_dual_0f_38_f1 = {
	I(DstMem | SrcReg | Mov, em_movbe), N
};

4829
static const struct gprefix three_byte_0f_38_f0 = {
4830
	ID(0, &instr_dual_0f_38_f0), N, N, N
4831 4832 4833
};

static const struct gprefix three_byte_0f_38_f1 = {
4834
	ID(0, &instr_dual_0f_38_f1), N, N, N
4835 4836 4837 4838 4839 4840 4841 4842 4843
};

/*
 * Insns below are selected by the prefix which indexed by the third opcode
 * byte.
 */
static const struct opcode opcode_map_0f_38[256] = {
	/* 0x00 - 0x7f */
	X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
B
Borislav Petkov 已提交
4844 4845 4846
	/* 0x80 - 0xef */
	X16(N), X16(N), X16(N), X16(N), X16(N), X16(N), X16(N),
	/* 0xf0 - 0xf1 */
4847 4848
	GP(EmulateOnUD | ModRM, &three_byte_0f_38_f0),
	GP(EmulateOnUD | ModRM, &three_byte_0f_38_f1),
B
Borislav Petkov 已提交
4849 4850
	/* 0xf2 - 0xff */
	N, N, X4(N), X8(N)
4851 4852
};

4853 4854 4855 4856 4857
#undef D
#undef N
#undef G
#undef GD
#undef I
4858
#undef GP
4859
#undef EXT
4860
#undef MD
N
Nadav Amit 已提交
4861
#undef ID
4862

4863
#undef D2bv
4864
#undef D2bvIP
4865
#undef I2bv
4866
#undef I2bvIP
4867
#undef I6ALU
4868

4869
static unsigned imm_size(struct x86_emulate_ctxt *ctxt)
4870 4871 4872
{
	unsigned size;

4873
	size = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4874 4875 4876 4877 4878 4879 4880 4881 4882 4883 4884 4885
	if (size == 8)
		size = 4;
	return size;
}

static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
		      unsigned size, bool sign_extension)
{
	int rc = X86EMUL_CONTINUE;

	op->type = OP_IMM;
	op->bytes = size;
4886
	op->addr.mem.ea = ctxt->_eip;
4887 4888 4889
	/* NB. Immediates are sign-extended as necessary. */
	switch (op->bytes) {
	case 1:
4890
		op->val = insn_fetch(s8, ctxt);
4891 4892
		break;
	case 2:
4893
		op->val = insn_fetch(s16, ctxt);
4894 4895
		break;
	case 4:
4896
		op->val = insn_fetch(s32, ctxt);
4897
		break;
4898 4899 4900
	case 8:
		op->val = insn_fetch(s64, ctxt);
		break;
4901 4902 4903 4904 4905 4906 4907 4908 4909 4910 4911 4912 4913 4914 4915 4916 4917 4918
	}
	if (!sign_extension) {
		switch (op->bytes) {
		case 1:
			op->val &= 0xff;
			break;
		case 2:
			op->val &= 0xffff;
			break;
		case 4:
			op->val &= 0xffffffff;
			break;
		}
	}
done:
	return rc;
}

4919 4920 4921 4922 4923 4924 4925
static int decode_operand(struct x86_emulate_ctxt *ctxt, struct operand *op,
			  unsigned d)
{
	int rc = X86EMUL_CONTINUE;

	switch (d) {
	case OpReg:
4926
		decode_register_operand(ctxt, op);
4927 4928
		break;
	case OpImmUByte:
4929
		rc = decode_imm(ctxt, op, 1, false);
4930 4931
		break;
	case OpMem:
4932
		ctxt->memop.bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4933 4934 4935
	mem_common:
		*op = ctxt->memop;
		ctxt->memopp = op;
4936
		if (ctxt->d & BitOp)
4937 4938 4939
			fetch_bit_operand(ctxt);
		op->orig_val = op->val;
		break;
4940
	case OpMem64:
4941
		ctxt->memop.bytes = (ctxt->op_bytes == 8) ? 16 : 8;
4942
		goto mem_common;
4943 4944 4945
	case OpAcc:
		op->type = OP_REG;
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
4946
		op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
4947 4948 4949
		fetch_register_operand(op);
		op->orig_val = op->val;
		break;
4950 4951 4952 4953 4954 4955 4956 4957 4958 4959 4960 4961 4962 4963 4964 4965 4966 4967
	case OpAccLo:
		op->type = OP_REG;
		op->bytes = (ctxt->d & ByteOp) ? 2 : ctxt->op_bytes;
		op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RAX);
		fetch_register_operand(op);
		op->orig_val = op->val;
		break;
	case OpAccHi:
		if (ctxt->d & ByteOp) {
			op->type = OP_NONE;
			break;
		}
		op->type = OP_REG;
		op->bytes = ctxt->op_bytes;
		op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
		fetch_register_operand(op);
		op->orig_val = op->val;
		break;
4968 4969 4970 4971
	case OpDI:
		op->type = OP_MEM;
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		op->addr.mem.ea =
4972
			register_address(ctxt, VCPU_REGS_RDI);
4973 4974
		op->addr.mem.seg = VCPU_SREG_ES;
		op->val = 0;
4975
		op->count = 1;
4976 4977 4978 4979
		break;
	case OpDX:
		op->type = OP_REG;
		op->bytes = 2;
4980
		op->addr.reg = reg_rmw(ctxt, VCPU_REGS_RDX);
4981 4982
		fetch_register_operand(op);
		break;
4983
	case OpCL:
4984
		op->type = OP_IMM;
4985
		op->bytes = 1;
4986
		op->val = reg_read(ctxt, VCPU_REGS_RCX) & 0xff;
4987 4988 4989 4990 4991
		break;
	case OpImmByte:
		rc = decode_imm(ctxt, op, 1, true);
		break;
	case OpOne:
4992
		op->type = OP_IMM;
4993 4994 4995 4996 4997 4998
		op->bytes = 1;
		op->val = 1;
		break;
	case OpImm:
		rc = decode_imm(ctxt, op, imm_size(ctxt), true);
		break;
4999 5000 5001
	case OpImm64:
		rc = decode_imm(ctxt, op, ctxt->op_bytes, true);
		break;
5002 5003
	case OpMem8:
		ctxt->memop.bytes = 1;
5004
		if (ctxt->memop.type == OP_REG) {
5005 5006
			ctxt->memop.addr.reg = decode_register(ctxt,
					ctxt->modrm_rm, true);
5007 5008
			fetch_register_operand(&ctxt->memop);
		}
5009
		goto mem_common;
5010 5011 5012 5013 5014 5015 5016 5017 5018 5019 5020 5021 5022 5023 5024 5025
	case OpMem16:
		ctxt->memop.bytes = 2;
		goto mem_common;
	case OpMem32:
		ctxt->memop.bytes = 4;
		goto mem_common;
	case OpImmU16:
		rc = decode_imm(ctxt, op, 2, false);
		break;
	case OpImmU:
		rc = decode_imm(ctxt, op, imm_size(ctxt), false);
		break;
	case OpSI:
		op->type = OP_MEM;
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		op->addr.mem.ea =
5026
			register_address(ctxt, VCPU_REGS_RSI);
B
Bandan Das 已提交
5027
		op->addr.mem.seg = ctxt->seg_override;
5028
		op->val = 0;
5029
		op->count = 1;
5030
		break;
P
Paolo Bonzini 已提交
5031 5032 5033 5034
	case OpXLat:
		op->type = OP_MEM;
		op->bytes = (ctxt->d & ByteOp) ? 1 : ctxt->op_bytes;
		op->addr.mem.ea =
5035
			address_mask(ctxt,
P
Paolo Bonzini 已提交
5036 5037
				reg_read(ctxt, VCPU_REGS_RBX) +
				(reg_read(ctxt, VCPU_REGS_RAX) & 0xff));
B
Bandan Das 已提交
5038
		op->addr.mem.seg = ctxt->seg_override;
P
Paolo Bonzini 已提交
5039 5040
		op->val = 0;
		break;
5041 5042 5043 5044 5045 5046 5047 5048 5049
	case OpImmFAddr:
		op->type = OP_IMM;
		op->addr.mem.ea = ctxt->_eip;
		op->bytes = ctxt->op_bytes + 2;
		insn_fetch_arr(op->valptr, op->bytes, ctxt);
		break;
	case OpMemFAddr:
		ctxt->memop.bytes = ctxt->op_bytes + 2;
		goto mem_common;
5050
	case OpES:
5051
		op->type = OP_IMM;
5052 5053 5054
		op->val = VCPU_SREG_ES;
		break;
	case OpCS:
5055
		op->type = OP_IMM;
5056 5057 5058
		op->val = VCPU_SREG_CS;
		break;
	case OpSS:
5059
		op->type = OP_IMM;
5060 5061 5062
		op->val = VCPU_SREG_SS;
		break;
	case OpDS:
5063
		op->type = OP_IMM;
5064 5065 5066
		op->val = VCPU_SREG_DS;
		break;
	case OpFS:
5067
		op->type = OP_IMM;
5068 5069 5070
		op->val = VCPU_SREG_FS;
		break;
	case OpGS:
5071
		op->type = OP_IMM;
5072 5073
		op->val = VCPU_SREG_GS;
		break;
5074 5075 5076 5077 5078 5079 5080 5081 5082 5083 5084
	case OpImplicit:
		/* Special instructions do their own operand decoding. */
	default:
		op->type = OP_NONE; /* Disable writeback. */
		break;
	}

done:
	return rc;
}

5085
int x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
5086 5087 5088
{
	int rc = X86EMUL_CONTINUE;
	int mode = ctxt->mode;
5089
	int def_op_bytes, def_ad_bytes, goffset, simd_prefix;
5090
	bool op_prefix = false;
B
Bandan Das 已提交
5091
	bool has_seg_override = false;
5092
	struct opcode opcode;
5093 5094
	u16 dummy;
	struct desc_struct desc;
5095

5096 5097
	ctxt->memop.type = OP_NONE;
	ctxt->memopp = NULL;
5098
	ctxt->_eip = ctxt->eip;
5099 5100
	ctxt->fetch.ptr = ctxt->fetch.data;
	ctxt->fetch.end = ctxt->fetch.data + insn_len;
B
Borislav Petkov 已提交
5101
	ctxt->opcode_len = 1;
5102
	if (insn_len > 0)
5103
		memcpy(ctxt->fetch.data, insn, insn_len);
5104
	else {
5105
		rc = __do_insn_fetch_bytes(ctxt, 1);
5106 5107 5108
		if (rc != X86EMUL_CONTINUE)
			return rc;
	}
5109 5110 5111 5112

	switch (mode) {
	case X86EMUL_MODE_REAL:
	case X86EMUL_MODE_VM86:
5113 5114 5115 5116 5117
		def_op_bytes = def_ad_bytes = 2;
		ctxt->ops->get_segment(ctxt, &dummy, &desc, NULL, VCPU_SREG_CS);
		if (desc.d)
			def_op_bytes = def_ad_bytes = 4;
		break;
5118 5119 5120 5121 5122 5123 5124 5125 5126 5127 5128 5129 5130
	case X86EMUL_MODE_PROT16:
		def_op_bytes = def_ad_bytes = 2;
		break;
	case X86EMUL_MODE_PROT32:
		def_op_bytes = def_ad_bytes = 4;
		break;
#ifdef CONFIG_X86_64
	case X86EMUL_MODE_PROT64:
		def_op_bytes = 4;
		def_ad_bytes = 8;
		break;
#endif
	default:
5131
		return EMULATION_FAILED;
5132 5133
	}

5134 5135
	ctxt->op_bytes = def_op_bytes;
	ctxt->ad_bytes = def_ad_bytes;
5136 5137 5138

	/* Legacy prefixes. */
	for (;;) {
5139
		switch (ctxt->b = insn_fetch(u8, ctxt)) {
5140
		case 0x66:	/* operand-size override */
5141
			op_prefix = true;
5142
			/* switch between 2/4 bytes */
5143
			ctxt->op_bytes = def_op_bytes ^ 6;
5144 5145 5146 5147
			break;
		case 0x67:	/* address-size override */
			if (mode == X86EMUL_MODE_PROT64)
				/* switch between 4/8 bytes */
5148
				ctxt->ad_bytes = def_ad_bytes ^ 12;
5149 5150
			else
				/* switch between 2/4 bytes */
5151
				ctxt->ad_bytes = def_ad_bytes ^ 6;
5152 5153 5154 5155 5156
			break;
		case 0x26:	/* ES override */
		case 0x2e:	/* CS override */
		case 0x36:	/* SS override */
		case 0x3e:	/* DS override */
B
Bandan Das 已提交
5157 5158
			has_seg_override = true;
			ctxt->seg_override = (ctxt->b >> 3) & 3;
5159 5160 5161
			break;
		case 0x64:	/* FS override */
		case 0x65:	/* GS override */
B
Bandan Das 已提交
5162 5163
			has_seg_override = true;
			ctxt->seg_override = ctxt->b & 7;
5164 5165 5166 5167
			break;
		case 0x40 ... 0x4f: /* REX */
			if (mode != X86EMUL_MODE_PROT64)
				goto done_prefixes;
5168
			ctxt->rex_prefix = ctxt->b;
5169 5170
			continue;
		case 0xf0:	/* LOCK */
5171
			ctxt->lock_prefix = 1;
5172 5173 5174
			break;
		case 0xf2:	/* REPNE/REPNZ */
		case 0xf3:	/* REP/REPE/REPZ */
5175
			ctxt->rep_prefix = ctxt->b;
5176 5177 5178 5179 5180 5181 5182
			break;
		default:
			goto done_prefixes;
		}

		/* Any legacy prefix after a REX prefix nullifies its effect. */

5183
		ctxt->rex_prefix = 0;
5184 5185 5186 5187 5188
	}

done_prefixes:

	/* REX prefix. */
5189 5190
	if (ctxt->rex_prefix & 8)
		ctxt->op_bytes = 8;	/* REX.W */
5191 5192

	/* Opcode byte(s). */
5193
	opcode = opcode_table[ctxt->b];
5194
	/* Two-byte opcode? */
5195
	if (ctxt->b == 0x0f) {
B
Borislav Petkov 已提交
5196
		ctxt->opcode_len = 2;
5197
		ctxt->b = insn_fetch(u8, ctxt);
5198
		opcode = twobyte_table[ctxt->b];
5199 5200 5201 5202 5203 5204 5205

		/* 0F_38 opcode map */
		if (ctxt->b == 0x38) {
			ctxt->opcode_len = 3;
			ctxt->b = insn_fetch(u8, ctxt);
			opcode = opcode_map_0f_38[ctxt->b];
		}
5206
	}
5207
	ctxt->d = opcode.flags;
5208

5209 5210 5211
	if (ctxt->d & ModRM)
		ctxt->modrm = insn_fetch(u8, ctxt);

5212 5213
	/* vex-prefix instructions are not implemented */
	if (ctxt->opcode_len == 1 && (ctxt->b == 0xc5 || ctxt->b == 0xc4) &&
5214
	    (mode == X86EMUL_MODE_PROT64 || (ctxt->modrm & 0xc0) == 0xc0)) {
5215 5216 5217
		ctxt->d = NotImpl;
	}

5218 5219
	while (ctxt->d & GroupMask) {
		switch (ctxt->d & GroupMask) {
5220
		case Group:
5221
			goffset = (ctxt->modrm >> 3) & 7;
5222 5223 5224
			opcode = opcode.u.group[goffset];
			break;
		case GroupDual:
5225 5226
			goffset = (ctxt->modrm >> 3) & 7;
			if ((ctxt->modrm >> 6) == 3)
5227 5228 5229 5230 5231
				opcode = opcode.u.gdual->mod3[goffset];
			else
				opcode = opcode.u.gdual->mod012[goffset];
			break;
		case RMExt:
5232
			goffset = ctxt->modrm & 7;
5233
			opcode = opcode.u.group[goffset];
5234 5235
			break;
		case Prefix:
5236
			if (ctxt->rep_prefix && op_prefix)
5237
				return EMULATION_FAILED;
5238
			simd_prefix = op_prefix ? 0x66 : ctxt->rep_prefix;
5239 5240 5241 5242 5243 5244 5245
			switch (simd_prefix) {
			case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
			case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
			case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
			case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
			}
			break;
5246 5247 5248 5249 5250 5251
		case Escape:
			if (ctxt->modrm > 0xbf)
				opcode = opcode.u.esc->high[ctxt->modrm - 0xc0];
			else
				opcode = opcode.u.esc->op[(ctxt->modrm >> 3) & 7];
			break;
5252 5253 5254 5255 5256 5257
		case InstrDual:
			if ((ctxt->modrm >> 6) == 3)
				opcode = opcode.u.idual->mod3;
			else
				opcode = opcode.u.idual->mod012;
			break;
5258 5259 5260 5261 5262 5263
		case ModeDual:
			if (ctxt->mode == X86EMUL_MODE_PROT64)
				opcode = opcode.u.mdual->mode64;
			else
				opcode = opcode.u.mdual->mode32;
			break;
5264
		default:
5265
			return EMULATION_FAILED;
5266
		}
5267

5268
		ctxt->d &= ~(u64)GroupMask;
5269
		ctxt->d |= opcode.flags;
5270 5271
	}

5272 5273 5274 5275
	/* Unrecognised? */
	if (ctxt->d == 0)
		return EMULATION_FAILED;

5276
	ctxt->execute = opcode.u.execute;
5277

5278 5279 5280
	if (unlikely(ctxt->ud) && likely(!(ctxt->d & EmulateOnUD)))
		return EMULATION_FAILED;

5281
	if (unlikely(ctxt->d &
5282 5283
	    (NotImpl|Stack|Op3264|Sse|Mmx|Intercept|CheckPerm|NearBranch|
	     No16))) {
5284 5285 5286 5287 5288 5289
		/*
		 * These are copied unconditionally here, and checked unconditionally
		 * in x86_emulate_insn.
		 */
		ctxt->check_perm = opcode.check_perm;
		ctxt->intercept = opcode.intercept;
5290

5291 5292
		if (ctxt->d & NotImpl)
			return EMULATION_FAILED;
5293

5294 5295 5296 5297 5298 5299
		if (mode == X86EMUL_MODE_PROT64) {
			if (ctxt->op_bytes == 4 && (ctxt->d & Stack))
				ctxt->op_bytes = 8;
			else if (ctxt->d & NearBranch)
				ctxt->op_bytes = 8;
		}
5300

5301 5302 5303 5304 5305 5306 5307
		if (ctxt->d & Op3264) {
			if (mode == X86EMUL_MODE_PROT64)
				ctxt->op_bytes = 8;
			else
				ctxt->op_bytes = 4;
		}

5308 5309 5310
		if ((ctxt->d & No16) && ctxt->op_bytes == 2)
			ctxt->op_bytes = 4;

5311 5312 5313 5314 5315
		if (ctxt->d & Sse)
			ctxt->op_bytes = 16;
		else if (ctxt->d & Mmx)
			ctxt->op_bytes = 8;
	}
A
Avi Kivity 已提交
5316

5317
	/* ModRM and SIB bytes. */
5318
	if (ctxt->d & ModRM) {
5319
		rc = decode_modrm(ctxt, &ctxt->memop);
B
Bandan Das 已提交
5320 5321 5322 5323
		if (!has_seg_override) {
			has_seg_override = true;
			ctxt->seg_override = ctxt->modrm_seg;
		}
5324
	} else if (ctxt->d & MemAbs)
5325
		rc = decode_abs(ctxt, &ctxt->memop);
5326 5327 5328
	if (rc != X86EMUL_CONTINUE)
		goto done;

B
Bandan Das 已提交
5329 5330
	if (!has_seg_override)
		ctxt->seg_override = VCPU_SREG_DS;
5331

B
Bandan Das 已提交
5332
	ctxt->memop.addr.mem.seg = ctxt->seg_override;
5333 5334 5335 5336 5337

	/*
	 * Decode and fetch the source operand: register, memory
	 * or immediate.
	 */
5338
	rc = decode_operand(ctxt, &ctxt->src, (ctxt->d >> SrcShift) & OpMask);
5339 5340 5341
	if (rc != X86EMUL_CONTINUE)
		goto done;

5342 5343 5344 5345
	/*
	 * Decode and fetch the second source operand: register, memory
	 * or immediate.
	 */
5346
	rc = decode_operand(ctxt, &ctxt->src2, (ctxt->d >> Src2Shift) & OpMask);
5347 5348 5349
	if (rc != X86EMUL_CONTINUE)
		goto done;

5350
	/* Decode and fetch the destination operand: register or memory. */
5351
	rc = decode_operand(ctxt, &ctxt->dst, (ctxt->d >> DstShift) & OpMask);
5352

5353
	if (ctxt->rip_relative && likely(ctxt->memopp))
5354 5355
		ctxt->memopp->addr.mem.ea = address_mask(ctxt,
					ctxt->memopp->addr.mem.ea + ctxt->_eip);
5356

5357
done:
5358
	return (rc != X86EMUL_CONTINUE) ? EMULATION_FAILED : EMULATION_OK;
5359 5360
}

5361 5362 5363 5364 5365
bool x86_page_table_writing_insn(struct x86_emulate_ctxt *ctxt)
{
	return ctxt->d & PageTable;
}

5366 5367 5368 5369 5370 5371 5372 5373 5374
static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
{
	/* The second termination condition only applies for REPE
	 * and REPNE. Test if the repeat string operation prefix is
	 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
	 * corresponding termination condition according to:
	 * 	- if REPE/REPZ and ZF = 0 then done
	 * 	- if REPNE/REPNZ and ZF = 1 then done
	 */
5375 5376 5377
	if (((ctxt->b == 0xa6) || (ctxt->b == 0xa7) ||
	     (ctxt->b == 0xae) || (ctxt->b == 0xaf))
	    && (((ctxt->rep_prefix == REPE_PREFIX) &&
5378
		 ((ctxt->eflags & X86_EFLAGS_ZF) == 0))
5379
		|| ((ctxt->rep_prefix == REPNE_PREFIX) &&
5380
		    ((ctxt->eflags & X86_EFLAGS_ZF) == X86_EFLAGS_ZF))))
5381 5382 5383 5384 5385
		return true;

	return false;
}

A
Avi Kivity 已提交
5386 5387
static int flush_pending_x87_faults(struct x86_emulate_ctxt *ctxt)
{
R
Radim Krčmář 已提交
5388
	int rc;
A
Avi Kivity 已提交
5389

R
Radim Krčmář 已提交
5390
	rc = asm_safe("fwait");
A
Avi Kivity 已提交
5391

R
Radim Krčmář 已提交
5392
	if (unlikely(rc != X86EMUL_CONTINUE))
A
Avi Kivity 已提交
5393 5394 5395 5396 5397 5398 5399 5400 5401 5402 5403 5404
		return emulate_exception(ctxt, MF_VECTOR, 0, false);

	return X86EMUL_CONTINUE;
}

static void fetch_possible_mmx_operand(struct x86_emulate_ctxt *ctxt,
				       struct operand *op)
{
	if (op->type == OP_MM)
		read_mmx_reg(ctxt, &op->mm_val, op->addr.mm);
}

5405 5406 5407
static int fastop(struct x86_emulate_ctxt *ctxt, void (*fop)(struct fastop *))
{
	ulong flags = (ctxt->eflags & EFLAGS_MASK) | X86_EFLAGS_IF;
5408

5409 5410
	if (!(ctxt->d & ByteOp))
		fop += __ffs(ctxt->dst.bytes) * FASTOP_SIZE;
5411

5412
	asm("push %[flags]; popf; " CALL_NOSPEC " ; pushf; pop %[flags]\n"
5413
	    : "+a"(ctxt->dst.val), "+d"(ctxt->src.val), [flags]"+D"(flags),
5414
	      [thunk_target]"+S"(fop), ASM_CALL_CONSTRAINT
5415
	    : "c"(ctxt->src2.val));
5416

5417
	ctxt->eflags = (ctxt->eflags & ~EFLAGS_MASK) | (flags & EFLAGS_MASK);
5418 5419
	if (!fop) /* exception is returned in fop variable */
		return emulate_de(ctxt);
5420 5421
	return X86EMUL_CONTINUE;
}
5422

5423 5424
void init_decode_cache(struct x86_emulate_ctxt *ctxt)
{
B
Bandan Das 已提交
5425 5426
	memset(&ctxt->rip_relative, 0,
	       (void *)&ctxt->modrm - (void *)&ctxt->rip_relative);
5427 5428 5429 5430 5431 5432

	ctxt->io_read.pos = 0;
	ctxt->io_read.end = 0;
	ctxt->mem_read.end = 0;
}

5433
int x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
5434
{
5435
	const struct x86_emulate_ops *ops = ctxt->ops;
5436
	int rc = X86EMUL_CONTINUE;
5437
	int saved_dst_type = ctxt->dst.type;
5438
	unsigned emul_flags;
5439

5440
	ctxt->mem_read.pos = 0;
5441

5442 5443
	/* LOCK prefix is allowed only with some instructions */
	if (ctxt->lock_prefix && (!(ctxt->d & Lock) || ctxt->dst.type != OP_MEM)) {
5444
		rc = emulate_ud(ctxt);
5445 5446 5447
		goto done;
	}

5448
	if ((ctxt->d & SrcMask) == SrcMemFAddr && ctxt->src.type != OP_MEM) {
5449
		rc = emulate_ud(ctxt);
5450 5451 5452
		goto done;
	}

5453
	emul_flags = ctxt->ops->get_hflags(ctxt);
5454 5455 5456 5457 5458 5459 5460
	if (unlikely(ctxt->d &
		     (No64|Undefined|Sse|Mmx|Intercept|CheckPerm|Priv|Prot|String))) {
		if ((ctxt->mode == X86EMUL_MODE_PROT64 && (ctxt->d & No64)) ||
				(ctxt->d & Undefined)) {
			rc = emulate_ud(ctxt);
			goto done;
		}
A
Avi Kivity 已提交
5461

5462 5463 5464
		if (((ctxt->d & (Sse|Mmx)) && ((ops->get_cr(ctxt, 0) & X86_CR0_EM)))
		    || ((ctxt->d & Sse) && !(ops->get_cr(ctxt, 4) & X86_CR4_OSFXSR))) {
			rc = emulate_ud(ctxt);
A
Avi Kivity 已提交
5465
			goto done;
5466
		}
A
Avi Kivity 已提交
5467

5468 5469
		if ((ctxt->d & (Sse|Mmx)) && (ops->get_cr(ctxt, 0) & X86_CR0_TS)) {
			rc = emulate_nm(ctxt);
5470
			goto done;
5471
		}
5472

5473 5474 5475 5476 5477 5478 5479 5480 5481 5482 5483 5484 5485
		if (ctxt->d & Mmx) {
			rc = flush_pending_x87_faults(ctxt);
			if (rc != X86EMUL_CONTINUE)
				goto done;
			/*
			 * Now that we know the fpu is exception safe, we can fetch
			 * operands from it.
			 */
			fetch_possible_mmx_operand(ctxt, &ctxt->src);
			fetch_possible_mmx_operand(ctxt, &ctxt->src2);
			if (!(ctxt->d & Mov))
				fetch_possible_mmx_operand(ctxt, &ctxt->dst);
		}
5486

5487
		if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && ctxt->intercept) {
5488 5489 5490 5491 5492
			rc = emulator_check_intercept(ctxt, ctxt->intercept,
						      X86_ICPT_PRE_EXCEPT);
			if (rc != X86EMUL_CONTINUE)
				goto done;
		}
5493

5494 5495 5496 5497 5498 5499
		/* Instruction can only be executed in protected mode */
		if ((ctxt->d & Prot) && ctxt->mode < X86EMUL_MODE_PROT16) {
			rc = emulate_ud(ctxt);
			goto done;
		}

5500 5501
		/* Privileged instruction can be executed only in CPL=0 */
		if ((ctxt->d & Priv) && ops->cpl(ctxt)) {
5502 5503 5504 5505
			if (ctxt->d & PrivUD)
				rc = emulate_ud(ctxt);
			else
				rc = emulate_gp(ctxt, 0);
5506
			goto done;
5507
		}
5508

5509
		/* Do instruction specific permission checks */
5510
		if (ctxt->d & CheckPerm) {
5511 5512 5513 5514 5515
			rc = ctxt->check_perm(ctxt);
			if (rc != X86EMUL_CONTINUE)
				goto done;
		}

5516
		if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) {
5517 5518 5519 5520 5521 5522 5523 5524 5525
			rc = emulator_check_intercept(ctxt, ctxt->intercept,
						      X86_ICPT_POST_EXCEPT);
			if (rc != X86EMUL_CONTINUE)
				goto done;
		}

		if (ctxt->rep_prefix && (ctxt->d & String)) {
			/* All REP prefixes have the same first termination condition */
			if (address_mask(ctxt, reg_read(ctxt, VCPU_REGS_RCX)) == 0) {
5526
				string_registers_quirk(ctxt);
5527
				ctxt->eip = ctxt->_eip;
5528
				ctxt->eflags &= ~X86_EFLAGS_RF;
5529 5530
				goto done;
			}
5531 5532 5533
		}
	}

5534 5535 5536
	if ((ctxt->src.type == OP_MEM) && !(ctxt->d & NoAccess)) {
		rc = segmented_read(ctxt, ctxt->src.addr.mem,
				    ctxt->src.valptr, ctxt->src.bytes);
5537
		if (rc != X86EMUL_CONTINUE)
5538
			goto done;
5539
		ctxt->src.orig_val64 = ctxt->src.val64;
5540 5541
	}

5542 5543 5544
	if (ctxt->src2.type == OP_MEM) {
		rc = segmented_read(ctxt, ctxt->src2.addr.mem,
				    &ctxt->src2.val, ctxt->src2.bytes);
5545 5546 5547 5548
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

5549
	if ((ctxt->d & DstMask) == ImplicitOps)
5550 5551 5552
		goto special_insn;


5553
	if ((ctxt->dst.type == OP_MEM) && !(ctxt->d & Mov)) {
5554
		/* optimisation - avoid slow emulated read if Mov */
5555 5556
		rc = segmented_read(ctxt, ctxt->dst.addr.mem,
				   &ctxt->dst.val, ctxt->dst.bytes);
5557
		if (rc != X86EMUL_CONTINUE) {
5558 5559
			if (!(ctxt->d & NoWrite) &&
			    rc == X86EMUL_PROPAGATE_FAULT &&
5560 5561
			    ctxt->exception.vector == PF_VECTOR)
				ctxt->exception.error_code |= PFERR_WRITE_MASK;
5562
			goto done;
5563
		}
5564
	}
5565 5566
	/* Copy full 64-bit value for CMPXCHG8B.  */
	ctxt->dst.orig_val64 = ctxt->dst.val64;
5567

5568 5569
special_insn:

5570
	if (unlikely(emul_flags & X86EMUL_GUEST_MASK) && (ctxt->d & Intercept)) {
5571
		rc = emulator_check_intercept(ctxt, ctxt->intercept,
5572
					      X86_ICPT_POST_MEMACCESS);
5573 5574 5575 5576
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}

5577
	if (ctxt->rep_prefix && (ctxt->d & String))
5578
		ctxt->eflags |= X86_EFLAGS_RF;
5579
	else
5580
		ctxt->eflags &= ~X86_EFLAGS_RF;
5581

5582
	if (ctxt->execute) {
5583 5584 5585 5586 5587 5588 5589
		if (ctxt->d & Fastop) {
			void (*fop)(struct fastop *) = (void *)ctxt->execute;
			rc = fastop(ctxt, fop);
			if (rc != X86EMUL_CONTINUE)
				goto done;
			goto writeback;
		}
5590
		rc = ctxt->execute(ctxt);
5591 5592 5593 5594 5595
		if (rc != X86EMUL_CONTINUE)
			goto done;
		goto writeback;
	}

B
Borislav Petkov 已提交
5596
	if (ctxt->opcode_len == 2)
A
Avi Kivity 已提交
5597
		goto twobyte_insn;
5598 5599
	else if (ctxt->opcode_len == 3)
		goto threebyte_insn;
A
Avi Kivity 已提交
5600

5601
	switch (ctxt->b) {
5602
	case 0x70 ... 0x7f: /* jcc (short) */
5603
		if (test_cc(ctxt->b, ctxt->eflags))
5604
			rc = jmp_rel(ctxt, ctxt->src.val);
5605
		break;
N
Nitin A Kamble 已提交
5606
	case 0x8d: /* lea r16/r32, m */
5607
		ctxt->dst.val = ctxt->src.addr.mem.ea;
N
Nitin A Kamble 已提交
5608
		break;
5609
	case 0x90 ... 0x97: /* nop / xchg reg, rax */
5610
		if (ctxt->dst.addr.reg == reg_rmw(ctxt, VCPU_REGS_RAX))
5611 5612 5613
			ctxt->dst.type = OP_NONE;
		else
			rc = em_xchg(ctxt);
5614
		break;
5615
	case 0x98: /* cbw/cwde/cdqe */
5616 5617 5618 5619
		switch (ctxt->op_bytes) {
		case 2: ctxt->dst.val = (s8)ctxt->dst.val; break;
		case 4: ctxt->dst.val = (s16)ctxt->dst.val; break;
		case 8: ctxt->dst.val = (s32)ctxt->dst.val; break;
5620 5621
		}
		break;
5622
	case 0xcc:		/* int3 */
5623 5624
		rc = emulate_int(ctxt, 3);
		break;
5625
	case 0xcd:		/* int n */
5626
		rc = emulate_int(ctxt, ctxt->src.val);
5627 5628
		break;
	case 0xce:		/* into */
5629
		if (ctxt->eflags & X86_EFLAGS_OF)
5630
			rc = emulate_int(ctxt, 4);
5631
		break;
5632
	case 0xe9: /* jmp rel */
5633
	case 0xeb: /* jmp rel short */
5634
		rc = jmp_rel(ctxt, ctxt->src.val);
5635
		ctxt->dst.type = OP_NONE; /* Disable writeback. */
5636
		break;
5637
	case 0xf4:              /* hlt */
5638
		ctxt->ops->halt(ctxt);
5639
		break;
5640 5641
	case 0xf5:	/* cmc */
		/* complement carry flag from eflags reg */
5642
		ctxt->eflags ^= X86_EFLAGS_CF;
5643 5644
		break;
	case 0xf8: /* clc */
5645
		ctxt->eflags &= ~X86_EFLAGS_CF;
5646
		break;
5647
	case 0xf9: /* stc */
5648
		ctxt->eflags |= X86_EFLAGS_CF;
5649
		break;
5650
	case 0xfc: /* cld */
5651
		ctxt->eflags &= ~X86_EFLAGS_DF;
5652 5653
		break;
	case 0xfd: /* std */
5654
		ctxt->eflags |= X86_EFLAGS_DF;
5655
		break;
5656 5657
	default:
		goto cannot_emulate;
A
Avi Kivity 已提交
5658
	}
5659

5660 5661 5662
	if (rc != X86EMUL_CONTINUE)
		goto done;

5663
writeback:
5664 5665 5666 5667 5668 5669
	if (ctxt->d & SrcWrite) {
		BUG_ON(ctxt->src.type == OP_MEM || ctxt->src.type == OP_MEM_STR);
		rc = writeback(ctxt, &ctxt->src);
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}
5670 5671 5672 5673 5674
	if (!(ctxt->d & NoWrite)) {
		rc = writeback(ctxt, &ctxt->dst);
		if (rc != X86EMUL_CONTINUE)
			goto done;
	}
5675

5676 5677 5678 5679
	/*
	 * restore dst type in case the decoding will be reused
	 * (happens for string instruction )
	 */
5680
	ctxt->dst.type = saved_dst_type;
5681

5682
	if ((ctxt->d & SrcMask) == SrcSI)
5683
		string_addr_inc(ctxt, VCPU_REGS_RSI, &ctxt->src);
5684

5685
	if ((ctxt->d & DstMask) == DstDI)
5686
		string_addr_inc(ctxt, VCPU_REGS_RDI, &ctxt->dst);
5687

5688
	if (ctxt->rep_prefix && (ctxt->d & String)) {
5689
		unsigned int count;
5690
		struct read_cache *r = &ctxt->io_read;
5691 5692 5693 5694
		if ((ctxt->d & SrcMask) == SrcSI)
			count = ctxt->src.count;
		else
			count = ctxt->dst.count;
5695
		register_address_increment(ctxt, VCPU_REGS_RCX, -count);
5696

5697 5698 5699 5700 5701
		if (!string_insn_completed(ctxt)) {
			/*
			 * Re-enter guest when pio read ahead buffer is empty
			 * or, if it is not used, after each 1024 iteration.
			 */
5702
			if ((r->end != 0 || reg_read(ctxt, VCPU_REGS_RCX) & 0x3ff) &&
5703 5704 5705 5706 5707 5708
			    (r->end == 0 || r->end != r->pos)) {
				/*
				 * Reset read cache. Usually happens before
				 * decode, but since instruction is restarted
				 * we have to do it here.
				 */
5709
				ctxt->mem_read.end = 0;
5710
				writeback_registers(ctxt);
5711 5712 5713
				return EMULATION_RESTART;
			}
			goto done; /* skip rip writeback */
5714
		}
5715
		ctxt->eflags &= ~X86_EFLAGS_RF;
5716
	}
5717

5718
	ctxt->eip = ctxt->_eip;
5719 5720

done:
5721 5722
	if (rc == X86EMUL_PROPAGATE_FAULT) {
		WARN_ON(ctxt->exception.vector > 0x1f);
5723
		ctxt->have_exception = true;
5724
	}
5725 5726 5727
	if (rc == X86EMUL_INTERCEPTED)
		return EMULATION_INTERCEPTED;

5728 5729 5730
	if (rc == X86EMUL_CONTINUE)
		writeback_registers(ctxt);

5731
	return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
A
Avi Kivity 已提交
5732 5733

twobyte_insn:
5734
	switch (ctxt->b) {
5735
	case 0x09:		/* wbinvd */
5736
		(ctxt->ops->wbinvd)(ctxt);
5737 5738
		break;
	case 0x08:		/* invd */
5739 5740
	case 0x0d:		/* GrpP (prefetch) */
	case 0x18:		/* Grp16 (prefetch/nop) */
P
Paolo Bonzini 已提交
5741
	case 0x1f:		/* nop */
5742 5743
		break;
	case 0x20: /* mov cr, reg */
5744
		ctxt->dst.val = ops->get_cr(ctxt, ctxt->modrm_reg);
5745
		break;
A
Avi Kivity 已提交
5746
	case 0x21: /* mov from dr to reg */
5747
		ops->get_dr(ctxt, ctxt->modrm_reg, &ctxt->dst.val);
A
Avi Kivity 已提交
5748 5749
		break;
	case 0x40 ... 0x4f:	/* cmov */
5750 5751
		if (test_cc(ctxt->b, ctxt->eflags))
			ctxt->dst.val = ctxt->src.val;
5752
		else if (ctxt->op_bytes != 4)
5753
			ctxt->dst.type = OP_NONE; /* no writeback */
A
Avi Kivity 已提交
5754
		break;
5755
	case 0x80 ... 0x8f: /* jnz rel, etc*/
5756
		if (test_cc(ctxt->b, ctxt->eflags))
5757
			rc = jmp_rel(ctxt, ctxt->src.val);
5758
		break;
5759
	case 0x90 ... 0x9f:     /* setcc r/m8 */
5760
		ctxt->dst.val = test_cc(ctxt->b, ctxt->eflags);
5761
		break;
A
Avi Kivity 已提交
5762
	case 0xb6 ... 0xb7:	/* movzx */
5763
		ctxt->dst.bytes = ctxt->op_bytes;
5764
		ctxt->dst.val = (ctxt->src.bytes == 1) ? (u8) ctxt->src.val
5765
						       : (u16) ctxt->src.val;
A
Avi Kivity 已提交
5766 5767
		break;
	case 0xbe ... 0xbf:	/* movsx */
5768
		ctxt->dst.bytes = ctxt->op_bytes;
5769
		ctxt->dst.val = (ctxt->src.bytes == 1) ? (s8) ctxt->src.val :
5770
							(s16) ctxt->src.val;
A
Avi Kivity 已提交
5771
		break;
5772 5773
	default:
		goto cannot_emulate;
A
Avi Kivity 已提交
5774
	}
5775

5776 5777
threebyte_insn:

5778 5779 5780
	if (rc != X86EMUL_CONTINUE)
		goto done;

A
Avi Kivity 已提交
5781 5782 5783
	goto writeback;

cannot_emulate:
5784
	return EMULATION_FAILED;
A
Avi Kivity 已提交
5785
}
5786 5787 5788 5789 5790 5791 5792 5793 5794 5795

void emulator_invalidate_register_cache(struct x86_emulate_ctxt *ctxt)
{
	invalidate_registers(ctxt);
}

void emulator_writeback_register_cache(struct x86_emulate_ctxt *ctxt)
{
	writeback_registers(ctxt);
}
5796 5797 5798 5799 5800 5801 5802 5803 5804 5805 5806

bool emulator_can_use_gpa(struct x86_emulate_ctxt *ctxt)
{
	if (ctxt->rep_prefix && (ctxt->d & String))
		return false;

	if (ctxt->d & TwoMemOp)
		return false;

	return true;
}