i915_drv.h 122.8 KB
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/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#ifndef _I915_DRV_H_
#define _I915_DRV_H_

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#include <uapi/drm/i915_drm.h>
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#include <uapi/drm/drm_fourcc.h>
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#include <linux/io-mapping.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/backlight.h>
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#include <linux/hash.h>
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#include <linux/intel-iommu.h>
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#include <linux/kref.h>
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#include <linux/perf_event.h>
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#include <linux/pm_qos.h>
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#include <linux/reservation.h>
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#include <linux/shmem_fs.h>

#include <drm/drmP.h>
#include <drm/intel-gtt.h>
#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
#include <drm/drm_gem.h>
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#include <drm/drm_auth.h>
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#include <drm/drm_cache.h>
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#include "i915_params.h"
#include "i915_reg.h"
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#include "i915_utils.h"
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#include "intel_bios.h"
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#include "intel_device_info.h"
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#include "intel_display.h"
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#include "intel_dpll_mgr.h"
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#include "intel_lrc.h"
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#include "intel_opregion.h"
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#include "intel_ringbuffer.h"
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#include "intel_uncore.h"
#include "intel_uc.h"
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#include "i915_gem.h"
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#include "i915_gem_context.h"
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#include "i915_gem_fence_reg.h"
#include "i915_gem_object.h"
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#include "i915_gem_gtt.h"
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#include "i915_gem_request.h"
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#include "i915_gem_timeline.h"
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#include "i915_vma.h"

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#include "intel_gvt.h"

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/* General customization:
 */

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
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#define DRIVER_DATE		"20171222"
#define DRIVER_TIMESTAMP	1513971710
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/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 * which may not necessarily be a user visible problem.  This will either
 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 * enable distros and users to tailor their preferred amount of i915 abrt
 * spam.
 */
#define I915_STATE_WARN(condition, format...) ({			\
	int __ret_warn_on = !!(condition);				\
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	if (unlikely(__ret_warn_on))					\
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		if (!WARN(i915_modparams.verbose_state_checks, format))	\
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			DRM_ERROR(format);				\
	unlikely(__ret_warn_on);					\
})

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#define I915_STATE_WARN_ON(x)						\
	I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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bool __i915_inject_load_failure(const char *func, int line);
#define i915_inject_load_failure() \
	__i915_inject_load_failure(__func__, __LINE__)

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typedef struct {
	uint32_t val;
} uint_fixed_16_16_t;

#define FP_16_16_MAX ({ \
	uint_fixed_16_16_t fp; \
	fp.val = UINT_MAX; \
	fp; \
})

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static inline bool is_fixed16_zero(uint_fixed_16_16_t val)
{
	if (val.val == 0)
		return true;
	return false;
}

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static inline uint_fixed_16_16_t u32_to_fixed16(uint32_t val)
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{
	uint_fixed_16_16_t fp;

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	WARN_ON(val > U16_MAX);
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	fp.val = val << 16;
	return fp;
}

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static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp)
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{
	return DIV_ROUND_UP(fp.val, 1 << 16);
}

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static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp)
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{
	return fp.val >> 16;
}

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static inline uint_fixed_16_16_t min_fixed16(uint_fixed_16_16_t min1,
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						 uint_fixed_16_16_t min2)
{
	uint_fixed_16_16_t min;

	min.val = min(min1.val, min2.val);
	return min;
}

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static inline uint_fixed_16_16_t max_fixed16(uint_fixed_16_16_t max1,
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						 uint_fixed_16_16_t max2)
{
	uint_fixed_16_16_t max;

	max.val = max(max1.val, max2.val);
	return max;
}

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static inline uint_fixed_16_16_t clamp_u64_to_fixed16(uint64_t val)
{
	uint_fixed_16_16_t fp;
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	WARN_ON(val > U32_MAX);
	fp.val = (uint32_t) val;
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	return fp;
}

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static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val,
					    uint_fixed_16_16_t d)
{
	return DIV_ROUND_UP(val.val, d.val);
}

static inline uint32_t mul_round_up_u32_fixed16(uint32_t val,
						uint_fixed_16_16_t mul)
{
	uint64_t intermediate_val;

	intermediate_val = (uint64_t) val * mul.val;
	intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16);
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	WARN_ON(intermediate_val > U32_MAX);
	return (uint32_t) intermediate_val;
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}

static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val,
					     uint_fixed_16_16_t mul)
{
	uint64_t intermediate_val;

	intermediate_val = (uint64_t) val.val * mul.val;
	intermediate_val = intermediate_val >> 16;
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	return clamp_u64_to_fixed16(intermediate_val);
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}

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static inline uint_fixed_16_16_t div_fixed16(uint32_t val, uint32_t d)
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{
	uint64_t interm_val;

	interm_val = (uint64_t)val << 16;
	interm_val = DIV_ROUND_UP_ULL(interm_val, d);
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	return clamp_u64_to_fixed16(interm_val);
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}

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static inline uint32_t div_round_up_u32_fixed16(uint32_t val,
						uint_fixed_16_16_t d)
{
	uint64_t interm_val;

	interm_val = (uint64_t)val << 16;
	interm_val = DIV_ROUND_UP_ULL(interm_val, d.val);
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	WARN_ON(interm_val > U32_MAX);
	return (uint32_t) interm_val;
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}

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static inline uint_fixed_16_16_t mul_u32_fixed16(uint32_t val,
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						     uint_fixed_16_16_t mul)
{
	uint64_t intermediate_val;

	intermediate_val = (uint64_t) val * mul.val;
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	return clamp_u64_to_fixed16(intermediate_val);
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}

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static inline uint_fixed_16_16_t add_fixed16(uint_fixed_16_16_t add1,
					     uint_fixed_16_16_t add2)
{
	uint64_t interm_sum;

	interm_sum = (uint64_t) add1.val + add2.val;
	return clamp_u64_to_fixed16(interm_sum);
}

static inline uint_fixed_16_16_t add_fixed16_u32(uint_fixed_16_16_t add1,
						 uint32_t add2)
{
	uint64_t interm_sum;
	uint_fixed_16_16_t interm_add2 = u32_to_fixed16(add2);

	interm_sum = (uint64_t) add1.val + interm_add2.val;
	return clamp_u64_to_fixed16(interm_sum);
}

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enum hpd_pin {
	HPD_NONE = 0,
	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
	HPD_CRT,
	HPD_SDVO_B,
	HPD_SDVO_C,
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	HPD_PORT_A,
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	HPD_PORT_B,
	HPD_PORT_C,
	HPD_PORT_D,
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	HPD_PORT_E,
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	HPD_NUM_PINS
};

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#define for_each_hpd_pin(__pin) \
	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)

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#define HPD_STORM_DEFAULT_THRESHOLD 5

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struct i915_hotplug {
	struct work_struct hotplug_work;

	struct {
		unsigned long last_jiffies;
		int count;
		enum {
			HPD_ENABLED = 0,
			HPD_DISABLED = 1,
			HPD_MARK_DISABLED = 2
		} state;
	} stats[HPD_NUM_PINS];
	u32 event_bits;
	struct delayed_work reenable_work;

	struct intel_digital_port *irq_port[I915_MAX_PORTS];
	u32 long_port_mask;
	u32 short_port_mask;
	struct work_struct dig_port_work;

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	struct work_struct poll_init_work;
	bool poll_enabled;

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	unsigned int hpd_storm_threshold;

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	/*
	 * if we get a HPD irq from DP and a HPD irq from non-DP
	 * the non-DP HPD could block the workqueue on a mode config
	 * mutex getting, that userspace may have taken. However
	 * userspace is waiting on the DP workqueue to run which is
	 * blocked behind the non-DP one.
	 */
	struct workqueue_struct *dp_wq;
};

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#define I915_GEM_GPU_DOMAINS \
	(I915_GEM_DOMAIN_RENDER | \
	 I915_GEM_DOMAIN_SAMPLER | \
	 I915_GEM_DOMAIN_COMMAND | \
	 I915_GEM_DOMAIN_INSTRUCTION | \
	 I915_GEM_DOMAIN_VERTEX)
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struct drm_i915_private;
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struct i915_mm_struct;
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struct i915_mmu_object;
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struct drm_i915_file_private {
	struct drm_i915_private *dev_priv;
	struct drm_file *file;

	struct {
		spinlock_t lock;
		struct list_head request_list;
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/* 20ms is a fairly arbitrary limit (greater than the average frame time)
 * chosen to prevent the CPU getting more than a frame ahead of the GPU
 * (when using lax throttling for the frontbuffer). We also use it to
 * offer free GPU waitboosts for severely congested workloads.
 */
#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
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	} mm;
	struct idr context_idr;

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	struct intel_rps_client {
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		atomic_t boosts;
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	} rps_client;
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	unsigned int bsd_engine;
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/* Client can have a maximum of 3 contexts banned before
 * it is denied of creating new contexts. As one context
 * ban needs 4 consecutive hangs, and more if there is
 * progress in between, this is a last resort stop gap measure
 * to limit the badly behaving clients access to gpu.
 */
#define I915_MAX_CLIENT_CONTEXT_BANS 3
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	atomic_t context_bans;
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};

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/* Interface history:
 *
 * 1.1: Original.
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 * 1.2: Add Power Management
 * 1.3: Add vblank support
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 * 1.4: Fix cmdbuffer path, add heap destroy
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 * 1.5: Add vblank pipe configuration
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 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
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 */
#define DRIVER_MAJOR		1
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#define DRIVER_MINOR		6
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#define DRIVER_PATCHLEVEL	0

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struct intel_overlay;
struct intel_overlay_error_state;

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struct sdvo_device_mapping {
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	u8 initialized;
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	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
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	u8 i2c_pin;
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	u8 ddc_pin;
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};

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struct intel_connector;
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struct intel_encoder;
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struct intel_atomic_state;
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struct intel_crtc_state;
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struct intel_initial_plane_config;
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struct intel_crtc;
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struct intel_limit;
struct dpll;
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struct intel_cdclk_state;
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struct drm_i915_display_funcs {
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	void (*get_cdclk)(struct drm_i915_private *dev_priv,
			  struct intel_cdclk_state *cdclk_state);
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	void (*set_cdclk)(struct drm_i915_private *dev_priv,
			  const struct intel_cdclk_state *cdclk_state);
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	int (*get_fifo_size)(struct drm_i915_private *dev_priv,
			     enum i9xx_plane_id i9xx_plane);
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	int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
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	int (*compute_intermediate_wm)(struct drm_device *dev,
				       struct intel_crtc *intel_crtc,
				       struct intel_crtc_state *newstate);
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	void (*initial_watermarks)(struct intel_atomic_state *state,
				   struct intel_crtc_state *cstate);
	void (*atomic_update_watermarks)(struct intel_atomic_state *state,
					 struct intel_crtc_state *cstate);
	void (*optimize_watermarks)(struct intel_atomic_state *state,
				    struct intel_crtc_state *cstate);
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	int (*compute_global_watermarks)(struct drm_atomic_state *state);
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	void (*update_wm)(struct intel_crtc *crtc);
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	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
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	/* Returns the active state of the crtc, and if the crtc is active,
	 * fills out the pipe-config with the hw state. */
	bool (*get_pipe_config)(struct intel_crtc *,
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				struct intel_crtc_state *);
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	void (*get_initial_plane_config)(struct intel_crtc *,
					 struct intel_initial_plane_config *);
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	int (*crtc_compute_clock)(struct intel_crtc *crtc,
				  struct intel_crtc_state *crtc_state);
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	void (*crtc_enable)(struct intel_crtc_state *pipe_config,
			    struct drm_atomic_state *old_state);
	void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
			     struct drm_atomic_state *old_state);
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	void (*update_crtcs)(struct drm_atomic_state *state);
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	void (*audio_codec_enable)(struct intel_encoder *encoder,
				   const struct intel_crtc_state *crtc_state,
				   const struct drm_connector_state *conn_state);
	void (*audio_codec_disable)(struct intel_encoder *encoder,
				    const struct intel_crtc_state *old_crtc_state,
				    const struct drm_connector_state *old_conn_state);
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	void (*fdi_link_train)(struct intel_crtc *crtc,
			       const struct intel_crtc_state *crtc_state);
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	void (*init_clock_gating)(struct drm_i915_private *dev_priv);
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	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
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	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
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	void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
	void (*load_luts)(struct drm_crtc_state *crtc_state);
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};

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#define CSR_VERSION(major, minor)	((major) << 16 | (minor))
#define CSR_VERSION_MAJOR(version)	((version) >> 16)
#define CSR_VERSION_MINOR(version)	((version) & 0xffff)

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struct intel_csr {
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	struct work_struct work;
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	const char *fw_path;
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	uint32_t *dmc_payload;
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	uint32_t dmc_fw_size;
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	uint32_t version;
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	uint32_t mmio_count;
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	i915_reg_t mmioaddr[8];
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	uint32_t mmiodata[8];
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	uint32_t dc_state;
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	uint32_t allowed_dc_mask;
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};

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struct intel_display_error_state;

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struct i915_gpu_state {
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	struct kref ref;
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	ktime_t time;
	ktime_t boottime;
	ktime_t uptime;
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	struct drm_i915_private *i915;

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	char error_msg[128];
	bool simulated;
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	bool awake;
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	bool wakelock;
	bool suspended;
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	int iommu;
	u32 reset_count;
	u32 suspend_count;
	struct intel_device_info device_info;
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	struct i915_params params;
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	struct i915_error_uc {
		struct intel_uc_fw guc_fw;
		struct intel_uc_fw huc_fw;
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		struct drm_i915_error_object *guc_log;
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	} uc;

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	/* Generic register state */
	u32 eir;
	u32 pgtbl_er;
	u32 ier;
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	u32 gtier[4], ngtier;
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	u32 ccid;
	u32 derrmr;
	u32 forcewake;
	u32 error; /* gen6+ */
	u32 err_int; /* gen7 */
	u32 fault_data0; /* gen8, gen9 */
	u32 fault_data1; /* gen8, gen9 */
	u32 done_reg;
	u32 gac_eco;
	u32 gam_ecochk;
	u32 gab_ctl;
	u32 gfx_mode;
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	u32 nfence;
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	u64 fence[I915_MAX_NUM_FENCES];
	struct intel_overlay_error_state *overlay;
	struct intel_display_error_state *display;

	struct drm_i915_error_engine {
		int engine_id;
		/* Software tracked state */
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		bool idle;
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		bool waiting;
		int num_waiters;
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		unsigned long hangcheck_timestamp;
		bool hangcheck_stalled;
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		enum intel_engine_hangcheck_action hangcheck_action;
		struct i915_address_space *vm;
		int num_requests;
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		u32 reset_count;
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		/* position of active request inside the ring */
		u32 rq_head, rq_post, rq_tail;

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		/* our own tracking of ring head and tail */
		u32 cpu_ring_head;
		u32 cpu_ring_tail;

		u32 last_seqno;

		/* Register state */
		u32 start;
		u32 tail;
		u32 head;
		u32 ctl;
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		u32 mode;
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		u32 hws;
		u32 ipeir;
		u32 ipehr;
		u32 bbstate;
		u32 instpm;
		u32 instps;
		u32 seqno;
		u64 bbaddr;
		u64 acthd;
		u32 fault_reg;
		u64 faddr;
		u32 rc_psmi; /* sleep state */
		u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
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		struct intel_instdone instdone;
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		struct drm_i915_error_context {
			char comm[TASK_COMM_LEN];
			pid_t pid;
			u32 handle;
			u32 hw_id;
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			int priority;
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			int ban_score;
			int active;
			int guilty;
		} context;

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		struct drm_i915_error_object {
			u64 gtt_offset;
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			u64 gtt_size;
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			int page_count;
			int unused;
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			u32 *pages[0];
		} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;

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		struct drm_i915_error_object **user_bo;
		long user_bo_count;

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		struct drm_i915_error_object *wa_ctx;
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		struct drm_i915_error_object *default_state;
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		struct drm_i915_error_request {
			long jiffies;
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			pid_t pid;
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			u32 context;
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			int priority;
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			int ban_score;
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			u32 seqno;
			u32 head;
			u32 tail;
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		} *requests, execlist[EXECLIST_MAX_PORTS];
		unsigned int num_ports;
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		struct drm_i915_error_waiter {
			char comm[TASK_COMM_LEN];
			pid_t pid;
			u32 seqno;
		} *waiters;

		struct {
			u32 gfx_mode;
			union {
				u64 pdp[4];
				u32 pp_dir_base;
			};
		} vm_info;
	} engine[I915_NUM_ENGINES];

	struct drm_i915_error_buffer {
		u32 size;
		u32 name;
		u32 rseqno[I915_NUM_ENGINES], wseqno;
		u64 gtt_offset;
		u32 read_domains;
		u32 write_domain;
		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
		u32 tiling:2;
		u32 dirty:1;
		u32 purgeable:1;
		u32 userptr:1;
		s32 engine:4;
		u32 cache_level:3;
	} *active_bo[I915_NUM_ENGINES], *pinned_bo;
	u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
	struct i915_address_space *active_vm[I915_NUM_ENGINES];
};

616 617
enum i915_cache_level {
	I915_CACHE_NONE = 0,
618 619 620 621 622
	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
			      caches, eg sampler/render caches, and the
			      large Last-Level-Cache. LLC is coherent with
			      the CPU, but L3 is only visible to the GPU. */
623
	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
624 625
};

626 627
#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */

628 629 630 631 632
enum fb_op_origin {
	ORIGIN_GTT,
	ORIGIN_CPU,
	ORIGIN_CS,
	ORIGIN_FLIP,
633
	ORIGIN_DIRTYFB,
634 635
};

636
struct intel_fbc {
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Paulo Zanoni 已提交
637 638 639
	/* This is always the inner lock when overlapping with struct_mutex and
	 * it's the outer lock when overlapping with stolen_lock. */
	struct mutex lock;
B
Ben Widawsky 已提交
640
	unsigned threshold;
641 642
	unsigned int possible_framebuffer_bits;
	unsigned int busy_bits;
643
	unsigned int visible_pipes_mask;
644
	struct intel_crtc *crtc;
645

646
	struct drm_mm_node compressed_fb;
647 648
	struct drm_mm_node *compressed_llb;

649 650
	bool false_color;

651
	bool enabled;
652
	bool active;
653

654 655 656
	bool underrun_detected;
	struct work_struct underrun_work;

657 658 659 660 661
	/*
	 * Due to the atomic rules we can't access some structures without the
	 * appropriate locking, so we cache information here in order to avoid
	 * these problems.
	 */
662
	struct intel_fbc_state_cache {
663 664
		struct i915_vma *vma;

665 666 667 668 669 670 671 672 673 674
		struct {
			unsigned int mode_flags;
			uint32_t hsw_bdw_pixel_rate;
		} crtc;

		struct {
			unsigned int rotation;
			int src_w;
			int src_h;
			bool visible;
675 676 677 678 679 680 681 682
			/*
			 * Display surface base address adjustement for
			 * pageflips. Note that on gen4+ this only adjusts up
			 * to a tile, offsets within a tile are handled in
			 * the hw itself (with the TILEOFF register).
			 */
			int adjusted_x;
			int adjusted_y;
683 684

			int y;
685 686 687
		} plane;

		struct {
688
			const struct drm_format_info *format;
689 690 691 692
			unsigned int stride;
		} fb;
	} state_cache;

693 694 695 696 697 698 699
	/*
	 * This structure contains everything that's relevant to program the
	 * hardware registers. When we want to figure out if we need to disable
	 * and re-enable FBC for a new configuration we just check if there's
	 * something different in the struct. The genx_fbc_activate functions
	 * are supposed to read from it in order to program the registers.
	 */
700
	struct intel_fbc_reg_params {
701 702
		struct i915_vma *vma;

703 704
		struct {
			enum pipe pipe;
705
			enum i9xx_plane_id i9xx_plane;
706 707 708 709
			unsigned int fence_y_offset;
		} crtc;

		struct {
710
			const struct drm_format_info *format;
711 712 713 714
			unsigned int stride;
		} fb;

		int cfb_size;
715
		unsigned int gen9_wa_cfb_stride;
716 717
	} params;

718
	struct intel_fbc_work {
719
		bool scheduled;
720
		u32 scheduled_vblank;
721 722
		struct work_struct work;
	} work;
723

724
	const char *no_fbc_reason;
725 726
};

727
/*
728 729 730 731 732 733 734 735 736 737 738 739 740 741
 * HIGH_RR is the highest eDP panel refresh rate read from EDID
 * LOW_RR is the lowest eDP panel refresh rate found from EDID
 * parsing for same resolution.
 */
enum drrs_refresh_rate_type {
	DRRS_HIGH_RR,
	DRRS_LOW_RR,
	DRRS_MAX_RR, /* RR count */
};

enum drrs_support_type {
	DRRS_NOT_SUPPORTED = 0,
	STATIC_DRRS_SUPPORT = 1,
	SEAMLESS_DRRS_SUPPORT = 2
742 743
};

744
struct intel_dp;
745 746 747 748 749 750 751 752 753
struct i915_drrs {
	struct mutex mutex;
	struct delayed_work work;
	struct intel_dp *dp;
	unsigned busy_frontbuffer_bits;
	enum drrs_refresh_rate_type refresh_rate_type;
	enum drrs_support_type type;
};

R
Rodrigo Vivi 已提交
754
struct i915_psr {
755
	struct mutex lock;
R
Rodrigo Vivi 已提交
756
	bool sink_support;
757
	struct intel_dp *enabled;
758 759
	bool active;
	struct delayed_work work;
760
	unsigned busy_frontbuffer_bits;
761 762
	bool psr2_support;
	bool aux_frame_sync;
763
	bool link_standby;
764 765
	bool y_cord_support;
	bool colorimetry_support;
766
	bool alpm;
767

768 769
	void (*enable_source)(struct intel_dp *,
			      const struct intel_crtc_state *);
770 771
	void (*disable_source)(struct intel_dp *,
			       const struct intel_crtc_state *);
772
	void (*enable_sink)(struct intel_dp *);
R
Rodrigo Vivi 已提交
773
	void (*activate)(struct intel_dp *);
774
	void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *);
775
};
776

777
enum intel_pch {
778
	PCH_NONE = 0,	/* No PCH present */
779
	PCH_IBX,	/* Ibexpeak PCH */
780 781
	PCH_CPT,	/* Cougarpoint/Pantherpoint PCH */
	PCH_LPT,	/* Lynxpoint/Wildcatpoint PCH */
782
	PCH_SPT,        /* Sunrisepoint PCH */
783 784
	PCH_KBP,        /* Kaby Lake PCH */
	PCH_CNP,        /* Cannon Lake PCH */
785
	PCH_ICP,	/* Ice Lake PCH */
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Ben Widawsky 已提交
786
	PCH_NOP,
787 788
};

789 790 791 792 793
enum intel_sbi_destination {
	SBI_ICLK,
	SBI_MPHY,
};

794
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
795
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
796
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
797
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
798
#define QUIRK_INCREASE_T12_DELAY (1<<6)
799

800
struct intel_fbdev;
801
struct intel_fbc_work;
802

803 804
struct intel_gmbus {
	struct i2c_adapter adapter;
805
#define GMBUS_FORCE_BIT_RETRY (1U << 31)
806
	u32 force_bit;
807
	u32 reg0;
808
	i915_reg_t gpio_reg;
809
	struct i2c_algo_bit_data bit_algo;
810 811 812
	struct drm_i915_private *dev_priv;
};

813
struct i915_suspend_saved_registers {
814
	u32 saveDSPARB;
J
Jesse Barnes 已提交
815
	u32 saveFBC_CONTROL;
816 817
	u32 saveCACHE_MODE_0;
	u32 saveMI_ARB_STATE;
J
Jesse Barnes 已提交
818 819
	u32 saveSWF0[16];
	u32 saveSWF1[16];
820
	u32 saveSWF3[3];
821
	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
822
	u32 savePCH_PORT_HOTPLUG;
823
	u16 saveGCDGMBUS;
824
};
825

826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854 855 856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883
struct vlv_s0ix_state {
	/* GAM */
	u32 wr_watermark;
	u32 gfx_prio_ctrl;
	u32 arb_mode;
	u32 gfx_pend_tlb0;
	u32 gfx_pend_tlb1;
	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
	u32 media_max_req_count;
	u32 gfx_max_req_count;
	u32 render_hwsp;
	u32 ecochk;
	u32 bsd_hwsp;
	u32 blt_hwsp;
	u32 tlb_rd_addr;

	/* MBC */
	u32 g3dctl;
	u32 gsckgctl;
	u32 mbctl;

	/* GCP */
	u32 ucgctl1;
	u32 ucgctl3;
	u32 rcgctl1;
	u32 rcgctl2;
	u32 rstctl;
	u32 misccpctl;

	/* GPM */
	u32 gfxpause;
	u32 rpdeuhwtc;
	u32 rpdeuc;
	u32 ecobus;
	u32 pwrdwnupctl;
	u32 rp_down_timeout;
	u32 rp_deucsw;
	u32 rcubmabdtmr;
	u32 rcedata;
	u32 spare2gh;

	/* Display 1 CZ domain */
	u32 gt_imr;
	u32 gt_ier;
	u32 pm_imr;
	u32 pm_ier;
	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

	/* GT SA CZ domain */
	u32 tilectl;
	u32 gt_fifoctl;
	u32 gtlc_wake_ctrl;
	u32 gtlc_survive;
	u32 pmwgicz;

	/* Display 2 CZ domain */
	u32 gu_ctl0;
	u32 gu_ctl1;
884
	u32 pcbr;
885 886 887
	u32 clock_gate_dis2;
};

888
struct intel_rps_ei {
889
	ktime_t ktime;
890 891
	u32 render_c0;
	u32 media_c0;
892 893
};

894
struct intel_rps {
I
Imre Deak 已提交
895 896 897 898
	/*
	 * work, interrupts_enabled and pm_iir are protected by
	 * dev_priv->irq_lock
	 */
899
	struct work_struct work;
I
Imre Deak 已提交
900
	bool interrupts_enabled;
901
	u32 pm_iir;
902

903
	/* PM interrupt bits that should never be masked */
904
	u32 pm_intrmsk_mbz;
905

906 907 908 909 910 911 912 913 914 915 916 917 918 919 920
	/* Frequencies are stored in potentially platform dependent multiples.
	 * In other words, *_freq needs to be multiplied by X to be interesting.
	 * Soft limits are those which are used for the dynamic reclocking done
	 * by the driver (raise frequencies under heavy loads, and lower for
	 * lighter loads). Hard limits are those imposed by the hardware.
	 *
	 * A distinction is made for overclocking, which is never enabled by
	 * default, and is considered to be above the hard limit if it's
	 * possible at all.
	 */
	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
	u8 min_freq;		/* AKA RPn. Minimum frequency */
921
	u8 boost_freq;		/* Frequency to request when wait boosting */
922
	u8 idle_freq;		/* Frequency to request when we are idle */
923 924 925
	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
	u8 rp1_freq;		/* "less than" RP0 power/freqency */
	u8 rp0_freq;		/* Non-overclocked max frequency. */
926
	u16 gpll_ref_freq;	/* vlv/chv GPLL reference frequency */
927

928 929 930
	u8 up_threshold; /* Current %busy required to uplock */
	u8 down_threshold; /* Current %busy required to downclock */

931 932 933
	int last_adj;
	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;

934
	bool enabled;
935 936
	atomic_t num_waiters;
	atomic_t boosts;
937

938
	/* manual wa residency calculations */
939
	struct intel_rps_ei ei;
940 941
};

942 943 944 945 946 947 948 949
struct intel_rc6 {
	bool enabled;
};

struct intel_llc_pstate {
	bool enabled;
};

950 951
struct intel_gen6_power_mgmt {
	struct intel_rps rps;
952 953
	struct intel_rc6 rc6;
	struct intel_llc_pstate llc_pstate;
954 955
};

D
Daniel Vetter 已提交
956 957 958
/* defined intel_pm.c */
extern spinlock_t mchdev_lock;

959 960 961 962 963 964 965 966 967 968 969
struct intel_ilk_power_mgmt {
	u8 cur_delay;
	u8 min_delay;
	u8 max_delay;
	u8 fmax;
	u8 fstart;

	u64 last_count1;
	unsigned long last_time1;
	unsigned long chipset_power;
	u64 last_count2;
970
	u64 last_time2;
971 972 973 974 975 976 977
	unsigned long gfx_power;
	u8 corr;

	int c_m;
	int r_t;
};

978 979 980 981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007
struct drm_i915_private;
struct i915_power_well;

struct i915_power_well_ops {
	/*
	 * Synchronize the well's hw state to match the current sw state, for
	 * example enable/disable it based on the current refcount. Called
	 * during driver init and resume time, possibly after first calling
	 * the enable/disable handlers.
	 */
	void (*sync_hw)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/*
	 * Enable the well and resources that depend on it (for example
	 * interrupts located on the well). Called after the 0->1 refcount
	 * transition.
	 */
	void (*enable)(struct drm_i915_private *dev_priv,
		       struct i915_power_well *power_well);
	/*
	 * Disable the well and resources that depend on it. Called after
	 * the 1->0 refcount transition.
	 */
	void (*disable)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/* Returns the hw enabled state. */
	bool (*is_enabled)(struct drm_i915_private *dev_priv,
			   struct i915_power_well *power_well);
};

1008 1009
/* Power well structure for haswell */
struct i915_power_well {
1010
	const char *name;
1011
	bool always_on;
1012 1013
	/* power well enable/disable usage count */
	int count;
1014 1015
	/* cached hw enabled state */
	bool hw_enabled;
1016
	u64 domains;
1017
	/* unique identifier for this power well */
I
Imre Deak 已提交
1018
	enum i915_power_well_id id;
1019 1020 1021 1022
	/*
	 * Arbitraty data associated with this power well. Platform and power
	 * well specific.
	 */
1023 1024 1025 1026
	union {
		struct {
			enum dpio_phy phy;
		} bxt;
1027 1028 1029 1030 1031
		struct {
			/* Mask of pipes whose IRQ logic is backed by the pw */
			u8 irq_pipe_mask;
			/* The pw is backing the VGA functionality */
			bool has_vga:1;
1032
			bool has_fuses:1;
1033
		} hsw;
1034
	};
1035
	const struct i915_power_well_ops *ops;
1036 1037
};

1038
struct i915_power_domains {
1039 1040 1041 1042 1043
	/*
	 * Power wells needed for initialization at driver init and suspend
	 * time are on. They are kept on until after the first modeset.
	 */
	bool init_power_on;
1044
	bool initializing;
1045
	int power_well_count;
1046

1047
	struct mutex lock;
1048
	int domain_use_count[POWER_DOMAIN_NUM];
1049
	struct i915_power_well *power_wells;
1050 1051
};

1052
#define MAX_L3_SLICES 2
1053
struct intel_l3_parity {
1054
	u32 *remap_info[MAX_L3_SLICES];
1055
	struct work_struct error_work;
1056
	int which_slice;
1057 1058
};

1059 1060 1061
struct i915_gem_mm {
	/** Memory allocator for GTT stolen memory */
	struct drm_mm stolen;
1062 1063 1064 1065
	/** Protects the usage of the GTT stolen memory allocator. This is
	 * always the inner lock when overlapping with struct_mutex. */
	struct mutex stolen_lock;

1066 1067 1068
	/* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
	spinlock_t obj_lock;

1069 1070 1071 1072 1073
	/** List of all objects in gtt_space. Used to restore gtt
	 * mappings on resume */
	struct list_head bound_list;
	/**
	 * List of objects which are not bound to the GTT (thus
1074 1075
	 * are idle and not used by the GPU). These objects may or may
	 * not actually have any pages attached.
1076 1077 1078
	 */
	struct list_head unbound_list;

1079 1080 1081 1082 1083
	/** List of all objects in gtt_space, currently mmaped by userspace.
	 * All objects within this list must also be on bound_list.
	 */
	struct list_head userfault_list;

1084 1085 1086 1087 1088
	/**
	 * List of objects which are pending destruction.
	 */
	struct llist_head free_list;
	struct work_struct free_work;
1089
	spinlock_t free_lock;
1090

1091 1092 1093 1094 1095
	/**
	 * Small stash of WC pages
	 */
	struct pagevec wc_stash;

M
Matthew Auld 已提交
1096 1097 1098 1099 1100
	/**
	 * tmpfs instance used for shmem backed objects
	 */
	struct vfsmount *gemfs;

1101 1102 1103
	/** PPGTT used for aliasing the PPGTT with the GTT */
	struct i915_hw_ppgtt *aliasing_ppgtt;

1104
	struct notifier_block oom_notifier;
1105
	struct notifier_block vmap_notifier;
1106
	struct shrinker shrinker;
1107 1108 1109 1110

	/** LRU list of objects with fence regs on them. */
	struct list_head fence_list;

1111 1112 1113 1114 1115 1116 1117
	/**
	 * Workqueue to fault in userptr pages, flushed by the execbuf
	 * when required but otherwise left to userspace to try again
	 * on EAGAIN.
	 */
	struct workqueue_struct *userptr_wq;

1118 1119
	u64 unordered_timeline;

1120
	/* the indicator for dispatch video commands on two BSD rings */
1121
	atomic_t bsd_engine_dispatch_index;
1122

1123 1124 1125 1126 1127 1128
	/** Bit 6 swizzling required for X tiling */
	uint32_t bit_6_swizzle_x;
	/** Bit 6 swizzling required for Y tiling */
	uint32_t bit_6_swizzle_y;

	/* accounting, useful for userland debugging */
1129
	spinlock_t object_stat_lock;
1130
	u64 object_memory;
1131 1132 1133
	u32 object_count;
};

1134
struct drm_i915_error_state_buf {
1135
	struct drm_i915_private *i915;
1136 1137 1138 1139 1140 1141 1142 1143
	unsigned bytes;
	unsigned size;
	int err;
	u8 *buf;
	loff_t start;
	loff_t pos;
};

1144 1145
#define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */

1146 1147 1148
#define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
#define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */

1149 1150 1151
#define I915_ENGINE_DEAD_TIMEOUT  (4 * HZ)  /* Seqno, head and subunits dead */
#define I915_SEQNO_DEAD_TIMEOUT   (12 * HZ) /* Seqno dead with active head */

1152 1153 1154 1155
struct i915_gpu_error {
	/* For hangcheck timer */
#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1156

1157
	struct delayed_work hangcheck_work;
1158 1159 1160 1161

	/* For reset and error_state handling. */
	spinlock_t lock;
	/* Protected by the above dev->gpu_error.lock. */
1162
	struct i915_gpu_state *first_error;
1163

1164 1165
	atomic_t pending_fb_pin;

1166 1167
	unsigned long missed_irq_rings;

1168
	/**
M
Mika Kuoppala 已提交
1169
	 * State variable controlling the reset flow and count
1170
	 *
M
Mika Kuoppala 已提交
1171
	 * This is a counter which gets incremented when reset is triggered,
1172
	 *
1173
	 * Before the reset commences, the I915_RESET_BACKOFF bit is set
1174 1175
	 * meaning that any waiters holding onto the struct_mutex should
	 * relinquish the lock immediately in order for the reset to start.
M
Mika Kuoppala 已提交
1176 1177 1178 1179 1180 1181 1182 1183 1184
	 *
	 * If reset is not completed succesfully, the I915_WEDGE bit is
	 * set meaning that hardware is terminally sour and there is no
	 * recovery. All waiters on the reset_queue will be woken when
	 * that happens.
	 *
	 * This counter is used by the wait_seqno code to notice that reset
	 * event happened and it needs to restart the entire ioctl (since most
	 * likely the seqno it waited for won't ever signal anytime soon).
1185 1186 1187 1188
	 *
	 * This is important for lock-free wait paths, where no contended lock
	 * naturally enforces the correct ordering between the bail-out of the
	 * waiter and the gpu reset work code.
1189
	 */
1190
	unsigned long reset_count;
1191

1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210
	/**
	 * flags: Control various stages of the GPU reset
	 *
	 * #I915_RESET_BACKOFF - When we start a reset, we want to stop any
	 * other users acquiring the struct_mutex. To do this we set the
	 * #I915_RESET_BACKOFF bit in the error flags when we detect a reset
	 * and then check for that bit before acquiring the struct_mutex (in
	 * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a
	 * secondary role in preventing two concurrent global reset attempts.
	 *
	 * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the
	 * struct_mutex. We try to acquire the struct_mutex in the reset worker,
	 * but it may be held by some long running waiter (that we cannot
	 * interrupt without causing trouble). Once we are ready to do the GPU
	 * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If
	 * they already hold the struct_mutex and want to participate they can
	 * inspect the bit and do the reset directly, otherwise the worker
	 * waits for the struct_mutex.
	 *
1211 1212 1213 1214 1215 1216
	 * #I915_RESET_ENGINE[num_engines] - Since the driver doesn't need to
	 * acquire the struct_mutex to reset an engine, we need an explicit
	 * flag to prevent two concurrent reset attempts in the same engine.
	 * As the number of engines continues to grow, allocate the flags from
	 * the most significant bits.
	 *
1217 1218 1219 1220 1221
	 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
	 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
	 * i915_gem_request_alloc(), this bit is checked and the sequence
	 * aborted (with -EIO reported to userspace) if set.
	 */
1222
	unsigned long flags;
1223 1224
#define I915_RESET_BACKOFF	0
#define I915_RESET_HANDOFF	1
1225
#define I915_RESET_MODESET	2
1226
#define I915_WEDGED		(BITS_PER_LONG - 1)
1227
#define I915_RESET_ENGINE	(I915_WEDGED - I915_NUM_ENGINES)
1228

1229 1230 1231
	/** Number of times an engine has been reset */
	u32 reset_engine_count[I915_NUM_ENGINES];

1232 1233 1234 1235 1236 1237
	/**
	 * Waitqueue to signal when a hang is detected. Used to for waiters
	 * to release the struct_mutex for the reset to procede.
	 */
	wait_queue_head_t wait_queue;

1238 1239 1240 1241 1242
	/**
	 * Waitqueue to signal when the reset has completed. Used by clients
	 * that wait for dev_priv->mm.wedged to settle.
	 */
	wait_queue_head_t reset_queue;
1243

1244
	/* For missed irq/seqno simulation. */
1245
	unsigned long test_irq_rings;
1246 1247
};

1248 1249 1250 1251 1252 1253
enum modeset_restore {
	MODESET_ON_LID_OPEN,
	MODESET_DONE,
	MODESET_SUSPENDED,
};

1254 1255 1256 1257 1258
#define DP_AUX_A 0x40
#define DP_AUX_B 0x10
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30

X
Xiong Zhang 已提交
1259 1260 1261 1262
#define DDC_PIN_B  0x05
#define DDC_PIN_C  0x04
#define DDC_PIN_D  0x06

1263
struct ddi_vbt_port_info {
1264 1265
	int max_tmds_clock;

1266 1267 1268 1269 1270 1271
	/*
	 * This is an index in the HDMI/DVI DDI buffer translation table.
	 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
	 * populate this field.
	 */
#define HDMI_LEVEL_SHIFT_UNKNOWN	0xff
1272
	uint8_t hdmi_level_shift;
1273 1274 1275 1276

	uint8_t supports_dvi:1;
	uint8_t supports_hdmi:1;
	uint8_t supports_dp:1;
1277
	uint8_t supports_edp:1;
1278 1279

	uint8_t alternate_aux_channel;
X
Xiong Zhang 已提交
1280
	uint8_t alternate_ddc_pin;
1281 1282 1283

	uint8_t dp_boost_level;
	uint8_t hdmi_boost_level;
1284 1285
};

R
Rodrigo Vivi 已提交
1286 1287 1288 1289 1290
enum psr_lines_to_wait {
	PSR_0_LINES_TO_WAIT = 0,
	PSR_1_LINE_TO_WAIT,
	PSR_4_LINES_TO_WAIT,
	PSR_8_LINES_TO_WAIT
1291 1292
};

1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304
struct intel_vbt_data {
	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits */
	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int lvds_vbt:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
	unsigned int display_clock_mode:1;
	unsigned int fdi_rx_polarity_inverted:1;
1305
	unsigned int panel_type:4;
1306 1307 1308
	int lvds_ssc_freq;
	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

1309 1310
	enum drrs_support_type drrs_type;

1311 1312 1313 1314 1315
	struct {
		int rate;
		int lanes;
		int preemphasis;
		int vswing;
1316
		bool low_vswing;
1317 1318 1319 1320 1321
		bool initialized;
		bool support;
		int bpp;
		struct edp_power_seq pps;
	} edp;
1322

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Rodrigo Vivi 已提交
1323 1324 1325 1326 1327 1328 1329 1330 1331
	struct {
		bool full_link;
		bool require_aux_wakeup;
		int idle_frames;
		enum psr_lines_to_wait lines_to_wait;
		int tp1_wakeup_time;
		int tp2_tp3_wakeup_time;
	} psr;

1332 1333
	struct {
		u16 pwm_freq_hz;
1334
		bool present;
1335
		bool active_low_pwm;
1336
		u8 min_brightness;	/* min_brightness/255 of max */
1337
		u8 controller;		/* brightness controller number */
1338
		enum intel_backlight_type type;
1339 1340
	} backlight;

1341 1342 1343
	/* MIPI DSI */
	struct {
		u16 panel_id;
1344 1345
		struct mipi_config *config;
		struct mipi_pps_data *pps;
1346 1347
		u16 bl_ports;
		u16 cabc_ports;
1348 1349 1350
		u8 seq_version;
		u32 size;
		u8 *data;
1351
		const u8 *sequence[MIPI_SEQ_MAX];
1352 1353
	} dsi;

1354 1355 1356
	int crt_ddc_pin;

	int child_dev_num;
1357
	struct child_device_config *child_dev;
1358 1359

	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1360
	struct sdvo_device_mapping sdvo_mappings[2];
1361 1362
};

1363 1364 1365 1366 1367
enum intel_ddb_partitioning {
	INTEL_DDB_PART_1_2,
	INTEL_DDB_PART_5_6, /* IVB+ */
};

1368 1369 1370 1371 1372 1373 1374 1375
struct intel_wm_level {
	bool enable;
	uint32_t pri_val;
	uint32_t spr_val;
	uint32_t cur_val;
	uint32_t fbc_val;
};

1376
struct ilk_wm_values {
1377 1378 1379 1380 1381 1382 1383 1384
	uint32_t wm_pipe[3];
	uint32_t wm_lp[3];
	uint32_t wm_lp_spr[3];
	uint32_t wm_linetime[3];
	bool enable_fbc_wm;
	enum intel_ddb_partitioning partitioning;
};

1385
struct g4x_pipe_wm {
1386
	uint16_t plane[I915_MAX_PLANES];
1387
	uint16_t fbc;
1388
};
1389

1390
struct g4x_sr_wm {
1391
	uint16_t plane;
1392
	uint16_t cursor;
1393
	uint16_t fbc;
1394 1395 1396 1397
};

struct vlv_wm_ddl_values {
	uint8_t plane[I915_MAX_PLANES];
1398
};
1399

1400
struct vlv_wm_values {
1401 1402
	struct g4x_pipe_wm pipe[3];
	struct g4x_sr_wm sr;
1403
	struct vlv_wm_ddl_values ddl[3];
1404 1405
	uint8_t level;
	bool cxsr;
1406 1407
};

1408 1409 1410 1411 1412 1413 1414 1415 1416
struct g4x_wm_values {
	struct g4x_pipe_wm pipe[2];
	struct g4x_sr_wm sr;
	struct g4x_sr_wm hpll;
	bool cxsr;
	bool hpll_en;
	bool fbc_en;
};

1417
struct skl_ddb_entry {
1418
	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
1419 1420 1421 1422
};

static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
{
1423
	return entry->end - entry->start;
1424 1425
}

1426 1427 1428 1429 1430 1431 1432 1433 1434
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
				       const struct skl_ddb_entry *e2)
{
	if (e1->start == e2->start && e1->end == e2->end)
		return true;

	return false;
}

1435
struct skl_ddb_allocation {
1436
	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1437
	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1438 1439
};

1440
struct skl_wm_values {
1441
	unsigned dirty_pipes;
1442
	struct skl_ddb_allocation ddb;
1443 1444 1445
};

struct skl_wm_level {
L
Lyude 已提交
1446 1447 1448
	bool plane_en;
	uint16_t plane_res_b;
	uint8_t plane_res_l;
1449 1450
};

1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464
/* Stores plane specific WM parameters */
struct skl_wm_params {
	bool x_tiled, y_tiled;
	bool rc_surface;
	uint32_t width;
	uint8_t cpp;
	uint32_t plane_pixel_rate;
	uint32_t y_min_scanlines;
	uint32_t plane_bytes_per_line;
	uint_fixed_16_16_t plane_blocks_per_line;
	uint_fixed_16_16_t y_tile_minimum;
	uint32_t linetime_us;
};

1465
/*
1466 1467 1468 1469
 * This struct helps tracking the state needed for runtime PM, which puts the
 * device in PCI D3 state. Notice that when this happens, nothing on the
 * graphics device works, even register access, so we don't get interrupts nor
 * anything else.
1470
 *
1471 1472 1473
 * Every piece of our code that needs to actually touch the hardware needs to
 * either call intel_runtime_pm_get or call intel_display_power_get with the
 * appropriate power domain.
1474
 *
1475 1476
 * Our driver uses the autosuspend delay feature, which means we'll only really
 * suspend if we stay with zero refcount for a certain amount of time. The
1477
 * default value is currently very conservative (see intel_runtime_pm_enable), but
1478
 * it can be changed with the standard runtime PM files from sysfs.
1479 1480 1481 1482 1483
 *
 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
 * goes back to false exactly before we reenable the IRQs. We use this variable
 * to check if someone is trying to enable/disable IRQs while they're supposed
 * to be disabled. This shouldn't happen and we'll print some error messages in
1484
 * case it happens.
1485
 *
1486
 * For more, read the Documentation/power/runtime_pm.txt.
1487
 */
1488
struct i915_runtime_pm {
1489
	atomic_t wakeref_count;
1490
	bool suspended;
1491
	bool irqs_enabled;
1492 1493
};

1494 1495 1496 1497 1498
enum intel_pipe_crc_source {
	INTEL_PIPE_CRC_SOURCE_NONE,
	INTEL_PIPE_CRC_SOURCE_PLANE1,
	INTEL_PIPE_CRC_SOURCE_PLANE2,
	INTEL_PIPE_CRC_SOURCE_PF,
1499
	INTEL_PIPE_CRC_SOURCE_PIPE,
D
Daniel Vetter 已提交
1500 1501 1502 1503 1504
	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
	INTEL_PIPE_CRC_SOURCE_TV,
	INTEL_PIPE_CRC_SOURCE_DP_B,
	INTEL_PIPE_CRC_SOURCE_DP_C,
	INTEL_PIPE_CRC_SOURCE_DP_D,
1505
	INTEL_PIPE_CRC_SOURCE_AUTO,
1506 1507 1508
	INTEL_PIPE_CRC_SOURCE_MAX,
};

1509
struct intel_pipe_crc_entry {
1510
	uint32_t frame;
1511 1512 1513
	uint32_t crc[5];
};

1514
#define INTEL_PIPE_CRC_ENTRIES_NR	128
1515
struct intel_pipe_crc {
1516 1517
	spinlock_t lock;
	bool opened;		/* exclusive access to the result file */
1518
	struct intel_pipe_crc_entry *entries;
1519
	enum intel_pipe_crc_source source;
1520
	int head, tail;
1521
	wait_queue_head_t wq;
T
Tomeu Vizoso 已提交
1522
	int skipped;
1523 1524
};

1525
struct i915_frontbuffer_tracking {
1526
	spinlock_t lock;
1527 1528 1529 1530 1531 1532 1533 1534 1535

	/*
	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
	 * scheduled flips.
	 */
	unsigned busy_bits;
	unsigned flip_bits;
};

1536
struct i915_wa_reg {
1537
	i915_reg_t addr;
1538 1539 1540 1541 1542
	u32 value;
	/* bitmask representing WA bits */
	u32 mask;
};

1543
#define I915_MAX_WA_REGS 16
1544 1545 1546 1547

struct i915_workarounds {
	struct i915_wa_reg reg[I915_MAX_WA_REGS];
	u32 count;
1548
	u32 hw_whitelist_count[I915_NUM_ENGINES];
1549 1550
};

1551 1552
struct i915_virtual_gpu {
	bool active;
1553
	u32 caps;
1554 1555
};

1556 1557 1558 1559 1560 1561 1562
/* used in computing the new watermarks state */
struct intel_wm_config {
	unsigned int num_pipes_active;
	bool sprites_enabled;
	bool sprites_scaled;
};

1563 1564 1565 1566 1567
struct i915_oa_format {
	u32 format;
	int size;
};

1568 1569 1570 1571 1572
struct i915_oa_reg {
	i915_reg_t addr;
	u32 value;
};

1573 1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586
struct i915_oa_config {
	char uuid[UUID_STRING_LEN + 1];
	int id;

	const struct i915_oa_reg *mux_regs;
	u32 mux_regs_len;
	const struct i915_oa_reg *b_counter_regs;
	u32 b_counter_regs_len;
	const struct i915_oa_reg *flex_regs;
	u32 flex_regs_len;

	struct attribute_group sysfs_metric;
	struct attribute *attrs[2];
	struct device_attribute sysfs_metric_id;
1587 1588

	atomic_t ref_count;
1589 1590
};

1591 1592
struct i915_perf_stream;

1593 1594 1595
/**
 * struct i915_perf_stream_ops - the OPs to support a specific stream type
 */
1596
struct i915_perf_stream_ops {
1597 1598 1599 1600
	/**
	 * @enable: Enables the collection of HW samples, either in response to
	 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
	 * without `I915_PERF_FLAG_DISABLED`.
1601 1602 1603
	 */
	void (*enable)(struct i915_perf_stream *stream);

1604 1605 1606 1607
	/**
	 * @disable: Disables the collection of HW samples, either in response
	 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
	 * the stream.
1608 1609 1610
	 */
	void (*disable)(struct i915_perf_stream *stream);

1611 1612
	/**
	 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1613 1614 1615 1616 1617 1618
	 * once there is something ready to read() for the stream
	 */
	void (*poll_wait)(struct i915_perf_stream *stream,
			  struct file *file,
			  poll_table *wait);

1619 1620 1621
	/**
	 * @wait_unlocked: For handling a blocking read, wait until there is
	 * something to ready to read() for the stream. E.g. wait on the same
1622
	 * wait queue that would be passed to poll_wait().
1623 1624 1625
	 */
	int (*wait_unlocked)(struct i915_perf_stream *stream);

1626 1627 1628 1629 1630 1631 1632
	/**
	 * @read: Copy buffered metrics as records to userspace
	 * **buf**: the userspace, destination buffer
	 * **count**: the number of bytes to copy, requested by userspace
	 * **offset**: zero at the start of the read, updated as the read
	 * proceeds, it represents how many bytes have been copied so far and
	 * the buffer offset for copying the next record.
1633
	 *
1634 1635
	 * Copy as many buffered i915 perf samples and records for this stream
	 * to userspace as will fit in the given buffer.
1636
	 *
1637 1638
	 * Only write complete records; returning -%ENOSPC if there isn't room
	 * for a complete record.
1639
	 *
1640 1641 1642
	 * Return any error condition that results in a short read such as
	 * -%ENOSPC or -%EFAULT, even though these may be squashed before
	 * returning to userspace.
1643 1644 1645 1646 1647 1648
	 */
	int (*read)(struct i915_perf_stream *stream,
		    char __user *buf,
		    size_t count,
		    size_t *offset);

1649 1650
	/**
	 * @destroy: Cleanup any stream specific resources.
1651 1652 1653 1654 1655 1656
	 *
	 * The stream will always be disabled before this is called.
	 */
	void (*destroy)(struct i915_perf_stream *stream);
};

1657 1658 1659
/**
 * struct i915_perf_stream - state for a single open stream FD
 */
1660
struct i915_perf_stream {
1661 1662 1663
	/**
	 * @dev_priv: i915 drm device
	 */
1664 1665
	struct drm_i915_private *dev_priv;

1666 1667 1668
	/**
	 * @link: Links the stream into ``&drm_i915_private->streams``
	 */
1669 1670
	struct list_head link;

1671 1672 1673 1674 1675
	/**
	 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
	 * properties given when opening a stream, representing the contents
	 * of a single sample as read() by userspace.
	 */
1676
	u32 sample_flags;
1677 1678 1679 1680 1681 1682

	/**
	 * @sample_size: Considering the configured contents of a sample
	 * combined with the required header size, this is the total size
	 * of a single sample record.
	 */
1683
	int sample_size;
1684

1685 1686 1687 1688
	/**
	 * @ctx: %NULL if measuring system-wide across all contexts or a
	 * specific context that is being monitored.
	 */
1689
	struct i915_gem_context *ctx;
1690 1691 1692 1693 1694 1695

	/**
	 * @enabled: Whether the stream is currently enabled, considering
	 * whether the stream was opened in a disabled state and based
	 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
	 */
1696 1697
	bool enabled;

1698 1699 1700 1701
	/**
	 * @ops: The callbacks providing the implementation of this specific
	 * type of configured stream.
	 */
1702
	const struct i915_perf_stream_ops *ops;
1703 1704 1705 1706 1707

	/**
	 * @oa_config: The OA configuration used by the stream.
	 */
	struct i915_oa_config *oa_config;
1708 1709
};

1710 1711 1712
/**
 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
 */
1713
struct i915_oa_ops {
1714 1715 1716 1717 1718 1719 1720 1721 1722 1723 1724 1725 1726 1727 1728 1729 1730 1731 1732
	/**
	 * @is_valid_b_counter_reg: Validates register's address for
	 * programming boolean counters for a particular platform.
	 */
	bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv,
				       u32 addr);

	/**
	 * @is_valid_mux_reg: Validates register's address for programming mux
	 * for a particular platform.
	 */
	bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr);

	/**
	 * @is_valid_flex_reg: Validates register's address for programming
	 * flex EU filtering for a particular platform.
	 */
	bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr);

1733 1734 1735 1736 1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747
	/**
	 * @init_oa_buffer: Resets the head and tail pointers of the
	 * circular buffer for periodic OA reports.
	 *
	 * Called when first opening a stream for OA metrics, but also may be
	 * called in response to an OA buffer overflow or other error
	 * condition.
	 *
	 * Note it may be necessary to clear the full OA buffer here as part of
	 * maintaining the invariable that new reports must be written to
	 * zeroed memory for us to be able to reliable detect if an expected
	 * report has not yet landed in memory.  (At least on Haswell the OA
	 * buffer tail pointer is not synchronized with reports being visible
	 * to the CPU)
	 */
1748
	void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
1749

1750 1751 1752 1753
	/**
	 * @enable_metric_set: Selects and applies any MUX configuration to set
	 * up the Boolean and Custom (B/C) counters that are part of the
	 * counter reports being sampled. May apply system constraints such as
1754 1755
	 * disabling EU clock gating as required.
	 */
1756 1757
	int (*enable_metric_set)(struct drm_i915_private *dev_priv,
				 const struct i915_oa_config *oa_config);
1758 1759 1760 1761 1762

	/**
	 * @disable_metric_set: Remove system constraints associated with using
	 * the OA unit.
	 */
1763
	void (*disable_metric_set)(struct drm_i915_private *dev_priv);
1764 1765 1766 1767

	/**
	 * @oa_enable: Enable periodic sampling
	 */
1768
	void (*oa_enable)(struct drm_i915_private *dev_priv);
1769 1770 1771 1772

	/**
	 * @oa_disable: Disable periodic sampling
	 */
1773
	void (*oa_disable)(struct drm_i915_private *dev_priv);
1774 1775 1776 1777 1778

	/**
	 * @read: Copy data from the circular OA buffer into a given userspace
	 * buffer.
	 */
1779 1780 1781 1782
	int (*read)(struct i915_perf_stream *stream,
		    char __user *buf,
		    size_t count,
		    size_t *offset);
1783 1784

	/**
1785
	 * @oa_hw_tail_read: read the OA tail pointer register
1786
	 *
1787 1788 1789
	 * In particular this enables us to share all the fiddly code for
	 * handling the OA unit tail pointer race that affects multiple
	 * generations.
1790
	 */
1791
	u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv);
1792 1793
};

1794
struct intel_cdclk_state {
1795
	unsigned int cdclk, vco, ref, bypass;
1796
	u8 voltage_level;
1797 1798
};

1799
struct drm_i915_private {
1800 1801
	struct drm_device drm;

1802
	struct kmem_cache *objects;
1803
	struct kmem_cache *vmas;
1804
	struct kmem_cache *luts;
1805
	struct kmem_cache *requests;
1806
	struct kmem_cache *dependencies;
1807
	struct kmem_cache *priorities;
1808

1809
	const struct intel_device_info info;
1810

1811 1812 1813
	/**
	 * Data Stolen Memory - aka "i915 stolen memory" gives us the start and
	 * end of stolen which we can optionally use to create GEM objects
1814
	 * backed by stolen memory. Note that stolen_usable_size tells us
1815 1816 1817 1818
	 * exactly how much of this we are actually allowed to use, given that
	 * some portion of it is in fact reserved for use by hardware functions.
	 */
	struct resource dsm;
1819 1820 1821 1822
	/**
	 * Reseved portion of Data Stolen Memory
	 */
	struct resource dsm_reserved;
1823

1824 1825 1826 1827 1828 1829 1830 1831 1832
	/*
	 * Stolen memory is segmented in hardware with different portions
	 * offlimits to certain functions.
	 *
	 * The drm_mm is initialised to the total accessible range, as found
	 * from the PCI config. On Broadwell+, this is further restricted to
	 * avoid the first page! The upper end of stolen memory is reserved for
	 * hardware functions and similarly removed from the accessible range.
	 */
1833
	resource_size_t stolen_usable_size;	/* Total size minus reserved ranges */
1834

1835 1836
	void __iomem *regs;

1837
	struct intel_uncore uncore;
1838

1839 1840
	struct i915_virtual_gpu vgpu;

1841
	struct intel_gvt *gvt;
1842

1843
	struct intel_huc huc;
1844 1845
	struct intel_guc guc;

1846 1847
	struct intel_csr csr;

1848
	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1849

1850 1851 1852 1853 1854 1855 1856 1857 1858
	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
	 * controller on different i2c buses. */
	struct mutex gmbus_mutex;

	/**
	 * Base address of the gmbus and gpio block.
	 */
	uint32_t gpio_mmio_base;

1859 1860 1861
	/* MMIO base address for MIPI regs */
	uint32_t mipi_mmio_base;

1862 1863
	uint32_t psr_mmio_base;

1864 1865
	uint32_t pps_mmio_base;

1866 1867
	wait_queue_head_t gmbus_wait_queue;

1868
	struct pci_dev *bridge_dev;
1869
	struct intel_engine_cs *engine[I915_NUM_ENGINES];
1870 1871 1872 1873
	/* Context used internally to idle the GPU and setup initial state */
	struct i915_gem_context *kernel_context;
	/* Context only to be used for injecting preemption commands */
	struct i915_gem_context *preempt_context;
1874 1875
	struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1]
					    [MAX_ENGINE_INSTANCE + 1];
1876

1877
	struct drm_dma_handle *status_page_dmah;
1878 1879 1880 1881 1882
	struct resource mch_res;

	/* protects the irq masks */
	spinlock_t irq_lock;

1883 1884
	bool display_irqs_enabled;

1885 1886 1887
	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
	struct pm_qos_request pm_qos;

V
Ville Syrjälä 已提交
1888 1889
	/* Sideband mailbox protection */
	struct mutex sb_lock;
1890 1891

	/** Cached value of IMR to avoid reads in updating the bitfield */
1892 1893 1894 1895
	union {
		u32 irq_mask;
		u32 de_irq_mask[I915_MAX_PIPES];
	};
1896
	u32 gt_irq_mask;
1897 1898
	u32 pm_imr;
	u32 pm_ier;
1899
	u32 pm_rps_events;
1900
	u32 pm_guc_events;
1901
	u32 pipestat_irq_mask[I915_MAX_PIPES];
1902

1903
	struct i915_hotplug hotplug;
1904
	struct intel_fbc fbc;
1905
	struct i915_drrs drrs;
1906
	struct intel_opregion opregion;
1907
	struct intel_vbt_data vbt;
1908

1909 1910
	bool preserve_bios_swizzle;

1911 1912 1913
	/* overlay */
	struct intel_overlay *overlay;

1914
	/* backlight registers and fields in struct intel_panel */
1915
	struct mutex backlight_lock;
1916

1917 1918 1919
	/* LVDS info */
	bool no_aux_handshake;

V
Ville Syrjälä 已提交
1920 1921 1922
	/* protects panel power sequencer state */
	struct mutex pps_mutex;

1923 1924 1925 1926
	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */

	unsigned int fsb_freq, mem_freq, is_ddr3;
1927
	unsigned int skl_preferred_vco_freq;
1928
	unsigned int max_cdclk_freq;
1929

M
Mika Kahola 已提交
1930
	unsigned int max_dotclk_freq;
1931
	unsigned int rawclk_freq;
1932
	unsigned int hpll_freq;
1933
	unsigned int fdi_pll_freq;
1934
	unsigned int czclk_freq;
1935

1936
	struct {
1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950
		/*
		 * The current logical cdclk state.
		 * See intel_atomic_state.cdclk.logical
		 *
		 * For reading holding any crtc lock is sufficient,
		 * for writing must hold all of them.
		 */
		struct intel_cdclk_state logical;
		/*
		 * The current actual cdclk state.
		 * See intel_atomic_state.cdclk.actual
		 */
		struct intel_cdclk_state actual;
		/* The current hardware cdclk state */
1951 1952
		struct intel_cdclk_state hw;
	} cdclk;
1953

1954 1955 1956 1957 1958 1959 1960
	/**
	 * wq - Driver workqueue for GEM.
	 *
	 * NOTE: Work items scheduled here are not allowed to grab any modeset
	 * locks, for otherwise the flushing done in the pageflip code will
	 * result in deadlocks.
	 */
1961 1962
	struct workqueue_struct *wq;

1963 1964 1965
	/* ordered wq for modesets */
	struct workqueue_struct *modeset_wq;

1966 1967 1968 1969 1970
	/* Display functions */
	struct drm_i915_display_funcs display;

	/* PCH chipset type */
	enum intel_pch pch_type;
1971
	unsigned short pch_id;
1972 1973 1974

	unsigned long quirks;

1975 1976
	enum modeset_restore modeset_restore;
	struct mutex modeset_restore_lock;
1977
	struct drm_atomic_state *modeset_restore_state;
1978
	struct drm_modeset_acquire_ctx reset_ctx;
1979

1980
	struct list_head vm_list; /* Global list of all address spaces */
1981
	struct i915_ggtt ggtt; /* VM representing the global address space */
B
Ben Widawsky 已提交
1982

1983
	struct i915_gem_mm mm;
1984 1985
	DECLARE_HASHTABLE(mm_structs, 7);
	struct mutex mm_lock;
1986

1987 1988
	struct intel_ppat ppat;

1989 1990
	/* Kernel Modesetting */

1991 1992
	struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
	struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1993

1994 1995 1996 1997
#ifdef CONFIG_DEBUG_FS
	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif

1998
	/* dpll and cdclk state is protected by connection_mutex */
D
Daniel Vetter 已提交
1999 2000
	int num_shared_dpll;
	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2001
	const struct intel_dpll_mgr *dpll_mgr;
2002

2003 2004 2005 2006 2007 2008 2009
	/*
	 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
	 * Must be global rather than per dpll, because on some platforms
	 * plls share registers.
	 */
	struct mutex dpll_lock;

2010
	unsigned int active_crtcs;
2011 2012
	/* minimum acceptable cdclk for each pipe */
	int min_cdclk[I915_MAX_PIPES];
2013 2014
	/* minimum acceptable voltage level for each pipe */
	u8 min_voltage_level[I915_MAX_PIPES];
2015

2016
	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2017

2018
	struct i915_workarounds workarounds;
2019

2020 2021
	struct i915_frontbuffer_tracking fb_tracking;

2022 2023 2024 2025 2026
	struct intel_atomic_helper {
		struct llist_head free_list;
		struct work_struct free_work;
	} atomic_helper;

2027
	u16 orig_clock;
2028

2029
	bool mchbar_need_disable;
2030

2031 2032
	struct intel_l3_parity l3_parity;

B
Ben Widawsky 已提交
2033
	/* Cannot be determined by PCIID. You must always read a register. */
2034
	u32 edram_cap;
B
Ben Widawsky 已提交
2035

2036 2037 2038 2039 2040 2041 2042 2043
	/*
	 * Protects RPS/RC6 register access and PCU communication.
	 * Must be taken after struct_mutex if nested. Note that
	 * this lock may be held for long periods of time when
	 * talking to hw - so only take it when talking to hw!
	 */
	struct mutex pcu_lock;

2044 2045
	/* gen6+ GT PM state */
	struct intel_gen6_power_mgmt gt_pm;
2046

2047 2048
	/* ilk-only ips/rps state. Everything in here is protected by the global
	 * mchdev_lock in intel_pm.c */
2049
	struct intel_ilk_power_mgmt ips;
2050

2051
	struct i915_power_domains power_domains;
2052

R
Rodrigo Vivi 已提交
2053
	struct i915_psr psr;
2054

2055
	struct i915_gpu_error gpu_error;
2056

2057 2058
	struct drm_i915_gem_object *vlv_pctx;

2059 2060
	/* list of fbdev register on this device */
	struct intel_fbdev *fbdev;
2061
	struct work_struct fbdev_suspend_work;
2062 2063

	struct drm_property *broadcast_rgb_property;
2064
	struct drm_property *force_audio_property;
2065

I
Imre Deak 已提交
2066
	/* hda/i915 audio component */
2067
	struct i915_audio_component *audio_component;
I
Imre Deak 已提交
2068
	bool audio_component_registered;
2069 2070 2071 2072 2073
	/**
	 * av_mutex - mutex for audio/video sync
	 *
	 */
	struct mutex av_mutex;
I
Imre Deak 已提交
2074

2075 2076
	struct {
		struct list_head list;
2077 2078
		struct llist_head free_list;
		struct work_struct free_work;
2079 2080 2081 2082 2083 2084 2085 2086

		/* The hw wants to have a stable context identifier for the
		 * lifetime of the context (for OA, PASID, faults, etc).
		 * This is limited in execlists to 21 bits.
		 */
		struct ida hw_ida;
#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
	} contexts;
2087

2088
	u32 fdi_rx_config;
2089

2090
	/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2091
	u32 chv_phy_control;
2092 2093 2094 2095 2096 2097
	/*
	 * Shadows for CHV DPLL_MD regs to keep the state
	 * checker somewhat working in the presence hardware
	 * crappiness (can't read out DPLL_MD for pipes B & C).
	 */
	u32 chv_dpll_md[I915_MAX_PIPES];
2098
	u32 bxt_phy_grc;
2099

2100
	u32 suspend_count;
2101
	bool suspended_to_idle;
2102
	struct i915_suspend_saved_registers regfile;
2103
	struct vlv_s0ix_state vlv_s0ix_state;
2104

2105
	enum {
2106 2107 2108 2109 2110
		I915_SAGV_UNKNOWN = 0,
		I915_SAGV_DISABLED,
		I915_SAGV_ENABLED,
		I915_SAGV_NOT_CONTROLLED
	} sagv_status;
2111

2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123
	struct {
		/*
		 * Raw watermark latency values:
		 * in 0.1us units for WM0,
		 * in 0.5us units for WM1+.
		 */
		/* primary */
		uint16_t pri_latency[5];
		/* sprite */
		uint16_t spr_latency[5];
		/* cursor */
		uint16_t cur_latency[5];
2124 2125 2126 2127 2128 2129
		/*
		 * Raw watermark memory latency values
		 * for SKL for all 8 levels
		 * in 1us units.
		 */
		uint16_t skl_latency[8];
2130 2131

		/* current hardware state */
2132 2133 2134
		union {
			struct ilk_wm_values hw;
			struct skl_wm_values skl_hw;
2135
			struct vlv_wm_values vlv;
2136
			struct g4x_wm_values g4x;
2137
		};
2138 2139

		uint8_t max_level;
2140 2141 2142 2143 2144 2145 2146

		/*
		 * Should be held around atomic WM register writing; also
		 * protects * intel_crtc->wm.active and
		 * cstate->wm.need_postvbl_update.
		 */
		struct mutex wm_mutex;
2147 2148 2149 2150 2151 2152 2153

		/*
		 * Set during HW readout of watermarks/DDB.  Some platforms
		 * need to know when we're still using BIOS-provided values
		 * (which we don't fully trust).
		 */
		bool distrust_bios_wm;
2154 2155
	} wm;

2156
	struct i915_runtime_pm runtime_pm;
2157

2158 2159
	struct {
		bool initialized;
2160

2161
		struct kobject *metrics_kobj;
2162
		struct ctl_table_header *sysctl_header;
2163

2164 2165 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175 2176 2177 2178 2179
		/*
		 * Lock associated with adding/modifying/removing OA configs
		 * in dev_priv->perf.metrics_idr.
		 */
		struct mutex metrics_lock;

		/*
		 * List of dynamic configurations, you need to hold
		 * dev_priv->perf.metrics_lock to access it.
		 */
		struct idr metrics_idr;

		/*
		 * Lock associated with anything below within this structure
		 * except exclusive_stream.
		 */
2180 2181
		struct mutex lock;
		struct list_head streams;
2182 2183

		struct {
2184 2185 2186 2187 2188 2189
			/*
			 * The stream currently using the OA unit. If accessed
			 * outside a syscall associated to its file
			 * descriptor, you need to hold
			 * dev_priv->drm.struct_mutex.
			 */
2190 2191 2192 2193 2194 2195 2196 2197
			struct i915_perf_stream *exclusive_stream;

			u32 specific_ctx_id;

			struct hrtimer poll_check_timer;
			wait_queue_head_t poll_wq;
			bool pollin;

2198 2199 2200 2201 2202 2203
			/**
			 * For rate limiting any notifications of spurious
			 * invalid OA reports
			 */
			struct ratelimit_state spurious_report_rs;

2204 2205 2206
			bool periodic;
			int period_exponent;

2207
			struct i915_oa_config test_config;
2208 2209 2210 2211

			struct {
				struct i915_vma *vma;
				u8 *vaddr;
2212
				u32 last_ctx_id;
2213 2214
				int format;
				int format_size;
2215

2216 2217 2218 2219 2220 2221 2222 2223 2224 2225 2226 2227 2228 2229 2230 2231 2232 2233 2234 2235 2236 2237 2238 2239 2240 2241 2242 2243 2244 2245 2246 2247 2248 2249 2250 2251 2252 2253 2254 2255 2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268
				/**
				 * Locks reads and writes to all head/tail state
				 *
				 * Consider: the head and tail pointer state
				 * needs to be read consistently from a hrtimer
				 * callback (atomic context) and read() fop
				 * (user context) with tail pointer updates
				 * happening in atomic context and head updates
				 * in user context and the (unlikely)
				 * possibility of read() errors needing to
				 * reset all head/tail state.
				 *
				 * Note: Contention or performance aren't
				 * currently a significant concern here
				 * considering the relatively low frequency of
				 * hrtimer callbacks (5ms period) and that
				 * reads typically only happen in response to a
				 * hrtimer event and likely complete before the
				 * next callback.
				 *
				 * Note: This lock is not held *while* reading
				 * and copying data to userspace so the value
				 * of head observed in htrimer callbacks won't
				 * represent any partial consumption of data.
				 */
				spinlock_t ptr_lock;

				/**
				 * One 'aging' tail pointer and one 'aged'
				 * tail pointer ready to used for reading.
				 *
				 * Initial values of 0xffffffff are invalid
				 * and imply that an update is required
				 * (and should be ignored by an attempted
				 * read)
				 */
				struct {
					u32 offset;
				} tails[2];

				/**
				 * Index for the aged tail ready to read()
				 * data up to.
				 */
				unsigned int aged_tail_idx;

				/**
				 * A monotonic timestamp for when the current
				 * aging tail pointer was read; used to
				 * determine when it is old enough to trust.
				 */
				u64 aging_timestamp;

2269 2270 2271 2272 2273 2274 2275 2276 2277 2278
				/**
				 * Although we can always read back the head
				 * pointer register, we prefer to avoid
				 * trusting the HW state, just to avoid any
				 * risk that some hardware condition could
				 * somehow bump the head pointer unpredictably
				 * and cause us to forward the wrong OA buffer
				 * data to userspace.
				 */
				u32 head;
2279 2280 2281
			} oa_buffer;

			u32 gen7_latched_oastatus1;
2282 2283 2284 2285 2286 2287 2288 2289 2290
			u32 ctx_oactxctrl_offset;
			u32 ctx_flexeu0_offset;

			/**
			 * The RPT_ID/reason field for Gen8+ includes a bit
			 * to determine if the CTX ID in the report is valid
			 * but the specific bit differs between Gen 8 and 9
			 */
			u32 gen8_valid_ctx_bit;
2291 2292 2293

			struct i915_oa_ops ops;
			const struct i915_oa_format *oa_formats;
2294
		} oa;
2295 2296
	} perf;

2297 2298
	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
	struct {
2299
		void (*resume)(struct drm_i915_private *);
2300
		void (*cleanup_engine)(struct intel_engine_cs *engine);
2301

2302 2303
		struct list_head timelines;
		struct i915_gem_timeline global_timeline;
2304
		u32 active_requests;
2305

2306 2307 2308 2309 2310 2311 2312 2313 2314
		/**
		 * Is the GPU currently considered idle, or busy executing
		 * userspace requests? Whilst idle, we allow runtime power
		 * management to power down the hardware and display clocks.
		 * In order to reduce the effect on performance, there
		 * is a slight delay before we do so.
		 */
		bool awake;

2315 2316 2317 2318 2319 2320
		/**
		 * The number of times we have woken up.
		 */
		unsigned int epoch;
#define I915_EPOCH_INVALID 0

2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334 2335 2336 2337
		/**
		 * We leave the user IRQ off as much as possible,
		 * but this means that requests will finish and never
		 * be retired once the system goes idle. Set a timer to
		 * fire periodically while the ring is running. When it
		 * fires, go retire requests.
		 */
		struct delayed_work retire_work;

		/**
		 * When we detect an idle GPU, we want to turn on
		 * powersaving features. So once we see that there
		 * are no more requests outstanding and no more
		 * arrive within a small period of time, we fire
		 * off the idle_work.
		 */
		struct delayed_work idle_work;
2338 2339

		ktime_t last_init_time;
2340 2341
	} gt;

2342 2343 2344
	/* perform PHY state sanity checks? */
	bool chv_phy_assert[2];

M
Mahesh Kumar 已提交
2345 2346
	bool ipc_enabled;

2347 2348
	/* Used to save the pipe-to-encoder mapping for audio */
	struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2349

2350 2351 2352 2353 2354 2355
	/* necessary resource sharing with HDMI LPE audio driver. */
	struct {
		struct platform_device *platdev;
		int	irq;
	} lpe_audio;

2356 2357
	struct i915_pmu pmu;

2358 2359 2360 2361
	/*
	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
	 * will be rejected. Instead look for a better place.
	 */
2362
};
L
Linus Torvalds 已提交
2363

2364 2365
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
2366
	return container_of(dev, struct drm_i915_private, drm);
2367 2368
}

2369
static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
I
Imre Deak 已提交
2370
{
2371
	return to_i915(dev_get_drvdata(kdev));
I
Imre Deak 已提交
2372 2373
}

2374 2375 2376 2377 2378
static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
{
	return container_of(guc, struct drm_i915_private, guc);
}

A
Arkadiusz Hiler 已提交
2379 2380 2381 2382 2383
static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
{
	return container_of(huc, struct drm_i915_private, huc);
}

2384
/* Simple iterator over all initialised engines */
2385 2386 2387 2388 2389
#define for_each_engine(engine__, dev_priv__, id__) \
	for ((id__) = 0; \
	     (id__) < I915_NUM_ENGINES; \
	     (id__)++) \
		for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2390 2391

/* Iterator over subset of engines selected by mask */
2392 2393
#define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
	for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask;	\
2394
	     tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2395

2396 2397 2398 2399 2400 2401 2402
enum hdmi_force_audio {
	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
	HDMI_AUDIO_AUTO,		/* trust EDID */
	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
};

2403
#define I915_GTT_OFFSET_NONE ((u32)-1)
2404

2405 2406
/*
 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2407
 * considered to be the frontbuffer for the given plane interface-wise. This
2408 2409 2410 2411 2412
 * doesn't mean that the hw necessarily already scans it out, but that any
 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
 *
 * We have one bit per pipe and per scanout plane type.
 */
2413 2414
#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2415 2416 2417
#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
#define INTEL_FRONTBUFFER_CURSOR(pipe) \
2418 2419 2420
	(1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
	(1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2421
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2422
	(1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2423
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2424
	(0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2425

2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451
/*
 * Optimised SGL iterator for GEM objects
 */
static __always_inline struct sgt_iter {
	struct scatterlist *sgp;
	union {
		unsigned long pfn;
		dma_addr_t dma;
	};
	unsigned int curr;
	unsigned int max;
} __sgt_iter(struct scatterlist *sgl, bool dma) {
	struct sgt_iter s = { .sgp = sgl };

	if (s.sgp) {
		s.max = s.curr = s.sgp->offset;
		s.max += s.sgp->length;
		if (dma)
			s.dma = sg_dma_address(s.sgp);
		else
			s.pfn = page_to_pfn(sg_page(s.sgp));
	}

	return s;
}

2452 2453 2454 2455 2456 2457 2458 2459
static inline struct scatterlist *____sg_next(struct scatterlist *sg)
{
	++sg;
	if (unlikely(sg_is_chain(sg)))
		sg = sg_chain_ptr(sg);
	return sg;
}

2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473
/**
 * __sg_next - return the next scatterlist entry in a list
 * @sg:		The current sg entry
 *
 * Description:
 *   If the entry is the last, return NULL; otherwise, step to the next
 *   element in the array (@sg@+1). If that's a chain pointer, follow it;
 *   otherwise just return the pointer to the current element.
 **/
static inline struct scatterlist *__sg_next(struct scatterlist *sg)
{
#ifdef CONFIG_DEBUG_SG
	BUG_ON(sg->sg_magic != SG_MAGIC);
#endif
2474
	return sg_is_last(sg) ? NULL : ____sg_next(sg);
2475 2476
}

2477 2478 2479 2480 2481 2482 2483 2484 2485
/**
 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
 * @__dmap:	DMA address (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_dma(__dmap, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, true);			\
	     ((__dmap) = (__iter).dma + (__iter).curr);			\
2486 2487
	     (((__iter).curr += PAGE_SIZE) >= (__iter).max) ?		\
	     (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0)
2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498

/**
 * for_each_sgt_page - iterate over the pages of the given sg_table
 * @__pp:	page pointer (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_page(__pp, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, false);		\
	     ((__pp) = (__iter).pfn == 0 ? NULL :			\
	      pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2499 2500
	     (((__iter).curr += PAGE_SIZE) >= (__iter).max) ?		\
	     (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0)
2501

2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516
static inline unsigned int i915_sg_page_sizes(struct scatterlist *sg)
{
	unsigned int page_sizes;

	page_sizes = 0;
	while (sg) {
		GEM_BUG_ON(sg->offset);
		GEM_BUG_ON(!IS_ALIGNED(sg->length, PAGE_SIZE));
		page_sizes |= sg->length;
		sg = __sg_next(sg);
	}

	return page_sizes;
}

2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531
static inline unsigned int i915_sg_segment_size(void)
{
	unsigned int size = swiotlb_max_segment();

	if (size == 0)
		return SCATTERLIST_MAX_SEGMENT;

	size = rounddown(size, PAGE_SIZE);
	/* swiotlb_max_segment_size can return 1 byte when it means one page. */
	if (size < PAGE_SIZE)
		size = PAGE_SIZE;

	return size;
}

2532 2533 2534 2535 2536 2537 2538
static inline const struct intel_device_info *
intel_info(const struct drm_i915_private *dev_priv)
{
	return &dev_priv->info;
}

#define INTEL_INFO(dev_priv)	intel_info((dev_priv))
2539

2540
#define INTEL_GEN(dev_priv)	((dev_priv)->info.gen)
2541
#define INTEL_DEVID(dev_priv)	((dev_priv)->info.device_id)
2542

2543
#define REVID_FOREVER		0xff
2544
#define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
2545 2546

#define GEN_FOREVER (0)
2547 2548 2549 2550 2551 2552 2553 2554

#define INTEL_GEN_MASK(s, e) ( \
	BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
	BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
	GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
		(s) != GEN_FOREVER ? (s) - 1 : 0) \
)

2555 2556 2557 2558 2559
/*
 * Returns true if Gen is in inclusive range [Start, End].
 *
 * Use GEN_FOREVER for unbound start and or end.
 */
2560 2561
#define IS_GEN(dev_priv, s, e) \
	(!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
2562

2563 2564 2565 2566 2567 2568 2569 2570
/*
 * Return true if revision is in range [since,until] inclusive.
 *
 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
 */
#define IS_REVID(p, since, until) \
	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))

2571
#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
T
Tvrtko Ursulin 已提交
2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584

#define IS_I830(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I830)
#define IS_I845G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I845G)
#define IS_I85X(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I85X)
#define IS_I865G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I865G)
#define IS_I915G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915G)
#define IS_I915GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915GM)
#define IS_I945G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945G)
#define IS_I945GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945GM)
#define IS_I965G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965G)
#define IS_I965GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965GM)
#define IS_G45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G45)
#define IS_GM45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GM45)
2585
#define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))
2586 2587
#define IS_PINEVIEW_G(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa001)
#define IS_PINEVIEW_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa011)
T
Tvrtko Ursulin 已提交
2588 2589
#define IS_PINEVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
#define IS_G33(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G33)
2590
#define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
T
Tvrtko Ursulin 已提交
2591
#define IS_IVYBRIDGE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
2592 2593
#define IS_IVB_GT1(dev_priv)	(IS_IVYBRIDGE(dev_priv) && \
				 (dev_priv)->info.gt == 1)
T
Tvrtko Ursulin 已提交
2594 2595 2596 2597 2598 2599 2600 2601 2602 2603
#define IS_VALLEYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
#define IS_CHERRYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
#define IS_HASWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_HASWELL)
#define IS_BROADWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROADWELL)
#define IS_SKYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
#define IS_BROXTON(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROXTON)
#define IS_KABYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
#define IS_GEMINILAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
#define IS_COFFEELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
#define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
2604
#define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
2605
#define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
2606 2607 2608 2609 2610 2611
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||	\
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||	\
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
V
Ville Syrjälä 已提交
2612
/* ULX machines are also considered ULT. */
2613 2614 2615
#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
#define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
2616
				 (dev_priv)->info.gt == 3)
2617 2618 2619
#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
#define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
2620
				 (dev_priv)->info.gt == 3)
2621
/* ULX machines are also considered ULT. */
2622 2623 2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639
#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
				 INTEL_DEVID(dev_priv) == 0x0A1E)
#define IS_SKL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x1906 || \
				 INTEL_DEVID(dev_priv) == 0x1913 || \
				 INTEL_DEVID(dev_priv) == 0x1916 || \
				 INTEL_DEVID(dev_priv) == 0x1921 || \
				 INTEL_DEVID(dev_priv) == 0x1926)
#define IS_SKL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x190E || \
				 INTEL_DEVID(dev_priv) == 0x1915 || \
				 INTEL_DEVID(dev_priv) == 0x191E)
#define IS_KBL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x5906 || \
				 INTEL_DEVID(dev_priv) == 0x5913 || \
				 INTEL_DEVID(dev_priv) == 0x5916 || \
				 INTEL_DEVID(dev_priv) == 0x5921 || \
				 INTEL_DEVID(dev_priv) == 0x5926)
#define IS_KBL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x590E || \
				 INTEL_DEVID(dev_priv) == 0x5915 || \
				 INTEL_DEVID(dev_priv) == 0x591E)
2640
#define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \
2641
				 (dev_priv)->info.gt == 2)
2642
#define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
2643
				 (dev_priv)->info.gt == 3)
2644
#define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \
2645
				 (dev_priv)->info.gt == 4)
2646
#define IS_KBL_GT2(dev_priv)	(IS_KABYLAKE(dev_priv) && \
2647
				 (dev_priv)->info.gt == 2)
2648
#define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \
2649
				 (dev_priv)->info.gt == 3)
2650 2651
#define IS_CFL_ULT(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
2652 2653
#define IS_CFL_GT2(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
				 (dev_priv)->info.gt == 2)
2654 2655
#define IS_CFL_GT3(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
				 (dev_priv)->info.gt == 3)
2656

2657
#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2658

2659 2660 2661 2662 2663 2664
#define SKL_REVID_A0		0x0
#define SKL_REVID_B0		0x1
#define SKL_REVID_C0		0x2
#define SKL_REVID_D0		0x3
#define SKL_REVID_E0		0x4
#define SKL_REVID_F0		0x5
2665 2666
#define SKL_REVID_G0		0x6
#define SKL_REVID_H0		0x7
2667

2668 2669
#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))

2670
#define BXT_REVID_A0		0x0
2671
#define BXT_REVID_A1		0x1
2672
#define BXT_REVID_B0		0x3
2673
#define BXT_REVID_B_LAST	0x8
2674
#define BXT_REVID_C0		0x9
N
Nick Hoath 已提交
2675

2676 2677
#define IS_BXT_REVID(dev_priv, since, until) \
	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2678

M
Mika Kuoppala 已提交
2679 2680
#define KBL_REVID_A0		0x0
#define KBL_REVID_B0		0x1
2681 2682 2683
#define KBL_REVID_C0		0x2
#define KBL_REVID_D0		0x3
#define KBL_REVID_E0		0x4
M
Mika Kuoppala 已提交
2684

2685 2686
#define IS_KBL_REVID(dev_priv, since, until) \
	(IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
M
Mika Kuoppala 已提交
2687

2688 2689 2690 2691 2692 2693
#define GLK_REVID_A0		0x0
#define GLK_REVID_A1		0x1

#define IS_GLK_REVID(dev_priv, since, until) \
	(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))

2694 2695
#define CNL_REVID_A0		0x0
#define CNL_REVID_B0		0x1
R
Rodrigo Vivi 已提交
2696
#define CNL_REVID_C0		0x2
2697 2698 2699 2700

#define IS_CNL_REVID(p, since, until) \
	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))

2701 2702 2703 2704 2705 2706
/*
 * The genX designation typically refers to the render engine, so render
 * capability related checks should use IS_GEN, while display and other checks
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 * chips, etc.).
 */
2707 2708 2709 2710 2711 2712 2713 2714
#define IS_GEN2(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(1)))
#define IS_GEN3(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(2)))
#define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))
#define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))
#define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))
#define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
#define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
#define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
2715
#define IS_GEN10(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(9)))
2716
#define IS_GEN11(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(10)))
2717

2718
#define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
2719 2720
#define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv)	(IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2721

2722 2723 2724 2725 2726 2727 2728 2729 2730
#define ENGINE_MASK(id)	BIT(id)
#define RENDER_RING	ENGINE_MASK(RCS)
#define BSD_RING	ENGINE_MASK(VCS)
#define BLT_RING	ENGINE_MASK(BCS)
#define VEBOX_RING	ENGINE_MASK(VECS)
#define BSD2_RING	ENGINE_MASK(VCS2)
#define ALL_ENGINES	(~0)

#define HAS_ENGINE(dev_priv, id) \
2731
	(!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2732 2733 2734 2735 2736 2737

#define HAS_BSD(dev_priv)	HAS_ENGINE(dev_priv, VCS)
#define HAS_BSD2(dev_priv)	HAS_ENGINE(dev_priv, VCS2)
#define HAS_BLT(dev_priv)	HAS_ENGINE(dev_priv, BCS)
#define HAS_VEBOX(dev_priv)	HAS_ENGINE(dev_priv, VECS)

2738 2739
#define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv)

2740 2741 2742
#define HAS_LLC(dev_priv)	((dev_priv)->info.has_llc)
#define HAS_SNOOP(dev_priv)	((dev_priv)->info.has_snoop)
#define HAS_EDRAM(dev_priv)	(!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2743 2744
#define HAS_WT(dev_priv)	((IS_HASWELL(dev_priv) || \
				 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2745

2746
#define HWS_NEEDS_PHYSICAL(dev_priv)	((dev_priv)->info.hws_needs_physical)
2747

2748 2749
#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
		((dev_priv)->info.has_logical_ring_contexts)
2750 2751
#define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
		((dev_priv)->info.has_logical_ring_preemption)
2752 2753 2754

#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)

2755 2756 2757
#define USES_PPGTT(dev_priv)		(i915_modparams.enable_ppgtt)
#define USES_FULL_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt >= 2)
#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915_modparams.enable_ppgtt == 3)
2758 2759 2760 2761
#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
	GEM_BUG_ON((sizes) == 0); \
	((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
})
2762 2763 2764 2765

#define HAS_OVERLAY(dev_priv)		 ((dev_priv)->info.has_overlay)
#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
		((dev_priv)->info.overlay_needs_physical)
2766

2767
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2768
#define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_I845G(dev_priv))
2769 2770

/* WaRsDisableCoarsePowerGating:skl,bxt */
2771
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2772
	(IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2773

2774 2775 2776 2777 2778
/*
 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
 * even when in MSI mode. This results in spurious interrupt warnings if the
 * legacy irq no. is shared with another device. The kernel then disables that
 * interrupt source and so prevents the other device from working properly.
2779 2780 2781
 *
 * Since we don't enable MSI anymore on gen4, we can always use GMBUS/AUX
 * interrupts.
2782
 */
2783 2784
#define HAS_AUX_IRQ(dev_priv)   true
#define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4)
2785

2786 2787 2788
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
2789 2790 2791
#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
					 !(IS_I915G(dev_priv) || \
					 IS_I915GM(dev_priv)))
2792 2793
#define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)
#define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)
2794

2795 2796
#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
#define HAS_FBC(dev_priv)	((dev_priv)->info.has_fbc)
2797
#define HAS_CUR_FBC(dev_priv)	(!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7)
2798

2799
#define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2800

2801
#define HAS_DP_MST(dev_priv)	((dev_priv)->info.has_dp_mst)
2802

2803 2804 2805
#define HAS_DDI(dev_priv)		 ((dev_priv)->info.has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
#define HAS_PSR(dev_priv)		 ((dev_priv)->info.has_psr)
2806

2807 2808
#define HAS_RC6(dev_priv)		 ((dev_priv)->info.has_rc6)
#define HAS_RC6p(dev_priv)		 ((dev_priv)->info.has_rc6p)
2809
#define HAS_RC6pp(dev_priv)		 (false) /* HW was never validated */
P
Paulo Zanoni 已提交
2810

2811
#define HAS_CSR(dev_priv)	((dev_priv)->info.has_csr)
2812

2813
#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2814 2815
#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)

2816 2817
#define HAS_IPC(dev_priv)		 ((dev_priv)->info.has_ipc)

2818 2819 2820 2821 2822
/*
 * For now, anything with a GuC requires uCode loading, and then supports
 * command submission once loaded. But these are logically independent
 * properties, so we have separate macros to test them.
 */
2823
#define HAS_GUC(dev_priv)	((dev_priv)->info.has_guc)
2824
#define HAS_GUC_CT(dev_priv)	((dev_priv)->info.has_guc_ct)
2825 2826
#define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
#define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
2827 2828 2829

/* For now, anything with a GuC has also HuC */
#define HAS_HUC(dev_priv)	(HAS_GUC(dev_priv))
2830
#define HAS_HUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
2831

2832
/* Having a GuC is not the same as using a GuC */
2833 2834 2835
#define USES_GUC(dev_priv)		intel_uc_is_using_guc()
#define USES_GUC_SUBMISSION(dev_priv)	intel_uc_is_using_guc_submission()
#define USES_HUC(dev_priv)		intel_uc_is_using_huc()
2836

2837
#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2838

2839
#define HAS_POOLED_EU(dev_priv)	((dev_priv)->info.has_pooled_eu)
2840

2841
#define INTEL_PCH_DEVICE_ID_MASK		0xff80
2842 2843 2844 2845 2846
#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
2847 2848
#define INTEL_PCH_WPT_DEVICE_ID_TYPE		0x8c80
#define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE		0x9c80
2849 2850
#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
2851
#define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA280
2852
#define INTEL_PCH_CNP_DEVICE_ID_TYPE		0xA300
2853
#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE		0x9D80
2854
#define INTEL_PCH_ICP_DEVICE_ID_TYPE		0x3480
2855
#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
2856
#define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
2857
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
2858

2859
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2860
#define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
2861
#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2862 2863
#define HAS_PCH_CNP_LP(dev_priv) \
	((dev_priv)->pch_id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
2864 2865 2866
#define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2867
#define HAS_PCH_LPT_LP(dev_priv) \
2868 2869
	((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
	 (dev_priv)->pch_id == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
2870
#define HAS_PCH_LPT_H(dev_priv) \
2871 2872
	((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
	 (dev_priv)->pch_id == INTEL_PCH_WPT_DEVICE_ID_TYPE)
2873 2874 2875 2876
#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2877

2878
#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2879

2880
#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
2881

2882
/* DPF == dynamic parity feature */
2883
#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2884 2885
#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
				 2 : HAS_L3_DPF(dev_priv))
2886

2887
#define GT_FREQUENCY_MULTIPLIER 50
A
Akash Goel 已提交
2888
#define GEN9_FREQ_SCALER 3
2889

2890 2891
#include "i915_trace.h"

2892
static inline bool intel_vtd_active(void)
2893 2894
{
#ifdef CONFIG_INTEL_IOMMU
2895
	if (intel_iommu_gfx_mapped)
2896 2897 2898 2899 2900
		return true;
#endif
	return false;
}

2901 2902 2903 2904 2905
static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
	return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
}

2906 2907 2908
static inline bool
intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
2909
	return IS_BROXTON(dev_priv) && intel_vtd_active();
2910 2911
}

2912
int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2913
				int enable_ppgtt);
2914

2915
/* i915_drv.c */
2916 2917 2918 2919 2920 2921 2922
void __printf(3, 4)
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
	      const char *fmt, ...);

#define i915_report_error(dev_priv, fmt, ...)				   \
	__i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)

2923
#ifdef CONFIG_COMPAT
D
Dave Airlie 已提交
2924 2925
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);
2926 2927
#else
#define i915_compat_ioctl NULL
2928
#endif
2929 2930 2931 2932 2933
extern const struct dev_pm_ops i915_pm_ops;

extern int i915_driver_load(struct pci_dev *pdev,
			    const struct pci_device_id *ent);
extern void i915_driver_unload(struct drm_device *dev);
2934 2935
extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2936 2937 2938 2939 2940 2941

#define I915_RESET_QUIET BIT(0)
extern void i915_reset(struct drm_i915_private *i915, unsigned int flags);
extern int i915_reset_engine(struct intel_engine_cs *engine,
			     unsigned int flags);

2942
extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv);
2943
extern int intel_reset_guc(struct drm_i915_private *dev_priv);
2944 2945
extern int intel_guc_reset_engine(struct intel_guc *guc,
				  struct intel_engine_cs *engine);
2946
extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2947
extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
2948 2949 2950 2951
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2952
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2953

2954
int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
2955 2956
int intel_engines_init(struct drm_i915_private *dev_priv);

2957
/* intel_hotplug.c */
2958 2959
void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
			   u32 pin_mask, u32 long_mask);
2960 2961 2962
void intel_hpd_init(struct drm_i915_private *dev_priv);
void intel_hpd_init_work(struct drm_i915_private *dev_priv);
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2963
enum port intel_hpd_pin_to_port(enum hpd_pin pin);
2964
enum hpd_pin intel_hpd_pin(enum port port);
2965 2966
bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2967

L
Linus Torvalds 已提交
2968
/* i915_irq.c */
2969 2970 2971 2972
static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
{
	unsigned long delay;

2973
	if (unlikely(!i915_modparams.enable_hangcheck))
2974 2975 2976 2977 2978 2979 2980 2981 2982 2983 2984 2985
		return;

	/* Don't continually defer the hangcheck so that it is always run at
	 * least once after work has been scheduled on any ring. Otherwise,
	 * we will ignore a hung ring if a second ring is kept busy.
	 */

	delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
	queue_delayed_work(system_long_wq,
			   &dev_priv->gpu_error.hangcheck_work, delay);
}

2986
__printf(3, 4)
2987 2988
void i915_handle_error(struct drm_i915_private *dev_priv,
		       u32 engine_mask,
2989
		       const char *fmt, ...);
L
Linus Torvalds 已提交
2990

2991
extern void intel_irq_init(struct drm_i915_private *dev_priv);
2992
extern void intel_irq_fini(struct drm_i915_private *dev_priv);
2993 2994
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2995

2996 2997
static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
{
2998
	return dev_priv->gvt;
2999 3000
}

3001
static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
3002
{
3003
	return dev_priv->vgpu.active;
3004
}
3005

3006 3007
u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv,
			      enum pipe pipe);
3008
void
3009
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3010
		     u32 status_mask);
3011 3012

void
3013
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3014
		      u32 status_mask);
3015

3016 3017
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3018 3019 3020
void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
				   uint32_t mask,
				   uint32_t bits);
3021 3022 3023 3024 3025 3026 3027 3028 3029 3030 3031 3032 3033
void ilk_update_display_irq(struct drm_i915_private *dev_priv,
			    uint32_t interrupt_mask,
			    uint32_t enabled_irq_mask);
static inline void
ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, bits);
}
static inline void
ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, 0);
}
3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045 3046 3047
void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
			 enum pipe pipe,
			 uint32_t interrupt_mask,
			 uint32_t enabled_irq_mask);
static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
				       enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
}
static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
					enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
}
3048 3049 3050
void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask);
3051 3052 3053 3054 3055 3056 3057 3058 3059 3060 3061
static inline void
ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, bits);
}
static inline void
ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, 0);
}

3062 3063 3064 3065 3066 3067 3068 3069 3070
/* i915_gem.c */
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3071 3072
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3073 3074 3075 3076 3077 3078
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
			     struct drm_file *file_priv);
int i915_gem_execbuffer(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
J
Jesse Barnes 已提交
3079 3080
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
3081 3082
int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
B
Ben Widawsky 已提交
3083 3084 3085 3086
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
3087 3088
int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
3089 3090
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
3091 3092 3093 3094
int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
3095 3096
int i915_gem_init_userptr(struct drm_i915_private *dev_priv);
void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv);
3097 3098
int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file);
3099 3100
int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
3101 3102
int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3103
void i915_gem_sanitize(struct drm_i915_private *i915);
3104 3105
int i915_gem_load_init(struct drm_i915_private *dev_priv);
void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
3106
void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3107
int i915_gem_freeze(struct drm_i915_private *dev_priv);
3108 3109
int i915_gem_freeze_late(struct drm_i915_private *dev_priv);

3110
void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
3111
void i915_gem_object_free(struct drm_i915_gem_object *obj);
3112 3113
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			 const struct drm_i915_gem_object_ops *ops);
3114 3115 3116 3117 3118
struct drm_i915_gem_object *
i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
struct drm_i915_gem_object *
i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
				 const void *data, size_t size);
3119
void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3120
void i915_gem_free_object(struct drm_gem_object *obj);
3121

3122 3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134
static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
{
	/* A single pass should suffice to release all the freed objects (along
	 * most call paths) , but be a little more paranoid in that freeing
	 * the objects does take a little amount of time, during which the rcu
	 * callbacks could have added new objects into the freed list, and
	 * armed the work again.
	 */
	do {
		rcu_barrier();
	} while (flush_work(&i915->mm.free_work));
}

3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150 3151 3152 3153 3154
static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915)
{
	/*
	 * Similar to objects above (see i915_gem_drain_freed-objects), in
	 * general we have workers that are armed by RCU and then rearm
	 * themselves in their callbacks. To be paranoid, we need to
	 * drain the workqueue a second time after waiting for the RCU
	 * grace period so that we catch work queued via RCU from the first
	 * pass. As neither drain_workqueue() nor flush_workqueue() report
	 * a result, we make an assumption that we only don't require more
	 * than 2 passes to catch all recursive RCU delayed work.
	 *
	 */
	int pass = 2;
	do {
		rcu_barrier();
		drain_workqueue(i915->wq);
	} while (--pass);
}

C
Chris Wilson 已提交
3155
struct i915_vma * __must_check
3156 3157
i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
			 const struct i915_ggtt_view *view,
3158
			 u64 size,
3159 3160
			 u64 alignment,
			 u64 flags);
3161

3162
int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3163
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3164

3165 3166
void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);

C
Chris Wilson 已提交
3167
static inline int __sg_page_count(const struct scatterlist *sg)
3168
{
3169 3170
	return sg->length >> PAGE_SHIFT;
}
3171

3172 3173 3174
struct scatterlist *
i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
		       unsigned int n, unsigned int *offset);
3175

3176 3177 3178
struct page *
i915_gem_object_get_page(struct drm_i915_gem_object *obj,
			 unsigned int n);
3179

3180 3181 3182
struct page *
i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
			       unsigned int n);
3183

3184 3185 3186
dma_addr_t
i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
				unsigned long n);
3187

3188
void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
3189
				 struct sg_table *pages,
M
Matthew Auld 已提交
3190
				 unsigned int sg_page_sizes);
C
Chris Wilson 已提交
3191 3192 3193 3194 3195
int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);

static inline int __must_check
i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
{
3196
	might_lock(&obj->mm.lock);
C
Chris Wilson 已提交
3197

3198
	if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
C
Chris Wilson 已提交
3199 3200 3201 3202 3203
		return 0;

	return __i915_gem_object_get_pages(obj);
}

3204 3205 3206 3207 3208 3209
static inline bool
i915_gem_object_has_pages(struct drm_i915_gem_object *obj)
{
	return !IS_ERR_OR_NULL(READ_ONCE(obj->mm.pages));
}

C
Chris Wilson 已提交
3210 3211
static inline void
__i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3212
{
3213
	GEM_BUG_ON(!i915_gem_object_has_pages(obj));
C
Chris Wilson 已提交
3214

3215
	atomic_inc(&obj->mm.pages_pin_count);
C
Chris Wilson 已提交
3216 3217 3218 3219 3220
}

static inline bool
i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
{
3221
	return atomic_read(&obj->mm.pages_pin_count);
C
Chris Wilson 已提交
3222 3223 3224 3225 3226
}

static inline void
__i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
{
3227
	GEM_BUG_ON(!i915_gem_object_has_pages(obj));
C
Chris Wilson 已提交
3228 3229
	GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));

3230
	atomic_dec(&obj->mm.pages_pin_count);
3231
}
3232

3233 3234
static inline void
i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3235
{
C
Chris Wilson 已提交
3236
	__i915_gem_object_unpin_pages(obj);
3237 3238
}

3239 3240 3241 3242 3243 3244 3245
enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
	I915_MM_NORMAL = 0,
	I915_MM_SHRINKER
};

void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
				 enum i915_mm_subclass subclass);
3246
void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
C
Chris Wilson 已提交
3247

3248 3249 3250
enum i915_map_type {
	I915_MAP_WB = 0,
	I915_MAP_WC,
3251 3252 3253
#define I915_MAP_OVERRIDE BIT(31)
	I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE,
	I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE,
3254 3255
};

3256 3257
/**
 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3258 3259
 * @obj: the object to map into kernel address space
 * @type: the type of mapping, used to select pgprot_t
3260 3261 3262
 *
 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
 * pages and then returns a contiguous mapping of the backing storage into
3263 3264
 * the kernel address space. Based on the @type of mapping, the PTE will be
 * set to either WriteBack or WriteCombine (via pgprot_t).
3265
 *
3266 3267
 * The caller is responsible for calling i915_gem_object_unpin_map() when the
 * mapping is no longer required.
3268
 *
3269 3270
 * Returns the pointer through which to access the mapped object, or an
 * ERR_PTR() on error.
3271
 */
3272 3273
void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
					   enum i915_map_type type);
3274 3275 3276

/**
 * i915_gem_object_unpin_map - releases an earlier mapping
3277
 * @obj: the object to unmap
3278 3279 3280 3281 3282 3283 3284 3285 3286 3287 3288
 *
 * After pinning the object and mapping its pages, once you are finished
 * with your access, call i915_gem_object_unpin_map() to release the pin
 * upon the mapping. Once the pin count reaches zero, that mapping may be
 * removed.
 */
static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3289 3290 3291 3292
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
				    unsigned int *needs_clflush);
int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
				     unsigned int *needs_clflush);
3293 3294 3295
#define CLFLUSH_BEFORE	BIT(0)
#define CLFLUSH_AFTER	BIT(1)
#define CLFLUSH_FLAGS	(CLFLUSH_BEFORE | CLFLUSH_AFTER)
3296 3297 3298 3299 3300 3301 3302

static inline void
i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3303
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
B
Ben Widawsky 已提交
3304
void i915_vma_move_to_active(struct i915_vma *vma,
3305 3306
			     struct drm_i915_gem_request *req,
			     unsigned int flags);
3307 3308 3309
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
3310 3311
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
		      uint32_t handle, uint64_t *offset);
3312
int i915_gem_mmap_gtt_version(void);
3313 3314 3315 3316 3317

void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits);

3318
int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3319

3320
struct drm_i915_gem_request *
3321
i915_gem_find_active_request(struct intel_engine_cs *engine);
3322

3323
void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3324

3325 3326 3327 3328 3329 3330
static inline bool i915_reset_backoff(struct i915_gpu_error *error)
{
	return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
}

static inline bool i915_reset_handoff(struct i915_gpu_error *error)
3331
{
3332
	return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags));
3333 3334
}

3335
static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3336
{
3337
	return unlikely(test_bit(I915_WEDGED, &error->flags));
3338 3339
}

3340
static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error)
3341
{
3342
	return i915_reset_backoff(error) | i915_terminally_wedged(error);
M
Mika Kuoppala 已提交
3343 3344 3345 3346
}

static inline u32 i915_reset_count(struct i915_gpu_error *error)
{
3347
	return READ_ONCE(error->reset_count);
3348
}
3349

3350 3351 3352 3353 3354 3355
static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
					  struct intel_engine_cs *engine)
{
	return READ_ONCE(error->reset_engine_count[engine->id]);
}

3356 3357
struct drm_i915_gem_request *
i915_gem_reset_prepare_engine(struct intel_engine_cs *engine);
3358
int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3359
void i915_gem_reset(struct drm_i915_private *dev_priv);
3360
void i915_gem_reset_finish_engine(struct intel_engine_cs *engine);
3361
void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3362
void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3363
bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3364 3365
void i915_gem_reset_engine(struct intel_engine_cs *engine,
			   struct drm_i915_gem_request *request);
3366

3367
void i915_gem_init_mmio(struct drm_i915_private *i915);
3368 3369
int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3370
void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3371
void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3372 3373
int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
			   unsigned int flags);
3374 3375
int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
void i915_gem_resume(struct drm_i915_private *dev_priv);
3376
int i915_gem_fault(struct vm_fault *vmf);
3377 3378 3379 3380
int i915_gem_object_wait(struct drm_i915_gem_object *obj,
			 unsigned int flags,
			 long timeout,
			 struct intel_rps_client *rps);
3381 3382 3383 3384 3385
int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
				  unsigned int flags,
				  int priority);
#define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX

3386
int __must_check
3387 3388 3389
i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
int __must_check
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
3390
int __must_check
3391
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
C
Chris Wilson 已提交
3392
struct i915_vma * __must_check
3393 3394
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
3395
				     const struct i915_ggtt_view *view);
C
Chris Wilson 已提交
3396
void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3397
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3398
				int align);
3399
int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file);
3400
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3401

3402 3403 3404
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);

3405 3406 3407 3408 3409 3410
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
				struct dma_buf *dma_buf);

struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
				struct drm_gem_object *gem_obj, int flags);

3411 3412 3413 3414 3415 3416
static inline struct i915_hw_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space *vm)
{
	return container_of(vm, struct i915_hw_ppgtt, base);
}

J
Joonas Lahtinen 已提交
3417
/* i915_gem_fence_reg.c */
3418 3419 3420
struct drm_i915_fence_reg *
i915_reserve_fence(struct drm_i915_private *dev_priv);
void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
3421

3422
void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3423
void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3424

3425
void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3426 3427 3428 3429
void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
				       struct sg_table *pages);
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
					 struct sg_table *pages);
3430

3431 3432 3433 3434 3435 3436
static inline struct i915_gem_context *
__i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id)
{
	return idr_find(&file_priv->context_idr, id);
}

3437 3438 3439 3440 3441
static inline struct i915_gem_context *
i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
{
	struct i915_gem_context *ctx;

3442 3443 3444 3445 3446
	rcu_read_lock();
	ctx = __i915_gem_context_lookup_rcu(file_priv, id);
	if (ctx && !kref_get_unless_zero(&ctx->ref))
		ctx = NULL;
	rcu_read_unlock();
3447 3448 3449 3450

	return ctx;
}

C
Chris Wilson 已提交
3451 3452 3453 3454 3455 3456 3457 3458 3459 3460
static inline struct intel_timeline *
i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
				 struct intel_engine_cs *engine)
{
	struct i915_address_space *vm;

	vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
	return &vm->timeline.engine[engine->id];
}

3461 3462
int i915_perf_open_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file);
3463 3464 3465 3466
int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
				  struct drm_file *file);
3467 3468 3469
void i915_oa_init_reg_state(struct intel_engine_cs *engine,
			    struct i915_gem_context *ctx,
			    uint32_t *reg_state);
3470

3471
/* i915_gem_evict.c */
3472
int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3473
					  u64 min_size, u64 alignment,
3474
					  unsigned cache_level,
3475
					  u64 start, u64 end,
3476
					  unsigned flags);
3477 3478 3479
int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
					 struct drm_mm_node *node,
					 unsigned int flags);
3480
int i915_gem_evict_vm(struct i915_address_space *vm);
3481

3482 3483
void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv);

3484
/* belongs in i915_gem_gtt.h */
3485
static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3486
{
3487
	wmb();
3488
	if (INTEL_GEN(dev_priv) < 6)
3489 3490
		intel_gtt_chipset_flush();
}
3491

3492
/* i915_gem_stolen.c */
3493 3494 3495
int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
				struct drm_mm_node *node, u64 size,
				unsigned alignment);
3496 3497 3498 3499
int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
					 struct drm_mm_node *node, u64 size,
					 unsigned alignment, u64 start,
					 u64 end);
3500 3501
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
				 struct drm_mm_node *node);
3502
int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3503
void i915_gem_cleanup_stolen(struct drm_device *dev);
3504
struct drm_i915_gem_object *
3505 3506
i915_gem_object_create_stolen(struct drm_i915_private *dev_priv,
			      resource_size_t size);
3507
struct drm_i915_gem_object *
3508
i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3509 3510 3511
					       resource_size_t stolen_offset,
					       resource_size_t gtt_offset,
					       resource_size_t size);
3512

3513 3514 3515
/* i915_gem_internal.c */
struct drm_i915_gem_object *
i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3516
				phys_addr_t size);
3517

3518
/* i915_gem_shrinker.c */
3519
unsigned long i915_gem_shrink(struct drm_i915_private *i915,
3520
			      unsigned long target,
3521
			      unsigned long *nr_scanned,
3522 3523 3524 3525
			      unsigned flags);
#define I915_SHRINK_PURGEABLE 0x1
#define I915_SHRINK_UNBOUND 0x2
#define I915_SHRINK_BOUND 0x4
3526
#define I915_SHRINK_ACTIVE 0x8
3527
#define I915_SHRINK_VMAPS 0x10
3528 3529 3530
unsigned long i915_gem_shrink_all(struct drm_i915_private *i915);
void i915_gem_shrinker_register(struct drm_i915_private *i915);
void i915_gem_shrinker_unregister(struct drm_i915_private *i915);
3531 3532


3533
/* i915_gem_tiling.c */
3534
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3535
{
3536
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3537 3538

	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3539
		i915_gem_object_is_tiled(obj);
3540 3541
}

3542 3543 3544 3545 3546
u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
			unsigned int tiling, unsigned int stride);
u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
			     unsigned int tiling, unsigned int stride);

3547
/* i915_debugfs.c */
3548
#ifdef CONFIG_DEBUG_FS
3549
int i915_debugfs_register(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3550
int i915_debugfs_connector_add(struct drm_connector *connector);
3551
void intel_display_crc_init(struct drm_i915_private *dev_priv);
3552
#else
3553
static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3554 3555
static inline int i915_debugfs_connector_add(struct drm_connector *connector)
{ return 0; }
3556
static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3557
#endif
3558 3559

/* i915_gpu_error.c */
3560 3561
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)

3562 3563
__printf(2, 3)
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3564
int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3565
			    const struct i915_gpu_state *gpu);
3566
int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3567
			      struct drm_i915_private *i915,
3568 3569 3570 3571 3572 3573
			      size_t count, loff_t pos);
static inline void i915_error_state_buf_release(
	struct drm_i915_error_state_buf *eb)
{
	kfree(eb->buf);
}
3574 3575

struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
3576 3577
void i915_capture_error_state(struct drm_i915_private *dev_priv,
			      u32 engine_mask,
3578
			      const char *error_msg);
3579 3580 3581 3582 3583 3584 3585 3586 3587 3588 3589 3590 3591 3592 3593 3594 3595

static inline struct i915_gpu_state *
i915_gpu_state_get(struct i915_gpu_state *gpu)
{
	kref_get(&gpu->ref);
	return gpu;
}

void __i915_gpu_state_free(struct kref *kref);
static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
{
	if (gpu)
		kref_put(&gpu->ref, __i915_gpu_state_free);
}

struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
void i915_reset_error_state(struct drm_i915_private *i915);
3596

3597 3598 3599 3600 3601 3602 3603 3604
#else

static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
					    u32 engine_mask,
					    const char *error_msg)
{
}

3605 3606 3607 3608 3609 3610 3611
static inline struct i915_gpu_state *
i915_first_error_state(struct drm_i915_private *i915)
{
	return NULL;
}

static inline void i915_reset_error_state(struct drm_i915_private *i915)
3612 3613 3614 3615 3616
{
}

#endif

3617
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3618

3619
/* i915_cmd_parser.c */
3620
int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3621
void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3622 3623 3624 3625 3626 3627 3628
void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
int intel_engine_cmd_parser(struct intel_engine_cs *engine,
			    struct drm_i915_gem_object *batch_obj,
			    struct drm_i915_gem_object *shadow_batch_obj,
			    u32 batch_start_offset,
			    u32 batch_len,
			    bool is_master);
3629

3630 3631 3632
/* i915_perf.c */
extern void i915_perf_init(struct drm_i915_private *dev_priv);
extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3633 3634
extern void i915_perf_register(struct drm_i915_private *dev_priv);
extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3635

3636
/* i915_suspend.c */
3637 3638
extern int i915_save_state(struct drm_i915_private *dev_priv);
extern int i915_restore_state(struct drm_i915_private *dev_priv);
3639

B
Ben Widawsky 已提交
3640
/* i915_sysfs.c */
D
David Weinehall 已提交
3641 3642
void i915_setup_sysfs(struct drm_i915_private *dev_priv);
void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
B
Ben Widawsky 已提交
3643

3644 3645 3646 3647
/* intel_lpe_audio.c */
int  intel_lpe_audio_init(struct drm_i915_private *dev_priv);
void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3648
void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3649 3650
			    enum pipe pipe, enum port port,
			    const void *eld, int ls_clock, bool dp_output);
3651

3652
/* intel_i2c.c */
3653 3654
extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3655 3656
extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
				     unsigned int pin);
3657

3658 3659
extern struct i2c_adapter *
intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
C
Chris Wilson 已提交
3660 3661
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3662
static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3663 3664 3665
{
	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
}
3666
extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3667

3668
/* intel_bios.c */
3669
void intel_bios_init(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3670
bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3671
bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3672
bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3673
bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3674
bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3675
bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3676
bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3677 3678
bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
				     enum port port);
3679 3680 3681
bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
				enum port port);

J
Jesse Barnes 已提交
3682 3683 3684 3685 3686 3687 3688 3689 3690
/* intel_acpi.c */
#ifdef CONFIG_ACPI
extern void intel_register_dsm_handler(void);
extern void intel_unregister_dsm_handler(void);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */

3691 3692 3693 3694 3695 3696 3697
/* intel_device_info.c */
static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private *dev_priv)
{
	return (struct intel_device_info *)&dev_priv->info;
}

J
Jesse Barnes 已提交
3698
/* modesetting */
3699
extern void intel_modeset_init_hw(struct drm_device *dev);
3700
extern int intel_modeset_init(struct drm_device *dev);
J
Jesse Barnes 已提交
3701
extern void intel_modeset_cleanup(struct drm_device *dev);
3702
extern int intel_connector_register(struct drm_connector *);
3703
extern void intel_connector_unregister(struct drm_connector *);
3704 3705
extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
				       bool state);
3706
extern void intel_display_resume(struct drm_device *dev);
3707 3708
extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3709
extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3710
extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3711
extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3712
extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3713
				  bool enable);
3714

B
Ben Widawsky 已提交
3715 3716
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file);
3717

3718
/* overlay */
3719 3720
extern struct intel_overlay_error_state *
intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3721 3722
extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
					    struct intel_overlay_error_state *error);
3723

3724 3725
extern struct intel_display_error_state *
intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3726
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3727
					    struct intel_display_error_state *error);
3728

3729 3730
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3731 3732
int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
		      u32 reply_mask, u32 reply, int timeout_base_ms);
3733 3734

/* intel_sideband.c */
3735
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3736
int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3737
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3738 3739
u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3740 3741 3742 3743
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3744 3745
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3746 3747
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3748 3749 3750 3751
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		   enum intel_sbi_destination destination);
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		     enum intel_sbi_destination destination);
3752 3753
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3754

3755
/* intel_dpio_phy.c */
3756
void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3757
			     enum dpio_phy *phy, enum dpio_channel *ch);
3758 3759 3760
void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
				  enum port port, u32 margin, u32 scale,
				  u32 enable, u32 deemphasis);
3761 3762 3763 3764 3765 3766
void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
			    enum dpio_phy phy);
bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
			      enum dpio_phy phy);
3767
uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count);
3768 3769 3770 3771
void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
				     uint8_t lane_lat_optim_mask);
uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);

3772 3773 3774
void chv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 deemph_reg_value, u32 margin_reg_value,
			      bool uniq_trans_scale);
3775
void chv_data_lane_soft_reset(struct intel_encoder *encoder,
3776
			      const struct intel_crtc_state *crtc_state,
3777
			      bool reset);
3778 3779 3780 3781
void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
			    const struct intel_crtc_state *crtc_state);
void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
				const struct intel_crtc_state *crtc_state);
3782
void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3783 3784
void chv_phy_post_pll_disable(struct intel_encoder *encoder,
			      const struct intel_crtc_state *old_crtc_state);
3785

3786 3787 3788
void vlv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 demph_reg_value, u32 preemph_reg_value,
			      u32 uniqtranscale_reg_value, u32 tx3_demph);
3789 3790 3791 3792 3793 3794
void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
			    const struct intel_crtc_state *crtc_state);
void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
				const struct intel_crtc_state *crtc_state);
void vlv_phy_reset_lanes(struct intel_encoder *encoder,
			 const struct intel_crtc_state *old_crtc_state);
3795

3796 3797
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3798
u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv,
3799
			   const i915_reg_t reg);
3800

T
Tvrtko Ursulin 已提交
3801 3802
u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);

3803 3804 3805 3806 3807 3808
static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
					 const i915_reg_t reg)
{
	return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000);
}

3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821
#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

#define I915_READ16(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
#define I915_WRITE16(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
#define I915_READ16_NOTRACE(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
#define I915_WRITE16_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)

#define I915_READ(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
#define I915_WRITE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
#define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
#define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)

3822 3823 3824 3825
/* Be very careful with read/write 64-bit values. On 32-bit machines, they
 * will be implemented using 2 32-bit writes in an arbitrary order with
 * an arbitrary delay between them. This can cause the hardware to
 * act upon the intermediate value, possibly leading to corruption and
3826 3827 3828 3829 3830 3831 3832 3833 3834
 * machine death. For this reason we do not support I915_WRITE64, or
 * dev_priv->uncore.funcs.mmio_writeq.
 *
 * When reading a 64-bit value as two 32-bit values, the delay may cause
 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
 * occasionally a 64-bit register does not actualy support a full readq
 * and must be read using two 32-bit reads.
 *
 * You have been warned.
3835
 */
3836
#define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3837

3838
#define I915_READ64_2x32(lower_reg, upper_reg) ({			\
3839 3840
	u32 upper, lower, old_upper, loop = 0;				\
	upper = I915_READ(upper_reg);					\
3841
	do {								\
3842
		old_upper = upper;					\
3843
		lower = I915_READ(lower_reg);				\
3844 3845
		upper = I915_READ(upper_reg);				\
	} while (upper != old_upper && loop++ < 2);			\
3846
	(u64)upper << 32 | lower; })
3847

3848 3849 3850
#define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)

3851
#define __raw_read(x, s) \
3852
static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
3853
					     i915_reg_t reg) \
3854
{ \
3855
	return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3856 3857 3858
}

#define __raw_write(x, s) \
3859
static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
3860
				       i915_reg_t reg, uint##x##_t val) \
3861
{ \
3862
	write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3863 3864 3865 3866 3867 3868 3869 3870 3871 3872 3873 3874 3875 3876
}
__raw_read(8, b)
__raw_read(16, w)
__raw_read(32, l)
__raw_read(64, q)

__raw_write(8, b)
__raw_write(16, w)
__raw_write(32, l)
__raw_write(64, q)

#undef __raw_read
#undef __raw_write

3877
/* These are untraced mmio-accessors that are only valid to be used inside
3878
 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3879
 * controlled.
3880
 *
3881
 * Think twice, and think again, before using these.
3882 3883 3884 3885 3886 3887 3888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901
 *
 * As an example, these accessors can possibly be used between:
 *
 * spin_lock_irq(&dev_priv->uncore.lock);
 * intel_uncore_forcewake_get__locked();
 *
 * and
 *
 * intel_uncore_forcewake_put__locked();
 * spin_unlock_irq(&dev_priv->uncore.lock);
 *
 *
 * Note: some registers may not need forcewake held, so
 * intel_uncore_forcewake_{get,put} can be omitted, see
 * intel_uncore_forcewake_for_reg().
 *
 * Certain architectures will die if the same cacheline is concurrently accessed
 * by different clients (e.g. on Ivybridge). Access to registers should
 * therefore generally be serialised, by either the dev_priv->uncore.lock or
 * a more localised lock guarding all access to that bank of registers.
3902
 */
3903 3904
#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3905
#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3906 3907
#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)

3908 3909 3910 3911
/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
#define INTEL_BROADCAST_RGB_FULL 1
#define INTEL_BROADCAST_RGB_LIMITED 2
3912

3913
static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3914
{
3915
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3916
		return VLV_VGACNTRL;
3917
	else if (INTEL_GEN(dev_priv) >= 5)
3918
		return CPU_VGACNTRL;
3919 3920 3921 3922
	else
		return VGACNTRL;
}

3923 3924 3925 3926 3927 3928 3929
static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
{
	unsigned long j = msecs_to_jiffies(m);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3930 3931
static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
{
3932 3933 3934 3935 3936
	/* nsecs_to_jiffies64() does not guard against overflow */
	if (NSEC_PER_SEC % HZ &&
	    div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
		return MAX_JIFFY_OFFSET;

3937 3938 3939
        return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
}

3940 3941 3942 3943 3944 3945 3946 3947
static inline unsigned long
timespec_to_jiffies_timeout(const struct timespec *value)
{
	unsigned long j = timespec_to_jiffies(value);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3948 3949 3950 3951 3952 3953 3954 3955 3956
/*
 * If you need to wait X milliseconds between events A and B, but event B
 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
 * when event A happened, then just before event B you call this function and
 * pass the timestamp as the first argument, and X as the second argument.
 */
static inline void
wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
{
3957
	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3958 3959 3960 3961 3962 3963 3964 3965 3966 3967

	/*
	 * Don't re-read the value of "jiffies" every time since it may change
	 * behind our back and break the math.
	 */
	tmp_jiffies = jiffies;
	target_jiffies = timestamp_jiffies +
			 msecs_to_jiffies_timeout(to_wait_ms);

	if (time_after(target_jiffies, tmp_jiffies)) {
3968 3969 3970 3971
		remaining_jiffies = target_jiffies - tmp_jiffies;
		while (remaining_jiffies)
			remaining_jiffies =
			    schedule_timeout_uninterruptible(remaining_jiffies);
3972 3973
	}
}
3974 3975

static inline bool
3976
__i915_request_irq_complete(const struct drm_i915_gem_request *req)
3977
{
3978
	struct intel_engine_cs *engine = req->engine;
3979
	u32 seqno;
3980

3981 3982 3983 3984 3985 3986 3987 3988 3989
	/* Note that the engine may have wrapped around the seqno, and
	 * so our request->global_seqno will be ahead of the hardware,
	 * even though it completed the request before wrapping. We catch
	 * this by kicking all the waiters before resetting the seqno
	 * in hardware, and also signal the fence.
	 */
	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &req->fence.flags))
		return true;

3990 3991 3992 3993 3994 3995 3996 3997 3998 3999
	/* The request was dequeued before we were awoken. We check after
	 * inspecting the hw to confirm that this was the same request
	 * that generated the HWS update. The memory barriers within
	 * the request execution are sufficient to ensure that a check
	 * after reading the value from hw matches this request.
	 */
	seqno = i915_gem_request_global_seqno(req);
	if (!seqno)
		return false;

4000 4001 4002
	/* Before we do the heavier coherent read of the seqno,
	 * check the value (hopefully) in the CPU cacheline.
	 */
4003
	if (__i915_gem_request_completed(req, seqno))
4004 4005
		return true;

4006 4007 4008 4009 4010 4011 4012 4013 4014 4015 4016
	/* Ensure our read of the seqno is coherent so that we
	 * do not "miss an interrupt" (i.e. if this is the last
	 * request and the seqno write from the GPU is not visible
	 * by the time the interrupt fires, we will see that the
	 * request is incomplete and go back to sleep awaiting
	 * another interrupt that will never come.)
	 *
	 * Strictly, we only need to do this once after an interrupt,
	 * but it is easier and safer to do it every time the waiter
	 * is woken.
	 */
4017
	if (engine->irq_seqno_barrier &&
4018
	    test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
4019
		struct intel_breadcrumbs *b = &engine->breadcrumbs;
4020

4021 4022 4023 4024 4025 4026 4027 4028 4029 4030 4031 4032
		/* The ordering of irq_posted versus applying the barrier
		 * is crucial. The clearing of the current irq_posted must
		 * be visible before we perform the barrier operation,
		 * such that if a subsequent interrupt arrives, irq_posted
		 * is reasserted and our task rewoken (which causes us to
		 * do another __i915_request_irq_complete() immediately
		 * and reapply the barrier). Conversely, if the clear
		 * occurs after the barrier, then an interrupt that arrived
		 * whilst we waited on the barrier would not trigger a
		 * barrier on the next pass, and the read may not see the
		 * seqno update.
		 */
4033
		engine->irq_seqno_barrier(engine);
4034 4035 4036 4037 4038 4039 4040

		/* If we consume the irq, but we are no longer the bottom-half,
		 * the real bottom-half may not have serialised their own
		 * seqno check with the irq-barrier (i.e. may have inspected
		 * the seqno before we believe it coherent since they see
		 * irq_posted == false but we are still running).
		 */
4041
		spin_lock_irq(&b->irq_lock);
4042
		if (b->irq_wait && b->irq_wait->tsk != current)
4043 4044 4045 4046 4047 4048
			/* Note that if the bottom-half is changed as we
			 * are sending the wake-up, the new bottom-half will
			 * be woken by whomever made the change. We only have
			 * to worry about when we steal the irq-posted for
			 * ourself.
			 */
4049
			wake_up_process(b->irq_wait->tsk);
4050
		spin_unlock_irq(&b->irq_lock);
4051

4052
		if (__i915_gem_request_completed(req, seqno))
4053 4054
			return true;
	}
4055 4056 4057 4058

	return false;
}

4059 4060 4061
void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);

4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077
/* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
 * perform the operation. To check beforehand, pass in the parameters to
 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
 * you only need to pass in the minor offsets, page-aligned pointers are
 * always valid.
 *
 * For just checking for SSE4.1, in the foreknowledge that the future use
 * will be correctly aligned, just use i915_has_memcpy_from_wc().
 */
#define i915_can_memcpy_from_wc(dst, src, len) \
	i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)

#define i915_has_memcpy_from_wc() \
	i915_memcpy_from_wc(NULL, NULL, 0)

4078 4079 4080 4081 4082
/* i915_mm.c */
int remap_io_mapping(struct vm_area_struct *vma,
		     unsigned long addr, unsigned long pfn, unsigned long size,
		     struct io_mapping *iomap);

4083 4084 4085 4086 4087 4088 4089 4090
static inline int intel_hws_csb_write_index(struct drm_i915_private *i915)
{
	if (INTEL_GEN(i915) >= 10)
		return CNL_HWS_CSB_WRITE_INDEX;
	else
		return I915_HWS_CSB_WRITE_INDEX;
}

L
Linus Torvalds 已提交
4091
#endif