i915_drv.h 124.3 KB
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/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#ifndef _I915_DRV_H_
#define _I915_DRV_H_

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#include <uapi/drm/i915_drm.h>
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#include <uapi/drm/drm_fourcc.h>
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#include <linux/io-mapping.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/backlight.h>
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#include <linux/hashtable.h>
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#include <linux/intel-iommu.h>
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#include <linux/kref.h>
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#include <linux/pm_qos.h>
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#include <linux/reservation.h>
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#include <linux/shmem_fs.h>

#include <drm/drmP.h>
#include <drm/intel-gtt.h>
#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
#include <drm/drm_gem.h>
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#include <drm/drm_auth.h>
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#include <drm/drm_cache.h>
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#include "i915_params.h"
#include "i915_reg.h"
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#include "i915_utils.h"
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#include "intel_uncore.h"
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#include "intel_bios.h"
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#include "intel_dpll_mgr.h"
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#include "intel_uc.h"
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#include "intel_lrc.h"
#include "intel_ringbuffer.h"

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#include "i915_gem.h"
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#include "i915_gem_context.h"
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#include "i915_gem_fence_reg.h"
#include "i915_gem_object.h"
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#include "i915_gem_gtt.h"
#include "i915_gem_render_state.h"
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#include "i915_gem_request.h"
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#include "i915_gem_timeline.h"
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#include "i915_vma.h"

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#include "intel_gvt.h"

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/* General customization:
 */

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
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#define DRIVER_DATE		"20170529"
#define DRIVER_TIMESTAMP	1496041258
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/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 * which may not necessarily be a user visible problem.  This will either
 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 * enable distros and users to tailor their preferred amount of i915 abrt
 * spam.
 */
#define I915_STATE_WARN(condition, format...) ({			\
	int __ret_warn_on = !!(condition);				\
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	if (unlikely(__ret_warn_on))					\
		if (!WARN(i915.verbose_state_checks, format))		\
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			DRM_ERROR(format);				\
	unlikely(__ret_warn_on);					\
})

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#define I915_STATE_WARN_ON(x)						\
	I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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bool __i915_inject_load_failure(const char *func, int line);
#define i915_inject_load_failure() \
	__i915_inject_load_failure(__func__, __LINE__)

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typedef struct {
	uint32_t val;
} uint_fixed_16_16_t;

#define FP_16_16_MAX ({ \
	uint_fixed_16_16_t fp; \
	fp.val = UINT_MAX; \
	fp; \
})

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static inline bool is_fixed16_zero(uint_fixed_16_16_t val)
{
	if (val.val == 0)
		return true;
	return false;
}

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static inline uint_fixed_16_16_t u32_to_fixed_16_16(uint32_t val)
{
	uint_fixed_16_16_t fp;

	WARN_ON(val >> 16);

	fp.val = val << 16;
	return fp;
}

static inline uint32_t fixed_16_16_to_u32_round_up(uint_fixed_16_16_t fp)
{
	return DIV_ROUND_UP(fp.val, 1 << 16);
}

static inline uint32_t fixed_16_16_to_u32(uint_fixed_16_16_t fp)
{
	return fp.val >> 16;
}

static inline uint_fixed_16_16_t min_fixed_16_16(uint_fixed_16_16_t min1,
						 uint_fixed_16_16_t min2)
{
	uint_fixed_16_16_t min;

	min.val = min(min1.val, min2.val);
	return min;
}

static inline uint_fixed_16_16_t max_fixed_16_16(uint_fixed_16_16_t max1,
						 uint_fixed_16_16_t max2)
{
	uint_fixed_16_16_t max;

	max.val = max(max1.val, max2.val);
	return max;
}

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static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val,
					    uint_fixed_16_16_t d)
{
	return DIV_ROUND_UP(val.val, d.val);
}

static inline uint32_t mul_round_up_u32_fixed16(uint32_t val,
						uint_fixed_16_16_t mul)
{
	uint64_t intermediate_val;
	uint32_t result;

	intermediate_val = (uint64_t) val * mul.val;
	intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16);
	WARN_ON(intermediate_val >> 32);
	result = clamp_t(uint32_t, intermediate_val, 0, ~0);
	return result;
}

static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val,
					     uint_fixed_16_16_t mul)
{
	uint64_t intermediate_val;
	uint_fixed_16_16_t fp;

	intermediate_val = (uint64_t) val.val * mul.val;
	intermediate_val = intermediate_val >> 16;
	WARN_ON(intermediate_val >> 32);
	fp.val = clamp_t(uint32_t, intermediate_val, 0, ~0);
	return fp;
}

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static inline uint_fixed_16_16_t fixed_16_16_div(uint32_t val, uint32_t d)
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{
	uint_fixed_16_16_t fp, res;

	fp = u32_to_fixed_16_16(val);
	res.val = DIV_ROUND_UP(fp.val, d);
	return res;
}

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static inline uint_fixed_16_16_t fixed_16_16_div_u64(uint32_t val, uint32_t d)
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{
	uint_fixed_16_16_t res;
	uint64_t interm_val;

	interm_val = (uint64_t)val << 16;
	interm_val = DIV_ROUND_UP_ULL(interm_val, d);
	WARN_ON(interm_val >> 32);
	res.val = (uint32_t) interm_val;

	return res;
}

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static inline uint32_t div_round_up_u32_fixed16(uint32_t val,
						uint_fixed_16_16_t d)
{
	uint64_t interm_val;

	interm_val = (uint64_t)val << 16;
	interm_val = DIV_ROUND_UP_ULL(interm_val, d.val);
	WARN_ON(interm_val >> 32);
	return clamp_t(uint32_t, interm_val, 0, ~0);
}

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static inline uint_fixed_16_16_t mul_u32_fixed_16_16(uint32_t val,
						     uint_fixed_16_16_t mul)
{
	uint64_t intermediate_val;
	uint_fixed_16_16_t fp;

	intermediate_val = (uint64_t) val * mul.val;
	WARN_ON(intermediate_val >> 32);
	fp.val = (uint32_t) intermediate_val;
	return fp;
}

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static inline const char *yesno(bool v)
{
	return v ? "yes" : "no";
}

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static inline const char *onoff(bool v)
{
	return v ? "on" : "off";
}

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static inline const char *enableddisabled(bool v)
{
	return v ? "enabled" : "disabled";
}

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enum pipe {
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	INVALID_PIPE = -1,
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	PIPE_A = 0,
	PIPE_B,
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	PIPE_C,
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	_PIPE_EDP,
	I915_MAX_PIPES = _PIPE_EDP
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};
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#define pipe_name(p) ((p) + 'A')
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enum transcoder {
	TRANSCODER_A = 0,
	TRANSCODER_B,
	TRANSCODER_C,
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	TRANSCODER_EDP,
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	TRANSCODER_DSI_A,
	TRANSCODER_DSI_C,
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	I915_MAX_TRANSCODERS
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};
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static inline const char *transcoder_name(enum transcoder transcoder)
{
	switch (transcoder) {
	case TRANSCODER_A:
		return "A";
	case TRANSCODER_B:
		return "B";
	case TRANSCODER_C:
		return "C";
	case TRANSCODER_EDP:
		return "EDP";
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	case TRANSCODER_DSI_A:
		return "DSI A";
	case TRANSCODER_DSI_C:
		return "DSI C";
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	default:
		return "<invalid>";
	}
}
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static inline bool transcoder_is_dsi(enum transcoder transcoder)
{
	return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
}

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/*
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 * Global legacy plane identifier. Valid only for primary/sprite
 * planes on pre-g4x, and only for primary planes on g4x+.
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 */
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enum plane {
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	PLANE_A,
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	PLANE_B,
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	PLANE_C,
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};
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#define plane_name(p) ((p) + 'A')
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#define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
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/*
 * Per-pipe plane identifier.
 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 * number of planes per CRTC.  Not all platforms really have this many planes,
 * which means some arrays of size I915_MAX_PLANES may have unused entries
 * between the topmost sprite plane and the cursor plane.
 *
 * This is expected to be passed to various register macros
 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
 */
enum plane_id {
	PLANE_PRIMARY,
	PLANE_SPRITE0,
	PLANE_SPRITE1,
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	PLANE_SPRITE2,
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	PLANE_CURSOR,
	I915_MAX_PLANES,
};

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#define for_each_plane_id_on_crtc(__crtc, __p) \
	for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
		for_each_if ((__crtc)->plane_ids_mask & BIT(__p))

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enum port {
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	PORT_NONE = -1,
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	PORT_A = 0,
	PORT_B,
	PORT_C,
	PORT_D,
	PORT_E,
	I915_MAX_PORTS
};
#define port_name(p) ((p) + 'A')

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#define I915_NUM_PHYS_VLV 2
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enum dpio_channel {
	DPIO_CH0,
	DPIO_CH1
};

enum dpio_phy {
	DPIO_PHY0,
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	DPIO_PHY1,
	DPIO_PHY2,
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};

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enum intel_display_power_domain {
	POWER_DOMAIN_PIPE_A,
	POWER_DOMAIN_PIPE_B,
	POWER_DOMAIN_PIPE_C,
	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
	POWER_DOMAIN_TRANSCODER_A,
	POWER_DOMAIN_TRANSCODER_B,
	POWER_DOMAIN_TRANSCODER_C,
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	POWER_DOMAIN_TRANSCODER_EDP,
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	POWER_DOMAIN_TRANSCODER_DSI_A,
	POWER_DOMAIN_TRANSCODER_DSI_C,
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	POWER_DOMAIN_PORT_DDI_A_LANES,
	POWER_DOMAIN_PORT_DDI_B_LANES,
	POWER_DOMAIN_PORT_DDI_C_LANES,
	POWER_DOMAIN_PORT_DDI_D_LANES,
	POWER_DOMAIN_PORT_DDI_E_LANES,
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	POWER_DOMAIN_PORT_DDI_A_IO,
	POWER_DOMAIN_PORT_DDI_B_IO,
	POWER_DOMAIN_PORT_DDI_C_IO,
	POWER_DOMAIN_PORT_DDI_D_IO,
	POWER_DOMAIN_PORT_DDI_E_IO,
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	POWER_DOMAIN_PORT_DSI,
	POWER_DOMAIN_PORT_CRT,
	POWER_DOMAIN_PORT_OTHER,
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	POWER_DOMAIN_VGA,
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	POWER_DOMAIN_AUDIO,
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	POWER_DOMAIN_PLLS,
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	POWER_DOMAIN_AUX_A,
	POWER_DOMAIN_AUX_B,
	POWER_DOMAIN_AUX_C,
	POWER_DOMAIN_AUX_D,
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	POWER_DOMAIN_GMBUS,
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	POWER_DOMAIN_MODESET,
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	POWER_DOMAIN_INIT,
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	POWER_DOMAIN_NUM,
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};

#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
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#define POWER_DOMAIN_TRANSCODER(tran) \
	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
	 (tran) + POWER_DOMAIN_TRANSCODER_A)
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enum hpd_pin {
	HPD_NONE = 0,
	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
	HPD_CRT,
	HPD_SDVO_B,
	HPD_SDVO_C,
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	HPD_PORT_A,
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	HPD_PORT_B,
	HPD_PORT_C,
	HPD_PORT_D,
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	HPD_PORT_E,
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	HPD_NUM_PINS
};

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#define for_each_hpd_pin(__pin) \
	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)

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#define HPD_STORM_DEFAULT_THRESHOLD 5

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struct i915_hotplug {
	struct work_struct hotplug_work;

	struct {
		unsigned long last_jiffies;
		int count;
		enum {
			HPD_ENABLED = 0,
			HPD_DISABLED = 1,
			HPD_MARK_DISABLED = 2
		} state;
	} stats[HPD_NUM_PINS];
	u32 event_bits;
	struct delayed_work reenable_work;

	struct intel_digital_port *irq_port[I915_MAX_PORTS];
	u32 long_port_mask;
	u32 short_port_mask;
	struct work_struct dig_port_work;

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	struct work_struct poll_init_work;
	bool poll_enabled;

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	unsigned int hpd_storm_threshold;

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	/*
	 * if we get a HPD irq from DP and a HPD irq from non-DP
	 * the non-DP HPD could block the workqueue on a mode config
	 * mutex getting, that userspace may have taken. However
	 * userspace is waiting on the DP workqueue to run which is
	 * blocked behind the non-DP one.
	 */
	struct workqueue_struct *dp_wq;
};

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#define I915_GEM_GPU_DOMAINS \
	(I915_GEM_DOMAIN_RENDER | \
	 I915_GEM_DOMAIN_SAMPLER | \
	 I915_GEM_DOMAIN_COMMAND | \
	 I915_GEM_DOMAIN_INSTRUCTION | \
	 I915_GEM_DOMAIN_VERTEX)
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#define for_each_pipe(__dev_priv, __p) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
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#define for_each_pipe_masked(__dev_priv, __p, __mask) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
		for_each_if ((__mask) & (1 << (__p)))
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#define for_each_universal_plane(__dev_priv, __pipe, __p)		\
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	for ((__p) = 0;							\
	     (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;	\
	     (__p)++)
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#define for_each_sprite(__dev_priv, __p, __s)				\
	for ((__s) = 0;							\
	     (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];	\
	     (__s)++)
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#define for_each_port_masked(__port, __ports_mask) \
	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	\
		for_each_if ((__ports_mask) & (1 << (__port)))

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#define for_each_crtc(dev, crtc) \
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	list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
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#define for_each_intel_plane(dev, intel_plane) \
	list_for_each_entry(intel_plane,			\
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			    &(dev)->mode_config.plane_list,	\
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			    base.head)

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#define for_each_intel_plane_mask(dev, intel_plane, plane_mask)		\
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	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
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			    base.head)					\
		for_each_if ((plane_mask) &				\
			     (1 << drm_plane_index(&intel_plane->base)))

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#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)	\
	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
			    base.head)					\
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		for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
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#define for_each_intel_crtc(dev, intel_crtc)				\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)
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#define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)		\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)					\
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		for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))

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#define for_each_intel_encoder(dev, intel_encoder)		\
	list_for_each_entry(intel_encoder,			\
			    &(dev)->mode_config.encoder_list,	\
			    base.head)

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#define for_each_intel_connector_iter(intel_connector, iter) \
	while ((intel_connector = to_intel_connector(drm_connector_list_iter_next(iter))))

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#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
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		for_each_if ((intel_encoder)->base.crtc == (__crtc))
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#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
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		for_each_if ((intel_connector)->base.encoder == (__encoder))
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#define for_each_power_domain(domain, mask)				\
	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
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		for_each_if (BIT_ULL(domain) & (mask))
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#define for_each_power_well(__dev_priv, __power_well)				\
	for ((__power_well) = (__dev_priv)->power_domains.power_wells;	\
	     (__power_well) - (__dev_priv)->power_domains.power_wells <	\
		(__dev_priv)->power_domains.power_well_count;		\
	     (__power_well)++)

#define for_each_power_well_rev(__dev_priv, __power_well)			\
	for ((__power_well) = (__dev_priv)->power_domains.power_wells +		\
			      (__dev_priv)->power_domains.power_well_count - 1;	\
	     (__power_well) - (__dev_priv)->power_domains.power_wells >= 0;	\
	     (__power_well)--)

#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask)	\
	for_each_power_well(__dev_priv, __power_well)				\
		for_each_if ((__power_well)->domains & (__domain_mask))

#define for_each_power_domain_well_rev(__dev_priv, __power_well, __domain_mask) \
	for_each_power_well_rev(__dev_priv, __power_well)		        \
		for_each_if ((__power_well)->domains & (__domain_mask))

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#define for_each_intel_plane_in_state(__state, plane, plane_state, __i) \
	for ((__i) = 0; \
	     (__i) < (__state)->base.dev->mode_config.num_total_plane && \
		     ((plane) = to_intel_plane((__state)->base.planes[__i].ptr), \
		      (plane_state) = to_intel_plane_state((__state)->base.planes[__i].state), 1); \
	     (__i)++) \
		for_each_if (plane_state)

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struct drm_i915_private;
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struct i915_mm_struct;
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struct i915_mmu_object;
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struct drm_i915_file_private {
	struct drm_i915_private *dev_priv;
	struct drm_file *file;

	struct {
		spinlock_t lock;
		struct list_head request_list;
577 578 579 580 581 582
/* 20ms is a fairly arbitrary limit (greater than the average frame time)
 * chosen to prevent the CPU getting more than a frame ahead of the GPU
 * (when using lax throttling for the frontbuffer). We also use it to
 * offer free GPU waitboosts for severely congested workloads.
 */
#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
583 584 585
	} mm;
	struct idr context_idr;

586 587 588 589
	struct intel_rps_client {
		struct list_head link;
		unsigned boosts;
	} rps;
590

591
	unsigned int bsd_engine;
592 593 594 595 596 597 598 599 600

/* Client can have a maximum of 3 contexts banned before
 * it is denied of creating new contexts. As one context
 * ban needs 4 consecutive hangs, and more if there is
 * progress in between, this is a last resort stop gap measure
 * to limit the badly behaving clients access to gpu.
 */
#define I915_MAX_CLIENT_CONTEXT_BANS 3
	int context_bans;
601 602
};

603 604 605 606 607 608 609 610 611 612 613 614 615
/* Used by dp and fdi links */
struct intel_link_m_n {
	uint32_t	tu;
	uint32_t	gmch_m;
	uint32_t	gmch_n;
	uint32_t	link_m;
	uint32_t	link_n;
};

void intel_link_compute_m_n(int bpp, int nlanes,
			    int pixel_clock, int link_clock,
			    struct intel_link_m_n *m_n);

L
Linus Torvalds 已提交
616 617 618
/* Interface history:
 *
 * 1.1: Original.
D
Dave Airlie 已提交
619 620
 * 1.2: Add Power Management
 * 1.3: Add vblank support
621
 * 1.4: Fix cmdbuffer path, add heap destroy
622
 * 1.5: Add vblank pipe configuration
=
=?utf-8?q?Michel_D=C3=A4nzer?= 已提交
623 624
 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
L
Linus Torvalds 已提交
625 626
 */
#define DRIVER_MAJOR		1
=
=?utf-8?q?Michel_D=C3=A4nzer?= 已提交
627
#define DRIVER_MINOR		6
L
Linus Torvalds 已提交
628 629
#define DRIVER_PATCHLEVEL	0

630 631 632 633 634
struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
struct opregion_asle;

635
struct intel_opregion {
636 637 638
	struct opregion_header *header;
	struct opregion_acpi *acpi;
	struct opregion_swsci *swsci;
J
Jani Nikula 已提交
639 640
	u32 swsci_gbda_sub_functions;
	u32 swsci_sbcb_sub_functions;
641
	struct opregion_asle *asle;
642
	void *rvda;
643
	const void *vbt;
644
	u32 vbt_size;
645
	u32 *lid_state;
646
	struct work_struct asle_work;
647
};
648
#define OPREGION_SIZE            (8*1024)
649

650 651 652
struct intel_overlay;
struct intel_overlay_error_state;

653
struct sdvo_device_mapping {
C
Chris Wilson 已提交
654
	u8 initialized;
655 656 657
	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
C
Chris Wilson 已提交
658
	u8 i2c_pin;
659
	u8 ddc_pin;
660 661
};

662
struct intel_connector;
663
struct intel_encoder;
664
struct intel_atomic_state;
665
struct intel_crtc_state;
666
struct intel_initial_plane_config;
667
struct intel_crtc;
668 669
struct intel_limit;
struct dpll;
670
struct intel_cdclk_state;
671

672
struct drm_i915_display_funcs {
673 674
	void (*get_cdclk)(struct drm_i915_private *dev_priv,
			  struct intel_cdclk_state *cdclk_state);
675 676
	void (*set_cdclk)(struct drm_i915_private *dev_priv,
			  const struct intel_cdclk_state *cdclk_state);
677
	int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
678
	int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
679 680 681
	int (*compute_intermediate_wm)(struct drm_device *dev,
				       struct intel_crtc *intel_crtc,
				       struct intel_crtc_state *newstate);
682 683 684 685 686 687
	void (*initial_watermarks)(struct intel_atomic_state *state,
				   struct intel_crtc_state *cstate);
	void (*atomic_update_watermarks)(struct intel_atomic_state *state,
					 struct intel_crtc_state *cstate);
	void (*optimize_watermarks)(struct intel_atomic_state *state,
				    struct intel_crtc_state *cstate);
688
	int (*compute_global_watermarks)(struct drm_atomic_state *state);
689
	void (*update_wm)(struct intel_crtc *crtc);
690
	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
691 692 693
	/* Returns the active state of the crtc, and if the crtc is active,
	 * fills out the pipe-config with the hw state. */
	bool (*get_pipe_config)(struct intel_crtc *,
694
				struct intel_crtc_state *);
695 696
	void (*get_initial_plane_config)(struct intel_crtc *,
					 struct intel_initial_plane_config *);
697 698
	int (*crtc_compute_clock)(struct intel_crtc *crtc,
				  struct intel_crtc_state *crtc_state);
699 700 701 702
	void (*crtc_enable)(struct intel_crtc_state *pipe_config,
			    struct drm_atomic_state *old_state);
	void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
			     struct drm_atomic_state *old_state);
703 704
	void (*update_crtcs)(struct drm_atomic_state *state,
			     unsigned int *crtc_vblank_mask);
705 706
	void (*audio_codec_enable)(struct drm_connector *connector,
				   struct intel_encoder *encoder,
707
				   const struct drm_display_mode *adjusted_mode);
708
	void (*audio_codec_disable)(struct intel_encoder *encoder);
709 710
	void (*fdi_link_train)(struct intel_crtc *crtc,
			       const struct intel_crtc_state *crtc_state);
711
	void (*init_clock_gating)(struct drm_i915_private *dev_priv);
712 713 714 715 716
	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
			  struct drm_framebuffer *fb,
			  struct drm_i915_gem_object *obj,
			  struct drm_i915_gem_request *req,
			  uint32_t flags);
717
	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
718 719 720 721 722
	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
723

724 725
	void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
	void (*load_luts)(struct drm_crtc_state *crtc_state);
726 727
};

728 729 730 731
#define CSR_VERSION(major, minor)	((major) << 16 | (minor))
#define CSR_VERSION_MAJOR(version)	((version) >> 16)
#define CSR_VERSION_MINOR(version)	((version) & 0xffff)

732
struct intel_csr {
733
	struct work_struct work;
734
	const char *fw_path;
735
	uint32_t *dmc_payload;
736
	uint32_t dmc_fw_size;
737
	uint32_t version;
738
	uint32_t mmio_count;
739
	i915_reg_t mmioaddr[8];
740
	uint32_t mmiodata[8];
741
	uint32_t dc_state;
742
	uint32_t allowed_dc_mask;
743 744
};

745 746
#define DEV_INFO_FOR_EACH_FLAG(func) \
	func(is_mobile); \
747
	func(is_lp); \
748
	func(is_alpha_support); \
749
	/* Keep has_* in alphabetical order */ \
750
	func(has_64bit_reloc); \
751
	func(has_aliasing_ppgtt); \
752
	func(has_csr); \
753
	func(has_ddi); \
754
	func(has_dp_mst); \
755 756
	func(has_fbc); \
	func(has_fpga_dbg); \
757 758
	func(has_full_ppgtt); \
	func(has_full_48bit_ppgtt); \
759 760 761
	func(has_gmbus_irq); \
	func(has_gmch_display); \
	func(has_guc); \
762
	func(has_guc_ct); \
763
	func(has_hotplug); \
764
	func(has_l3_dpf); \
765
	func(has_llc); \
766 767 768 769 770 771 772 773 774
	func(has_logical_ring_contexts); \
	func(has_overlay); \
	func(has_pipe_cxsr); \
	func(has_pooled_eu); \
	func(has_psr); \
	func(has_rc6); \
	func(has_rc6p); \
	func(has_resource_streamer); \
	func(has_runtime_pm); \
775
	func(has_snoop); \
776
	func(unfenced_needs_alignment); \
777 778 779
	func(cursor_needs_physical); \
	func(hws_needs_physical); \
	func(overlay_needs_physical); \
780
	func(supports_tv);
D
Daniel Vetter 已提交
781

782
struct sseu_dev_info {
783
	u8 slice_mask;
784
	u8 subslice_mask;
785 786
	u8 eu_total;
	u8 eu_per_subslice;
787 788 789 790 791 792
	u8 min_eu_in_pool;
	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
	u8 subslice_7eu[3];
	u8 has_slice_pg:1;
	u8 has_subslice_pg:1;
	u8 has_eu_pg:1;
793 794
};

795 796 797 798 799
static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
{
	return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
}

800 801 802 803 804 805 806 807 808 809 810 811 812
/* Keep in gen based order, and chronological order within a gen */
enum intel_platform {
	INTEL_PLATFORM_UNINITIALIZED = 0,
	INTEL_I830,
	INTEL_I845G,
	INTEL_I85X,
	INTEL_I865G,
	INTEL_I915G,
	INTEL_I915GM,
	INTEL_I945G,
	INTEL_I945GM,
	INTEL_G33,
	INTEL_PINEVIEW,
813 814
	INTEL_I965G,
	INTEL_I965GM,
815 816
	INTEL_G45,
	INTEL_GM45,
817 818 819 820 821 822 823 824 825 826 827
	INTEL_IRONLAKE,
	INTEL_SANDYBRIDGE,
	INTEL_IVYBRIDGE,
	INTEL_VALLEYVIEW,
	INTEL_HASWELL,
	INTEL_BROADWELL,
	INTEL_CHERRYVIEW,
	INTEL_SKYLAKE,
	INTEL_BROXTON,
	INTEL_KABYLAKE,
	INTEL_GEMINILAKE,
828
	INTEL_CANNONLAKE,
829
	INTEL_MAX_PLATFORMS
830 831
};

832
struct intel_device_info {
833
	u32 display_mmio_offset;
834
	u16 device_id;
835
	u8 num_pipes;
836
	u8 num_sprites[I915_MAX_PIPES];
837
	u8 num_scalers[I915_MAX_PIPES];
838
	u8 gen;
839
	u16 gen_mask;
840
	enum intel_platform platform;
841
	u8 ring_mask; /* Rings supported by the HW */
842
	u8 num_rings;
843 844 845
#define DEFINE_FLAG(name) u8 name:1
	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
846
	u16 ddb_size; /* in blocks */
847 848 849 850
	/* Register offsets for the various display pipes and transcoders */
	int pipe_offsets[I915_MAX_TRANSCODERS];
	int trans_offsets[I915_MAX_TRANSCODERS];
	int palette_offsets[I915_MAX_PIPES];
851
	int cursor_offsets[I915_MAX_PIPES];
852 853

	/* Slice/subslice/EU info */
854
	struct sseu_dev_info sseu;
855 856 857 858 859

	struct color_luts {
		u16 degamma_lut_size;
		u16 gamma_lut_size;
	} color;
860 861
};

862 863
struct intel_display_error_state;

864
struct i915_gpu_state {
865 866
	struct kref ref;
	struct timeval time;
867 868
	struct timeval boottime;
	struct timeval uptime;
869

870 871
	struct drm_i915_private *i915;

872 873
	char error_msg[128];
	bool simulated;
874
	bool awake;
875 876
	bool wakelock;
	bool suspended;
877 878 879 880
	int iommu;
	u32 reset_count;
	u32 suspend_count;
	struct intel_device_info device_info;
881
	struct i915_params params;
882 883 884 885 886

	/* Generic register state */
	u32 eir;
	u32 pgtbl_er;
	u32 ier;
887
	u32 gtier[4], ngtier;
888 889 890 891 892 893 894 895 896 897 898 899
	u32 ccid;
	u32 derrmr;
	u32 forcewake;
	u32 error; /* gen6+ */
	u32 err_int; /* gen7 */
	u32 fault_data0; /* gen8, gen9 */
	u32 fault_data1; /* gen8, gen9 */
	u32 done_reg;
	u32 gac_eco;
	u32 gam_ecochk;
	u32 gab_ctl;
	u32 gfx_mode;
900

901
	u32 nfence;
902 903 904
	u64 fence[I915_MAX_NUM_FENCES];
	struct intel_overlay_error_state *overlay;
	struct intel_display_error_state *display;
905
	struct drm_i915_error_object *semaphore;
906
	struct drm_i915_error_object *guc_log;
907 908 909 910 911 912

	struct drm_i915_error_engine {
		int engine_id;
		/* Software tracked state */
		bool waiting;
		int num_waiters;
913 914
		unsigned long hangcheck_timestamp;
		bool hangcheck_stalled;
915 916 917 918
		enum intel_engine_hangcheck_action hangcheck_action;
		struct i915_address_space *vm;
		int num_requests;

919 920 921
		/* position of active request inside the ring */
		u32 rq_head, rq_post, rq_tail;

922 923 924 925 926 927 928 929 930 931 932
		/* our own tracking of ring head and tail */
		u32 cpu_ring_head;
		u32 cpu_ring_tail;

		u32 last_seqno;

		/* Register state */
		u32 start;
		u32 tail;
		u32 head;
		u32 ctl;
933
		u32 mode;
934 935 936 937 938 939 940 941 942 943 944 945 946
		u32 hws;
		u32 ipeir;
		u32 ipehr;
		u32 bbstate;
		u32 instpm;
		u32 instps;
		u32 seqno;
		u64 bbaddr;
		u64 acthd;
		u32 fault_reg;
		u64 faddr;
		u32 rc_psmi; /* sleep state */
		u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
947
		struct intel_instdone instdone;
948

949 950 951 952 953 954 955 956 957 958
		struct drm_i915_error_context {
			char comm[TASK_COMM_LEN];
			pid_t pid;
			u32 handle;
			u32 hw_id;
			int ban_score;
			int active;
			int guilty;
		} context;

959 960
		struct drm_i915_error_object {
			u64 gtt_offset;
961
			u64 gtt_size;
962 963
			int page_count;
			int unused;
964 965 966
			u32 *pages[0];
		} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;

967 968 969
		struct drm_i915_error_object **user_bo;
		long user_bo_count;

970 971 972 973
		struct drm_i915_error_object *wa_ctx;

		struct drm_i915_error_request {
			long jiffies;
974
			pid_t pid;
975
			u32 context;
976
			int ban_score;
977 978 979
			u32 seqno;
			u32 head;
			u32 tail;
980
		} *requests, execlist[2];
981 982 983 984 985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015

		struct drm_i915_error_waiter {
			char comm[TASK_COMM_LEN];
			pid_t pid;
			u32 seqno;
		} *waiters;

		struct {
			u32 gfx_mode;
			union {
				u64 pdp[4];
				u32 pp_dir_base;
			};
		} vm_info;
	} engine[I915_NUM_ENGINES];

	struct drm_i915_error_buffer {
		u32 size;
		u32 name;
		u32 rseqno[I915_NUM_ENGINES], wseqno;
		u64 gtt_offset;
		u32 read_domains;
		u32 write_domain;
		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
		u32 tiling:2;
		u32 dirty:1;
		u32 purgeable:1;
		u32 userptr:1;
		s32 engine:4;
		u32 cache_level:3;
	} *active_bo[I915_NUM_ENGINES], *pinned_bo;
	u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
	struct i915_address_space *active_vm[I915_NUM_ENGINES];
};

1016 1017
enum i915_cache_level {
	I915_CACHE_NONE = 0,
1018 1019 1020 1021 1022
	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
			      caches, eg sampler/render caches, and the
			      large Last-Level-Cache. LLC is coherent with
			      the CPU, but L3 is only visible to the GPU. */
1023
	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
1024 1025
};

1026 1027
#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */

1028 1029 1030 1031 1032
enum fb_op_origin {
	ORIGIN_GTT,
	ORIGIN_CPU,
	ORIGIN_CS,
	ORIGIN_FLIP,
1033
	ORIGIN_DIRTYFB,
1034 1035
};

1036
struct intel_fbc {
P
Paulo Zanoni 已提交
1037 1038 1039
	/* This is always the inner lock when overlapping with struct_mutex and
	 * it's the outer lock when overlapping with stolen_lock. */
	struct mutex lock;
B
Ben Widawsky 已提交
1040
	unsigned threshold;
1041 1042
	unsigned int possible_framebuffer_bits;
	unsigned int busy_bits;
1043
	unsigned int visible_pipes_mask;
1044
	struct intel_crtc *crtc;
1045

1046
	struct drm_mm_node compressed_fb;
1047 1048
	struct drm_mm_node *compressed_llb;

1049 1050
	bool false_color;

1051
	bool enabled;
1052
	bool active;
1053

1054 1055 1056
	bool underrun_detected;
	struct work_struct underrun_work;

1057
	struct intel_fbc_state_cache {
1058 1059
		struct i915_vma *vma;

1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072
		struct {
			unsigned int mode_flags;
			uint32_t hsw_bdw_pixel_rate;
		} crtc;

		struct {
			unsigned int rotation;
			int src_w;
			int src_h;
			bool visible;
		} plane;

		struct {
1073
			const struct drm_format_info *format;
1074 1075 1076 1077
			unsigned int stride;
		} fb;
	} state_cache;

1078
	struct intel_fbc_reg_params {
1079 1080
		struct i915_vma *vma;

1081 1082 1083 1084 1085 1086 1087
		struct {
			enum pipe pipe;
			enum plane plane;
			unsigned int fence_y_offset;
		} crtc;

		struct {
1088
			const struct drm_format_info *format;
1089 1090 1091 1092 1093 1094
			unsigned int stride;
		} fb;

		int cfb_size;
	} params;

1095
	struct intel_fbc_work {
1096
		bool scheduled;
1097
		u32 scheduled_vblank;
1098 1099
		struct work_struct work;
	} work;
1100

1101
	const char *no_fbc_reason;
1102 1103
};

1104
/*
1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118
 * HIGH_RR is the highest eDP panel refresh rate read from EDID
 * LOW_RR is the lowest eDP panel refresh rate found from EDID
 * parsing for same resolution.
 */
enum drrs_refresh_rate_type {
	DRRS_HIGH_RR,
	DRRS_LOW_RR,
	DRRS_MAX_RR, /* RR count */
};

enum drrs_support_type {
	DRRS_NOT_SUPPORTED = 0,
	STATIC_DRRS_SUPPORT = 1,
	SEAMLESS_DRRS_SUPPORT = 2
1119 1120
};

1121
struct intel_dp;
1122 1123 1124 1125 1126 1127 1128 1129 1130
struct i915_drrs {
	struct mutex mutex;
	struct delayed_work work;
	struct intel_dp *dp;
	unsigned busy_frontbuffer_bits;
	enum drrs_refresh_rate_type refresh_rate_type;
	enum drrs_support_type type;
};

R
Rodrigo Vivi 已提交
1131
struct i915_psr {
1132
	struct mutex lock;
R
Rodrigo Vivi 已提交
1133 1134
	bool sink_support;
	bool source_ok;
1135
	struct intel_dp *enabled;
1136 1137
	bool active;
	struct delayed_work work;
1138
	unsigned busy_frontbuffer_bits;
1139 1140
	bool psr2_support;
	bool aux_frame_sync;
1141
	bool link_standby;
1142 1143
	bool y_cord_support;
	bool colorimetry_support;
1144
	bool alpm;
1145
};
1146

1147
enum intel_pch {
1148
	PCH_NONE = 0,	/* No PCH present */
1149 1150
	PCH_IBX,	/* Ibexpeak PCH */
	PCH_CPT,	/* Cougarpoint PCH */
1151
	PCH_LPT,	/* Lynxpoint PCH */
1152
	PCH_SPT,        /* Sunrisepoint PCH */
1153
	PCH_KBP,        /* Kabypoint PCH */
1154
	PCH_CNP,        /* Cannonpoint PCH */
B
Ben Widawsky 已提交
1155
	PCH_NOP,
1156 1157
};

1158 1159 1160 1161 1162
enum intel_sbi_destination {
	SBI_ICLK,
	SBI_MPHY,
};

1163
#define QUIRK_PIPEA_FORCE (1<<0)
1164
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
1165
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
1166
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
1167
#define QUIRK_PIPEB_FORCE (1<<4)
1168
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1169

1170
struct intel_fbdev;
1171
struct intel_fbc_work;
1172

1173 1174
struct intel_gmbus {
	struct i2c_adapter adapter;
1175
#define GMBUS_FORCE_BIT_RETRY (1U << 31)
1176
	u32 force_bit;
1177
	u32 reg0;
1178
	i915_reg_t gpio_reg;
1179
	struct i2c_algo_bit_data bit_algo;
1180 1181 1182
	struct drm_i915_private *dev_priv;
};

1183
struct i915_suspend_saved_registers {
1184
	u32 saveDSPARB;
J
Jesse Barnes 已提交
1185
	u32 saveFBC_CONTROL;
1186 1187
	u32 saveCACHE_MODE_0;
	u32 saveMI_ARB_STATE;
J
Jesse Barnes 已提交
1188 1189
	u32 saveSWF0[16];
	u32 saveSWF1[16];
1190
	u32 saveSWF3[3];
1191
	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1192
	u32 savePCH_PORT_HOTPLUG;
1193
	u16 saveGCDGMBUS;
1194
};
1195

1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253
struct vlv_s0ix_state {
	/* GAM */
	u32 wr_watermark;
	u32 gfx_prio_ctrl;
	u32 arb_mode;
	u32 gfx_pend_tlb0;
	u32 gfx_pend_tlb1;
	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
	u32 media_max_req_count;
	u32 gfx_max_req_count;
	u32 render_hwsp;
	u32 ecochk;
	u32 bsd_hwsp;
	u32 blt_hwsp;
	u32 tlb_rd_addr;

	/* MBC */
	u32 g3dctl;
	u32 gsckgctl;
	u32 mbctl;

	/* GCP */
	u32 ucgctl1;
	u32 ucgctl3;
	u32 rcgctl1;
	u32 rcgctl2;
	u32 rstctl;
	u32 misccpctl;

	/* GPM */
	u32 gfxpause;
	u32 rpdeuhwtc;
	u32 rpdeuc;
	u32 ecobus;
	u32 pwrdwnupctl;
	u32 rp_down_timeout;
	u32 rp_deucsw;
	u32 rcubmabdtmr;
	u32 rcedata;
	u32 spare2gh;

	/* Display 1 CZ domain */
	u32 gt_imr;
	u32 gt_ier;
	u32 pm_imr;
	u32 pm_ier;
	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

	/* GT SA CZ domain */
	u32 tilectl;
	u32 gt_fifoctl;
	u32 gtlc_wake_ctrl;
	u32 gtlc_survive;
	u32 pmwgicz;

	/* Display 2 CZ domain */
	u32 gu_ctl0;
	u32 gu_ctl1;
1254
	u32 pcbr;
1255 1256 1257
	u32 clock_gate_dis2;
};

1258
struct intel_rps_ei {
1259
	ktime_t ktime;
1260 1261
	u32 render_c0;
	u32 media_c0;
1262 1263
};

1264
struct intel_gen6_power_mgmt {
I
Imre Deak 已提交
1265 1266 1267 1268
	/*
	 * work, interrupts_enabled and pm_iir are protected by
	 * dev_priv->irq_lock
	 */
1269
	struct work_struct work;
I
Imre Deak 已提交
1270
	bool interrupts_enabled;
1271
	u32 pm_iir;
1272

1273
	/* PM interrupt bits that should never be masked */
1274
	u32 pm_intrmsk_mbz;
1275

1276 1277 1278 1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290
	/* Frequencies are stored in potentially platform dependent multiples.
	 * In other words, *_freq needs to be multiplied by X to be interesting.
	 * Soft limits are those which are used for the dynamic reclocking done
	 * by the driver (raise frequencies under heavy loads, and lower for
	 * lighter loads). Hard limits are those imposed by the hardware.
	 *
	 * A distinction is made for overclocking, which is never enabled by
	 * default, and is considered to be above the hard limit if it's
	 * possible at all.
	 */
	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
	u8 min_freq;		/* AKA RPn. Minimum frequency */
1291
	u8 boost_freq;		/* Frequency to request when wait boosting */
1292
	u8 idle_freq;		/* Frequency to request when we are idle */
1293 1294 1295
	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
	u8 rp1_freq;		/* "less than" RP0 power/freqency */
	u8 rp0_freq;		/* Non-overclocked max frequency. */
1296
	u16 gpll_ref_freq;	/* vlv/chv GPLL reference frequency */
1297

1298 1299 1300
	u8 up_threshold; /* Current %busy required to uplock */
	u8 down_threshold; /* Current %busy required to downclock */

1301 1302 1303
	int last_adj;
	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;

1304 1305 1306 1307
	spinlock_t client_lock;
	struct list_head clients;
	bool client_boost;

1308
	bool enabled;
1309
	struct delayed_work autoenable_work;
1310
	unsigned boosts;
1311

1312
	/* manual wa residency calculations */
1313
	struct intel_rps_ei ei;
1314

1315 1316
	/*
	 * Protects RPS/RC6 register access and PCU communication.
1317 1318 1319
	 * Must be taken after struct_mutex if nested. Note that
	 * this lock may be held for long periods of time when
	 * talking to hw - so only take it when talking to hw!
1320 1321
	 */
	struct mutex hw_lock;
1322 1323
};

D
Daniel Vetter 已提交
1324 1325 1326
/* defined intel_pm.c */
extern spinlock_t mchdev_lock;

1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337
struct intel_ilk_power_mgmt {
	u8 cur_delay;
	u8 min_delay;
	u8 max_delay;
	u8 fmax;
	u8 fstart;

	u64 last_count1;
	unsigned long last_time1;
	unsigned long chipset_power;
	u64 last_count2;
1338
	u64 last_time2;
1339 1340 1341 1342 1343 1344 1345
	unsigned long gfx_power;
	u8 corr;

	int c_m;
	int r_t;
};

1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375
struct drm_i915_private;
struct i915_power_well;

struct i915_power_well_ops {
	/*
	 * Synchronize the well's hw state to match the current sw state, for
	 * example enable/disable it based on the current refcount. Called
	 * during driver init and resume time, possibly after first calling
	 * the enable/disable handlers.
	 */
	void (*sync_hw)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/*
	 * Enable the well and resources that depend on it (for example
	 * interrupts located on the well). Called after the 0->1 refcount
	 * transition.
	 */
	void (*enable)(struct drm_i915_private *dev_priv,
		       struct i915_power_well *power_well);
	/*
	 * Disable the well and resources that depend on it. Called after
	 * the 1->0 refcount transition.
	 */
	void (*disable)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/* Returns the hw enabled state. */
	bool (*is_enabled)(struct drm_i915_private *dev_priv,
			   struct i915_power_well *power_well);
};

1376 1377
/* Power well structure for haswell */
struct i915_power_well {
1378
	const char *name;
1379
	bool always_on;
1380 1381
	/* power well enable/disable usage count */
	int count;
1382 1383
	/* cached hw enabled state */
	bool hw_enabled;
1384
	u64 domains;
1385 1386
	/* unique identifier for this power well */
	unsigned long id;
1387 1388 1389 1390 1391
	/*
	 * Arbitraty data associated with this power well. Platform and power
	 * well specific.
	 */
	unsigned long data;
1392
	const struct i915_power_well_ops *ops;
1393 1394
};

1395
struct i915_power_domains {
1396 1397 1398 1399 1400
	/*
	 * Power wells needed for initialization at driver init and suspend
	 * time are on. They are kept on until after the first modeset.
	 */
	bool init_power_on;
1401
	bool initializing;
1402
	int power_well_count;
1403

1404
	struct mutex lock;
1405
	int domain_use_count[POWER_DOMAIN_NUM];
1406
	struct i915_power_well *power_wells;
1407 1408
};

1409
#define MAX_L3_SLICES 2
1410
struct intel_l3_parity {
1411
	u32 *remap_info[MAX_L3_SLICES];
1412
	struct work_struct error_work;
1413
	int which_slice;
1414 1415
};

1416 1417 1418
struct i915_gem_mm {
	/** Memory allocator for GTT stolen memory */
	struct drm_mm stolen;
1419 1420 1421 1422
	/** Protects the usage of the GTT stolen memory allocator. This is
	 * always the inner lock when overlapping with struct_mutex. */
	struct mutex stolen_lock;

1423 1424 1425 1426 1427
	/** List of all objects in gtt_space. Used to restore gtt
	 * mappings on resume */
	struct list_head bound_list;
	/**
	 * List of objects which are not bound to the GTT (thus
1428 1429
	 * are idle and not used by the GPU). These objects may or may
	 * not actually have any pages attached.
1430 1431 1432
	 */
	struct list_head unbound_list;

1433 1434 1435 1436 1437
	/** List of all objects in gtt_space, currently mmaped by userspace.
	 * All objects within this list must also be on bound_list.
	 */
	struct list_head userfault_list;

1438 1439 1440 1441 1442 1443
	/**
	 * List of objects which are pending destruction.
	 */
	struct llist_head free_list;
	struct work_struct free_work;

1444
	/** Usable portion of the GTT for GEM */
1445
	dma_addr_t stolen_base; /* limited to low memory (32-bit) */
1446 1447 1448 1449

	/** PPGTT used for aliasing the PPGTT with the GTT */
	struct i915_hw_ppgtt *aliasing_ppgtt;

1450
	struct notifier_block oom_notifier;
1451
	struct notifier_block vmap_notifier;
1452
	struct shrinker shrinker;
1453 1454 1455 1456

	/** LRU list of objects with fence regs on them. */
	struct list_head fence_list;

1457 1458
	u64 unordered_timeline;

1459
	/* the indicator for dispatch video commands on two BSD rings */
1460
	atomic_t bsd_engine_dispatch_index;
1461

1462 1463 1464 1465 1466 1467
	/** Bit 6 swizzling required for X tiling */
	uint32_t bit_6_swizzle_x;
	/** Bit 6 swizzling required for Y tiling */
	uint32_t bit_6_swizzle_y;

	/* accounting, useful for userland debugging */
1468
	spinlock_t object_stat_lock;
1469
	u64 object_memory;
1470 1471 1472
	u32 object_count;
};

1473
struct drm_i915_error_state_buf {
1474
	struct drm_i915_private *i915;
1475 1476 1477 1478 1479 1480 1481 1482
	unsigned bytes;
	unsigned size;
	int err;
	u8 *buf;
	loff_t start;
	loff_t pos;
};

1483 1484 1485
#define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
#define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */

1486 1487 1488
#define I915_ENGINE_DEAD_TIMEOUT  (4 * HZ)  /* Seqno, head and subunits dead */
#define I915_SEQNO_DEAD_TIMEOUT   (12 * HZ) /* Seqno dead with active head */

1489 1490 1491 1492
struct i915_gpu_error {
	/* For hangcheck timer */
#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1493

1494
	struct delayed_work hangcheck_work;
1495 1496 1497 1498

	/* For reset and error_state handling. */
	spinlock_t lock;
	/* Protected by the above dev->gpu_error.lock. */
1499
	struct i915_gpu_state *first_error;
1500 1501 1502

	unsigned long missed_irq_rings;

1503
	/**
M
Mika Kuoppala 已提交
1504
	 * State variable controlling the reset flow and count
1505
	 *
M
Mika Kuoppala 已提交
1506
	 * This is a counter which gets incremented when reset is triggered,
1507
	 *
1508
	 * Before the reset commences, the I915_RESET_BACKOFF bit is set
1509 1510
	 * meaning that any waiters holding onto the struct_mutex should
	 * relinquish the lock immediately in order for the reset to start.
M
Mika Kuoppala 已提交
1511 1512 1513 1514 1515 1516 1517 1518 1519
	 *
	 * If reset is not completed succesfully, the I915_WEDGE bit is
	 * set meaning that hardware is terminally sour and there is no
	 * recovery. All waiters on the reset_queue will be woken when
	 * that happens.
	 *
	 * This counter is used by the wait_seqno code to notice that reset
	 * event happened and it needs to restart the entire ioctl (since most
	 * likely the seqno it waited for won't ever signal anytime soon).
1520 1521 1522 1523
	 *
	 * This is important for lock-free wait paths, where no contended lock
	 * naturally enforces the correct ordering between the bail-out of the
	 * waiter and the gpu reset work code.
1524
	 */
1525
	unsigned long reset_count;
1526

1527 1528 1529 1530 1531 1532 1533 1534 1535 1536 1537 1538 1539 1540 1541 1542 1543 1544 1545 1546 1547 1548 1549 1550
	/**
	 * flags: Control various stages of the GPU reset
	 *
	 * #I915_RESET_BACKOFF - When we start a reset, we want to stop any
	 * other users acquiring the struct_mutex. To do this we set the
	 * #I915_RESET_BACKOFF bit in the error flags when we detect a reset
	 * and then check for that bit before acquiring the struct_mutex (in
	 * i915_mutex_lock_interruptible()?). I915_RESET_BACKOFF serves a
	 * secondary role in preventing two concurrent global reset attempts.
	 *
	 * #I915_RESET_HANDOFF - To perform the actual GPU reset, we need the
	 * struct_mutex. We try to acquire the struct_mutex in the reset worker,
	 * but it may be held by some long running waiter (that we cannot
	 * interrupt without causing trouble). Once we are ready to do the GPU
	 * reset, we set the I915_RESET_HANDOFF bit and wakeup any waiters. If
	 * they already hold the struct_mutex and want to participate they can
	 * inspect the bit and do the reset directly, otherwise the worker
	 * waits for the struct_mutex.
	 *
	 * #I915_WEDGED - If reset fails and we can no longer use the GPU,
	 * we set the #I915_WEDGED bit. Prior to command submission, e.g.
	 * i915_gem_request_alloc(), this bit is checked and the sequence
	 * aborted (with -EIO reported to userspace) if set.
	 */
1551
	unsigned long flags;
1552 1553
#define I915_RESET_BACKOFF	0
#define I915_RESET_HANDOFF	1
1554
#define I915_WEDGED		(BITS_PER_LONG - 1)
1555

1556 1557 1558 1559 1560 1561
	/**
	 * Waitqueue to signal when a hang is detected. Used to for waiters
	 * to release the struct_mutex for the reset to procede.
	 */
	wait_queue_head_t wait_queue;

1562 1563 1564 1565 1566
	/**
	 * Waitqueue to signal when the reset has completed. Used by clients
	 * that wait for dev_priv->mm.wedged to settle.
	 */
	wait_queue_head_t reset_queue;
1567

1568
	/* For missed irq/seqno simulation. */
1569
	unsigned long test_irq_rings;
1570 1571
};

1572 1573 1574 1575 1576 1577
enum modeset_restore {
	MODESET_ON_LID_OPEN,
	MODESET_DONE,
	MODESET_SUSPENDED,
};

1578 1579 1580 1581 1582
#define DP_AUX_A 0x40
#define DP_AUX_B 0x10
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30

X
Xiong Zhang 已提交
1583 1584 1585 1586
#define DDC_PIN_B  0x05
#define DDC_PIN_C  0x04
#define DDC_PIN_D  0x06

1587
struct ddi_vbt_port_info {
1588 1589 1590 1591 1592 1593
	/*
	 * This is an index in the HDMI/DVI DDI buffer translation table.
	 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
	 * populate this field.
	 */
#define HDMI_LEVEL_SHIFT_UNKNOWN	0xff
1594
	uint8_t hdmi_level_shift;
1595 1596 1597 1598

	uint8_t supports_dvi:1;
	uint8_t supports_hdmi:1;
	uint8_t supports_dp:1;
1599
	uint8_t supports_edp:1;
1600 1601

	uint8_t alternate_aux_channel;
X
Xiong Zhang 已提交
1602
	uint8_t alternate_ddc_pin;
1603 1604 1605

	uint8_t dp_boost_level;
	uint8_t hdmi_boost_level;
1606 1607
};

R
Rodrigo Vivi 已提交
1608 1609 1610 1611 1612
enum psr_lines_to_wait {
	PSR_0_LINES_TO_WAIT = 0,
	PSR_1_LINE_TO_WAIT,
	PSR_4_LINES_TO_WAIT,
	PSR_8_LINES_TO_WAIT
1613 1614
};

1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626
struct intel_vbt_data {
	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits */
	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int lvds_vbt:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
	unsigned int display_clock_mode:1;
	unsigned int fdi_rx_polarity_inverted:1;
1627
	unsigned int panel_type:4;
1628 1629 1630
	int lvds_ssc_freq;
	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

1631 1632
	enum drrs_support_type drrs_type;

1633 1634 1635 1636 1637
	struct {
		int rate;
		int lanes;
		int preemphasis;
		int vswing;
1638
		bool low_vswing;
1639 1640 1641 1642 1643
		bool initialized;
		bool support;
		int bpp;
		struct edp_power_seq pps;
	} edp;
1644

R
Rodrigo Vivi 已提交
1645 1646 1647 1648 1649 1650 1651 1652 1653
	struct {
		bool full_link;
		bool require_aux_wakeup;
		int idle_frames;
		enum psr_lines_to_wait lines_to_wait;
		int tp1_wakeup_time;
		int tp2_tp3_wakeup_time;
	} psr;

1654 1655
	struct {
		u16 pwm_freq_hz;
1656
		bool present;
1657
		bool active_low_pwm;
1658
		u8 min_brightness;	/* min_brightness/255 of max */
1659
		u8 controller;		/* brightness controller number */
1660
		enum intel_backlight_type type;
1661 1662
	} backlight;

1663 1664 1665
	/* MIPI DSI */
	struct {
		u16 panel_id;
1666 1667 1668 1669 1670
		struct mipi_config *config;
		struct mipi_pps_data *pps;
		u8 seq_version;
		u32 size;
		u8 *data;
1671
		const u8 *sequence[MIPI_SEQ_MAX];
1672 1673
	} dsi;

1674 1675 1676
	int crt_ddc_pin;

	int child_dev_num;
1677
	union child_device_config *child_dev;
1678 1679

	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1680
	struct sdvo_device_mapping sdvo_mappings[2];
1681 1682
};

1683 1684 1685 1686 1687
enum intel_ddb_partitioning {
	INTEL_DDB_PART_1_2,
	INTEL_DDB_PART_5_6, /* IVB+ */
};

1688 1689 1690 1691 1692 1693 1694 1695
struct intel_wm_level {
	bool enable;
	uint32_t pri_val;
	uint32_t spr_val;
	uint32_t cur_val;
	uint32_t fbc_val;
};

1696
struct ilk_wm_values {
1697 1698 1699 1700 1701 1702 1703 1704
	uint32_t wm_pipe[3];
	uint32_t wm_lp[3];
	uint32_t wm_lp_spr[3];
	uint32_t wm_linetime[3];
	bool enable_fbc_wm;
	enum intel_ddb_partitioning partitioning;
};

1705
struct g4x_pipe_wm {
1706
	uint16_t plane[I915_MAX_PLANES];
1707
	uint16_t fbc;
1708
};
1709

1710
struct g4x_sr_wm {
1711
	uint16_t plane;
1712
	uint16_t cursor;
1713
	uint16_t fbc;
1714 1715 1716 1717
};

struct vlv_wm_ddl_values {
	uint8_t plane[I915_MAX_PLANES];
1718
};
1719

1720
struct vlv_wm_values {
1721 1722
	struct g4x_pipe_wm pipe[3];
	struct g4x_sr_wm sr;
1723
	struct vlv_wm_ddl_values ddl[3];
1724 1725
	uint8_t level;
	bool cxsr;
1726 1727
};

1728 1729 1730 1731 1732 1733 1734 1735 1736
struct g4x_wm_values {
	struct g4x_pipe_wm pipe[2];
	struct g4x_sr_wm sr;
	struct g4x_sr_wm hpll;
	bool cxsr;
	bool hpll_en;
	bool fbc_en;
};

1737
struct skl_ddb_entry {
1738
	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
1739 1740 1741 1742
};

static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
{
1743
	return entry->end - entry->start;
1744 1745
}

1746 1747 1748 1749 1750 1751 1752 1753 1754
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
				       const struct skl_ddb_entry *e2)
{
	if (e1->start == e2->start && e1->end == e2->end)
		return true;

	return false;
}

1755
struct skl_ddb_allocation {
1756
	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1757
	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1758 1759
};

1760
struct skl_wm_values {
1761
	unsigned dirty_pipes;
1762
	struct skl_ddb_allocation ddb;
1763 1764 1765
};

struct skl_wm_level {
L
Lyude 已提交
1766 1767 1768
	bool plane_en;
	uint16_t plane_res_b;
	uint8_t plane_res_l;
1769 1770
};

1771
/*
1772 1773 1774 1775
 * This struct helps tracking the state needed for runtime PM, which puts the
 * device in PCI D3 state. Notice that when this happens, nothing on the
 * graphics device works, even register access, so we don't get interrupts nor
 * anything else.
1776
 *
1777 1778 1779
 * Every piece of our code that needs to actually touch the hardware needs to
 * either call intel_runtime_pm_get or call intel_display_power_get with the
 * appropriate power domain.
1780
 *
1781 1782
 * Our driver uses the autosuspend delay feature, which means we'll only really
 * suspend if we stay with zero refcount for a certain amount of time. The
1783
 * default value is currently very conservative (see intel_runtime_pm_enable), but
1784
 * it can be changed with the standard runtime PM files from sysfs.
1785 1786 1787 1788 1789
 *
 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
 * goes back to false exactly before we reenable the IRQs. We use this variable
 * to check if someone is trying to enable/disable IRQs while they're supposed
 * to be disabled. This shouldn't happen and we'll print some error messages in
1790
 * case it happens.
1791
 *
1792
 * For more, read the Documentation/power/runtime_pm.txt.
1793
 */
1794
struct i915_runtime_pm {
1795
	atomic_t wakeref_count;
1796
	bool suspended;
1797
	bool irqs_enabled;
1798 1799
};

1800 1801 1802 1803 1804
enum intel_pipe_crc_source {
	INTEL_PIPE_CRC_SOURCE_NONE,
	INTEL_PIPE_CRC_SOURCE_PLANE1,
	INTEL_PIPE_CRC_SOURCE_PLANE2,
	INTEL_PIPE_CRC_SOURCE_PF,
1805
	INTEL_PIPE_CRC_SOURCE_PIPE,
D
Daniel Vetter 已提交
1806 1807 1808 1809 1810
	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
	INTEL_PIPE_CRC_SOURCE_TV,
	INTEL_PIPE_CRC_SOURCE_DP_B,
	INTEL_PIPE_CRC_SOURCE_DP_C,
	INTEL_PIPE_CRC_SOURCE_DP_D,
1811
	INTEL_PIPE_CRC_SOURCE_AUTO,
1812 1813 1814
	INTEL_PIPE_CRC_SOURCE_MAX,
};

1815
struct intel_pipe_crc_entry {
1816
	uint32_t frame;
1817 1818 1819
	uint32_t crc[5];
};

1820
#define INTEL_PIPE_CRC_ENTRIES_NR	128
1821
struct intel_pipe_crc {
1822 1823
	spinlock_t lock;
	bool opened;		/* exclusive access to the result file */
1824
	struct intel_pipe_crc_entry *entries;
1825
	enum intel_pipe_crc_source source;
1826
	int head, tail;
1827
	wait_queue_head_t wq;
T
Tomeu Vizoso 已提交
1828
	int skipped;
1829 1830
};

1831
struct i915_frontbuffer_tracking {
1832
	spinlock_t lock;
1833 1834 1835 1836 1837 1838 1839 1840 1841

	/*
	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
	 * scheduled flips.
	 */
	unsigned busy_bits;
	unsigned flip_bits;
};

1842
struct i915_wa_reg {
1843
	i915_reg_t addr;
1844 1845 1846 1847 1848
	u32 value;
	/* bitmask representing WA bits */
	u32 mask;
};

1849 1850 1851 1852 1853 1854 1855
/*
 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
 * allowing it for RCS as we don't foresee any requirement of having
 * a whitelist for other engines. When it is really required for
 * other engines then the limit need to be increased.
 */
#define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1856 1857 1858 1859

struct i915_workarounds {
	struct i915_wa_reg reg[I915_MAX_WA_REGS];
	u32 count;
1860
	u32 hw_whitelist_count[I915_NUM_ENGINES];
1861 1862
};

1863 1864 1865 1866
struct i915_virtual_gpu {
	bool active;
};

1867 1868 1869 1870 1871 1872 1873
/* used in computing the new watermarks state */
struct intel_wm_config {
	unsigned int num_pipes_active;
	bool sprites_enabled;
	bool sprites_scaled;
};

1874 1875 1876 1877 1878
struct i915_oa_format {
	u32 format;
	int size;
};

1879 1880 1881 1882 1883
struct i915_oa_reg {
	i915_reg_t addr;
	u32 value;
};

1884 1885
struct i915_perf_stream;

1886 1887 1888
/**
 * struct i915_perf_stream_ops - the OPs to support a specific stream type
 */
1889
struct i915_perf_stream_ops {
1890 1891 1892 1893
	/**
	 * @enable: Enables the collection of HW samples, either in response to
	 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
	 * without `I915_PERF_FLAG_DISABLED`.
1894 1895 1896
	 */
	void (*enable)(struct i915_perf_stream *stream);

1897 1898 1899 1900
	/**
	 * @disable: Disables the collection of HW samples, either in response
	 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
	 * the stream.
1901 1902 1903
	 */
	void (*disable)(struct i915_perf_stream *stream);

1904 1905
	/**
	 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1906 1907 1908 1909 1910 1911
	 * once there is something ready to read() for the stream
	 */
	void (*poll_wait)(struct i915_perf_stream *stream,
			  struct file *file,
			  poll_table *wait);

1912 1913 1914
	/**
	 * @wait_unlocked: For handling a blocking read, wait until there is
	 * something to ready to read() for the stream. E.g. wait on the same
1915
	 * wait queue that would be passed to poll_wait().
1916 1917 1918
	 */
	int (*wait_unlocked)(struct i915_perf_stream *stream);

1919 1920 1921 1922 1923 1924 1925
	/**
	 * @read: Copy buffered metrics as records to userspace
	 * **buf**: the userspace, destination buffer
	 * **count**: the number of bytes to copy, requested by userspace
	 * **offset**: zero at the start of the read, updated as the read
	 * proceeds, it represents how many bytes have been copied so far and
	 * the buffer offset for copying the next record.
1926
	 *
1927 1928
	 * Copy as many buffered i915 perf samples and records for this stream
	 * to userspace as will fit in the given buffer.
1929
	 *
1930 1931
	 * Only write complete records; returning -%ENOSPC if there isn't room
	 * for a complete record.
1932
	 *
1933 1934 1935
	 * Return any error condition that results in a short read such as
	 * -%ENOSPC or -%EFAULT, even though these may be squashed before
	 * returning to userspace.
1936 1937 1938 1939 1940 1941
	 */
	int (*read)(struct i915_perf_stream *stream,
		    char __user *buf,
		    size_t count,
		    size_t *offset);

1942 1943
	/**
	 * @destroy: Cleanup any stream specific resources.
1944 1945 1946 1947 1948 1949
	 *
	 * The stream will always be disabled before this is called.
	 */
	void (*destroy)(struct i915_perf_stream *stream);
};

1950 1951 1952
/**
 * struct i915_perf_stream - state for a single open stream FD
 */
1953
struct i915_perf_stream {
1954 1955 1956
	/**
	 * @dev_priv: i915 drm device
	 */
1957 1958
	struct drm_i915_private *dev_priv;

1959 1960 1961
	/**
	 * @link: Links the stream into ``&drm_i915_private->streams``
	 */
1962 1963
	struct list_head link;

1964 1965 1966 1967 1968
	/**
	 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
	 * properties given when opening a stream, representing the contents
	 * of a single sample as read() by userspace.
	 */
1969
	u32 sample_flags;
1970 1971 1972 1973 1974 1975

	/**
	 * @sample_size: Considering the configured contents of a sample
	 * combined with the required header size, this is the total size
	 * of a single sample record.
	 */
1976
	int sample_size;
1977

1978 1979 1980 1981
	/**
	 * @ctx: %NULL if measuring system-wide across all contexts or a
	 * specific context that is being monitored.
	 */
1982
	struct i915_gem_context *ctx;
1983 1984 1985 1986 1987 1988

	/**
	 * @enabled: Whether the stream is currently enabled, considering
	 * whether the stream was opened in a disabled state and based
	 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
	 */
1989 1990
	bool enabled;

1991 1992 1993 1994
	/**
	 * @ops: The callbacks providing the implementation of this specific
	 * type of configured stream.
	 */
1995 1996 1997
	const struct i915_perf_stream_ops *ops;
};

1998 1999 2000
/**
 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
 */
2001
struct i915_oa_ops {
2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016
	/**
	 * @init_oa_buffer: Resets the head and tail pointers of the
	 * circular buffer for periodic OA reports.
	 *
	 * Called when first opening a stream for OA metrics, but also may be
	 * called in response to an OA buffer overflow or other error
	 * condition.
	 *
	 * Note it may be necessary to clear the full OA buffer here as part of
	 * maintaining the invariable that new reports must be written to
	 * zeroed memory for us to be able to reliable detect if an expected
	 * report has not yet landed in memory.  (At least on Haswell the OA
	 * buffer tail pointer is not synchronized with reports being visible
	 * to the CPU)
	 */
2017
	void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
2018 2019 2020 2021 2022 2023 2024

	/**
	 * @enable_metric_set: Applies any MUX configuration to set up the
	 * Boolean and Custom (B/C) counters that are part of the counter
	 * reports being sampled. May apply system constraints such as
	 * disabling EU clock gating as required.
	 */
2025
	int (*enable_metric_set)(struct drm_i915_private *dev_priv);
2026 2027 2028 2029 2030

	/**
	 * @disable_metric_set: Remove system constraints associated with using
	 * the OA unit.
	 */
2031
	void (*disable_metric_set)(struct drm_i915_private *dev_priv);
2032 2033 2034 2035

	/**
	 * @oa_enable: Enable periodic sampling
	 */
2036
	void (*oa_enable)(struct drm_i915_private *dev_priv);
2037 2038 2039 2040

	/**
	 * @oa_disable: Disable periodic sampling
	 */
2041
	void (*oa_disable)(struct drm_i915_private *dev_priv);
2042 2043 2044 2045 2046

	/**
	 * @read: Copy data from the circular OA buffer into a given userspace
	 * buffer.
	 */
2047 2048 2049 2050
	int (*read)(struct i915_perf_stream *stream,
		    char __user *buf,
		    size_t count,
		    size_t *offset);
2051 2052

	/**
2053
	 * @oa_buffer_check: Check for OA buffer data + update tail
2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065
	 *
	 * This is either called via fops or the poll check hrtimer (atomic
	 * ctx) without any locks taken.
	 *
	 * It's safe to read OA config state here unlocked, assuming that this
	 * is only called while the stream is enabled, while the global OA
	 * configuration can't be modified.
	 *
	 * Efficiency is more important than avoiding some false positives
	 * here, which will be handled gracefully - likely resulting in an
	 * %EAGAIN error for userspace.
	 */
2066
	bool (*oa_buffer_check)(struct drm_i915_private *dev_priv);
2067 2068
};

2069 2070 2071 2072
struct intel_cdclk_state {
	unsigned int cdclk, vco, ref;
};

2073
struct drm_i915_private {
2074 2075
	struct drm_device drm;

2076
	struct kmem_cache *objects;
2077
	struct kmem_cache *vmas;
2078
	struct kmem_cache *requests;
2079
	struct kmem_cache *dependencies;
2080
	struct kmem_cache *priorities;
2081

2082
	const struct intel_device_info info;
2083 2084 2085

	void __iomem *regs;

2086
	struct intel_uncore uncore;
2087

2088 2089
	struct i915_virtual_gpu vgpu;

2090
	struct intel_gvt *gvt;
2091

2092
	struct intel_huc huc;
2093 2094
	struct intel_guc guc;

2095 2096
	struct intel_csr csr;

2097
	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
2098

2099 2100 2101 2102 2103 2104 2105 2106 2107
	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
	 * controller on different i2c buses. */
	struct mutex gmbus_mutex;

	/**
	 * Base address of the gmbus and gpio block.
	 */
	uint32_t gpio_mmio_base;

2108 2109 2110
	/* MMIO base address for MIPI regs */
	uint32_t mipi_mmio_base;

2111 2112
	uint32_t psr_mmio_base;

2113 2114
	uint32_t pps_mmio_base;

2115 2116
	wait_queue_head_t gmbus_wait_queue;

2117
	struct pci_dev *bridge_dev;
2118
	struct i915_gem_context *kernel_context;
2119
	struct intel_engine_cs *engine[I915_NUM_ENGINES];
2120
	struct i915_vma *semaphore;
2121

2122
	struct drm_dma_handle *status_page_dmah;
2123 2124 2125 2126 2127
	struct resource mch_res;

	/* protects the irq masks */
	spinlock_t irq_lock;

2128 2129 2130
	/* protects the mmio flip data */
	spinlock_t mmio_flip_lock;

2131 2132
	bool display_irqs_enabled;

2133 2134 2135
	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
	struct pm_qos_request pm_qos;

V
Ville Syrjälä 已提交
2136 2137
	/* Sideband mailbox protection */
	struct mutex sb_lock;
2138 2139

	/** Cached value of IMR to avoid reads in updating the bitfield */
2140 2141 2142 2143
	union {
		u32 irq_mask;
		u32 de_irq_mask[I915_MAX_PIPES];
	};
2144
	u32 gt_irq_mask;
2145 2146
	u32 pm_imr;
	u32 pm_ier;
2147
	u32 pm_rps_events;
2148
	u32 pm_guc_events;
2149
	u32 pipestat_irq_mask[I915_MAX_PIPES];
2150

2151
	struct i915_hotplug hotplug;
2152
	struct intel_fbc fbc;
2153
	struct i915_drrs drrs;
2154
	struct intel_opregion opregion;
2155
	struct intel_vbt_data vbt;
2156

2157 2158
	bool preserve_bios_swizzle;

2159 2160 2161
	/* overlay */
	struct intel_overlay *overlay;

2162
	/* backlight registers and fields in struct intel_panel */
2163
	struct mutex backlight_lock;
2164

2165 2166 2167
	/* LVDS info */
	bool no_aux_handshake;

V
Ville Syrjälä 已提交
2168 2169 2170
	/* protects panel power sequencer state */
	struct mutex pps_mutex;

2171 2172 2173 2174
	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */

	unsigned int fsb_freq, mem_freq, is_ddr3;
2175
	unsigned int skl_preferred_vco_freq;
2176
	unsigned int max_cdclk_freq;
2177

M
Mika Kahola 已提交
2178
	unsigned int max_dotclk_freq;
2179
	unsigned int rawclk_freq;
2180
	unsigned int hpll_freq;
2181
	unsigned int czclk_freq;
2182

2183
	struct {
2184 2185 2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197
		/*
		 * The current logical cdclk state.
		 * See intel_atomic_state.cdclk.logical
		 *
		 * For reading holding any crtc lock is sufficient,
		 * for writing must hold all of them.
		 */
		struct intel_cdclk_state logical;
		/*
		 * The current actual cdclk state.
		 * See intel_atomic_state.cdclk.actual
		 */
		struct intel_cdclk_state actual;
		/* The current hardware cdclk state */
2198 2199
		struct intel_cdclk_state hw;
	} cdclk;
2200

2201 2202 2203 2204 2205 2206 2207
	/**
	 * wq - Driver workqueue for GEM.
	 *
	 * NOTE: Work items scheduled here are not allowed to grab any modeset
	 * locks, for otherwise the flushing done in the pageflip code will
	 * result in deadlocks.
	 */
2208 2209 2210 2211 2212 2213 2214
	struct workqueue_struct *wq;

	/* Display functions */
	struct drm_i915_display_funcs display;

	/* PCH chipset type */
	enum intel_pch pch_type;
2215
	unsigned short pch_id;
2216 2217 2218

	unsigned long quirks;

2219 2220
	enum modeset_restore modeset_restore;
	struct mutex modeset_restore_lock;
2221
	struct drm_atomic_state *modeset_restore_state;
2222
	struct drm_modeset_acquire_ctx reset_ctx;
2223

2224
	struct list_head vm_list; /* Global list of all address spaces */
2225
	struct i915_ggtt ggtt; /* VM representing the global address space */
B
Ben Widawsky 已提交
2226

2227
	struct i915_gem_mm mm;
2228 2229
	DECLARE_HASHTABLE(mm_structs, 7);
	struct mutex mm_lock;
2230

2231 2232 2233 2234 2235 2236 2237
	/* The hw wants to have a stable context identifier for the lifetime
	 * of the context (for OA, PASID, faults, etc). This is limited
	 * in execlists to 21 bits.
	 */
	struct ida context_hw_ida;
#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */

2238 2239
	/* Kernel Modesetting */

2240 2241
	struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
	struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2242 2243
	wait_queue_head_t pending_flip_queue;

2244 2245 2246 2247
#ifdef CONFIG_DEBUG_FS
	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif

2248
	/* dpll and cdclk state is protected by connection_mutex */
D
Daniel Vetter 已提交
2249 2250
	int num_shared_dpll;
	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2251
	const struct intel_dpll_mgr *dpll_mgr;
2252

2253 2254 2255 2256 2257 2258 2259
	/*
	 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
	 * Must be global rather than per dpll, because on some platforms
	 * plls share registers.
	 */
	struct mutex dpll_lock;

2260 2261 2262
	unsigned int active_crtcs;
	unsigned int min_pixclk[I915_MAX_PIPES];

2263
	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2264

2265
	struct i915_workarounds workarounds;
2266

2267 2268
	struct i915_frontbuffer_tracking fb_tracking;

2269 2270 2271 2272 2273
	struct intel_atomic_helper {
		struct llist_head free_list;
		struct work_struct free_work;
	} atomic_helper;

2274
	u16 orig_clock;
2275

2276
	bool mchbar_need_disable;
2277

2278 2279
	struct intel_l3_parity l3_parity;

B
Ben Widawsky 已提交
2280
	/* Cannot be determined by PCIID. You must always read a register. */
2281
	u32 edram_cap;
B
Ben Widawsky 已提交
2282

2283
	/* gen6+ rps state */
2284
	struct intel_gen6_power_mgmt rps;
2285

2286 2287
	/* ilk-only ips/rps state. Everything in here is protected by the global
	 * mchdev_lock in intel_pm.c */
2288
	struct intel_ilk_power_mgmt ips;
2289

2290
	struct i915_power_domains power_domains;
2291

R
Rodrigo Vivi 已提交
2292
	struct i915_psr psr;
2293

2294
	struct i915_gpu_error gpu_error;
2295

2296 2297
	struct drm_i915_gem_object *vlv_pctx;

2298
#ifdef CONFIG_DRM_FBDEV_EMULATION
2299 2300
	/* list of fbdev register on this device */
	struct intel_fbdev *fbdev;
2301
	struct work_struct fbdev_suspend_work;
2302
#endif
2303 2304

	struct drm_property *broadcast_rgb_property;
2305
	struct drm_property *force_audio_property;
2306

I
Imre Deak 已提交
2307
	/* hda/i915 audio component */
2308
	struct i915_audio_component *audio_component;
I
Imre Deak 已提交
2309
	bool audio_component_registered;
2310 2311 2312 2313 2314
	/**
	 * av_mutex - mutex for audio/video sync
	 *
	 */
	struct mutex av_mutex;
I
Imre Deak 已提交
2315

2316
	struct list_head context_list;
2317

2318
	u32 fdi_rx_config;
2319

2320
	/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2321
	u32 chv_phy_control;
2322 2323 2324 2325 2326 2327
	/*
	 * Shadows for CHV DPLL_MD regs to keep the state
	 * checker somewhat working in the presence hardware
	 * crappiness (can't read out DPLL_MD for pipes B & C).
	 */
	u32 chv_dpll_md[I915_MAX_PIPES];
2328
	u32 bxt_phy_grc;
2329

2330
	u32 suspend_count;
2331
	bool suspended_to_idle;
2332
	struct i915_suspend_saved_registers regfile;
2333
	struct vlv_s0ix_state vlv_s0ix_state;
2334

2335
	enum {
2336 2337 2338 2339 2340
		I915_SAGV_UNKNOWN = 0,
		I915_SAGV_DISABLED,
		I915_SAGV_ENABLED,
		I915_SAGV_NOT_CONTROLLED
	} sagv_status;
2341

2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353
	struct {
		/*
		 * Raw watermark latency values:
		 * in 0.1us units for WM0,
		 * in 0.5us units for WM1+.
		 */
		/* primary */
		uint16_t pri_latency[5];
		/* sprite */
		uint16_t spr_latency[5];
		/* cursor */
		uint16_t cur_latency[5];
2354 2355 2356 2357 2358 2359
		/*
		 * Raw watermark memory latency values
		 * for SKL for all 8 levels
		 * in 1us units.
		 */
		uint16_t skl_latency[8];
2360 2361

		/* current hardware state */
2362 2363 2364
		union {
			struct ilk_wm_values hw;
			struct skl_wm_values skl_hw;
2365
			struct vlv_wm_values vlv;
2366
			struct g4x_wm_values g4x;
2367
		};
2368 2369

		uint8_t max_level;
2370 2371 2372 2373 2374 2375 2376

		/*
		 * Should be held around atomic WM register writing; also
		 * protects * intel_crtc->wm.active and
		 * cstate->wm.need_postvbl_update.
		 */
		struct mutex wm_mutex;
2377 2378 2379 2380 2381 2382 2383

		/*
		 * Set during HW readout of watermarks/DDB.  Some platforms
		 * need to know when we're still using BIOS-provided values
		 * (which we don't fully trust).
		 */
		bool distrust_bios_wm;
2384 2385
	} wm;

2386 2387
	struct i915_runtime_pm pm;

2388 2389
	struct {
		bool initialized;
2390

2391
		struct kobject *metrics_kobj;
2392
		struct ctl_table_header *sysctl_header;
2393

2394 2395
		struct mutex lock;
		struct list_head streams;
2396

2397 2398
		spinlock_t hook_lock;

2399
		struct {
2400 2401 2402 2403 2404 2405 2406 2407
			struct i915_perf_stream *exclusive_stream;

			u32 specific_ctx_id;

			struct hrtimer poll_check_timer;
			wait_queue_head_t poll_wq;
			bool pollin;

2408 2409 2410 2411 2412 2413
			/**
			 * For rate limiting any notifications of spurious
			 * invalid OA reports
			 */
			struct ratelimit_state spurious_report_rs;

2414 2415 2416 2417
			bool periodic;
			int period_exponent;

			int metrics_set;
2418 2419 2420 2421 2422

			const struct i915_oa_reg *mux_regs;
			int mux_regs_len;
			const struct i915_oa_reg *b_counter_regs;
			int b_counter_regs_len;
2423 2424 2425 2426 2427 2428

			struct {
				struct i915_vma *vma;
				u8 *vaddr;
				int format;
				int format_size;
2429

2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482
				/**
				 * Locks reads and writes to all head/tail state
				 *
				 * Consider: the head and tail pointer state
				 * needs to be read consistently from a hrtimer
				 * callback (atomic context) and read() fop
				 * (user context) with tail pointer updates
				 * happening in atomic context and head updates
				 * in user context and the (unlikely)
				 * possibility of read() errors needing to
				 * reset all head/tail state.
				 *
				 * Note: Contention or performance aren't
				 * currently a significant concern here
				 * considering the relatively low frequency of
				 * hrtimer callbacks (5ms period) and that
				 * reads typically only happen in response to a
				 * hrtimer event and likely complete before the
				 * next callback.
				 *
				 * Note: This lock is not held *while* reading
				 * and copying data to userspace so the value
				 * of head observed in htrimer callbacks won't
				 * represent any partial consumption of data.
				 */
				spinlock_t ptr_lock;

				/**
				 * One 'aging' tail pointer and one 'aged'
				 * tail pointer ready to used for reading.
				 *
				 * Initial values of 0xffffffff are invalid
				 * and imply that an update is required
				 * (and should be ignored by an attempted
				 * read)
				 */
				struct {
					u32 offset;
				} tails[2];

				/**
				 * Index for the aged tail ready to read()
				 * data up to.
				 */
				unsigned int aged_tail_idx;

				/**
				 * A monotonic timestamp for when the current
				 * aging tail pointer was read; used to
				 * determine when it is old enough to trust.
				 */
				u64 aging_timestamp;

2483 2484 2485 2486 2487 2488 2489 2490 2491 2492
				/**
				 * Although we can always read back the head
				 * pointer register, we prefer to avoid
				 * trusting the HW state, just to avoid any
				 * risk that some hardware condition could
				 * somehow bump the head pointer unpredictably
				 * and cause us to forward the wrong OA buffer
				 * data to userspace.
				 */
				u32 head;
2493 2494 2495 2496 2497 2498 2499
			} oa_buffer;

			u32 gen7_latched_oastatus1;

			struct i915_oa_ops ops;
			const struct i915_oa_format *oa_formats;
			int n_builtin_sets;
2500
		} oa;
2501 2502
	} perf;

2503 2504
	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
	struct {
2505
		void (*resume)(struct drm_i915_private *);
2506
		void (*cleanup_engine)(struct intel_engine_cs *engine);
2507

2508 2509
		struct list_head timelines;
		struct i915_gem_timeline global_timeline;
2510
		u32 active_requests;
2511

2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537
		/**
		 * Is the GPU currently considered idle, or busy executing
		 * userspace requests? Whilst idle, we allow runtime power
		 * management to power down the hardware and display clocks.
		 * In order to reduce the effect on performance, there
		 * is a slight delay before we do so.
		 */
		bool awake;

		/**
		 * We leave the user IRQ off as much as possible,
		 * but this means that requests will finish and never
		 * be retired once the system goes idle. Set a timer to
		 * fire periodically while the ring is running. When it
		 * fires, go retire requests.
		 */
		struct delayed_work retire_work;

		/**
		 * When we detect an idle GPU, we want to turn on
		 * powersaving features. So once we see that there
		 * are no more requests outstanding and no more
		 * arrive within a small period of time, we fire
		 * off the idle_work.
		 */
		struct delayed_work idle_work;
2538 2539

		ktime_t last_init_time;
2540 2541
	} gt;

2542 2543 2544
	/* perform PHY state sanity checks? */
	bool chv_phy_assert[2];

M
Mahesh Kumar 已提交
2545 2546
	bool ipc_enabled;

2547 2548
	/* Used to save the pipe-to-encoder mapping for audio */
	struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2549

2550 2551 2552 2553 2554 2555
	/* necessary resource sharing with HDMI LPE audio driver. */
	struct {
		struct platform_device *platdev;
		int	irq;
	} lpe_audio;

2556 2557 2558 2559
	/*
	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
	 * will be rejected. Instead look for a better place.
	 */
2560
};
L
Linus Torvalds 已提交
2561

2562 2563
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
2564
	return container_of(dev, struct drm_i915_private, drm);
2565 2566
}

2567
static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
I
Imre Deak 已提交
2568
{
2569
	return to_i915(dev_get_drvdata(kdev));
I
Imre Deak 已提交
2570 2571
}

2572 2573 2574 2575 2576
static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
{
	return container_of(guc, struct drm_i915_private, guc);
}

A
Arkadiusz Hiler 已提交
2577 2578 2579 2580 2581
static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc)
{
	return container_of(huc, struct drm_i915_private, huc);
}

2582
/* Simple iterator over all initialised engines */
2583 2584 2585 2586 2587
#define for_each_engine(engine__, dev_priv__, id__) \
	for ((id__) = 0; \
	     (id__) < I915_NUM_ENGINES; \
	     (id__)++) \
		for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2588 2589

/* Iterator over subset of engines selected by mask */
2590 2591
#define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
	for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask;	\
2592
	     tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2593

2594 2595 2596 2597 2598 2599 2600
enum hdmi_force_audio {
	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
	HDMI_AUDIO_AUTO,		/* trust EDID */
	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
};

2601
#define I915_GTT_OFFSET_NONE ((u32)-1)
2602

2603 2604
/*
 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2605
 * considered to be the frontbuffer for the given plane interface-wise. This
2606 2607 2608 2609 2610
 * doesn't mean that the hw necessarily already scans it out, but that any
 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
 *
 * We have one bit per pipe and per scanout plane type.
 */
2611 2612
#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2613 2614 2615
#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
#define INTEL_FRONTBUFFER_CURSOR(pipe) \
2616 2617 2618
	(1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
	(1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2619
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2620
	(1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2621
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2622
	(0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2623

2624 2625 2626 2627 2628 2629 2630 2631 2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645 2646 2647 2648 2649
/*
 * Optimised SGL iterator for GEM objects
 */
static __always_inline struct sgt_iter {
	struct scatterlist *sgp;
	union {
		unsigned long pfn;
		dma_addr_t dma;
	};
	unsigned int curr;
	unsigned int max;
} __sgt_iter(struct scatterlist *sgl, bool dma) {
	struct sgt_iter s = { .sgp = sgl };

	if (s.sgp) {
		s.max = s.curr = s.sgp->offset;
		s.max += s.sgp->length;
		if (dma)
			s.dma = sg_dma_address(s.sgp);
		else
			s.pfn = page_to_pfn(sg_page(s.sgp));
	}

	return s;
}

2650 2651 2652 2653 2654 2655 2656 2657
static inline struct scatterlist *____sg_next(struct scatterlist *sg)
{
	++sg;
	if (unlikely(sg_is_chain(sg)))
		sg = sg_chain_ptr(sg);
	return sg;
}

2658 2659 2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671
/**
 * __sg_next - return the next scatterlist entry in a list
 * @sg:		The current sg entry
 *
 * Description:
 *   If the entry is the last, return NULL; otherwise, step to the next
 *   element in the array (@sg@+1). If that's a chain pointer, follow it;
 *   otherwise just return the pointer to the current element.
 **/
static inline struct scatterlist *__sg_next(struct scatterlist *sg)
{
#ifdef CONFIG_DEBUG_SG
	BUG_ON(sg->sg_magic != SG_MAGIC);
#endif
2672
	return sg_is_last(sg) ? NULL : ____sg_next(sg);
2673 2674
}

2675 2676 2677 2678 2679 2680 2681 2682 2683 2684
/**
 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
 * @__dmap:	DMA address (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_dma(__dmap, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, true);			\
	     ((__dmap) = (__iter).dma + (__iter).curr);			\
	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
2685
	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2686 2687 2688 2689 2690 2691 2692 2693 2694 2695 2696 2697

/**
 * for_each_sgt_page - iterate over the pages of the given sg_table
 * @__pp:	page pointer (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_page(__pp, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, false);		\
	     ((__pp) = (__iter).pfn == 0 ? NULL :			\
	      pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
2698
	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2699

2700 2701 2702 2703 2704 2705 2706
static inline const struct intel_device_info *
intel_info(const struct drm_i915_private *dev_priv)
{
	return &dev_priv->info;
}

#define INTEL_INFO(dev_priv)	intel_info((dev_priv))
2707

2708
#define INTEL_GEN(dev_priv)	((dev_priv)->info.gen)
2709
#define INTEL_DEVID(dev_priv)	((dev_priv)->info.device_id)
2710

2711
#define REVID_FOREVER		0xff
2712
#define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
2713 2714 2715 2716 2717 2718 2719

#define GEN_FOREVER (0)
/*
 * Returns true if Gen is in inclusive range [Start, End].
 *
 * Use GEN_FOREVER for unbound start and or end.
 */
2720
#define IS_GEN(dev_priv, s, e) ({ \
2721 2722 2723 2724 2725 2726 2727 2728 2729
	unsigned int __s = (s), __e = (e); \
	BUILD_BUG_ON(!__builtin_constant_p(s)); \
	BUILD_BUG_ON(!__builtin_constant_p(e)); \
	if ((__s) != GEN_FOREVER) \
		__s = (s) - 1; \
	if ((__e) == GEN_FOREVER) \
		__e = BITS_PER_LONG - 1; \
	else \
		__e = (e) - 1; \
2730
	!!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2731 2732
})

2733 2734 2735 2736 2737 2738 2739 2740
/*
 * Return true if revision is in range [since,until] inclusive.
 *
 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
 */
#define IS_REVID(p, since, until) \
	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))

2741 2742
#define IS_I830(dev_priv)	((dev_priv)->info.platform == INTEL_I830)
#define IS_I845G(dev_priv)	((dev_priv)->info.platform == INTEL_I845G)
2743
#define IS_I85X(dev_priv)	((dev_priv)->info.platform == INTEL_I85X)
2744
#define IS_I865G(dev_priv)	((dev_priv)->info.platform == INTEL_I865G)
2745
#define IS_I915G(dev_priv)	((dev_priv)->info.platform == INTEL_I915G)
2746 2747
#define IS_I915GM(dev_priv)	((dev_priv)->info.platform == INTEL_I915GM)
#define IS_I945G(dev_priv)	((dev_priv)->info.platform == INTEL_I945G)
2748
#define IS_I945GM(dev_priv)	((dev_priv)->info.platform == INTEL_I945GM)
2749 2750
#define IS_I965G(dev_priv)	((dev_priv)->info.platform == INTEL_I965G)
#define IS_I965GM(dev_priv)	((dev_priv)->info.platform == INTEL_I965GM)
2751 2752 2753
#define IS_G45(dev_priv)	((dev_priv)->info.platform == INTEL_G45)
#define IS_GM45(dev_priv)	((dev_priv)->info.platform == INTEL_GM45)
#define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))
2754 2755
#define IS_PINEVIEW_G(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa001)
#define IS_PINEVIEW_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa011)
2756
#define IS_PINEVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_PINEVIEW)
2757
#define IS_G33(dev_priv)	((dev_priv)->info.platform == INTEL_G33)
2758
#define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
2759
#define IS_IVYBRIDGE(dev_priv)	((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2760 2761 2762
#define IS_IVB_GT1(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0156 || \
				 INTEL_DEVID(dev_priv) == 0x0152 || \
				 INTEL_DEVID(dev_priv) == 0x015a)
2763 2764 2765 2766 2767 2768 2769 2770
#define IS_VALLEYVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_VALLEYVIEW)
#define IS_CHERRYVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_CHERRYVIEW)
#define IS_HASWELL(dev_priv)	((dev_priv)->info.platform == INTEL_HASWELL)
#define IS_BROADWELL(dev_priv)	((dev_priv)->info.platform == INTEL_BROADWELL)
#define IS_SKYLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_SKYLAKE)
#define IS_BROXTON(dev_priv)	((dev_priv)->info.platform == INTEL_BROXTON)
#define IS_KABYLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_KABYLAKE)
#define IS_GEMINILAKE(dev_priv)	((dev_priv)->info.platform == INTEL_GEMINILAKE)
2771
#define IS_CANNONLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_CANNONLAKE)
2772
#define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
2773 2774 2775 2776 2777 2778
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||	\
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||	\
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
V
Ville Syrjälä 已提交
2779
/* ULX machines are also considered ULT. */
2780 2781 2782 2783 2784 2785 2786 2787
#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
#define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
#define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2788
/* ULX machines are also considered ULT. */
2789 2790 2791 2792 2793 2794 2795 2796 2797 2798 2799 2800 2801 2802 2803 2804 2805 2806 2807 2808 2809 2810
#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
				 INTEL_DEVID(dev_priv) == 0x0A1E)
#define IS_SKL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x1906 || \
				 INTEL_DEVID(dev_priv) == 0x1913 || \
				 INTEL_DEVID(dev_priv) == 0x1916 || \
				 INTEL_DEVID(dev_priv) == 0x1921 || \
				 INTEL_DEVID(dev_priv) == 0x1926)
#define IS_SKL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x190E || \
				 INTEL_DEVID(dev_priv) == 0x1915 || \
				 INTEL_DEVID(dev_priv) == 0x191E)
#define IS_KBL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x5906 || \
				 INTEL_DEVID(dev_priv) == 0x5913 || \
				 INTEL_DEVID(dev_priv) == 0x5916 || \
				 INTEL_DEVID(dev_priv) == 0x5921 || \
				 INTEL_DEVID(dev_priv) == 0x5926)
#define IS_KBL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x590E || \
				 INTEL_DEVID(dev_priv) == 0x5915 || \
				 INTEL_DEVID(dev_priv) == 0x591E)
#define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
#define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2811

2812
#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2813

2814 2815 2816 2817 2818 2819
#define SKL_REVID_A0		0x0
#define SKL_REVID_B0		0x1
#define SKL_REVID_C0		0x2
#define SKL_REVID_D0		0x3
#define SKL_REVID_E0		0x4
#define SKL_REVID_F0		0x5
2820 2821
#define SKL_REVID_G0		0x6
#define SKL_REVID_H0		0x7
2822

2823 2824
#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))

2825
#define BXT_REVID_A0		0x0
2826
#define BXT_REVID_A1		0x1
2827
#define BXT_REVID_B0		0x3
2828
#define BXT_REVID_B_LAST	0x8
2829
#define BXT_REVID_C0		0x9
N
Nick Hoath 已提交
2830

2831 2832
#define IS_BXT_REVID(dev_priv, since, until) \
	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2833

M
Mika Kuoppala 已提交
2834 2835
#define KBL_REVID_A0		0x0
#define KBL_REVID_B0		0x1
2836 2837 2838
#define KBL_REVID_C0		0x2
#define KBL_REVID_D0		0x3
#define KBL_REVID_E0		0x4
M
Mika Kuoppala 已提交
2839

2840 2841
#define IS_KBL_REVID(dev_priv, since, until) \
	(IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
M
Mika Kuoppala 已提交
2842

2843 2844 2845 2846 2847 2848
#define GLK_REVID_A0		0x0
#define GLK_REVID_A1		0x1

#define IS_GLK_REVID(dev_priv, since, until) \
	(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))

2849 2850 2851 2852 2853 2854
#define CNL_REVID_A0		0x0
#define CNL_REVID_B0		0x1

#define IS_CNL_REVID(p, since, until) \
	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))

2855 2856 2857 2858 2859 2860
/*
 * The genX designation typically refers to the render engine, so render
 * capability related checks should use IS_GEN, while display and other checks
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 * chips, etc.).
 */
2861 2862 2863 2864 2865 2866 2867 2868
#define IS_GEN2(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(1)))
#define IS_GEN3(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(2)))
#define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))
#define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))
#define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))
#define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
#define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
#define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
2869
#define IS_GEN10(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(9)))
2870

2871
#define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
2872 2873
#define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))
#define IS_GEN9_BC(dev_priv)	(IS_GEN9(dev_priv) && !IS_LP(dev_priv))
2874

2875 2876 2877 2878 2879 2880 2881 2882 2883
#define ENGINE_MASK(id)	BIT(id)
#define RENDER_RING	ENGINE_MASK(RCS)
#define BSD_RING	ENGINE_MASK(VCS)
#define BLT_RING	ENGINE_MASK(BCS)
#define VEBOX_RING	ENGINE_MASK(VECS)
#define BSD2_RING	ENGINE_MASK(VCS2)
#define ALL_ENGINES	(~0)

#define HAS_ENGINE(dev_priv, id) \
2884
	(!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2885 2886 2887 2888 2889 2890

#define HAS_BSD(dev_priv)	HAS_ENGINE(dev_priv, VCS)
#define HAS_BSD2(dev_priv)	HAS_ENGINE(dev_priv, VCS2)
#define HAS_BLT(dev_priv)	HAS_ENGINE(dev_priv, BCS)
#define HAS_VEBOX(dev_priv)	HAS_ENGINE(dev_priv, VECS)

2891 2892 2893
#define HAS_LLC(dev_priv)	((dev_priv)->info.has_llc)
#define HAS_SNOOP(dev_priv)	((dev_priv)->info.has_snoop)
#define HAS_EDRAM(dev_priv)	(!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2894 2895
#define HAS_WT(dev_priv)	((IS_HASWELL(dev_priv) || \
				 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2896

2897
#define HWS_NEEDS_PHYSICAL(dev_priv)	((dev_priv)->info.hws_needs_physical)
2898

2899 2900 2901 2902 2903 2904 2905 2906 2907
#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
		((dev_priv)->info.has_logical_ring_contexts)
#define USES_PPGTT(dev_priv)		(i915.enable_ppgtt)
#define USES_FULL_PPGTT(dev_priv)	(i915.enable_ppgtt >= 2)
#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915.enable_ppgtt == 3)

#define HAS_OVERLAY(dev_priv)		 ((dev_priv)->info.has_overlay)
#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
		((dev_priv)->info.overlay_needs_physical)
2908

2909
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2910
#define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_I845G(dev_priv))
2911 2912

/* WaRsDisableCoarsePowerGating:skl,bxt */
2913
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2914
	(IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
2915

2916 2917 2918 2919 2920 2921
/*
 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
 * even when in MSI mode. This results in spurious interrupt warnings if the
 * legacy irq no. is shared with another device. The kernel then disables that
 * interrupt source and so prevents the other device from working properly.
 */
2922 2923
#define HAS_AUX_IRQ(dev_priv)   ((dev_priv)->info.gen >= 5)
#define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2924

2925 2926 2927
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
2928 2929 2930
#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
					 !(IS_I915G(dev_priv) || \
					 IS_I915GM(dev_priv)))
2931 2932
#define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)
#define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)
2933

2934 2935 2936
#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
#define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
#define HAS_FBC(dev_priv)	((dev_priv)->info.has_fbc)
2937
#define HAS_CUR_FBC(dev_priv)	(!HAS_GMCH_DISPLAY(dev_priv) && INTEL_INFO(dev_priv)->gen >= 7)
2938

2939
#define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2940

2941
#define HAS_DP_MST(dev_priv)	((dev_priv)->info.has_dp_mst)
2942

2943 2944 2945 2946 2947
#define HAS_DDI(dev_priv)		 ((dev_priv)->info.has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
#define HAS_PSR(dev_priv)		 ((dev_priv)->info.has_psr)
#define HAS_RC6(dev_priv)		 ((dev_priv)->info.has_rc6)
#define HAS_RC6p(dev_priv)		 ((dev_priv)->info.has_rc6p)
P
Paulo Zanoni 已提交
2948

2949
#define HAS_CSR(dev_priv)	((dev_priv)->info.has_csr)
2950

2951
#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2952 2953
#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)

2954 2955 2956 2957 2958
/*
 * For now, anything with a GuC requires uCode loading, and then supports
 * command submission once loaded. But these are logically independent
 * properties, so we have separate macros to test them.
 */
2959
#define HAS_GUC(dev_priv)	((dev_priv)->info.has_guc)
2960
#define HAS_GUC_CT(dev_priv)	((dev_priv)->info.has_guc_ct)
2961 2962
#define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
#define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
2963
#define HAS_HUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
2964

2965
#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2966

2967
#define HAS_POOLED_EU(dev_priv)	((dev_priv)->info.has_pooled_eu)
2968

2969
#define INTEL_PCH_DEVICE_ID_MASK		0xff00
2970
#define INTEL_PCH_DEVICE_ID_MASK_EXT		0xff80
2971 2972 2973 2974 2975
#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
2976 2977
#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
2978
#define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA200
2979
#define INTEL_PCH_CNP_DEVICE_ID_TYPE		0xA300
2980
#define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE		0x9D80
2981
#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
2982
#define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
2983
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
2984

2985
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
2986
#define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
2987 2988
#define HAS_PCH_CNP_LP(dev_priv) \
	((dev_priv)->pch_id == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE)
2989 2990 2991
#define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2992 2993 2994 2995
#define HAS_PCH_LPT_LP(dev_priv) \
	((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
#define HAS_PCH_LPT_H(dev_priv) \
	((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2996 2997 2998 2999
#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
3000

3001
#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
3002

3003 3004
#define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))

3005
/* DPF == dynamic parity feature */
3006
#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
3007 3008
#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
				 2 : HAS_L3_DPF(dev_priv))
3009

3010
#define GT_FREQUENCY_MULTIPLIER 50
A
Akash Goel 已提交
3011
#define GEN9_FREQ_SCALER 3
3012

3013 3014
#include "i915_trace.h"

3015
static inline bool intel_vtd_active(void)
3016 3017
{
#ifdef CONFIG_INTEL_IOMMU
3018
	if (intel_iommu_gfx_mapped)
3019 3020 3021 3022 3023
		return true;
#endif
	return false;
}

3024 3025 3026 3027 3028
static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
	return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active();
}

3029 3030 3031
static inline bool
intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
3032
	return IS_BROXTON(dev_priv) && intel_vtd_active();
3033 3034
}

3035
int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
3036
				int enable_ppgtt);
3037

3038 3039
bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);

3040
/* i915_drv.c */
3041 3042 3043 3044 3045 3046 3047
void __printf(3, 4)
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
	      const char *fmt, ...);

#define i915_report_error(dev_priv, fmt, ...)				   \
	__i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)

3048
#ifdef CONFIG_COMPAT
D
Dave Airlie 已提交
3049 3050
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);
3051 3052
#else
#define i915_compat_ioctl NULL
3053
#endif
3054 3055 3056 3057 3058
extern const struct dev_pm_ops i915_pm_ops;

extern int i915_driver_load(struct pci_dev *pdev,
			    const struct pci_device_id *ent);
extern void i915_driver_unload(struct drm_device *dev);
3059 3060
extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
3061
extern void i915_reset(struct drm_i915_private *dev_priv);
3062
extern int intel_guc_reset(struct drm_i915_private *dev_priv);
3063
extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
3064
extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
3065 3066 3067 3068
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
3069
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
3070

3071
int intel_engines_init_mmio(struct drm_i915_private *dev_priv);
3072 3073
int intel_engines_init(struct drm_i915_private *dev_priv);

3074
/* intel_hotplug.c */
3075 3076
void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
			   u32 pin_mask, u32 long_mask);
3077 3078 3079
void intel_hpd_init(struct drm_i915_private *dev_priv);
void intel_hpd_init_work(struct drm_i915_private *dev_priv);
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
3080
bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
3081 3082
bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3083

L
Linus Torvalds 已提交
3084
/* i915_irq.c */
3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101
static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
{
	unsigned long delay;

	if (unlikely(!i915.enable_hangcheck))
		return;

	/* Don't continually defer the hangcheck so that it is always run at
	 * least once after work has been scheduled on any ring. Otherwise,
	 * we will ignore a hung ring if a second ring is kept busy.
	 */

	delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
	queue_delayed_work(system_long_wq,
			   &dev_priv->gpu_error.hangcheck_work, delay);
}

3102
__printf(3, 4)
3103 3104
void i915_handle_error(struct drm_i915_private *dev_priv,
		       u32 engine_mask,
3105
		       const char *fmt, ...);
L
Linus Torvalds 已提交
3106

3107
extern void intel_irq_init(struct drm_i915_private *dev_priv);
3108
extern void intel_irq_fini(struct drm_i915_private *dev_priv);
3109 3110
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
3111

3112 3113
static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
{
3114
	return dev_priv->gvt;
3115 3116
}

3117
static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
3118
{
3119
	return dev_priv->vgpu.active;
3120
}
3121

3122
void
3123
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3124
		     u32 status_mask);
3125 3126

void
3127
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3128
		      u32 status_mask);
3129

3130 3131
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3132 3133 3134
void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
				   uint32_t mask,
				   uint32_t bits);
3135 3136 3137 3138 3139 3140 3141 3142 3143 3144 3145 3146 3147
void ilk_update_display_irq(struct drm_i915_private *dev_priv,
			    uint32_t interrupt_mask,
			    uint32_t enabled_irq_mask);
static inline void
ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, bits);
}
static inline void
ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, 0);
}
3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161
void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
			 enum pipe pipe,
			 uint32_t interrupt_mask,
			 uint32_t enabled_irq_mask);
static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
				       enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
}
static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
					enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
}
3162 3163 3164
void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask);
3165 3166 3167 3168 3169 3170 3171 3172 3173 3174 3175
static inline void
ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, bits);
}
static inline void
ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, 0);
}

3176 3177 3178 3179 3180 3181 3182 3183 3184
/* i915_gem.c */
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3185 3186
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3187 3188 3189 3190 3191 3192
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
			     struct drm_file *file_priv);
int i915_gem_execbuffer(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
J
Jesse Barnes 已提交
3193 3194
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
3195 3196
int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
B
Ben Widawsky 已提交
3197 3198 3199 3200
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
3201 3202
int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
3203 3204
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
3205 3206 3207 3208
int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
3209
void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3210 3211
int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file);
3212 3213
int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
3214 3215
int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3216
void i915_gem_sanitize(struct drm_i915_private *i915);
3217 3218
int i915_gem_load_init(struct drm_i915_private *dev_priv);
void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
3219
void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3220
int i915_gem_freeze(struct drm_i915_private *dev_priv);
3221 3222
int i915_gem_freeze_late(struct drm_i915_private *dev_priv);

3223
void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
3224
void i915_gem_object_free(struct drm_i915_gem_object *obj);
3225 3226
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			 const struct drm_i915_gem_object_ops *ops);
3227 3228 3229 3230 3231
struct drm_i915_gem_object *
i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
struct drm_i915_gem_object *
i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
				 const void *data, size_t size);
3232
void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3233
void i915_gem_free_object(struct drm_gem_object *obj);
3234

3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247
static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915)
{
	/* A single pass should suffice to release all the freed objects (along
	 * most call paths) , but be a little more paranoid in that freeing
	 * the objects does take a little amount of time, during which the rcu
	 * callbacks could have added new objects into the freed list, and
	 * armed the work again.
	 */
	do {
		rcu_barrier();
	} while (flush_work(&i915->mm.free_work));
}

C
Chris Wilson 已提交
3248
struct i915_vma * __must_check
3249 3250
i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
			 const struct i915_ggtt_view *view,
3251
			 u64 size,
3252 3253
			 u64 alignment,
			 u64 flags);
3254

3255
int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3256
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3257

3258 3259
void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);

C
Chris Wilson 已提交
3260
static inline int __sg_page_count(const struct scatterlist *sg)
3261
{
3262 3263
	return sg->length >> PAGE_SHIFT;
}
3264

3265 3266 3267
struct scatterlist *
i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
		       unsigned int n, unsigned int *offset);
3268

3269 3270 3271
struct page *
i915_gem_object_get_page(struct drm_i915_gem_object *obj,
			 unsigned int n);
3272

3273 3274 3275
struct page *
i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
			       unsigned int n);
3276

3277 3278 3279
dma_addr_t
i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
				unsigned long n);
3280

3281 3282
void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
				 struct sg_table *pages);
C
Chris Wilson 已提交
3283 3284 3285 3286 3287
int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);

static inline int __must_check
i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
{
3288
	might_lock(&obj->mm.lock);
C
Chris Wilson 已提交
3289

3290
	if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
C
Chris Wilson 已提交
3291 3292 3293 3294 3295 3296 3297
		return 0;

	return __i915_gem_object_get_pages(obj);
}

static inline void
__i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3298
{
C
Chris Wilson 已提交
3299 3300
	GEM_BUG_ON(!obj->mm.pages);

3301
	atomic_inc(&obj->mm.pages_pin_count);
C
Chris Wilson 已提交
3302 3303 3304 3305 3306
}

static inline bool
i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
{
3307
	return atomic_read(&obj->mm.pages_pin_count);
C
Chris Wilson 已提交
3308 3309 3310 3311 3312 3313 3314 3315
}

static inline void
__i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
{
	GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
	GEM_BUG_ON(!obj->mm.pages);

3316
	atomic_dec(&obj->mm.pages_pin_count);
3317
}
3318

3319 3320
static inline void
i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3321
{
C
Chris Wilson 已提交
3322
	__i915_gem_object_unpin_pages(obj);
3323 3324
}

3325 3326 3327 3328 3329 3330 3331
enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
	I915_MM_NORMAL = 0,
	I915_MM_SHRINKER
};

void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
				 enum i915_mm_subclass subclass);
3332
void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
C
Chris Wilson 已提交
3333

3334 3335 3336 3337 3338
enum i915_map_type {
	I915_MAP_WB = 0,
	I915_MAP_WC,
};

3339 3340
/**
 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3341 3342
 * @obj: the object to map into kernel address space
 * @type: the type of mapping, used to select pgprot_t
3343 3344 3345
 *
 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
 * pages and then returns a contiguous mapping of the backing storage into
3346 3347
 * the kernel address space. Based on the @type of mapping, the PTE will be
 * set to either WriteBack or WriteCombine (via pgprot_t).
3348
 *
3349 3350
 * The caller is responsible for calling i915_gem_object_unpin_map() when the
 * mapping is no longer required.
3351
 *
3352 3353
 * Returns the pointer through which to access the mapped object, or an
 * ERR_PTR() on error.
3354
 */
3355 3356
void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
					   enum i915_map_type type);
3357 3358 3359

/**
 * i915_gem_object_unpin_map - releases an earlier mapping
3360
 * @obj: the object to unmap
3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371
 *
 * After pinning the object and mapping its pages, once you are finished
 * with your access, call i915_gem_object_unpin_map() to release the pin
 * upon the mapping. Once the pin count reaches zero, that mapping may be
 * removed.
 */
static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3372 3373 3374 3375
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
				    unsigned int *needs_clflush);
int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
				     unsigned int *needs_clflush);
3376 3377 3378
#define CLFLUSH_BEFORE	BIT(0)
#define CLFLUSH_AFTER	BIT(1)
#define CLFLUSH_FLAGS	(CLFLUSH_BEFORE | CLFLUSH_AFTER)
3379 3380 3381 3382 3383 3384 3385

static inline void
i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3386
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
B
Ben Widawsky 已提交
3387
void i915_vma_move_to_active(struct i915_vma *vma,
3388 3389
			     struct drm_i915_gem_request *req,
			     unsigned int flags);
3390 3391 3392
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
3393 3394
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
		      uint32_t handle, uint64_t *offset);
3395
int i915_gem_mmap_gtt_version(void);
3396 3397 3398 3399 3400

void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits);

3401
int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3402

3403
struct drm_i915_gem_request *
3404
i915_gem_find_active_request(struct intel_engine_cs *engine);
3405

3406
void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3407

3408 3409 3410 3411 3412 3413
static inline bool i915_reset_backoff(struct i915_gpu_error *error)
{
	return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags));
}

static inline bool i915_reset_handoff(struct i915_gpu_error *error)
3414
{
3415
	return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags));
3416 3417
}

3418
static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3419
{
3420
	return unlikely(test_bit(I915_WEDGED, &error->flags));
3421 3422
}

3423
static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error)
3424
{
3425
	return i915_reset_backoff(error) | i915_terminally_wedged(error);
M
Mika Kuoppala 已提交
3426 3427 3428 3429
}

static inline u32 i915_reset_count(struct i915_gpu_error *error)
{
3430
	return READ_ONCE(error->reset_count);
3431
}
3432

3433
int i915_gem_reset_prepare(struct drm_i915_private *dev_priv);
3434
void i915_gem_reset(struct drm_i915_private *dev_priv);
3435
void i915_gem_reset_finish(struct drm_i915_private *dev_priv);
3436
void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3437
bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv);
3438

3439
void i915_gem_init_mmio(struct drm_i915_private *i915);
3440 3441
int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3442
void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3443
void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3444 3445
int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
			   unsigned int flags);
3446 3447
int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
void i915_gem_resume(struct drm_i915_private *dev_priv);
3448
int i915_gem_fault(struct vm_fault *vmf);
3449 3450 3451 3452
int i915_gem_object_wait(struct drm_i915_gem_object *obj,
			 unsigned int flags,
			 long timeout,
			 struct intel_rps_client *rps);
3453 3454 3455 3456 3457
int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
				  unsigned int flags,
				  int priority);
#define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX

3458
int __must_check
3459 3460 3461
i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write);
int __must_check
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write);
3462
int __must_check
3463
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
C
Chris Wilson 已提交
3464
struct i915_vma * __must_check
3465 3466
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
3467
				     const struct i915_ggtt_view *view);
C
Chris Wilson 已提交
3468
void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3469
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3470
				int align);
3471
int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3472
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3473

3474 3475 3476
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);

3477 3478 3479 3480 3481 3482
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
				struct dma_buf *dma_buf);

struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
				struct drm_gem_object *gem_obj, int flags);

3483 3484 3485 3486 3487 3488
static inline struct i915_hw_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space *vm)
{
	return container_of(vm, struct i915_hw_ppgtt, base);
}

J
Joonas Lahtinen 已提交
3489
/* i915_gem_fence_reg.c */
3490 3491 3492
int __must_check i915_vma_get_fence(struct i915_vma *vma);
int __must_check i915_vma_put_fence(struct i915_vma *vma);

3493
void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
3494
void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3495

3496
void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3497 3498 3499 3500
void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
				       struct sg_table *pages);
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
					 struct sg_table *pages);
3501

3502 3503 3504 3505 3506
static inline struct i915_gem_context *
i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
{
	struct i915_gem_context *ctx;

3507
	lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3508 3509 3510 3511 3512 3513 3514 3515

	ctx = idr_find(&file_priv->context_idr, id);
	if (!ctx)
		return ERR_PTR(-ENOENT);

	return ctx;
}

3516 3517
static inline struct i915_gem_context *
i915_gem_context_get(struct i915_gem_context *ctx)
3518
{
3519
	kref_get(&ctx->ref);
3520
	return ctx;
3521 3522
}

3523
static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3524
{
3525
	lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3526
	kref_put(&ctx->ref, i915_gem_context_free);
3527 3528
}

3529 3530
static inline void i915_gem_context_put_unlocked(struct i915_gem_context *ctx)
{
3531 3532 3533 3534
	struct mutex *lock = &ctx->i915->drm.struct_mutex;

	if (kref_put_mutex(&ctx->ref, i915_gem_context_free, lock))
		mutex_unlock(lock);
3535 3536
}

C
Chris Wilson 已提交
3537 3538 3539 3540 3541 3542 3543 3544 3545 3546
static inline struct intel_timeline *
i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
				 struct intel_engine_cs *engine)
{
	struct i915_address_space *vm;

	vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
	return &vm->timeline.engine[engine->id];
}

3547 3548 3549
int i915_perf_open_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file);

3550
/* i915_gem_evict.c */
3551
int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3552
					  u64 min_size, u64 alignment,
3553
					  unsigned cache_level,
3554
					  u64 start, u64 end,
3555
					  unsigned flags);
3556 3557 3558
int __must_check i915_gem_evict_for_node(struct i915_address_space *vm,
					 struct drm_mm_node *node,
					 unsigned int flags);
3559
int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3560

3561
/* belongs in i915_gem_gtt.h */
3562
static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3563
{
3564
	wmb();
3565
	if (INTEL_GEN(dev_priv) < 6)
3566 3567
		intel_gtt_chipset_flush();
}
3568

3569
/* i915_gem_stolen.c */
3570 3571 3572
int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
				struct drm_mm_node *node, u64 size,
				unsigned alignment);
3573 3574 3575 3576
int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
					 struct drm_mm_node *node, u64 size,
					 unsigned alignment, u64 start,
					 u64 end);
3577 3578
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
				 struct drm_mm_node *node);
3579
int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3580
void i915_gem_cleanup_stolen(struct drm_device *dev);
3581
struct drm_i915_gem_object *
3582
i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
3583
struct drm_i915_gem_object *
3584
i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3585 3586 3587
					       u32 stolen_offset,
					       u32 gtt_offset,
					       u32 size);
3588

3589 3590 3591
/* i915_gem_internal.c */
struct drm_i915_gem_object *
i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
3592
				phys_addr_t size);
3593

3594 3595
/* i915_gem_shrinker.c */
unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3596
			      unsigned long target,
3597 3598 3599 3600
			      unsigned flags);
#define I915_SHRINK_PURGEABLE 0x1
#define I915_SHRINK_UNBOUND 0x2
#define I915_SHRINK_BOUND 0x4
3601
#define I915_SHRINK_ACTIVE 0x8
3602
#define I915_SHRINK_VMAPS 0x10
3603 3604
unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3605
void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3606 3607


3608
/* i915_gem_tiling.c */
3609
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3610
{
3611
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3612 3613

	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3614
		i915_gem_object_is_tiled(obj);
3615 3616
}

3617 3618 3619 3620 3621
u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size,
			unsigned int tiling, unsigned int stride);
u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size,
			     unsigned int tiling, unsigned int stride);

3622
/* i915_debugfs.c */
3623
#ifdef CONFIG_DEBUG_FS
3624
int i915_debugfs_register(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3625
int i915_debugfs_connector_add(struct drm_connector *connector);
3626
void intel_display_crc_init(struct drm_i915_private *dev_priv);
3627
#else
3628
static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
3629 3630
static inline int i915_debugfs_connector_add(struct drm_connector *connector)
{ return 0; }
3631
static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3632
#endif
3633 3634

/* i915_gpu_error.c */
3635 3636
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)

3637 3638
__printf(2, 3)
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3639
int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3640
			    const struct i915_gpu_state *gpu);
3641
int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3642
			      struct drm_i915_private *i915,
3643 3644 3645 3646 3647 3648
			      size_t count, loff_t pos);
static inline void i915_error_state_buf_release(
	struct drm_i915_error_state_buf *eb)
{
	kfree(eb->buf);
}
3649 3650

struct i915_gpu_state *i915_capture_gpu_state(struct drm_i915_private *i915);
3651 3652
void i915_capture_error_state(struct drm_i915_private *dev_priv,
			      u32 engine_mask,
3653
			      const char *error_msg);
3654 3655 3656 3657 3658 3659 3660 3661 3662 3663 3664 3665 3666 3667 3668 3669 3670

static inline struct i915_gpu_state *
i915_gpu_state_get(struct i915_gpu_state *gpu)
{
	kref_get(&gpu->ref);
	return gpu;
}

void __i915_gpu_state_free(struct kref *kref);
static inline void i915_gpu_state_put(struct i915_gpu_state *gpu)
{
	if (gpu)
		kref_put(&gpu->ref, __i915_gpu_state_free);
}

struct i915_gpu_state *i915_first_error_state(struct drm_i915_private *i915);
void i915_reset_error_state(struct drm_i915_private *i915);
3671

3672 3673 3674 3675 3676 3677 3678 3679
#else

static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
					    u32 engine_mask,
					    const char *error_msg)
{
}

3680 3681 3682 3683 3684 3685 3686
static inline struct i915_gpu_state *
i915_first_error_state(struct drm_i915_private *i915)
{
	return NULL;
}

static inline void i915_reset_error_state(struct drm_i915_private *i915)
3687 3688 3689 3690 3691
{
}

#endif

3692
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3693

3694
/* i915_cmd_parser.c */
3695
int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3696
void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3697 3698 3699 3700 3701 3702 3703
void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
int intel_engine_cmd_parser(struct intel_engine_cs *engine,
			    struct drm_i915_gem_object *batch_obj,
			    struct drm_i915_gem_object *shadow_batch_obj,
			    u32 batch_start_offset,
			    u32 batch_len,
			    bool is_master);
3704

3705 3706 3707
/* i915_perf.c */
extern void i915_perf_init(struct drm_i915_private *dev_priv);
extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3708 3709
extern void i915_perf_register(struct drm_i915_private *dev_priv);
extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3710

3711
/* i915_suspend.c */
3712 3713
extern int i915_save_state(struct drm_i915_private *dev_priv);
extern int i915_restore_state(struct drm_i915_private *dev_priv);
3714

B
Ben Widawsky 已提交
3715
/* i915_sysfs.c */
D
David Weinehall 已提交
3716 3717
void i915_setup_sysfs(struct drm_i915_private *dev_priv);
void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
B
Ben Widawsky 已提交
3718

3719 3720 3721 3722
/* intel_lpe_audio.c */
int  intel_lpe_audio_init(struct drm_i915_private *dev_priv);
void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv);
void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv);
3723
void intel_lpe_audio_notify(struct drm_i915_private *dev_priv,
3724 3725
			    enum pipe pipe, enum port port,
			    const void *eld, int ls_clock, bool dp_output);
3726

3727
/* intel_i2c.c */
3728 3729
extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3730 3731
extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
				     unsigned int pin);
3732

3733 3734
extern struct i2c_adapter *
intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
C
Chris Wilson 已提交
3735 3736
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3737
static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3738 3739 3740
{
	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
}
3741
extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3742

3743
/* intel_bios.c */
3744
void intel_bios_init(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3745
bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3746
bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3747
bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3748
bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3749
bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3750
bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3751
bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3752 3753
bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
				     enum port port);
3754 3755 3756
bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
				enum port port);

3757

3758
/* intel_opregion.c */
3759
#ifdef CONFIG_ACPI
3760
extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3761 3762
extern void intel_opregion_register(struct drm_i915_private *dev_priv);
extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3763
extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3764 3765
extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
					 bool enable);
3766
extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3767
					 pci_power_t state);
3768
extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3769
#else
3770
static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3771 3772
static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3773 3774 3775
static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
{
}
3776 3777 3778 3779 3780
static inline int
intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
{
	return 0;
}
3781
static inline int
3782
intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3783 3784 3785
{
	return 0;
}
3786
static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3787 3788 3789
{
	return -ENODEV;
}
3790
#endif
3791

J
Jesse Barnes 已提交
3792 3793 3794 3795 3796 3797 3798 3799 3800
/* intel_acpi.c */
#ifdef CONFIG_ACPI
extern void intel_register_dsm_handler(void);
extern void intel_unregister_dsm_handler(void);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */

3801 3802 3803 3804 3805 3806 3807
/* intel_device_info.c */
static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private *dev_priv)
{
	return (struct intel_device_info *)&dev_priv->info;
}

3808
const char *intel_platform_name(enum intel_platform platform);
3809 3810 3811
void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
void intel_device_info_dump(struct drm_i915_private *dev_priv);

J
Jesse Barnes 已提交
3812
/* modesetting */
3813
extern void intel_modeset_init_hw(struct drm_device *dev);
3814
extern int intel_modeset_init(struct drm_device *dev);
3815
extern void intel_modeset_gem_init(struct drm_device *dev);
J
Jesse Barnes 已提交
3816
extern void intel_modeset_cleanup(struct drm_device *dev);
3817
extern int intel_connector_register(struct drm_connector *);
3818
extern void intel_connector_unregister(struct drm_connector *);
3819 3820
extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
				       bool state);
3821
extern void intel_display_resume(struct drm_device *dev);
3822 3823
extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3824
extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3825
extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3826
extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3827
extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3828
				  bool enable);
3829

B
Ben Widawsky 已提交
3830 3831
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file);
3832

3833
/* overlay */
3834 3835
extern struct intel_overlay_error_state *
intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3836 3837
extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
					    struct intel_overlay_error_state *error);
3838

3839 3840
extern struct intel_display_error_state *
intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3841
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3842
					    struct intel_display_error_state *error);
3843

3844 3845
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3846 3847
int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
		      u32 reply_mask, u32 reply, int timeout_base_ms);
3848 3849

/* intel_sideband.c */
3850
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3851
int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3852
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3853 3854
u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3855 3856 3857 3858
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3859 3860
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3861 3862
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3863 3864 3865 3866
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		   enum intel_sbi_destination destination);
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		     enum intel_sbi_destination destination);
3867 3868
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3869

3870
/* intel_dpio_phy.c */
3871
void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3872
			     enum dpio_phy *phy, enum dpio_channel *ch);
3873 3874 3875
void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
				  enum port port, u32 margin, u32 scale,
				  u32 enable, u32 deemphasis);
3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887
void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
			    enum dpio_phy phy);
bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
			      enum dpio_phy phy);
uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
					     uint8_t lane_count);
void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
				     uint8_t lane_lat_optim_mask);
uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);

3888 3889 3890
void chv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 deemph_reg_value, u32 margin_reg_value,
			      bool uniq_trans_scale);
3891 3892
void chv_data_lane_soft_reset(struct intel_encoder *encoder,
			      bool reset);
3893
void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3894 3895
void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3896
void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3897

3898 3899 3900
void vlv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 demph_reg_value, u32 preemph_reg_value,
			      u32 uniqtranscale_reg_value, u32 tx3_demph);
3901
void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3902
void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3903
void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3904

3905 3906
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3907 3908
u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv,
			   const i915_reg_t reg);
3909

3910 3911 3912 3913 3914 3915 3916 3917 3918 3919 3920 3921 3922
#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

#define I915_READ16(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
#define I915_WRITE16(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
#define I915_READ16_NOTRACE(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
#define I915_WRITE16_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)

#define I915_READ(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
#define I915_WRITE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
#define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
#define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)

3923 3924 3925 3926
/* Be very careful with read/write 64-bit values. On 32-bit machines, they
 * will be implemented using 2 32-bit writes in an arbitrary order with
 * an arbitrary delay between them. This can cause the hardware to
 * act upon the intermediate value, possibly leading to corruption and
3927 3928 3929 3930 3931 3932 3933 3934 3935
 * machine death. For this reason we do not support I915_WRITE64, or
 * dev_priv->uncore.funcs.mmio_writeq.
 *
 * When reading a 64-bit value as two 32-bit values, the delay may cause
 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
 * occasionally a 64-bit register does not actualy support a full readq
 * and must be read using two 32-bit reads.
 *
 * You have been warned.
3936
 */
3937
#define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3938

3939
#define I915_READ64_2x32(lower_reg, upper_reg) ({			\
3940 3941
	u32 upper, lower, old_upper, loop = 0;				\
	upper = I915_READ(upper_reg);					\
3942
	do {								\
3943
		old_upper = upper;					\
3944
		lower = I915_READ(lower_reg);				\
3945 3946
		upper = I915_READ(upper_reg);				\
	} while (upper != old_upper && loop++ < 2);			\
3947
	(u64)upper << 32 | lower; })
3948

3949 3950 3951
#define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)

3952
#define __raw_read(x, s) \
3953
static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \
3954
					     i915_reg_t reg) \
3955
{ \
3956
	return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3957 3958 3959
}

#define __raw_write(x, s) \
3960
static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \
3961
				       i915_reg_t reg, uint##x##_t val) \
3962
{ \
3963
	write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977
}
__raw_read(8, b)
__raw_read(16, w)
__raw_read(32, l)
__raw_read(64, q)

__raw_write(8, b)
__raw_write(16, w)
__raw_write(32, l)
__raw_write(64, q)

#undef __raw_read
#undef __raw_write

3978
/* These are untraced mmio-accessors that are only valid to be used inside
3979
 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3980
 * controlled.
3981
 *
3982
 * Think twice, and think again, before using these.
3983 3984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 3999 4000 4001 4002
 *
 * As an example, these accessors can possibly be used between:
 *
 * spin_lock_irq(&dev_priv->uncore.lock);
 * intel_uncore_forcewake_get__locked();
 *
 * and
 *
 * intel_uncore_forcewake_put__locked();
 * spin_unlock_irq(&dev_priv->uncore.lock);
 *
 *
 * Note: some registers may not need forcewake held, so
 * intel_uncore_forcewake_{get,put} can be omitted, see
 * intel_uncore_forcewake_for_reg().
 *
 * Certain architectures will die if the same cacheline is concurrently accessed
 * by different clients (e.g. on Ivybridge). Access to registers should
 * therefore generally be serialised, by either the dev_priv->uncore.lock or
 * a more localised lock guarding all access to that bank of registers.
4003
 */
4004 4005
#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
4006
#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
4007 4008
#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)

4009 4010 4011 4012
/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
#define INTEL_BROADCAST_RGB_FULL 1
#define INTEL_BROADCAST_RGB_LIMITED 2
4013

4014
static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
4015
{
4016
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4017
		return VLV_VGACNTRL;
4018
	else if (INTEL_GEN(dev_priv) >= 5)
4019
		return CPU_VGACNTRL;
4020 4021 4022 4023
	else
		return VGACNTRL;
}

4024 4025 4026 4027 4028 4029 4030
static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
{
	unsigned long j = msecs_to_jiffies(m);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

4031 4032 4033 4034 4035
static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
{
        return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
}

4036 4037 4038 4039 4040 4041 4042 4043
static inline unsigned long
timespec_to_jiffies_timeout(const struct timespec *value)
{
	unsigned long j = timespec_to_jiffies(value);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

4044 4045 4046 4047 4048 4049 4050 4051 4052
/*
 * If you need to wait X milliseconds between events A and B, but event B
 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
 * when event A happened, then just before event B you call this function and
 * pass the timestamp as the first argument, and X as the second argument.
 */
static inline void
wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
{
4053
	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
4054 4055 4056 4057 4058 4059 4060 4061 4062 4063

	/*
	 * Don't re-read the value of "jiffies" every time since it may change
	 * behind our back and break the math.
	 */
	tmp_jiffies = jiffies;
	target_jiffies = timestamp_jiffies +
			 msecs_to_jiffies_timeout(to_wait_ms);

	if (time_after(target_jiffies, tmp_jiffies)) {
4064 4065 4066 4067
		remaining_jiffies = target_jiffies - tmp_jiffies;
		while (remaining_jiffies)
			remaining_jiffies =
			    schedule_timeout_uninterruptible(remaining_jiffies);
4068 4069
	}
}
4070 4071

static inline bool
4072
__i915_request_irq_complete(const struct drm_i915_gem_request *req)
4073
{
4074
	struct intel_engine_cs *engine = req->engine;
4075
	u32 seqno;
4076

4077 4078 4079 4080 4081 4082 4083 4084 4085
	/* Note that the engine may have wrapped around the seqno, and
	 * so our request->global_seqno will be ahead of the hardware,
	 * even though it completed the request before wrapping. We catch
	 * this by kicking all the waiters before resetting the seqno
	 * in hardware, and also signal the fence.
	 */
	if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &req->fence.flags))
		return true;

4086 4087 4088 4089 4090 4091 4092 4093 4094 4095
	/* The request was dequeued before we were awoken. We check after
	 * inspecting the hw to confirm that this was the same request
	 * that generated the HWS update. The memory barriers within
	 * the request execution are sufficient to ensure that a check
	 * after reading the value from hw matches this request.
	 */
	seqno = i915_gem_request_global_seqno(req);
	if (!seqno)
		return false;

4096 4097 4098
	/* Before we do the heavier coherent read of the seqno,
	 * check the value (hopefully) in the CPU cacheline.
	 */
4099
	if (__i915_gem_request_completed(req, seqno))
4100 4101
		return true;

4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112
	/* Ensure our read of the seqno is coherent so that we
	 * do not "miss an interrupt" (i.e. if this is the last
	 * request and the seqno write from the GPU is not visible
	 * by the time the interrupt fires, we will see that the
	 * request is incomplete and go back to sleep awaiting
	 * another interrupt that will never come.)
	 *
	 * Strictly, we only need to do this once after an interrupt,
	 * but it is easier and safer to do it every time the waiter
	 * is woken.
	 */
4113
	if (engine->irq_seqno_barrier &&
4114
	    test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) {
4115
		struct intel_breadcrumbs *b = &engine->breadcrumbs;
4116

4117 4118 4119 4120 4121 4122 4123 4124 4125 4126 4127 4128
		/* The ordering of irq_posted versus applying the barrier
		 * is crucial. The clearing of the current irq_posted must
		 * be visible before we perform the barrier operation,
		 * such that if a subsequent interrupt arrives, irq_posted
		 * is reasserted and our task rewoken (which causes us to
		 * do another __i915_request_irq_complete() immediately
		 * and reapply the barrier). Conversely, if the clear
		 * occurs after the barrier, then an interrupt that arrived
		 * whilst we waited on the barrier would not trigger a
		 * barrier on the next pass, and the read may not see the
		 * seqno update.
		 */
4129
		engine->irq_seqno_barrier(engine);
4130 4131 4132 4133 4134 4135 4136

		/* If we consume the irq, but we are no longer the bottom-half,
		 * the real bottom-half may not have serialised their own
		 * seqno check with the irq-barrier (i.e. may have inspected
		 * the seqno before we believe it coherent since they see
		 * irq_posted == false but we are still running).
		 */
4137
		spin_lock_irq(&b->irq_lock);
4138
		if (b->irq_wait && b->irq_wait->tsk != current)
4139 4140 4141 4142 4143 4144
			/* Note that if the bottom-half is changed as we
			 * are sending the wake-up, the new bottom-half will
			 * be woken by whomever made the change. We only have
			 * to worry about when we steal the irq-posted for
			 * ourself.
			 */
4145
			wake_up_process(b->irq_wait->tsk);
4146
		spin_unlock_irq(&b->irq_lock);
4147

4148
		if (__i915_gem_request_completed(req, seqno))
4149 4150
			return true;
	}
4151 4152 4153 4154

	return false;
}

4155 4156 4157
void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);

4158 4159 4160 4161 4162 4163 4164 4165 4166 4167 4168 4169 4170 4171 4172 4173
/* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment,
 * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot
 * perform the operation. To check beforehand, pass in the parameters to
 * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits,
 * you only need to pass in the minor offsets, page-aligned pointers are
 * always valid.
 *
 * For just checking for SSE4.1, in the foreknowledge that the future use
 * will be correctly aligned, just use i915_has_memcpy_from_wc().
 */
#define i915_can_memcpy_from_wc(dst, src, len) \
	i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0)

#define i915_has_memcpy_from_wc() \
	i915_memcpy_from_wc(NULL, NULL, 0)

4174 4175 4176 4177 4178
/* i915_mm.c */
int remap_io_mapping(struct vm_area_struct *vma,
		     unsigned long addr, unsigned long pfn, unsigned long size,
		     struct io_mapping *iomap);

4179 4180 4181 4182 4183 4184
static inline bool i915_gem_object_is_coherent(struct drm_i915_gem_object *obj)
{
	return (obj->cache_level != I915_CACHE_NONE ||
		HAS_LLC(to_i915(obj->base.dev)));
}

L
Linus Torvalds 已提交
4185
#endif