i915_drv.h 122.5 KB
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/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#ifndef _I915_DRV_H_
#define _I915_DRV_H_

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#include <uapi/drm/i915_drm.h>
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#include <uapi/drm/drm_fourcc.h>
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#include <linux/io-mapping.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/backlight.h>
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#include <linux/hashtable.h>
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#include <linux/intel-iommu.h>
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#include <linux/kref.h>
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#include <linux/pm_qos.h>
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#include <linux/reservation.h>
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#include <linux/shmem_fs.h>

#include <drm/drmP.h>
#include <drm/intel-gtt.h>
#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
#include <drm/drm_gem.h>
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#include <drm/drm_auth.h>
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#include "i915_params.h"
#include "i915_reg.h"

#include "intel_bios.h"
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#include "intel_dpll_mgr.h"
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#include "intel_uc.h"
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#include "intel_lrc.h"
#include "intel_ringbuffer.h"

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#include "i915_gem.h"
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#include "i915_gem_fence_reg.h"
#include "i915_gem_object.h"
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#include "i915_gem_gtt.h"
#include "i915_gem_render_state.h"
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#include "i915_gem_request.h"
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#include "i915_gem_timeline.h"
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#include "i915_vma.h"

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#include "intel_gvt.h"

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/* General customization:
 */

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
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#define DRIVER_DATE		"20161205"
#define DRIVER_TIMESTAMP	1480926326
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#undef WARN_ON
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/* Many gcc seem to no see through this and fall over :( */
#if 0
#define WARN_ON(x) ({ \
	bool __i915_warn_cond = (x); \
	if (__builtin_constant_p(__i915_warn_cond)) \
		BUILD_BUG_ON(__i915_warn_cond); \
	WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
#else
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#define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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#endif

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#undef WARN_ON_ONCE
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#define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
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#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
			     (long) (x), __func__);
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/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 * which may not necessarily be a user visible problem.  This will either
 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 * enable distros and users to tailor their preferred amount of i915 abrt
 * spam.
 */
#define I915_STATE_WARN(condition, format...) ({			\
	int __ret_warn_on = !!(condition);				\
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	if (unlikely(__ret_warn_on))					\
		if (!WARN(i915.verbose_state_checks, format))		\
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			DRM_ERROR(format);				\
	unlikely(__ret_warn_on);					\
})

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#define I915_STATE_WARN_ON(x)						\
	I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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bool __i915_inject_load_failure(const char *func, int line);
#define i915_inject_load_failure() \
	__i915_inject_load_failure(__func__, __LINE__)

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typedef struct {
	uint32_t val;
} uint_fixed_16_16_t;

#define FP_16_16_MAX ({ \
	uint_fixed_16_16_t fp; \
	fp.val = UINT_MAX; \
	fp; \
})

static inline uint_fixed_16_16_t u32_to_fixed_16_16(uint32_t val)
{
	uint_fixed_16_16_t fp;

	WARN_ON(val >> 16);

	fp.val = val << 16;
	return fp;
}

static inline uint32_t fixed_16_16_to_u32_round_up(uint_fixed_16_16_t fp)
{
	return DIV_ROUND_UP(fp.val, 1 << 16);
}

static inline uint32_t fixed_16_16_to_u32(uint_fixed_16_16_t fp)
{
	return fp.val >> 16;
}

static inline uint_fixed_16_16_t min_fixed_16_16(uint_fixed_16_16_t min1,
						 uint_fixed_16_16_t min2)
{
	uint_fixed_16_16_t min;

	min.val = min(min1.val, min2.val);
	return min;
}

static inline uint_fixed_16_16_t max_fixed_16_16(uint_fixed_16_16_t max1,
						 uint_fixed_16_16_t max2)
{
	uint_fixed_16_16_t max;

	max.val = max(max1.val, max2.val);
	return max;
}

static inline uint_fixed_16_16_t fixed_16_16_div_round_up(uint32_t val,
							  uint32_t d)
{
	uint_fixed_16_16_t fp, res;

	fp = u32_to_fixed_16_16(val);
	res.val = DIV_ROUND_UP(fp.val, d);
	return res;
}

static inline uint_fixed_16_16_t fixed_16_16_div_round_up_u64(uint32_t val,
							      uint32_t d)
{
	uint_fixed_16_16_t res;
	uint64_t interm_val;

	interm_val = (uint64_t)val << 16;
	interm_val = DIV_ROUND_UP_ULL(interm_val, d);
	WARN_ON(interm_val >> 32);
	res.val = (uint32_t) interm_val;

	return res;
}

static inline uint_fixed_16_16_t mul_u32_fixed_16_16(uint32_t val,
						     uint_fixed_16_16_t mul)
{
	uint64_t intermediate_val;
	uint_fixed_16_16_t fp;

	intermediate_val = (uint64_t) val * mul.val;
	WARN_ON(intermediate_val >> 32);
	fp.val = (uint32_t) intermediate_val;
	return fp;
}

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static inline const char *yesno(bool v)
{
	return v ? "yes" : "no";
}

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static inline const char *onoff(bool v)
{
	return v ? "on" : "off";
}

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static inline const char *enableddisabled(bool v)
{
	return v ? "enabled" : "disabled";
}

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#define range_overflows(start, size, max) ({ \
	typeof(start) start__ = (start); \
	typeof(size) size__ = (size); \
	typeof(max) max__ = (max); \
	(void)(&start__ == &size__); \
	(void)(&start__ == &max__); \
	start__ > max__ || size__ > max__ - start__; \
})

#define range_overflows_t(type, start, size, max) \
	range_overflows((type)(start), (type)(size), (type)(max))

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enum pipe {
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	INVALID_PIPE = -1,
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	PIPE_A = 0,
	PIPE_B,
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	PIPE_C,
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	_PIPE_EDP,
	I915_MAX_PIPES = _PIPE_EDP
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};
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#define pipe_name(p) ((p) + 'A')
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enum transcoder {
	TRANSCODER_A = 0,
	TRANSCODER_B,
	TRANSCODER_C,
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	TRANSCODER_EDP,
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	TRANSCODER_DSI_A,
	TRANSCODER_DSI_C,
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	I915_MAX_TRANSCODERS
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};
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static inline const char *transcoder_name(enum transcoder transcoder)
{
	switch (transcoder) {
	case TRANSCODER_A:
		return "A";
	case TRANSCODER_B:
		return "B";
	case TRANSCODER_C:
		return "C";
	case TRANSCODER_EDP:
		return "EDP";
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	case TRANSCODER_DSI_A:
		return "DSI A";
	case TRANSCODER_DSI_C:
		return "DSI C";
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	default:
		return "<invalid>";
	}
}
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static inline bool transcoder_is_dsi(enum transcoder transcoder)
{
	return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
}

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/*
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 * Global legacy plane identifier. Valid only for primary/sprite
 * planes on pre-g4x, and only for primary planes on g4x+.
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 */
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enum plane {
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	PLANE_A,
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	PLANE_B,
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	PLANE_C,
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};
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#define plane_name(p) ((p) + 'A')
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#define sprite_name(p, s) ((p) * INTEL_INFO(dev_priv)->num_sprites[(p)] + (s) + 'A')
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/*
 * Per-pipe plane identifier.
 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 * number of planes per CRTC.  Not all platforms really have this many planes,
 * which means some arrays of size I915_MAX_PLANES may have unused entries
 * between the topmost sprite plane and the cursor plane.
 *
 * This is expected to be passed to various register macros
 * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
 */
enum plane_id {
	PLANE_PRIMARY,
	PLANE_SPRITE0,
	PLANE_SPRITE1,
	PLANE_CURSOR,
	I915_MAX_PLANES,
};

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#define for_each_plane_id_on_crtc(__crtc, __p) \
	for ((__p) = PLANE_PRIMARY; (__p) < I915_MAX_PLANES; (__p)++) \
		for_each_if ((__crtc)->plane_ids_mask & BIT(__p))

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enum port {
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	PORT_NONE = -1,
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	PORT_A = 0,
	PORT_B,
	PORT_C,
	PORT_D,
	PORT_E,
	I915_MAX_PORTS
};
#define port_name(p) ((p) + 'A')

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#define I915_NUM_PHYS_VLV 2
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enum dpio_channel {
	DPIO_CH0,
	DPIO_CH1
};

enum dpio_phy {
	DPIO_PHY0,
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	DPIO_PHY1,
	DPIO_PHY2,
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};

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enum intel_display_power_domain {
	POWER_DOMAIN_PIPE_A,
	POWER_DOMAIN_PIPE_B,
	POWER_DOMAIN_PIPE_C,
	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
	POWER_DOMAIN_TRANSCODER_A,
	POWER_DOMAIN_TRANSCODER_B,
	POWER_DOMAIN_TRANSCODER_C,
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	POWER_DOMAIN_TRANSCODER_EDP,
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	POWER_DOMAIN_TRANSCODER_DSI_A,
	POWER_DOMAIN_TRANSCODER_DSI_C,
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	POWER_DOMAIN_PORT_DDI_A_LANES,
	POWER_DOMAIN_PORT_DDI_B_LANES,
	POWER_DOMAIN_PORT_DDI_C_LANES,
	POWER_DOMAIN_PORT_DDI_D_LANES,
	POWER_DOMAIN_PORT_DDI_E_LANES,
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	POWER_DOMAIN_PORT_DSI,
	POWER_DOMAIN_PORT_CRT,
	POWER_DOMAIN_PORT_OTHER,
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	POWER_DOMAIN_VGA,
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	POWER_DOMAIN_AUDIO,
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	POWER_DOMAIN_PLLS,
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	POWER_DOMAIN_AUX_A,
	POWER_DOMAIN_AUX_B,
	POWER_DOMAIN_AUX_C,
	POWER_DOMAIN_AUX_D,
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	POWER_DOMAIN_GMBUS,
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	POWER_DOMAIN_MODESET,
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	POWER_DOMAIN_INIT,
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	POWER_DOMAIN_NUM,
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};

#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
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#define POWER_DOMAIN_TRANSCODER(tran) \
	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
	 (tran) + POWER_DOMAIN_TRANSCODER_A)
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enum hpd_pin {
	HPD_NONE = 0,
	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
	HPD_CRT,
	HPD_SDVO_B,
	HPD_SDVO_C,
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	HPD_PORT_A,
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	HPD_PORT_B,
	HPD_PORT_C,
	HPD_PORT_D,
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	HPD_PORT_E,
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	HPD_NUM_PINS
};

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#define for_each_hpd_pin(__pin) \
	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)

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struct i915_hotplug {
	struct work_struct hotplug_work;

	struct {
		unsigned long last_jiffies;
		int count;
		enum {
			HPD_ENABLED = 0,
			HPD_DISABLED = 1,
			HPD_MARK_DISABLED = 2
		} state;
	} stats[HPD_NUM_PINS];
	u32 event_bits;
	struct delayed_work reenable_work;

	struct intel_digital_port *irq_port[I915_MAX_PORTS];
	u32 long_port_mask;
	u32 short_port_mask;
	struct work_struct dig_port_work;

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	struct work_struct poll_init_work;
	bool poll_enabled;

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	/*
	 * if we get a HPD irq from DP and a HPD irq from non-DP
	 * the non-DP HPD could block the workqueue on a mode config
	 * mutex getting, that userspace may have taken. However
	 * userspace is waiting on the DP workqueue to run which is
	 * blocked behind the non-DP one.
	 */
	struct workqueue_struct *dp_wq;
};

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#define I915_GEM_GPU_DOMAINS \
	(I915_GEM_DOMAIN_RENDER | \
	 I915_GEM_DOMAIN_SAMPLER | \
	 I915_GEM_DOMAIN_COMMAND | \
	 I915_GEM_DOMAIN_INSTRUCTION | \
	 I915_GEM_DOMAIN_VERTEX)
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#define for_each_pipe(__dev_priv, __p) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
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#define for_each_pipe_masked(__dev_priv, __p, __mask) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
		for_each_if ((__mask) & (1 << (__p)))
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#define for_each_universal_plane(__dev_priv, __pipe, __p)		\
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	for ((__p) = 0;							\
	     (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;	\
	     (__p)++)
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#define for_each_sprite(__dev_priv, __p, __s)				\
	for ((__s) = 0;							\
	     (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];	\
	     (__s)++)
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#define for_each_port_masked(__port, __ports_mask) \
	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	\
		for_each_if ((__ports_mask) & (1 << (__port)))

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#define for_each_crtc(dev, crtc) \
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	list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
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#define for_each_intel_plane(dev, intel_plane) \
	list_for_each_entry(intel_plane,			\
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			    &(dev)->mode_config.plane_list,	\
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			    base.head)

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#define for_each_intel_plane_mask(dev, intel_plane, plane_mask)		\
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	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
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			    base.head)					\
		for_each_if ((plane_mask) &				\
			     (1 << drm_plane_index(&intel_plane->base)))

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#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)	\
	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
			    base.head)					\
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		for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
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#define for_each_intel_crtc(dev, intel_crtc)				\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)
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#define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)		\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)					\
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		for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))

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#define for_each_intel_encoder(dev, intel_encoder)		\
	list_for_each_entry(intel_encoder,			\
			    &(dev)->mode_config.encoder_list,	\
			    base.head)

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#define for_each_intel_connector(dev, intel_connector)		\
	list_for_each_entry(intel_connector,			\
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			    &(dev)->mode_config.connector_list,	\
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			    base.head)

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#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
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		for_each_if ((intel_encoder)->base.crtc == (__crtc))
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#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
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		for_each_if ((intel_connector)->base.encoder == (__encoder))
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#define for_each_power_domain(domain, mask)				\
	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
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		for_each_if ((1 << (domain)) & (mask))
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struct drm_i915_private;
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struct i915_mm_struct;
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struct i915_mmu_object;
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struct drm_i915_file_private {
	struct drm_i915_private *dev_priv;
	struct drm_file *file;

	struct {
		spinlock_t lock;
		struct list_head request_list;
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/* 20ms is a fairly arbitrary limit (greater than the average frame time)
 * chosen to prevent the CPU getting more than a frame ahead of the GPU
 * (when using lax throttling for the frontbuffer). We also use it to
 * offer free GPU waitboosts for severely congested workloads.
 */
#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
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	} mm;
	struct idr context_idr;

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	struct intel_rps_client {
		struct list_head link;
		unsigned boosts;
	} rps;
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	unsigned int bsd_engine;
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/* Client can have a maximum of 3 contexts banned before
 * it is denied of creating new contexts. As one context
 * ban needs 4 consecutive hangs, and more if there is
 * progress in between, this is a last resort stop gap measure
 * to limit the badly behaving clients access to gpu.
 */
#define I915_MAX_CLIENT_CONTEXT_BANS 3
	int context_bans;
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};

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/* Used by dp and fdi links */
struct intel_link_m_n {
	uint32_t	tu;
	uint32_t	gmch_m;
	uint32_t	gmch_n;
	uint32_t	link_m;
	uint32_t	link_n;
};

void intel_link_compute_m_n(int bpp, int nlanes,
			    int pixel_clock, int link_clock,
			    struct intel_link_m_n *m_n);

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/* Interface history:
 *
 * 1.1: Original.
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 * 1.2: Add Power Management
 * 1.3: Add vblank support
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 * 1.4: Fix cmdbuffer path, add heap destroy
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 * 1.5: Add vblank pipe configuration
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 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
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 */
#define DRIVER_MAJOR		1
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#define DRIVER_MINOR		6
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#define DRIVER_PATCHLEVEL	0

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struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
struct opregion_asle;

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struct intel_opregion {
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	struct opregion_header *header;
	struct opregion_acpi *acpi;
	struct opregion_swsci *swsci;
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	u32 swsci_gbda_sub_functions;
	u32 swsci_sbcb_sub_functions;
583
	struct opregion_asle *asle;
584
	void *rvda;
585
	const void *vbt;
586
	u32 vbt_size;
587
	u32 *lid_state;
588
	struct work_struct asle_work;
589
};
590
#define OPREGION_SIZE            (8*1024)
591

592 593 594
struct intel_overlay;
struct intel_overlay_error_state;

595
struct sdvo_device_mapping {
C
Chris Wilson 已提交
596
	u8 initialized;
597 598 599
	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
C
Chris Wilson 已提交
600
	u8 i2c_pin;
601
	u8 ddc_pin;
602 603
};

604
struct intel_connector;
605
struct intel_encoder;
606
struct intel_atomic_state;
607
struct intel_crtc_state;
608
struct intel_initial_plane_config;
609
struct intel_crtc;
610 611
struct intel_limit;
struct dpll;
612

613
struct drm_i915_display_funcs {
614
	int (*get_display_clock_speed)(struct drm_i915_private *dev_priv);
615
	int (*get_fifo_size)(struct drm_i915_private *dev_priv, int plane);
616
	int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
617 618 619
	int (*compute_intermediate_wm)(struct drm_device *dev,
				       struct intel_crtc *intel_crtc,
				       struct intel_crtc_state *newstate);
620 621 622 623 624 625
	void (*initial_watermarks)(struct intel_atomic_state *state,
				   struct intel_crtc_state *cstate);
	void (*atomic_update_watermarks)(struct intel_atomic_state *state,
					 struct intel_crtc_state *cstate);
	void (*optimize_watermarks)(struct intel_atomic_state *state,
				    struct intel_crtc_state *cstate);
626
	int (*compute_global_watermarks)(struct drm_atomic_state *state);
627
	void (*update_wm)(struct intel_crtc *crtc);
628 629
	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
	void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
630 631 632
	/* Returns the active state of the crtc, and if the crtc is active,
	 * fills out the pipe-config with the hw state. */
	bool (*get_pipe_config)(struct intel_crtc *,
633
				struct intel_crtc_state *);
634 635
	void (*get_initial_plane_config)(struct intel_crtc *,
					 struct intel_initial_plane_config *);
636 637
	int (*crtc_compute_clock)(struct intel_crtc *crtc,
				  struct intel_crtc_state *crtc_state);
638 639 640 641
	void (*crtc_enable)(struct intel_crtc_state *pipe_config,
			    struct drm_atomic_state *old_state);
	void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
			     struct drm_atomic_state *old_state);
642 643
	void (*update_crtcs)(struct drm_atomic_state *state,
			     unsigned int *crtc_vblank_mask);
644 645
	void (*audio_codec_enable)(struct drm_connector *connector,
				   struct intel_encoder *encoder,
646
				   const struct drm_display_mode *adjusted_mode);
647
	void (*audio_codec_disable)(struct intel_encoder *encoder);
648
	void (*fdi_link_train)(struct drm_crtc *crtc);
649
	void (*init_clock_gating)(struct drm_i915_private *dev_priv);
650 651 652 653 654
	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
			  struct drm_framebuffer *fb,
			  struct drm_i915_gem_object *obj,
			  struct drm_i915_gem_request *req,
			  uint32_t flags);
655
	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
656 657 658 659 660
	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
661

662 663
	void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
	void (*load_luts)(struct drm_crtc_state *crtc_state);
664 665
};

666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682
enum forcewake_domain_id {
	FW_DOMAIN_ID_RENDER = 0,
	FW_DOMAIN_ID_BLITTER,
	FW_DOMAIN_ID_MEDIA,

	FW_DOMAIN_ID_COUNT
};

enum forcewake_domains {
	FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
	FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
	FORCEWAKE_MEDIA	= (1 << FW_DOMAIN_ID_MEDIA),
	FORCEWAKE_ALL = (FORCEWAKE_RENDER |
			 FORCEWAKE_BLITTER |
			 FORCEWAKE_MEDIA)
};

683 684 685
#define FW_REG_READ  (1)
#define FW_REG_WRITE (2)

686 687 688 689 690 691 692 693 694 695 696 697
enum decoupled_power_domain {
	GEN9_DECOUPLED_PD_BLITTER = 0,
	GEN9_DECOUPLED_PD_RENDER,
	GEN9_DECOUPLED_PD_MEDIA,
	GEN9_DECOUPLED_PD_ALL
};

enum decoupled_ops {
	GEN9_DECOUPLED_OP_WRITE = 0,
	GEN9_DECOUPLED_OP_READ
};

698 699 700 701
enum forcewake_domains
intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
			       i915_reg_t reg, unsigned int op);

702
struct intel_uncore_funcs {
703
	void (*force_wake_get)(struct drm_i915_private *dev_priv,
704
							enum forcewake_domains domains);
705
	void (*force_wake_put)(struct drm_i915_private *dev_priv,
706
							enum forcewake_domains domains);
707

708 709 710 711
	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
712

713
	void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
714
				uint8_t val, bool trace);
715
	void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
716
				uint16_t val, bool trace);
717
	void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
718
				uint32_t val, bool trace);
719 720
};

721 722 723 724 725 726 727
struct intel_forcewake_range {
	u32 start;
	u32 end;

	enum forcewake_domains domains;
};

728 729 730
struct intel_uncore {
	spinlock_t lock; /** lock is also taken in irq contexts. */

731 732 733
	const struct intel_forcewake_range *fw_domains_table;
	unsigned int fw_domains_table_entries;

734 735 736
	struct intel_uncore_funcs funcs;

	unsigned fifo_count;
737

738
	enum forcewake_domains fw_domains;
739
	enum forcewake_domains fw_domains_active;
740 741 742

	struct intel_uncore_forcewake_domain {
		struct drm_i915_private *i915;
743
		enum forcewake_domain_id id;
744
		enum forcewake_domains mask;
745
		unsigned wake_count;
746
		struct hrtimer timer;
747
		i915_reg_t reg_set;
748 749
		u32 val_set;
		u32 val_clear;
750 751
		i915_reg_t reg_ack;
		i915_reg_t reg_post;
752
		u32 val_reset;
753
	} fw_domain[FW_DOMAIN_ID_COUNT];
754 755

	int unclaimed_mmio_check;
756 757 758
};

/* Iterate over initialised fw domains */
759 760 761 762 763 764 765 766
#define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
	for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
	     (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
	     (domain__)++) \
		for_each_if ((mask__) & (domain__)->mask)

#define for_each_fw_domain(domain__, dev_priv__) \
	for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
767

768 769 770 771
#define CSR_VERSION(major, minor)	((major) << 16 | (minor))
#define CSR_VERSION_MAJOR(version)	((version) >> 16)
#define CSR_VERSION_MINOR(version)	((version) & 0xffff)

772
struct intel_csr {
773
	struct work_struct work;
774
	const char *fw_path;
775
	uint32_t *dmc_payload;
776
	uint32_t dmc_fw_size;
777
	uint32_t version;
778
	uint32_t mmio_count;
779
	i915_reg_t mmioaddr[8];
780
	uint32_t mmiodata[8];
781
	uint32_t dc_state;
782
	uint32_t allowed_dc_mask;
783 784
};

785 786
#define DEV_INFO_FOR_EACH_FLAG(func) \
	func(is_mobile); \
787
	func(is_lp); \
788
	func(is_alpha_support); \
789
	/* Keep has_* in alphabetical order */ \
790
	func(has_64bit_reloc); \
791
	func(has_aliasing_ppgtt); \
792
	func(has_csr); \
793
	func(has_ddi); \
794
	func(has_decoupled_mmio); \
795
	func(has_dp_mst); \
796 797
	func(has_fbc); \
	func(has_fpga_dbg); \
798 799
	func(has_full_ppgtt); \
	func(has_full_48bit_ppgtt); \
800 801 802 803
	func(has_gmbus_irq); \
	func(has_gmch_display); \
	func(has_guc); \
	func(has_hotplug); \
804 805
	func(has_hw_contexts); \
	func(has_l3_dpf); \
806
	func(has_llc); \
807 808 809 810 811 812 813 814 815
	func(has_logical_ring_contexts); \
	func(has_overlay); \
	func(has_pipe_cxsr); \
	func(has_pooled_eu); \
	func(has_psr); \
	func(has_rc6); \
	func(has_rc6p); \
	func(has_resource_streamer); \
	func(has_runtime_pm); \
816
	func(has_snoop); \
817 818 819
	func(cursor_needs_physical); \
	func(hws_needs_physical); \
	func(overlay_needs_physical); \
820
	func(supports_tv);
D
Daniel Vetter 已提交
821

822
struct sseu_dev_info {
823
	u8 slice_mask;
824
	u8 subslice_mask;
825 826
	u8 eu_total;
	u8 eu_per_subslice;
827 828 829 830 831 832
	u8 min_eu_in_pool;
	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
	u8 subslice_7eu[3];
	u8 has_slice_pg:1;
	u8 has_subslice_pg:1;
	u8 has_eu_pg:1;
833 834
};

835 836 837 838 839
static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
{
	return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
}

840 841 842 843 844 845 846 847 848 849 850 851 852
/* Keep in gen based order, and chronological order within a gen */
enum intel_platform {
	INTEL_PLATFORM_UNINITIALIZED = 0,
	INTEL_I830,
	INTEL_I845G,
	INTEL_I85X,
	INTEL_I865G,
	INTEL_I915G,
	INTEL_I915GM,
	INTEL_I945G,
	INTEL_I945GM,
	INTEL_G33,
	INTEL_PINEVIEW,
853 854
	INTEL_I965G,
	INTEL_I965GM,
855 856
	INTEL_G45,
	INTEL_GM45,
857 858 859 860 861 862 863 864 865 866 867 868 869
	INTEL_IRONLAKE,
	INTEL_SANDYBRIDGE,
	INTEL_IVYBRIDGE,
	INTEL_VALLEYVIEW,
	INTEL_HASWELL,
	INTEL_BROADWELL,
	INTEL_CHERRYVIEW,
	INTEL_SKYLAKE,
	INTEL_BROXTON,
	INTEL_KABYLAKE,
	INTEL_GEMINILAKE,
};

870
struct intel_device_info {
871
	u32 display_mmio_offset;
872
	u16 device_id;
873
	u8 num_pipes;
874
	u8 num_sprites[I915_MAX_PIPES];
875
	u8 gen;
876
	u16 gen_mask;
877
	enum intel_platform platform;
878
	u8 ring_mask; /* Rings supported by the HW */
879
	u8 num_rings;
880 881 882
#define DEFINE_FLAG(name) u8 name:1
	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
#undef DEFINE_FLAG
883
	u16 ddb_size; /* in blocks */
884 885 886 887
	/* Register offsets for the various display pipes and transcoders */
	int pipe_offsets[I915_MAX_TRANSCODERS];
	int trans_offsets[I915_MAX_TRANSCODERS];
	int palette_offsets[I915_MAX_PIPES];
888
	int cursor_offsets[I915_MAX_PIPES];
889 890

	/* Slice/subslice/EU info */
891
	struct sseu_dev_info sseu;
892 893 894 895 896

	struct color_luts {
		u16 degamma_lut_size;
		u16 gamma_lut_size;
	} color;
897 898
};

899 900 901 902 903
struct intel_display_error_state;

struct drm_i915_error_state {
	struct kref ref;
	struct timeval time;
904 905
	struct timeval boottime;
	struct timeval uptime;
906

907 908
	struct drm_i915_private *i915;

909 910 911 912 913 914 915 916 917 918 919 920 921 922 923 924 925 926 927 928 929 930 931 932
	char error_msg[128];
	bool simulated;
	int iommu;
	u32 reset_count;
	u32 suspend_count;
	struct intel_device_info device_info;

	/* Generic register state */
	u32 eir;
	u32 pgtbl_er;
	u32 ier;
	u32 gtier[4];
	u32 ccid;
	u32 derrmr;
	u32 forcewake;
	u32 error; /* gen6+ */
	u32 err_int; /* gen7 */
	u32 fault_data0; /* gen8, gen9 */
	u32 fault_data1; /* gen8, gen9 */
	u32 done_reg;
	u32 gac_eco;
	u32 gam_ecochk;
	u32 gab_ctl;
	u32 gfx_mode;
933

934 935 936
	u64 fence[I915_MAX_NUM_FENCES];
	struct intel_overlay_error_state *overlay;
	struct intel_display_error_state *display;
937
	struct drm_i915_error_object *semaphore;
938
	struct drm_i915_error_object *guc_log;
939 940 941 942 943 944

	struct drm_i915_error_engine {
		int engine_id;
		/* Software tracked state */
		bool waiting;
		int num_waiters;
945 946
		unsigned long hangcheck_timestamp;
		bool hangcheck_stalled;
947 948 949 950
		enum intel_engine_hangcheck_action hangcheck_action;
		struct i915_address_space *vm;
		int num_requests;

951 952 953
		/* position of active request inside the ring */
		u32 rq_head, rq_post, rq_tail;

954 955 956 957 958 959 960 961 962 963 964
		/* our own tracking of ring head and tail */
		u32 cpu_ring_head;
		u32 cpu_ring_tail;

		u32 last_seqno;

		/* Register state */
		u32 start;
		u32 tail;
		u32 head;
		u32 ctl;
965
		u32 mode;
966 967 968 969 970 971 972 973 974 975 976 977 978
		u32 hws;
		u32 ipeir;
		u32 ipehr;
		u32 bbstate;
		u32 instpm;
		u32 instps;
		u32 seqno;
		u64 bbaddr;
		u64 acthd;
		u32 fault_reg;
		u64 faddr;
		u32 rc_psmi; /* sleep state */
		u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
979
		struct intel_instdone instdone;
980 981 982

		struct drm_i915_error_object {
			u64 gtt_offset;
983
			u64 gtt_size;
984 985
			int page_count;
			int unused;
986 987 988 989 990 991 992
			u32 *pages[0];
		} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;

		struct drm_i915_error_object *wa_ctx;

		struct drm_i915_error_request {
			long jiffies;
993
			pid_t pid;
994
			u32 context;
995
			int ban_score;
996 997 998
			u32 seqno;
			u32 head;
			u32 tail;
999
		} *requests, execlist[2];
1000 1001 1002 1003 1004 1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015 1016

		struct drm_i915_error_waiter {
			char comm[TASK_COMM_LEN];
			pid_t pid;
			u32 seqno;
		} *waiters;

		struct {
			u32 gfx_mode;
			union {
				u64 pdp[4];
				u32 pp_dir_base;
			};
		} vm_info;

		pid_t pid;
		char comm[TASK_COMM_LEN];
1017
		int context_bans;
1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032 1033 1034 1035 1036 1037 1038
	} engine[I915_NUM_ENGINES];

	struct drm_i915_error_buffer {
		u32 size;
		u32 name;
		u32 rseqno[I915_NUM_ENGINES], wseqno;
		u64 gtt_offset;
		u32 read_domains;
		u32 write_domain;
		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
		u32 tiling:2;
		u32 dirty:1;
		u32 purgeable:1;
		u32 userptr:1;
		s32 engine:4;
		u32 cache_level:3;
	} *active_bo[I915_NUM_ENGINES], *pinned_bo;
	u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
	struct i915_address_space *active_vm[I915_NUM_ENGINES];
};

1039 1040
enum i915_cache_level {
	I915_CACHE_NONE = 0,
1041 1042 1043 1044 1045
	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
			      caches, eg sampler/render caches, and the
			      large Last-Level-Cache. LLC is coherent with
			      the CPU, but L3 is only visible to the GPU. */
1046
	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
1047 1048
};

1049 1050
#define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */

1051
#define DEFAULT_CONTEXT_HANDLE 0
1052

1053
/**
1054
 * struct i915_gem_context - as the name implies, represents a context.
1055 1056 1057
 * @ref: reference count.
 * @user_handle: userspace tracking identity for this context.
 * @remap_slice: l3 row remapping information.
1058 1059
 * @flags: context specific flags:
 *         CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
1060 1061 1062 1063
 * @file_priv: filp associated with this context (NULL for global default
 *	       context).
 * @hang_stats: information about the role of this context in possible GPU
 *		hangs.
1064
 * @ppgtt: virtual memory space used by this context.
1065 1066 1067 1068 1069 1070 1071
 * @legacy_hw_ctx: render context backing object and whether it is correctly
 *                initialized (legacy ring submission mechanism only).
 * @link: link in the global list of contexts.
 *
 * Contexts are memory images used by the hardware to store copies of their
 * internal state.
 */
1072
struct i915_gem_context {
1073
	struct kref ref;
1074
	struct drm_i915_private *i915;
1075
	struct drm_i915_file_private *file_priv;
1076
	struct i915_hw_ppgtt *ppgtt;
1077
	struct pid *pid;
1078
	const char *name;
1079

1080
	unsigned long flags;
1081 1082
#define CONTEXT_NO_ZEROMAP		BIT(0)
#define CONTEXT_NO_ERROR_CAPTURE	BIT(1)
1083 1084 1085

	/* Unique identifier for this context, used by the hw for tracking */
	unsigned int hw_id;
1086
	u32 user_handle;
1087
	int priority; /* greater priorities are serviced first */
1088

1089 1090
	u32 ggtt_alignment;

1091
	struct intel_context {
1092
		struct i915_vma *state;
1093
		struct intel_ring *ring;
1094
		uint32_t *lrc_reg_state;
1095 1096
		u64 lrc_desc;
		int pin_count;
1097
		bool initialised;
1098
	} engine[I915_NUM_ENGINES];
1099
	u32 ring_size;
1100
	u32 desc_template;
1101
	struct atomic_notifier_head status_notifier;
1102
	bool execlists_force_single_submission;
1103

1104
	struct list_head link;
1105 1106

	u8 remap_slice;
1107
	bool closed:1;
1108 1109 1110 1111 1112 1113 1114 1115 1116 1117
	bool bannable:1;
	bool banned:1;

	unsigned int guilty_count; /* guilty of a hang */
	unsigned int active_count; /* active during hang */

#define CONTEXT_SCORE_GUILTY		10
#define CONTEXT_SCORE_BAN_THRESHOLD	40
	/* Accumulated score of hangs caused by this context */
	int ban_score;
1118 1119
};

1120 1121 1122 1123 1124
enum fb_op_origin {
	ORIGIN_GTT,
	ORIGIN_CPU,
	ORIGIN_CS,
	ORIGIN_FLIP,
1125
	ORIGIN_DIRTYFB,
1126 1127
};

1128
struct intel_fbc {
P
Paulo Zanoni 已提交
1129 1130 1131
	/* This is always the inner lock when overlapping with struct_mutex and
	 * it's the outer lock when overlapping with stolen_lock. */
	struct mutex lock;
B
Ben Widawsky 已提交
1132
	unsigned threshold;
1133 1134
	unsigned int possible_framebuffer_bits;
	unsigned int busy_bits;
1135
	unsigned int visible_pipes_mask;
1136
	struct intel_crtc *crtc;
1137

1138
	struct drm_mm_node compressed_fb;
1139 1140
	struct drm_mm_node *compressed_llb;

1141 1142
	bool false_color;

1143
	bool enabled;
1144
	bool active;
1145

1146 1147 1148
	bool underrun_detected;
	struct work_struct underrun_work;

1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164 1165 1166 1167 1168 1169 1170
	struct intel_fbc_state_cache {
		struct {
			unsigned int mode_flags;
			uint32_t hsw_bdw_pixel_rate;
		} crtc;

		struct {
			unsigned int rotation;
			int src_w;
			int src_h;
			bool visible;
		} plane;

		struct {
			u64 ilk_ggtt_offset;
			uint32_t pixel_format;
			unsigned int stride;
			int fence_reg;
			unsigned int tiling_mode;
		} fb;
	} state_cache;

1171 1172 1173 1174 1175 1176 1177 1178 1179 1180 1181 1182 1183 1184 1185 1186 1187
	struct intel_fbc_reg_params {
		struct {
			enum pipe pipe;
			enum plane plane;
			unsigned int fence_y_offset;
		} crtc;

		struct {
			u64 ggtt_offset;
			uint32_t pixel_format;
			unsigned int stride;
			int fence_reg;
		} fb;

		int cfb_size;
	} params;

1188
	struct intel_fbc_work {
1189
		bool scheduled;
1190
		u32 scheduled_vblank;
1191 1192
		struct work_struct work;
	} work;
1193

1194
	const char *no_fbc_reason;
1195 1196
};

1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211
/**
 * HIGH_RR is the highest eDP panel refresh rate read from EDID
 * LOW_RR is the lowest eDP panel refresh rate found from EDID
 * parsing for same resolution.
 */
enum drrs_refresh_rate_type {
	DRRS_HIGH_RR,
	DRRS_LOW_RR,
	DRRS_MAX_RR, /* RR count */
};

enum drrs_support_type {
	DRRS_NOT_SUPPORTED = 0,
	STATIC_DRRS_SUPPORT = 1,
	SEAMLESS_DRRS_SUPPORT = 2
1212 1213
};

1214
struct intel_dp;
1215 1216 1217 1218 1219 1220 1221 1222 1223
struct i915_drrs {
	struct mutex mutex;
	struct delayed_work work;
	struct intel_dp *dp;
	unsigned busy_frontbuffer_bits;
	enum drrs_refresh_rate_type refresh_rate_type;
	enum drrs_support_type type;
};

R
Rodrigo Vivi 已提交
1224
struct i915_psr {
1225
	struct mutex lock;
R
Rodrigo Vivi 已提交
1226 1227
	bool sink_support;
	bool source_ok;
1228
	struct intel_dp *enabled;
1229 1230
	bool active;
	struct delayed_work work;
1231
	unsigned busy_frontbuffer_bits;
1232 1233
	bool psr2_support;
	bool aux_frame_sync;
1234
	bool link_standby;
1235
};
1236

1237
enum intel_pch {
1238
	PCH_NONE = 0,	/* No PCH present */
1239 1240
	PCH_IBX,	/* Ibexpeak PCH */
	PCH_CPT,	/* Cougarpoint PCH */
1241
	PCH_LPT,	/* Lynxpoint PCH */
1242
	PCH_SPT,        /* Sunrisepoint PCH */
1243
	PCH_KBP,        /* Kabypoint PCH */
B
Ben Widawsky 已提交
1244
	PCH_NOP,
1245 1246
};

1247 1248 1249 1250 1251
enum intel_sbi_destination {
	SBI_ICLK,
	SBI_MPHY,
};

1252
#define QUIRK_PIPEA_FORCE (1<<0)
1253
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
1254
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
1255
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
1256
#define QUIRK_PIPEB_FORCE (1<<4)
1257
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1258

1259
struct intel_fbdev;
1260
struct intel_fbc_work;
1261

1262 1263
struct intel_gmbus {
	struct i2c_adapter adapter;
1264
#define GMBUS_FORCE_BIT_RETRY (1U << 31)
1265
	u32 force_bit;
1266
	u32 reg0;
1267
	i915_reg_t gpio_reg;
1268
	struct i2c_algo_bit_data bit_algo;
1269 1270 1271
	struct drm_i915_private *dev_priv;
};

1272
struct i915_suspend_saved_registers {
1273
	u32 saveDSPARB;
J
Jesse Barnes 已提交
1274
	u32 saveFBC_CONTROL;
1275 1276
	u32 saveCACHE_MODE_0;
	u32 saveMI_ARB_STATE;
J
Jesse Barnes 已提交
1277 1278
	u32 saveSWF0[16];
	u32 saveSWF1[16];
1279
	u32 saveSWF3[3];
1280
	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1281
	u32 savePCH_PORT_HOTPLUG;
1282
	u16 saveGCDGMBUS;
1283
};
1284

1285 1286 1287 1288 1289 1290 1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342
struct vlv_s0ix_state {
	/* GAM */
	u32 wr_watermark;
	u32 gfx_prio_ctrl;
	u32 arb_mode;
	u32 gfx_pend_tlb0;
	u32 gfx_pend_tlb1;
	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
	u32 media_max_req_count;
	u32 gfx_max_req_count;
	u32 render_hwsp;
	u32 ecochk;
	u32 bsd_hwsp;
	u32 blt_hwsp;
	u32 tlb_rd_addr;

	/* MBC */
	u32 g3dctl;
	u32 gsckgctl;
	u32 mbctl;

	/* GCP */
	u32 ucgctl1;
	u32 ucgctl3;
	u32 rcgctl1;
	u32 rcgctl2;
	u32 rstctl;
	u32 misccpctl;

	/* GPM */
	u32 gfxpause;
	u32 rpdeuhwtc;
	u32 rpdeuc;
	u32 ecobus;
	u32 pwrdwnupctl;
	u32 rp_down_timeout;
	u32 rp_deucsw;
	u32 rcubmabdtmr;
	u32 rcedata;
	u32 spare2gh;

	/* Display 1 CZ domain */
	u32 gt_imr;
	u32 gt_ier;
	u32 pm_imr;
	u32 pm_ier;
	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

	/* GT SA CZ domain */
	u32 tilectl;
	u32 gt_fifoctl;
	u32 gtlc_wake_ctrl;
	u32 gtlc_survive;
	u32 pmwgicz;

	/* Display 2 CZ domain */
	u32 gu_ctl0;
	u32 gu_ctl1;
1343
	u32 pcbr;
1344 1345 1346
	u32 clock_gate_dis2;
};

1347 1348 1349 1350
struct intel_rps_ei {
	u32 cz_clock;
	u32 render_c0;
	u32 media_c0;
1351 1352
};

1353
struct intel_gen6_power_mgmt {
I
Imre Deak 已提交
1354 1355 1356 1357
	/*
	 * work, interrupts_enabled and pm_iir are protected by
	 * dev_priv->irq_lock
	 */
1358
	struct work_struct work;
I
Imre Deak 已提交
1359
	bool interrupts_enabled;
1360
	u32 pm_iir;
1361

1362
	/* PM interrupt bits that should never be masked */
1363 1364
	u32 pm_intr_keep;

1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377 1378 1379
	/* Frequencies are stored in potentially platform dependent multiples.
	 * In other words, *_freq needs to be multiplied by X to be interesting.
	 * Soft limits are those which are used for the dynamic reclocking done
	 * by the driver (raise frequencies under heavy loads, and lower for
	 * lighter loads). Hard limits are those imposed by the hardware.
	 *
	 * A distinction is made for overclocking, which is never enabled by
	 * default, and is considered to be above the hard limit if it's
	 * possible at all.
	 */
	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
	u8 min_freq;		/* AKA RPn. Minimum frequency */
1380
	u8 boost_freq;		/* Frequency to request when wait boosting */
1381
	u8 idle_freq;		/* Frequency to request when we are idle */
1382 1383 1384
	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
	u8 rp1_freq;		/* "less than" RP0 power/freqency */
	u8 rp0_freq;		/* Non-overclocked max frequency. */
1385
	u16 gpll_ref_freq;	/* vlv/chv GPLL reference frequency */
1386

1387 1388 1389
	u8 up_threshold; /* Current %busy required to uplock */
	u8 down_threshold; /* Current %busy required to downclock */

1390 1391 1392
	int last_adj;
	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;

1393 1394 1395 1396
	spinlock_t client_lock;
	struct list_head clients;
	bool client_boost;

1397
	bool enabled;
1398
	struct delayed_work autoenable_work;
1399
	unsigned boosts;
1400

1401 1402 1403
	/* manual wa residency calculations */
	struct intel_rps_ei up_ei, down_ei;

1404 1405
	/*
	 * Protects RPS/RC6 register access and PCU communication.
1406 1407 1408
	 * Must be taken after struct_mutex if nested. Note that
	 * this lock may be held for long periods of time when
	 * talking to hw - so only take it when talking to hw!
1409 1410
	 */
	struct mutex hw_lock;
1411 1412
};

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Daniel Vetter 已提交
1413 1414 1415
/* defined intel_pm.c */
extern spinlock_t mchdev_lock;

1416 1417 1418 1419 1420 1421 1422 1423 1424 1425 1426
struct intel_ilk_power_mgmt {
	u8 cur_delay;
	u8 min_delay;
	u8 max_delay;
	u8 fmax;
	u8 fstart;

	u64 last_count1;
	unsigned long last_time1;
	unsigned long chipset_power;
	u64 last_count2;
1427
	u64 last_time2;
1428 1429 1430 1431 1432 1433 1434
	unsigned long gfx_power;
	u8 corr;

	int c_m;
	int r_t;
};

1435 1436 1437 1438 1439 1440 1441 1442 1443 1444 1445 1446 1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458 1459 1460 1461 1462 1463 1464
struct drm_i915_private;
struct i915_power_well;

struct i915_power_well_ops {
	/*
	 * Synchronize the well's hw state to match the current sw state, for
	 * example enable/disable it based on the current refcount. Called
	 * during driver init and resume time, possibly after first calling
	 * the enable/disable handlers.
	 */
	void (*sync_hw)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/*
	 * Enable the well and resources that depend on it (for example
	 * interrupts located on the well). Called after the 0->1 refcount
	 * transition.
	 */
	void (*enable)(struct drm_i915_private *dev_priv,
		       struct i915_power_well *power_well);
	/*
	 * Disable the well and resources that depend on it. Called after
	 * the 1->0 refcount transition.
	 */
	void (*disable)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/* Returns the hw enabled state. */
	bool (*is_enabled)(struct drm_i915_private *dev_priv,
			   struct i915_power_well *power_well);
};

1465 1466
/* Power well structure for haswell */
struct i915_power_well {
1467
	const char *name;
1468
	bool always_on;
1469 1470
	/* power well enable/disable usage count */
	int count;
1471 1472
	/* cached hw enabled state */
	bool hw_enabled;
1473
	unsigned long domains;
1474 1475
	/* unique identifier for this power well */
	unsigned long id;
1476 1477 1478 1479 1480
	/*
	 * Arbitraty data associated with this power well. Platform and power
	 * well specific.
	 */
	unsigned long data;
1481
	const struct i915_power_well_ops *ops;
1482 1483
};

1484
struct i915_power_domains {
1485 1486 1487 1488 1489
	/*
	 * Power wells needed for initialization at driver init and suspend
	 * time are on. They are kept on until after the first modeset.
	 */
	bool init_power_on;
1490
	bool initializing;
1491
	int power_well_count;
1492

1493
	struct mutex lock;
1494
	int domain_use_count[POWER_DOMAIN_NUM];
1495
	struct i915_power_well *power_wells;
1496 1497
};

1498
#define MAX_L3_SLICES 2
1499
struct intel_l3_parity {
1500
	u32 *remap_info[MAX_L3_SLICES];
1501
	struct work_struct error_work;
1502
	int which_slice;
1503 1504
};

1505 1506 1507
struct i915_gem_mm {
	/** Memory allocator for GTT stolen memory */
	struct drm_mm stolen;
1508 1509 1510 1511
	/** Protects the usage of the GTT stolen memory allocator. This is
	 * always the inner lock when overlapping with struct_mutex. */
	struct mutex stolen_lock;

1512 1513 1514 1515 1516
	/** List of all objects in gtt_space. Used to restore gtt
	 * mappings on resume */
	struct list_head bound_list;
	/**
	 * List of objects which are not bound to the GTT (thus
1517 1518
	 * are idle and not used by the GPU). These objects may or may
	 * not actually have any pages attached.
1519 1520 1521
	 */
	struct list_head unbound_list;

1522 1523 1524 1525 1526
	/** List of all objects in gtt_space, currently mmaped by userspace.
	 * All objects within this list must also be on bound_list.
	 */
	struct list_head userfault_list;

1527 1528 1529 1530 1531 1532
	/**
	 * List of objects which are pending destruction.
	 */
	struct llist_head free_list;
	struct work_struct free_work;

1533 1534 1535 1536 1537 1538
	/** Usable portion of the GTT for GEM */
	unsigned long stolen_base; /* limited to low memory (32-bit) */

	/** PPGTT used for aliasing the PPGTT with the GTT */
	struct i915_hw_ppgtt *aliasing_ppgtt;

1539
	struct notifier_block oom_notifier;
1540
	struct notifier_block vmap_notifier;
1541
	struct shrinker shrinker;
1542 1543 1544 1545 1546 1547 1548 1549 1550 1551

	/** LRU list of objects with fence regs on them. */
	struct list_head fence_list;

	/**
	 * Are we in a non-interruptible section of code like
	 * modesetting?
	 */
	bool interruptible;

1552
	/* the indicator for dispatch video commands on two BSD rings */
1553
	atomic_t bsd_engine_dispatch_index;
1554

1555 1556 1557 1558 1559 1560
	/** Bit 6 swizzling required for X tiling */
	uint32_t bit_6_swizzle_x;
	/** Bit 6 swizzling required for Y tiling */
	uint32_t bit_6_swizzle_y;

	/* accounting, useful for userland debugging */
1561
	spinlock_t object_stat_lock;
1562
	u64 object_memory;
1563 1564 1565
	u32 object_count;
};

1566
struct drm_i915_error_state_buf {
1567
	struct drm_i915_private *i915;
1568 1569 1570 1571 1572 1573 1574 1575
	unsigned bytes;
	unsigned size;
	int err;
	u8 *buf;
	loff_t start;
	loff_t pos;
};

1576
struct i915_error_state_file_priv {
1577
	struct drm_i915_private *i915;
1578 1579 1580
	struct drm_i915_error_state *error;
};

1581 1582 1583
#define I915_RESET_TIMEOUT (10 * HZ) /* 10s */
#define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */

1584 1585 1586
#define I915_ENGINE_DEAD_TIMEOUT  (4 * HZ)  /* Seqno, head and subunits dead */
#define I915_SEQNO_DEAD_TIMEOUT   (12 * HZ) /* Seqno dead with active head */

1587 1588 1589 1590
struct i915_gpu_error {
	/* For hangcheck timer */
#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1591

1592
	struct delayed_work hangcheck_work;
1593 1594 1595 1596 1597

	/* For reset and error_state handling. */
	spinlock_t lock;
	/* Protected by the above dev->gpu_error.lock. */
	struct drm_i915_error_state *first_error;
1598 1599 1600

	unsigned long missed_irq_rings;

1601
	/**
M
Mika Kuoppala 已提交
1602
	 * State variable controlling the reset flow and count
1603
	 *
M
Mika Kuoppala 已提交
1604
	 * This is a counter which gets incremented when reset is triggered,
1605 1606 1607 1608
	 *
	 * Before the reset commences, the I915_RESET_IN_PROGRESS bit is set
	 * meaning that any waiters holding onto the struct_mutex should
	 * relinquish the lock immediately in order for the reset to start.
M
Mika Kuoppala 已提交
1609 1610 1611 1612 1613 1614 1615 1616 1617
	 *
	 * If reset is not completed succesfully, the I915_WEDGE bit is
	 * set meaning that hardware is terminally sour and there is no
	 * recovery. All waiters on the reset_queue will be woken when
	 * that happens.
	 *
	 * This counter is used by the wait_seqno code to notice that reset
	 * event happened and it needs to restart the entire ioctl (since most
	 * likely the seqno it waited for won't ever signal anytime soon).
1618 1619 1620 1621
	 *
	 * This is important for lock-free wait paths, where no contended lock
	 * naturally enforces the correct ordering between the bail-out of the
	 * waiter and the gpu reset work code.
1622
	 */
1623
	unsigned long reset_count;
1624

1625 1626 1627
	unsigned long flags;
#define I915_RESET_IN_PROGRESS	0
#define I915_WEDGED		(BITS_PER_LONG - 1)
1628

1629 1630 1631 1632 1633 1634
	/**
	 * Waitqueue to signal when a hang is detected. Used to for waiters
	 * to release the struct_mutex for the reset to procede.
	 */
	wait_queue_head_t wait_queue;

1635 1636 1637 1638 1639
	/**
	 * Waitqueue to signal when the reset has completed. Used by clients
	 * that wait for dev_priv->mm.wedged to settle.
	 */
	wait_queue_head_t reset_queue;
1640

1641
	/* For missed irq/seqno simulation. */
1642
	unsigned long test_irq_rings;
1643 1644
};

1645 1646 1647 1648 1649 1650
enum modeset_restore {
	MODESET_ON_LID_OPEN,
	MODESET_DONE,
	MODESET_SUSPENDED,
};

1651 1652 1653 1654 1655
#define DP_AUX_A 0x40
#define DP_AUX_B 0x10
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30

X
Xiong Zhang 已提交
1656 1657 1658 1659
#define DDC_PIN_B  0x05
#define DDC_PIN_C  0x04
#define DDC_PIN_D  0x06

1660
struct ddi_vbt_port_info {
1661 1662 1663 1664 1665 1666
	/*
	 * This is an index in the HDMI/DVI DDI buffer translation table.
	 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
	 * populate this field.
	 */
#define HDMI_LEVEL_SHIFT_UNKNOWN	0xff
1667
	uint8_t hdmi_level_shift;
1668 1669 1670 1671

	uint8_t supports_dvi:1;
	uint8_t supports_hdmi:1;
	uint8_t supports_dp:1;
1672 1673

	uint8_t alternate_aux_channel;
X
Xiong Zhang 已提交
1674
	uint8_t alternate_ddc_pin;
1675 1676 1677

	uint8_t dp_boost_level;
	uint8_t hdmi_boost_level;
1678 1679
};

R
Rodrigo Vivi 已提交
1680 1681 1682 1683 1684
enum psr_lines_to_wait {
	PSR_0_LINES_TO_WAIT = 0,
	PSR_1_LINE_TO_WAIT,
	PSR_4_LINES_TO_WAIT,
	PSR_8_LINES_TO_WAIT
1685 1686
};

1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697 1698
struct intel_vbt_data {
	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits */
	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int lvds_vbt:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
	unsigned int display_clock_mode:1;
	unsigned int fdi_rx_polarity_inverted:1;
1699
	unsigned int panel_type:4;
1700 1701 1702
	int lvds_ssc_freq;
	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

1703 1704
	enum drrs_support_type drrs_type;

1705 1706 1707 1708 1709
	struct {
		int rate;
		int lanes;
		int preemphasis;
		int vswing;
1710
		bool low_vswing;
1711 1712 1713 1714 1715
		bool initialized;
		bool support;
		int bpp;
		struct edp_power_seq pps;
	} edp;
1716

R
Rodrigo Vivi 已提交
1717 1718 1719 1720 1721 1722 1723 1724 1725
	struct {
		bool full_link;
		bool require_aux_wakeup;
		int idle_frames;
		enum psr_lines_to_wait lines_to_wait;
		int tp1_wakeup_time;
		int tp2_tp3_wakeup_time;
	} psr;

1726 1727
	struct {
		u16 pwm_freq_hz;
1728
		bool present;
1729
		bool active_low_pwm;
1730
		u8 min_brightness;	/* min_brightness/255 of max */
1731
		u8 controller;		/* brightness controller number */
1732
		enum intel_backlight_type type;
1733 1734
	} backlight;

1735 1736 1737
	/* MIPI DSI */
	struct {
		u16 panel_id;
1738 1739 1740 1741 1742
		struct mipi_config *config;
		struct mipi_pps_data *pps;
		u8 seq_version;
		u32 size;
		u8 *data;
1743
		const u8 *sequence[MIPI_SEQ_MAX];
1744 1745
	} dsi;

1746 1747 1748
	int crt_ddc_pin;

	int child_dev_num;
1749
	union child_device_config *child_dev;
1750 1751

	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1752
	struct sdvo_device_mapping sdvo_mappings[2];
1753 1754
};

1755 1756 1757 1758 1759
enum intel_ddb_partitioning {
	INTEL_DDB_PART_1_2,
	INTEL_DDB_PART_5_6, /* IVB+ */
};

1760 1761 1762 1763 1764 1765 1766 1767
struct intel_wm_level {
	bool enable;
	uint32_t pri_val;
	uint32_t spr_val;
	uint32_t cur_val;
	uint32_t fbc_val;
};

1768
struct ilk_wm_values {
1769 1770 1771 1772 1773 1774 1775 1776
	uint32_t wm_pipe[3];
	uint32_t wm_lp[3];
	uint32_t wm_lp_spr[3];
	uint32_t wm_linetime[3];
	bool enable_fbc_wm;
	enum intel_ddb_partitioning partitioning;
};

1777
struct vlv_pipe_wm {
1778
	uint16_t plane[I915_MAX_PLANES];
1779
};
1780

1781 1782
struct vlv_sr_wm {
	uint16_t plane;
1783 1784 1785 1786 1787
	uint16_t cursor;
};

struct vlv_wm_ddl_values {
	uint8_t plane[I915_MAX_PLANES];
1788
};
1789

1790 1791 1792
struct vlv_wm_values {
	struct vlv_pipe_wm pipe[3];
	struct vlv_sr_wm sr;
1793
	struct vlv_wm_ddl_values ddl[3];
1794 1795
	uint8_t level;
	bool cxsr;
1796 1797
};

1798
struct skl_ddb_entry {
1799
	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
1800 1801 1802 1803
};

static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
{
1804
	return entry->end - entry->start;
1805 1806
}

1807 1808 1809 1810 1811 1812 1813 1814 1815
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
				       const struct skl_ddb_entry *e2)
{
	if (e1->start == e2->start && e1->end == e2->end)
		return true;

	return false;
}

1816
struct skl_ddb_allocation {
1817
	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1818
	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1819 1820
};

1821
struct skl_wm_values {
1822
	unsigned dirty_pipes;
1823
	struct skl_ddb_allocation ddb;
1824 1825 1826
};

struct skl_wm_level {
L
Lyude 已提交
1827 1828 1829
	bool plane_en;
	uint16_t plane_res_b;
	uint8_t plane_res_l;
1830 1831
};

1832
/*
1833 1834 1835 1836
 * This struct helps tracking the state needed for runtime PM, which puts the
 * device in PCI D3 state. Notice that when this happens, nothing on the
 * graphics device works, even register access, so we don't get interrupts nor
 * anything else.
1837
 *
1838 1839 1840
 * Every piece of our code that needs to actually touch the hardware needs to
 * either call intel_runtime_pm_get or call intel_display_power_get with the
 * appropriate power domain.
1841
 *
1842 1843
 * Our driver uses the autosuspend delay feature, which means we'll only really
 * suspend if we stay with zero refcount for a certain amount of time. The
1844
 * default value is currently very conservative (see intel_runtime_pm_enable), but
1845
 * it can be changed with the standard runtime PM files from sysfs.
1846 1847 1848 1849 1850
 *
 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
 * goes back to false exactly before we reenable the IRQs. We use this variable
 * to check if someone is trying to enable/disable IRQs while they're supposed
 * to be disabled. This shouldn't happen and we'll print some error messages in
1851
 * case it happens.
1852
 *
1853
 * For more, read the Documentation/power/runtime_pm.txt.
1854
 */
1855
struct i915_runtime_pm {
1856
	atomic_t wakeref_count;
1857
	bool suspended;
1858
	bool irqs_enabled;
1859 1860
};

1861 1862 1863 1864 1865
enum intel_pipe_crc_source {
	INTEL_PIPE_CRC_SOURCE_NONE,
	INTEL_PIPE_CRC_SOURCE_PLANE1,
	INTEL_PIPE_CRC_SOURCE_PLANE2,
	INTEL_PIPE_CRC_SOURCE_PF,
1866
	INTEL_PIPE_CRC_SOURCE_PIPE,
D
Daniel Vetter 已提交
1867 1868 1869 1870 1871
	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
	INTEL_PIPE_CRC_SOURCE_TV,
	INTEL_PIPE_CRC_SOURCE_DP_B,
	INTEL_PIPE_CRC_SOURCE_DP_C,
	INTEL_PIPE_CRC_SOURCE_DP_D,
1872
	INTEL_PIPE_CRC_SOURCE_AUTO,
1873 1874 1875
	INTEL_PIPE_CRC_SOURCE_MAX,
};

1876
struct intel_pipe_crc_entry {
1877
	uint32_t frame;
1878 1879 1880
	uint32_t crc[5];
};

1881
#define INTEL_PIPE_CRC_ENTRIES_NR	128
1882
struct intel_pipe_crc {
1883 1884
	spinlock_t lock;
	bool opened;		/* exclusive access to the result file */
1885
	struct intel_pipe_crc_entry *entries;
1886
	enum intel_pipe_crc_source source;
1887
	int head, tail;
1888
	wait_queue_head_t wq;
1889 1890
};

1891
struct i915_frontbuffer_tracking {
1892
	spinlock_t lock;
1893 1894 1895 1896 1897 1898 1899 1900 1901

	/*
	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
	 * scheduled flips.
	 */
	unsigned busy_bits;
	unsigned flip_bits;
};

1902
struct i915_wa_reg {
1903
	i915_reg_t addr;
1904 1905 1906 1907 1908
	u32 value;
	/* bitmask representing WA bits */
	u32 mask;
};

1909 1910 1911 1912 1913 1914 1915
/*
 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
 * allowing it for RCS as we don't foresee any requirement of having
 * a whitelist for other engines. When it is really required for
 * other engines then the limit need to be increased.
 */
#define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1916 1917 1918 1919

struct i915_workarounds {
	struct i915_wa_reg reg[I915_MAX_WA_REGS];
	u32 count;
1920
	u32 hw_whitelist_count[I915_NUM_ENGINES];
1921 1922
};

1923 1924 1925 1926
struct i915_virtual_gpu {
	bool active;
};

1927 1928 1929 1930 1931 1932 1933
/* used in computing the new watermarks state */
struct intel_wm_config {
	unsigned int num_pipes_active;
	bool sprites_enabled;
	bool sprites_scaled;
};

1934 1935 1936 1937 1938
struct i915_oa_format {
	u32 format;
	int size;
};

1939 1940 1941 1942 1943
struct i915_oa_reg {
	i915_reg_t addr;
	u32 value;
};

1944 1945
struct i915_perf_stream;

1946 1947 1948
/**
 * struct i915_perf_stream_ops - the OPs to support a specific stream type
 */
1949
struct i915_perf_stream_ops {
1950 1951 1952 1953
	/**
	 * @enable: Enables the collection of HW samples, either in response to
	 * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened
	 * without `I915_PERF_FLAG_DISABLED`.
1954 1955 1956
	 */
	void (*enable)(struct i915_perf_stream *stream);

1957 1958 1959 1960
	/**
	 * @disable: Disables the collection of HW samples, either in response
	 * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying
	 * the stream.
1961 1962 1963
	 */
	void (*disable)(struct i915_perf_stream *stream);

1964 1965
	/**
	 * @poll_wait: Call poll_wait, passing a wait queue that will be woken
1966 1967 1968 1969 1970 1971
	 * once there is something ready to read() for the stream
	 */
	void (*poll_wait)(struct i915_perf_stream *stream,
			  struct file *file,
			  poll_table *wait);

1972 1973 1974
	/**
	 * @wait_unlocked: For handling a blocking read, wait until there is
	 * something to ready to read() for the stream. E.g. wait on the same
1975
	 * wait queue that would be passed to poll_wait().
1976 1977 1978
	 */
	int (*wait_unlocked)(struct i915_perf_stream *stream);

1979 1980 1981 1982 1983 1984 1985
	/**
	 * @read: Copy buffered metrics as records to userspace
	 * **buf**: the userspace, destination buffer
	 * **count**: the number of bytes to copy, requested by userspace
	 * **offset**: zero at the start of the read, updated as the read
	 * proceeds, it represents how many bytes have been copied so far and
	 * the buffer offset for copying the next record.
1986
	 *
1987 1988
	 * Copy as many buffered i915 perf samples and records for this stream
	 * to userspace as will fit in the given buffer.
1989
	 *
1990 1991
	 * Only write complete records; returning -%ENOSPC if there isn't room
	 * for a complete record.
1992
	 *
1993 1994 1995
	 * Return any error condition that results in a short read such as
	 * -%ENOSPC or -%EFAULT, even though these may be squashed before
	 * returning to userspace.
1996 1997 1998 1999 2000 2001
	 */
	int (*read)(struct i915_perf_stream *stream,
		    char __user *buf,
		    size_t count,
		    size_t *offset);

2002 2003
	/**
	 * @destroy: Cleanup any stream specific resources.
2004 2005 2006 2007 2008 2009
	 *
	 * The stream will always be disabled before this is called.
	 */
	void (*destroy)(struct i915_perf_stream *stream);
};

2010 2011 2012
/**
 * struct i915_perf_stream - state for a single open stream FD
 */
2013
struct i915_perf_stream {
2014 2015 2016
	/**
	 * @dev_priv: i915 drm device
	 */
2017 2018
	struct drm_i915_private *dev_priv;

2019 2020 2021
	/**
	 * @link: Links the stream into ``&drm_i915_private->streams``
	 */
2022 2023
	struct list_head link;

2024 2025 2026 2027 2028
	/**
	 * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
	 * properties given when opening a stream, representing the contents
	 * of a single sample as read() by userspace.
	 */
2029
	u32 sample_flags;
2030 2031 2032 2033 2034 2035

	/**
	 * @sample_size: Considering the configured contents of a sample
	 * combined with the required header size, this is the total size
	 * of a single sample record.
	 */
2036
	int sample_size;
2037

2038 2039 2040 2041
	/**
	 * @ctx: %NULL if measuring system-wide across all contexts or a
	 * specific context that is being monitored.
	 */
2042
	struct i915_gem_context *ctx;
2043 2044 2045 2046 2047 2048

	/**
	 * @enabled: Whether the stream is currently enabled, considering
	 * whether the stream was opened in a disabled state and based
	 * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls.
	 */
2049 2050
	bool enabled;

2051 2052 2053 2054
	/**
	 * @ops: The callbacks providing the implementation of this specific
	 * type of configured stream.
	 */
2055 2056 2057
	const struct i915_perf_stream_ops *ops;
};

2058 2059 2060
/**
 * struct i915_oa_ops - Gen specific implementation of an OA unit stream
 */
2061
struct i915_oa_ops {
2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076
	/**
	 * @init_oa_buffer: Resets the head and tail pointers of the
	 * circular buffer for periodic OA reports.
	 *
	 * Called when first opening a stream for OA metrics, but also may be
	 * called in response to an OA buffer overflow or other error
	 * condition.
	 *
	 * Note it may be necessary to clear the full OA buffer here as part of
	 * maintaining the invariable that new reports must be written to
	 * zeroed memory for us to be able to reliable detect if an expected
	 * report has not yet landed in memory.  (At least on Haswell the OA
	 * buffer tail pointer is not synchronized with reports being visible
	 * to the CPU)
	 */
2077
	void (*init_oa_buffer)(struct drm_i915_private *dev_priv);
2078 2079 2080 2081 2082 2083 2084

	/**
	 * @enable_metric_set: Applies any MUX configuration to set up the
	 * Boolean and Custom (B/C) counters that are part of the counter
	 * reports being sampled. May apply system constraints such as
	 * disabling EU clock gating as required.
	 */
2085
	int (*enable_metric_set)(struct drm_i915_private *dev_priv);
2086 2087 2088 2089 2090

	/**
	 * @disable_metric_set: Remove system constraints associated with using
	 * the OA unit.
	 */
2091
	void (*disable_metric_set)(struct drm_i915_private *dev_priv);
2092 2093 2094 2095

	/**
	 * @oa_enable: Enable periodic sampling
	 */
2096
	void (*oa_enable)(struct drm_i915_private *dev_priv);
2097 2098 2099 2100

	/**
	 * @oa_disable: Disable periodic sampling
	 */
2101
	void (*oa_disable)(struct drm_i915_private *dev_priv);
2102 2103 2104 2105 2106

	/**
	 * @read: Copy data from the circular OA buffer into a given userspace
	 * buffer.
	 */
2107 2108 2109 2110
	int (*read)(struct i915_perf_stream *stream,
		    char __user *buf,
		    size_t count,
		    size_t *offset);
2111 2112 2113 2114 2115 2116 2117 2118 2119 2120 2121 2122 2123 2124 2125

	/**
	 * @oa_buffer_is_empty: Check if OA buffer empty (false positives OK)
	 *
	 * This is either called via fops or the poll check hrtimer (atomic
	 * ctx) without any locks taken.
	 *
	 * It's safe to read OA config state here unlocked, assuming that this
	 * is only called while the stream is enabled, while the global OA
	 * configuration can't be modified.
	 *
	 * Efficiency is more important than avoiding some false positives
	 * here, which will be handled gracefully - likely resulting in an
	 * %EAGAIN error for userspace.
	 */
2126
	bool (*oa_buffer_is_empty)(struct drm_i915_private *dev_priv);
2127 2128
};

2129
struct drm_i915_private {
2130 2131
	struct drm_device drm;

2132
	struct kmem_cache *objects;
2133
	struct kmem_cache *vmas;
2134
	struct kmem_cache *requests;
2135
	struct kmem_cache *dependencies;
2136

2137
	const struct intel_device_info info;
2138 2139 2140 2141 2142

	int relative_constants_mode;

	void __iomem *regs;

2143
	struct intel_uncore uncore;
2144

2145 2146
	struct i915_virtual_gpu vgpu;

2147
	struct intel_gvt *gvt;
2148

2149 2150
	struct intel_guc guc;

2151 2152
	struct intel_csr csr;

2153
	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
2154

2155 2156 2157 2158 2159 2160 2161 2162 2163
	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
	 * controller on different i2c buses. */
	struct mutex gmbus_mutex;

	/**
	 * Base address of the gmbus and gpio block.
	 */
	uint32_t gpio_mmio_base;

2164 2165 2166
	/* MMIO base address for MIPI regs */
	uint32_t mipi_mmio_base;

2167 2168
	uint32_t psr_mmio_base;

2169 2170
	uint32_t pps_mmio_base;

2171 2172
	wait_queue_head_t gmbus_wait_queue;

2173
	struct pci_dev *bridge_dev;
2174
	struct i915_gem_context *kernel_context;
2175
	struct intel_engine_cs *engine[I915_NUM_ENGINES];
2176
	struct i915_vma *semaphore;
2177

2178
	struct drm_dma_handle *status_page_dmah;
2179 2180 2181 2182 2183
	struct resource mch_res;

	/* protects the irq masks */
	spinlock_t irq_lock;

2184 2185 2186
	/* protects the mmio flip data */
	spinlock_t mmio_flip_lock;

2187 2188
	bool display_irqs_enabled;

2189 2190 2191
	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
	struct pm_qos_request pm_qos;

V
Ville Syrjälä 已提交
2192 2193
	/* Sideband mailbox protection */
	struct mutex sb_lock;
2194 2195

	/** Cached value of IMR to avoid reads in updating the bitfield */
2196 2197 2198 2199
	union {
		u32 irq_mask;
		u32 de_irq_mask[I915_MAX_PIPES];
	};
2200
	u32 gt_irq_mask;
2201 2202
	u32 pm_imr;
	u32 pm_ier;
2203
	u32 pm_rps_events;
2204
	u32 pm_guc_events;
2205
	u32 pipestat_irq_mask[I915_MAX_PIPES];
2206

2207
	struct i915_hotplug hotplug;
2208
	struct intel_fbc fbc;
2209
	struct i915_drrs drrs;
2210
	struct intel_opregion opregion;
2211
	struct intel_vbt_data vbt;
2212

2213 2214
	bool preserve_bios_swizzle;

2215 2216 2217
	/* overlay */
	struct intel_overlay *overlay;

2218
	/* backlight registers and fields in struct intel_panel */
2219
	struct mutex backlight_lock;
2220

2221 2222 2223
	/* LVDS info */
	bool no_aux_handshake;

V
Ville Syrjälä 已提交
2224 2225 2226
	/* protects panel power sequencer state */
	struct mutex pps_mutex;

2227 2228 2229 2230
	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */

	unsigned int fsb_freq, mem_freq, is_ddr3;
2231
	unsigned int skl_preferred_vco_freq;
2232 2233 2234 2235 2236 2237 2238 2239
	unsigned int cdclk_freq, max_cdclk_freq;

	/*
	 * For reading holding any crtc lock is sufficient,
	 * for writing must hold all of them.
	 */
	unsigned int atomic_cdclk_freq;

M
Mika Kahola 已提交
2240
	unsigned int max_dotclk_freq;
2241
	unsigned int rawclk_freq;
2242
	unsigned int hpll_freq;
2243
	unsigned int czclk_freq;
2244

2245
	struct {
2246
		unsigned int vco, ref;
2247 2248
	} cdclk_pll;

2249 2250 2251 2252 2253 2254 2255
	/**
	 * wq - Driver workqueue for GEM.
	 *
	 * NOTE: Work items scheduled here are not allowed to grab any modeset
	 * locks, for otherwise the flushing done in the pageflip code will
	 * result in deadlocks.
	 */
2256 2257 2258 2259 2260 2261 2262
	struct workqueue_struct *wq;

	/* Display functions */
	struct drm_i915_display_funcs display;

	/* PCH chipset type */
	enum intel_pch pch_type;
2263
	unsigned short pch_id;
2264 2265 2266

	unsigned long quirks;

2267 2268
	enum modeset_restore modeset_restore;
	struct mutex modeset_restore_lock;
2269
	struct drm_atomic_state *modeset_restore_state;
2270
	struct drm_modeset_acquire_ctx reset_ctx;
2271

2272
	struct list_head vm_list; /* Global list of all address spaces */
2273
	struct i915_ggtt ggtt; /* VM representing the global address space */
B
Ben Widawsky 已提交
2274

2275
	struct i915_gem_mm mm;
2276 2277
	DECLARE_HASHTABLE(mm_structs, 7);
	struct mutex mm_lock;
2278

2279 2280 2281 2282 2283 2284 2285
	/* The hw wants to have a stable context identifier for the lifetime
	 * of the context (for OA, PASID, faults, etc). This is limited
	 * in execlists to 21 bits.
	 */
	struct ida context_hw_ida;
#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */

2286 2287
	/* Kernel Modesetting */

2288 2289
	struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
	struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
2290 2291
	wait_queue_head_t pending_flip_queue;

2292 2293 2294 2295
#ifdef CONFIG_DEBUG_FS
	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif

2296
	/* dpll and cdclk state is protected by connection_mutex */
D
Daniel Vetter 已提交
2297 2298
	int num_shared_dpll;
	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
2299
	const struct intel_dpll_mgr *dpll_mgr;
2300

2301 2302 2303 2304 2305 2306 2307
	/*
	 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
	 * Must be global rather than per dpll, because on some platforms
	 * plls share registers.
	 */
	struct mutex dpll_lock;

2308 2309 2310
	unsigned int active_crtcs;
	unsigned int min_pixclk[I915_MAX_PIPES];

2311
	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
2312

2313
	struct i915_workarounds workarounds;
2314

2315 2316
	struct i915_frontbuffer_tracking fb_tracking;

2317
	u16 orig_clock;
2318

2319
	bool mchbar_need_disable;
2320

2321 2322
	struct intel_l3_parity l3_parity;

B
Ben Widawsky 已提交
2323
	/* Cannot be determined by PCIID. You must always read a register. */
2324
	u32 edram_cap;
B
Ben Widawsky 已提交
2325

2326
	/* gen6+ rps state */
2327
	struct intel_gen6_power_mgmt rps;
2328

2329 2330
	/* ilk-only ips/rps state. Everything in here is protected by the global
	 * mchdev_lock in intel_pm.c */
2331
	struct intel_ilk_power_mgmt ips;
2332

2333
	struct i915_power_domains power_domains;
2334

R
Rodrigo Vivi 已提交
2335
	struct i915_psr psr;
2336

2337
	struct i915_gpu_error gpu_error;
2338

2339 2340
	struct drm_i915_gem_object *vlv_pctx;

2341
#ifdef CONFIG_DRM_FBDEV_EMULATION
2342 2343
	/* list of fbdev register on this device */
	struct intel_fbdev *fbdev;
2344
	struct work_struct fbdev_suspend_work;
2345
#endif
2346 2347

	struct drm_property *broadcast_rgb_property;
2348
	struct drm_property *force_audio_property;
2349

I
Imre Deak 已提交
2350
	/* hda/i915 audio component */
2351
	struct i915_audio_component *audio_component;
I
Imre Deak 已提交
2352
	bool audio_component_registered;
2353 2354 2355 2356 2357
	/**
	 * av_mutex - mutex for audio/video sync
	 *
	 */
	struct mutex av_mutex;
I
Imre Deak 已提交
2358

2359
	uint32_t hw_context_size;
2360
	struct list_head context_list;
2361

2362
	u32 fdi_rx_config;
2363

2364
	/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
2365
	u32 chv_phy_control;
2366 2367 2368 2369 2370 2371
	/*
	 * Shadows for CHV DPLL_MD regs to keep the state
	 * checker somewhat working in the presence hardware
	 * crappiness (can't read out DPLL_MD for pipes B & C).
	 */
	u32 chv_dpll_md[I915_MAX_PIPES];
2372
	u32 bxt_phy_grc;
2373

2374
	u32 suspend_count;
2375
	bool suspended_to_idle;
2376
	struct i915_suspend_saved_registers regfile;
2377
	struct vlv_s0ix_state vlv_s0ix_state;
2378

2379
	enum {
2380 2381 2382 2383 2384
		I915_SAGV_UNKNOWN = 0,
		I915_SAGV_DISABLED,
		I915_SAGV_ENABLED,
		I915_SAGV_NOT_CONTROLLED
	} sagv_status;
2385

2386
	struct {
2387 2388 2389
		/* protects DSPARB registers on pre-g4x/vlv/chv */
		spinlock_t dsparb_lock;

2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400
		/*
		 * Raw watermark latency values:
		 * in 0.1us units for WM0,
		 * in 0.5us units for WM1+.
		 */
		/* primary */
		uint16_t pri_latency[5];
		/* sprite */
		uint16_t spr_latency[5];
		/* cursor */
		uint16_t cur_latency[5];
2401 2402 2403 2404 2405 2406
		/*
		 * Raw watermark memory latency values
		 * for SKL for all 8 levels
		 * in 1us units.
		 */
		uint16_t skl_latency[8];
2407 2408

		/* current hardware state */
2409 2410 2411
		union {
			struct ilk_wm_values hw;
			struct skl_wm_values skl_hw;
2412
			struct vlv_wm_values vlv;
2413
		};
2414 2415

		uint8_t max_level;
2416 2417 2418 2419 2420 2421 2422

		/*
		 * Should be held around atomic WM register writing; also
		 * protects * intel_crtc->wm.active and
		 * cstate->wm.need_postvbl_update.
		 */
		struct mutex wm_mutex;
2423 2424 2425 2426 2427 2428 2429

		/*
		 * Set during HW readout of watermarks/DDB.  Some platforms
		 * need to know when we're still using BIOS-provided values
		 * (which we don't fully trust).
		 */
		bool distrust_bios_wm;
2430 2431
	} wm;

2432 2433
	struct i915_runtime_pm pm;

2434 2435
	struct {
		bool initialized;
2436

2437
		struct kobject *metrics_kobj;
2438
		struct ctl_table_header *sysctl_header;
2439

2440 2441
		struct mutex lock;
		struct list_head streams;
2442

2443 2444
		spinlock_t hook_lock;

2445
		struct {
2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460
			struct i915_perf_stream *exclusive_stream;

			u32 specific_ctx_id;

			struct hrtimer poll_check_timer;
			wait_queue_head_t poll_wq;
			bool pollin;

			bool periodic;
			int period_exponent;
			int timestamp_frequency;

			int tail_margin;

			int metrics_set;
2461 2462 2463 2464 2465

			const struct i915_oa_reg *mux_regs;
			int mux_regs_len;
			const struct i915_oa_reg *b_counter_regs;
			int b_counter_regs_len;
2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478

			struct {
				struct i915_vma *vma;
				u8 *vaddr;
				int format;
				int format_size;
			} oa_buffer;

			u32 gen7_latched_oastatus1;

			struct i915_oa_ops ops;
			const struct i915_oa_format *oa_formats;
			int n_builtin_sets;
2479
		} oa;
2480 2481
	} perf;

2482 2483
	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
	struct {
2484
		void (*resume)(struct drm_i915_private *);
2485
		void (*cleanup_engine)(struct intel_engine_cs *engine);
2486

2487 2488
		struct list_head timelines;
		struct i915_gem_timeline global_timeline;
2489
		u32 active_requests;
2490

2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516
		/**
		 * Is the GPU currently considered idle, or busy executing
		 * userspace requests? Whilst idle, we allow runtime power
		 * management to power down the hardware and display clocks.
		 * In order to reduce the effect on performance, there
		 * is a slight delay before we do so.
		 */
		bool awake;

		/**
		 * We leave the user IRQ off as much as possible,
		 * but this means that requests will finish and never
		 * be retired once the system goes idle. Set a timer to
		 * fire periodically while the ring is running. When it
		 * fires, go retire requests.
		 */
		struct delayed_work retire_work;

		/**
		 * When we detect an idle GPU, we want to turn on
		 * powersaving features. So once we see that there
		 * are no more requests outstanding and no more
		 * arrive within a small period of time, we fire
		 * off the idle_work.
		 */
		struct delayed_work idle_work;
2517 2518

		ktime_t last_init_time;
2519 2520
	} gt;

2521 2522 2523
	/* perform PHY state sanity checks? */
	bool chv_phy_assert[2];

M
Mahesh Kumar 已提交
2524 2525
	bool ipc_enabled;

2526 2527
	/* Used to save the pipe-to-encoder mapping for audio */
	struct intel_encoder *av_enc_map[I915_MAX_PIPES];
2528

2529 2530 2531 2532
	/*
	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
	 * will be rejected. Instead look for a better place.
	 */
2533
};
L
Linus Torvalds 已提交
2534

2535 2536
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
2537
	return container_of(dev, struct drm_i915_private, drm);
2538 2539
}

2540
static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
I
Imre Deak 已提交
2541
{
2542
	return to_i915(dev_get_drvdata(kdev));
I
Imre Deak 已提交
2543 2544
}

2545 2546 2547 2548 2549
static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
{
	return container_of(guc, struct drm_i915_private, guc);
}

2550
/* Simple iterator over all initialised engines */
2551 2552 2553 2554 2555
#define for_each_engine(engine__, dev_priv__, id__) \
	for ((id__) = 0; \
	     (id__) < I915_NUM_ENGINES; \
	     (id__)++) \
		for_each_if ((engine__) = (dev_priv__)->engine[(id__)])
2556

2557 2558 2559 2560 2561 2562
#define __mask_next_bit(mask) ({					\
	int __idx = ffs(mask) - 1;					\
	mask &= ~BIT(__idx);						\
	__idx;								\
})

2563
/* Iterator over subset of engines selected by mask */
2564 2565
#define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
	for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask;	\
2566
	     tmp__ ? (engine__ = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2567

2568 2569 2570 2571 2572 2573 2574
enum hdmi_force_audio {
	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
	HDMI_AUDIO_AUTO,		/* trust EDID */
	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
};

2575
#define I915_GTT_OFFSET_NONE ((u32)-1)
2576

2577 2578
/*
 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2579
 * considered to be the frontbuffer for the given plane interface-wise. This
2580 2581 2582 2583 2584
 * doesn't mean that the hw necessarily already scans it out, but that any
 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
 *
 * We have one bit per pipe and per scanout plane type.
 */
2585 2586
#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2587 2588 2589
#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
#define INTEL_FRONTBUFFER_CURSOR(pipe) \
2590 2591 2592
	(1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
	(1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2593
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2594
	(1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2595
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2596
	(0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2597

2598 2599 2600 2601 2602 2603 2604 2605 2606 2607 2608 2609 2610 2611 2612 2613 2614 2615 2616 2617 2618 2619 2620 2621 2622 2623
/*
 * Optimised SGL iterator for GEM objects
 */
static __always_inline struct sgt_iter {
	struct scatterlist *sgp;
	union {
		unsigned long pfn;
		dma_addr_t dma;
	};
	unsigned int curr;
	unsigned int max;
} __sgt_iter(struct scatterlist *sgl, bool dma) {
	struct sgt_iter s = { .sgp = sgl };

	if (s.sgp) {
		s.max = s.curr = s.sgp->offset;
		s.max += s.sgp->length;
		if (dma)
			s.dma = sg_dma_address(s.sgp);
		else
			s.pfn = page_to_pfn(sg_page(s.sgp));
	}

	return s;
}

2624 2625 2626 2627 2628 2629 2630 2631
static inline struct scatterlist *____sg_next(struct scatterlist *sg)
{
	++sg;
	if (unlikely(sg_is_chain(sg)))
		sg = sg_chain_ptr(sg);
	return sg;
}

2632 2633 2634 2635 2636 2637 2638 2639 2640 2641 2642 2643 2644 2645
/**
 * __sg_next - return the next scatterlist entry in a list
 * @sg:		The current sg entry
 *
 * Description:
 *   If the entry is the last, return NULL; otherwise, step to the next
 *   element in the array (@sg@+1). If that's a chain pointer, follow it;
 *   otherwise just return the pointer to the current element.
 **/
static inline struct scatterlist *__sg_next(struct scatterlist *sg)
{
#ifdef CONFIG_DEBUG_SG
	BUG_ON(sg->sg_magic != SG_MAGIC);
#endif
2646
	return sg_is_last(sg) ? NULL : ____sg_next(sg);
2647 2648
}

2649 2650 2651 2652 2653 2654 2655 2656 2657 2658
/**
 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
 * @__dmap:	DMA address (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_dma(__dmap, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, true);			\
	     ((__dmap) = (__iter).dma + (__iter).curr);			\
	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
2659
	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2660 2661 2662 2663 2664 2665 2666 2667 2668 2669 2670 2671

/**
 * for_each_sgt_page - iterate over the pages of the given sg_table
 * @__pp:	page pointer (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_page(__pp, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, false);		\
	     ((__pp) = (__iter).pfn == 0 ? NULL :			\
	      pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
2672
	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2673

2674 2675 2676 2677 2678 2679 2680
static inline const struct intel_device_info *
intel_info(const struct drm_i915_private *dev_priv)
{
	return &dev_priv->info;
}

#define INTEL_INFO(dev_priv)	intel_info((dev_priv))
2681

2682
#define INTEL_GEN(dev_priv)	((dev_priv)->info.gen)
2683
#define INTEL_DEVID(dev_priv)	((dev_priv)->info.device_id)
2684

2685
#define REVID_FOREVER		0xff
2686
#define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
2687 2688 2689 2690 2691 2692 2693

#define GEN_FOREVER (0)
/*
 * Returns true if Gen is in inclusive range [Start, End].
 *
 * Use GEN_FOREVER for unbound start and or end.
 */
2694
#define IS_GEN(dev_priv, s, e) ({ \
2695 2696 2697 2698 2699 2700 2701 2702 2703
	unsigned int __s = (s), __e = (e); \
	BUILD_BUG_ON(!__builtin_constant_p(s)); \
	BUILD_BUG_ON(!__builtin_constant_p(e)); \
	if ((__s) != GEN_FOREVER) \
		__s = (s) - 1; \
	if ((__e) == GEN_FOREVER) \
		__e = BITS_PER_LONG - 1; \
	else \
		__e = (e) - 1; \
2704
	!!((dev_priv)->info.gen_mask & GENMASK((__e), (__s))); \
2705 2706
})

2707 2708 2709 2710 2711 2712 2713 2714
/*
 * Return true if revision is in range [since,until] inclusive.
 *
 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
 */
#define IS_REVID(p, since, until) \
	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))

2715 2716
#define IS_I830(dev_priv)	((dev_priv)->info.platform == INTEL_I830)
#define IS_I845G(dev_priv)	((dev_priv)->info.platform == INTEL_I845G)
2717
#define IS_I85X(dev_priv)	((dev_priv)->info.platform == INTEL_I85X)
2718
#define IS_I865G(dev_priv)	((dev_priv)->info.platform == INTEL_I865G)
2719
#define IS_I915G(dev_priv)	((dev_priv)->info.platform == INTEL_I915G)
2720 2721
#define IS_I915GM(dev_priv)	((dev_priv)->info.platform == INTEL_I915GM)
#define IS_I945G(dev_priv)	((dev_priv)->info.platform == INTEL_I945G)
2722
#define IS_I945GM(dev_priv)	((dev_priv)->info.platform == INTEL_I945GM)
2723 2724
#define IS_I965G(dev_priv)	((dev_priv)->info.platform == INTEL_I965G)
#define IS_I965GM(dev_priv)	((dev_priv)->info.platform == INTEL_I965GM)
2725 2726 2727
#define IS_G45(dev_priv)	((dev_priv)->info.platform == INTEL_G45)
#define IS_GM45(dev_priv)	((dev_priv)->info.platform == INTEL_GM45)
#define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))
2728 2729
#define IS_PINEVIEW_G(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa001)
#define IS_PINEVIEW_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa011)
2730
#define IS_PINEVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_PINEVIEW)
2731
#define IS_G33(dev_priv)	((dev_priv)->info.platform == INTEL_G33)
2732
#define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
2733
#define IS_IVYBRIDGE(dev_priv)	((dev_priv)->info.platform == INTEL_IVYBRIDGE)
2734 2735 2736
#define IS_IVB_GT1(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0156 || \
				 INTEL_DEVID(dev_priv) == 0x0152 || \
				 INTEL_DEVID(dev_priv) == 0x015a)
2737 2738 2739 2740 2741 2742 2743 2744
#define IS_VALLEYVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_VALLEYVIEW)
#define IS_CHERRYVIEW(dev_priv)	((dev_priv)->info.platform == INTEL_CHERRYVIEW)
#define IS_HASWELL(dev_priv)	((dev_priv)->info.platform == INTEL_HASWELL)
#define IS_BROADWELL(dev_priv)	((dev_priv)->info.platform == INTEL_BROADWELL)
#define IS_SKYLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_SKYLAKE)
#define IS_BROXTON(dev_priv)	((dev_priv)->info.platform == INTEL_BROXTON)
#define IS_KABYLAKE(dev_priv)	((dev_priv)->info.platform == INTEL_KABYLAKE)
#define IS_GEMINILAKE(dev_priv)	((dev_priv)->info.platform == INTEL_GEMINILAKE)
2745
#define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
2746 2747 2748 2749 2750 2751
#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
#define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||	\
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||	\
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
V
Ville Syrjälä 已提交
2752
/* ULX machines are also considered ULT. */
2753 2754 2755 2756 2757 2758 2759 2760
#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
#define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
#define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
2761
/* ULX machines are also considered ULT. */
2762 2763 2764 2765 2766 2767 2768 2769 2770 2771 2772 2773 2774 2775 2776 2777 2778 2779 2780 2781 2782 2783
#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
				 INTEL_DEVID(dev_priv) == 0x0A1E)
#define IS_SKL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x1906 || \
				 INTEL_DEVID(dev_priv) == 0x1913 || \
				 INTEL_DEVID(dev_priv) == 0x1916 || \
				 INTEL_DEVID(dev_priv) == 0x1921 || \
				 INTEL_DEVID(dev_priv) == 0x1926)
#define IS_SKL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x190E || \
				 INTEL_DEVID(dev_priv) == 0x1915 || \
				 INTEL_DEVID(dev_priv) == 0x191E)
#define IS_KBL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x5906 || \
				 INTEL_DEVID(dev_priv) == 0x5913 || \
				 INTEL_DEVID(dev_priv) == 0x5916 || \
				 INTEL_DEVID(dev_priv) == 0x5921 || \
				 INTEL_DEVID(dev_priv) == 0x5926)
#define IS_KBL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x590E || \
				 INTEL_DEVID(dev_priv) == 0x5915 || \
				 INTEL_DEVID(dev_priv) == 0x591E)
#define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0020)
#define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \
				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x0030)
2784

2785
#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
2786

2787 2788 2789 2790 2791 2792
#define SKL_REVID_A0		0x0
#define SKL_REVID_B0		0x1
#define SKL_REVID_C0		0x2
#define SKL_REVID_D0		0x3
#define SKL_REVID_E0		0x4
#define SKL_REVID_F0		0x5
2793 2794
#define SKL_REVID_G0		0x6
#define SKL_REVID_H0		0x7
2795

2796 2797
#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))

2798
#define BXT_REVID_A0		0x0
2799
#define BXT_REVID_A1		0x1
2800
#define BXT_REVID_B0		0x3
2801
#define BXT_REVID_B_LAST	0x8
2802
#define BXT_REVID_C0		0x9
N
Nick Hoath 已提交
2803

2804 2805
#define IS_BXT_REVID(dev_priv, since, until) \
	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
2806

M
Mika Kuoppala 已提交
2807 2808
#define KBL_REVID_A0		0x0
#define KBL_REVID_B0		0x1
2809 2810 2811
#define KBL_REVID_C0		0x2
#define KBL_REVID_D0		0x3
#define KBL_REVID_E0		0x4
M
Mika Kuoppala 已提交
2812

2813 2814
#define IS_KBL_REVID(dev_priv, since, until) \
	(IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
M
Mika Kuoppala 已提交
2815

2816 2817 2818 2819 2820 2821
/*
 * The genX designation typically refers to the render engine, so render
 * capability related checks should use IS_GEN, while display and other checks
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 * chips, etc.).
 */
2822 2823 2824 2825 2826 2827 2828 2829
#define IS_GEN2(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(1)))
#define IS_GEN3(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(2)))
#define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))
#define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))
#define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))
#define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
#define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
#define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
2830

2831 2832
#define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && INTEL_INFO(dev_priv)->is_lp)

2833 2834 2835 2836 2837 2838 2839 2840 2841
#define ENGINE_MASK(id)	BIT(id)
#define RENDER_RING	ENGINE_MASK(RCS)
#define BSD_RING	ENGINE_MASK(VCS)
#define BLT_RING	ENGINE_MASK(BCS)
#define VEBOX_RING	ENGINE_MASK(VECS)
#define BSD2_RING	ENGINE_MASK(VCS2)
#define ALL_ENGINES	(~0)

#define HAS_ENGINE(dev_priv, id) \
2842
	(!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
2843 2844 2845 2846 2847 2848

#define HAS_BSD(dev_priv)	HAS_ENGINE(dev_priv, VCS)
#define HAS_BSD2(dev_priv)	HAS_ENGINE(dev_priv, VCS2)
#define HAS_BLT(dev_priv)	HAS_ENGINE(dev_priv, BCS)
#define HAS_VEBOX(dev_priv)	HAS_ENGINE(dev_priv, VECS)

2849 2850 2851
#define HAS_LLC(dev_priv)	((dev_priv)->info.has_llc)
#define HAS_SNOOP(dev_priv)	((dev_priv)->info.has_snoop)
#define HAS_EDRAM(dev_priv)	(!!((dev_priv)->edram_cap & EDRAM_ENABLED))
2852 2853
#define HAS_WT(dev_priv)	((IS_HASWELL(dev_priv) || \
				 IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
2854

2855
#define HWS_NEEDS_PHYSICAL(dev_priv)	((dev_priv)->info.hws_needs_physical)
2856

2857 2858 2859 2860 2861 2862 2863 2864 2865 2866
#define HAS_HW_CONTEXTS(dev_priv)	    ((dev_priv)->info.has_hw_contexts)
#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
		((dev_priv)->info.has_logical_ring_contexts)
#define USES_PPGTT(dev_priv)		(i915.enable_ppgtt)
#define USES_FULL_PPGTT(dev_priv)	(i915.enable_ppgtt >= 2)
#define USES_FULL_48BIT_PPGTT(dev_priv)	(i915.enable_ppgtt == 3)

#define HAS_OVERLAY(dev_priv)		 ((dev_priv)->info.has_overlay)
#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
		((dev_priv)->info.overlay_needs_physical)
2867

2868
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
2869
#define HAS_BROKEN_CS_TLB(dev_priv)	(IS_I830(dev_priv) || IS_I845G(dev_priv))
2870 2871

/* WaRsDisableCoarsePowerGating:skl,bxt */
2872 2873 2874 2875
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
	(IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
	 IS_SKL_GT3(dev_priv) || \
	 IS_SKL_GT4(dev_priv))
2876

2877 2878 2879 2880 2881 2882
/*
 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
 * even when in MSI mode. This results in spurious interrupt warnings if the
 * legacy irq no. is shared with another device. The kernel then disables that
 * interrupt source and so prevents the other device from working properly.
 */
2883 2884
#define HAS_AUX_IRQ(dev_priv)   ((dev_priv)->info.gen >= 5)
#define HAS_GMBUS_IRQ(dev_priv) ((dev_priv)->info.has_gmbus_irq)
2885

2886 2887 2888
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
2889 2890 2891
#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \
					 !(IS_I915G(dev_priv) || \
					 IS_I915GM(dev_priv)))
2892 2893
#define SUPPORTS_TV(dev_priv)		((dev_priv)->info.supports_tv)
#define I915_HAS_HOTPLUG(dev_priv)	((dev_priv)->info.has_hotplug)
2894

2895 2896 2897
#define HAS_FW_BLC(dev_priv) 	(INTEL_GEN(dev_priv) > 2)
#define HAS_PIPE_CXSR(dev_priv) ((dev_priv)->info.has_pipe_cxsr)
#define HAS_FBC(dev_priv)	((dev_priv)->info.has_fbc)
2898

2899
#define HAS_IPS(dev_priv)	(IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
2900

2901
#define HAS_DP_MST(dev_priv)	((dev_priv)->info.has_dp_mst)
2902

2903 2904 2905 2906 2907
#define HAS_DDI(dev_priv)		 ((dev_priv)->info.has_ddi)
#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
#define HAS_PSR(dev_priv)		 ((dev_priv)->info.has_psr)
#define HAS_RC6(dev_priv)		 ((dev_priv)->info.has_rc6)
#define HAS_RC6p(dev_priv)		 ((dev_priv)->info.has_rc6p)
P
Paulo Zanoni 已提交
2908

2909
#define HAS_CSR(dev_priv)	((dev_priv)->info.has_csr)
2910

2911
#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
2912 2913
#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)

2914 2915 2916 2917 2918
/*
 * For now, anything with a GuC requires uCode loading, and then supports
 * command submission once loaded. But these are logically independent
 * properties, so we have separate macros to test them.
 */
2919 2920 2921
#define HAS_GUC(dev_priv)	((dev_priv)->info.has_guc)
#define HAS_GUC_UCODE(dev_priv)	(HAS_GUC(dev_priv))
#define HAS_GUC_SCHED(dev_priv)	(HAS_GUC(dev_priv))
2922

2923
#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
2924

2925
#define HAS_POOLED_EU(dev_priv)	((dev_priv)->info.has_pooled_eu)
2926

2927 2928 2929 2930 2931 2932
#define INTEL_PCH_DEVICE_ID_MASK		0xff00
#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
2933 2934
#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
2935
#define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA200
2936
#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
2937
#define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
2938
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
2939

2940 2941 2942 2943
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
#define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP)
#define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
#define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
2944 2945 2946 2947
#define HAS_PCH_LPT_LP(dev_priv) \
	((dev_priv)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
#define HAS_PCH_LPT_H(dev_priv) \
	((dev_priv)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2948 2949 2950 2951
#define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
#define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
2952

2953
#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display)
2954

2955 2956
#define HAS_LSPCON(dev_priv) (IS_GEN9(dev_priv))

2957
/* DPF == dynamic parity feature */
2958
#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
2959 2960
#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
				 2 : HAS_L3_DPF(dev_priv))
2961

2962
#define GT_FREQUENCY_MULTIPLIER 50
A
Akash Goel 已提交
2963
#define GEN9_FREQ_SCALER 3
2964

2965 2966
#define HAS_DECOUPLED_MMIO(dev_priv) (INTEL_INFO(dev_priv)->has_decoupled_mmio)

2967 2968
#include "i915_trace.h"

2969 2970 2971 2972 2973 2974 2975 2976 2977
static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
#ifdef CONFIG_INTEL_IOMMU
	if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
		return true;
#endif
	return false;
}

2978
int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2979
				int enable_ppgtt);
2980

2981 2982
bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);

2983
/* i915_drv.c */
2984 2985 2986 2987 2988 2989 2990
void __printf(3, 4)
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
	      const char *fmt, ...);

#define i915_report_error(dev_priv, fmt, ...)				   \
	__i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)

2991
#ifdef CONFIG_COMPAT
D
Dave Airlie 已提交
2992 2993
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);
2994 2995
#else
#define i915_compat_ioctl NULL
2996
#endif
2997 2998 2999 3000 3001
extern const struct dev_pm_ops i915_pm_ops;

extern int i915_driver_load(struct pci_dev *pdev,
			    const struct pci_device_id *ent);
extern void i915_driver_unload(struct drm_device *dev);
3002 3003
extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
3004
extern void i915_reset(struct drm_i915_private *dev_priv);
3005
extern int intel_guc_reset(struct drm_i915_private *dev_priv);
3006
extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
3007
extern void intel_hangcheck_init(struct drm_i915_private *dev_priv);
3008 3009 3010 3011
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
3012
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
3013

3014
/* intel_hotplug.c */
3015 3016
void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
			   u32 pin_mask, u32 long_mask);
3017 3018 3019
void intel_hpd_init(struct drm_i915_private *dev_priv);
void intel_hpd_init_work(struct drm_i915_private *dev_priv);
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
3020
bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
3021 3022
bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
3023

L
Linus Torvalds 已提交
3024
/* i915_irq.c */
3025 3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041
static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
{
	unsigned long delay;

	if (unlikely(!i915.enable_hangcheck))
		return;

	/* Don't continually defer the hangcheck so that it is always run at
	 * least once after work has been scheduled on any ring. Otherwise,
	 * we will ignore a hung ring if a second ring is kept busy.
	 */

	delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
	queue_delayed_work(system_long_wq,
			   &dev_priv->gpu_error.hangcheck_work, delay);
}

3042
__printf(3, 4)
3043 3044
void i915_handle_error(struct drm_i915_private *dev_priv,
		       u32 engine_mask,
3045
		       const char *fmt, ...);
L
Linus Torvalds 已提交
3046

3047
extern void intel_irq_init(struct drm_i915_private *dev_priv);
3048 3049
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
3050

3051 3052
extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
3053
					bool restore_forcewake);
3054
extern void intel_uncore_init(struct drm_i915_private *dev_priv);
3055
extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
3056
extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
3057 3058 3059
extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
					 bool restore);
3060
const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
3061
void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
3062
				enum forcewake_domains domains);
3063
void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
3064
				enum forcewake_domains domains);
3065 3066 3067 3068 3069 3070 3071
/* Like above but the caller must manage the uncore.lock itself.
 * Must be used with I915_READ_FW and friends.
 */
void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
3072 3073
u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);

3074
void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
3075

3076 3077 3078 3079 3080 3081 3082 3083 3084 3085 3086
int intel_wait_for_register(struct drm_i915_private *dev_priv,
			    i915_reg_t reg,
			    const u32 mask,
			    const u32 value,
			    const unsigned long timeout_ms);
int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
			       i915_reg_t reg,
			       const u32 mask,
			       const u32 value,
			       const unsigned long timeout_ms);

3087 3088
static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
{
3089
	return dev_priv->gvt;
3090 3091
}

3092
static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
3093
{
3094
	return dev_priv->vgpu.active;
3095
}
3096

3097
void
3098
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3099
		     u32 status_mask);
3100 3101

void
3102
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
3103
		      u32 status_mask);
3104

3105 3106
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
3107 3108 3109
void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
				   uint32_t mask,
				   uint32_t bits);
3110 3111 3112 3113 3114 3115 3116 3117 3118 3119 3120 3121 3122
void ilk_update_display_irq(struct drm_i915_private *dev_priv,
			    uint32_t interrupt_mask,
			    uint32_t enabled_irq_mask);
static inline void
ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, bits);
}
static inline void
ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, 0);
}
3123 3124 3125 3126 3127 3128 3129 3130 3131 3132 3133 3134 3135 3136
void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
			 enum pipe pipe,
			 uint32_t interrupt_mask,
			 uint32_t enabled_irq_mask);
static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
				       enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
}
static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
					enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
}
3137 3138 3139
void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask);
3140 3141 3142 3143 3144 3145 3146 3147 3148 3149 3150
static inline void
ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, bits);
}
static inline void
ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, 0);
}

3151 3152 3153 3154 3155 3156 3157 3158 3159
/* i915_gem.c */
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3160 3161
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3162 3163 3164 3165 3166 3167
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
			     struct drm_file *file_priv);
int i915_gem_execbuffer(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
J
Jesse Barnes 已提交
3168 3169
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
3170 3171
int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
B
Ben Widawsky 已提交
3172 3173 3174 3175
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
3176 3177
int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
3178 3179
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
3180 3181 3182 3183
int i915_gem_set_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
int i915_gem_get_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3184
void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3185 3186
int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file);
3187 3188
int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
3189 3190
int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3191 3192
int i915_gem_load_init(struct drm_i915_private *dev_priv);
void i915_gem_load_cleanup(struct drm_i915_private *dev_priv);
3193
void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3194
int i915_gem_freeze(struct drm_i915_private *dev_priv);
3195 3196
int i915_gem_freeze_late(struct drm_i915_private *dev_priv);

3197
void *i915_gem_object_alloc(struct drm_i915_private *dev_priv);
3198
void i915_gem_object_free(struct drm_i915_gem_object *obj);
3199 3200
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			 const struct drm_i915_gem_object_ops *ops);
3201 3202 3203 3204 3205
struct drm_i915_gem_object *
i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size);
struct drm_i915_gem_object *
i915_gem_object_create_from_data(struct drm_i915_private *dev_priv,
				 const void *data, size_t size);
3206
void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3207
void i915_gem_free_object(struct drm_gem_object *obj);
3208

C
Chris Wilson 已提交
3209
struct i915_vma * __must_check
3210 3211
i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
			 const struct i915_ggtt_view *view,
3212
			 u64 size,
3213 3214
			 u64 alignment,
			 u64 flags);
3215

3216
int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3217
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3218

3219 3220
void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv);

C
Chris Wilson 已提交
3221
static inline int __sg_page_count(const struct scatterlist *sg)
3222
{
3223 3224
	return sg->length >> PAGE_SHIFT;
}
3225

3226 3227 3228
struct scatterlist *
i915_gem_object_get_sg(struct drm_i915_gem_object *obj,
		       unsigned int n, unsigned int *offset);
3229

3230 3231 3232
struct page *
i915_gem_object_get_page(struct drm_i915_gem_object *obj,
			 unsigned int n);
3233

3234 3235 3236
struct page *
i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj,
			       unsigned int n);
3237

3238 3239 3240
dma_addr_t
i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj,
				unsigned long n);
3241

3242 3243
void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj,
				 struct sg_table *pages);
C
Chris Wilson 已提交
3244 3245 3246 3247 3248
int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj);

static inline int __must_check
i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
{
3249
	might_lock(&obj->mm.lock);
C
Chris Wilson 已提交
3250

3251
	if (atomic_inc_not_zero(&obj->mm.pages_pin_count))
C
Chris Wilson 已提交
3252 3253 3254 3255 3256 3257 3258
		return 0;

	return __i915_gem_object_get_pages(obj);
}

static inline void
__i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
3259
{
C
Chris Wilson 已提交
3260 3261
	GEM_BUG_ON(!obj->mm.pages);

3262
	atomic_inc(&obj->mm.pages_pin_count);
C
Chris Wilson 已提交
3263 3264 3265 3266 3267
}

static inline bool
i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj)
{
3268
	return atomic_read(&obj->mm.pages_pin_count);
C
Chris Wilson 已提交
3269 3270 3271 3272 3273 3274 3275 3276
}

static inline void
__i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
{
	GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
	GEM_BUG_ON(!obj->mm.pages);

3277 3278
	atomic_dec(&obj->mm.pages_pin_count);
	GEM_BUG_ON(atomic_read(&obj->mm.pages_pin_count) < obj->bind_count);
3279
}
3280

3281 3282
static inline void
i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
3283
{
C
Chris Wilson 已提交
3284
	__i915_gem_object_unpin_pages(obj);
3285 3286
}

3287 3288 3289 3290 3291 3292 3293
enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */
	I915_MM_NORMAL = 0,
	I915_MM_SHRINKER
};

void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj,
				 enum i915_mm_subclass subclass);
3294
void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj);
C
Chris Wilson 已提交
3295

3296 3297 3298 3299 3300
enum i915_map_type {
	I915_MAP_WB = 0,
	I915_MAP_WC,
};

3301 3302 3303
/**
 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
 * @obj - the object to map into kernel address space
3304
 * @type - the type of mapping, used to select pgprot_t
3305 3306 3307
 *
 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
 * pages and then returns a contiguous mapping of the backing storage into
3308 3309
 * the kernel address space. Based on the @type of mapping, the PTE will be
 * set to either WriteBack or WriteCombine (via pgprot_t).
3310
 *
3311 3312
 * The caller is responsible for calling i915_gem_object_unpin_map() when the
 * mapping is no longer required.
3313
 *
3314 3315
 * Returns the pointer through which to access the mapped object, or an
 * ERR_PTR() on error.
3316
 */
3317 3318
void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
					   enum i915_map_type type);
3319 3320 3321 3322 3323 3324 3325 3326 3327 3328 3329 3330 3331 3332 3333

/**
 * i915_gem_object_unpin_map - releases an earlier mapping
 * @obj - the object to unmap
 *
 * After pinning the object and mapping its pages, once you are finished
 * with your access, call i915_gem_object_unpin_map() to release the pin
 * upon the mapping. Once the pin count reaches zero, that mapping may be
 * removed.
 */
static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3334 3335 3336 3337 3338 3339 3340 3341 3342 3343 3344 3345 3346 3347
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
				    unsigned int *needs_clflush);
int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
				     unsigned int *needs_clflush);
#define CLFLUSH_BEFORE 0x1
#define CLFLUSH_AFTER 0x2
#define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)

static inline void
i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3348
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
B
Ben Widawsky 已提交
3349
void i915_vma_move_to_active(struct i915_vma *vma,
3350 3351
			     struct drm_i915_gem_request *req,
			     unsigned int flags);
3352 3353 3354
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
3355 3356
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
		      uint32_t handle, uint64_t *offset);
3357
int i915_gem_mmap_gtt_version(void);
3358 3359 3360 3361 3362

void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits);

3363
int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno);
3364

3365
struct drm_i915_gem_request *
3366
i915_gem_find_active_request(struct intel_engine_cs *engine);
3367

3368
void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3369

3370 3371
static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
{
3372
	return unlikely(test_bit(I915_RESET_IN_PROGRESS, &error->flags));
3373 3374
}

3375
static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
3376
{
3377
	return unlikely(test_bit(I915_WEDGED, &error->flags));
3378 3379
}

3380
static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
3381
{
3382
	return i915_reset_in_progress(error) | i915_terminally_wedged(error);
M
Mika Kuoppala 已提交
3383 3384 3385 3386
}

static inline u32 i915_reset_count(struct i915_gpu_error *error)
{
3387
	return READ_ONCE(error->reset_count);
3388
}
3389

3390 3391
void i915_gem_reset(struct drm_i915_private *dev_priv);
void i915_gem_set_wedged(struct drm_i915_private *dev_priv);
3392
void i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3393 3394
int __must_check i915_gem_init(struct drm_i915_private *dev_priv);
int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv);
3395
void i915_gem_init_swizzling(struct drm_i915_private *dev_priv);
3396
void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv);
3397
int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
3398
					unsigned int flags);
3399 3400
int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv);
void i915_gem_resume(struct drm_i915_private *dev_priv);
3401
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3402 3403 3404 3405
int i915_gem_object_wait(struct drm_i915_gem_object *obj,
			 unsigned int flags,
			 long timeout,
			 struct intel_rps_client *rps);
3406 3407 3408 3409 3410
int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj,
				  unsigned int flags,
				  int priority);
#define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX

3411
int __must_check
3412 3413 3414
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
				  bool write);
int __must_check
3415
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
C
Chris Wilson 已提交
3416
struct i915_vma * __must_check
3417 3418
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
3419
				     const struct i915_ggtt_view *view);
C
Chris Wilson 已提交
3420
void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3421
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3422
				int align);
3423
int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3424
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3425

3426 3427 3428
u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u64 size,
			   int tiling_mode);
u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
3429
				int tiling_mode, bool fenced);
3430

3431 3432 3433
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);

3434 3435 3436 3437 3438 3439
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
				struct dma_buf *dma_buf);

struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
				struct drm_gem_object *gem_obj, int flags);

3440
struct i915_vma *
3441
i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
C
Chris Wilson 已提交
3442 3443
		     struct i915_address_space *vm,
		     const struct i915_ggtt_view *view);
3444

3445 3446
struct i915_vma *
i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
C
Chris Wilson 已提交
3447 3448
				  struct i915_address_space *vm,
				  const struct i915_ggtt_view *view);
3449

3450 3451 3452 3453 3454 3455
static inline struct i915_hw_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space *vm)
{
	return container_of(vm, struct i915_hw_ppgtt, base);
}

C
Chris Wilson 已提交
3456 3457 3458
static inline struct i915_vma *
i915_gem_object_to_ggtt(struct drm_i915_gem_object *obj,
			const struct i915_ggtt_view *view)
3459
{
C
Chris Wilson 已提交
3460
	return i915_gem_obj_to_vma(obj, &to_i915(obj->base.dev)->ggtt.base, view);
3461 3462
}

C
Chris Wilson 已提交
3463 3464 3465
static inline unsigned long
i915_gem_object_ggtt_offset(struct drm_i915_gem_object *o,
			    const struct i915_ggtt_view *view)
3466
{
3467
	return i915_ggtt_offset(i915_gem_object_to_ggtt(o, view));
3468
}
3469

J
Joonas Lahtinen 已提交
3470
/* i915_gem_fence_reg.c */
3471 3472 3473
int __must_check i915_vma_get_fence(struct i915_vma *vma);
int __must_check i915_vma_put_fence(struct i915_vma *vma);

3474
void i915_gem_restore_fences(struct drm_i915_private *dev_priv);
3475

3476
void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv);
3477 3478 3479 3480
void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj,
				       struct sg_table *pages);
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj,
					 struct sg_table *pages);
3481

3482
/* i915_gem_context.c */
3483
int __must_check i915_gem_context_init(struct drm_i915_private *dev_priv);
3484
void i915_gem_context_lost(struct drm_i915_private *dev_priv);
3485
void i915_gem_context_fini(struct drm_i915_private *dev_priv);
3486
int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3487
void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3488
int i915_switch_context(struct drm_i915_gem_request *req);
3489
int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv);
3490
void i915_gem_context_free(struct kref *ctx_ref);
3491 3492
struct i915_gem_context *
i915_gem_context_create_gvt(struct drm_device *dev);
3493 3494 3495 3496 3497 3498

static inline struct i915_gem_context *
i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
{
	struct i915_gem_context *ctx;

3499
	lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3500 3501 3502 3503 3504 3505 3506 3507

	ctx = idr_find(&file_priv->context_idr, id);
	if (!ctx)
		return ERR_PTR(-ENOENT);

	return ctx;
}

3508 3509
static inline struct i915_gem_context *
i915_gem_context_get(struct i915_gem_context *ctx)
3510
{
3511
	kref_get(&ctx->ref);
3512
	return ctx;
3513 3514
}

3515
static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3516
{
3517
	lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3518
	kref_put(&ctx->ref, i915_gem_context_free);
3519 3520
}

3521 3522 3523 3524 3525 3526 3527
static inline void i915_gem_context_put_unlocked(struct i915_gem_context *ctx)
{
	kref_put_mutex(&ctx->ref,
		       i915_gem_context_free,
		       &ctx->i915->drm.struct_mutex);
}

C
Chris Wilson 已提交
3528 3529 3530 3531 3532 3533 3534 3535 3536 3537
static inline struct intel_timeline *
i915_gem_context_lookup_timeline(struct i915_gem_context *ctx,
				 struct intel_engine_cs *engine)
{
	struct i915_address_space *vm;

	vm = ctx->ppgtt ? &ctx->ppgtt->base : &ctx->i915->ggtt.base;
	return &vm->timeline.engine[engine->id];
}

3538
static inline bool i915_gem_context_is_default(const struct i915_gem_context *c)
3539
{
3540
	return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3541 3542
}

3543 3544 3545 3546
int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
				  struct drm_file *file);
int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
				   struct drm_file *file);
3547 3548 3549 3550
int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file_priv);
int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file_priv);
3551 3552
int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
				       struct drm_file *file);
3553

3554 3555 3556
int i915_perf_open_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file);

3557
/* i915_gem_evict.c */
3558
int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3559
					  u64 min_size, u64 alignment,
3560
					  unsigned cache_level,
3561
					  u64 start, u64 end,
3562
					  unsigned flags);
3563 3564
int __must_check i915_gem_evict_for_vma(struct i915_vma *vma,
					unsigned int flags);
3565
int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3566

3567
/* belongs in i915_gem_gtt.h */
3568
static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3569
{
3570
	wmb();
3571
	if (INTEL_GEN(dev_priv) < 6)
3572 3573
		intel_gtt_chipset_flush();
}
3574

3575
/* i915_gem_stolen.c */
3576 3577 3578
int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
				struct drm_mm_node *node, u64 size,
				unsigned alignment);
3579 3580 3581 3582
int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
					 struct drm_mm_node *node, u64 size,
					 unsigned alignment, u64 start,
					 u64 end);
3583 3584
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
				 struct drm_mm_node *node);
3585
int i915_gem_init_stolen(struct drm_i915_private *dev_priv);
3586
void i915_gem_cleanup_stolen(struct drm_device *dev);
3587
struct drm_i915_gem_object *
3588
i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, u32 size);
3589
struct drm_i915_gem_object *
3590
i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv,
3591 3592 3593
					       u32 stolen_offset,
					       u32 gtt_offset,
					       u32 size);
3594

3595 3596 3597 3598 3599
/* i915_gem_internal.c */
struct drm_i915_gem_object *
i915_gem_object_create_internal(struct drm_i915_private *dev_priv,
				unsigned int size);

3600 3601
/* i915_gem_shrinker.c */
unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3602
			      unsigned long target,
3603 3604 3605 3606
			      unsigned flags);
#define I915_SHRINK_PURGEABLE 0x1
#define I915_SHRINK_UNBOUND 0x2
#define I915_SHRINK_BOUND 0x4
3607
#define I915_SHRINK_ACTIVE 0x8
3608
#define I915_SHRINK_VMAPS 0x10
3609 3610
unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3611
void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3612 3613


3614
/* i915_gem_tiling.c */
3615
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3616
{
3617
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3618 3619

	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3620
		i915_gem_object_is_tiled(obj);
3621 3622
}

3623
/* i915_debugfs.c */
3624
#ifdef CONFIG_DEBUG_FS
3625 3626
int i915_debugfs_register(struct drm_i915_private *dev_priv);
void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3627
int i915_debugfs_connector_add(struct drm_connector *connector);
3628
void intel_display_crc_init(struct drm_i915_private *dev_priv);
3629
#else
3630 3631
static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {}
3632 3633
static inline int i915_debugfs_connector_add(struct drm_connector *connector)
{ return 0; }
3634
static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3635
#endif
3636 3637

/* i915_gpu_error.c */
3638 3639
#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)

3640 3641
__printf(2, 3)
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3642 3643
int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
			    const struct i915_error_state_file_priv *error);
3644
int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3645
			      struct drm_i915_private *i915,
3646 3647 3648 3649 3650 3651
			      size_t count, loff_t pos);
static inline void i915_error_state_buf_release(
	struct drm_i915_error_state_buf *eb)
{
	kfree(eb->buf);
}
3652 3653
void i915_capture_error_state(struct drm_i915_private *dev_priv,
			      u32 engine_mask,
3654
			      const char *error_msg);
3655 3656 3657
void i915_error_state_get(struct drm_device *dev,
			  struct i915_error_state_file_priv *error_priv);
void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3658
void i915_destroy_error_state(struct drm_i915_private *dev_priv);
3659

3660 3661 3662 3663 3664 3665 3666 3667
#else

static inline void i915_capture_error_state(struct drm_i915_private *dev_priv,
					    u32 engine_mask,
					    const char *error_msg)
{
}

3668
static inline void i915_destroy_error_state(struct drm_i915_private *dev_priv)
3669 3670 3671 3672 3673
{
}

#endif

3674
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3675

3676
/* i915_cmd_parser.c */
3677
int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3678
void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3679 3680 3681 3682 3683 3684 3685
void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
int intel_engine_cmd_parser(struct intel_engine_cs *engine,
			    struct drm_i915_gem_object *batch_obj,
			    struct drm_i915_gem_object *shadow_batch_obj,
			    u32 batch_start_offset,
			    u32 batch_len,
			    bool is_master);
3686

3687 3688 3689
/* i915_perf.c */
extern void i915_perf_init(struct drm_i915_private *dev_priv);
extern void i915_perf_fini(struct drm_i915_private *dev_priv);
3690 3691
extern void i915_perf_register(struct drm_i915_private *dev_priv);
extern void i915_perf_unregister(struct drm_i915_private *dev_priv);
3692

3693
/* i915_suspend.c */
3694 3695
extern int i915_save_state(struct drm_i915_private *dev_priv);
extern int i915_restore_state(struct drm_i915_private *dev_priv);
3696

B
Ben Widawsky 已提交
3697
/* i915_sysfs.c */
D
David Weinehall 已提交
3698 3699
void i915_setup_sysfs(struct drm_i915_private *dev_priv);
void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
B
Ben Widawsky 已提交
3700

3701
/* intel_i2c.c */
3702 3703
extern int intel_setup_gmbus(struct drm_i915_private *dev_priv);
extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv);
3704 3705
extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
				     unsigned int pin);
3706

3707 3708
extern struct i2c_adapter *
intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
C
Chris Wilson 已提交
3709 3710
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3711
static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3712 3713 3714
{
	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
}
3715
extern void intel_i2c_reset(struct drm_i915_private *dev_priv);
3716

3717
/* intel_bios.c */
3718
int intel_bios_init(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3719
bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3720
bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3721
bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3722
bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3723
bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3724
bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3725
bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3726 3727
bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
				     enum port port);
3728 3729 3730
bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv,
				enum port port);

3731

3732
/* intel_opregion.c */
3733
#ifdef CONFIG_ACPI
3734
extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3735 3736
extern void intel_opregion_register(struct drm_i915_private *dev_priv);
extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3737
extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3738 3739
extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
					 bool enable);
3740
extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3741
					 pci_power_t state);
3742
extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3743
#else
3744
static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3745 3746
static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3747 3748 3749
static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
{
}
3750 3751 3752 3753 3754
static inline int
intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
{
	return 0;
}
3755
static inline int
3756
intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3757 3758 3759
{
	return 0;
}
3760
static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3761 3762 3763
{
	return -ENODEV;
}
3764
#endif
3765

J
Jesse Barnes 已提交
3766 3767 3768 3769 3770 3771 3772 3773 3774
/* intel_acpi.c */
#ifdef CONFIG_ACPI
extern void intel_register_dsm_handler(void);
extern void intel_unregister_dsm_handler(void);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */

3775 3776 3777 3778 3779 3780 3781
/* intel_device_info.c */
static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private *dev_priv)
{
	return (struct intel_device_info *)&dev_priv->info;
}

3782
const char *intel_platform_name(enum intel_platform platform);
3783 3784 3785
void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
void intel_device_info_dump(struct drm_i915_private *dev_priv);

J
Jesse Barnes 已提交
3786
/* modesetting */
3787
extern void intel_modeset_init_hw(struct drm_device *dev);
3788
extern int intel_modeset_init(struct drm_device *dev);
3789
extern void intel_modeset_gem_init(struct drm_device *dev);
J
Jesse Barnes 已提交
3790
extern void intel_modeset_cleanup(struct drm_device *dev);
3791
extern int intel_connector_register(struct drm_connector *);
3792
extern void intel_connector_unregister(struct drm_connector *);
3793 3794
extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv,
				       bool state);
3795
extern void intel_display_resume(struct drm_device *dev);
3796 3797
extern void i915_redisable_vga(struct drm_i915_private *dev_priv);
extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv);
3798
extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
3799
extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);
3800
extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3801
extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3802
				  bool enable);
3803

B
Ben Widawsky 已提交
3804 3805
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file);
3806

3807
/* overlay */
3808 3809
extern struct intel_overlay_error_state *
intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3810 3811
extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
					    struct intel_overlay_error_state *error);
3812

3813 3814
extern struct intel_display_error_state *
intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3815
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3816
					    struct drm_i915_private *dev_priv,
3817
					    struct intel_display_error_state *error);
3818

3819 3820
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3821 3822
int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
		      u32 reply_mask, u32 reply, int timeout_base_ms);
3823 3824

/* intel_sideband.c */
3825 3826
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3827
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3828 3829
u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3830 3831 3832 3833
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3834 3835
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3836 3837
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3838 3839 3840 3841
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		   enum intel_sbi_destination destination);
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		     enum intel_sbi_destination destination);
3842 3843
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3844

3845
/* intel_dpio_phy.c */
3846
void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
3847
			     enum dpio_phy *phy, enum dpio_channel *ch);
3848 3849 3850
void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
				  enum port port, u32 margin, u32 scale,
				  u32 enable, u32 deemphasis);
3851 3852 3853 3854 3855 3856 3857 3858 3859 3860 3861 3862
void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
			    enum dpio_phy phy);
bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
			      enum dpio_phy phy);
uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
					     uint8_t lane_count);
void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
				     uint8_t lane_lat_optim_mask);
uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);

3863 3864 3865
void chv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 deemph_reg_value, u32 margin_reg_value,
			      bool uniq_trans_scale);
3866 3867
void chv_data_lane_soft_reset(struct intel_encoder *encoder,
			      bool reset);
3868
void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3869 3870
void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3871
void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3872

3873 3874 3875
void vlv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 demph_reg_value, u32 preemph_reg_value,
			      u32 uniqtranscale_reg_value, u32 tx3_demph);
3876
void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3877
void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3878
void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3879

3880 3881
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3882

3883 3884 3885 3886 3887 3888 3889 3890 3891 3892 3893 3894 3895
#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

#define I915_READ16(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
#define I915_WRITE16(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
#define I915_READ16_NOTRACE(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
#define I915_WRITE16_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)

#define I915_READ(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
#define I915_WRITE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
#define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
#define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)

3896 3897 3898 3899
/* Be very careful with read/write 64-bit values. On 32-bit machines, they
 * will be implemented using 2 32-bit writes in an arbitrary order with
 * an arbitrary delay between them. This can cause the hardware to
 * act upon the intermediate value, possibly leading to corruption and
3900 3901 3902 3903 3904 3905 3906 3907 3908
 * machine death. For this reason we do not support I915_WRITE64, or
 * dev_priv->uncore.funcs.mmio_writeq.
 *
 * When reading a 64-bit value as two 32-bit values, the delay may cause
 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
 * occasionally a 64-bit register does not actualy support a full readq
 * and must be read using two 32-bit reads.
 *
 * You have been warned.
3909
 */
3910
#define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3911

3912
#define I915_READ64_2x32(lower_reg, upper_reg) ({			\
3913 3914
	u32 upper, lower, old_upper, loop = 0;				\
	upper = I915_READ(upper_reg);					\
3915
	do {								\
3916
		old_upper = upper;					\
3917
		lower = I915_READ(lower_reg);				\
3918 3919
		upper = I915_READ(upper_reg);				\
	} while (upper != old_upper && loop++ < 2);			\
3920
	(u64)upper << 32 | lower; })
3921

3922 3923 3924
#define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)

3925 3926
#define __raw_read(x, s) \
static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3927
					     i915_reg_t reg) \
3928
{ \
3929
	return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3930 3931 3932 3933
}

#define __raw_write(x, s) \
static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3934
				       i915_reg_t reg, uint##x##_t val) \
3935
{ \
3936
	write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3937 3938 3939 3940 3941 3942 3943 3944 3945 3946 3947 3948 3949 3950
}
__raw_read(8, b)
__raw_read(16, w)
__raw_read(32, l)
__raw_read(64, q)

__raw_write(8, b)
__raw_write(16, w)
__raw_write(32, l)
__raw_write(64, q)

#undef __raw_read
#undef __raw_write

3951
/* These are untraced mmio-accessors that are only valid to be used inside
3952
 * critical sections, such as inside IRQ handlers, where forcewake is explicitly
3953
 * controlled.
3954
 *
3955
 * Think twice, and think again, before using these.
3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975
 *
 * As an example, these accessors can possibly be used between:
 *
 * spin_lock_irq(&dev_priv->uncore.lock);
 * intel_uncore_forcewake_get__locked();
 *
 * and
 *
 * intel_uncore_forcewake_put__locked();
 * spin_unlock_irq(&dev_priv->uncore.lock);
 *
 *
 * Note: some registers may not need forcewake held, so
 * intel_uncore_forcewake_{get,put} can be omitted, see
 * intel_uncore_forcewake_for_reg().
 *
 * Certain architectures will die if the same cacheline is concurrently accessed
 * by different clients (e.g. on Ivybridge). Access to registers should
 * therefore generally be serialised, by either the dev_priv->uncore.lock or
 * a more localised lock guarding all access to that bank of registers.
3976
 */
3977 3978
#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3979
#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3980 3981
#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)

3982 3983 3984 3985
/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
#define INTEL_BROADCAST_RGB_FULL 1
#define INTEL_BROADCAST_RGB_LIMITED 2
3986

3987
static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv)
3988
{
3989
	if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3990
		return VLV_VGACNTRL;
3991
	else if (INTEL_GEN(dev_priv) >= 5)
3992
		return CPU_VGACNTRL;
3993 3994 3995 3996
	else
		return VGACNTRL;
}

3997 3998 3999 4000 4001 4002 4003
static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
{
	unsigned long j = msecs_to_jiffies(m);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

4004 4005 4006 4007 4008
static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
{
        return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
}

4009 4010 4011 4012 4013 4014 4015 4016
static inline unsigned long
timespec_to_jiffies_timeout(const struct timespec *value)
{
	unsigned long j = timespec_to_jiffies(value);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

4017 4018 4019 4020 4021 4022 4023 4024 4025
/*
 * If you need to wait X milliseconds between events A and B, but event B
 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
 * when event A happened, then just before event B you call this function and
 * pass the timestamp as the first argument, and X as the second argument.
 */
static inline void
wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
{
4026
	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
4027 4028 4029 4030 4031 4032 4033 4034 4035 4036

	/*
	 * Don't re-read the value of "jiffies" every time since it may change
	 * behind our back and break the math.
	 */
	tmp_jiffies = jiffies;
	target_jiffies = timestamp_jiffies +
			 msecs_to_jiffies_timeout(to_wait_ms);

	if (time_after(target_jiffies, tmp_jiffies)) {
4037 4038 4039 4040
		remaining_jiffies = target_jiffies - tmp_jiffies;
		while (remaining_jiffies)
			remaining_jiffies =
			    schedule_timeout_uninterruptible(remaining_jiffies);
4041 4042
	}
}
4043 4044 4045

static inline bool
__i915_request_irq_complete(struct drm_i915_gem_request *req)
4046
{
4047 4048
	struct intel_engine_cs *engine = req->engine;

4049 4050 4051
	/* Before we do the heavier coherent read of the seqno,
	 * check the value (hopefully) in the CPU cacheline.
	 */
4052
	if (__i915_gem_request_completed(req))
4053 4054
		return true;

4055 4056 4057 4058 4059 4060 4061 4062 4063 4064 4065
	/* Ensure our read of the seqno is coherent so that we
	 * do not "miss an interrupt" (i.e. if this is the last
	 * request and the seqno write from the GPU is not visible
	 * by the time the interrupt fires, we will see that the
	 * request is incomplete and go back to sleep awaiting
	 * another interrupt that will never come.)
	 *
	 * Strictly, we only need to do this once after an interrupt,
	 * but it is easier and safer to do it every time the waiter
	 * is woken.
	 */
4066
	if (engine->irq_seqno_barrier &&
4067
	    rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current &&
4068
	    cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) {
4069 4070
		struct task_struct *tsk;

4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081 4082
		/* The ordering of irq_posted versus applying the barrier
		 * is crucial. The clearing of the current irq_posted must
		 * be visible before we perform the barrier operation,
		 * such that if a subsequent interrupt arrives, irq_posted
		 * is reasserted and our task rewoken (which causes us to
		 * do another __i915_request_irq_complete() immediately
		 * and reapply the barrier). Conversely, if the clear
		 * occurs after the barrier, then an interrupt that arrived
		 * whilst we waited on the barrier would not trigger a
		 * barrier on the next pass, and the read may not see the
		 * seqno update.
		 */
4083
		engine->irq_seqno_barrier(engine);
4084 4085 4086 4087 4088 4089 4090 4091

		/* If we consume the irq, but we are no longer the bottom-half,
		 * the real bottom-half may not have serialised their own
		 * seqno check with the irq-barrier (i.e. may have inspected
		 * the seqno before we believe it coherent since they see
		 * irq_posted == false but we are still running).
		 */
		rcu_read_lock();
4092
		tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh);
4093 4094 4095 4096 4097 4098 4099 4100 4101 4102
		if (tsk && tsk != current)
			/* Note that if the bottom-half is changed as we
			 * are sending the wake-up, the new bottom-half will
			 * be woken by whomever made the change. We only have
			 * to worry about when we steal the irq-posted for
			 * ourself.
			 */
			wake_up_process(tsk);
		rcu_read_unlock();

4103
		if (__i915_gem_request_completed(req))
4104 4105
			return true;
	}
4106 4107 4108 4109

	return false;
}

4110 4111 4112
void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);

4113 4114 4115 4116 4117
/* i915_mm.c */
int remap_io_mapping(struct vm_area_struct *vma,
		     unsigned long addr, unsigned long pfn, unsigned long size,
		     struct io_mapping *iomap);

4118 4119 4120 4121 4122
#define ptr_mask_bits(ptr) ({						\
	unsigned long __v = (unsigned long)(ptr);			\
	(typeof(ptr))(__v & PAGE_MASK);					\
})

4123 4124 4125 4126 4127 4128 4129 4130 4131
#define ptr_unpack_bits(ptr, bits) ({					\
	unsigned long __v = (unsigned long)(ptr);			\
	(bits) = __v & ~PAGE_MASK;					\
	(typeof(ptr))(__v & PAGE_MASK);					\
})

#define ptr_pack_bits(ptr, bits)					\
	((typeof(ptr))((unsigned long)(ptr) | (bits)))

4132 4133 4134 4135 4136 4137
#define fetch_and_zero(ptr) ({						\
	typeof(*ptr) __T = *(ptr);					\
	*(ptr) = (typeof(*ptr))0;					\
	__T;								\
})

L
Linus Torvalds 已提交
4138
#endif