intel_lrc.c 65.8 KB
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/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Ben Widawsky <ben@bwidawsk.net>
 *    Michel Thierry <michel.thierry@intel.com>
 *    Thomas Daniel <thomas.daniel@intel.com>
 *    Oscar Mateo <oscar.mateo@intel.com>
 *
 */

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/**
 * DOC: Logical Rings, Logical Ring Contexts and Execlists
 *
 * Motivation:
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 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
 * These expanded contexts enable a number of new abilities, especially
 * "Execlists" (also implemented in this file).
 *
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 * One of the main differences with the legacy HW contexts is that logical
 * ring contexts incorporate many more things to the context's state, like
 * PDPs or ringbuffer control registers:
 *
 * The reason why PDPs are included in the context is straightforward: as
 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
 * instead, the GPU will do it for you on the context switch.
 *
 * But, what about the ringbuffer control registers (head, tail, etc..)?
 * shouldn't we just need a set of those per engine command streamer? This is
 * where the name "Logical Rings" starts to make sense: by virtualizing the
 * rings, the engine cs shifts to a new "ring buffer" with every context
 * switch. When you want to submit a workload to the GPU you: A) choose your
 * context, B) find its appropriate virtualized ring, C) write commands to it
 * and then, finally, D) tell the GPU to switch to that context.
 *
 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
 * to a contexts is via a context execution list, ergo "Execlists".
 *
 * LRC implementation:
 * Regarding the creation of contexts, we have:
 *
 * - One global default context.
 * - One local default context for each opened fd.
 * - One local extra context for each context create ioctl call.
 *
 * Now that ringbuffers belong per-context (and not per-engine, like before)
 * and that contexts are uniquely tied to a given engine (and not reusable,
 * like before) we need:
 *
 * - One ringbuffer per-engine inside each context.
 * - One backing object per-engine inside each context.
 *
 * The global default context starts its life with these new objects fully
 * allocated and populated. The local default context for each opened fd is
 * more complex, because we don't know at creation time which engine is going
 * to use them. To handle this, we have implemented a deferred creation of LR
 * contexts:
 *
 * The local context starts its life as a hollow or blank holder, that only
 * gets populated for a given engine once we receive an execbuffer. If later
 * on we receive another execbuffer ioctl for the same context but a different
 * engine, we allocate/populate a new ringbuffer and context backing object and
 * so on.
 *
 * Finally, regarding local contexts created using the ioctl call: as they are
 * only allowed with the render ring, we can allocate & populate them right
 * away (no need to defer anything, at least for now).
 *
 * Execlists implementation:
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 * Execlists are the new method by which, on gen8+ hardware, workloads are
 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
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 * This method works as follows:
 *
 * When a request is committed, its commands (the BB start and any leading or
 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
 * for the appropriate context. The tail pointer in the hardware context is not
 * updated at this time, but instead, kept by the driver in the ringbuffer
 * structure. A structure representing this request is added to a request queue
 * for the appropriate engine: this structure contains a copy of the context's
 * tail after the request was written to the ring buffer and a pointer to the
 * context itself.
 *
 * If the engine's request queue was empty before the request was added, the
 * queue is processed immediately. Otherwise the queue will be processed during
 * a context switch interrupt. In any case, elements on the queue will get sent
 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
 * globally unique 20-bits submission ID.
 *
 * When execution of a request completes, the GPU updates the context status
 * buffer with a context complete event and generates a context switch interrupt.
 * During the interrupt handling, the driver examines the events in the buffer:
 * for each context complete event, if the announced ID matches that on the head
 * of the request queue, then that request is retired and removed from the queue.
 *
 * After processing, if any requests were retired and the queue is not empty
 * then a new execution list can be submitted. The two requests at the front of
 * the queue are next to be submitted but since a context may not occur twice in
 * an execution list, if subsequent requests have the same ID as the first then
 * the two requests must be combined. This is done simply by discarding requests
 * at the head of the queue until either only one requests is left (in which case
 * we use a NULL second context) or the first two requests have unique IDs.
 *
 * By always executing the first two requests in the queue the driver ensures
 * that the GPU is kept as busy as possible. In the case where a single context
 * completes but a second context is still executing, the request for this second
 * context will be at the head of the queue when we remove the first one. This
 * request will then be resubmitted along with a new request for a different context,
 * which will cause the hardware to continue executing the second request and queue
 * the new request (the GPU detects the condition of a context getting preempted
 * with the same context and optimizes the context switch flow by not doing
 * preemption, but just sampling the new tail pointer).
 *
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 */
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#include <linux/interrupt.h>
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#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"
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#include "intel_mocs.h"
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#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
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#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
#define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)

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#define RING_EXECLIST_QFULL		(1 << 0x2)
#define RING_EXECLIST1_VALID		(1 << 0x3)
#define RING_EXECLIST0_VALID		(1 << 0x4)
#define RING_EXECLIST_ACTIVE_STATUS	(3 << 0xE)
#define RING_EXECLIST1_ACTIVE		(1 << 0x11)
#define RING_EXECLIST0_ACTIVE		(1 << 0x12)

#define GEN8_CTX_STATUS_IDLE_ACTIVE	(1 << 0)
#define GEN8_CTX_STATUS_PREEMPTED	(1 << 1)
#define GEN8_CTX_STATUS_ELEMENT_SWITCH	(1 << 2)
#define GEN8_CTX_STATUS_ACTIVE_IDLE	(1 << 3)
#define GEN8_CTX_STATUS_COMPLETE	(1 << 4)
#define GEN8_CTX_STATUS_LITE_RESTORE	(1 << 15)
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#define CTX_LRI_HEADER_0		0x01
#define CTX_CONTEXT_CONTROL		0x02
#define CTX_RING_HEAD			0x04
#define CTX_RING_TAIL			0x06
#define CTX_RING_BUFFER_START		0x08
#define CTX_RING_BUFFER_CONTROL		0x0a
#define CTX_BB_HEAD_U			0x0c
#define CTX_BB_HEAD_L			0x0e
#define CTX_BB_STATE			0x10
#define CTX_SECOND_BB_HEAD_U		0x12
#define CTX_SECOND_BB_HEAD_L		0x14
#define CTX_SECOND_BB_STATE		0x16
#define CTX_BB_PER_CTX_PTR		0x18
#define CTX_RCS_INDIRECT_CTX		0x1a
#define CTX_RCS_INDIRECT_CTX_OFFSET	0x1c
#define CTX_LRI_HEADER_1		0x21
#define CTX_CTX_TIMESTAMP		0x22
#define CTX_PDP3_UDW			0x24
#define CTX_PDP3_LDW			0x26
#define CTX_PDP2_UDW			0x28
#define CTX_PDP2_LDW			0x2a
#define CTX_PDP1_UDW			0x2c
#define CTX_PDP1_LDW			0x2e
#define CTX_PDP0_UDW			0x30
#define CTX_PDP0_LDW			0x32
#define CTX_LRI_HEADER_2		0x41
#define CTX_R_PWR_CLK_STATE		0x42
#define CTX_GPGPU_CSR_BASE_ADDRESS	0x44

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#define GEN8_CTX_VALID (1<<0)
#define GEN8_CTX_FORCE_PD_RESTORE (1<<1)
#define GEN8_CTX_FORCE_RESTORE (1<<2)
#define GEN8_CTX_L3LLC_COHERENT (1<<5)
#define GEN8_CTX_PRIVILEGE (1<<8)
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#define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
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	(reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
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	(reg_state)[(pos)+1] = (val); \
} while (0)

#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do {		\
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	const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n));	\
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	reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
	reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
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} while (0)
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#define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
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	reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
	reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
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} while (0)
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enum {
	FAULT_AND_HANG = 0,
	FAULT_AND_HALT, /* Debug only */
	FAULT_AND_STREAM,
	FAULT_AND_CONTINUE /* Unsupported */
};
#define GEN8_CTX_ID_SHIFT 32
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#define GEN8_CTX_ID_WIDTH 21
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#define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x17
#define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x26
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/* Typical size of the average request (2 pipecontrols and a MI_BB) */
#define EXECLISTS_REQUEST_SIZE 64 /* bytes */

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static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
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					    struct intel_engine_cs *engine);
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static int intel_lr_context_pin(struct i915_gem_context *ctx,
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				struct intel_engine_cs *engine);
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/**
 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
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 * @dev_priv: i915 device private
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 * @enable_execlists: value of i915.enable_execlists module parameter.
 *
 * Only certain platforms support Execlists (the prerequisites being
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 * support for Logical Ring Contexts and Aliasing PPGTT or better).
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 *
 * Return: 1 if Execlists is supported and has to be enabled.
 */
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int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists)
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{
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	/* On platforms with execlist available, vGPU will only
	 * support execlist mode, no ring buffer mode.
	 */
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	if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv))
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		return 1;

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	if (INTEL_GEN(dev_priv) >= 9)
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		return 1;

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	if (enable_execlists == 0)
		return 0;

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	if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) &&
	    USES_PPGTT(dev_priv) &&
	    i915.use_mmio_flip >= 0)
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		return 1;

	return 0;
}
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static void
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logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
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{
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	struct drm_i915_private *dev_priv = engine->i915;
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	if (IS_GEN8(dev_priv) || IS_GEN9(dev_priv))
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		engine->idle_lite_restore_wa = ~0;
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	engine->disable_lite_restore_wa = (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
					IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) &&
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					(engine->id == VCS || engine->id == VCS2);
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	engine->ctx_desc_template = GEN8_CTX_VALID;
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	if (IS_GEN8(dev_priv))
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		engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT;
	engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE;
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	/* TODO: WaDisableLiteRestore when we start using semaphore
	 * signalling between Command Streamers */
	/* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */

	/* WaEnableForceRestoreInCtxtDescForVCS:skl */
	/* WaEnableForceRestoreInCtxtDescForVCS:bxt */
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	if (engine->disable_lite_restore_wa)
		engine->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
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}

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/**
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 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
 * 					  descriptor for a pinned context
 * @ctx: Context to work on
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 * @engine: Engine the descriptor will be used with
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 *
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 * The context descriptor encodes various attributes of a context,
 * including its GTT address and some flags. Because it's fairly
 * expensive to calculate, we'll just do it once and cache the result,
 * which remains valid until the context is unpinned.
 *
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 * This is what a descriptor looks like, from LSB to MSB::
 *
 *      bits  0-11:    flags, GEN8_CTX_* (cached in ctx_desc_template)
 *      bits 12-31:    LRCA, GTT address of (the HWSP of) this context
 *      bits 32-52:    ctx ID, a globally unique tag
 *      bits 53-54:    mbz, reserved for use by hardware
 *      bits 55-63:    group ID, currently unused and set to 0
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 */
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static void
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intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
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				   struct intel_engine_cs *engine)
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{
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	struct intel_context *ce = &ctx->engine[engine->id];
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	u64 desc;
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	BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH));
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	desc = ctx->desc_template;				/* bits  3-4  */
	desc |= engine->ctx_desc_template;			/* bits  0-11 */
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	desc |= ce->state->node.start + LRC_PPHWSP_PN * PAGE_SIZE;
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								/* bits 12-31 */
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	desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT;		/* bits 32-52 */
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	ce->lrc_desc = desc;
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}

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uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
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				     struct intel_engine_cs *engine)
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{
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	return ctx->engine[engine->id].lrc_desc;
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}
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static void execlists_elsp_write(struct drm_i915_gem_request *rq0,
				 struct drm_i915_gem_request *rq1)
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{
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	struct intel_engine_cs *engine = rq0->engine;
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	struct drm_i915_private *dev_priv = rq0->i915;
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	uint64_t desc[2];
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	if (rq1) {
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		desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->engine);
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		rq1->elsp_submitted++;
	} else {
		desc[1] = 0;
	}
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	desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->engine);
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	rq0->elsp_submitted++;
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	/* You must always write both descriptors in the order below. */
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	I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[1]));
	I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[1]));
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	I915_WRITE_FW(RING_ELSP(engine), upper_32_bits(desc[0]));
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	/* The context is automatically loaded after the following */
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	I915_WRITE_FW(RING_ELSP(engine), lower_32_bits(desc[0]));
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	/* ELSP is a wo register, use another nearby reg for posting */
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	POSTING_READ_FW(RING_EXECLIST_STATUS_LO(engine));
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}

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static void
execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
{
	ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
	ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
	ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
	ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
}

static void execlists_update_context(struct drm_i915_gem_request *rq)
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{
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	struct intel_engine_cs *engine = rq->engine;
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	struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt;
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	uint32_t *reg_state = rq->ctx->engine[engine->id].lrc_reg_state;
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	reg_state[CTX_RING_TAIL+1] = intel_ring_offset(rq->ring, rq->tail);
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	/* True 32b PPGTT with dynamic page allocation: update PDP
	 * registers and point the unallocated PDPs to scratch page.
	 * PML4 is allocated during ppgtt init, so this is not needed
	 * in 48-bit mode.
	 */
	if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev))
		execlists_update_context_pdps(ppgtt, reg_state);
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}

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static void execlists_elsp_submit_contexts(struct drm_i915_gem_request *rq0,
					   struct drm_i915_gem_request *rq1)
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{
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	struct drm_i915_private *dev_priv = rq0->i915;
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	unsigned int fw_domains = rq0->engine->fw_domains;
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	execlists_update_context(rq0);
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	if (rq1)
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		execlists_update_context(rq1);
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	spin_lock_irq(&dev_priv->uncore.lock);
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	intel_uncore_forcewake_get__locked(dev_priv, fw_domains);
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	execlists_elsp_write(rq0, rq1);
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	intel_uncore_forcewake_put__locked(dev_priv, fw_domains);
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	spin_unlock_irq(&dev_priv->uncore.lock);
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}

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static inline void execlists_context_status_change(
		struct drm_i915_gem_request *rq,
		unsigned long status)
{
	/*
	 * Only used when GVT-g is enabled now. When GVT-g is disabled,
	 * The compiler should eliminate this function as dead-code.
	 */
	if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
		return;

	atomic_notifier_call_chain(&rq->ctx->status_notifier, status, rq);
}

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static void execlists_unqueue(struct intel_engine_cs *engine)
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{
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	struct drm_i915_gem_request *req0 = NULL, *req1 = NULL;
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	struct drm_i915_gem_request *cursor, *tmp;
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	assert_spin_locked(&engine->execlist_lock);
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	/*
	 * If irqs are not active generate a warning as batches that finish
	 * without the irqs may get lost and a GPU Hang may occur.
	 */
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	WARN_ON(!intel_irqs_enabled(engine->i915));
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	/* Try to read in pairs */
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	list_for_each_entry_safe(cursor, tmp, &engine->execlist_queue,
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				 execlist_link) {
		if (!req0) {
			req0 = cursor;
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		} else if (req0->ctx == cursor->ctx) {
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			/* Same ctx: ignore first request, as second request
			 * will update tail past first request's workload */
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			cursor->elsp_submitted = req0->elsp_submitted;
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			list_del(&req0->execlist_link);
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			i915_gem_request_put(req0);
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			req0 = cursor;
		} else {
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			if (IS_ENABLED(CONFIG_DRM_I915_GVT)) {
				/*
				 * req0 (after merged) ctx requires single
				 * submission, stop picking
				 */
				if (req0->ctx->execlists_force_single_submission)
					break;
				/*
				 * req0 ctx doesn't require single submission,
				 * but next req ctx requires, stop picking
				 */
				if (cursor->ctx->execlists_force_single_submission)
					break;
			}
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			req1 = cursor;
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			WARN_ON(req1->elsp_submitted);
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			break;
		}
	}

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	if (unlikely(!req0))
		return;

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	execlists_context_status_change(req0, INTEL_CONTEXT_SCHEDULE_IN);

	if (req1)
		execlists_context_status_change(req1,
						INTEL_CONTEXT_SCHEDULE_IN);

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	if (req0->elsp_submitted & engine->idle_lite_restore_wa) {
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		/*
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		 * WaIdleLiteRestore: make sure we never cause a lite restore
		 * with HEAD==TAIL.
		 *
		 * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL as we
		 * resubmit the request. See gen8_emit_request() for where we
		 * prepare the padding after the end of the request.
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		 */
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		req0->tail += 8;
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		req0->tail &= req0->ring->size - 1;
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	}

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	execlists_elsp_submit_contexts(req0, req1);
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}

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static unsigned int
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execlists_check_remove_request(struct intel_engine_cs *engine, u32 ctx_id)
494
{
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	struct drm_i915_gem_request *head_req;
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	assert_spin_locked(&engine->execlist_lock);
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	head_req = list_first_entry_or_null(&engine->execlist_queue,
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					    struct drm_i915_gem_request,
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					    execlist_link);

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	if (WARN_ON(!head_req || (head_req->ctx_hw_id != ctx_id)))
               return 0;
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	WARN(head_req->elsp_submitted == 0, "Never submitted head request\n");

	if (--head_req->elsp_submitted > 0)
		return 0;

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	execlists_context_status_change(head_req, INTEL_CONTEXT_SCHEDULE_OUT);

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	list_del(&head_req->execlist_link);
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	i915_gem_request_put(head_req);
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	return 1;
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}

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static u32
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get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer,
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		   u32 *context_id)
522
{
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	struct drm_i915_private *dev_priv = engine->i915;
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	u32 status;
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	read_pointer %= GEN8_CSB_ENTRIES;

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	status = I915_READ_FW(RING_CONTEXT_STATUS_BUF_LO(engine, read_pointer));
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	if (status & GEN8_CTX_STATUS_IDLE_ACTIVE)
		return 0;
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	*context_id = I915_READ_FW(RING_CONTEXT_STATUS_BUF_HI(engine,
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							      read_pointer));

	return status;
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}

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/*
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 * Check the unread Context Status Buffers and manage the submission of new
 * contexts to the ELSP accordingly.
 */
543
static void intel_lrc_irq_handler(unsigned long data)
544
{
545
	struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
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	struct drm_i915_private *dev_priv = engine->i915;
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	u32 status_pointer;
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	unsigned int read_pointer, write_pointer;
549 550
	u32 csb[GEN8_CSB_ENTRIES][2];
	unsigned int csb_read = 0, i;
551 552
	unsigned int submit_contexts = 0;

553
	intel_uncore_forcewake_get(dev_priv, engine->fw_domains);
554

555
	status_pointer = I915_READ_FW(RING_CONTEXT_STATUS_PTR(engine));
556

557
	read_pointer = engine->next_context_status_buffer;
558
	write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
559
	if (read_pointer > write_pointer)
560
		write_pointer += GEN8_CSB_ENTRIES;
561 562

	while (read_pointer < write_pointer) {
563 564 565 566 567 568
		if (WARN_ON_ONCE(csb_read == GEN8_CSB_ENTRIES))
			break;
		csb[csb_read][0] = get_context_status(engine, ++read_pointer,
						      &csb[csb_read][1]);
		csb_read++;
	}
569

570 571 572 573 574 575 576 577
	engine->next_context_status_buffer = write_pointer % GEN8_CSB_ENTRIES;

	/* Update the read pointer to the old write pointer. Manual ringbuffer
	 * management ftw </sarcasm> */
	I915_WRITE_FW(RING_CONTEXT_STATUS_PTR(engine),
		      _MASKED_FIELD(GEN8_CSB_READ_PTR_MASK,
				    engine->next_context_status_buffer << 8));

578
	intel_uncore_forcewake_put(dev_priv, engine->fw_domains);
579 580 581 582 583 584 585

	spin_lock(&engine->execlist_lock);

	for (i = 0; i < csb_read; i++) {
		if (unlikely(csb[i][0] & GEN8_CTX_STATUS_PREEMPTED)) {
			if (csb[i][0] & GEN8_CTX_STATUS_LITE_RESTORE) {
				if (execlists_check_remove_request(engine, csb[i][1]))
586 587 588 589 590
					WARN(1, "Lite Restored request removed from queue\n");
			} else
				WARN(1, "Preemption without Lite Restore\n");
		}

591
		if (csb[i][0] & (GEN8_CTX_STATUS_ACTIVE_IDLE |
592 593
		    GEN8_CTX_STATUS_ELEMENT_SWITCH))
			submit_contexts +=
594
				execlists_check_remove_request(engine, csb[i][1]);
595 596
	}

597
	if (submit_contexts) {
598
		if (!engine->disable_lite_restore_wa ||
599
		    (csb[i][0] & GEN8_CTX_STATUS_ACTIVE_IDLE))
600
			execlists_unqueue(engine);
601
	}
602

603
	spin_unlock(&engine->execlist_lock);
604 605 606

	if (unlikely(submit_contexts > 2))
		DRM_ERROR("More than two context complete events?\n");
607 608
}

609
static void execlists_submit_request(struct drm_i915_gem_request *request)
610
{
611
	struct intel_engine_cs *engine = request->engine;
612
	struct drm_i915_gem_request *cursor;
613
	int num_elements = 0;
614

615
	spin_lock_bh(&engine->execlist_lock);
616

617
	list_for_each_entry(cursor, &engine->execlist_queue, execlist_link)
618 619 620 621
		if (++num_elements > 2)
			break;

	if (num_elements > 2) {
622
		struct drm_i915_gem_request *tail_req;
623

624
		tail_req = list_last_entry(&engine->execlist_queue,
625
					   struct drm_i915_gem_request,
626 627
					   execlist_link);

628
		if (request->ctx == tail_req->ctx) {
629
			WARN(tail_req->elsp_submitted != 0,
630
				"More than 2 already-submitted reqs queued\n");
631
			list_del(&tail_req->execlist_link);
632
			i915_gem_request_put(tail_req);
633 634 635
		}
	}

636
	i915_gem_request_get(request);
637
	list_add_tail(&request->execlist_link, &engine->execlist_queue);
638
	request->ctx_hw_id = request->ctx->hw_id;
639
	if (num_elements == 0)
640
		execlists_unqueue(engine);
641

642
	spin_unlock_bh(&engine->execlist_lock);
643 644
}

645
int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request)
646
{
647
	struct intel_engine_cs *engine = request->engine;
648
	struct intel_context *ce = &request->ctx->engine[engine->id];
649
	int ret;
650

651 652 653 654
	/* Flush enough space to reduce the likelihood of waiting after
	 * we start building the request - in which case we will just
	 * have to repeat work.
	 */
655
	request->reserved_space += EXECLISTS_REQUEST_SIZE;
656

657
	if (!ce->state) {
658 659 660 661 662
		ret = execlists_context_deferred_alloc(request->ctx, engine);
		if (ret)
			return ret;
	}

663
	request->ring = ce->ring;
664

665 666 667 668 669 670
	if (i915.enable_guc_submission) {
		/*
		 * Check that the GuC has space for the request before
		 * going any further, as the i915_add_request() call
		 * later on mustn't fail ...
		 */
671
		ret = i915_guc_wq_check_space(request);
672 673 674 675
		if (ret)
			return ret;
	}

676 677 678
	ret = intel_lr_context_pin(request->ctx, engine);
	if (ret)
		return ret;
679

680 681 682 683
	ret = intel_ring_begin(request, 0);
	if (ret)
		goto err_unpin;

684
	if (!ce->initialised) {
685 686 687 688
		ret = engine->init_context(request);
		if (ret)
			goto err_unpin;

689
		ce->initialised = true;
690 691 692 693 694 695 696 697 698
	}

	/* Note that after this point, we have committed to using
	 * this request as it is being used to both track the
	 * state of engine initialisation and liveness of the
	 * golden renderstate above. Think twice before you try
	 * to cancel/unwind this request now.
	 */

699
	request->reserved_space -= EXECLISTS_REQUEST_SIZE;
700 701 702
	return 0;

err_unpin:
703
	intel_lr_context_unpin(request->ctx, engine);
704
	return ret;
705 706 707
}

/*
708
 * intel_logical_ring_advance() - advance the tail and prepare for submission
709
 * @request: Request to advance the logical ringbuffer of.
710 711 712 713 714 715
 *
 * The tail is updated in our logical ringbuffer struct, not in the actual context. What
 * really happens during submission is that the context and current tail will be placed
 * on a queue waiting for the ELSP to be ready to accept a new context submission. At that
 * point, the tail *inside* the context is updated and the ELSP written to.
 */
716
static int
717
intel_logical_ring_advance(struct drm_i915_gem_request *request)
718
{
719
	struct intel_ring *ring = request->ring;
720
	struct intel_engine_cs *engine = request->engine;
721

722 723
	intel_ring_advance(ring);
	request->tail = ring->tail;
724

725 726 727 728 729 730
	/*
	 * Here we add two extra NOOPs as padding to avoid
	 * lite restore of a context with HEAD==TAIL.
	 *
	 * Caller must reserve WA_TAIL_DWORDS for us!
	 */
731 732 733
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_advance(ring);
734

735 736 737 738 739 740 741 742
	/* We keep the previous context alive until we retire the following
	 * request. This ensures that any the context object is still pinned
	 * for any residual writes the HW makes into it on the context switch
	 * into the next object following the breadcrumb. Otherwise, we may
	 * retire the context too early.
	 */
	request->previous_context = engine->last_context;
	engine->last_context = request->ctx;
743
	return 0;
744 745
}

746
void intel_execlists_cancel_requests(struct intel_engine_cs *engine)
747
{
748
	struct drm_i915_gem_request *req, *tmp;
749
	LIST_HEAD(cancel_list);
750

751
	WARN_ON(!mutex_is_locked(&engine->i915->drm.struct_mutex));
752

753
	spin_lock_bh(&engine->execlist_lock);
754
	list_replace_init(&engine->execlist_queue, &cancel_list);
755
	spin_unlock_bh(&engine->execlist_lock);
756

757
	list_for_each_entry_safe(req, tmp, &cancel_list, execlist_link) {
758
		list_del(&req->execlist_link);
759
		i915_gem_request_put(req);
760 761 762
	}
}

763
static int intel_lr_context_pin(struct i915_gem_context *ctx,
764
				struct intel_engine_cs *engine)
765
{
766
	struct intel_context *ce = &ctx->engine[engine->id];
767 768
	void *vaddr;
	u32 *lrc_reg_state;
769
	int ret;
770

771
	lockdep_assert_held(&ctx->i915->drm.struct_mutex);
772

773
	if (ce->pin_count++)
774 775
		return 0;

776 777
	ret = i915_vma_pin(ce->state, 0, GEN8_LR_CONTEXT_ALIGN,
			   PIN_OFFSET_BIAS | GUC_WOPCM_TOP | PIN_GLOBAL);
778
	if (ret)
779
		goto err;
780

781
	vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
782 783
	if (IS_ERR(vaddr)) {
		ret = PTR_ERR(vaddr);
784
		goto unpin_vma;
785 786
	}

787 788
	lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;

789
	ret = intel_ring_pin(ce->ring);
790
	if (ret)
791
		goto unpin_map;
792

793
	intel_lr_context_descriptor_update(ctx, engine);
794

795
	lrc_reg_state[CTX_RING_BUFFER_START+1] = ce->ring->vma->node.start;
796
	ce->lrc_reg_state = lrc_reg_state;
797
	ce->state->obj->dirty = true;
798

799
	/* Invalidate GuC TLB. */
800 801
	if (i915.enable_guc_submission) {
		struct drm_i915_private *dev_priv = ctx->i915;
802
		I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE);
803
	}
804

805
	i915_gem_context_get(ctx);
806
	return 0;
807

808
unpin_map:
809 810 811
	i915_gem_object_unpin_map(ce->state->obj);
unpin_vma:
	__i915_vma_unpin(ce->state);
812
err:
813
	ce->pin_count = 0;
814 815 816
	return ret;
}

817
void intel_lr_context_unpin(struct i915_gem_context *ctx,
818
			    struct intel_engine_cs *engine)
819
{
820
	struct intel_context *ce = &ctx->engine[engine->id];
821

822
	lockdep_assert_held(&ctx->i915->drm.struct_mutex);
823
	GEM_BUG_ON(ce->pin_count == 0);
824

825
	if (--ce->pin_count)
826
		return;
827

828
	intel_ring_unpin(ce->ring);
829

830 831
	i915_gem_object_unpin_map(ce->state->obj);
	i915_vma_unpin(ce->state);
832

833
	i915_gem_context_put(ctx);
834 835
}

836
static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
837 838
{
	int ret, i;
839
	struct intel_ring *ring = req->ring;
840
	struct i915_workarounds *w = &req->i915->workarounds;
841

842
	if (w->count == 0)
843 844
		return 0;

845
	ret = req->engine->emit_flush(req, EMIT_BARRIER);
846 847 848
	if (ret)
		return ret;

849
	ret = intel_ring_begin(req, w->count * 2 + 2);
850 851 852
	if (ret)
		return ret;

853
	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count));
854
	for (i = 0; i < w->count; i++) {
855 856
		intel_ring_emit_reg(ring, w->reg[i].addr);
		intel_ring_emit(ring, w->reg[i].value);
857
	}
858
	intel_ring_emit(ring, MI_NOOP);
859

860
	intel_ring_advance(ring);
861

862
	ret = req->engine->emit_flush(req, EMIT_BARRIER);
863 864 865 866 867 868
	if (ret)
		return ret;

	return 0;
}

869
#define wa_ctx_emit(batch, index, cmd)					\
870
	do {								\
871 872
		int __index = (index)++;				\
		if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
873 874
			return -ENOSPC;					\
		}							\
875
		batch[__index] = (cmd);					\
876 877
	} while (0)

878
#define wa_ctx_emit_reg(batch, index, reg) \
879
	wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
880 881 882 883 884 885 886 887 888 889 890 891 892 893 894 895 896

/*
 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
 * but there is a slight complication as this is applied in WA batch where the
 * values are only initialized once so we cannot take register value at the
 * beginning and reuse it further; hence we save its value to memory, upload a
 * constant value with bit21 set and then we restore it back with the saved value.
 * To simplify the WA, a constant value is formed by using the default value
 * of this register. This shouldn't be a problem because we are only modifying
 * it for a short period and this batch in non-premptible. We can ofcourse
 * use additional instructions that read the actual value of the register
 * at that time and set our bit of interest but it makes the WA complicated.
 *
 * This WA is also required for Gen9 so extracting as a function avoids
 * code duplication.
 */
897
static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
898
						uint32_t *batch,
899 900
						uint32_t index)
{
901
	struct drm_i915_private *dev_priv = engine->i915;
902 903
	uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);

904
	/*
905
	 * WaDisableLSQCROPERFforOCL:skl,kbl
906 907 908 909
	 * This WA is implemented in skl_init_clock_gating() but since
	 * this batch updates GEN8_L3SQCREG4 with default value we need to
	 * set this bit here to retain the WA during flush.
	 */
910 911
	if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0) ||
	    IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0))
912 913
		l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS;

914
	wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
915
				   MI_SRM_LRM_GLOBAL_GTT));
916
	wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
917
	wa_ctx_emit(batch, index, engine->scratch->node.start + 256);
918 919 920
	wa_ctx_emit(batch, index, 0);

	wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
921
	wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
922 923 924 925 926 927 928 929 930 931
	wa_ctx_emit(batch, index, l3sqc4_flush);

	wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
	wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL |
				   PIPE_CONTROL_DC_FLUSH_ENABLE));
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);

932
	wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
933
				   MI_SRM_LRM_GLOBAL_GTT));
934
	wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
935
	wa_ctx_emit(batch, index, engine->scratch->node.start + 256);
936
	wa_ctx_emit(batch, index, 0);
937 938 939 940

	return index;
}

941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959
static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx,
				    uint32_t offset,
				    uint32_t start_alignment)
{
	return wa_ctx->offset = ALIGN(offset, start_alignment);
}

static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
			     uint32_t offset,
			     uint32_t size_alignment)
{
	wa_ctx->size = offset - wa_ctx->offset;

	WARN(wa_ctx->size % size_alignment,
	     "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
	     wa_ctx->size, size_alignment);
	return 0;
}

960 961 962 963 964 965
/*
 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
 * initialized at the beginning and shared across all contexts but this field
 * helps us to have multiple batches at different offsets and select them based
 * on a criteria. At the moment this batch always start at the beginning of the page
 * and at this point we don't have multiple wa_ctx batch buffers.
966
 *
967 968
 * The number of WA applied are not known at the beginning; we use this field
 * to return the no of DWORDS written.
969
 *
970 971 972 973
 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
 * so it adds NOOPs as padding to make it cacheline aligned.
 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
 * makes a complete batch buffer.
974
 */
975
static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine,
976
				    struct i915_wa_ctx_bb *wa_ctx,
977
				    uint32_t *batch,
978 979
				    uint32_t *offset)
{
980
	uint32_t scratch_addr;
981 982
	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);

983
	/* WaDisableCtxRestoreArbitration:bdw,chv */
984
	wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
985

986
	/* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
987
	if (IS_BROADWELL(engine->i915)) {
988
		int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index);
989 990 991
		if (rc < 0)
			return rc;
		index = rc;
992 993
	}

994 995
	/* WaClearSlmSpaceAtContextSwitch:bdw,chv */
	/* Actual scratch location is at 128 bytes offset */
996
	scratch_addr = engine->scratch->node.start + 2 * CACHELINE_BYTES;
997

998 999 1000 1001 1002 1003 1004 1005 1006
	wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
	wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
				   PIPE_CONTROL_GLOBAL_GTT_IVB |
				   PIPE_CONTROL_CS_STALL |
				   PIPE_CONTROL_QW_WRITE));
	wa_ctx_emit(batch, index, scratch_addr);
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);
1007

1008 1009
	/* Pad to end of cacheline */
	while (index % CACHELINE_DWORDS)
1010
		wa_ctx_emit(batch, index, MI_NOOP);
1011 1012 1013 1014 1015 1016 1017 1018 1019 1020

	/*
	 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
	 * execution depends on the length specified in terms of cache lines
	 * in the register CTX_RCS_INDIRECT_CTX
	 */

	return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
}

1021 1022 1023
/*
 *  This batch is started immediately after indirect_ctx batch. Since we ensure
 *  that indirect_ctx ends on a cacheline this batch is aligned automatically.
1024
 *
1025
 *  The number of DWORDS written are returned using this field.
1026 1027 1028 1029
 *
 *  This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
 *  to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
 */
1030
static int gen8_init_perctx_bb(struct intel_engine_cs *engine,
1031
			       struct i915_wa_ctx_bb *wa_ctx,
1032
			       uint32_t *batch,
1033 1034 1035 1036
			       uint32_t *offset)
{
	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);

1037
	/* WaDisableCtxRestoreArbitration:bdw,chv */
1038
	wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1039

1040
	wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1041 1042 1043 1044

	return wa_ctx_end(wa_ctx, *offset = index, 1);
}

1045
static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
1046
				    struct i915_wa_ctx_bb *wa_ctx,
1047
				    uint32_t *batch,
1048 1049
				    uint32_t *offset)
{
1050
	int ret;
1051
	struct drm_i915_private *dev_priv = engine->i915;
1052 1053
	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);

1054
	/* WaDisableCtxRestoreArbitration:skl,bxt */
1055 1056
	if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) ||
	    IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
1057
		wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1058

1059
	/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */
1060
	ret = gen8_emit_flush_coherentl3_wa(engine, batch, index);
1061 1062 1063 1064
	if (ret < 0)
		return ret;
	index = ret;

1065 1066 1067 1068 1069 1070 1071
	/* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl */
	wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
	wa_ctx_emit_reg(batch, index, COMMON_SLICE_CHICKEN2);
	wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(
			    GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE));
	wa_ctx_emit(batch, index, MI_NOOP);

1072 1073
	/* WaClearSlmSpaceAtContextSwitch:kbl */
	/* Actual scratch location is at 128 bytes offset */
1074
	if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0)) {
1075 1076
		u32 scratch_addr =
			engine->scratch->node.start + 2 * CACHELINE_BYTES;
1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087

		wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
		wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
					   PIPE_CONTROL_GLOBAL_GTT_IVB |
					   PIPE_CONTROL_CS_STALL |
					   PIPE_CONTROL_QW_WRITE));
		wa_ctx_emit(batch, index, scratch_addr);
		wa_ctx_emit(batch, index, 0);
		wa_ctx_emit(batch, index, 0);
		wa_ctx_emit(batch, index, 0);
	}
1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112

	/* WaMediaPoolStateCmdInWABB:bxt */
	if (HAS_POOLED_EU(engine->i915)) {
		/*
		 * EU pool configuration is setup along with golden context
		 * during context initialization. This value depends on
		 * device type (2x6 or 3x6) and needs to be updated based
		 * on which subslice is disabled especially for 2x6
		 * devices, however it is safe to load default
		 * configuration of 3x6 device instead of masking off
		 * corresponding bits because HW ignores bits of a disabled
		 * subslice and drops down to appropriate config. Please
		 * see render_state_setup() in i915_gem_render_state.c for
		 * possible configurations, to avoid duplication they are
		 * not shown here again.
		 */
		u32 eu_pool_config = 0x00777000;
		wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_STATE);
		wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_ENABLE);
		wa_ctx_emit(batch, index, eu_pool_config);
		wa_ctx_emit(batch, index, 0);
		wa_ctx_emit(batch, index, 0);
		wa_ctx_emit(batch, index, 0);
	}

1113 1114 1115 1116 1117 1118 1119
	/* Pad to end of cacheline */
	while (index % CACHELINE_DWORDS)
		wa_ctx_emit(batch, index, MI_NOOP);

	return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
}

1120
static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
1121
			       struct i915_wa_ctx_bb *wa_ctx,
1122
			       uint32_t *batch,
1123 1124 1125 1126
			       uint32_t *offset)
{
	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);

1127
	/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
1128 1129
	if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_B0) ||
	    IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
1130
		wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
1131
		wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
1132 1133 1134 1135 1136
		wa_ctx_emit(batch, index,
			    _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING));
		wa_ctx_emit(batch, index, MI_NOOP);
	}

1137
	/* WaClearTdlStateAckDirtyBits:bxt */
1138
	if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_B0)) {
1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155
		wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4));

		wa_ctx_emit_reg(batch, index, GEN8_STATE_ACK);
		wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));

		wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE1);
		wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));

		wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE2);
		wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS));

		wa_ctx_emit_reg(batch, index, GEN7_ROW_CHICKEN2);
		/* dummy write to CS, mask bits are 0 to ensure the register is not modified */
		wa_ctx_emit(batch, index, 0x0);
		wa_ctx_emit(batch, index, MI_NOOP);
	}

1156
	/* WaDisableCtxRestoreArbitration:skl,bxt */
1157 1158
	if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_D0) ||
	    IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
1159 1160
		wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);

1161 1162 1163 1164 1165
	wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);

	return wa_ctx_end(wa_ctx, *offset = index, 1);
}

1166
static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size)
1167
{
1168 1169 1170
	struct drm_i915_gem_object *obj;
	struct i915_vma *vma;
	int err;
1171

1172 1173 1174
	obj = i915_gem_object_create(&engine->i915->drm, PAGE_ALIGN(size));
	if (IS_ERR(obj))
		return PTR_ERR(obj);
1175

1176 1177 1178 1179
	vma = i915_vma_create(obj, &engine->i915->ggtt.base, NULL);
	if (IS_ERR(vma)) {
		err = PTR_ERR(vma);
		goto err;
1180 1181
	}

1182 1183 1184 1185 1186
	err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH);
	if (err)
		goto err;

	engine->wa_ctx.vma = vma;
1187
	return 0;
1188 1189 1190 1191

err:
	i915_gem_object_put(obj);
	return err;
1192 1193
}

1194
static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *engine)
1195
{
1196
	i915_vma_unpin_and_release(&engine->wa_ctx.vma);
1197 1198
}

1199
static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1200
{
1201
	struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1202 1203 1204
	uint32_t *batch;
	uint32_t offset;
	struct page *page;
1205
	int ret;
1206

1207
	WARN_ON(engine->id != RCS);
1208

1209
	/* update this when WA for higher Gen are added */
1210
	if (INTEL_GEN(engine->i915) > 9) {
1211
		DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1212
			  INTEL_GEN(engine->i915));
1213
		return 0;
1214
	}
1215

1216
	/* some WA perform writes to scratch page, ensure it is valid */
1217
	if (!engine->scratch) {
1218
		DRM_ERROR("scratch page not allocated for %s\n", engine->name);
1219 1220 1221
		return -EINVAL;
	}

1222
	ret = lrc_setup_wa_ctx_obj(engine, PAGE_SIZE);
1223 1224 1225 1226 1227
	if (ret) {
		DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
		return ret;
	}

1228
	page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0);
1229 1230 1231
	batch = kmap_atomic(page);
	offset = 0;

1232
	if (IS_GEN8(engine->i915)) {
1233
		ret = gen8_init_indirectctx_bb(engine,
1234 1235 1236 1237 1238 1239
					       &wa_ctx->indirect_ctx,
					       batch,
					       &offset);
		if (ret)
			goto out;

1240
		ret = gen8_init_perctx_bb(engine,
1241 1242 1243 1244 1245
					  &wa_ctx->per_ctx,
					  batch,
					  &offset);
		if (ret)
			goto out;
1246
	} else if (IS_GEN9(engine->i915)) {
1247
		ret = gen9_init_indirectctx_bb(engine,
1248 1249 1250 1251 1252 1253
					       &wa_ctx->indirect_ctx,
					       batch,
					       &offset);
		if (ret)
			goto out;

1254
		ret = gen9_init_perctx_bb(engine,
1255 1256 1257 1258 1259
					  &wa_ctx->per_ctx,
					  batch,
					  &offset);
		if (ret)
			goto out;
1260 1261 1262 1263 1264
	}

out:
	kunmap_atomic(batch);
	if (ret)
1265
		lrc_destroy_wa_ctx_obj(engine);
1266 1267 1268 1269

	return ret;
}

1270 1271
static void lrc_init_hws(struct intel_engine_cs *engine)
{
1272
	struct drm_i915_private *dev_priv = engine->i915;
1273 1274

	I915_WRITE(RING_HWS_PGA(engine->mmio_base),
1275
		   engine->status_page.ggtt_offset);
1276 1277 1278
	POSTING_READ(RING_HWS_PGA(engine->mmio_base));
}

1279
static int gen8_init_common_ring(struct intel_engine_cs *engine)
1280
{
1281
	struct drm_i915_private *dev_priv = engine->i915;
1282
	unsigned int next_context_status_buffer_hw;
1283

1284
	lrc_init_hws(engine);
1285

1286 1287 1288
	I915_WRITE_IMR(engine,
		       ~(engine->irq_enable_mask | engine->irq_keep_mask));
	I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
1289

1290
	I915_WRITE(RING_MODE_GEN7(engine),
1291 1292
		   _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
		   _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1293
	POSTING_READ(RING_MODE_GEN7(engine));
1294 1295 1296 1297 1298 1299 1300 1301 1302 1303

	/*
	 * Instead of resetting the Context Status Buffer (CSB) read pointer to
	 * zero, we need to read the write pointer from hardware and use its
	 * value because "this register is power context save restored".
	 * Effectively, these states have been observed:
	 *
	 *      | Suspend-to-idle (freeze) | Suspend-to-RAM (mem) |
	 * BDW  | CSB regs not reset       | CSB regs reset       |
	 * CHT  | CSB regs not reset       | CSB regs not reset   |
1304 1305
	 * SKL  |         ?                |         ?            |
	 * BXT  |         ?                |         ?            |
1306
	 */
1307
	next_context_status_buffer_hw =
1308
		GEN8_CSB_WRITE_PTR(I915_READ(RING_CONTEXT_STATUS_PTR(engine)));
1309 1310 1311 1312 1313 1314 1315 1316 1317

	/*
	 * When the CSB registers are reset (also after power-up / gpu reset),
	 * CSB write pointer is set to all 1's, which is not valid, use '5' in
	 * this special case, so the first element read is CSB[0].
	 */
	if (next_context_status_buffer_hw == GEN8_CSB_PTR_MASK)
		next_context_status_buffer_hw = (GEN8_CSB_ENTRIES - 1);

1318 1319
	engine->next_context_status_buffer = next_context_status_buffer_hw;
	DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
1320

1321
	intel_engine_init_hangcheck(engine);
1322

1323
	return intel_mocs_init_engine(engine);
1324 1325
}

1326
static int gen8_init_render_ring(struct intel_engine_cs *engine)
1327
{
1328
	struct drm_i915_private *dev_priv = engine->i915;
1329 1330
	int ret;

1331
	ret = gen8_init_common_ring(engine);
1332 1333 1334 1335 1336 1337 1338 1339 1340 1341 1342 1343 1344
	if (ret)
		return ret;

	/* We need to disable the AsyncFlip performance optimisations in order
	 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
	 * programmed to '1' on all products.
	 *
	 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
	 */
	I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));

	I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));

1345
	return init_workarounds_ring(engine);
1346 1347
}

1348
static int gen9_init_render_ring(struct intel_engine_cs *engine)
1349 1350 1351
{
	int ret;

1352
	ret = gen8_init_common_ring(engine);
1353 1354 1355
	if (ret)
		return ret;

1356
	return init_workarounds_ring(engine);
1357 1358
}

1359 1360 1361
static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
{
	struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
1362
	struct intel_ring *ring = req->ring;
1363
	struct intel_engine_cs *engine = req->engine;
1364 1365 1366
	const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
	int i, ret;

1367
	ret = intel_ring_begin(req, num_lri_cmds * 2 + 2);
1368 1369 1370
	if (ret)
		return ret;

1371
	intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_lri_cmds));
1372 1373 1374
	for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
		const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);

1375 1376 1377 1378
		intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(engine, i));
		intel_ring_emit(ring, upper_32_bits(pd_daddr));
		intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(engine, i));
		intel_ring_emit(ring, lower_32_bits(pd_daddr));
1379 1380
	}

1381 1382
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_advance(ring);
1383 1384 1385 1386

	return 0;
}

1387
static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1388 1389
			      u64 offset, u32 len,
			      unsigned int dispatch_flags)
1390
{
1391
	struct intel_ring *ring = req->ring;
1392
	bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1393 1394
	int ret;

1395 1396 1397 1398
	/* Don't rely in hw updating PDPs, specially in lite-restore.
	 * Ideally, we should set Force PD Restore in ctx descriptor,
	 * but we can't. Force Restore would be a second option, but
	 * it is unsafe in case of lite-restore (because the ctx is
1399 1400
	 * not idle). PML4 is allocated during ppgtt init so this is
	 * not needed in 48-bit.*/
1401
	if (req->ctx->ppgtt &&
1402
	    (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) {
1403
		if (!USES_FULL_48BIT_PPGTT(req->i915) &&
1404
		    !intel_vgpu_active(req->i915)) {
1405 1406 1407 1408
			ret = intel_logical_ring_emit_pdps(req);
			if (ret)
				return ret;
		}
1409

1410
		req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine);
1411 1412
	}

1413
	ret = intel_ring_begin(req, 4);
1414 1415 1416 1417
	if (ret)
		return ret;

	/* FIXME(BDW): Address space and security selectors. */
1418 1419 1420 1421 1422 1423 1424 1425
	intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 |
			(ppgtt<<8) |
			(dispatch_flags & I915_DISPATCH_RS ?
			 MI_BATCH_RESOURCE_STREAMER : 0));
	intel_ring_emit(ring, lower_32_bits(offset));
	intel_ring_emit(ring, upper_32_bits(offset));
	intel_ring_emit(ring, MI_NOOP);
	intel_ring_advance(ring);
1426 1427 1428 1429

	return 0;
}

1430
static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
1431
{
1432
	struct drm_i915_private *dev_priv = engine->i915;
1433 1434 1435
	I915_WRITE_IMR(engine,
		       ~(engine->irq_enable_mask | engine->irq_keep_mask));
	POSTING_READ_FW(RING_IMR(engine->mmio_base));
1436 1437
}

1438
static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
1439
{
1440
	struct drm_i915_private *dev_priv = engine->i915;
1441
	I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1442 1443
}

1444
static int gen8_emit_flush(struct drm_i915_gem_request *request, u32 mode)
1445
{
1446 1447
	struct intel_ring *ring = request->ring;
	u32 cmd;
1448 1449
	int ret;

1450
	ret = intel_ring_begin(request, 4);
1451 1452 1453 1454 1455
	if (ret)
		return ret;

	cmd = MI_FLUSH_DW + 1;

1456 1457 1458 1459 1460 1461 1462
	/* We always require a command barrier so that subsequent
	 * commands, such as breadcrumb interrupts, are strictly ordered
	 * wrt the contents of the write cache being flushed to memory
	 * (and thus being coherent from the CPU).
	 */
	cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;

1463
	if (mode & EMIT_INVALIDATE) {
1464
		cmd |= MI_INVALIDATE_TLB;
1465
		if (request->engine->id == VCS)
1466
			cmd |= MI_INVALIDATE_BSD;
1467 1468
	}

1469 1470 1471 1472 1473 1474 1475
	intel_ring_emit(ring, cmd);
	intel_ring_emit(ring,
			I915_GEM_HWS_SCRATCH_ADDR |
			MI_FLUSH_DW_USE_GTT);
	intel_ring_emit(ring, 0); /* upper addr */
	intel_ring_emit(ring, 0); /* value */
	intel_ring_advance(ring);
1476 1477 1478 1479

	return 0;
}

1480
static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1481
				  u32 mode)
1482
{
1483
	struct intel_ring *ring = request->ring;
1484
	struct intel_engine_cs *engine = request->engine;
1485
	u32 scratch_addr = engine->scratch->node.start + 2 * CACHELINE_BYTES;
1486
	bool vf_flush_wa = false, dc_flush_wa = false;
1487 1488
	u32 flags = 0;
	int ret;
1489
	int len;
1490 1491 1492

	flags |= PIPE_CONTROL_CS_STALL;

1493
	if (mode & EMIT_FLUSH) {
1494 1495
		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1496
		flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
1497
		flags |= PIPE_CONTROL_FLUSH_ENABLE;
1498 1499
	}

1500
	if (mode & EMIT_INVALIDATE) {
1501 1502 1503 1504 1505 1506 1507 1508 1509
		flags |= PIPE_CONTROL_TLB_INVALIDATE;
		flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_QW_WRITE;
		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;

1510 1511 1512 1513
		/*
		 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
		 * pipe control.
		 */
1514
		if (IS_GEN9(request->i915))
1515
			vf_flush_wa = true;
1516 1517 1518 1519

		/* WaForGAMHang:kbl */
		if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
			dc_flush_wa = true;
1520
	}
1521

1522 1523 1524 1525 1526 1527 1528 1529 1530
	len = 6;

	if (vf_flush_wa)
		len += 6;

	if (dc_flush_wa)
		len += 12;

	ret = intel_ring_begin(request, len);
1531 1532 1533
	if (ret)
		return ret;

1534
	if (vf_flush_wa) {
1535 1536 1537 1538 1539 1540
		intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
		intel_ring_emit(ring, 0);
		intel_ring_emit(ring, 0);
		intel_ring_emit(ring, 0);
		intel_ring_emit(ring, 0);
		intel_ring_emit(ring, 0);
1541 1542
	}

1543
	if (dc_flush_wa) {
1544 1545 1546 1547 1548 1549
		intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
		intel_ring_emit(ring, PIPE_CONTROL_DC_FLUSH_ENABLE);
		intel_ring_emit(ring, 0);
		intel_ring_emit(ring, 0);
		intel_ring_emit(ring, 0);
		intel_ring_emit(ring, 0);
1550 1551
	}

1552 1553 1554 1555 1556 1557
	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
	intel_ring_emit(ring, flags);
	intel_ring_emit(ring, scratch_addr);
	intel_ring_emit(ring, 0);
	intel_ring_emit(ring, 0);
	intel_ring_emit(ring, 0);
1558 1559

	if (dc_flush_wa) {
1560 1561 1562 1563 1564 1565
		intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
		intel_ring_emit(ring, PIPE_CONTROL_CS_STALL);
		intel_ring_emit(ring, 0);
		intel_ring_emit(ring, 0);
		intel_ring_emit(ring, 0);
		intel_ring_emit(ring, 0);
1566 1567
	}

1568
	intel_ring_advance(ring);
1569 1570 1571 1572

	return 0;
}

1573
static void bxt_a_seqno_barrier(struct intel_engine_cs *engine)
1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584
{
	/*
	 * On BXT A steppings there is a HW coherency issue whereby the
	 * MI_STORE_DATA_IMM storing the completed request's seqno
	 * occasionally doesn't invalidate the CPU cache. Work around this by
	 * clflushing the corresponding cacheline whenever the caller wants
	 * the coherency to be guaranteed. Note that this cacheline is known
	 * to be clean at this point, since we only write it in
	 * bxt_a_set_seqno(), where we also do a clflush after the write. So
	 * this clflush in practice becomes an invalidate operation.
	 */
1585
	intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
1586 1587
}

1588 1589 1590 1591 1592 1593 1594
/*
 * Reserve space for 2 NOOPs at the end of each request to be
 * used as a workaround for not being allowed to do lite
 * restore with HEAD==TAIL (WaIdleLiteRestore).
 */
#define WA_TAIL_DWORDS 2

1595
static int gen8_emit_request(struct drm_i915_gem_request *request)
1596
{
1597
	struct intel_ring *ring = request->ring;
1598 1599
	int ret;

1600
	ret = intel_ring_begin(request, 6 + WA_TAIL_DWORDS);
1601 1602 1603
	if (ret)
		return ret;

1604 1605
	/* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
	BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
1606

1607 1608 1609 1610 1611 1612 1613 1614
	intel_ring_emit(ring, (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW);
	intel_ring_emit(ring,
			intel_hws_seqno_address(request->engine) |
			MI_FLUSH_DW_USE_GTT);
	intel_ring_emit(ring, 0);
	intel_ring_emit(ring, request->fence.seqno);
	intel_ring_emit(ring, MI_USER_INTERRUPT);
	intel_ring_emit(ring, MI_NOOP);
1615
	return intel_logical_ring_advance(request);
1616
}
1617

1618 1619
static int gen8_emit_request_render(struct drm_i915_gem_request *request)
{
1620
	struct intel_ring *ring = request->ring;
1621
	int ret;
1622

1623
	ret = intel_ring_begin(request, 8 + WA_TAIL_DWORDS);
1624 1625 1626
	if (ret)
		return ret;

1627 1628 1629
	/* We're using qword write, seqno should be aligned to 8 bytes. */
	BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);

1630 1631 1632 1633
	/* w/a for post sync ops following a GPGPU operation we
	 * need a prior CS_STALL, which is emitted by the flush
	 * following the batch.
	 */
1634 1635 1636 1637 1638 1639 1640 1641
	intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6));
	intel_ring_emit(ring,
			(PIPE_CONTROL_GLOBAL_GTT_IVB |
			 PIPE_CONTROL_CS_STALL |
			 PIPE_CONTROL_QW_WRITE));
	intel_ring_emit(ring, intel_hws_seqno_address(request->engine));
	intel_ring_emit(ring, 0);
	intel_ring_emit(ring, i915_gem_request_get_seqno(request));
1642
	/* We're thrashing one dword of HWS. */
1643 1644 1645
	intel_ring_emit(ring, 0);
	intel_ring_emit(ring, MI_USER_INTERRUPT);
	intel_ring_emit(ring, MI_NOOP);
1646
	return intel_logical_ring_advance(request);
1647 1648
}

1649
static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1650 1651 1652
{
	int ret;

1653
	ret = intel_logical_ring_workarounds_emit(req);
1654 1655 1656
	if (ret)
		return ret;

1657 1658 1659 1660 1661 1662 1663 1664
	ret = intel_rcs_context_init_mocs(req);
	/*
	 * Failing to program the MOCS is non-fatal.The system will not
	 * run at peak performance. So generate an error and carry on.
	 */
	if (ret)
		DRM_ERROR("MOCS failed to program: expect performance issues.\n");

1665
	return i915_gem_render_state_init(req);
1666 1667
}

1668 1669
/**
 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1670
 * @engine: Engine Command Streamer.
1671
 */
1672
void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
1673
{
1674
	struct drm_i915_private *dev_priv;
1675

1676
	if (!intel_engine_initialized(engine))
1677 1678
		return;

1679 1680 1681 1682 1683 1684 1685
	/*
	 * Tasklet cannot be active at this point due intel_mark_active/idle
	 * so this is just for documentation.
	 */
	if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state)))
		tasklet_kill(&engine->irq_tasklet);

1686
	dev_priv = engine->i915;
1687

1688 1689
	if (engine->buffer) {
		WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
1690
	}
1691

1692 1693
	if (engine->cleanup)
		engine->cleanup(engine);
1694

1695
	intel_engine_cleanup_common(engine);
1696

1697 1698 1699
	if (engine->status_page.vma) {
		i915_gem_object_unpin_map(engine->status_page.vma->obj);
		engine->status_page.vma = NULL;
1700
	}
1701
	intel_lr_context_unpin(dev_priv->kernel_context, engine);
1702

1703 1704 1705
	engine->idle_lite_restore_wa = 0;
	engine->disable_lite_restore_wa = false;
	engine->ctx_desc_template = 0;
1706

1707
	lrc_destroy_wa_ctx_obj(engine);
1708
	engine->i915 = NULL;
1709 1710
}

1711 1712 1713 1714 1715
void intel_execlists_enable_submission(struct drm_i915_private *dev_priv)
{
	struct intel_engine_cs *engine;

	for_each_engine(engine, dev_priv)
1716
		engine->submit_request = execlists_submit_request;
1717 1718
}

1719
static void
1720
logical_ring_default_vfuncs(struct intel_engine_cs *engine)
1721 1722
{
	/* Default vfuncs which can be overriden by each engine. */
1723 1724
	engine->init_hw = gen8_init_common_ring;
	engine->emit_flush = gen8_emit_flush;
1725
	engine->emit_request = gen8_emit_request;
1726
	engine->submit_request = execlists_submit_request;
1727

1728 1729
	engine->irq_enable = gen8_logical_ring_enable_irq;
	engine->irq_disable = gen8_logical_ring_disable_irq;
1730
	engine->emit_bb_start = gen8_emit_bb_start;
1731
	if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
1732
		engine->irq_seqno_barrier = bxt_a_seqno_barrier;
1733 1734
}

1735
static inline void
1736
logical_ring_default_irqs(struct intel_engine_cs *engine)
1737
{
1738
	unsigned shift = engine->irq_shift;
1739 1740
	engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
	engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
1741 1742
}

1743
static int
1744
lrc_setup_hws(struct intel_engine_cs *engine, struct i915_vma *vma)
1745
{
1746
	const int hws_offset = LRC_PPHWSP_PN * PAGE_SIZE;
1747
	void *hws;
1748 1749

	/* The HWSP is part of the default context object in LRC mode. */
1750
	hws = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
1751 1752
	if (IS_ERR(hws))
		return PTR_ERR(hws);
1753 1754 1755 1756

	engine->status_page.page_addr = hws + hws_offset;
	engine->status_page.ggtt_offset = vma->node.start + hws_offset;
	engine->status_page.vma = vma;
1757 1758

	return 0;
1759 1760
}

1761 1762 1763 1764 1765 1766
static void
logical_ring_setup(struct intel_engine_cs *engine)
{
	struct drm_i915_private *dev_priv = engine->i915;
	enum forcewake_domains fw_domains;

1767 1768
	intel_engine_setup_common(engine);

1769 1770 1771 1772 1773 1774 1775 1776 1777 1778 1779 1780 1781 1782 1783 1784 1785 1786 1787 1788 1789 1790 1791 1792 1793
	/* Intentionally left blank. */
	engine->buffer = NULL;

	fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
						    RING_ELSP(engine),
						    FW_REG_WRITE);

	fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
						     RING_CONTEXT_STATUS_PTR(engine),
						     FW_REG_READ | FW_REG_WRITE);

	fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
						     RING_CONTEXT_STATUS_BUF_BASE(engine),
						     FW_REG_READ);

	engine->fw_domains = fw_domains;

	tasklet_init(&engine->irq_tasklet,
		     intel_lrc_irq_handler, (unsigned long)engine);

	logical_ring_init_platform_invariants(engine);
	logical_ring_default_vfuncs(engine);
	logical_ring_default_irqs(engine);
}

1794 1795 1796 1797 1798 1799
static int
logical_ring_init(struct intel_engine_cs *engine)
{
	struct i915_gem_context *dctx = engine->i915->kernel_context;
	int ret;

1800
	ret = intel_engine_init_common(engine);
1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818 1819 1820 1821 1822 1823 1824 1825 1826 1827 1828 1829
	if (ret)
		goto error;

	ret = execlists_context_deferred_alloc(dctx, engine);
	if (ret)
		goto error;

	/* As this is the default context, always pin it */
	ret = intel_lr_context_pin(dctx, engine);
	if (ret) {
		DRM_ERROR("Failed to pin context for %s: %d\n",
			  engine->name, ret);
		goto error;
	}

	/* And setup the hardware status page. */
	ret = lrc_setup_hws(engine, dctx->engine[engine->id].state);
	if (ret) {
		DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret);
		goto error;
	}

	return 0;

error:
	intel_logical_ring_cleanup(engine);
	return ret;
}

1830
int logical_render_ring_init(struct intel_engine_cs *engine)
1831 1832 1833 1834
{
	struct drm_i915_private *dev_priv = engine->i915;
	int ret;

1835 1836
	logical_ring_setup(engine);

1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848
	if (HAS_L3_DPF(dev_priv))
		engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;

	/* Override some for render ring. */
	if (INTEL_GEN(dev_priv) >= 9)
		engine->init_hw = gen9_init_render_ring;
	else
		engine->init_hw = gen8_init_render_ring;
	engine->init_context = gen8_init_rcs_context;
	engine->emit_flush = gen8_emit_flush_render;
	engine->emit_request = gen8_emit_request_render;

1849
	ret = intel_engine_create_scratch(engine, 4096);
1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871
	if (ret)
		return ret;

	ret = intel_init_workaround_bb(engine);
	if (ret) {
		/*
		 * We continue even if we fail to initialize WA batch
		 * because we only expect rare glitches but nothing
		 * critical to prevent us from using GPU
		 */
		DRM_ERROR("WA batch buffer initialization failed: %d\n",
			  ret);
	}

	ret = logical_ring_init(engine);
	if (ret) {
		lrc_destroy_wa_ctx_obj(engine);
	}

	return ret;
}

1872
int logical_xcs_ring_init(struct intel_engine_cs *engine)
1873 1874 1875 1876
{
	logical_ring_setup(engine);

	return logical_ring_init(engine);
1877 1878
}

1879
static u32
1880
make_rpcs(struct drm_i915_private *dev_priv)
1881 1882 1883 1884 1885 1886 1887
{
	u32 rpcs = 0;

	/*
	 * No explicit RPCS request is needed to ensure full
	 * slice/subslice/EU enablement prior to Gen9.
	*/
1888
	if (INTEL_GEN(dev_priv) < 9)
1889 1890 1891 1892 1893 1894 1895 1896
		return 0;

	/*
	 * Starting in Gen9, render power gating can leave
	 * slice/subslice/EU in a partially enabled state. We
	 * must make an explicit request through RPCS for full
	 * enablement.
	*/
1897
	if (INTEL_INFO(dev_priv)->has_slice_pg) {
1898
		rpcs |= GEN8_RPCS_S_CNT_ENABLE;
1899
		rpcs |= INTEL_INFO(dev_priv)->slice_total <<
1900 1901 1902 1903
			GEN8_RPCS_S_CNT_SHIFT;
		rpcs |= GEN8_RPCS_ENABLE;
	}

1904
	if (INTEL_INFO(dev_priv)->has_subslice_pg) {
1905
		rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
1906
		rpcs |= INTEL_INFO(dev_priv)->subslice_per_slice <<
1907 1908 1909 1910
			GEN8_RPCS_SS_CNT_SHIFT;
		rpcs |= GEN8_RPCS_ENABLE;
	}

1911 1912
	if (INTEL_INFO(dev_priv)->has_eu_pg) {
		rpcs |= INTEL_INFO(dev_priv)->eu_per_subslice <<
1913
			GEN8_RPCS_EU_MIN_SHIFT;
1914
		rpcs |= INTEL_INFO(dev_priv)->eu_per_subslice <<
1915 1916 1917 1918 1919 1920 1921
			GEN8_RPCS_EU_MAX_SHIFT;
		rpcs |= GEN8_RPCS_ENABLE;
	}

	return rpcs;
}

1922
static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
1923 1924 1925
{
	u32 indirect_ctx_offset;

1926
	switch (INTEL_GEN(engine->i915)) {
1927
	default:
1928
		MISSING_CASE(INTEL_GEN(engine->i915));
1929 1930 1931 1932 1933 1934 1935 1936 1937 1938 1939 1940 1941 1942
		/* fall through */
	case 9:
		indirect_ctx_offset =
			GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
		break;
	case 8:
		indirect_ctx_offset =
			GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
		break;
	}

	return indirect_ctx_offset;
}

1943
static int
1944
populate_lr_context(struct i915_gem_context *ctx,
1945
		    struct drm_i915_gem_object *ctx_obj,
1946
		    struct intel_engine_cs *engine,
1947
		    struct intel_ring *ring)
1948
{
1949
	struct drm_i915_private *dev_priv = ctx->i915;
1950
	struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
1951 1952
	void *vaddr;
	u32 *reg_state;
1953 1954
	int ret;

1955 1956 1957
	if (!ppgtt)
		ppgtt = dev_priv->mm.aliasing_ppgtt;

1958 1959 1960 1961 1962 1963
	ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
	if (ret) {
		DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
		return ret;
	}

1964
	vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
1965 1966 1967
	if (IS_ERR(vaddr)) {
		ret = PTR_ERR(vaddr);
		DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
1968 1969
		return ret;
	}
1970
	ctx_obj->dirty = true;
1971 1972 1973

	/* The second page of the context object contains some fields which must
	 * be set up prior to the first execution. */
1974
	reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
1975 1976 1977 1978 1979 1980

	/* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
	 * commands followed by (reg, value) pairs. The values we are setting here are
	 * only for the first context restore: on a subsequent save, the GPU will
	 * recreate this batchbuffer with new values (including all the missing
	 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1981
	reg_state[CTX_LRI_HEADER_0] =
1982 1983 1984
		MI_LOAD_REGISTER_IMM(engine->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED;
	ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL,
		       RING_CONTEXT_CONTROL(engine),
1985 1986
		       _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
					  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
1987
					  (HAS_RESOURCE_STREAMER(dev_priv) ?
1988
					    CTX_CTRL_RS_CTX_ENABLE : 0)));
1989 1990 1991 1992
	ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(engine->mmio_base),
		       0);
1993 1994 1995
	/* Ring buffer start address is not known until the buffer is pinned.
	 * It is written to the context image in execlists_update_context()
	 */
1996 1997 1998 1999
	ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START,
		       RING_START(engine->mmio_base), 0);
	ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL,
		       RING_CTL(engine->mmio_base),
2000
		       ((ring->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID);
2001 2002 2003 2004 2005 2006
	ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U,
		       RING_BBADDR_UDW(engine->mmio_base), 0);
	ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L,
		       RING_BBADDR(engine->mmio_base), 0);
	ASSIGN_CTX_REG(reg_state, CTX_BB_STATE,
		       RING_BBSTATE(engine->mmio_base),
2007
		       RING_BB_PPGTT);
2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020
	ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U,
		       RING_SBBADDR_UDW(engine->mmio_base), 0);
	ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L,
		       RING_SBBADDR(engine->mmio_base), 0);
	ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE,
		       RING_SBBSTATE(engine->mmio_base), 0);
	if (engine->id == RCS) {
		ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR,
			       RING_BB_PER_CTX_PTR(engine->mmio_base), 0);
		ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX,
			       RING_INDIRECT_CTX(engine->mmio_base), 0);
		ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET,
			       RING_INDIRECT_CTX_OFFSET(engine->mmio_base), 0);
2021
		if (engine->wa_ctx.vma) {
2022
			struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2023
			u32 ggtt_offset = wa_ctx->vma->node.start;
2024 2025 2026 2027 2028 2029

			reg_state[CTX_RCS_INDIRECT_CTX+1] =
				(ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
				(wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);

			reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
2030
				intel_lr_indirect_ctx_offset(engine) << 6;
2031 2032 2033 2034 2035

			reg_state[CTX_BB_PER_CTX_PTR+1] =
				(ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
				0x01;
		}
2036
	}
2037
	reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2038 2039
	ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP,
		       RING_CTX_TIMESTAMP(engine->mmio_base), 0);
2040
	/* PDP values well be assigned later if needed */
2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056
	ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0),
		       0);
2057

2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069
	if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) {
		/* 64b PPGTT (48bit canonical)
		 * PDP0_DESCRIPTOR contains the base address to PML4 and
		 * other PDP Descriptors are ignored.
		 */
		ASSIGN_CTX_PML4(ppgtt, reg_state);
	} else {
		/* 32b PPGTT
		 * PDP*_DESCRIPTOR contains the base address of space supported.
		 * With dynamic page allocation, PDPs may not be allocated at
		 * this point. Point the unallocated PDPs to the scratch page
		 */
2070
		execlists_update_context_pdps(ppgtt, reg_state);
2071 2072
	}

2073
	if (engine->id == RCS) {
2074
		reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2075
		ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
2076
			       make_rpcs(dev_priv));
2077 2078
	}

2079
	i915_gem_object_unpin_map(ctx_obj);
2080 2081 2082 2083

	return 0;
}

2084 2085
/**
 * intel_lr_context_size() - return the size of the context for an engine
2086
 * @engine: which engine to find the context size for
2087 2088 2089 2090 2091 2092 2093 2094 2095 2096 2097
 *
 * Each engine may require a different amount of space for a context image,
 * so when allocating (or copying) an image, this function can be used to
 * find the right size for the specific engine.
 *
 * Return: size (in bytes) of an engine-specific context image
 *
 * Note: this size includes the HWSP, which is part of the context image
 * in LRC mode, but does not include the "shared data page" used with
 * GuC submission. The caller should account for this if using the GuC.
 */
2098
uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
2099 2100 2101
{
	int ret = 0;

2102
	WARN_ON(INTEL_GEN(engine->i915) < 8);
2103

2104
	switch (engine->id) {
2105
	case RCS:
2106
		if (INTEL_GEN(engine->i915) >= 9)
2107 2108 2109
			ret = GEN9_LR_CONTEXT_RENDER_SIZE;
		else
			ret = GEN8_LR_CONTEXT_RENDER_SIZE;
2110 2111 2112 2113 2114 2115 2116 2117 2118 2119
		break;
	case VCS:
	case BCS:
	case VECS:
	case VCS2:
		ret = GEN8_LR_CONTEXT_OTHER_SIZE;
		break;
	}

	return ret;
2120 2121
}

2122
static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
2123
					    struct intel_engine_cs *engine)
2124
{
2125
	struct drm_i915_gem_object *ctx_obj;
2126
	struct intel_context *ce = &ctx->engine[engine->id];
2127
	struct i915_vma *vma;
2128
	uint32_t context_size;
2129
	struct intel_ring *ring;
2130 2131
	int ret;

2132
	WARN_ON(ce->state);
2133

2134
	context_size = round_up(intel_lr_context_size(engine), 4096);
2135

2136 2137 2138
	/* One extra page as the sharing data between driver and GuC */
	context_size += PAGE_SIZE * LRC_PPHWSP_PN;

2139
	ctx_obj = i915_gem_object_create(&ctx->i915->drm, context_size);
2140
	if (IS_ERR(ctx_obj)) {
2141
		DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2142
		return PTR_ERR(ctx_obj);
2143 2144
	}

2145 2146 2147 2148 2149 2150
	vma = i915_vma_create(ctx_obj, &ctx->i915->ggtt.base, NULL);
	if (IS_ERR(vma)) {
		ret = PTR_ERR(vma);
		goto error_deref_obj;
	}

2151
	ring = intel_engine_create_ring(engine, ctx->ring_size);
2152 2153
	if (IS_ERR(ring)) {
		ret = PTR_ERR(ring);
2154
		goto error_deref_obj;
2155 2156
	}

2157
	ret = populate_lr_context(ctx, ctx_obj, engine, ring);
2158 2159
	if (ret) {
		DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2160
		goto error_ring_free;
2161 2162
	}

2163
	ce->ring = ring;
2164
	ce->state = vma;
2165
	ce->initialised = engine->init_context == NULL;
2166 2167

	return 0;
2168

2169
error_ring_free:
2170
	intel_ring_free(ring);
2171
error_deref_obj:
2172
	i915_gem_object_put(ctx_obj);
2173
	return ret;
2174
}
2175

2176
void intel_lr_context_reset(struct drm_i915_private *dev_priv,
2177
			    struct i915_gem_context *ctx)
2178
{
2179
	struct intel_engine_cs *engine;
2180

2181
	for_each_engine(engine, dev_priv) {
2182
		struct intel_context *ce = &ctx->engine[engine->id];
2183
		void *vaddr;
2184 2185
		uint32_t *reg_state;

2186
		if (!ce->state)
2187 2188
			continue;

2189
		vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
2190
		if (WARN_ON(IS_ERR(vaddr)))
2191
			continue;
2192 2193

		reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
2194 2195 2196 2197

		reg_state[CTX_RING_HEAD+1] = 0;
		reg_state[CTX_RING_TAIL+1] = 0;

2198 2199
		ce->state->obj->dirty = true;
		i915_gem_object_unpin_map(ce->state->obj);
2200

2201 2202
		ce->ring->head = 0;
		ce->ring->tail = 0;
2203 2204
	}
}
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