Corner Case that makes l2tlb's performance decrease sharply:
core may have mis-speculative memory access, which may cause tlb-miss and ptw req to l2tlb.
In l2tlb, the reqs may still miss and even have invalid pte that won't be stored in l2tlb.cache.
If the relative ptes are invalid, these reqs will be held by miss queue and wait for page walker performing
page table walk one by one. It's too slow and will raise time out assert in l2tlb.missqueue.

Solution:
store invalid entries(only super entries) into sp.
Bad news is that sp only has16 entries, so invaid entries will pollute sp as well.
Good news is that the invalid reqs are always in same super page, so only one entries is mostly enough.

* l2tlb.cache: sp entries now handles invalid entries

* l2tlb.cache: fix syntax error, forgot assgin some signals

Add support for compiling XiangShan with CIRCT

* bump huancun

* sram: fix sram, keep rdata when w.valid

* tlb: when refill, just return miss at next cycle, rm unused assert

bump difftest and fix Makefile for VCS support

iprefetch uses vaddr instead of paddr.

Fix the file extension for inline verilog modules.

* IFU <bug-fix>: deal with itlb miss for resend

* IFU <bug fix>: enable crossPageFault for resend-pf
Co-authored-by: NDeltaZero <lacrosseelis@gmail.com>

* readme: update dir structure description and sync en/zh readme

* readme: update fig of nanhu-arch

* readme: update docs information

* readme: fix md format

* bump huancun

* bump huancun

* bump huancun

* Insert 1 buffer betwwen L2 and L3
Co-authored-by: NLinJiawei <linjiawei20s@ict.ac.cn>

* mem: opt dcache tag error check timing

dcache.resp.bits.miss used to depend on tag_error, it causes severe
timing problem. That dependence is now removed.

Now when tag_error, we:

* Set access fault bit in exception vec
* Do not update miss queue. That is to say, if miss, that inst
may not be refilled
* Mark that inst as dataForwarded so it will not wait for refill
* Report error to CSR and BEU

If tag_error come with a miss, writeback taht inst from load
queue. Otherwise, writeback it from load pipeline.

* mem: opt tag error exception writeback logic

dcache.resp.bits.miss used to depend on tag_error, it causes severe
timing problem. That dependence is now removed.

Now when tag_error, we:

* Set access fault bit in exception vec
* Do not update miss queue. That is to say, if miss, that inst
may not be refilled
* Mark that inst as dataForwarded so it will not wait for refill
* Report error to CSR and BEU

If tag_error come with a miss, writeback taht inst from load
queue. Otherwise, writeback it from load pipeline.

* ITLB <timing>: delay miss and flush req for ITLB

* add 2 ILTB requestor and delete tlb_arb

* Bump huancun

* ICacheMainPipe <bug-fix>: fix slot invalid condition

* ITLB <timing>: add port to 6

* ICacheMainPipe <bug-fix>: stop pipe when tlb miss

* ICacheMainPipe <bug-fix>: fix illegal flush
Co-authored-by: NLinJiawei <linjiawei20s@ict.ac.cn>

* mem: fix ldld vio mask gen logic

* mem: fix lq released flag update logic

Make sure that every load before a probe has correct released flag

See the PR of this commit for illustration

* mem: fix ld-ld violation check logic

* ci: clean up workspace before do real test

* mem: reduce lq released flag update delay for 1 cycle

* chore: bump difftest to run no-smp diff

* ci: add mc test

* mem: fix lq released flag update logic

* chore: set difftest firstCommit_limit to 10000

* ci: use dual-nemu-so for mc test

the mulitple-hit problem is yet to be solved (although it may be very rare)

* SoC: remove error_xbar; add more buffers

* Bump huancun

* Misc: set timeout threshold to 10000 cycles

* Bump huancun

* SoC: timing opt

* Added buffers for pma
Co-authored-by: NYinan Xu <xuyinan@ict.ac.cn>