mem: opt tag error exception writeback logic (#1464)

* mem: opt dcache tag error check timing

dcache.resp.bits.miss used to depend on tag_error, it causes severe
timing problem. That dependence is now removed.

Now when tag_error, we:

* Set access fault bit in exception vec
* Do not update miss queue. That is to say, if miss, that inst
may not be refilled
* Mark that inst as dataForwarded so it will not wait for refill
* Report error to CSR and BEU

If tag_error come with a miss, writeback taht inst from load
queue. Otherwise, writeback it from load pipeline.

* mem: opt tag error exception writeback logic

src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala

@@ -423,8 +423,8 @@ class LoadUnit_S2(implicit p: Parameters) extends XSModule with HasLoadHelper {
   //    will not update miss queue. That is to say, if miss, that inst
   //    may not be refilled
   // Such inst will be writebacked from load queue.
-  io.dataForwarded := s2_cache_miss && fullForward && !s2_exception && !s2_forward_fail || // case 1
-    io.csrCtrl.cache_error_enable && s2_cache_tag_error // case 2
+  io.dataForwarded := s2_cache_miss && !s2_exception && !s2_forward_fail &&
+    (fullForward || io.csrCtrl.cache_error_enable && s2_cache_tag_error)
   // io.out.bits.forwardX will be send to lq
   io.out.bits.forwardMask := forwardMask
   // data retbrived from dcache is also included in io.out.bits.forwardData