l2tlb: req from missqueue doesn't cause prefetch (#1448)

src/main/scala/xiangshan/cache/mmu/PTW.scala

@@ -112,8 +112,10 @@ class PTWImp(outer: PTW)(implicit p: Parameters) extends PtwModule(outer) with H
   if (l2tlbParams.enablePrefetch) {
     val prefetch = Module(new L2TlbPrefetch())
     val recv = cache.io.resp
+    // NOTE: 1. prefetch doesn't gen prefetch 2. req from mq doesn't gen prefetch
+    // NOTE: 1. miss req gen prefetch 2. hit but prefetched gen prefetch
     prefetch.io.in.valid := recv.fire() && !from_pre(recv.bits.req_info.source) && (!recv.bits.hit  ||
-      recv.bits.prefetch)
+      recv.bits.prefetch) && recv.bits.isFirst
     prefetch.io.in.bits.vpn := recv.bits.req_info.vpn
     prefetch.io.sfence := sfence
     prefetch.io.csr := csr

src/main/scala/xiangshan/cache/mmu/PageTableCache.scala

@@ -67,6 +67,7 @@ class PtwCacheIO()(implicit p: Parameters) extends MMUIOBaseBundle with HasPtwCo
   val req = Flipped(DecoupledIO(new PtwCacheReq()))
   val resp = DecoupledIO(new Bundle {
     val req_info = new L2TlbInnerBundle()
+    val isFirst = Bool()
     val hit = Bool()
     val prefetch = Bool() // is the entry fetched by prefetch
     val toFsm = new Bundle {
@@ -323,6 +324,7 @@ class PtwCache()(implicit p: Parameters) extends XSModule with HasPtwConst with
   }
 
   io.resp.bits.req_info   := stage3.bits.req_info
+  io.resp.bits.isFirst  := stage3.bits.isFirst
   io.resp.bits.hit      := s3_res.l3.hit || s3_res.sp.hit
   io.resp.bits.prefetch := s3_res.l3.pre && s3_res.l3.hit || s3_res.sp.pre && s3_res.sp.hit
   io.resp.bits.toFsm.l1Hit := s3_res.l1.hit