bump huancun (#1466)

* bump huancun

* bump huancun

* bump huancun

* Insert 1 buffer betwwen L2 and L3
Co-authored-by: NLinJiawei <linjiawei20s@ict.ac.cn>

huancun @ db0f43bb

-Subproject commit bce16f9d57c76d4aad8dfbfe5d3ec61591b1b6cf
+Subproject commit db0f43bbae65ff24b1af72469abb9589fe2a21e1

src/main/scala/xiangshan/XSTile.scala

@@ -57,7 +57,7 @@ class XSTileMisc()(implicit p: Parameters) extends LazyModule
 
   l2_binder match {
     case Some(binder) =>
-      memory_port := TLBuffer() := TLClientsMerger() := TLXbar() :=* binder
+      memory_port := TLBuffer.chainNode(2) := TLClientsMerger() := TLXbar() :=* binder
     case None =>
       memory_port := l1_xbar
   }