SoC: timing opt (#1431)

* SoC: timing opt

* Added buffers for pma
Co-authored-by: NYinan Xu <xuyinan@ict.ac.cn>

src/main/scala/system/SoC.scala

@@ -154,7 +154,7 @@ trait HaveAXI4MemPort {
   mem_xbar :=*
     TLXbar() :=*
     BinaryArbiter() :=*
-    TLBuffer() :=*
+    TLBuffer.chainNode(2) :=*
     TLCacheCork() :=*
     bankedNode
 
@@ -288,8 +288,7 @@ class SoCMisc()(implicit p: Parameters) extends BaseSoC
 
   val pma = LazyModule(new TLPMA)
   pma.node := 
-    TLBuffer() :=
-    TLBuffer() :=
+    TLBuffer.chainNode(4) :=
     peripheralXbar
 
   lazy val module = new LazyModuleImp(this){

src/main/scala/top/Top.scala

@@ -107,7 +107,7 @@ class XSTop()(implicit p: Parameters) extends BaseXSSoc() with HasSoCParameter
 
   l3cacheOpt match {
     case Some(l3) =>
-      misc.l3_out :*= l3.node :*= TLBuffer() :*= misc.l3_banked_xbar
+      misc.l3_out :*= l3.node :*= TLBuffer.chainNode(2) :*= misc.l3_banked_xbar
     case None =>
   }