未验证 提交 acc88887 编写于 作者: J Jiawei Lin 提交者: GitHub

SoC: remove error_xbar; add more buffers (#1454)

* SoC: remove error_xbar; add more buffers

* Bump huancun

* Misc: set timeout threshold to 10000 cycles

* Bump huancun
上级 f678dd91
Subproject commit 298ac7737b0ce633490844f92c2fd199a2f4744d
Subproject commit 9ee39663d874715a75fcd7d89b4c6e6e6e3c4716
......@@ -108,7 +108,7 @@ trait HaveSlaveAXI4Port {
))
private val error_xbar = TLXbar()
error_xbar :=
l3_xbar :=
TLFIFOFixer() :=
TLWidthWidget(32) :=
AXI4ToTL() :=
......@@ -118,10 +118,7 @@ trait HaveSlaveAXI4Port {
AXI4Buffer() :=
AXI4IdIndexer(1) :=
l3FrontendAXI4Node
errorDevice.node := error_xbar
l3_xbar :=
TLBuffer() :=
error_xbar
errorDevice.node := l3_xbar
val dma = InModuleBody {
l3FrontendAXI4Node.makeIOs()
......@@ -153,7 +150,6 @@ trait HaveAXI4MemPort {
val mem_xbar = TLXbar()
mem_xbar :=*
TLXbar() :=*
BinaryArbiter() :=*
TLBuffer.chainNode(2) :=*
TLCacheCork() :=*
bankedNode
......@@ -164,6 +160,8 @@ trait HaveAXI4MemPort {
peripheralXbar
memAXI4SlaveNode :=
AXI4Buffer() :=
AXI4Buffer() :=
AXI4Buffer() :=
AXI4IdIndexer(idBits = 14) :=
AXI4UserYanker() :=
......@@ -214,7 +212,7 @@ trait HaveAXI4PeripheralPort { this: BaseSoC =>
AXI4UserYanker() :=
AXI4Deinterleaver(8) :=
TLToAXI4() :=
TLBuffer() :=
TLBuffer.chainNode(3) :=
peripheralXbar
val peripheral = InModuleBody {
......@@ -253,7 +251,7 @@ class SoCMisc()(implicit p: Parameters) extends BaseSoC
TLBuffer() :=
core_out
}
l3_banked_xbar := TLBuffer() := l3_xbar
l3_banked_xbar := TLBuffer.chainNode(2) := l3_xbar
val clint = LazyModule(new CLINT(CLINTParams(0x38000000L), 8))
clint.node := peripheralXbar
......
......@@ -90,7 +90,7 @@ trait HasTlbConst extends HasXSParameter {
val sramSinglePort = true
val timeOutThreshold = 5000
val timeOutThreshold = 10000
def get_set_idx(vpn: UInt, nSets: Int): UInt = {
require(nSets >= 1)
......
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