Misc: add support for compiling with CIRCT

Makefile

@@ -26,6 +26,18 @@ SIMTOP  = top.SimTop
 IMAGE  ?= temp
 CONFIG ?= DefaultConfig
 NUM_CORES ?= 1
+MFC ?= 0
+
+FPGA_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full
+SIM_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full
+
+# select firrtl complier
+ifeq ($(MFC),1)
+override FC_ARGS = --mfc
+override FPGA_MEM_ARGS =
+override SIM_MEM_ARGS =
+endif
+
 
 # co-simulation with DRAMsim3
 ifeq ($(WITH_DRAMSIM3),1)
@@ -47,19 +59,28 @@ endif
 TIMELOG = $(BUILD_DIR)/time.log
 TIME_CMD = time -a -o $(TIMELOG)
 
+SED_CMD = sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g'
+
+# add comments to 'firrtl_black_box_resource_files'
+AWK_CMD = gawk -i inplace 'BEGIN{f=0} /FILE "firrtl_black_box_resource_files.f"/{f=1} !f{print $$0} f{print "//", $$0}'
+
+
 .DEFAULT_GOAL = verilog
 
 help:
-	mill -i XiangShan.test.runMain $(SIMTOP) --help
+	mill -i XiangShan.runMain $(FPGATOP) --help
 
 $(TOP_V): $(SCALA_FILE)
 	mkdir -p $(@D)
-	$(TIME_CMD) mill -i XiangShan.runMain $(FPGATOP) -td $(@D)		\
-		--config $(CONFIG) --full-stacktrace --output-file $(@F)    \
-		--infer-rw --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf \
-		--gen-mem-verilog full --num-cores $(NUM_CORES)             \
-		$(RELEASE_ARGS)
-	sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' $@
+	$(TIME_CMD) mill -i XiangShan.runMain $(FPGATOP) -td $(@D)  \
+		--config $(CONFIG)                                        \
+		$(FPGA_MEM_ARGS)                                          \
+		--num-cores $(NUM_CORES)                                  \
+		$(RELEASE_ARGS) $(FC_ARGS)
+	$(SED_CMD) $@
+ifeq ($(MFC),1)
+	$(AWK_CMD) $@
+endif
 	@git log -n 1 >> .__head__
 	@git diff >> .__diff__
 	@sed -i 's/^/\/\// ' .__head__
@@ -76,12 +97,15 @@ $(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
 	mkdir -p $(@D)
 	@echo "\n[mill] Generating Verilog files..." > $(TIMELOG)
 	@date -R | tee -a $(TIMELOG)
-	$(TIME_CMD) mill -i XiangShan.test.runMain $(SIMTOP) -td $(@D)      \
-		--config $(CONFIG) --full-stacktrace --output-file $(@F)    \
-		--infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf  \
-		--gen-mem-verilog full --num-cores $(NUM_CORES)             \
-		$(SIM_ARGS)
-	sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' $@
+	$(TIME_CMD) mill -i XiangShan.test.runMain $(SIMTOP) -td $(@D)  \
+		--config $(CONFIG)                                            \
+		$(SIM_MEM_ARGS)                                               \
+		--num-cores $(NUM_CORES)                                      \
+		$(SIM_ARGS) $(FC_ARGS)
+	$(SED_CMD) $@
+ifeq ($(MFC),1)
+	$(AWK_CMD) $@
+endif
 	@git log -n 1 >> .__head__
 	@git diff >> .__diff__
 	@sed -i 's/^/\/\// ' .__head__

build.sc

@@ -28,6 +28,7 @@ object ivys {
   val chisel3 = ivy"edu.berkeley.cs::chisel3:3.5.0"
   val chisel3Plugin = ivy"edu.berkeley.cs:::chisel3-plugin:3.5.0"
   val chiseltest = ivy"edu.berkeley.cs::chiseltest:0.3.2"
+  val chiselCirct = ivy"com.sifive::chisel-circt:0.4.0"
   val scalatest = ivy"org.scalatest::scalatest:3.2.2"
   val macroParadise = ivy"org.scalamacros:::paradise:2.1.1"
 }
@@ -45,7 +46,7 @@ trait XSModule extends ScalaModule with PublishModule {
 
   override def scalacOptions = Seq("-Xsource:2.11")
 
-  override def ivyDeps = if(chiselOpt.isEmpty) Agg(ivys.chisel3) else Agg.empty[Dep]
+  override def ivyDeps = (if(chiselOpt.isEmpty) Agg(ivys.chisel3) else Agg.empty[Dep]) ++ Agg(ivys.chiselCirct)
 
   override def moduleDeps = Seq() ++ chiselOpt
 

src/main/scala/top/ArgParser.scala

@@ -36,6 +36,7 @@ object ArgParser {
       |--enable-difftest
       |--enable-log
       |--disable-perf
+      |--mfc
       |""".stripMargin
 
   def getConfigByName(confString: String): Parameters = {
@@ -46,9 +47,10 @@ object ArgParser {
     val c = Class.forName(prefix + confString).getConstructor(Integer.TYPE)
     c.newInstance(1.asInstanceOf[Object]).asInstanceOf[Parameters]
   }
-  def parse(args: Array[String]): (Parameters, Array[String]) = {
+  def parse(args: Array[String]): (Parameters, Array[String], FirrtlCompiler) = {
     val default = new DefaultConfig(1)
     var firrtlOpts = Array[String]()
+    var firrtlCompiler: FirrtlCompiler = SFC
     @tailrec
     def nextOption(config: Parameters, list: List[String]): Parameters = {
       list match {
@@ -85,6 +87,9 @@ object ArgParser {
           nextOption(config.alter((site, here, up) => {
             case DebugOptionsKey => up(DebugOptionsKey).copy(EnablePerfDebug = false)
           }), tail)
+        case "--mfc" :: tail =>
+          firrtlCompiler = MFC
+          nextOption(config, tail)
         case option :: tail =>
           // unknown option, maybe a firrtl option, skip
           firrtlOpts :+= option
@@ -92,6 +97,6 @@ object ArgParser {
       }
     }
     var config = nextOption(default, args.toList)
-    (config, firrtlOpts)
+    (config, firrtlOpts, firrtlCompiler)
   }
 }

src/main/scala/top/XiangShanStage.scala → src/main/scala/top/Generator.scala

@@ -16,11 +16,11 @@
 
 package top
 
-import chisel3.stage.ChiselCli
-import firrtl.AnnotationSeq
-import firrtl.options.{Dependency, HasShellOptions, Shell, ShellOption}
+import chisel3.RawModule
+import chisel3.stage.{ChiselCli, ChiselGeneratorAnnotation}
+import firrtl.options.Shell
 import firrtl.stage.{FirrtlCli, RunFirrtlTransformAnnotation}
-import freechips.rocketchip.transforms.naming.{OverrideDesiredNameAnnotation, RenameDesiredNames}
+import freechips.rocketchip.transforms.naming.RenameDesiredNames
 import xstransforms._
 
 trait XiangShanCli { this: Shell =>
@@ -38,19 +38,50 @@ class XiangShanStage extends chisel3.stage.ChiselStage {
     with FirrtlCli
 }
 
-object XiangShanStage {
-  def execute
-  (
-    args: Array[String],
-    annotations: AnnotationSeq
-  ): AnnotationSeq = {
-    (new XiangShanStage).execute(
-      args,
-      annotations ++ Seq(
-        RunFirrtlTransformAnnotation(new PrintControl),
-        RunFirrtlTransformAnnotation(new PrintModuleName),
-        RunFirrtlTransformAnnotation(new RenameDesiredNames)
-      )
-    )
+abstract class FirrtlCompiler
+case object SFC extends FirrtlCompiler
+case object MFC extends FirrtlCompiler
+
+object Generator {
+
+  def execute(args: Array[String], mod: => RawModule, fc: FirrtlCompiler) = {
+    fc match {
+      case MFC =>
+        val sfcXsTransforms = Seq(
+          DisablePrintfAnnotation,
+          EnablePrintfAnnotation,
+          DisableAllPrintAnnotation,
+          RemoveAssertAnnotation
+        )
+        val sfcOptions = sfcXsTransforms.flatMap(_.options.map(_.longOption)) ++
+          sfcXsTransforms.flatMap(_.options.flatMap(_.shortOption))
+        val mfcArgs = args.filter(s => {
+          val option_s = if(s.startsWith("--")){
+            s.replace("--", "")
+          } else if(s.startsWith("-")){
+            s.replace("-", "")
+          } else s
+          val cond = sfcOptions.contains(option_s)
+          if(cond){
+            println(s"[Warnning] SFC Transform Option ${s} will be removed in MFC!")
+          }
+          !cond
+        })
+        (new circt.stage.ChiselStage).execute(mfcArgs, Seq(
+          ChiselGeneratorAnnotation(mod _),
+          circt.stage.CIRCTTargetAnnotation(circt.stage.CIRCTTarget.Verilog),
+          circt.stage.CIRCTHandover(circt.stage.CIRCTHandover.CHIRRTL)
+        ))
+      case SFC =>
+        (new XiangShanStage).execute(args, Seq(
+          ChiselGeneratorAnnotation(mod _),
+          RunFirrtlTransformAnnotation(new PrintControl),
+          RunFirrtlTransformAnnotation(new PrintModuleName),
+          RunFirrtlTransformAnnotation(new RenameDesiredNames)
+        ))
+      case _ =>
+        assert(false, s"Unknown firrtl compiler: ${fc.getClass.getName}!")
+    }
   }
+
 }

src/main/scala/top/Top.scala

@@ -24,20 +24,11 @@ import system._
 import device._
 import chisel3.stage.ChiselGeneratorAnnotation
 import chipsalliance.rocketchip.config._
-import device.{AXI4Plic, DebugModule, TLTimer}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
-import freechips.rocketchip.amba.axi4._
-import freechips.rocketchip.devices.tilelink._
-import freechips.rocketchip.diplomaticobjectmodel.logicaltree.GenericLogicalTreeNode
-import freechips.rocketchip.interrupts._
 import freechips.rocketchip.jtag.JTAGIO
-import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, XLen}
-import freechips.rocketchip.tilelink
 import freechips.rocketchip.util.{ElaborationArtefacts, HasRocketChipStageUtils, UIntToOH1}
-import huancun.debug.TLLogger
 import huancun.{HCCacheParamsKey, HuanCun}
-import freechips.rocketchip.devices.debug.{DebugIO, ResetCtrlIO}
 
 abstract class BaseXSSoc()(implicit p: Parameters) extends LazyModule
   with BindingScope
@@ -201,13 +192,9 @@ class XSTop()(implicit p: Parameters) extends BaseXSSoc() with HasSoCParameter
 
 object TopMain extends App with HasRocketChipStageUtils {
   override def main(args: Array[String]): Unit = {
-    val (config, firrtlOpts) = ArgParser.parse(args)
+    val (config, firrtlOpts, firrtlComplier) = ArgParser.parse(args)
     val soc = DisableMonitors(p => LazyModule(new XSTop()(p)))(config)
-    XiangShanStage.execute(firrtlOpts, Seq(
-      ChiselGeneratorAnnotation(() => {
-        soc.module
-      })
-    ))
+    Generator.execute(firrtlOpts, soc.module, firrtlComplier)
     ElaborationArtefacts.files.foreach{ case (extension, contents) =>
       writeOutputFile("./build", s"XSTop.${extension}", contents())
     }

src/test/scala/top/SimTop.scala

@@ -61,7 +61,7 @@ class SimTop(implicit p: Parameters) extends Module {
   soc.io.cacheable_check := DontCare
 
   val success = Wire(Bool())
-  val jtag = Module(new SimJTAG(tickDelay=3)(p)).connect(soc.io.systemjtag.jtag, clock, reset.asBool, ~reset.asBool, success)
+  val jtag = Module(new SimJTAG(tickDelay=3)(p)).connect(soc.io.systemjtag.jtag, clock, reset.asBool, !reset.asBool, success)
   soc.io.systemjtag.reset := reset
   soc.io.systemjtag.mfr_id := 0.U(11.W)
   soc.io.systemjtag.part_number := 0.U(16.W)
@@ -102,12 +102,12 @@ class SimTop(implicit p: Parameters) extends Module {
 object SimTop extends App {
   override def main(args: Array[String]): Unit = {
     // Keep this the same as TopMain except that SimTop is used here instead of XSTop
-    val (config, firrtlOpts) = ArgParser.parse(args)
-    XiangShanStage.execute(firrtlOpts, Seq(
-      ChiselGeneratorAnnotation(() => {
-        DisableMonitors(p => new SimTop()(p))(config)
-      })
-    ))
+    val (config, firrtlOpts, firrtlComplier) = ArgParser.parse(args)
+    Generator.execute(
+      firrtlOpts,
+      DisableMonitors(p => new SimTop()(p))(config),
+      firrtlComplier
+    )
     ElaborationArtefacts.files.foreach{ case (extension, contents) =>
       writeOutputFile("./build", s"XSTop.${extension}", contents())
     }