std: delay fp regfile read for one cycle (#1473)

src/main/scala/xiangshan/backend/Scheduler.scala

@@ -377,7 +377,8 @@ class SchedulerImp(outer: Scheduler) extends LazyModuleImp(outer) with HasXSPara
   }
 
   if (io.extra.fpRfReadIn.isDefined) {
-    io.extra.fpRfReadIn.get.map(_.addr).zip(readFpRf).foreach{ case (r, addr) => r := addr}
+    // Due to distance issues, we RegNext the address for cross-block regfile read
+    io.extra.fpRfReadIn.get.map(_.addr).zip(readFpRf).foreach{ case (r, addr) => r := RegNext(addr)}
     require(io.extra.fpRfReadIn.get.length == readFpRf.length)
   }
 

src/main/scala/xiangshan/backend/issue/DataArray.scala

@@ -66,8 +66,9 @@ class DataArray(params: RSParams)(implicit p: Parameters) extends XSModule {
   val io = IO(new DataArrayIO(params))
 
   for (i <- 0 until params.numSrc) {
-    val delayedWen = if (params.delayedRf) io.delayedWrite.map(_.valid) else Seq()
-    val delayedWaddr = if (params.delayedRf) RegNext(VecInit(io.write.map(_.addr))) else Seq()
+    // delayed by more one cycle for delayed write ports
+    val delayedWen = if (params.delayedRf) RegNext(VecInit(io.delayedWrite.map(_.valid))) else Seq()
+    val delayedWaddr = if (params.delayedRf) RegNext(RegNext(VecInit(io.write.map(_.addr)))) else Seq()
     val delayedWdata = if (params.delayedRf) io.delayedWrite.map(_.bits) else Seq()
 
     val partialWen = if (i < 2 && params.hasMidState) io.partialWrite.map(_.enable) else Seq()

src/main/scala/xiangshan/backend/issue/ReservationStation.scala

@@ -271,7 +271,7 @@ class ReservationStation(params: RSParams)(implicit p: Parameters) extends XSMod
     statusArray.io.update(i).data.valid := true.B
     statusArray.io.update(i).data.scheduled := params.delayedRf.B && needFpSource(i)
     statusArray.io.update(i).data.blocked := params.checkWaitBit.B && io.fromDispatch(i).bits.cf.loadWaitBit
-    statusArray.io.update(i).data.credit := Mux(params.delayedRf.B && needFpSource(i), 2.U, 0.U)
+    statusArray.io.update(i).data.credit := Mux(params.delayedRf.B && needFpSource(i), 3.U, 0.U)
     statusArray.io.update(i).data.srcState := VecInit(io.fromDispatch(i).bits.srcIsReady.take(params.numSrc))
     statusArray.io.update(i).data.midState := false.B
     statusArray.io.update(i).data.psrc := VecInit(io.fromDispatch(i).bits.psrc.take(params.numSrc))