bump difftest and fix Makefile for VCS support

Makefile

@@ -81,6 +81,7 @@ $(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
 		--infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf  \
 		--gen-mem-verilog full --num-cores $(NUM_CORES)             \
 		$(SIM_ARGS)
+	sed -i -e 's/_\(aw\|ar\|w\|r\|b\)_\(\|bits_\)/_\1/g' $@
 	@git log -n 1 >> .__head__
 	@git diff >> .__diff__
 	@sed -i 's/^/\/\// ' .__head__
@@ -121,4 +122,3 @@ simv:
 	$(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES)
 
 .PHONY: verilog sim-verilog emu clean help init bump bsp $(REF_SO)
-

difftest @ 334f9833

-Subproject commit fb79ce2b81dc816d1930854ef94d96e42526a47c
+Subproject commit 334f98335db6af0cbb582326aa197d7c941f365b

src/test/scala/top/SimTop.scala

@@ -35,6 +35,9 @@ class SimTop(implicit p: Parameters) extends Module {
 
   val l_soc = LazyModule(new XSTop())
   val soc = Module(l_soc.module)
+  // Don't allow the top-level signals to be optimized out,
+  // so that we can re-use this SimTop for any generated Verilog RTL.
+  dontTouch(soc.io)
 
   l_soc.module.dma <> 0.U.asTypeOf(l_soc.module.dma)