readme: update new information and sync zh/en version (#1494)

* readme: update dir structure description and sync en/zh readme

* readme: update fig of nanhu-arch

* readme: update docs information

* readme: fix md format

README.md

@@ -4,14 +4,15 @@ XiangShan (香山) is an open-source high-performance RISC-V processor project.
 
 中文说明[在此](readme.zh-cn.md)。
 
-Copyright 2020-2021 by Institute of Computing Technology, Chinese Academy of Sciences.
+Copyright 2020-2022 by Institute of Computing Technology, Chinese Academy of Sciences.
 
-Copyright 2020-2021 by Peng Cheng Laboratory.
+Copyright 2020-2022 by Peng Cheng Laboratory.
 
 ## Docs and slides
-We gave 20+ presentations on RISC-V World Conference China 2021. XiangShan tutorial was held at the same place. Our slides for RVWC2021 have been updated on [our doc repo](https://github.com/OpenXiangShan/XiangShan-doc) (in Chinese).
 
-我们在2021年RISC-V中国峰会的报告已经更新到[这里](https://github.com/OpenXiangShan/XiangShan-doc)。文档和相关信息也将持续更新到相同的仓库。
+[XiangShan-doc](https://github.com/OpenXiangShan/XiangShan-doc) is our official documentation repository. It contains design spec., technical slides, tutorial and more.
+
+* Micro-architecture documentation of XiangShan has been published. Please check out https://xiangshan-doc.readthedocs.io
 
 ## Follow us
 
@@ -29,9 +30,9 @@ You can contact us through [our mail list](mailto:xiangshan-all@ict.ac.cn). All
 
 The first stable micro-architecture of XiangShan is called Yanqihu (雁栖湖) on this [branch](https://github.com/OpenXiangShan/XiangShan/tree/yanqihu), which has been developed since June 2020. The current version of XiangShan, also known as Nanhu (南湖), is still under development on the master branch.
 
-The micro-architecture overview is shown below.
+The micro-architecture overview of Nanhu (南湖) is shown below.
 
-![xs-arch-single](images/xs-arch-simple.svg)
+![xs-arch-nanhu](images/xs-arch-nanhu.svg)
 
 
 
@@ -41,18 +42,19 @@ Some of the key directories are shown below.
 
 ```
 .
-├── ready-to-run           # pre-built simulation images
+├── src
+│   └── main/scala         # design files
+│       ├── device         # virtual device for simulation
+│       ├── system         # SoC wrapper
+│       ├── top            # top module
+│       ├── utils          # utilization code
+│       ├── xiangshan      # main design code
+│       └── xstransforms   # some useful firrtl transforms
 ├── scripts                # scripts for agile development
-└── src
-    ├── test               # test files (including diff-test, module-test, etc.)
-    └── main/scala         # design files
-        ├── device         # virtual device for simulation
-        ├── difftest       # diff-test chisel interface
-        ├── system         # SoC wrapper
-        ├── top            # top module
-        ├── utils          # utilization code
-        ├── xiangshan      # main design code
-        └── xstransforms   # some useful firrtl transforms
+├── fudian                 # floating unit submodule of XiangShan
+├── huancun                # L2/L3 cache submodule of XiangShan
+├── difftest               # difftest co-simulation framework
+└── ready-to-run           # pre-built simulation images
 ```
 
 ## IDE Support
@@ -110,7 +112,7 @@ In the development of XiangShan, some sub-modules from the open-source community
 | Sub-module         | Source                                                       | Detail                                                       |
 | ------------------ | ------------------------------------------------------------ | ------------------------------------------------------------ |
 | L2 Cache/LLC       | [Sifive block-inclusivecache](https://github.com/ucb-bar/block-inclusivecache-sifive) | Our new L2/L3 design are inspired by Sifive's `block-inclusivecache`. |
-| Diplomacy/TileLink | [Rocket-chip](https://github.com/chipsalliance/rocket-chip)  | We reused the diplomacy framework and TileLink utility that exist in rocket-chip to negotiate bus. |
+| Diplomacy/TileLink | [Rocket-chip](https://github.com/chipsalliance/rocket-chip)  | We reused the Diplomacy framework and TileLink utility that exist in rocket-chip to negotiate bus. |
 
 We are grateful for the support of the open-source community and encourage other open-source projects to reuse our code within the scope of the [license](LICENSE).
 

readme.zh-cn.md

 # 香山
 
-香山是一款开源的高性能 RISC-V 处理器。采用 Chisel 硬件设计语言开发，支持 RV64GC 指令集。
+香山（XiangShan）是一款开源的高性能 RISC-V 处理器。
 
-详细文档将在未来放出。
 English Readme is [here](README.md).
 
-©2020-2021 中国科学院计算技术研究所版权所有。
+©2020-2022 中国科学院计算技术研究所版权所有
+
+©2020-2022 鹏城实验室版权所有
 
 ## 文档和报告
 
-在 2021 年 6 月的 RISC-V 中国峰会上，我们给出了超过 20 个技术报告。报告已经更新到[我们的文档仓库](https://github.com/OpenXiangShan/XiangShan-doc)。
+[XiangShan-doc](https://github.com/OpenXiangShan/XiangShan-doc) 是我们的官方文档仓库，其中包含了设计文档、技术报告、使用教程等内容。
 
-更多的文档也将持续更新到相同的仓库。
+* 香山微结构文档已经发布，欢迎访问 https://xiangshan-doc.readthedocs.io
 
 ## 关注我们
 
@@ -29,8 +30,8 @@ Weibo/微博：[香山开源处理器](https://weibo.com/u/7706264932)
 
 自 2020 年 6 月开始开发的[雁栖湖](https://github.com/OpenXiangShan/XiangShan/tree/yanqihu)为香山处理器的首个稳定的微架构。目前版本的香山（即南湖）正在 master 分支上不断开发中。
 
-微架构概览：
-![xs-arch-single](images/xs-arch-simple.svg)
+南湖微架构概览：
+![xs-arch-nanhu](images/xs-arch-nanhu.svg)
 
 ## 目录概览
 
@@ -38,22 +39,34 @@ Weibo/微博：[香山开源处理器](https://weibo.com/u/7706264932)
 
 ```
 .
-├── fpga                   # 支持的 FPGA 开发板、用于构建 Vivado 项目的文件
-├── read-to-run            # 预建的仿真镜像文件
+├── src
+│   └── main/scala         # 设计文件
+│       ├── device         # 用于仿真的虚拟设备
+│       ├── system         # SoC 封装
+│       ├── top            # 顶层模块
+│       ├── utils          # 复用封装
+│       ├── xiangshan      # 主体设计代码
+│       └── xstransforms   # 一些实用的 firrtl 变换代码
 ├── scripts                # 用于敏捷开发的脚本文件
-└── src
-    ├── test               # 测试文件（包括差异测试（diff-test）和模块测试（module-test） 等）
-    └── main/scala         # 设计文件
-        ├── bus/tilelink   # tilelink 实用工具
-        ├── device         # 用于仿真的虚拟设备
-        ├── difftest       # chisel 差异测试接口
-        ├── system         # SoC 封装
-        ├── top            # 顶层模块
-        ├── utils          # 复用封装
-        ├── xiangshan      # 主体设计代码
-        └── xstransforms   # 一些实用的 firrtl 变换代码
+├── fudian                 # 香山浮点子模块
+├── huancun                # 香山 L2/L3 缓存子模块
+├── difftest               # 香山协同仿真框架
+└── read-to-run            # 预建的仿真镜像文件
+```
+
+## IDE 支持
+
+### bsp
+```
+make bsp
 ```
 
+### IDEA
+```
+make idea
+```
+
+
 ## 生成 Verilog
 
 * 运行 `make verilog` 以生成 verilog 代码。输出文件为 `build/XSTop.v`。
@@ -83,14 +96,17 @@ make emu CONFIG=MinimalConfig EMU_THREADS=2 -j10
 ./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so
 ```
 
+## 错误排除指南
+
+[Troubleshooting Guide](https://github.com/OpenXiangShan/XiangShan/wiki/Troubleshooting-Guide)
+
 ## 致谢
 
 在香山的开发过程中，我们采用了来自开源社区的子模块。具体情况如下：
 
 | 子模块         | 来源                                                       | 详细用途                                                       |
 | ------------------ | ------------------------------------------------------------ | ------------------------------------------------------------ |
-| L2 Cache/LLC       | [Sifive block-inclusivecache](https://github.com/ucb-bar/block-inclusivecache-sifive) | 我们增强了原模块的功能和时序，最终使之能胜任 L2/LLC 任务的缓存生成器 |
-| Diplomacy/TileLink | [Rocket-chip](https://github.com/chipsalliance/rocket-chip)  | 我们复用了来自 rocket-chip 的外接框架和链接，来调度总线 |
-| FPU                | [Berkeley hardfloat](https://github.com/ucb-bar/berkeley-hardfloat) | 我们使用了 Barkeley-hardfloat 作为浮点运算器并为之设计了 SRT-4 除法/开方运算单元。此外我们分割了 FMA 流水线以优化时序 |
+| L2 Cache/LLC       | [Sifive block-inclusivecache](https://github.com/ucb-bar/block-inclusivecache-sifive) | 我们的新 L2/L3 缓存设计受到了 Sifive `block-inclusivecache` 的启发. |
+| Diplomacy/TileLink | [Rocket-chip](https://github.com/chipsalliance/rocket-chip)  | 我们复用了来自 rocket-chip 的 Diplomacy 框架和 Tilelink 工具，来协商总线. |
 
-我们深深地感谢来自开源社区的支持，我们也鼓励其他开源项目在[木兰宽松许可证](LICENSE)的范围下复用我们的代码。:)
+我们深深地感谢来自开源社区的支持，我们也鼓励其他开源项目在[木兰宽松许可证](LICENSE)的范围下复用我们的代码。