arm_arch_timer.c 35.3 KB
Newer Older
1 2 3 4 5 6 7 8 9 10
/*
 *  linux/drivers/clocksource/arm_arch_timer.c
 *
 *  Copyright (C) 2011 ARM Ltd.
 *  All Rights Reserved
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
11 12 13

#define pr_fmt(fmt)	"arm_arch_timer: " fmt

14 15 16 17 18
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/device.h>
#include <linux/smp.h>
#include <linux/cpu.h>
19
#include <linux/cpu_pm.h>
20
#include <linux/clockchips.h>
21
#include <linux/clocksource.h>
22 23
#include <linux/interrupt.h>
#include <linux/of_irq.h>
24
#include <linux/of_address.h>
25
#include <linux/io.h>
26
#include <linux/slab.h>
27
#include <linux/sched/clock.h>
28
#include <linux/sched_clock.h>
29
#include <linux/acpi.h>
30 31

#include <asm/arch_timer.h>
32
#include <asm/virt.h>
33 34 35

#include <clocksource/arm_arch_timer.h>

36 37 38
#undef pr_fmt
#define pr_fmt(fmt) "arch_timer: " fmt

39 40 41
#define CNTTIDR		0x08
#define CNTTIDR_VIRT(n)	(BIT(1) << ((n) * 4))

42 43 44 45 46 47 48 49
#define CNTACR(n)	(0x40 + ((n) * 4))
#define CNTACR_RPCT	BIT(0)
#define CNTACR_RVCT	BIT(1)
#define CNTACR_RFRQ	BIT(2)
#define CNTACR_RVOFF	BIT(3)
#define CNTACR_RWVT	BIT(4)
#define CNTACR_RWPT	BIT(5)

50 51 52 53 54 55 56 57
#define CNTVCT_LO	0x08
#define CNTVCT_HI	0x0c
#define CNTFRQ		0x10
#define CNTP_TVAL	0x28
#define CNTP_CTL	0x2c
#define CNTV_TVAL	0x38
#define CNTV_CTL	0x3c

58 59
#define ARCH_TIMER_TYPE_CP15		BIT(0)
#define ARCH_TIMER_TYPE_MEM		BIT(1)
60 61 62 63 64 65 66 67 68 69 70
static unsigned arch_timers_present __initdata;

static void __iomem *arch_counter_base;

struct arch_timer {
	void __iomem *base;
	struct clock_event_device evt;
};

#define to_arch_timer(e) container_of(e, struct arch_timer, evt)

71 72
static u32 arch_timer_rate;

73 74 75 76 77 78
enum arch_timer_ppi_nr {
	ARCH_TIMER_PHYS_SECURE_PPI,
	ARCH_TIMER_PHYS_NONSECURE_PPI,
	ARCH_TIMER_VIRT_PPI,
	ARCH_TIMER_HYP_PPI,
	ARCH_TIMER_MAX_TIMER_PPI
79 80
};

81
static int arch_timer_ppi[ARCH_TIMER_MAX_TIMER_PPI];
82 83 84

static struct clock_event_device __percpu *arch_timer_evt;

85
static enum arch_timer_ppi_nr arch_timer_uses_ppi = ARCH_TIMER_VIRT_PPI;
86
static bool arch_timer_c3stop;
87
static bool arch_timer_mem_use_virtual;
88
static bool arch_counter_suspend_stop;
89
static bool vdso_default = true;
90

91 92 93 94 95 96 97 98
static bool evtstrm_enable = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM);

static int __init early_evtstrm_cfg(char *buf)
{
	return strtobool(buf, &evtstrm_enable);
}
early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);

99 100 101 102
/*
 * Architected system timer support.
 */

103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164
static __always_inline
void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
			  struct clock_event_device *clk)
{
	if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
		struct arch_timer *timer = to_arch_timer(clk);
		switch (reg) {
		case ARCH_TIMER_REG_CTRL:
			writel_relaxed(val, timer->base + CNTP_CTL);
			break;
		case ARCH_TIMER_REG_TVAL:
			writel_relaxed(val, timer->base + CNTP_TVAL);
			break;
		}
	} else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
		struct arch_timer *timer = to_arch_timer(clk);
		switch (reg) {
		case ARCH_TIMER_REG_CTRL:
			writel_relaxed(val, timer->base + CNTV_CTL);
			break;
		case ARCH_TIMER_REG_TVAL:
			writel_relaxed(val, timer->base + CNTV_TVAL);
			break;
		}
	} else {
		arch_timer_reg_write_cp15(access, reg, val);
	}
}

static __always_inline
u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
			struct clock_event_device *clk)
{
	u32 val;

	if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
		struct arch_timer *timer = to_arch_timer(clk);
		switch (reg) {
		case ARCH_TIMER_REG_CTRL:
			val = readl_relaxed(timer->base + CNTP_CTL);
			break;
		case ARCH_TIMER_REG_TVAL:
			val = readl_relaxed(timer->base + CNTP_TVAL);
			break;
		}
	} else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
		struct arch_timer *timer = to_arch_timer(clk);
		switch (reg) {
		case ARCH_TIMER_REG_CTRL:
			val = readl_relaxed(timer->base + CNTV_CTL);
			break;
		case ARCH_TIMER_REG_TVAL:
			val = readl_relaxed(timer->base + CNTV_TVAL);
			break;
		}
	} else {
		val = arch_timer_reg_read_cp15(access, reg);
	}

	return val;
}

165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195
/*
 * Default to cp15 based access because arm64 uses this function for
 * sched_clock() before DT is probed and the cp15 method is guaranteed
 * to exist on arm64. arm doesn't use this before DT is probed so even
 * if we don't have the cp15 accessors we won't have a problem.
 */
u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct;

static u64 arch_counter_read(struct clocksource *cs)
{
	return arch_timer_read_counter();
}

static u64 arch_counter_read_cc(const struct cyclecounter *cc)
{
	return arch_timer_read_counter();
}

static struct clocksource clocksource_counter = {
	.name	= "arch_sys_counter",
	.rating	= 400,
	.read	= arch_counter_read,
	.mask	= CLOCKSOURCE_MASK(56),
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
};

static struct cyclecounter cyclecounter __ro_after_init = {
	.read	= arch_counter_read_cc,
	.mask	= CLOCKSOURCE_MASK(56),
};

196 197 198 199 200 201
struct ate_acpi_oem_info {
	char oem_id[ACPI_OEM_ID_SIZE + 1];
	char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
	u32 oem_revision;
};

202
#ifdef CONFIG_FSL_ERRATUM_A008585
203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221
/*
 * The number of retries is an arbitrary value well beyond the highest number
 * of iterations the loop has been observed to take.
 */
#define __fsl_a008585_read_reg(reg) ({			\
	u64 _old, _new;					\
	int _retries = 200;				\
							\
	do {						\
		_old = read_sysreg(reg);		\
		_new = read_sysreg(reg);		\
		_retries--;				\
	} while (unlikely(_old != _new) && _retries);	\
							\
	WARN_ON_ONCE(!_retries);			\
	_new;						\
})

static u32 notrace fsl_a008585_read_cntp_tval_el0(void)
222 223 224 225
{
	return __fsl_a008585_read_reg(cntp_tval_el0);
}

226
static u32 notrace fsl_a008585_read_cntv_tval_el0(void)
227 228 229 230
{
	return __fsl_a008585_read_reg(cntv_tval_el0);
}

231
static u64 notrace fsl_a008585_read_cntvct_el0(void)
232 233 234
{
	return __fsl_a008585_read_reg(cntvct_el0);
}
235 236
#endif

237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275
#ifdef CONFIG_HISILICON_ERRATUM_161010101
/*
 * Verify whether the value of the second read is larger than the first by
 * less than 32 is the only way to confirm the value is correct, so clear the
 * lower 5 bits to check whether the difference is greater than 32 or not.
 * Theoretically the erratum should not occur more than twice in succession
 * when reading the system counter, but it is possible that some interrupts
 * may lead to more than twice read errors, triggering the warning, so setting
 * the number of retries far beyond the number of iterations the loop has been
 * observed to take.
 */
#define __hisi_161010101_read_reg(reg) ({				\
	u64 _old, _new;						\
	int _retries = 50;					\
								\
	do {							\
		_old = read_sysreg(reg);			\
		_new = read_sysreg(reg);			\
		_retries--;					\
	} while (unlikely((_new - _old) >> 5) && _retries);	\
								\
	WARN_ON_ONCE(!_retries);				\
	_new;							\
})

static u32 notrace hisi_161010101_read_cntp_tval_el0(void)
{
	return __hisi_161010101_read_reg(cntp_tval_el0);
}

static u32 notrace hisi_161010101_read_cntv_tval_el0(void)
{
	return __hisi_161010101_read_reg(cntv_tval_el0);
}

static u64 notrace hisi_161010101_read_cntvct_el0(void)
{
	return __hisi_161010101_read_reg(cntvct_el0);
}
276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298

static struct ate_acpi_oem_info hisi_161010101_oem_info[] = {
	/*
	 * Note that trailing spaces are required to properly match
	 * the OEM table information.
	 */
	{
		.oem_id		= "HISI  ",
		.oem_table_id	= "HIP05   ",
		.oem_revision	= 0,
	},
	{
		.oem_id		= "HISI  ",
		.oem_table_id	= "HIP06   ",
		.oem_revision	= 0,
	},
	{
		.oem_id		= "HISI  ",
		.oem_table_id	= "HIP07   ",
		.oem_revision	= 0,
	},
	{ /* Sentinel indicating the end of the OEM array */ },
};
299 300
#endif

301 302 303 304 305 306 307 308 309 310 311
#ifdef CONFIG_ARM64_ERRATUM_858921
static u64 notrace arm64_858921_read_cntvct_el0(void)
{
	u64 old, new;

	old = read_sysreg(cntvct_el0);
	new = read_sysreg(cntvct_el0);
	return (((old ^ new) >> 32) & 1) ? old : new;
}
#endif

312
#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
313 314
DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *,
	       timer_unstable_counter_workaround);
315 316 317 318 319
EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);

DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled);
EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled);

320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351
static void erratum_set_next_event_tval_generic(const int access, unsigned long evt,
						struct clock_event_device *clk)
{
	unsigned long ctrl;
	u64 cval = evt + arch_counter_get_cntvct();

	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
	ctrl |= ARCH_TIMER_CTRL_ENABLE;
	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;

	if (access == ARCH_TIMER_PHYS_ACCESS)
		write_sysreg(cval, cntp_cval_el0);
	else
		write_sysreg(cval, cntv_cval_el0);

	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
}

static int erratum_set_next_event_tval_virt(unsigned long evt,
					    struct clock_event_device *clk)
{
	erratum_set_next_event_tval_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk);
	return 0;
}

static int erratum_set_next_event_tval_phys(unsigned long evt,
					    struct clock_event_device *clk)
{
	erratum_set_next_event_tval_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk);
	return 0;
}

352 353 354
static const struct arch_timer_erratum_workaround ool_workarounds[] = {
#ifdef CONFIG_FSL_ERRATUM_A008585
	{
355
		.match_type = ate_match_dt,
356
		.id = "fsl,erratum-a008585",
357
		.desc = "Freescale erratum a005858",
358 359 360
		.read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0,
		.read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0,
		.read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
361 362
		.set_next_event_phys = erratum_set_next_event_tval_phys,
		.set_next_event_virt = erratum_set_next_event_tval_virt,
363 364
	},
#endif
365 366
#ifdef CONFIG_HISILICON_ERRATUM_161010101
	{
367
		.match_type = ate_match_dt,
368
		.id = "hisilicon,erratum-161010101",
369
		.desc = "HiSilicon erratum 161010101",
370 371 372
		.read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
		.read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
		.read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
373 374
		.set_next_event_phys = erratum_set_next_event_tval_phys,
		.set_next_event_virt = erratum_set_next_event_tval_virt,
375 376 377 378 379 380 381 382 383 384
	},
	{
		.match_type = ate_match_acpi_oem_info,
		.id = hisi_161010101_oem_info,
		.desc = "HiSilicon erratum 161010101",
		.read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
		.read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
		.read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
		.set_next_event_phys = erratum_set_next_event_tval_phys,
		.set_next_event_virt = erratum_set_next_event_tval_virt,
385 386
	},
#endif
387 388 389 390 391 392 393 394
#ifdef CONFIG_ARM64_ERRATUM_858921
	{
		.match_type = ate_match_local_cap_id,
		.id = (void *)ARM64_WORKAROUND_858921,
		.desc = "ARM erratum 858921",
		.read_cntvct_el0 = arm64_858921_read_cntvct_el0,
	},
#endif
395
};
396 397 398 399 400 401 402 403 404 405 406 407 408

typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,
			       const void *);

static
bool arch_timer_check_dt_erratum(const struct arch_timer_erratum_workaround *wa,
				 const void *arg)
{
	const struct device_node *np = arg;

	return of_property_read_bool(np, wa->id);
}

409 410 411 412 413 414 415
static
bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround *wa,
					const void *arg)
{
	return this_cpu_has_cap((uintptr_t)wa->id);
}

416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437

static
bool arch_timer_check_acpi_oem_erratum(const struct arch_timer_erratum_workaround *wa,
				       const void *arg)
{
	static const struct ate_acpi_oem_info empty_oem_info = {};
	const struct ate_acpi_oem_info *info = wa->id;
	const struct acpi_table_header *table = arg;

	/* Iterate over the ACPI OEM info array, looking for a match */
	while (memcmp(info, &empty_oem_info, sizeof(*info))) {
		if (!memcmp(info->oem_id, table->oem_id, ACPI_OEM_ID_SIZE) &&
		    !memcmp(info->oem_table_id, table->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) &&
		    info->oem_revision == table->oem_revision)
			return true;

		info++;
	}

	return false;
}

438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456
static const struct arch_timer_erratum_workaround *
arch_timer_iterate_errata(enum arch_timer_erratum_match_type type,
			  ate_match_fn_t match_fn,
			  void *arg)
{
	int i;

	for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) {
		if (ool_workarounds[i].match_type != type)
			continue;

		if (match_fn(&ool_workarounds[i], arg))
			return &ool_workarounds[i];
	}

	return NULL;
}

static
457 458
void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa,
				  bool local)
459
{
460 461 462 463 464 465 466 467 468
	int i;

	if (local) {
		__this_cpu_write(timer_unstable_counter_workaround, wa);
	} else {
		for_each_possible_cpu(i)
			per_cpu(timer_unstable_counter_workaround, i) = wa;
	}

469
	static_branch_enable(&arch_timer_read_ool_enabled);
470 471 472 473 474 475 476 477 478 479 480

	/*
	 * Don't use the vdso fastpath if errata require using the
	 * out-of-line counter accessor. We may change our mind pretty
	 * late in the game (with a per-CPU erratum, for example), so
	 * change both the default value and the vdso itself.
	 */
	if (wa->read_cntvct_el0) {
		clocksource_counter.archdata.vdso_direct = false;
		vdso_default = false;
	}
481 482 483 484 485 486 487
}

static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type type,
					    void *arg)
{
	const struct arch_timer_erratum_workaround *wa;
	ate_match_fn_t match_fn = NULL;
488
	bool local = false;
489 490 491 492 493

	switch (type) {
	case ate_match_dt:
		match_fn = arch_timer_check_dt_erratum;
		break;
494 495 496 497
	case ate_match_local_cap_id:
		match_fn = arch_timer_check_local_cap_erratum;
		local = true;
		break;
498 499 500
	case ate_match_acpi_oem_info:
		match_fn = arch_timer_check_acpi_oem_erratum;
		break;
501 502 503 504 505 506 507 508 509
	default:
		WARN_ON(1);
		return;
	}

	wa = arch_timer_iterate_errata(type, match_fn, arg);
	if (!wa)
		return;

510
	if (needs_unstable_timer_counter_workaround()) {
511 512 513
		const struct arch_timer_erratum_workaround *__wa;
		__wa = __this_cpu_read(timer_unstable_counter_workaround);
		if (__wa && wa != __wa)
514
			pr_warn("Can't enable workaround for %s (clashes with %s\n)",
515 516 517 518
				wa->desc, __wa->desc);

		if (__wa)
			return;
519 520
	}

521
	arch_timer_enable_workaround(wa, local);
522 523
	pr_info("Enabling %s workaround for %s\n",
		local ? "local" : "global", wa->desc);
524 525
}

526 527 528
#define erratum_handler(fn, r, ...)					\
({									\
	bool __val;							\
529 530 531 532 533 534 535 536 537
	if (needs_unstable_timer_counter_workaround()) {		\
		const struct arch_timer_erratum_workaround *__wa;	\
		__wa = __this_cpu_read(timer_unstable_counter_workaround); \
		if (__wa && __wa->fn) {					\
			r = __wa->fn(__VA_ARGS__);			\
			__val = true;					\
		} else {						\
			__val = false;					\
		}							\
538 539 540 541 542 543
	} else {							\
		__val = false;						\
	}								\
	__val;								\
})

544 545 546 547 548 549 550
static bool arch_timer_this_cpu_has_cntvct_wa(void)
{
	const struct arch_timer_erratum_workaround *wa;

	wa = __this_cpu_read(timer_unstable_counter_workaround);
	return wa && wa->read_cntvct_el0;
}
551 552
#else
#define arch_timer_check_ool_workaround(t,a)		do { } while(0)
553 554
#define erratum_set_next_event_tval_virt(...)		({BUG(); 0;})
#define erratum_set_next_event_tval_phys(...)		({BUG(); 0;})
555
#define erratum_handler(fn, r, ...)			({false;})
556
#define arch_timer_this_cpu_has_cntvct_wa()		({false;})
557
#endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
558

559
static __always_inline irqreturn_t timer_handler(const int access,
560 561 562
					struct clock_event_device *evt)
{
	unsigned long ctrl;
563

564
	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, evt);
565 566
	if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
		ctrl |= ARCH_TIMER_CTRL_IT_MASK;
567
		arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, evt);
568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588
		evt->event_handler(evt);
		return IRQ_HANDLED;
	}

	return IRQ_NONE;
}

static irqreturn_t arch_timer_handler_virt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	return timer_handler(ARCH_TIMER_VIRT_ACCESS, evt);
}

static irqreturn_t arch_timer_handler_phys(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	return timer_handler(ARCH_TIMER_PHYS_ACCESS, evt);
}

589 590 591 592 593 594 595 596 597 598 599 600 601 602
static irqreturn_t arch_timer_handler_phys_mem(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	return timer_handler(ARCH_TIMER_MEM_PHYS_ACCESS, evt);
}

static irqreturn_t arch_timer_handler_virt_mem(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	return timer_handler(ARCH_TIMER_MEM_VIRT_ACCESS, evt);
}

603 604
static __always_inline int timer_shutdown(const int access,
					  struct clock_event_device *clk)
605 606
{
	unsigned long ctrl;
607 608 609 610 611 612

	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
	ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);

	return 0;
613 614
}

615
static int arch_timer_shutdown_virt(struct clock_event_device *clk)
616
{
617
	return timer_shutdown(ARCH_TIMER_VIRT_ACCESS, clk);
618 619
}

620
static int arch_timer_shutdown_phys(struct clock_event_device *clk)
621
{
622
	return timer_shutdown(ARCH_TIMER_PHYS_ACCESS, clk);
623 624
}

625
static int arch_timer_shutdown_virt_mem(struct clock_event_device *clk)
626
{
627
	return timer_shutdown(ARCH_TIMER_MEM_VIRT_ACCESS, clk);
628 629
}

630
static int arch_timer_shutdown_phys_mem(struct clock_event_device *clk)
631
{
632
	return timer_shutdown(ARCH_TIMER_MEM_PHYS_ACCESS, clk);
633 634
}

635
static __always_inline void set_next_event(const int access, unsigned long evt,
636
					   struct clock_event_device *clk)
637 638
{
	unsigned long ctrl;
639
	ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
640 641
	ctrl |= ARCH_TIMER_CTRL_ENABLE;
	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
642 643
	arch_timer_reg_write(access, ARCH_TIMER_REG_TVAL, evt, clk);
	arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
644 645 646
}

static int arch_timer_set_next_event_virt(unsigned long evt,
647
					  struct clock_event_device *clk)
648
{
649 650 651 652
	int ret;

	if (erratum_handler(set_next_event_virt, ret, evt, clk))
		return ret;
653

654
	set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
655 656 657 658
	return 0;
}

static int arch_timer_set_next_event_phys(unsigned long evt,
659
					  struct clock_event_device *clk)
660
{
661 662 663 664
	int ret;

	if (erratum_handler(set_next_event_phys, ret, evt, clk))
		return ret;
665

666
	set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
667 668 669
	return 0;
}

670 671
static int arch_timer_set_next_event_virt_mem(unsigned long evt,
					      struct clock_event_device *clk)
672
{
673 674 675 676 677 678 679 680 681 682 683
	set_next_event(ARCH_TIMER_MEM_VIRT_ACCESS, evt, clk);
	return 0;
}

static int arch_timer_set_next_event_phys_mem(unsigned long evt,
					      struct clock_event_device *clk)
{
	set_next_event(ARCH_TIMER_MEM_PHYS_ACCESS, evt, clk);
	return 0;
}

684 685
static void __arch_timer_setup(unsigned type,
			       struct clock_event_device *clk)
686 687 688
{
	clk->features = CLOCK_EVT_FEAT_ONESHOT;

689
	if (type == ARCH_TIMER_TYPE_CP15) {
690 691
		if (arch_timer_c3stop)
			clk->features |= CLOCK_EVT_FEAT_C3STOP;
692 693 694
		clk->name = "arch_sys_timer";
		clk->rating = 450;
		clk->cpumask = cpumask_of(smp_processor_id());
695 696
		clk->irq = arch_timer_ppi[arch_timer_uses_ppi];
		switch (arch_timer_uses_ppi) {
697
		case ARCH_TIMER_VIRT_PPI:
698
			clk->set_state_shutdown = arch_timer_shutdown_virt;
699
			clk->set_state_oneshot_stopped = arch_timer_shutdown_virt;
700
			clk->set_next_event = arch_timer_set_next_event_virt;
701
			break;
702 703 704
		case ARCH_TIMER_PHYS_SECURE_PPI:
		case ARCH_TIMER_PHYS_NONSECURE_PPI:
		case ARCH_TIMER_HYP_PPI:
705
			clk->set_state_shutdown = arch_timer_shutdown_phys;
706
			clk->set_state_oneshot_stopped = arch_timer_shutdown_phys;
707
			clk->set_next_event = arch_timer_set_next_event_phys;
708 709 710
			break;
		default:
			BUG();
711
		}
712

713
		arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL);
714
	} else {
715
		clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
716 717 718 719
		clk->name = "arch_mem_timer";
		clk->rating = 400;
		clk->cpumask = cpu_all_mask;
		if (arch_timer_mem_use_virtual) {
720
			clk->set_state_shutdown = arch_timer_shutdown_virt_mem;
721
			clk->set_state_oneshot_stopped = arch_timer_shutdown_virt_mem;
722 723 724
			clk->set_next_event =
				arch_timer_set_next_event_virt_mem;
		} else {
725
			clk->set_state_shutdown = arch_timer_shutdown_phys_mem;
726
			clk->set_state_oneshot_stopped = arch_timer_shutdown_phys_mem;
727 728 729
			clk->set_next_event =
				arch_timer_set_next_event_phys_mem;
		}
730 731
	}

732
	clk->set_state_shutdown(clk);
733

734 735
	clockevents_config_and_register(clk, arch_timer_rate, 0xf, 0x7fffffff);
}
736

737 738 739 740 741 742 743 744 745 746 747 748 749 750 751
static void arch_timer_evtstrm_enable(int divider)
{
	u32 cntkctl = arch_timer_get_cntkctl();

	cntkctl &= ~ARCH_TIMER_EVT_TRIGGER_MASK;
	/* Set the divider and enable virtual event stream */
	cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT)
			| ARCH_TIMER_VIRT_EVT_EN;
	arch_timer_set_cntkctl(cntkctl);
	elf_hwcap |= HWCAP_EVTSTRM;
#ifdef CONFIG_COMPAT
	compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM;
#endif
}

752 753 754 755 756 757 758 759 760 761 762 763 764
static void arch_timer_configure_evtstream(void)
{
	int evt_stream_div, pos;

	/* Find the closest power of two to the divisor */
	evt_stream_div = arch_timer_rate / ARCH_TIMER_EVT_STREAM_FREQ;
	pos = fls(evt_stream_div);
	if (pos > 1 && !(evt_stream_div & (1 << (pos - 2))))
		pos--;
	/* enable event stream */
	arch_timer_evtstrm_enable(min(pos, 15));
}

765 766 767 768
static void arch_counter_set_user_access(void)
{
	u32 cntkctl = arch_timer_get_cntkctl();

769
	/* Disable user access to the timers and both counters */
770 771 772
	/* Also disable virtual event stream */
	cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
			| ARCH_TIMER_USR_VT_ACCESS_EN
773
		        | ARCH_TIMER_USR_VCT_ACCESS_EN
774 775 776
			| ARCH_TIMER_VIRT_EVT_EN
			| ARCH_TIMER_USR_PCT_ACCESS_EN);

777 778 779 780 781 782 783 784 785
	/*
	 * Enable user access to the virtual counter if it doesn't
	 * need to be workaround. The vdso may have been already
	 * disabled though.
	 */
	if (arch_timer_this_cpu_has_cntvct_wa())
		pr_info("CPU%d: Trapping CNTVCT access\n", smp_processor_id());
	else
		cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
786 787 788 789

	arch_timer_set_cntkctl(cntkctl);
}

790 791
static bool arch_timer_has_nonsecure_ppi(void)
{
792 793
	return (arch_timer_uses_ppi == ARCH_TIMER_PHYS_SECURE_PPI &&
		arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
794 795
}

796 797 798 799 800 801 802 803 804 805 806 807 808
static u32 check_ppi_trigger(int irq)
{
	u32 flags = irq_get_trigger_type(irq);

	if (flags != IRQF_TRIGGER_HIGH && flags != IRQF_TRIGGER_LOW) {
		pr_warn("WARNING: Invalid trigger for IRQ%d, assuming level low\n", irq);
		pr_warn("WARNING: Please fix your firmware\n");
		flags = IRQF_TRIGGER_LOW;
	}

	return flags;
}

809
static int arch_timer_starting_cpu(unsigned int cpu)
810
{
811
	struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
812
	u32 flags;
813

814
	__arch_timer_setup(ARCH_TIMER_TYPE_CP15, clk);
815

816 817
	flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]);
	enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags);
818

819
	if (arch_timer_has_nonsecure_ppi()) {
820 821 822
		flags = check_ppi_trigger(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
		enable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
				  flags);
823
	}
824 825

	arch_counter_set_user_access();
826
	if (evtstrm_enable)
827
		arch_timer_configure_evtstream();
828 829 830 831

	return 0;
}

832 833
static void
arch_timer_detect_rate(void __iomem *cntbase, struct device_node *np)
834
{
835 836 837
	/* Who has more than one independent system counter? */
	if (arch_timer_rate)
		return;
838

839 840 841 842 843 844
	/*
	 * Try to determine the frequency from the device tree or CNTFRQ,
	 * if ACPI is enabled, get the frequency from CNTFRQ ONLY.
	 */
	if (!acpi_disabled ||
	    of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) {
845 846 847 848
		if (cntbase)
			arch_timer_rate = readl_relaxed(cntbase + CNTFRQ);
		else
			arch_timer_rate = arch_timer_get_cntfrq();
849 850
	}

851 852
	/* Check the timer frequency. */
	if (arch_timer_rate == 0)
853
		pr_warn("frequency not available\n");
854 855 856 857
}

static void arch_timer_banner(unsigned type)
{
858
	pr_info("%s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
859 860 861 862
		type & ARCH_TIMER_TYPE_CP15 ? "cp15" : "",
		type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ?
			" and " : "",
		type & ARCH_TIMER_TYPE_MEM ? "mmio" : "",
863 864
		(unsigned long)arch_timer_rate / 1000000,
		(unsigned long)(arch_timer_rate / 10000) % 100,
865
		type & ARCH_TIMER_TYPE_CP15 ?
866
			(arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) ? "virt" : "phys" :
867
			"",
868 869
		type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ? "/" : "",
		type & ARCH_TIMER_TYPE_MEM ?
870 871
			arch_timer_mem_use_virtual ? "virt" : "phys" :
			"");
872 873 874 875 876 877 878
}

u32 arch_timer_get_rate(void)
{
	return arch_timer_rate;
}

879
static u64 arch_counter_get_cntvct_mem(void)
880
{
881 882 883 884 885 886 887 888 889
	u32 vct_lo, vct_hi, tmp_hi;

	do {
		vct_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
		vct_lo = readl_relaxed(arch_counter_base + CNTVCT_LO);
		tmp_hi = readl_relaxed(arch_counter_base + CNTVCT_HI);
	} while (vct_hi != tmp_hi);

	return ((u64) vct_hi << 32) | vct_lo;
890 891
}

892 893 894 895 896 897
static struct arch_timer_kvm_info arch_timer_kvm_info;

struct arch_timer_kvm_info *arch_timer_get_kvm_info(void)
{
	return &arch_timer_kvm_info;
}
898

899 900 901 902 903
static void __init arch_counter_register(unsigned type)
{
	u64 start_count;

	/* Register the CP15 based counter if we have one */
904
	if (type & ARCH_TIMER_TYPE_CP15) {
905 906
		if (IS_ENABLED(CONFIG_ARM64) ||
		    arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI)
907 908 909
			arch_timer_read_counter = arch_counter_get_cntvct;
		else
			arch_timer_read_counter = arch_counter_get_cntpct;
910

911
		clocksource_counter.archdata.vdso_direct = vdso_default;
912
	} else {
913
		arch_timer_read_counter = arch_counter_get_cntvct_mem;
914 915
	}

916 917
	if (!arch_counter_suspend_stop)
		clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
918 919 920 921
	start_count = arch_timer_read_counter();
	clocksource_register_hz(&clocksource_counter, arch_timer_rate);
	cyclecounter.mult = clocksource_counter.mult;
	cyclecounter.shift = clocksource_counter.shift;
922 923
	timecounter_init(&arch_timer_kvm_info.timecounter,
			 &cyclecounter, start_count);
924 925 926

	/* 56 bits minimum, so we assume worst case rollover */
	sched_clock_register(arch_timer_read_counter, 56, arch_timer_rate);
927 928
}

929
static void arch_timer_stop(struct clock_event_device *clk)
930
{
931
	pr_debug("disable IRQ%d cpu #%d\n", clk->irq, smp_processor_id());
932

933 934
	disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]);
	if (arch_timer_has_nonsecure_ppi())
935
		disable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
936

937
	clk->set_state_shutdown(clk);
938 939
}

940
static int arch_timer_dying_cpu(unsigned int cpu)
941
{
942
	struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
943

944 945
	arch_timer_stop(clk);
	return 0;
946 947
}

948
#ifdef CONFIG_CPU_PM
949
static DEFINE_PER_CPU(unsigned long, saved_cntkctl);
950 951 952 953
static int arch_timer_cpu_pm_notify(struct notifier_block *self,
				    unsigned long action, void *hcpu)
{
	if (action == CPU_PM_ENTER)
954
		__this_cpu_write(saved_cntkctl, arch_timer_get_cntkctl());
955
	else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT)
956
		arch_timer_set_cntkctl(__this_cpu_read(saved_cntkctl));
957 958 959 960 961 962 963 964 965 966 967
	return NOTIFY_OK;
}

static struct notifier_block arch_timer_cpu_pm_notifier = {
	.notifier_call = arch_timer_cpu_pm_notify,
};

static int __init arch_timer_cpu_pm_init(void)
{
	return cpu_pm_register_notifier(&arch_timer_cpu_pm_notifier);
}
968 969 970 971 972 973

static void __init arch_timer_cpu_pm_deinit(void)
{
	WARN_ON(cpu_pm_unregister_notifier(&arch_timer_cpu_pm_notifier));
}

974 975 976 977 978
#else
static int __init arch_timer_cpu_pm_init(void)
{
	return 0;
}
979 980 981 982

static void __init arch_timer_cpu_pm_deinit(void)
{
}
983 984
#endif

985 986 987 988 989 990 991 992 993 994 995
static int __init arch_timer_register(void)
{
	int err;
	int ppi;

	arch_timer_evt = alloc_percpu(struct clock_event_device);
	if (!arch_timer_evt) {
		err = -ENOMEM;
		goto out;
	}

996 997
	ppi = arch_timer_ppi[arch_timer_uses_ppi];
	switch (arch_timer_uses_ppi) {
998
	case ARCH_TIMER_VIRT_PPI:
999 1000
		err = request_percpu_irq(ppi, arch_timer_handler_virt,
					 "arch_timer", arch_timer_evt);
1001
		break;
1002 1003
	case ARCH_TIMER_PHYS_SECURE_PPI:
	case ARCH_TIMER_PHYS_NONSECURE_PPI:
1004 1005
		err = request_percpu_irq(ppi, arch_timer_handler_phys,
					 "arch_timer", arch_timer_evt);
1006 1007
		if (!err && arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]) {
			ppi = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
1008 1009 1010
			err = request_percpu_irq(ppi, arch_timer_handler_phys,
						 "arch_timer", arch_timer_evt);
			if (err)
1011
				free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI],
1012 1013
						arch_timer_evt);
		}
1014
		break;
1015
	case ARCH_TIMER_HYP_PPI:
1016 1017 1018 1019 1020
		err = request_percpu_irq(ppi, arch_timer_handler_phys,
					 "arch_timer", arch_timer_evt);
		break;
	default:
		BUG();
1021 1022 1023
	}

	if (err) {
1024
		pr_err("can't register interrupt %d (%d)\n", ppi, err);
1025 1026 1027
		goto out_free;
	}

1028 1029 1030 1031
	err = arch_timer_cpu_pm_init();
	if (err)
		goto out_unreg_notify;

1032

1033 1034
	/* Register and immediately configure the timer on the boot CPU */
	err = cpuhp_setup_state(CPUHP_AP_ARM_ARCH_TIMER_STARTING,
T
Thomas Gleixner 已提交
1035
				"clockevents/arm/arch_timer:starting",
1036 1037 1038
				arch_timer_starting_cpu, arch_timer_dying_cpu);
	if (err)
		goto out_unreg_cpupm;
1039 1040
	return 0;

1041 1042 1043
out_unreg_cpupm:
	arch_timer_cpu_pm_deinit();

1044
out_unreg_notify:
1045 1046
	free_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], arch_timer_evt);
	if (arch_timer_has_nonsecure_ppi())
1047
		free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
1048 1049 1050 1051 1052 1053 1054 1055
				arch_timer_evt);

out_free:
	free_percpu(arch_timer_evt);
out:
	return err;
}

1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067
static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
{
	int ret;
	irq_handler_t func;
	struct arch_timer *t;

	t = kzalloc(sizeof(*t), GFP_KERNEL);
	if (!t)
		return -ENOMEM;

	t->base = base;
	t->evt.irq = irq;
1068
	__arch_timer_setup(ARCH_TIMER_TYPE_MEM, &t->evt);
1069 1070 1071 1072 1073 1074 1075 1076

	if (arch_timer_mem_use_virtual)
		func = arch_timer_handler_virt_mem;
	else
		func = arch_timer_handler_phys_mem;

	ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt);
	if (ret) {
1077
		pr_err("Failed to request mem timer irq\n");
1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094
		kfree(t);
	}

	return ret;
}

static const struct of_device_id arch_timer_of_match[] __initconst = {
	{ .compatible   = "arm,armv7-timer",    },
	{ .compatible   = "arm,armv8-timer",    },
	{},
};

static const struct of_device_id arch_timer_mem_of_match[] __initconst = {
	{ .compatible   = "arm,armv7-timer-mem", },
	{},
};

1095
static bool __init
1096
arch_timer_needs_probing(int type, const struct of_device_id *matches)
1097 1098
{
	struct device_node *dn;
1099
	bool needs_probing = false;
1100 1101

	dn = of_find_matching_node(NULL, matches);
1102
	if (dn && of_device_is_available(dn) && !(arch_timers_present & type))
1103
		needs_probing = true;
1104 1105
	of_node_put(dn);

1106
	return needs_probing;
1107 1108
}

1109
static int __init arch_timer_common_init(void)
1110
{
1111
	unsigned mask = ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM;
1112 1113 1114

	/* Wait until both nodes are probed if we have two timers */
	if ((arch_timers_present & mask) != mask) {
1115 1116
		if (arch_timer_needs_probing(ARCH_TIMER_TYPE_MEM,
					     arch_timer_mem_of_match))
1117
			return 0;
1118 1119
		if (arch_timer_needs_probing(ARCH_TIMER_TYPE_CP15,
					     arch_timer_of_match))
1120
			return 0;
1121 1122 1123 1124
	}

	arch_timer_banner(arch_timers_present);
	arch_counter_register(arch_timers_present);
1125
	return arch_timer_arch_init();
1126 1127
}

1128
static int __init arch_timer_init(void)
1129
{
1130
	int ret;
1131
	/*
1132 1133 1134 1135
	 * If HYP mode is available, we know that the physical timer
	 * has been configured to be accessible from PL1. Use it, so
	 * that a guest can use the virtual timer instead.
	 *
1136 1137
	 * If no interrupt provided for virtual timer, we'll have to
	 * stick to the physical timer. It'd better be accessible...
1138 1139 1140 1141 1142
	 *
	 * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE
	 * accesses to CNTP_*_EL1 registers are silently redirected to
	 * their CNTHP_*_EL2 counterparts, and use a different PPI
	 * number.
1143
	 */
1144
	if (is_hyp_mode_available() || !arch_timer_ppi[ARCH_TIMER_VIRT_PPI]) {
1145 1146 1147
		bool has_ppi;

		if (is_kernel_in_hyp_mode()) {
1148 1149
			arch_timer_uses_ppi = ARCH_TIMER_HYP_PPI;
			has_ppi = !!arch_timer_ppi[ARCH_TIMER_HYP_PPI];
1150
		} else {
1151 1152 1153
			arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI;
			has_ppi = (!!arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI] ||
				   !!arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
1154
		}
1155

1156
		if (!has_ppi) {
1157
			pr_warn("No interrupt available, giving up\n");
1158
			return -EINVAL;
1159 1160 1161
		}
	}

1162 1163 1164 1165 1166 1167 1168
	ret = arch_timer_register();
	if (ret)
		return ret;

	ret = arch_timer_common_init();
	if (ret)
		return ret;
1169

1170
	arch_timer_kvm_info.virtual_irq = arch_timer_ppi[ARCH_TIMER_VIRT_PPI];
1171

1172
	return 0;
1173
}
1174

1175
static int __init arch_timer_of_init(struct device_node *np)
1176 1177 1178
{
	int i;

1179
	if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
1180
		pr_warn("multiple nodes in dt, skipping\n");
1181
		return 0;
1182 1183
	}

1184
	arch_timers_present |= ARCH_TIMER_TYPE_CP15;
1185
	for (i = ARCH_TIMER_PHYS_SECURE_PPI; i < ARCH_TIMER_MAX_TIMER_PPI; i++)
1186 1187 1188 1189 1190 1191
		arch_timer_ppi[i] = irq_of_parse_and_map(np, i);

	arch_timer_detect_rate(NULL, np);

	arch_timer_c3stop = !of_property_read_bool(np, "always-on");

1192 1193
	/* Check for globally applicable workarounds */
	arch_timer_check_ool_workaround(ate_match_dt, np);
1194

1195 1196 1197 1198 1199 1200
	/*
	 * If we cannot rely on firmware initializing the timer registers then
	 * we should use the physical timers instead.
	 */
	if (IS_ENABLED(CONFIG_ARM) &&
	    of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
1201
		arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI;
1202

1203 1204 1205 1206
	/* On some systems, the counter stops ticking when in suspend. */
	arch_counter_suspend_stop = of_property_read_bool(np,
							 "arm,no-tick-in-suspend");

1207
	return arch_timer_init();
1208
}
1209 1210
CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);
1211

1212
static int __init arch_timer_mem_init(struct device_node *np)
1213 1214 1215
{
	struct device_node *frame, *best_frame = NULL;
	void __iomem *cntctlbase, *base;
1216
	unsigned int irq, ret = -EINVAL;
1217 1218
	u32 cnttidr;

1219
	arch_timers_present |= ARCH_TIMER_TYPE_MEM;
1220 1221
	cntctlbase = of_iomap(np, 0);
	if (!cntctlbase) {
1222
		pr_err("Can't find CNTCTLBase\n");
1223
		return -ENXIO;
1224 1225 1226 1227 1228 1229 1230 1231 1232 1233
	}

	cnttidr = readl_relaxed(cntctlbase + CNTTIDR);

	/*
	 * Try to find a virtual capable frame. Otherwise fall back to a
	 * physical capable frame.
	 */
	for_each_available_child_of_node(np, frame) {
		int n;
1234
		u32 cntacr;
1235 1236

		if (of_property_read_u32(frame, "frame-number", &n)) {
1237
			pr_err("Missing frame-number\n");
1238
			of_node_put(frame);
1239
			goto out;
1240 1241
		}

1242 1243 1244 1245 1246 1247 1248 1249
		/* Try enabling everything, and see what sticks */
		cntacr = CNTACR_RFRQ | CNTACR_RWPT | CNTACR_RPCT |
			 CNTACR_RWVT | CNTACR_RVOFF | CNTACR_RVCT;
		writel_relaxed(cntacr, cntctlbase + CNTACR(n));
		cntacr = readl_relaxed(cntctlbase + CNTACR(n));

		if ((cnttidr & CNTTIDR_VIRT(n)) &&
		    !(~cntacr & (CNTACR_RWVT | CNTACR_RVCT))) {
1250 1251 1252 1253 1254
			of_node_put(best_frame);
			best_frame = frame;
			arch_timer_mem_use_virtual = true;
			break;
		}
1255 1256 1257 1258

		if (~cntacr & (CNTACR_RWPT | CNTACR_RPCT))
			continue;

1259 1260 1261 1262
		of_node_put(best_frame);
		best_frame = of_node_get(frame);
	}

1263
	ret= -ENXIO;
1264 1265 1266
	base = arch_counter_base = of_io_request_and_map(best_frame, 0,
							 "arch_mem_timer");
	if (IS_ERR(base)) {
1267
		pr_err("Can't map frame's registers\n");
1268
		goto out;
1269 1270 1271 1272 1273 1274
	}

	if (arch_timer_mem_use_virtual)
		irq = irq_of_parse_and_map(best_frame, 1);
	else
		irq = irq_of_parse_and_map(best_frame, 0);
1275

1276
	ret = -EINVAL;
1277
	if (!irq) {
1278
		pr_err("Frame missing %s irq.\n",
1279
		       arch_timer_mem_use_virtual ? "virt" : "phys");
1280
		goto out;
1281 1282 1283
	}

	arch_timer_detect_rate(base, np);
1284 1285 1286 1287 1288
	ret = arch_timer_mem_register(base, irq);
	if (ret)
		goto out;

	return arch_timer_common_init();
1289 1290 1291
out:
	iounmap(cntctlbase);
	of_node_put(best_frame);
1292
	return ret;
1293
}
1294
CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
1295
		       arch_timer_mem_init);
1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317 1318

#ifdef CONFIG_ACPI
static int __init map_generic_timer_interrupt(u32 interrupt, u32 flags)
{
	int trigger, polarity;

	if (!interrupt)
		return 0;

	trigger = (flags & ACPI_GTDT_INTERRUPT_MODE) ? ACPI_EDGE_SENSITIVE
			: ACPI_LEVEL_SENSITIVE;

	polarity = (flags & ACPI_GTDT_INTERRUPT_POLARITY) ? ACPI_ACTIVE_LOW
			: ACPI_ACTIVE_HIGH;

	return acpi_register_gsi(NULL, interrupt, trigger, polarity);
}

/* Initialize per-processor generic timer */
static int __init arch_timer_acpi_init(struct acpi_table_header *table)
{
	struct acpi_table_gtdt *gtdt;

1319
	if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
1320
		pr_warn("already initialized, skipping\n");
1321 1322 1323 1324 1325
		return -EINVAL;
	}

	gtdt = container_of(table, struct acpi_table_gtdt, header);

1326
	arch_timers_present |= ARCH_TIMER_TYPE_CP15;
1327

1328
	arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI] =
1329 1330 1331
		map_generic_timer_interrupt(gtdt->secure_el1_interrupt,
		gtdt->secure_el1_flags);

1332
	arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI] =
1333 1334 1335
		map_generic_timer_interrupt(gtdt->non_secure_el1_interrupt,
		gtdt->non_secure_el1_flags);

1336
	arch_timer_ppi[ARCH_TIMER_VIRT_PPI] =
1337 1338 1339
		map_generic_timer_interrupt(gtdt->virtual_timer_interrupt,
		gtdt->virtual_timer_flags);

1340
	arch_timer_ppi[ARCH_TIMER_HYP_PPI] =
1341 1342 1343 1344 1345 1346 1347 1348 1349
		map_generic_timer_interrupt(gtdt->non_secure_el2_interrupt,
		gtdt->non_secure_el2_flags);

	/* Get the frequency from CNTFRQ */
	arch_timer_detect_rate(NULL, NULL);

	/* Always-on capability */
	arch_timer_c3stop = !(gtdt->non_secure_el1_flags & ACPI_GTDT_ALWAYS_ON);

1350 1351 1352
	/* Check for globally applicable workarounds */
	arch_timer_check_ool_workaround(ate_match_acpi_oem_info, table);

1353 1354 1355
	arch_timer_init();
	return 0;
}
1356
CLOCKSOURCE_ACPI_DECLARE(arch_timer, ACPI_SIG_GTDT, arch_timer_acpi_init);
1357
#endif