intel_dp.c 154.0 KB
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/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/i2c.h>
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <linux/notifier.h>
#include <linux/reboot.h>
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#include <drm/drmP.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
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#include "intel_drv.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"

#define DP_LINK_CHECK_TIMEOUT	(10 * 1000)

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struct dp_link_dpll {
	int link_bw;
	struct dpll dpll;
};

static const struct dp_link_dpll gen4_dpll[] = {
	{ DP_LINK_BW_1_62,
		{ .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
	{ DP_LINK_BW_2_7,
		{ .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
};

static const struct dp_link_dpll pch_dpll[] = {
	{ DP_LINK_BW_1_62,
		{ .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
	{ DP_LINK_BW_2_7,
		{ .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
};

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static const struct dp_link_dpll vlv_dpll[] = {
	{ DP_LINK_BW_1_62,
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		{ .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
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	{ DP_LINK_BW_2_7,
		{ .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
};

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/*
 * CHV supports eDP 1.4 that have  more link rates.
 * Below only provides the fixed rate but exclude variable rate.
 */
static const struct dp_link_dpll chv_dpll[] = {
	/*
	 * CHV requires to program fractional division for m2.
	 * m2 is stored in fixed point format using formula below
	 * (m2_int << 22) | m2_fraction
	 */
	{ DP_LINK_BW_1_62,	/* m2_int = 32, m2_fraction = 1677722 */
		{ .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
	{ DP_LINK_BW_2_7,	/* m2_int = 27, m2_fraction = 0 */
		{ .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
	{ DP_LINK_BW_5_4,	/* m2_int = 27, m2_fraction = 0 */
		{ .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
};

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/**
 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 * @intel_dp: DP struct
 *
 * If a CPU or PCH DP output is attached to an eDP panel, this function
 * will return true, and false otherwise.
 */
static bool is_edp(struct intel_dp *intel_dp)
{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
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}

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static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
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{
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	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

	return intel_dig_port->base.base.dev;
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}

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static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
{
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	return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
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}

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static void intel_dp_link_down(struct intel_dp *intel_dp);
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static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
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static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
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static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
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static void vlv_steal_power_sequencer(struct drm_device *dev,
				      enum pipe pipe);
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int
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intel_dp_max_link_bw(struct intel_dp *intel_dp)
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{
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	int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
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	struct drm_device *dev = intel_dp->attached_connector->base.dev;
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	switch (max_link_bw) {
	case DP_LINK_BW_1_62:
	case DP_LINK_BW_2_7:
		break;
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	case DP_LINK_BW_5_4: /* 1.2 capable displays may advertise higher bw */
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		if (((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) ||
		     INTEL_INFO(dev)->gen >= 8) &&
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		    intel_dp->dpcd[DP_DPCD_REV] >= 0x12)
			max_link_bw = DP_LINK_BW_5_4;
		else
			max_link_bw = DP_LINK_BW_2_7;
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		break;
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	default:
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		WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
		     max_link_bw);
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		max_link_bw = DP_LINK_BW_1_62;
		break;
	}
	return max_link_bw;
}

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static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	u8 source_max, sink_max;

	source_max = 4;
	if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
	    (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
		source_max = 2;

	sink_max = drm_dp_max_lane_count(intel_dp->dpcd);

	return min(source_max, sink_max);
}

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/*
 * The units on the numbers in the next two are... bizarre.  Examples will
 * make it clearer; this one parallels an example in the eDP spec.
 *
 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 *
 *     270000 * 1 * 8 / 10 == 216000
 *
 * The actual data capacity of that configuration is 2.16Gbit/s, so the
 * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 * 119000.  At 18bpp that's 2142000 kilobits per second.
 *
 * Thus the strange-looking division by 10 in intel_dp_link_required, to
 * get the result in decakilobits instead of kilobits.
 */

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static int
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intel_dp_link_required(int pixel_clock, int bpp)
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{
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	return (pixel_clock * bpp + 9) / 10;
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}

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static int
intel_dp_max_data_rate(int max_link_clock, int max_lanes)
{
	return (max_link_clock * max_lanes * 8) / 10;
}

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static enum drm_mode_status
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intel_dp_mode_valid(struct drm_connector *connector,
		    struct drm_display_mode *mode)
{
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	struct intel_dp *intel_dp = intel_attached_dp(connector);
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	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
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	int target_clock = mode->clock;
	int max_rate, mode_rate, max_lanes, max_link_clock;
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	if (is_edp(intel_dp) && fixed_mode) {
		if (mode->hdisplay > fixed_mode->hdisplay)
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			return MODE_PANEL;

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		if (mode->vdisplay > fixed_mode->vdisplay)
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			return MODE_PANEL;
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		target_clock = fixed_mode->clock;
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	}

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	max_link_clock = drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
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	max_lanes = intel_dp_max_lane_count(intel_dp);
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	max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
	mode_rate = intel_dp_link_required(target_clock, 18);

	if (mode_rate > max_rate)
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		return MODE_CLOCK_HIGH;
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	if (mode->clock < 10000)
		return MODE_CLOCK_LOW;

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	if (mode->flags & DRM_MODE_FLAG_DBLCLK)
		return MODE_H_ILLEGAL;

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	return MODE_OK;
}

static uint32_t
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pack_aux(const uint8_t *src, int src_bytes)
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{
	int	i;
	uint32_t v = 0;

	if (src_bytes > 4)
		src_bytes = 4;
	for (i = 0; i < src_bytes; i++)
		v |= ((uint32_t) src[i]) << ((3-i) * 8);
	return v;
}

static void
unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
{
	int i;
	if (dst_bytes > 4)
		dst_bytes = 4;
	for (i = 0; i < dst_bytes; i++)
		dst[i] = src >> ((3-i) * 8);
}

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/* hrawclock is 1/4 the FSB frequency */
static int
intel_hrawclk(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t clkcfg;

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	/* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
	if (IS_VALLEYVIEW(dev))
		return 200;

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	clkcfg = I915_READ(CLKCFG);
	switch (clkcfg & CLKCFG_FSB_MASK) {
	case CLKCFG_FSB_400:
		return 100;
	case CLKCFG_FSB_533:
		return 133;
	case CLKCFG_FSB_667:
		return 166;
	case CLKCFG_FSB_800:
		return 200;
	case CLKCFG_FSB_1067:
		return 266;
	case CLKCFG_FSB_1333:
		return 333;
	/* these two are just a guess; one of them might be right */
	case CLKCFG_FSB_1600:
	case CLKCFG_FSB_1600_ALT:
		return 400;
	default:
		return 133;
	}
}

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static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
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				    struct intel_dp *intel_dp);
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static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
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					      struct intel_dp *intel_dp);
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static void pps_lock(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *encoder = &intel_dig_port->base;
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum intel_display_power_domain power_domain;

	/*
	 * See vlv_power_sequencer_reset() why we need
	 * a power domain reference here.
	 */
	power_domain = intel_display_port_power_domain(encoder);
	intel_display_power_get(dev_priv, power_domain);

	mutex_lock(&dev_priv->pps_mutex);
}

static void pps_unlock(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *encoder = &intel_dig_port->base;
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum intel_display_power_domain power_domain;

	mutex_unlock(&dev_priv->pps_mutex);

	power_domain = intel_display_port_power_domain(encoder);
	intel_display_power_put(dev_priv, power_domain);
}

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static void
vlv_power_sequencer_kick(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum pipe pipe = intel_dp->pps_pipe;
	uint32_t DP;

	if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
		 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
		 pipe_name(pipe), port_name(intel_dig_port->port)))
		return;

	DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
		      pipe_name(pipe), port_name(intel_dig_port->port));

	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
	DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
	DP |= DP_PORT_WIDTH(1);
	DP |= DP_LINK_TRAIN_PAT_1;

	if (IS_CHERRYVIEW(dev))
		DP |= DP_PIPE_SELECT_CHV(pipe);
	else if (pipe == PIPE_B)
		DP |= DP_PIPEB_SELECT;

	/*
	 * Similar magic as in intel_dp_enable_port().
	 * We _must_ do this port enable + disable trick
	 * to make this power seqeuencer lock onto the port.
	 * Otherwise even VDD force bit won't work.
	 */
	I915_WRITE(intel_dp->output_reg, DP);
	POSTING_READ(intel_dp->output_reg);

	I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);

	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);
}

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static enum pipe
vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
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	struct intel_encoder *encoder;
	unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
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	enum pipe pipe;
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	lockdep_assert_held(&dev_priv->pps_mutex);
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	/* We should never land here with regular DP ports */
	WARN_ON(!is_edp(intel_dp));

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	if (intel_dp->pps_pipe != INVALID_PIPE)
		return intel_dp->pps_pipe;

	/*
	 * We don't have power sequencer currently.
	 * Pick one that's not used by other ports.
	 */
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		struct intel_dp *tmp;

		if (encoder->type != INTEL_OUTPUT_EDP)
			continue;

		tmp = enc_to_intel_dp(&encoder->base);

		if (tmp->pps_pipe != INVALID_PIPE)
			pipes &= ~(1 << tmp->pps_pipe);
	}

	/*
	 * Didn't find one. This should not happen since there
	 * are two power sequencers and up to two eDP ports.
	 */
	if (WARN_ON(pipes == 0))
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		pipe = PIPE_A;
	else
		pipe = ffs(pipes) - 1;
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	vlv_steal_power_sequencer(dev, pipe);
	intel_dp->pps_pipe = pipe;
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	DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
		      pipe_name(intel_dp->pps_pipe),
		      port_name(intel_dig_port->port));

	/* init power sequencer on this pipe and port */
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	intel_dp_init_panel_power_sequencer(dev, intel_dp);
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
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	/*
	 * Even vdd force doesn't work until we've made
	 * the power sequencer lock in on the port.
	 */
	vlv_power_sequencer_kick(intel_dp);

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	return intel_dp->pps_pipe;
}

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typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
			       enum pipe pipe);

static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
			       enum pipe pipe)
{
	return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
}

static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
				enum pipe pipe)
{
	return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
}

static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
			 enum pipe pipe)
{
	return true;
}
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static enum pipe
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vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
		     enum port port,
		     vlv_pipe_check pipe_check)
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{
	enum pipe pipe;
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	for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
		u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
			PANEL_PORT_SELECT_MASK;
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		if (port_sel != PANEL_PORT_SELECT_VLV(port))
			continue;

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		if (!pipe_check(dev_priv, pipe))
			continue;

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		return pipe;
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	}

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	return INVALID_PIPE;
}

static void
vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;

	lockdep_assert_held(&dev_priv->pps_mutex);

	/* try to find a pipe with this port selected */
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	/* first pick one where the panel is on */
	intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
						  vlv_pipe_has_pp_on);
	/* didn't find one? pick one where vdd is on */
	if (intel_dp->pps_pipe == INVALID_PIPE)
		intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
							  vlv_pipe_has_vdd_on);
	/* didn't find one? pick one with just the correct port */
	if (intel_dp->pps_pipe == INVALID_PIPE)
		intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
							  vlv_pipe_any);
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	/* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
	if (intel_dp->pps_pipe == INVALID_PIPE) {
		DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
			      port_name(port));
		return;
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	}

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	DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
		      port_name(port), pipe_name(intel_dp->pps_pipe));

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	intel_dp_init_panel_power_sequencer(dev, intel_dp);
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
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}

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void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
{
	struct drm_device *dev = dev_priv->dev;
	struct intel_encoder *encoder;

	if (WARN_ON(!IS_VALLEYVIEW(dev)))
		return;

	/*
	 * We can't grab pps_mutex here due to deadlock with power_domain
	 * mutex when power_domain functions are called while holding pps_mutex.
	 * That also means that in order to use pps_pipe the code needs to
	 * hold both a power domain reference and pps_mutex, and the power domain
	 * reference get/put must be done while _not_ holding pps_mutex.
	 * pps_{lock,unlock}() do these steps in the correct order, so one
	 * should use them always.
	 */

	list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
		struct intel_dp *intel_dp;

		if (encoder->type != INTEL_OUTPUT_EDP)
			continue;

		intel_dp = enc_to_intel_dp(&encoder->base);
		intel_dp->pps_pipe = INVALID_PIPE;
	}
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}

static u32 _pp_ctrl_reg(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

	if (HAS_PCH_SPLIT(dev))
		return PCH_PP_CONTROL;
	else
		return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
}

static u32 _pp_stat_reg(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);

	if (HAS_PCH_SPLIT(dev))
		return PCH_PP_STATUS;
	else
		return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
}

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/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
   This function only applicable when panel PM state is not to be tracked */
static int edp_notify_handler(struct notifier_block *this, unsigned long code,
			      void *unused)
{
	struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
						 edp_notifier);
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp_div;
	u32 pp_ctrl_reg, pp_div_reg;

	if (!is_edp(intel_dp) || code != SYS_RESTART)
		return 0;

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	pps_lock(intel_dp);
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	if (IS_VALLEYVIEW(dev)) {
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		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

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		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
		pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
		pp_div = I915_READ(pp_div_reg);
		pp_div &= PP_REFERENCE_DIVIDER_MASK;

		/* 0x1F write to PP_DIV_REG sets max cycle delay */
		I915_WRITE(pp_div_reg, pp_div | 0x1F);
		I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
		msleep(intel_dp->panel_power_cycle_delay);
	}

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	pps_unlock(intel_dp);
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	return 0;
}

602
static bool edp_have_panel_power(struct intel_dp *intel_dp)
603
{
604
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
605 606
	struct drm_i915_private *dev_priv = dev->dev_private;

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607 608
	lockdep_assert_held(&dev_priv->pps_mutex);

609 610 611 612
	if (IS_VALLEYVIEW(dev) &&
	    intel_dp->pps_pipe == INVALID_PIPE)
		return false;

613
	return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
614 615
}

616
static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
617
{
618
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
619 620
	struct drm_i915_private *dev_priv = dev->dev_private;

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621 622
	lockdep_assert_held(&dev_priv->pps_mutex);

623 624 625 626
	if (IS_VALLEYVIEW(dev) &&
	    intel_dp->pps_pipe == INVALID_PIPE)
		return false;

627
	return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
628 629
}

630 631 632
static void
intel_dp_check_edp(struct intel_dp *intel_dp)
{
633
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
634
	struct drm_i915_private *dev_priv = dev->dev_private;
635

636 637
	if (!is_edp(intel_dp))
		return;
638

639
	if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
640 641
		WARN(1, "eDP powered off while attempting aux channel communication.\n");
		DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
642 643
			      I915_READ(_pp_stat_reg(intel_dp)),
			      I915_READ(_pp_ctrl_reg(intel_dp)));
644 645 646
	}
}

647 648 649 650 651 652
static uint32_t
intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
653
	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
654 655 656
	uint32_t status;
	bool done;

657
#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
658
	if (has_aux_irq)
659
		done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
660
					  msecs_to_jiffies_timeout(10));
661 662 663 664 665 666 667 668 669 670
	else
		done = wait_for_atomic(C, 10) == 0;
	if (!done)
		DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
			  has_aux_irq);
#undef C

	return status;
}

671
static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
672
{
673 674
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
675

676 677 678
	/*
	 * The clock divider is based off the hrawclk, and would like to run at
	 * 2MHz.  So, take the hrawclk value and divide by 2 and use that
679
	 */
680 681 682 683 684 685 686 687 688 689 690 691 692
	return index ? 0 : intel_hrawclk(dev) / 2;
}

static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;

	if (index)
		return 0;

	if (intel_dig_port->port == PORT_A) {
		if (IS_GEN6(dev) || IS_GEN7(dev))
693
			return 200; /* SNB & IVB eDP input clock at 400Mhz */
694
		else
695
			return 225; /* eDP input clock at 450Mhz */
696 697 698 699 700 701 702 703 704 705 706 707 708 709 710
	} else {
		return DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
	}
}

static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

	if (intel_dig_port->port == PORT_A) {
		if (index)
			return 0;
		return DIV_ROUND_CLOSEST(intel_ddi_get_cdclk_freq(dev_priv), 2000);
711 712
	} else if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
		/* Workaround for non-ULT HSW */
713 714 715 716 717
		switch (index) {
		case 0: return 63;
		case 1: return 72;
		default: return 0;
		}
718
	} else  {
719
		return index ? 0 : DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
720
	}
721 722
}

723 724 725 726 727
static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	return index ? 0 : 100;
}

728 729 730 731 732 733 734 735 736 737
static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
	/*
	 * SKL doesn't need us to program the AUX clock divider (Hardware will
	 * derive the clock from CDCLK automatically). We still implement the
	 * get_aux_clock_divider vfunc to plug-in into the existing code.
	 */
	return index ? 0 : 1;
}

738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757
static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
				      bool has_aux_irq,
				      int send_bytes,
				      uint32_t aux_clock_divider)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	uint32_t precharge, timeout;

	if (IS_GEN6(dev))
		precharge = 3;
	else
		precharge = 5;

	if (IS_BROADWELL(dev) && intel_dp->aux_ch_ctl_reg == DPA_AUX_CH_CTL)
		timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
	else
		timeout = DP_AUX_CH_CTL_TIME_OUT_400us;

	return DP_AUX_CH_CTL_SEND_BUSY |
758
	       DP_AUX_CH_CTL_DONE |
759
	       (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
760
	       DP_AUX_CH_CTL_TIME_OUT_ERROR |
761
	       timeout |
762
	       DP_AUX_CH_CTL_RECEIVE_ERROR |
763 764
	       (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
	       (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
765
	       (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
766 767
}

768 769 770 771 772 773 774 775 776 777 778 779 780 781 782
static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
				      bool has_aux_irq,
				      int send_bytes,
				      uint32_t unused)
{
	return DP_AUX_CH_CTL_SEND_BUSY |
	       DP_AUX_CH_CTL_DONE |
	       (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
	       DP_AUX_CH_CTL_TIME_OUT_ERROR |
	       DP_AUX_CH_CTL_TIME_OUT_1600us |
	       DP_AUX_CH_CTL_RECEIVE_ERROR |
	       (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
	       DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
}

783 784
static int
intel_dp_aux_ch(struct intel_dp *intel_dp,
785
		const uint8_t *send, int send_bytes,
786 787 788 789 790 791 792
		uint8_t *recv, int recv_size)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t ch_ctl = intel_dp->aux_ch_ctl_reg;
	uint32_t ch_data = ch_ctl + 4;
793
	uint32_t aux_clock_divider;
794 795
	int i, ret, recv_bytes;
	uint32_t status;
796
	int try, clock = 0;
797
	bool has_aux_irq = HAS_AUX_IRQ(dev);
798 799
	bool vdd;

800
	pps_lock(intel_dp);
V
Ville Syrjälä 已提交
801

802 803 804 805 806 807
	/*
	 * We will be called with VDD already enabled for dpcd/edid/oui reads.
	 * In such cases we want to leave VDD enabled and it's up to upper layers
	 * to turn it off. But for eg. i2c-dev access we need to turn it on/off
	 * ourselves.
	 */
808
	vdd = edp_panel_vdd_on(intel_dp);
809 810 811 812 813 814 815 816

	/* dp aux is extremely sensitive to irq latency, hence request the
	 * lowest possible wakeup latency and so prevent the cpu from going into
	 * deep sleep states.
	 */
	pm_qos_update_request(&dev_priv->pm_qos, 0);

	intel_dp_check_edp(intel_dp);
817

818 819
	intel_aux_display_runtime_get(dev_priv);

820 821
	/* Try to wait for any previous AUX channel activity */
	for (try = 0; try < 3; try++) {
822
		status = I915_READ_NOTRACE(ch_ctl);
823 824 825 826 827 828 829 830
		if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
			break;
		msleep(1);
	}

	if (try == 3) {
		WARN(1, "dp_aux_ch not started status 0x%08x\n",
		     I915_READ(ch_ctl));
831 832
		ret = -EBUSY;
		goto out;
833 834
	}

835 836 837 838 839 840
	/* Only 5 data registers! */
	if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
		ret = -E2BIG;
		goto out;
	}

841
	while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
842 843 844 845
		u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
							  has_aux_irq,
							  send_bytes,
							  aux_clock_divider);
846

847 848 849 850 851 852 853 854
		/* Must try at least 3 times according to DP spec */
		for (try = 0; try < 5; try++) {
			/* Load the send data into the aux channel data registers */
			for (i = 0; i < send_bytes; i += 4)
				I915_WRITE(ch_data + i,
					   pack_aux(send + i, send_bytes - i));

			/* Send the command and wait for it to complete */
855
			I915_WRITE(ch_ctl, send_ctl);
856 857 858 859 860 861 862 863 864 865 866 867 868 869 870 871

			status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);

			/* Clear done status and any errors */
			I915_WRITE(ch_ctl,
				   status |
				   DP_AUX_CH_CTL_DONE |
				   DP_AUX_CH_CTL_TIME_OUT_ERROR |
				   DP_AUX_CH_CTL_RECEIVE_ERROR);

			if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
				      DP_AUX_CH_CTL_RECEIVE_ERROR))
				continue;
			if (status & DP_AUX_CH_CTL_DONE)
				break;
		}
872
		if (status & DP_AUX_CH_CTL_DONE)
873 874 875 876
			break;
	}

	if ((status & DP_AUX_CH_CTL_DONE) == 0) {
877
		DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
878 879
		ret = -EBUSY;
		goto out;
880 881 882 883 884
	}

	/* Check for timeout or receive error.
	 * Timeouts occur when the sink is not connected
	 */
885
	if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
886
		DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
887 888
		ret = -EIO;
		goto out;
889
	}
890 891 892

	/* Timeouts occur when the device isn't connected, so they're
	 * "normal" -- don't fill the kernel log with these */
893
	if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
894
		DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
895 896
		ret = -ETIMEDOUT;
		goto out;
897 898 899 900 901 902 903
	}

	/* Unload any bytes sent back from the other side */
	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
		      DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
	if (recv_bytes > recv_size)
		recv_bytes = recv_size;
904

905 906 907
	for (i = 0; i < recv_bytes; i += 4)
		unpack_aux(I915_READ(ch_data + i),
			   recv + i, recv_bytes - i);
908

909 910 911
	ret = recv_bytes;
out:
	pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
912
	intel_aux_display_runtime_put(dev_priv);
913

914 915 916
	if (vdd)
		edp_panel_vdd_off(intel_dp, false);

917
	pps_unlock(intel_dp);
V
Ville Syrjälä 已提交
918

919
	return ret;
920 921
}

922 923
#define BARE_ADDRESS_SIZE	3
#define HEADER_SIZE		(BARE_ADDRESS_SIZE + 1)
924 925
static ssize_t
intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
926
{
927 928 929
	struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
	uint8_t txbuf[20], rxbuf[20];
	size_t txsize, rxsize;
930 931
	int ret;

932 933 934 935
	txbuf[0] = msg->request << 4;
	txbuf[1] = msg->address >> 8;
	txbuf[2] = msg->address & 0xff;
	txbuf[3] = msg->size - 1;
936

937 938 939
	switch (msg->request & ~DP_AUX_I2C_MOT) {
	case DP_AUX_NATIVE_WRITE:
	case DP_AUX_I2C_WRITE:
940
		txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
941
		rxsize = 1;
942

943 944
		if (WARN_ON(txsize > 20))
			return -E2BIG;
945

946
		memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
947

948 949 950
		ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
		if (ret > 0) {
			msg->reply = rxbuf[0] >> 4;
951

952 953 954 955
			/* Return payload size. */
			ret = msg->size;
		}
		break;
956

957 958
	case DP_AUX_NATIVE_READ:
	case DP_AUX_I2C_READ:
959
		txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
960
		rxsize = msg->size + 1;
961

962 963
		if (WARN_ON(rxsize > 20))
			return -E2BIG;
964

965 966 967 968 969 970 971 972 973 974 975
		ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
		if (ret > 0) {
			msg->reply = rxbuf[0] >> 4;
			/*
			 * Assume happy day, and copy the data. The caller is
			 * expected to check msg->reply before touching it.
			 *
			 * Return payload size.
			 */
			ret--;
			memcpy(msg->buffer, rxbuf + 1, ret);
976
		}
977 978 979 980 981
		break;

	default:
		ret = -EINVAL;
		break;
982
	}
983

984
	return ret;
985 986
}

987 988 989 990
static void
intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
991 992
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	enum port port = intel_dig_port->port;
993
	const char *name = NULL;
994 995
	int ret;

996 997 998
	switch (port) {
	case PORT_A:
		intel_dp->aux_ch_ctl_reg = DPA_AUX_CH_CTL;
999
		name = "DPDDC-A";
1000
		break;
1001 1002
	case PORT_B:
		intel_dp->aux_ch_ctl_reg = PCH_DPB_AUX_CH_CTL;
1003
		name = "DPDDC-B";
1004
		break;
1005 1006
	case PORT_C:
		intel_dp->aux_ch_ctl_reg = PCH_DPC_AUX_CH_CTL;
1007
		name = "DPDDC-C";
1008
		break;
1009 1010
	case PORT_D:
		intel_dp->aux_ch_ctl_reg = PCH_DPD_AUX_CH_CTL;
1011
		name = "DPDDC-D";
1012 1013 1014
		break;
	default:
		BUG();
1015 1016
	}

1017 1018 1019 1020 1021 1022 1023 1024 1025 1026
	/*
	 * The AUX_CTL register is usually DP_CTL + 0x10.
	 *
	 * On Haswell and Broadwell though:
	 *   - Both port A DDI_BUF_CTL and DDI_AUX_CTL are on the CPU
	 *   - Port B/C/D AUX channels are on the PCH, DDI_BUF_CTL on the CPU
	 *
	 * Skylake moves AUX_CTL back next to DDI_BUF_CTL, on the CPU.
	 */
	if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1027
		intel_dp->aux_ch_ctl_reg = intel_dp->output_reg + 0x10;
1028

1029
	intel_dp->aux.name = name;
1030 1031
	intel_dp->aux.dev = dev->dev;
	intel_dp->aux.transfer = intel_dp_aux_transfer;
1032

1033 1034
	DRM_DEBUG_KMS("registering %s bus for %s\n", name,
		      connector->base.kdev->kobj.name);
1035

1036
	ret = drm_dp_aux_register(&intel_dp->aux);
1037
	if (ret < 0) {
1038
		DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1039 1040
			  name, ret);
		return;
1041
	}
1042

1043 1044 1045 1046 1047
	ret = sysfs_create_link(&connector->base.kdev->kobj,
				&intel_dp->aux.ddc.dev.kobj,
				intel_dp->aux.ddc.dev.kobj.name);
	if (ret < 0) {
		DRM_ERROR("sysfs_create_link() for %s failed (%d)\n", name, ret);
1048
		drm_dp_aux_unregister(&intel_dp->aux);
1049
	}
1050 1051
}

1052 1053 1054 1055 1056
static void
intel_dp_connector_unregister(struct intel_connector *intel_connector)
{
	struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);

1057 1058 1059
	if (!intel_connector->mst_port)
		sysfs_remove_link(&intel_connector->base.kdev->kobj,
				  intel_dp->aux.ddc.dev.kobj.name);
1060 1061 1062
	intel_connector_unregister(intel_connector);
}

1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078
static void
hsw_dp_set_ddi_pll_sel(struct intel_crtc_config *pipe_config, int link_bw)
{
	switch (link_bw) {
	case DP_LINK_BW_1_62:
		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
		break;
	case DP_LINK_BW_2_7:
		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
		break;
	case DP_LINK_BW_5_4:
		pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
		break;
	}
}

1079 1080 1081 1082 1083
static void
intel_dp_set_clock(struct intel_encoder *encoder,
		   struct intel_crtc_config *pipe_config, int link_bw)
{
	struct drm_device *dev = encoder->base.dev;
1084 1085
	const struct dp_link_dpll *divisor = NULL;
	int i, count = 0;
1086 1087

	if (IS_G4X(dev)) {
1088 1089
		divisor = gen4_dpll;
		count = ARRAY_SIZE(gen4_dpll);
1090
	} else if (HAS_PCH_SPLIT(dev)) {
1091 1092
		divisor = pch_dpll;
		count = ARRAY_SIZE(pch_dpll);
1093 1094 1095
	} else if (IS_CHERRYVIEW(dev)) {
		divisor = chv_dpll;
		count = ARRAY_SIZE(chv_dpll);
1096
	} else if (IS_VALLEYVIEW(dev)) {
1097 1098
		divisor = vlv_dpll;
		count = ARRAY_SIZE(vlv_dpll);
1099
	}
1100 1101 1102 1103 1104 1105 1106 1107 1108

	if (divisor && count) {
		for (i = 0; i < count; i++) {
			if (link_bw == divisor[i].link_bw) {
				pipe_config->dpll = divisor[i].dpll;
				pipe_config->clock_set = true;
				break;
			}
		}
1109 1110 1111
	}
}

P
Paulo Zanoni 已提交
1112
bool
1113 1114
intel_dp_compute_config(struct intel_encoder *encoder,
			struct intel_crtc_config *pipe_config)
1115
{
1116
	struct drm_device *dev = encoder->base.dev;
1117
	struct drm_i915_private *dev_priv = dev->dev_private;
1118 1119
	struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1120
	enum port port = dp_to_dig_port(intel_dp)->port;
1121
	struct intel_crtc *intel_crtc = encoder->new_crtc;
1122
	struct intel_connector *intel_connector = intel_dp->attached_connector;
1123
	int lane_count, clock;
1124
	int min_lane_count = 1;
1125
	int max_lane_count = intel_dp_max_lane_count(intel_dp);
1126
	/* Conveniently, the link BW constants become indices with a shift...*/
1127
	int min_clock = 0;
1128
	int max_clock = intel_dp_max_link_bw(intel_dp) >> 3;
1129
	int bpp, mode_rate;
1130
	static int bws[] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7, DP_LINK_BW_5_4 };
1131
	int link_avail, link_clock;
1132

1133
	if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1134 1135
		pipe_config->has_pch_encoder = true;

1136
	pipe_config->has_dp_encoder = true;
1137
	pipe_config->has_drrs = false;
1138
	pipe_config->has_audio = intel_dp->has_audio;
1139

1140 1141 1142
	if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
		intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
				       adjusted_mode);
1143 1144 1145 1146
		if (!HAS_PCH_SPLIT(dev))
			intel_gmch_panel_fitting(intel_crtc, pipe_config,
						 intel_connector->panel.fitting_mode);
		else
1147 1148
			intel_pch_panel_fitting(intel_crtc, pipe_config,
						intel_connector->panel.fitting_mode);
1149 1150
	}

1151
	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1152 1153
		return false;

1154 1155
	DRM_DEBUG_KMS("DP link computation with max lane count %i "
		      "max bw %02x pixel clock %iKHz\n",
1156 1157
		      max_lane_count, bws[max_clock],
		      adjusted_mode->crtc_clock);
1158

1159 1160
	/* Walk through all bpp values. Luckily they're all nicely spaced with 2
	 * bpc in between. */
1161
	bpp = pipe_config->pipe_bpp;
1162 1163 1164 1165 1166 1167 1168
	if (is_edp(intel_dp)) {
		if (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp) {
			DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
				      dev_priv->vbt.edp_bpp);
			bpp = dev_priv->vbt.edp_bpp;
		}

1169 1170 1171 1172 1173 1174 1175 1176 1177
		/*
		 * Use the maximum clock and number of lanes the eDP panel
		 * advertizes being capable of. The panels are generally
		 * designed to support only a single clock and lane
		 * configuration, and typically these values correspond to the
		 * native resolution of the panel.
		 */
		min_lane_count = max_lane_count;
		min_clock = max_clock;
1178
	}
1179

1180
	for (; bpp >= 6*3; bpp -= 2*3) {
1181 1182
		mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
						   bpp);
1183

1184 1185
		for (clock = min_clock; clock <= max_clock; clock++) {
			for (lane_count = min_lane_count; lane_count <= max_lane_count; lane_count <<= 1) {
1186 1187 1188 1189 1190 1191 1192 1193 1194 1195
				link_clock = drm_dp_bw_code_to_link_rate(bws[clock]);
				link_avail = intel_dp_max_data_rate(link_clock,
								    lane_count);

				if (mode_rate <= link_avail) {
					goto found;
				}
			}
		}
	}
1196

1197
	return false;
1198

1199
found:
1200 1201 1202 1203 1204 1205
	if (intel_dp->color_range_auto) {
		/*
		 * See:
		 * CEA-861-E - 5.1 Default Encoding Parameters
		 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
		 */
1206
		if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
1207 1208 1209 1210 1211
			intel_dp->color_range = DP_COLOR_RANGE_16_235;
		else
			intel_dp->color_range = 0;
	}

1212
	if (intel_dp->color_range)
1213
		pipe_config->limited_color_range = true;
1214

1215 1216
	intel_dp->link_bw = bws[clock];
	intel_dp->lane_count = lane_count;
1217
	pipe_config->pipe_bpp = bpp;
1218
	pipe_config->port_clock = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
1219

1220 1221
	DRM_DEBUG_KMS("DP link bw %02x lane count %d clock %d bpp %d\n",
		      intel_dp->link_bw, intel_dp->lane_count,
1222
		      pipe_config->port_clock, bpp);
1223 1224
	DRM_DEBUG_KMS("DP link bw required %i available %i\n",
		      mode_rate, link_avail);
1225

1226
	intel_link_compute_m_n(bpp, lane_count,
1227 1228
			       adjusted_mode->crtc_clock,
			       pipe_config->port_clock,
1229
			       &pipe_config->dp_m_n);
1230

1231 1232
	if (intel_connector->panel.downclock_mode != NULL &&
		intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) {
1233
			pipe_config->has_drrs = true;
1234 1235 1236 1237 1238 1239
			intel_link_compute_m_n(bpp, lane_count,
				intel_connector->panel.downclock_mode->clock,
				pipe_config->port_clock,
				&pipe_config->dp_m2_n2);
	}

1240
	if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1241 1242 1243
		hsw_dp_set_ddi_pll_sel(pipe_config, intel_dp->link_bw);
	else
		intel_dp_set_clock(encoder, pipe_config, intel_dp->link_bw);
1244

1245
	return true;
1246 1247
}

1248
static void ironlake_set_pll_cpu_edp(struct intel_dp *intel_dp)
1249
{
1250 1251 1252
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
	struct drm_device *dev = crtc->base.dev;
1253 1254 1255
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

1256
	DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", crtc->config.port_clock);
1257 1258 1259
	dpa_ctl = I915_READ(DP_A);
	dpa_ctl &= ~DP_PLL_FREQ_MASK;

1260
	if (crtc->config.port_clock == 162000) {
1261 1262 1263 1264
		/* For a long time we've carried around a ILK-DevA w/a for the
		 * 160MHz clock. If we're really unlucky, it's still required.
		 */
		DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
1265
		dpa_ctl |= DP_PLL_FREQ_160MHZ;
1266
		intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1267 1268
	} else {
		dpa_ctl |= DP_PLL_FREQ_270MHZ;
1269
		intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1270
	}
1271

1272 1273 1274 1275 1276 1277
	I915_WRITE(DP_A, dpa_ctl);

	POSTING_READ(DP_A);
	udelay(500);
}

1278
static void intel_dp_prepare(struct intel_encoder *encoder)
1279
{
1280
	struct drm_device *dev = encoder->base.dev;
1281
	struct drm_i915_private *dev_priv = dev->dev_private;
1282
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1283
	enum port port = dp_to_dig_port(intel_dp)->port;
1284 1285
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
	struct drm_display_mode *adjusted_mode = &crtc->config.adjusted_mode;
1286

1287
	/*
K
Keith Packard 已提交
1288
	 * There are four kinds of DP registers:
1289 1290
	 *
	 * 	IBX PCH
K
Keith Packard 已提交
1291 1292
	 * 	SNB CPU
	 *	IVB CPU
1293 1294 1295 1296 1297 1298 1299 1300 1301 1302
	 * 	CPT PCH
	 *
	 * IBX PCH and CPU are the same for almost everything,
	 * except that the CPU DP PLL is configured in this
	 * register
	 *
	 * CPT PCH is quite different, having many bits moved
	 * to the TRANS_DP_CTL register instead. That
	 * configuration happens (oddly) in ironlake_pch_enable
	 */
1303

1304 1305 1306 1307
	/* Preserve the BIOS-computed detected bit. This is
	 * supposed to be read-only.
	 */
	intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1308

1309 1310
	/* Handle DP bits in common between all three register formats */
	intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1311
	intel_dp->DP |= DP_PORT_WIDTH(intel_dp->lane_count);
1312

1313
	if (crtc->config.has_audio) {
1314
		DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
1315
				 pipe_name(crtc->pipe));
C
Chris Wilson 已提交
1316
		intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
1317
		intel_write_eld(encoder);
1318
	}
1319

1320
	/* Split out the IBX/CPU vs CPT settings */
1321

1322
	if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
K
Keith Packard 已提交
1323 1324 1325 1326 1327 1328
		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

1329
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
K
Keith Packard 已提交
1330 1331
			intel_dp->DP |= DP_ENHANCED_FRAMING;

1332
		intel_dp->DP |= crtc->pipe << 29;
1333
	} else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1334
		if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
1335
			intel_dp->DP |= intel_dp->color_range;
1336 1337 1338 1339 1340 1341 1342

		if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
			intel_dp->DP |= DP_SYNC_HS_HIGH;
		if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
			intel_dp->DP |= DP_SYNC_VS_HIGH;
		intel_dp->DP |= DP_LINK_TRAIN_OFF;

1343
		if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1344 1345
			intel_dp->DP |= DP_ENHANCED_FRAMING;

1346 1347 1348 1349 1350 1351
		if (!IS_CHERRYVIEW(dev)) {
			if (crtc->pipe == 1)
				intel_dp->DP |= DP_PIPEB_SELECT;
		} else {
			intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
		}
1352 1353
	} else {
		intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1354
	}
1355 1356
}

1357 1358
#define IDLE_ON_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
#define IDLE_ON_VALUE   	(PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1359

1360 1361
#define IDLE_OFF_MASK		(PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
#define IDLE_OFF_VALUE		(0     | PP_SEQUENCE_NONE | 0                     | 0)
1362

1363 1364
#define IDLE_CYCLE_MASK		(PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
#define IDLE_CYCLE_VALUE	(0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1365

1366
static void wait_panel_status(struct intel_dp *intel_dp,
1367 1368
				       u32 mask,
				       u32 value)
1369
{
1370
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1371
	struct drm_i915_private *dev_priv = dev->dev_private;
1372 1373
	u32 pp_stat_reg, pp_ctrl_reg;

V
Ville Syrjälä 已提交
1374 1375
	lockdep_assert_held(&dev_priv->pps_mutex);

1376 1377
	pp_stat_reg = _pp_stat_reg(intel_dp);
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1378

1379
	DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1380 1381 1382
			mask, value,
			I915_READ(pp_stat_reg),
			I915_READ(pp_ctrl_reg));
1383

1384
	if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1385
		DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1386 1387
				I915_READ(pp_stat_reg),
				I915_READ(pp_ctrl_reg));
1388
	}
1389 1390

	DRM_DEBUG_KMS("Wait complete\n");
1391
}
1392

1393
static void wait_panel_on(struct intel_dp *intel_dp)
1394 1395
{
	DRM_DEBUG_KMS("Wait for panel power on\n");
1396
	wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1397 1398
}

1399
static void wait_panel_off(struct intel_dp *intel_dp)
1400 1401
{
	DRM_DEBUG_KMS("Wait for panel power off time\n");
1402
	wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1403 1404
}

1405
static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1406 1407
{
	DRM_DEBUG_KMS("Wait for panel power cycle\n");
1408 1409 1410 1411 1412 1413

	/* When we disable the VDD override bit last we have to do the manual
	 * wait. */
	wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
				       intel_dp->panel_power_cycle_delay);

1414
	wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1415 1416
}

1417
static void wait_backlight_on(struct intel_dp *intel_dp)
1418 1419 1420 1421 1422
{
	wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
				       intel_dp->backlight_on_delay);
}

1423
static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1424 1425 1426 1427
{
	wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
				       intel_dp->backlight_off_delay);
}
1428

1429 1430 1431 1432
/* Read the current pp_control value, unlocking the register if it
 * is locked
 */

1433
static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1434
{
1435 1436 1437
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 control;
1438

V
Ville Syrjälä 已提交
1439 1440
	lockdep_assert_held(&dev_priv->pps_mutex);

1441
	control = I915_READ(_pp_ctrl_reg(intel_dp));
1442 1443 1444
	control &= ~PANEL_UNLOCK_MASK;
	control |= PANEL_UNLOCK_REGS;
	return control;
1445 1446
}

1447 1448 1449 1450 1451
/*
 * Must be paired with edp_panel_vdd_off().
 * Must hold pps_mutex around the whole on/off sequence.
 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
 */
1452
static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1453
{
1454
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1455 1456
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
1457
	struct drm_i915_private *dev_priv = dev->dev_private;
1458
	enum intel_display_power_domain power_domain;
1459
	u32 pp;
1460
	u32 pp_stat_reg, pp_ctrl_reg;
1461
	bool need_to_disable = !intel_dp->want_panel_vdd;
1462

V
Ville Syrjälä 已提交
1463 1464
	lockdep_assert_held(&dev_priv->pps_mutex);

1465
	if (!is_edp(intel_dp))
1466
		return false;
1467 1468

	intel_dp->want_panel_vdd = true;
1469

1470
	if (edp_have_panel_vdd(intel_dp))
1471
		return need_to_disable;
1472

1473 1474
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);
1475

1476
	DRM_DEBUG_KMS("Turning eDP VDD on\n");
1477

1478 1479
	if (!edp_have_panel_power(intel_dp))
		wait_panel_power_cycle(intel_dp);
1480

1481
	pp = ironlake_get_pp_control(intel_dp);
1482
	pp |= EDP_FORCE_VDD;
1483

1484 1485
	pp_stat_reg = _pp_stat_reg(intel_dp);
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1486 1487 1488 1489 1490

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
			I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1491 1492 1493
	/*
	 * If the panel wasn't on, delay before accessing aux channel
	 */
1494
	if (!edp_have_panel_power(intel_dp)) {
1495
		DRM_DEBUG_KMS("eDP was not running\n");
1496 1497
		msleep(intel_dp->panel_power_up_delay);
	}
1498 1499 1500 1501

	return need_to_disable;
}

1502 1503 1504 1505 1506 1507 1508
/*
 * Must be paired with intel_edp_panel_vdd_off() or
 * intel_edp_panel_off().
 * Nested calls to these functions are not allowed since
 * we drop the lock. Caller must use some higher level
 * locking to prevent nested calls from other threads.
 */
1509
void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1510
{
1511
	bool vdd;
1512

1513 1514 1515
	if (!is_edp(intel_dp))
		return;

1516
	pps_lock(intel_dp);
1517
	vdd = edp_panel_vdd_on(intel_dp);
1518
	pps_unlock(intel_dp);
1519 1520

	WARN(!vdd, "eDP VDD already requested on\n");
1521 1522
}

1523
static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1524
{
1525
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1526
	struct drm_i915_private *dev_priv = dev->dev_private;
1527 1528 1529 1530
	struct intel_digital_port *intel_dig_port =
		dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	enum intel_display_power_domain power_domain;
1531
	u32 pp;
1532
	u32 pp_stat_reg, pp_ctrl_reg;
1533

V
Ville Syrjälä 已提交
1534
	lockdep_assert_held(&dev_priv->pps_mutex);
1535

1536
	WARN_ON(intel_dp->want_panel_vdd);
1537

1538
	if (!edp_have_panel_vdd(intel_dp))
1539
		return;
1540

1541
	DRM_DEBUG_KMS("Turning eDP VDD off\n");
1542

1543 1544
	pp = ironlake_get_pp_control(intel_dp);
	pp &= ~EDP_FORCE_VDD;
1545

1546 1547
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
	pp_stat_reg = _pp_stat_reg(intel_dp);
1548

1549 1550
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
P
Paulo Zanoni 已提交
1551

1552 1553 1554
	/* Make sure sequencer is idle before allowing subsequent activity */
	DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
	I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1555

1556 1557
	if ((pp & POWER_TARGET_ON) == 0)
		intel_dp->last_power_cycle = jiffies;
1558

1559 1560
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_put(dev_priv, power_domain);
1561
}
1562

1563
static void edp_panel_vdd_work(struct work_struct *__work)
1564 1565 1566 1567
{
	struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
						 struct intel_dp, panel_vdd_work);

1568
	pps_lock(intel_dp);
1569 1570
	if (!intel_dp->want_panel_vdd)
		edp_panel_vdd_off_sync(intel_dp);
1571
	pps_unlock(intel_dp);
1572 1573
}

1574 1575 1576 1577 1578 1579 1580 1581 1582 1583 1584 1585 1586
static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
{
	unsigned long delay;

	/*
	 * Queue the timer to fire a long time from now (relative to the power
	 * down delay) to keep the panel power up across a sequence of
	 * operations.
	 */
	delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
	schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
}

1587 1588 1589 1590 1591
/*
 * Must be paired with edp_panel_vdd_on().
 * Must hold pps_mutex around the whole on/off sequence.
 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
 */
1592
static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1593
{
V
Ville Syrjälä 已提交
1594 1595 1596 1597 1598
	struct drm_i915_private *dev_priv =
		intel_dp_to_dev(intel_dp)->dev_private;

	lockdep_assert_held(&dev_priv->pps_mutex);

1599 1600
	if (!is_edp(intel_dp))
		return;
1601

1602
	WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1603

1604 1605
	intel_dp->want_panel_vdd = false;

1606
	if (sync)
1607
		edp_panel_vdd_off_sync(intel_dp);
1608 1609
	else
		edp_panel_vdd_schedule_off(intel_dp);
1610 1611
}

1612
static void edp_panel_on(struct intel_dp *intel_dp)
1613
{
1614
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1615
	struct drm_i915_private *dev_priv = dev->dev_private;
1616
	u32 pp;
1617
	u32 pp_ctrl_reg;
1618

1619 1620
	lockdep_assert_held(&dev_priv->pps_mutex);

1621
	if (!is_edp(intel_dp))
1622
		return;
1623 1624 1625

	DRM_DEBUG_KMS("Turn eDP power on\n");

1626
	if (edp_have_panel_power(intel_dp)) {
1627
		DRM_DEBUG_KMS("eDP power already on\n");
1628
		return;
1629
	}
1630

1631
	wait_panel_power_cycle(intel_dp);
1632

1633
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1634
	pp = ironlake_get_pp_control(intel_dp);
1635 1636 1637
	if (IS_GEN5(dev)) {
		/* ILK workaround: disable reset around power sequence */
		pp &= ~PANEL_POWER_RESET;
1638 1639
		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1640
	}
1641

1642
	pp |= POWER_TARGET_ON;
1643 1644 1645
	if (!IS_GEN5(dev))
		pp |= PANEL_POWER_RESET;

1646 1647
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1648

1649
	wait_panel_on(intel_dp);
1650
	intel_dp->last_power_on = jiffies;
1651

1652 1653
	if (IS_GEN5(dev)) {
		pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1654 1655
		I915_WRITE(pp_ctrl_reg, pp);
		POSTING_READ(pp_ctrl_reg);
1656
	}
1657
}
V
Ville Syrjälä 已提交
1658

1659 1660 1661 1662 1663 1664 1665
void intel_edp_panel_on(struct intel_dp *intel_dp)
{
	if (!is_edp(intel_dp))
		return;

	pps_lock(intel_dp);
	edp_panel_on(intel_dp);
1666
	pps_unlock(intel_dp);
1667 1668
}

1669 1670

static void edp_panel_off(struct intel_dp *intel_dp)
1671
{
1672 1673
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
1674
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1675
	struct drm_i915_private *dev_priv = dev->dev_private;
1676
	enum intel_display_power_domain power_domain;
1677
	u32 pp;
1678
	u32 pp_ctrl_reg;
1679

1680 1681
	lockdep_assert_held(&dev_priv->pps_mutex);

1682 1683
	if (!is_edp(intel_dp))
		return;
1684

1685
	DRM_DEBUG_KMS("Turn eDP power off\n");
1686

1687 1688
	WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");

1689
	pp = ironlake_get_pp_control(intel_dp);
1690 1691
	/* We need to switch off panel power _and_ force vdd, for otherwise some
	 * panels get very unhappy and cease to work. */
1692 1693
	pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
		EDP_BLC_ENABLE);
1694

1695
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1696

1697 1698
	intel_dp->want_panel_vdd = false;

1699 1700
	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1701

1702
	intel_dp->last_power_cycle = jiffies;
1703
	wait_panel_off(intel_dp);
1704 1705

	/* We got a reference when we enabled the VDD. */
1706 1707
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_put(dev_priv, power_domain);
1708
}
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1709

1710 1711 1712 1713 1714 1715 1716
void intel_edp_panel_off(struct intel_dp *intel_dp)
{
	if (!is_edp(intel_dp))
		return;

	pps_lock(intel_dp);
	edp_panel_off(intel_dp);
1717
	pps_unlock(intel_dp);
1718 1719
}

1720 1721
/* Enable backlight in the panel power control. */
static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
1722
{
1723 1724
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
1725 1726
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
1727
	u32 pp_ctrl_reg;
1728

1729 1730 1731 1732 1733 1734
	/*
	 * If we enable the backlight right away following a panel power
	 * on, we may see slight flicker as the panel syncs with the eDP
	 * link.  So delay a bit to make sure the image is solid before
	 * allowing it to appear.
	 */
1735
	wait_backlight_on(intel_dp);
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1736

1737
	pps_lock(intel_dp);
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1738

1739
	pp = ironlake_get_pp_control(intel_dp);
1740
	pp |= EDP_BLC_ENABLE;
1741

1742
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1743 1744 1745

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
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1746

1747
	pps_unlock(intel_dp);
1748 1749
}

1750 1751 1752 1753 1754 1755 1756 1757 1758 1759 1760 1761 1762 1763
/* Enable backlight PWM and backlight PP control. */
void intel_edp_backlight_on(struct intel_dp *intel_dp)
{
	if (!is_edp(intel_dp))
		return;

	DRM_DEBUG_KMS("\n");

	intel_panel_enable_backlight(intel_dp->attached_connector);
	_intel_edp_backlight_on(intel_dp);
}

/* Disable backlight in the panel power control. */
static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
1764
{
1765
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
1766 1767
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 pp;
1768
	u32 pp_ctrl_reg;
1769

1770 1771 1772
	if (!is_edp(intel_dp))
		return;

1773
	pps_lock(intel_dp);
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1774

1775
	pp = ironlake_get_pp_control(intel_dp);
1776
	pp &= ~EDP_BLC_ENABLE;
1777

1778
	pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1779 1780 1781

	I915_WRITE(pp_ctrl_reg, pp);
	POSTING_READ(pp_ctrl_reg);
1782

1783
	pps_unlock(intel_dp);
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1784 1785

	intel_dp->last_backlight_off = jiffies;
1786
	edp_wait_backlight_off(intel_dp);
1787
}
1788

1789 1790 1791 1792 1793 1794 1795
/* Disable backlight PP control and backlight PWM. */
void intel_edp_backlight_off(struct intel_dp *intel_dp)
{
	if (!is_edp(intel_dp))
		return;

	DRM_DEBUG_KMS("\n");
1796

1797
	_intel_edp_backlight_off(intel_dp);
1798
	intel_panel_disable_backlight(intel_dp->attached_connector);
1799
}
1800

1801 1802 1803 1804 1805 1806 1807 1808
/*
 * Hook for controlling the panel power control backlight through the bl_power
 * sysfs attribute. Take care to handle multiple calls.
 */
static void intel_edp_backlight_power(struct intel_connector *connector,
				      bool enable)
{
	struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
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1809 1810
	bool is_enabled;

1811
	pps_lock(intel_dp);
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1812
	is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
1813
	pps_unlock(intel_dp);
1814 1815 1816 1817

	if (is_enabled == enable)
		return;

1818 1819
	DRM_DEBUG_KMS("panel power control backlight %s\n",
		      enable ? "enable" : "disable");
1820 1821 1822 1823 1824 1825 1826

	if (enable)
		_intel_edp_backlight_on(intel_dp);
	else
		_intel_edp_backlight_off(intel_dp);
}

1827
static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1828
{
1829 1830 1831
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = crtc->dev;
1832 1833 1834
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

1835 1836 1837
	assert_pipe_disabled(dev_priv,
			     to_intel_crtc(crtc)->pipe);

1838 1839
	DRM_DEBUG_KMS("\n");
	dpa_ctl = I915_READ(DP_A);
1840 1841 1842 1843 1844 1845 1846 1847 1848
	WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");

	/* We don't adjust intel_dp->DP while tearing down the link, to
	 * facilitate link retraining (e.g. after hotplug). Hence clear all
	 * enable bits here to ensure that we don't enable too much. */
	intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
	intel_dp->DP |= DP_PLL_ENABLE;
	I915_WRITE(DP_A, intel_dp->DP);
1849 1850
	POSTING_READ(DP_A);
	udelay(200);
1851 1852
}

1853
static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1854
{
1855 1856 1857
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
	struct drm_device *dev = crtc->dev;
1858 1859 1860
	struct drm_i915_private *dev_priv = dev->dev_private;
	u32 dpa_ctl;

1861 1862 1863
	assert_pipe_disabled(dev_priv,
			     to_intel_crtc(crtc)->pipe);

1864
	dpa_ctl = I915_READ(DP_A);
1865 1866 1867 1868 1869 1870 1871
	WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
	     "dp pll off, should be on\n");
	WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");

	/* We can't rely on the value tracked for the DP register in
	 * intel_dp->DP because link_down must not change that (otherwise link
	 * re-training will fail. */
1872
	dpa_ctl &= ~DP_PLL_ENABLE;
1873
	I915_WRITE(DP_A, dpa_ctl);
1874
	POSTING_READ(DP_A);
1875 1876 1877
	udelay(200);
}

1878
/* If the sink supports it, try to set the power state appropriately */
1879
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1880 1881 1882 1883 1884 1885 1886 1887
{
	int ret, i;

	/* Should have a valid DPCD by this point */
	if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
		return;

	if (mode != DRM_MODE_DPMS_ON) {
1888 1889
		ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
					 DP_SET_POWER_D3);
1890 1891 1892 1893 1894 1895
	} else {
		/*
		 * When turning on, we need to retry for 1ms to give the sink
		 * time to wake up.
		 */
		for (i = 0; i < 3; i++) {
1896 1897
			ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
						 DP_SET_POWER_D0);
1898 1899 1900 1901 1902
			if (ret == 1)
				break;
			msleep(1);
		}
	}
1903 1904 1905 1906

	if (ret != 1)
		DRM_DEBUG_KMS("failed to %s sink power state\n",
			      mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
1907 1908
}

1909 1910
static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
				  enum pipe *pipe)
1911
{
1912
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1913
	enum port port = dp_to_dig_port(intel_dp)->port;
1914 1915
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
1916 1917 1918 1919
	enum intel_display_power_domain power_domain;
	u32 tmp;

	power_domain = intel_display_port_power_domain(encoder);
1920
	if (!intel_display_power_is_enabled(dev_priv, power_domain))
1921 1922 1923
		return false;

	tmp = I915_READ(intel_dp->output_reg);
1924 1925 1926 1927

	if (!(tmp & DP_PORT_EN))
		return false;

1928
	if (port == PORT_A && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
1929
		*pipe = PORT_TO_PIPE_CPT(tmp);
1930 1931
	} else if (IS_CHERRYVIEW(dev)) {
		*pipe = DP_PORT_TO_PIPE_CHV(tmp);
1932
	} else if (!HAS_PCH_CPT(dev) || port == PORT_A) {
1933 1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952
		*pipe = PORT_TO_PIPE(tmp);
	} else {
		u32 trans_sel;
		u32 trans_dp;
		int i;

		switch (intel_dp->output_reg) {
		case PCH_DP_B:
			trans_sel = TRANS_DP_PORT_SEL_B;
			break;
		case PCH_DP_C:
			trans_sel = TRANS_DP_PORT_SEL_C;
			break;
		case PCH_DP_D:
			trans_sel = TRANS_DP_PORT_SEL_D;
			break;
		default:
			return true;
		}

1953
		for_each_pipe(dev_priv, i) {
1954 1955 1956 1957 1958 1959 1960
			trans_dp = I915_READ(TRANS_DP_CTL(i));
			if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
				*pipe = i;
				return true;
			}
		}

1961 1962 1963
		DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
			      intel_dp->output_reg);
	}
1964

1965 1966
	return true;
}
1967

1968 1969 1970 1971 1972
static void intel_dp_get_config(struct intel_encoder *encoder,
				struct intel_crtc_config *pipe_config)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	u32 tmp, flags = 0;
1973 1974 1975 1976
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = dp_to_dig_port(intel_dp)->port;
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1977
	int dotclock;
1978

1979 1980 1981 1982
	tmp = I915_READ(intel_dp->output_reg);
	if (tmp & DP_AUDIO_OUTPUT_ENABLE)
		pipe_config->has_audio = true;

1983 1984 1985 1986 1987
	if ((port == PORT_A) || !HAS_PCH_CPT(dev)) {
		if (tmp & DP_SYNC_HS_HIGH)
			flags |= DRM_MODE_FLAG_PHSYNC;
		else
			flags |= DRM_MODE_FLAG_NHSYNC;
1988

1989 1990 1991 1992 1993 1994 1995 1996 1997 1998
		if (tmp & DP_SYNC_VS_HIGH)
			flags |= DRM_MODE_FLAG_PVSYNC;
		else
			flags |= DRM_MODE_FLAG_NVSYNC;
	} else {
		tmp = I915_READ(TRANS_DP_CTL(crtc->pipe));
		if (tmp & TRANS_DP_HSYNC_ACTIVE_HIGH)
			flags |= DRM_MODE_FLAG_PHSYNC;
		else
			flags |= DRM_MODE_FLAG_NHSYNC;
1999

2000 2001 2002 2003 2004
		if (tmp & TRANS_DP_VSYNC_ACTIVE_HIGH)
			flags |= DRM_MODE_FLAG_PVSYNC;
		else
			flags |= DRM_MODE_FLAG_NVSYNC;
	}
2005 2006

	pipe_config->adjusted_mode.flags |= flags;
2007

2008 2009 2010 2011
	if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
	    tmp & DP_COLOR_RANGE_16_235)
		pipe_config->limited_color_range = true;

2012 2013 2014 2015
	pipe_config->has_dp_encoder = true;

	intel_dp_get_m_n(crtc, pipe_config);

2016
	if (port == PORT_A) {
2017 2018 2019 2020 2021
		if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_160MHZ)
			pipe_config->port_clock = 162000;
		else
			pipe_config->port_clock = 270000;
	}
2022 2023 2024 2025 2026 2027 2028

	dotclock = intel_dotclock_calculate(pipe_config->port_clock,
					    &pipe_config->dp_m_n);

	if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
		ironlake_check_encoder_dotclock(pipe_config, dotclock);

2029
	pipe_config->adjusted_mode.crtc_clock = dotclock;
2030

2031 2032 2033 2034 2035 2036 2037 2038 2039 2040 2041 2042 2043 2044 2045 2046 2047 2048 2049
	if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
	    pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
		/*
		 * This is a big fat ugly hack.
		 *
		 * Some machines in UEFI boot mode provide us a VBT that has 18
		 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
		 * unknown we fail to light up. Yet the same BIOS boots up with
		 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
		 * max, not what it tells us to use.
		 *
		 * Note: This will still be broken if the eDP panel is not lit
		 * up by the BIOS, and thus we can't get the mode at module
		 * load.
		 */
		DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
			      pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
		dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
	}
2050 2051
}

2052
static bool is_edp_psr(struct intel_dp *intel_dp)
2053
{
2054
	return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
2055 2056
}

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static bool intel_edp_is_psr_enabled(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

2061
	if (!HAS_PSR(dev))
R
Rodrigo Vivi 已提交
2062 2063
		return false;

2064
	return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
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2065 2066 2067 2068 2069 2070 2071 2072 2073 2074 2075 2076 2077 2078 2079 2080 2081 2082 2083 2084 2085 2086 2087 2088 2089 2090 2091 2092 2093 2094 2095
}

static void intel_edp_psr_write_vsc(struct intel_dp *intel_dp,
				    struct edp_vsc_psr *vsc_psr)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
	u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config.cpu_transcoder);
	u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config.cpu_transcoder);
	uint32_t *data = (uint32_t *) vsc_psr;
	unsigned int i;

	/* As per BSPec (Pipe Video Data Island Packet), we need to disable
	   the video DIP being updated before program video DIP data buffer
	   registers for DIP being updated. */
	I915_WRITE(ctl_reg, 0);
	POSTING_READ(ctl_reg);

	for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
		if (i < sizeof(struct edp_vsc_psr))
			I915_WRITE(data_reg + i, *data++);
		else
			I915_WRITE(data_reg + i, 0);
	}

	I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
	POSTING_READ(ctl_reg);
}

2096
static void intel_edp_psr_setup_vsc(struct intel_dp *intel_dp)
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2097 2098 2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110
{
	struct edp_vsc_psr psr_vsc;

	/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
	memset(&psr_vsc, 0, sizeof(psr_vsc));
	psr_vsc.sdp_header.HB0 = 0;
	psr_vsc.sdp_header.HB1 = 0x7;
	psr_vsc.sdp_header.HB2 = 0x2;
	psr_vsc.sdp_header.HB3 = 0x8;
	intel_edp_psr_write_vsc(intel_dp, &psr_vsc);
}

static void intel_edp_psr_enable_sink(struct intel_dp *intel_dp)
{
2111 2112
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
R
Rodrigo Vivi 已提交
2113
	struct drm_i915_private *dev_priv = dev->dev_private;
2114
	uint32_t aux_clock_divider;
R
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2115
	int precharge = 0x3;
2116
	bool only_standby = false;
2117 2118 2119 2120 2121 2122 2123 2124 2125 2126
	static const uint8_t aux_msg[] = {
		[0] = DP_AUX_NATIVE_WRITE << 4,
		[1] = DP_SET_POWER >> 8,
		[2] = DP_SET_POWER & 0xff,
		[3] = 1 - 1,
		[4] = DP_SET_POWER_D0,
	};
	int i;

	BUILD_BUG_ON(sizeof(aux_msg) > 20);
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2128 2129
	aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);

2130 2131 2132
	if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
		only_standby = true;

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	/* Enable PSR in sink */
2134
	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby)
2135 2136
		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
				   DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
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	else
2138 2139
		drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
				   DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
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2140 2141

	/* Setup AUX registers */
2142 2143 2144 2145
	for (i = 0; i < sizeof(aux_msg); i += 4)
		I915_WRITE(EDP_PSR_AUX_DATA1(dev) + i,
			   pack_aux(&aux_msg[i], sizeof(aux_msg) - i));

2146
	I915_WRITE(EDP_PSR_AUX_CTL(dev),
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		   DP_AUX_CH_CTL_TIME_OUT_400us |
2148
		   (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
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2149 2150 2151 2152 2153 2154
		   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
		   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
}

static void intel_edp_psr_enable_source(struct intel_dp *intel_dp)
{
2155 2156
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
R
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2157 2158 2159 2160
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t max_sleep_time = 0x1f;
	uint32_t idle_frames = 1;
	uint32_t val = 0x0;
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	const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
2162 2163 2164 2165
	bool only_standby = false;

	if (IS_BROADWELL(dev) && dig_port->port != PORT_A)
		only_standby = true;
R
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2167
	if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT || only_standby) {
R
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2168 2169 2170 2171
		val |= EDP_PSR_LINK_STANDBY;
		val |= EDP_PSR_TP2_TP3_TIME_0us;
		val |= EDP_PSR_TP1_TIME_0us;
		val |= EDP_PSR_SKIP_AUX_EXIT;
2172
		val |= IS_BROADWELL(dev) ? BDW_PSR_SINGLE_FRAME : 0;
R
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2173 2174 2175
	} else
		val |= EDP_PSR_LINK_DISABLE;

2176
	I915_WRITE(EDP_PSR_CTL(dev), val |
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Ben Widawsky 已提交
2177
		   (IS_BROADWELL(dev) ? 0 : link_entry_time) |
R
Rodrigo Vivi 已提交
2178 2179 2180 2181 2182
		   max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
		   idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
		   EDP_PSR_ENABLE);
}

2183 2184 2185 2186 2187 2188 2189 2190
static bool intel_edp_psr_match_conditions(struct intel_dp *intel_dp)
{
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc = dig_port->base.base.crtc;
	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

2191 2192 2193 2194
	lockdep_assert_held(&dev_priv->psr.lock);
	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
	WARN_ON(!drm_modeset_is_locked(&crtc->mutex));

R
Rodrigo Vivi 已提交
2195 2196
	dev_priv->psr.source_ok = false;

2197
	if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
2198 2199 2200 2201
		DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
		return false;
	}

2202
	if (!i915.enable_psr) {
2203 2204 2205 2206
		DRM_DEBUG_KMS("PSR disable by flag\n");
		return false;
	}

2207 2208 2209 2210
	/* Below limitations aren't valid for Broadwell */
	if (IS_BROADWELL(dev))
		goto out;

2211 2212 2213 2214 2215 2216
	if (I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config.cpu_transcoder)) &
	    S3D_ENABLE) {
		DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
		return false;
	}

2217
	if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
2218 2219 2220 2221
		DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
		return false;
	}

2222
 out:
R
Rodrigo Vivi 已提交
2223
	dev_priv->psr.source_ok = true;
2224 2225 2226
	return true;
}

2227
static void intel_edp_psr_do_enable(struct intel_dp *intel_dp)
R
Rodrigo Vivi 已提交
2228
{
2229 2230 2231
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
R
Rodrigo Vivi 已提交
2232

2233 2234
	WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
	WARN_ON(dev_priv->psr.active);
2235
	lockdep_assert_held(&dev_priv->psr.lock);
R
Rodrigo Vivi 已提交
2236

2237
	/* Enable/Re-enable PSR on the host */
R
Rodrigo Vivi 已提交
2238
	intel_edp_psr_enable_source(intel_dp);
2239 2240

	dev_priv->psr.active = true;
R
Rodrigo Vivi 已提交
2241 2242
}

2243 2244 2245
void intel_edp_psr_enable(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2246
	struct drm_i915_private *dev_priv = dev->dev_private;
2247

2248 2249 2250 2251 2252
	if (!HAS_PSR(dev)) {
		DRM_DEBUG_KMS("PSR not supported on this platform\n");
		return;
	}

2253 2254 2255 2256 2257
	if (!is_edp_psr(intel_dp)) {
		DRM_DEBUG_KMS("PSR not supported by this panel\n");
		return;
	}

2258
	mutex_lock(&dev_priv->psr.lock);
2259 2260
	if (dev_priv->psr.enabled) {
		DRM_DEBUG_KMS("PSR already in use\n");
2261
		goto unlock;
2262 2263
	}

2264 2265 2266
	if (!intel_edp_psr_match_conditions(intel_dp))
		goto unlock;

2267 2268
	dev_priv->psr.busy_frontbuffer_bits = 0;

2269
	intel_edp_psr_setup_vsc(intel_dp);
2270

2271 2272 2273
	/* Avoid continuous PSR exit by masking memup and hpd */
	I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
		   EDP_PSR_DEBUG_MASK_HPD | EDP_PSR_DEBUG_MASK_LPSP);
2274

2275 2276 2277
	/* Enable PSR on the panel */
	intel_edp_psr_enable_sink(intel_dp);

2278 2279
	dev_priv->psr.enabled = intel_dp;
unlock:
2280
	mutex_unlock(&dev_priv->psr.lock);
2281 2282
}

R
Rodrigo Vivi 已提交
2283 2284 2285 2286 2287
void intel_edp_psr_disable(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;

2288 2289 2290 2291 2292 2293
	mutex_lock(&dev_priv->psr.lock);
	if (!dev_priv->psr.enabled) {
		mutex_unlock(&dev_priv->psr.lock);
		return;
	}

2294 2295 2296 2297 2298 2299 2300 2301
	if (dev_priv->psr.active) {
		I915_WRITE(EDP_PSR_CTL(dev),
			   I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);

		/* Wait till PSR is idle */
		if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
			       EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
			DRM_ERROR("Timed out waiting for PSR Idle State\n");
R
Rodrigo Vivi 已提交
2302

2303 2304 2305 2306
		dev_priv->psr.active = false;
	} else {
		WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
	}
2307

2308
	dev_priv->psr.enabled = NULL;
2309
	mutex_unlock(&dev_priv->psr.lock);
2310 2311

	cancel_delayed_work_sync(&dev_priv->psr.work);
R
Rodrigo Vivi 已提交
2312 2313
}

2314
static void intel_edp_psr_work(struct work_struct *work)
2315 2316 2317
{
	struct drm_i915_private *dev_priv =
		container_of(work, typeof(*dev_priv), psr.work.work);
2318 2319
	struct intel_dp *intel_dp = dev_priv->psr.enabled;

2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330
	/* We have to make sure PSR is ready for re-enable
	 * otherwise it keeps disabled until next full enable/disable cycle.
	 * PSR might take some time to get fully disabled
	 * and be ready for re-enable.
	 */
	if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
		      EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
		DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
		return;
	}

2331 2332 2333
	mutex_lock(&dev_priv->psr.lock);
	intel_dp = dev_priv->psr.enabled;

2334
	if (!intel_dp)
2335
		goto unlock;
2336

2337 2338 2339 2340 2341 2342 2343 2344 2345
	/*
	 * The delayed work can race with an invalidate hence we need to
	 * recheck. Since psr_flush first clears this and then reschedules we
	 * won't ever miss a flush when bailing out here.
	 */
	if (dev_priv->psr.busy_frontbuffer_bits)
		goto unlock;

	intel_edp_psr_do_enable(intel_dp);
2346 2347
unlock:
	mutex_unlock(&dev_priv->psr.lock);
2348 2349
}

2350
static void intel_edp_psr_do_exit(struct drm_device *dev)
2351 2352 2353
{
	struct drm_i915_private *dev_priv = dev->dev_private;

2354 2355 2356 2357 2358 2359 2360 2361 2362
	if (dev_priv->psr.active) {
		u32 val = I915_READ(EDP_PSR_CTL(dev));

		WARN_ON(!(val & EDP_PSR_ENABLE));

		I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);

		dev_priv->psr.active = false;
	}
2363

2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419
}

void intel_edp_psr_invalidate(struct drm_device *dev,
			      unsigned frontbuffer_bits)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
	enum pipe pipe;

	mutex_lock(&dev_priv->psr.lock);
	if (!dev_priv->psr.enabled) {
		mutex_unlock(&dev_priv->psr.lock);
		return;
	}

	crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
	pipe = to_intel_crtc(crtc)->pipe;

	intel_edp_psr_do_exit(dev);

	frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);

	dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
	mutex_unlock(&dev_priv->psr.lock);
}

void intel_edp_psr_flush(struct drm_device *dev,
			 unsigned frontbuffer_bits)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
	enum pipe pipe;

	mutex_lock(&dev_priv->psr.lock);
	if (!dev_priv->psr.enabled) {
		mutex_unlock(&dev_priv->psr.lock);
		return;
	}

	crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
	pipe = to_intel_crtc(crtc)->pipe;
	dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;

	/*
	 * On Haswell sprite plane updates don't result in a psr invalidating
	 * signal in the hardware. Which means we need to manually fake this in
	 * software for all flushes, not just when we've seen a preceding
	 * invalidation through frontbuffer rendering.
	 */
	if (IS_HASWELL(dev) &&
	    (frontbuffer_bits & INTEL_FRONTBUFFER_SPRITE(pipe)))
		intel_edp_psr_do_exit(dev);

	if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
		schedule_delayed_work(&dev_priv->psr.work,
				      msecs_to_jiffies(100));
2420
	mutex_unlock(&dev_priv->psr.lock);
2421 2422 2423 2424 2425 2426 2427
}

void intel_edp_psr_init(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;

	INIT_DELAYED_WORK(&dev_priv->psr.work, intel_edp_psr_work);
2428
	mutex_init(&dev_priv->psr.lock);
2429 2430
}

2431
static void intel_disable_dp(struct intel_encoder *encoder)
2432
{
2433
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2434
	struct drm_device *dev = encoder->base.dev;
2435 2436 2437

	/* Make sure the panel is off before trying to change the mode. But also
	 * ensure that we have vdd while we switch off the panel. */
2438
	intel_edp_panel_vdd_on(intel_dp);
2439
	intel_edp_backlight_off(intel_dp);
2440
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2441
	intel_edp_panel_off(intel_dp);
2442

2443 2444
	/* disable the port before the pipe on g4x */
	if (INTEL_INFO(dev)->gen < 5)
2445
		intel_dp_link_down(intel_dp);
2446 2447
}

2448
static void ilk_post_disable_dp(struct intel_encoder *encoder)
2449
{
2450
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2451
	enum port port = dp_to_dig_port(intel_dp)->port;
2452

2453
	intel_dp_link_down(intel_dp);
2454 2455
	if (port == PORT_A)
		ironlake_edp_pll_off(intel_dp);
2456 2457 2458 2459 2460 2461 2462
}

static void vlv_post_disable_dp(struct intel_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

	intel_dp_link_down(intel_dp);
2463 2464
}

2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481
static void chv_post_disable_dp(struct intel_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel ch = vlv_dport_to_channel(dport);
	enum pipe pipe = intel_crtc->pipe;
	u32 val;

	intel_dp_link_down(intel_dp);

	mutex_lock(&dev_priv->dpio_lock);

	/* Propagate soft reset to data lane reset */
2482
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2483
	val |= CHV_PCS_REQ_SOFTRESET_EN;
2484
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2485

2486 2487 2488 2489 2490 2491 2492 2493 2494
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
	val |= CHV_PCS_REQ_SOFTRESET_EN;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2495
	val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2496
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2497 2498 2499 2500

	mutex_unlock(&dev_priv->dpio_lock);
}

2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525 2526 2527 2528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2540 2541 2542 2543 2544 2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564 2565 2566 2567 2568 2569 2570 2571 2572 2573 2574 2575 2576 2577 2578 2579 2580 2581 2582 2583 2584 2585 2586 2587 2588 2589 2590 2591 2592 2593 2594
static void
_intel_dp_set_link_train(struct intel_dp *intel_dp,
			 uint32_t *DP,
			 uint8_t dp_train_pat)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;

	if (HAS_DDI(dev)) {
		uint32_t temp = I915_READ(DP_TP_CTL(port));

		if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
			temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
		else
			temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;

		temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;

			break;
		case DP_TRAINING_PATTERN_1:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
			break;
		case DP_TRAINING_PATTERN_2:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
			break;
		case DP_TRAINING_PATTERN_3:
			temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
			break;
		}
		I915_WRITE(DP_TP_CTL(port), temp);

	} else if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
		*DP &= ~DP_LINK_TRAIN_MASK_CPT;

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			*DP |= DP_LINK_TRAIN_OFF_CPT;
			break;
		case DP_TRAINING_PATTERN_1:
			*DP |= DP_LINK_TRAIN_PAT_1_CPT;
			break;
		case DP_TRAINING_PATTERN_2:
			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
			break;
		case DP_TRAINING_PATTERN_3:
			DRM_ERROR("DP training pattern 3 not supported\n");
			*DP |= DP_LINK_TRAIN_PAT_2_CPT;
			break;
		}

	} else {
		if (IS_CHERRYVIEW(dev))
			*DP &= ~DP_LINK_TRAIN_MASK_CHV;
		else
			*DP &= ~DP_LINK_TRAIN_MASK;

		switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
		case DP_TRAINING_PATTERN_DISABLE:
			*DP |= DP_LINK_TRAIN_OFF;
			break;
		case DP_TRAINING_PATTERN_1:
			*DP |= DP_LINK_TRAIN_PAT_1;
			break;
		case DP_TRAINING_PATTERN_2:
			*DP |= DP_LINK_TRAIN_PAT_2;
			break;
		case DP_TRAINING_PATTERN_3:
			if (IS_CHERRYVIEW(dev)) {
				*DP |= DP_LINK_TRAIN_PAT_3_CHV;
			} else {
				DRM_ERROR("DP training pattern 3 not supported\n");
				*DP |= DP_LINK_TRAIN_PAT_2;
			}
			break;
		}
	}
}

static void intel_dp_enable_port(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;

	/* enable with pattern 1 (as per spec) */
	_intel_dp_set_link_train(intel_dp, &intel_dp->DP,
				 DP_TRAINING_PATTERN_1);

	I915_WRITE(intel_dp->output_reg, intel_dp->DP);
	POSTING_READ(intel_dp->output_reg);
2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605

	/*
	 * Magic for VLV/CHV. We _must_ first set up the register
	 * without actually enabling the port, and then do another
	 * write to enable the port. Otherwise link training will
	 * fail when the power sequencer is freshly used for this port.
	 */
	intel_dp->DP |= DP_PORT_EN;

	I915_WRITE(intel_dp->output_reg, intel_dp->DP);
	POSTING_READ(intel_dp->output_reg);
2606 2607
}

2608
static void intel_enable_dp(struct intel_encoder *encoder)
2609
{
2610 2611 2612 2613
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2614

2615 2616
	if (WARN_ON(dp_reg & DP_PORT_EN))
		return;
2617

2618 2619 2620 2621 2622
	pps_lock(intel_dp);

	if (IS_VALLEYVIEW(dev))
		vlv_init_panel_power_sequencer(intel_dp);

2623
	intel_dp_enable_port(intel_dp);
2624 2625 2626 2627 2628 2629 2630

	edp_panel_vdd_on(intel_dp);
	edp_panel_on(intel_dp);
	edp_panel_vdd_off(intel_dp, true);

	pps_unlock(intel_dp);

2631 2632 2633
	if (IS_VALLEYVIEW(dev))
		vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp));

2634
	intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2635 2636
	intel_dp_start_link_train(intel_dp);
	intel_dp_complete_link_train(intel_dp);
2637
	intel_dp_stop_link_train(intel_dp);
2638
}
2639

2640 2641
static void g4x_enable_dp(struct intel_encoder *encoder)
{
2642 2643
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

2644
	intel_enable_dp(encoder);
2645
	intel_edp_backlight_on(intel_dp);
2646
}
2647

2648 2649
static void vlv_enable_dp(struct intel_encoder *encoder)
{
2650 2651
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

2652
	intel_edp_backlight_on(intel_dp);
2653 2654
}

2655
static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2656 2657 2658 2659
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);

2660 2661
	intel_dp_prepare(encoder);

2662 2663 2664
	/* Only ilk+ has port A */
	if (dport->port == PORT_A) {
		ironlake_set_pll_cpu_edp(intel_dp);
2665
		ironlake_edp_pll_on(intel_dp);
2666
	}
2667 2668
}

2669 2670 2671 2672 2673 2674 2675 2676 2677 2678 2679 2680 2681 2682 2683 2684 2685 2686 2687 2688 2689 2690 2691 2692 2693 2694
static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
	enum pipe pipe = intel_dp->pps_pipe;
	int pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);

	edp_panel_vdd_off_sync(intel_dp);

	/*
	 * VLV seems to get confused when multiple power seqeuencers
	 * have the same port selected (even if only one has power/vdd
	 * enabled). The failure manifests as vlv_wait_port_ready() failing
	 * CHV on the other hand doesn't seem to mind having the same port
	 * selected in multiple power seqeuencers, but let's clear the
	 * port select always when logically disconnecting a power sequencer
	 * from a port.
	 */
	DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
		      pipe_name(pipe), port_name(intel_dig_port->port));
	I915_WRITE(pp_on_reg, 0);
	POSTING_READ(pp_on_reg);

	intel_dp->pps_pipe = INVALID_PIPE;
}

2695 2696 2697 2698 2699 2700 2701 2702
static void vlv_steal_power_sequencer(struct drm_device *dev,
				      enum pipe pipe)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *encoder;

	lockdep_assert_held(&dev_priv->pps_mutex);

2703 2704 2705
	if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
		return;

2706 2707 2708
	list_for_each_entry(encoder, &dev->mode_config.encoder_list,
			    base.head) {
		struct intel_dp *intel_dp;
2709
		enum port port;
2710 2711 2712 2713 2714

		if (encoder->type != INTEL_OUTPUT_EDP)
			continue;

		intel_dp = enc_to_intel_dp(&encoder->base);
2715
		port = dp_to_dig_port(intel_dp)->port;
2716 2717 2718 2719 2720

		if (intel_dp->pps_pipe != pipe)
			continue;

		DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2721
			      pipe_name(pipe), port_name(port));
2722 2723

		/* make sure vdd is off before we steal it */
2724
		vlv_detach_power_sequencer(intel_dp);
2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 2737
	}
}

static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *encoder = &intel_dig_port->base;
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);

	lockdep_assert_held(&dev_priv->pps_mutex);

2738 2739 2740
	if (!is_edp(intel_dp))
		return;

2741 2742 2743 2744 2745 2746 2747 2748 2749
	if (intel_dp->pps_pipe == crtc->pipe)
		return;

	/*
	 * If another power sequencer was being used on this
	 * port previously make sure to turn off vdd there while
	 * we still have control of it.
	 */
	if (intel_dp->pps_pipe != INVALID_PIPE)
2750
		vlv_detach_power_sequencer(intel_dp);
2751 2752 2753 2754 2755 2756 2757 2758 2759 2760 2761 2762 2763 2764

	/*
	 * We may be stealing the power
	 * sequencer from another port.
	 */
	vlv_steal_power_sequencer(dev, crtc->pipe);

	/* now it's all ours */
	intel_dp->pps_pipe = crtc->pipe;

	DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
		      pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));

	/* init power sequencer on this pipe and port */
2765 2766
	intel_dp_init_panel_power_sequencer(dev, intel_dp);
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2767 2768
}

2769
static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2770
{
2771
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2772
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2773
	struct drm_device *dev = encoder->base.dev;
2774
	struct drm_i915_private *dev_priv = dev->dev_private;
2775
	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2776
	enum dpio_channel port = vlv_dport_to_channel(dport);
2777 2778
	int pipe = intel_crtc->pipe;
	u32 val;
2779

2780
	mutex_lock(&dev_priv->dpio_lock);
2781

2782
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2783 2784 2785 2786 2787 2788
	val = 0;
	if (pipe)
		val |= (1<<21);
	else
		val &= ~(1<<21);
	val |= 0x001000c4;
2789 2790 2791
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2792

2793 2794 2795
	mutex_unlock(&dev_priv->dpio_lock);

	intel_enable_dp(encoder);
2796 2797
}

2798
static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2799 2800 2801 2802
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
2803 2804
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
2805
	enum dpio_channel port = vlv_dport_to_channel(dport);
2806
	int pipe = intel_crtc->pipe;
2807

2808 2809
	intel_dp_prepare(encoder);

2810
	/* Program Tx lane resets to default */
2811
	mutex_lock(&dev_priv->dpio_lock);
2812
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2813 2814
			 DPIO_PCS_TX_LANE2_RESET |
			 DPIO_PCS_TX_LANE1_RESET);
2815
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2816 2817 2818 2819 2820 2821
			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
				 DPIO_PCS_CLK_SOFT_RESET);

	/* Fix up inter-pair skew failure */
2822 2823 2824
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2825
	mutex_unlock(&dev_priv->dpio_lock);
2826 2827
}

2828 2829 2830 2831 2832 2833 2834 2835 2836 2837 2838
static void chv_pre_enable_dp(struct intel_encoder *encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel ch = vlv_dport_to_channel(dport);
	int pipe = intel_crtc->pipe;
	int data, i;
2839
	u32 val;
2840 2841

	mutex_lock(&dev_priv->dpio_lock);
2842

2843 2844 2845 2846 2847 2848 2849 2850 2851
	/* allow hardware to manage TX FIFO reset source */
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);

2852
	/* Deassert soft data lane reset*/
2853
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2854
	val |= CHV_PCS_REQ_SOFTRESET_EN;
2855 2856 2857 2858 2859 2860 2861 2862 2863
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
	val |= CHV_PCS_REQ_SOFTRESET_EN;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2864

2865
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2866
	val |= (DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2867
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2868 2869

	/* Program Tx lane latency optimal setting*/
2870 2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887 2888 2889
	for (i = 0; i < 4; i++) {
		/* Set the latency optimal bit */
		data = (i == 1) ? 0x0 : 0x6;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW11(ch, i),
				data << DPIO_FRC_LATENCY_SHFIT);

		/* Set the upar bit */
		data = (i == 1) ? 0x0 : 0x1;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
				data << DPIO_UPAR_SHIFT);
	}

	/* Data lane stagger programming */
	/* FIXME: Fix up value only after power analysis */

	mutex_unlock(&dev_priv->dpio_lock);

	intel_enable_dp(encoder);
}

2890 2891 2892 2893 2894 2895 2896 2897 2898 2899 2900
static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
{
	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
	struct drm_device *dev = encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(encoder->base.crtc);
	enum dpio_channel ch = vlv_dport_to_channel(dport);
	enum pipe pipe = intel_crtc->pipe;
	u32 val;

2901 2902
	intel_dp_prepare(encoder);

2903 2904
	mutex_lock(&dev_priv->dpio_lock);

2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923
	/* program left/right clock distribution */
	if (pipe != PIPE_B) {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
		if (ch == DPIO_CH0)
			val |= CHV_BUFLEFTENA1_FORCE;
		if (ch == DPIO_CH1)
			val |= CHV_BUFRIGHTENA1_FORCE;
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
	} else {
		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
		if (ch == DPIO_CH0)
			val |= CHV_BUFLEFTENA2_FORCE;
		if (ch == DPIO_CH1)
			val |= CHV_BUFRIGHTENA2_FORCE;
		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
	}

2924 2925 2926 2927 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955
	/* program clock channel usage */
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
	if (pipe != PIPE_B)
		val &= ~CHV_PCS_USEDCLKCHANNEL;
	else
		val |= CHV_PCS_USEDCLKCHANNEL;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
	if (pipe != PIPE_B)
		val &= ~CHV_PCS_USEDCLKCHANNEL;
	else
		val |= CHV_PCS_USEDCLKCHANNEL;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);

	/*
	 * This a a bit weird since generally CL
	 * matches the pipe, but here we need to
	 * pick the CL based on the port.
	 */
	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
	if (pipe != PIPE_B)
		val &= ~CHV_CMN_USEDCLKCHANNEL;
	else
		val |= CHV_CMN_USEDCLKCHANNEL;
	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);

	mutex_unlock(&dev_priv->dpio_lock);
}

2956
/*
2957 2958
 * Native read with retry for link status and receiver capability reads for
 * cases where the sink may still be asleep.
2959 2960 2961
 *
 * Sinks are *supposed* to come up within 1ms from an off state, but we're also
 * supposed to retry 3 times per the spec.
2962
 */
2963 2964 2965
static ssize_t
intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
			void *buffer, size_t size)
2966
{
2967 2968
	ssize_t ret;
	int i;
2969 2970

	for (i = 0; i < 3; i++) {
2971 2972 2973
		ret = drm_dp_dpcd_read(aux, offset, buffer, size);
		if (ret == size)
			return ret;
2974 2975
		msleep(1);
	}
2976

2977
	return ret;
2978 2979 2980 2981 2982 2983 2984
}

/*
 * Fetch AUX CH registers 0x202 - 0x207 which contain
 * link status information
 */
static bool
2985
intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
2986
{
2987 2988 2989 2990
	return intel_dp_dpcd_read_wake(&intel_dp->aux,
				       DP_LANE0_1_STATUS,
				       link_status,
				       DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
2991 2992
}

2993
/* These are source-specific values. */
2994
static uint8_t
K
Keith Packard 已提交
2995
intel_dp_voltage_max(struct intel_dp *intel_dp)
2996
{
2997
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
2998
	enum port port = dp_to_dig_port(intel_dp)->port;
K
Keith Packard 已提交
2999

3000 3001 3002
	if (INTEL_INFO(dev)->gen >= 9)
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
	else if (IS_VALLEYVIEW(dev))
3003
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3004
	else if (IS_GEN7(dev) && port == PORT_A)
3005
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3006
	else if (HAS_PCH_CPT(dev) && port != PORT_A)
3007
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
K
Keith Packard 已提交
3008
	else
3009
		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
K
Keith Packard 已提交
3010 3011 3012 3013 3014
}

static uint8_t
intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
{
3015
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
3016
	enum port port = dp_to_dig_port(intel_dp)->port;
K
Keith Packard 已提交
3017

3018 3019 3020 3021 3022 3023 3024 3025 3026 3027 3028 3029
	if (INTEL_INFO(dev)->gen >= 9) {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_3;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
		default:
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
		}
	} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3030
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3031 3032 3033 3034 3035 3036 3037
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_3;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3038
		default:
3039
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
3040
		}
3041 3042
	} else if (IS_VALLEYVIEW(dev)) {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3043 3044 3045 3046 3047 3048 3049
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_3;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3050
		default:
3051
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
3052
		}
3053
	} else if (IS_GEN7(dev) && port == PORT_A) {
K
Keith Packard 已提交
3054
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3055 3056 3057 3058 3059
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
K
Keith Packard 已提交
3060
		default:
3061
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
K
Keith Packard 已提交
3062 3063 3064
		}
	} else {
		switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3065 3066 3067 3068 3069 3070 3071
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
			return DP_TRAIN_PRE_EMPH_LEVEL_2;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
			return DP_TRAIN_PRE_EMPH_LEVEL_1;
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
K
Keith Packard 已提交
3072
		default:
3073
			return DP_TRAIN_PRE_EMPH_LEVEL_0;
K
Keith Packard 已提交
3074
		}
3075 3076 3077
	}
}

3078 3079 3080 3081 3082
static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3083 3084
	struct intel_crtc *intel_crtc =
		to_intel_crtc(dport->base.base.crtc);
3085 3086 3087
	unsigned long demph_reg_value, preemph_reg_value,
		uniqtranscale_reg_value;
	uint8_t train_set = intel_dp->train_set[0];
3088
	enum dpio_channel port = vlv_dport_to_channel(dport);
3089
	int pipe = intel_crtc->pipe;
3090 3091

	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3092
	case DP_TRAIN_PRE_EMPH_LEVEL_0:
3093 3094
		preemph_reg_value = 0x0004000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3095
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3096 3097 3098
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x552AB83A;
			break;
3099
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3100 3101 3102
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5548B83A;
			break;
3103
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3104 3105 3106
			demph_reg_value = 0x2B245555;
			uniqtranscale_reg_value = 0x5560B83A;
			break;
3107
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3108 3109 3110 3111 3112 3113 3114
			demph_reg_value = 0x2B405555;
			uniqtranscale_reg_value = 0x5598DA3A;
			break;
		default:
			return 0;
		}
		break;
3115
	case DP_TRAIN_PRE_EMPH_LEVEL_1:
3116 3117
		preemph_reg_value = 0x0002000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3118
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3119 3120 3121
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x5552B83A;
			break;
3122
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3123 3124 3125
			demph_reg_value = 0x2B404848;
			uniqtranscale_reg_value = 0x5580B83A;
			break;
3126
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3127 3128 3129 3130 3131 3132 3133
			demph_reg_value = 0x2B404040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
3134
	case DP_TRAIN_PRE_EMPH_LEVEL_2:
3135 3136
		preemph_reg_value = 0x0000000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3137
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3138 3139 3140
			demph_reg_value = 0x2B305555;
			uniqtranscale_reg_value = 0x5570B83A;
			break;
3141
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3142 3143 3144 3145 3146 3147 3148
			demph_reg_value = 0x2B2B4040;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
3149
	case DP_TRAIN_PRE_EMPH_LEVEL_3:
3150 3151
		preemph_reg_value = 0x0006000;
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3152
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163
			demph_reg_value = 0x1B405555;
			uniqtranscale_reg_value = 0x55ADDA3A;
			break;
		default:
			return 0;
		}
		break;
	default:
		return 0;
	}

3164
	mutex_lock(&dev_priv->dpio_lock);
3165 3166 3167
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
3168
			 uniqtranscale_reg_value);
3169 3170 3171 3172
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
3173
	mutex_unlock(&dev_priv->dpio_lock);
3174 3175 3176 3177

	return 0;
}

3178 3179 3180 3181 3182 3183
static uint32_t intel_chv_signal_levels(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
	struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
3184
	u32 deemph_reg_value, margin_reg_value, val;
3185 3186
	uint8_t train_set = intel_dp->train_set[0];
	enum dpio_channel ch = vlv_dport_to_channel(dport);
3187 3188
	enum pipe pipe = intel_crtc->pipe;
	int i;
3189 3190

	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3191
	case DP_TRAIN_PRE_EMPH_LEVEL_0:
3192
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3193
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3194 3195 3196
			deemph_reg_value = 128;
			margin_reg_value = 52;
			break;
3197
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3198 3199 3200
			deemph_reg_value = 128;
			margin_reg_value = 77;
			break;
3201
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3202 3203 3204
			deemph_reg_value = 128;
			margin_reg_value = 102;
			break;
3205
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3206 3207 3208 3209 3210 3211 3212 3213
			deemph_reg_value = 128;
			margin_reg_value = 154;
			/* FIXME extra to set for 1200 */
			break;
		default:
			return 0;
		}
		break;
3214
	case DP_TRAIN_PRE_EMPH_LEVEL_1:
3215
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3216
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3217 3218 3219
			deemph_reg_value = 85;
			margin_reg_value = 78;
			break;
3220
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3221 3222 3223
			deemph_reg_value = 85;
			margin_reg_value = 116;
			break;
3224
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3225 3226 3227 3228 3229 3230 3231
			deemph_reg_value = 85;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
3232
	case DP_TRAIN_PRE_EMPH_LEVEL_2:
3233
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3234
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3235 3236 3237
			deemph_reg_value = 64;
			margin_reg_value = 104;
			break;
3238
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3239 3240 3241 3242 3243 3244 3245
			deemph_reg_value = 64;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
3246
	case DP_TRAIN_PRE_EMPH_LEVEL_3:
3247
		switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3248
		case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262
			deemph_reg_value = 43;
			margin_reg_value = 154;
			break;
		default:
			return 0;
		}
		break;
	default:
		return 0;
	}

	mutex_lock(&dev_priv->dpio_lock);

	/* Clear calc init */
3263 3264
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3265 3266
	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3267 3268 3269 3270
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3271 3272
	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3273
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3274

3275 3276 3277 3278 3279 3280 3281 3282 3283 3284
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);

3285
	/* Program swing deemph */
3286 3287 3288 3289 3290 3291
	for (i = 0; i < 4; i++) {
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
		val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
	}
3292 3293

	/* Program swing margin */
3294 3295
	for (i = 0; i < 4; i++) {
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3296 3297
		val &= ~DPIO_SWING_MARGIN000_MASK;
		val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
3298 3299
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
	}
3300 3301

	/* Disable unique transition scale */
3302 3303 3304 3305 3306
	for (i = 0; i < 4; i++) {
		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
		val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
	}
3307 3308

	if (((train_set & DP_TRAIN_PRE_EMPHASIS_MASK)
3309
			== DP_TRAIN_PRE_EMPH_LEVEL_0) &&
3310
		((train_set & DP_TRAIN_VOLTAGE_SWING_MASK)
3311
			== DP_TRAIN_VOLTAGE_SWING_LEVEL_3)) {
3312 3313 3314 3315 3316 3317 3318

		/*
		 * The document said it needs to set bit 27 for ch0 and bit 26
		 * for ch1. Might be a typo in the doc.
		 * For now, for this unique transition scale selection, set bit
		 * 27 for ch0 and ch1.
		 */
3319 3320 3321 3322 3323
		for (i = 0; i < 4; i++) {
			val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
			val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
			vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
		}
3324

3325 3326 3327 3328 3329 3330
		for (i = 0; i < 4; i++) {
			val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
			val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
			val |= (0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT);
			vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
		}
3331 3332 3333
	}

	/* Start swing calculation */
3334 3335 3336 3337 3338 3339 3340
	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);

	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
	vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3341 3342 3343 3344 3345 3346 3347 3348 3349 3350 3351

	/* LRC Bypass */
	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
	val |= DPIO_LRC_BYPASS;
	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, val);

	mutex_unlock(&dev_priv->dpio_lock);

	return 0;
}

3352
static void
J
Jani Nikula 已提交
3353 3354
intel_get_adjust_train(struct intel_dp *intel_dp,
		       const uint8_t link_status[DP_LINK_STATUS_SIZE])
3355 3356 3357 3358
{
	uint8_t v = 0;
	uint8_t p = 0;
	int lane;
K
Keith Packard 已提交
3359 3360
	uint8_t voltage_max;
	uint8_t preemph_max;
3361

3362
	for (lane = 0; lane < intel_dp->lane_count; lane++) {
3363 3364
		uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
		uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
3365 3366 3367 3368 3369 3370 3371

		if (this_v > v)
			v = this_v;
		if (this_p > p)
			p = this_p;
	}

K
Keith Packard 已提交
3372
	voltage_max = intel_dp_voltage_max(intel_dp);
3373 3374
	if (v >= voltage_max)
		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
3375

K
Keith Packard 已提交
3376 3377 3378
	preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
	if (p >= preemph_max)
		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
3379 3380

	for (lane = 0; lane < 4; lane++)
3381
		intel_dp->train_set[lane] = v | p;
3382 3383 3384
}

static uint32_t
3385
intel_gen4_signal_levels(uint8_t train_set)
3386
{
3387
	uint32_t	signal_levels = 0;
3388

3389
	switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3390
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3391 3392 3393
	default:
		signal_levels |= DP_VOLTAGE_0_4;
		break;
3394
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3395 3396
		signal_levels |= DP_VOLTAGE_0_6;
		break;
3397
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3398 3399
		signal_levels |= DP_VOLTAGE_0_8;
		break;
3400
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3401 3402 3403
		signal_levels |= DP_VOLTAGE_1_2;
		break;
	}
3404
	switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3405
	case DP_TRAIN_PRE_EMPH_LEVEL_0:
3406 3407 3408
	default:
		signal_levels |= DP_PRE_EMPHASIS_0;
		break;
3409
	case DP_TRAIN_PRE_EMPH_LEVEL_1:
3410 3411
		signal_levels |= DP_PRE_EMPHASIS_3_5;
		break;
3412
	case DP_TRAIN_PRE_EMPH_LEVEL_2:
3413 3414
		signal_levels |= DP_PRE_EMPHASIS_6;
		break;
3415
	case DP_TRAIN_PRE_EMPH_LEVEL_3:
3416 3417 3418 3419 3420 3421
		signal_levels |= DP_PRE_EMPHASIS_9_5;
		break;
	}
	return signal_levels;
}

3422 3423 3424 3425
/* Gen6's DP voltage swing and pre-emphasis control */
static uint32_t
intel_gen6_edp_signal_levels(uint8_t train_set)
{
3426 3427 3428
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
3429 3430
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3431
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3432
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3433
		return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3434 3435
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3436
		return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3437 3438
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3439
		return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3440 3441
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3442
		return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3443
	default:
3444 3445 3446
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3447 3448 3449
	}
}

K
Keith Packard 已提交
3450 3451 3452 3453 3454 3455 3456
/* Gen7's DP voltage swing and pre-emphasis control */
static uint32_t
intel_gen7_edp_signal_levels(uint8_t train_set)
{
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
3457
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
K
Keith Packard 已提交
3458
		return EDP_LINK_TRAIN_400MV_0DB_IVB;
3459
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
K
Keith Packard 已提交
3460
		return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3461
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
K
Keith Packard 已提交
3462 3463
		return EDP_LINK_TRAIN_400MV_6DB_IVB;

3464
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
K
Keith Packard 已提交
3465
		return EDP_LINK_TRAIN_600MV_0DB_IVB;
3466
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
K
Keith Packard 已提交
3467 3468
		return EDP_LINK_TRAIN_600MV_3_5DB_IVB;

3469
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
K
Keith Packard 已提交
3470
		return EDP_LINK_TRAIN_800MV_0DB_IVB;
3471
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
K
Keith Packard 已提交
3472 3473 3474 3475 3476 3477 3478 3479 3480
		return EDP_LINK_TRAIN_800MV_3_5DB_IVB;

	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
		return EDP_LINK_TRAIN_500MV_0DB_IVB;
	}
}

3481 3482
/* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
static uint32_t
3483
intel_hsw_signal_levels(uint8_t train_set)
3484
{
3485 3486 3487
	int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
					 DP_TRAIN_PRE_EMPHASIS_MASK);
	switch (signal_levels) {
3488
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3489
		return DDI_BUF_TRANS_SELECT(0);
3490
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3491
		return DDI_BUF_TRANS_SELECT(1);
3492
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3493
		return DDI_BUF_TRANS_SELECT(2);
3494
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
3495
		return DDI_BUF_TRANS_SELECT(3);
3496

3497
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3498
		return DDI_BUF_TRANS_SELECT(4);
3499
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3500
		return DDI_BUF_TRANS_SELECT(5);
3501
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3502
		return DDI_BUF_TRANS_SELECT(6);
3503

3504
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3505
		return DDI_BUF_TRANS_SELECT(7);
3506
	case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3507
		return DDI_BUF_TRANS_SELECT(8);
3508 3509 3510
	default:
		DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
			      "0x%x\n", signal_levels);
3511
		return DDI_BUF_TRANS_SELECT(0);
3512 3513 3514
	}
}

3515 3516 3517 3518 3519
/* Properly updates "DP" with the correct signal levels. */
static void
intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3520
	enum port port = intel_dig_port->port;
3521 3522 3523 3524
	struct drm_device *dev = intel_dig_port->base.base.dev;
	uint32_t signal_levels, mask;
	uint8_t train_set = intel_dp->train_set[0];

3525
	if (IS_HASWELL(dev) || IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
3526 3527
		signal_levels = intel_hsw_signal_levels(train_set);
		mask = DDI_BUF_EMP_MASK;
3528 3529 3530
	} else if (IS_CHERRYVIEW(dev)) {
		signal_levels = intel_chv_signal_levels(intel_dp);
		mask = 0;
3531 3532 3533
	} else if (IS_VALLEYVIEW(dev)) {
		signal_levels = intel_vlv_signal_levels(intel_dp);
		mask = 0;
3534
	} else if (IS_GEN7(dev) && port == PORT_A) {
3535 3536
		signal_levels = intel_gen7_edp_signal_levels(train_set);
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3537
	} else if (IS_GEN6(dev) && port == PORT_A) {
3538 3539 3540 3541 3542 3543 3544 3545 3546 3547 3548 3549
		signal_levels = intel_gen6_edp_signal_levels(train_set);
		mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
	} else {
		signal_levels = intel_gen4_signal_levels(train_set);
		mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
	}

	DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);

	*DP = (*DP & ~mask) | signal_levels;
}

3550
static bool
C
Chris Wilson 已提交
3551
intel_dp_set_link_train(struct intel_dp *intel_dp,
3552
			uint32_t *DP,
3553
			uint8_t dp_train_pat)
3554
{
3555 3556
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
3557
	struct drm_i915_private *dev_priv = dev->dev_private;
3558 3559
	uint8_t buf[sizeof(intel_dp->train_set) + 1];
	int ret, len;
3560

3561
	_intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
3562

3563
	I915_WRITE(intel_dp->output_reg, *DP);
C
Chris Wilson 已提交
3564
	POSTING_READ(intel_dp->output_reg);
3565

3566 3567
	buf[0] = dp_train_pat;
	if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) ==
3568
	    DP_TRAINING_PATTERN_DISABLE) {
3569 3570 3571 3572 3573 3574
		/* don't write DP_TRAINING_LANEx_SET on disable */
		len = 1;
	} else {
		/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
		memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count);
		len = intel_dp->lane_count + 1;
3575
	}
3576

3577 3578
	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_PATTERN_SET,
				buf, len);
3579 3580

	return ret == len;
3581 3582
}

3583 3584 3585 3586
static bool
intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
			uint8_t dp_train_pat)
{
3587
	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
3588 3589 3590 3591 3592 3593
	intel_dp_set_signal_levels(intel_dp, DP);
	return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
}

static bool
intel_dp_update_link_train(struct intel_dp *intel_dp, uint32_t *DP,
J
Jani Nikula 已提交
3594
			   const uint8_t link_status[DP_LINK_STATUS_SIZE])
3595 3596 3597 3598 3599 3600 3601 3602 3603 3604 3605 3606
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret;

	intel_get_adjust_train(intel_dp, link_status);
	intel_dp_set_signal_levels(intel_dp, DP);

	I915_WRITE(intel_dp->output_reg, *DP);
	POSTING_READ(intel_dp->output_reg);

3607 3608
	ret = drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET,
				intel_dp->train_set, intel_dp->lane_count);
3609 3610 3611 3612

	return ret == intel_dp->lane_count;
}

3613 3614 3615 3616 3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630 3631 3632 3633 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643
static void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	enum port port = intel_dig_port->port;
	uint32_t val;

	if (!HAS_DDI(dev))
		return;

	val = I915_READ(DP_TP_CTL(port));
	val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
	val |= DP_TP_CTL_LINK_TRAIN_IDLE;
	I915_WRITE(DP_TP_CTL(port), val);

	/*
	 * On PORT_A we can have only eDP in SST mode. There the only reason
	 * we need to set idle transmission mode is to work around a HW issue
	 * where we enable the pipe while not in idle link-training mode.
	 * In this case there is requirement to wait for a minimum number of
	 * idle patterns to be sent.
	 */
	if (port == PORT_A)
		return;

	if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
		     1))
		DRM_ERROR("Timed out waiting for DP idle patterns\n");
}

3644
/* Enable corresponding port and start training pattern 1 */
3645
void
3646
intel_dp_start_link_train(struct intel_dp *intel_dp)
3647
{
3648
	struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
3649
	struct drm_device *dev = encoder->dev;
3650 3651
	int i;
	uint8_t voltage;
3652
	int voltage_tries, loop_tries;
C
Chris Wilson 已提交
3653
	uint32_t DP = intel_dp->DP;
3654
	uint8_t link_config[2];
3655

P
Paulo Zanoni 已提交
3656
	if (HAS_DDI(dev))
3657 3658
		intel_ddi_prepare_link_retrain(encoder);

3659
	/* Write the link configuration data */
3660 3661 3662 3663
	link_config[0] = intel_dp->link_bw;
	link_config[1] = intel_dp->lane_count;
	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
3664
	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
3665 3666 3667

	link_config[0] = 0;
	link_config[1] = DP_SET_ANSI_8B10B;
3668
	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
3669 3670

	DP |= DP_PORT_EN;
K
Keith Packard 已提交
3671

3672 3673 3674 3675 3676 3677 3678 3679
	/* clock recovery */
	if (!intel_dp_reset_link_train(intel_dp, &DP,
				       DP_TRAINING_PATTERN_1 |
				       DP_LINK_SCRAMBLING_DISABLE)) {
		DRM_ERROR("failed to enable link training\n");
		return;
	}

3680
	voltage = 0xff;
3681 3682
	voltage_tries = 0;
	loop_tries = 0;
3683
	for (;;) {
3684
		uint8_t link_status[DP_LINK_STATUS_SIZE];
3685

3686
		drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
3687 3688
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
3689
			break;
3690
		}
3691

3692
		if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3693
			DRM_DEBUG_KMS("clock recovery OK\n");
3694 3695 3696 3697 3698 3699
			break;
		}

		/* Check to see if we've tried the max voltage */
		for (i = 0; i < intel_dp->lane_count; i++)
			if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
3700
				break;
3701
		if (i == intel_dp->lane_count) {
3702 3703
			++loop_tries;
			if (loop_tries == 5) {
3704
				DRM_ERROR("too many full retries, give up\n");
3705 3706
				break;
			}
3707 3708 3709
			intel_dp_reset_link_train(intel_dp, &DP,
						  DP_TRAINING_PATTERN_1 |
						  DP_LINK_SCRAMBLING_DISABLE);
3710 3711 3712
			voltage_tries = 0;
			continue;
		}
3713

3714
		/* Check to see if we've tried the same voltage 5 times */
3715
		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
3716
			++voltage_tries;
3717
			if (voltage_tries == 5) {
3718
				DRM_ERROR("too many voltage retries, give up\n");
3719 3720 3721 3722 3723
				break;
			}
		} else
			voltage_tries = 0;
		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
3724

3725 3726 3727 3728 3729
		/* Update training set as requested by target */
		if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
			DRM_ERROR("failed to update link training\n");
			break;
		}
3730 3731
	}

3732 3733 3734
	intel_dp->DP = DP;
}

3735
void
3736 3737 3738
intel_dp_complete_link_train(struct intel_dp *intel_dp)
{
	bool channel_eq = false;
3739
	int tries, cr_tries;
3740
	uint32_t DP = intel_dp->DP;
3741 3742 3743 3744 3745
	uint32_t training_pattern = DP_TRAINING_PATTERN_2;

	/* Training Pattern 3 for HBR2 ot 1.2 devices that support it*/
	if (intel_dp->link_bw == DP_LINK_BW_5_4 || intel_dp->use_tps3)
		training_pattern = DP_TRAINING_PATTERN_3;
3746

3747
	/* channel equalization */
3748
	if (!intel_dp_set_link_train(intel_dp, &DP,
3749
				     training_pattern |
3750 3751 3752 3753 3754
				     DP_LINK_SCRAMBLING_DISABLE)) {
		DRM_ERROR("failed to start channel equalization\n");
		return;
	}

3755
	tries = 0;
3756
	cr_tries = 0;
3757 3758
	channel_eq = false;
	for (;;) {
3759
		uint8_t link_status[DP_LINK_STATUS_SIZE];
3760

3761 3762 3763 3764 3765
		if (cr_tries > 5) {
			DRM_ERROR("failed to train DP, aborting\n");
			break;
		}

3766
		drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
3767 3768
		if (!intel_dp_get_link_status(intel_dp, link_status)) {
			DRM_ERROR("failed to get link status\n");
3769
			break;
3770
		}
3771

3772
		/* Make sure clock is still ok */
3773
		if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
3774
			intel_dp_start_link_train(intel_dp);
3775
			intel_dp_set_link_train(intel_dp, &DP,
3776
						training_pattern |
3777
						DP_LINK_SCRAMBLING_DISABLE);
3778 3779 3780 3781
			cr_tries++;
			continue;
		}

3782
		if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
3783 3784 3785
			channel_eq = true;
			break;
		}
3786

3787 3788 3789 3790
		/* Try 5 times, then try clock recovery if that fails */
		if (tries > 5) {
			intel_dp_link_down(intel_dp);
			intel_dp_start_link_train(intel_dp);
3791
			intel_dp_set_link_train(intel_dp, &DP,
3792
						training_pattern |
3793
						DP_LINK_SCRAMBLING_DISABLE);
3794 3795 3796 3797
			tries = 0;
			cr_tries++;
			continue;
		}
3798

3799 3800 3801 3802 3803
		/* Update training set as requested by target */
		if (!intel_dp_update_link_train(intel_dp, &DP, link_status)) {
			DRM_ERROR("failed to update link training\n");
			break;
		}
3804
		++tries;
3805
	}
3806

3807 3808 3809 3810
	intel_dp_set_idle_link_train(intel_dp);

	intel_dp->DP = DP;

3811
	if (channel_eq)
M
Masanari Iida 已提交
3812
		DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
3813

3814 3815 3816 3817
}

void intel_dp_stop_link_train(struct intel_dp *intel_dp)
{
3818
	intel_dp_set_link_train(intel_dp, &intel_dp->DP,
3819
				DP_TRAINING_PATTERN_DISABLE);
3820 3821 3822
}

static void
C
Chris Wilson 已提交
3823
intel_dp_link_down(struct intel_dp *intel_dp)
3824
{
3825
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3826
	enum port port = intel_dig_port->port;
3827
	struct drm_device *dev = intel_dig_port->base.base.dev;
3828
	struct drm_i915_private *dev_priv = dev->dev_private;
3829 3830
	struct intel_crtc *intel_crtc =
		to_intel_crtc(intel_dig_port->base.base.crtc);
C
Chris Wilson 已提交
3831
	uint32_t DP = intel_dp->DP;
3832

3833
	if (WARN_ON(HAS_DDI(dev)))
3834 3835
		return;

3836
	if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3837 3838
		return;

3839
	DRM_DEBUG_KMS("\n");
3840

3841
	if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || port != PORT_A)) {
3842
		DP &= ~DP_LINK_TRAIN_MASK_CPT;
C
Chris Wilson 已提交
3843
		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
3844
	} else {
3845 3846 3847 3848
		if (IS_CHERRYVIEW(dev))
			DP &= ~DP_LINK_TRAIN_MASK_CHV;
		else
			DP &= ~DP_LINK_TRAIN_MASK;
C
Chris Wilson 已提交
3849
		I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
3850
	}
3851
	POSTING_READ(intel_dp->output_reg);
3852

3853
	if (HAS_PCH_IBX(dev) &&
3854
	    I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
3855
		struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
3856

3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870
		/* Hardware workaround: leaving our transcoder select
		 * set to transcoder B while it's off will prevent the
		 * corresponding HDMI output on transcoder A.
		 *
		 * Combine this with another hardware workaround:
		 * transcoder select bit can only be cleared while the
		 * port is enabled.
		 */
		DP &= ~DP_PIPEB_SELECT;
		I915_WRITE(intel_dp->output_reg, DP);

		/* Changes to enable or select take place the vblank
		 * after being written.
		 */
3871 3872 3873 3874
		if (WARN_ON(crtc == NULL)) {
			/* We should never try to disable a port without a crtc
			 * attached. For paranoia keep the code around for a
			 * bit. */
3875 3876 3877
			POSTING_READ(intel_dp->output_reg);
			msleep(50);
		} else
3878
			intel_wait_for_vblank(dev, intel_crtc->pipe);
3879 3880
	}

3881
	DP &= ~DP_AUDIO_OUTPUT_ENABLE;
C
Chris Wilson 已提交
3882 3883
	I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
	POSTING_READ(intel_dp->output_reg);
3884
	msleep(intel_dp->panel_power_down_delay);
3885 3886
}

3887 3888
static bool
intel_dp_get_dpcd(struct intel_dp *intel_dp)
3889
{
R
Rodrigo Vivi 已提交
3890 3891 3892 3893
	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;

3894 3895
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
				    sizeof(intel_dp->dpcd)) < 0)
3896
		return false; /* aux transfer failed */
3897

3898
	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3899

3900 3901 3902
	if (intel_dp->dpcd[DP_DPCD_REV] == 0)
		return false; /* DPCD not present */

3903 3904
	/* Check if the panel supports PSR */
	memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3905
	if (is_edp(intel_dp)) {
3906 3907 3908
		intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
					intel_dp->psr_dpcd,
					sizeof(intel_dp->psr_dpcd));
R
Rodrigo Vivi 已提交
3909 3910
		if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
			dev_priv->psr.sink_support = true;
3911
			DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
R
Rodrigo Vivi 已提交
3912
		}
3913 3914
	}

3915 3916 3917 3918
	/* Training Pattern 3 support */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x12 &&
	    intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED) {
		intel_dp->use_tps3 = true;
3919
		DRM_DEBUG_KMS("Displayport TPS3 supported\n");
3920 3921 3922
	} else
		intel_dp->use_tps3 = false;

3923 3924 3925 3926 3927 3928 3929
	if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
	      DP_DWN_STRM_PORT_PRESENT))
		return true; /* native DP sink */

	if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
		return true; /* no per-port downstream info */

3930 3931 3932
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
				    intel_dp->downstream_ports,
				    DP_MAX_DOWNSTREAM_PORTS) < 0)
3933 3934 3935
		return false; /* downstream port status fetch failed */

	return true;
3936 3937
}

3938 3939 3940 3941 3942 3943 3944 3945
static void
intel_dp_probe_oui(struct intel_dp *intel_dp)
{
	u8 buf[3];

	if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
		return;

3946
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3947 3948 3949
		DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);

3950
	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3951 3952 3953 3954
		DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
			      buf[0], buf[1], buf[2]);
}

3955 3956 3957 3958 3959 3960 3961 3962 3963 3964 3965 3966 3967 3968 3969 3970 3971 3972 3973 3974 3975 3976 3977 3978 3979
static bool
intel_dp_probe_mst(struct intel_dp *intel_dp)
{
	u8 buf[1];

	if (!intel_dp->can_mst)
		return false;

	if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
		return false;

	if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
		if (buf[0] & DP_MST_CAP) {
			DRM_DEBUG_KMS("Sink is MST capable\n");
			intel_dp->is_mst = true;
		} else {
			DRM_DEBUG_KMS("Sink is not MST capable\n");
			intel_dp->is_mst = false;
		}
	}

	drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
	return intel_dp->is_mst;
}

3980 3981 3982 3983 3984 3985
int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
{
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct intel_crtc *intel_crtc =
		to_intel_crtc(intel_dig_port->base.base.crtc);
R
Rodrigo Vivi 已提交
3986 3987 3988
	u8 buf;
	int test_crc_count;
	int attempts = 6;
3989

R
Rodrigo Vivi 已提交
3990
	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3991
		return -EIO;
3992

R
Rodrigo Vivi 已提交
3993
	if (!(buf & DP_TEST_CRC_SUPPORTED))
3994 3995
		return -ENOTTY;

3996 3997 3998
	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
		return -EIO;

3999
	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4000
				buf | DP_TEST_SINK_START) < 0)
4001
		return -EIO;
4002

4003
	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
4004
		return -EIO;
R
Rodrigo Vivi 已提交
4005
	test_crc_count = buf & DP_TEST_COUNT_MASK;
4006

R
Rodrigo Vivi 已提交
4007
	do {
4008 4009 4010
		if (drm_dp_dpcd_readb(&intel_dp->aux,
				      DP_TEST_SINK_MISC, &buf) < 0)
			return -EIO;
R
Rodrigo Vivi 已提交
4011 4012 4013 4014 4015 4016 4017
		intel_wait_for_vblank(dev, intel_crtc->pipe);
	} while (--attempts && (buf & DP_TEST_COUNT_MASK) == test_crc_count);

	if (attempts == 0) {
		DRM_ERROR("Panel is unable to calculate CRC after 6 vblanks\n");
		return -EIO;
	}
4018

4019
	if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0)
4020
		return -EIO;
4021

4022 4023 4024 4025 4026
	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
		return -EIO;
	if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
			       buf & ~DP_TEST_SINK_START) < 0)
		return -EIO;
4027

4028 4029 4030
	return 0;
}

4031 4032 4033
static bool
intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
4034 4035 4036
	return intel_dp_dpcd_read_wake(&intel_dp->aux,
				       DP_DEVICE_SERVICE_IRQ_VECTOR,
				       sink_irq_vector, 1) == 1;
4037 4038
}

4039 4040 4041 4042 4043 4044 4045 4046 4047 4048 4049 4050 4051 4052
static bool
intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
{
	int ret;

	ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
					     DP_SINK_COUNT_ESI,
					     sink_irq_vector, 14);
	if (ret != 14)
		return false;

	return true;
}

4053 4054 4055 4056
static void
intel_dp_handle_test_request(struct intel_dp *intel_dp)
{
	/* NAK by default */
4057
	drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, DP_TEST_NAK);
4058 4059
}

4060 4061 4062 4063 4064 4065 4066 4067 4068 4069 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079 4080 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 4095 4096 4097 4098 4099 4100 4101 4102 4103 4104 4105 4106 4107 4108 4109 4110 4111 4112 4113 4114 4115 4116
static int
intel_dp_check_mst_status(struct intel_dp *intel_dp)
{
	bool bret;

	if (intel_dp->is_mst) {
		u8 esi[16] = { 0 };
		int ret = 0;
		int retry;
		bool handled;
		bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
go_again:
		if (bret == true) {

			/* check link status - esi[10] = 0x200c */
			if (intel_dp->active_mst_links && !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
				DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
				intel_dp_start_link_train(intel_dp);
				intel_dp_complete_link_train(intel_dp);
				intel_dp_stop_link_train(intel_dp);
			}

			DRM_DEBUG_KMS("got esi %02x %02x %02x\n", esi[0], esi[1], esi[2]);
			ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);

			if (handled) {
				for (retry = 0; retry < 3; retry++) {
					int wret;
					wret = drm_dp_dpcd_write(&intel_dp->aux,
								 DP_SINK_COUNT_ESI+1,
								 &esi[1], 3);
					if (wret == 3) {
						break;
					}
				}

				bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
				if (bret == true) {
					DRM_DEBUG_KMS("got esi2 %02x %02x %02x\n", esi[0], esi[1], esi[2]);
					goto go_again;
				}
			} else
				ret = 0;

			return ret;
		} else {
			struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
			DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
			intel_dp->is_mst = false;
			drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
			/* send a hotplug event */
			drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
		}
	}
	return -EINVAL;
}

4117 4118 4119 4120 4121 4122 4123 4124
/*
 * According to DP spec
 * 5.1.2:
 *  1. Read DPCD
 *  2. Configure link according to Receiver Capabilities
 *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
 *  4. Check link status on receipt of hot-plug interrupt
 */
P
Paulo Zanoni 已提交
4125
void
C
Chris Wilson 已提交
4126
intel_dp_check_link_status(struct intel_dp *intel_dp)
4127
{
4128
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
4129
	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4130
	u8 sink_irq_vector;
4131
	u8 link_status[DP_LINK_STATUS_SIZE];
4132

4133 4134
	WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));

4135
	if (!intel_encoder->connectors_active)
4136
		return;
4137

4138
	if (WARN_ON(!intel_encoder->base.crtc))
4139 4140
		return;

4141 4142 4143
	if (!to_intel_crtc(intel_encoder->base.crtc)->active)
		return;

4144
	/* Try to read receiver status if the link appears to be up */
4145
	if (!intel_dp_get_link_status(intel_dp, link_status)) {
4146 4147 4148
		return;
	}

4149
	/* Now read the DPCD to see if it's actually running */
4150
	if (!intel_dp_get_dpcd(intel_dp)) {
4151 4152 4153
		return;
	}

4154 4155 4156 4157
	/* Try to read the source of the interrupt */
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
		/* Clear interrupt source */
4158 4159 4160
		drm_dp_dpcd_writeb(&intel_dp->aux,
				   DP_DEVICE_SERVICE_IRQ_VECTOR,
				   sink_irq_vector);
4161 4162 4163 4164 4165 4166 4167

		if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
			intel_dp_handle_test_request(intel_dp);
		if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
			DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
	}

4168
	if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4169
		DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4170
			      intel_encoder->base.name);
4171 4172
		intel_dp_start_link_train(intel_dp);
		intel_dp_complete_link_train(intel_dp);
4173
		intel_dp_stop_link_train(intel_dp);
4174
	}
4175 4176
}

4177
/* XXX this is probably wrong for multiple downstream ports */
4178
static enum drm_connector_status
4179
intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4180
{
4181 4182 4183 4184 4185 4186 4187 4188
	uint8_t *dpcd = intel_dp->dpcd;
	uint8_t type;

	if (!intel_dp_get_dpcd(intel_dp))
		return connector_status_disconnected;

	/* if there's no downstream port, we're done */
	if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
4189
		return connector_status_connected;
4190 4191

	/* If we're HPD-aware, SINK_COUNT changes dynamically */
4192 4193
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
	    intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4194
		uint8_t reg;
4195 4196 4197

		if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
					    &reg, 1) < 0)
4198
			return connector_status_unknown;
4199

4200 4201
		return DP_GET_SINK_COUNT(reg) ? connector_status_connected
					      : connector_status_disconnected;
4202 4203 4204
	}

	/* If no HPD, poke DDC gently */
4205
	if (drm_probe_ddc(&intel_dp->aux.ddc))
4206
		return connector_status_connected;
4207 4208

	/* Well we tried, say unknown for unreliable port types */
4209 4210 4211 4212 4213 4214 4215 4216 4217 4218 4219 4220
	if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
		type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
		if (type == DP_DS_PORT_TYPE_VGA ||
		    type == DP_DS_PORT_TYPE_NON_EDID)
			return connector_status_unknown;
	} else {
		type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
			DP_DWN_STRM_PORT_TYPE_MASK;
		if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
		    type == DP_DWN_STRM_PORT_TYPE_OTHER)
			return connector_status_unknown;
	}
4221 4222 4223

	/* Anything else is out of spec, warn and ignore */
	DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4224
	return connector_status_disconnected;
4225 4226
}

4227 4228 4229 4230 4231 4232 4233 4234 4235 4236 4237 4238 4239
static enum drm_connector_status
edp_detect(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	enum drm_connector_status status;

	status = intel_panel_detect(dev);
	if (status == connector_status_unknown)
		status = connector_status_connected;

	return status;
}

4240
static enum drm_connector_status
Z
Zhenyu Wang 已提交
4241
ironlake_dp_detect(struct intel_dp *intel_dp)
4242
{
4243
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
4244 4245
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4246

4247 4248 4249
	if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
		return connector_status_disconnected;

4250
	return intel_dp_detect_dpcd(intel_dp);
4251 4252
}

4253 4254
static int g4x_digital_port_connected(struct drm_device *dev,
				       struct intel_digital_port *intel_dig_port)
4255 4256
{
	struct drm_i915_private *dev_priv = dev->dev_private;
4257
	uint32_t bit;
4258

4259 4260 4261 4262 4263 4264 4265 4266 4267 4268 4269 4270
	if (IS_VALLEYVIEW(dev)) {
		switch (intel_dig_port->port) {
		case PORT_B:
			bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
			break;
		case PORT_C:
			bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
			break;
		case PORT_D:
			bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
			break;
		default:
4271
			return -EINVAL;
4272 4273 4274 4275 4276 4277 4278 4279 4280 4281 4282 4283 4284
		}
	} else {
		switch (intel_dig_port->port) {
		case PORT_B:
			bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
			break;
		case PORT_C:
			bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
			break;
		case PORT_D:
			bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
			break;
		default:
4285
			return -EINVAL;
4286
		}
4287 4288
	}

4289
	if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
4290 4291 4292 4293 4294 4295 4296 4297 4298 4299 4300 4301 4302 4303 4304 4305 4306 4307 4308 4309 4310 4311 4312 4313 4314
		return 0;
	return 1;
}

static enum drm_connector_status
g4x_dp_detect(struct intel_dp *intel_dp)
{
	struct drm_device *dev = intel_dp_to_dev(intel_dp);
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	int ret;

	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp)) {
		enum drm_connector_status status;

		status = intel_panel_detect(dev);
		if (status == connector_status_unknown)
			status = connector_status_connected;
		return status;
	}

	ret = g4x_digital_port_connected(dev, intel_dig_port);
	if (ret == -EINVAL)
		return connector_status_unknown;
	else if (ret == 0)
4315 4316
		return connector_status_disconnected;

4317
	return intel_dp_detect_dpcd(intel_dp);
Z
Zhenyu Wang 已提交
4318 4319
}

4320
static struct edid *
4321
intel_dp_get_edid(struct intel_dp *intel_dp)
4322
{
4323
	struct intel_connector *intel_connector = intel_dp->attached_connector;
4324

4325 4326 4327 4328
	/* use cached edid if we have one */
	if (intel_connector->edid) {
		/* invalid edid */
		if (IS_ERR(intel_connector->edid))
4329 4330
			return NULL;

J
Jani Nikula 已提交
4331
		return drm_edid_duplicate(intel_connector->edid);
4332 4333 4334 4335
	} else
		return drm_get_edid(&intel_connector->base,
				    &intel_dp->aux.ddc);
}
4336

4337 4338 4339 4340 4341
static void
intel_dp_set_edid(struct intel_dp *intel_dp)
{
	struct intel_connector *intel_connector = intel_dp->attached_connector;
	struct edid *edid;
4342

4343 4344 4345 4346 4347 4348 4349
	edid = intel_dp_get_edid(intel_dp);
	intel_connector->detect_edid = edid;

	if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
		intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
	else
		intel_dp->has_audio = drm_detect_monitor_audio(edid);
4350 4351
}

4352 4353
static void
intel_dp_unset_edid(struct intel_dp *intel_dp)
4354
{
4355
	struct intel_connector *intel_connector = intel_dp->attached_connector;
4356

4357 4358
	kfree(intel_connector->detect_edid);
	intel_connector->detect_edid = NULL;
4359

4360 4361
	intel_dp->has_audio = false;
}
4362

4363 4364 4365 4366 4367 4368 4369 4370 4371 4372 4373
static enum intel_display_power_domain
intel_dp_power_get(struct intel_dp *dp)
{
	struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
	enum intel_display_power_domain power_domain;

	power_domain = intel_display_port_power_domain(encoder);
	intel_display_power_get(to_i915(encoder->base.dev), power_domain);

	return power_domain;
}
4374

4375 4376 4377 4378 4379 4380
static void
intel_dp_power_put(struct intel_dp *dp,
		   enum intel_display_power_domain power_domain)
{
	struct intel_encoder *encoder = &dp_to_dig_port(dp)->base;
	intel_display_power_put(to_i915(encoder->base.dev), power_domain);
4381 4382
}

Z
Zhenyu Wang 已提交
4383 4384 4385 4386
static enum drm_connector_status
intel_dp_detect(struct drm_connector *connector, bool force)
{
	struct intel_dp *intel_dp = intel_attached_dp(connector);
4387 4388
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
4389
	struct drm_device *dev = connector->dev;
Z
Zhenyu Wang 已提交
4390
	enum drm_connector_status status;
4391
	enum intel_display_power_domain power_domain;
4392
	bool ret;
Z
Zhenyu Wang 已提交
4393

4394
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4395
		      connector->base.id, connector->name);
4396
	intel_dp_unset_edid(intel_dp);
4397

4398 4399 4400 4401
	if (intel_dp->is_mst) {
		/* MST devices are disconnected from a monitor POV */
		if (intel_encoder->type != INTEL_OUTPUT_EDP)
			intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4402
		return connector_status_disconnected;
4403 4404
	}

4405
	power_domain = intel_dp_power_get(intel_dp);
Z
Zhenyu Wang 已提交
4406

4407 4408 4409 4410
	/* Can't disconnect eDP, but you can close the lid... */
	if (is_edp(intel_dp))
		status = edp_detect(intel_dp);
	else if (HAS_PCH_SPLIT(dev))
Z
Zhenyu Wang 已提交
4411 4412 4413 4414
		status = ironlake_dp_detect(intel_dp);
	else
		status = g4x_dp_detect(intel_dp);
	if (status != connector_status_connected)
4415
		goto out;
Z
Zhenyu Wang 已提交
4416

4417 4418
	intel_dp_probe_oui(intel_dp);

4419 4420 4421 4422 4423 4424 4425 4426 4427 4428
	ret = intel_dp_probe_mst(intel_dp);
	if (ret) {
		/* if we are in MST mode then this connector
		   won't appear connected or have anything with EDID on it */
		if (intel_encoder->type != INTEL_OUTPUT_EDP)
			intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
		status = connector_status_disconnected;
		goto out;
	}

4429
	intel_dp_set_edid(intel_dp);
Z
Zhenyu Wang 已提交
4430

4431 4432
	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4433 4434 4435
	status = connector_status_connected;

out:
4436
	intel_dp_power_put(intel_dp, power_domain);
4437
	return status;
4438 4439
}

4440 4441
static void
intel_dp_force(struct drm_connector *connector)
4442
{
4443
	struct intel_dp *intel_dp = intel_attached_dp(connector);
4444
	struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4445
	enum intel_display_power_domain power_domain;
4446

4447 4448 4449
	DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
		      connector->base.id, connector->name);
	intel_dp_unset_edid(intel_dp);
4450

4451 4452
	if (connector->status != connector_status_connected)
		return;
4453

4454 4455 4456 4457 4458 4459 4460 4461 4462 4463 4464 4465 4466 4467 4468 4469 4470 4471 4472 4473 4474
	power_domain = intel_dp_power_get(intel_dp);

	intel_dp_set_edid(intel_dp);

	intel_dp_power_put(intel_dp, power_domain);

	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
}

static int intel_dp_get_modes(struct drm_connector *connector)
{
	struct intel_connector *intel_connector = to_intel_connector(connector);
	struct edid *edid;

	edid = intel_connector->detect_edid;
	if (edid) {
		int ret = intel_connector_update_modes(connector, edid);
		if (ret)
			return ret;
	}
4475

4476
	/* if eDP has no EDID, fall back to fixed mode */
4477 4478
	if (is_edp(intel_attached_dp(connector)) &&
	    intel_connector->panel.fixed_mode) {
4479
		struct drm_display_mode *mode;
4480 4481

		mode = drm_mode_duplicate(connector->dev,
4482
					  intel_connector->panel.fixed_mode);
4483
		if (mode) {
4484 4485 4486 4487
			drm_mode_probed_add(connector, mode);
			return 1;
		}
	}
4488

4489
	return 0;
4490 4491
}

4492 4493 4494 4495
static bool
intel_dp_detect_audio(struct drm_connector *connector)
{
	bool has_audio = false;
4496
	struct edid *edid;
4497

4498 4499
	edid = to_intel_connector(connector)->detect_edid;
	if (edid)
4500
		has_audio = drm_detect_monitor_audio(edid);
4501

4502 4503 4504
	return has_audio;
}

4505 4506 4507 4508 4509
static int
intel_dp_set_property(struct drm_connector *connector,
		      struct drm_property *property,
		      uint64_t val)
{
4510
	struct drm_i915_private *dev_priv = connector->dev->dev_private;
4511
	struct intel_connector *intel_connector = to_intel_connector(connector);
4512 4513
	struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4514 4515
	int ret;

4516
	ret = drm_object_property_set_value(&connector->base, property, val);
4517 4518 4519
	if (ret)
		return ret;

4520
	if (property == dev_priv->force_audio_property) {
4521 4522 4523 4524
		int i = val;
		bool has_audio;

		if (i == intel_dp->force_audio)
4525 4526
			return 0;

4527
		intel_dp->force_audio = i;
4528

4529
		if (i == HDMI_AUDIO_AUTO)
4530 4531
			has_audio = intel_dp_detect_audio(connector);
		else
4532
			has_audio = (i == HDMI_AUDIO_ON);
4533 4534

		if (has_audio == intel_dp->has_audio)
4535 4536
			return 0;

4537
		intel_dp->has_audio = has_audio;
4538 4539 4540
		goto done;
	}

4541
	if (property == dev_priv->broadcast_rgb_property) {
4542 4543 4544
		bool old_auto = intel_dp->color_range_auto;
		uint32_t old_range = intel_dp->color_range;

4545 4546 4547 4548 4549 4550 4551 4552 4553 4554 4555 4556 4557 4558 4559
		switch (val) {
		case INTEL_BROADCAST_RGB_AUTO:
			intel_dp->color_range_auto = true;
			break;
		case INTEL_BROADCAST_RGB_FULL:
			intel_dp->color_range_auto = false;
			intel_dp->color_range = 0;
			break;
		case INTEL_BROADCAST_RGB_LIMITED:
			intel_dp->color_range_auto = false;
			intel_dp->color_range = DP_COLOR_RANGE_16_235;
			break;
		default:
			return -EINVAL;
		}
4560 4561 4562 4563 4564

		if (old_auto == intel_dp->color_range_auto &&
		    old_range == intel_dp->color_range)
			return 0;

4565 4566 4567
		goto done;
	}

4568 4569 4570 4571 4572 4573 4574 4575 4576 4577 4578 4579 4580 4581 4582 4583
	if (is_edp(intel_dp) &&
	    property == connector->dev->mode_config.scaling_mode_property) {
		if (val == DRM_MODE_SCALE_NONE) {
			DRM_DEBUG_KMS("no scaling not supported\n");
			return -EINVAL;
		}

		if (intel_connector->panel.fitting_mode == val) {
			/* the eDP scaling property is not changed */
			return 0;
		}
		intel_connector->panel.fitting_mode = val;

		goto done;
	}

4584 4585 4586
	return -EINVAL;

done:
4587 4588
	if (intel_encoder->base.crtc)
		intel_crtc_restore_mode(intel_encoder->base.crtc);
4589 4590 4591 4592

	return 0;
}

4593
static void
4594
intel_dp_connector_destroy(struct drm_connector *connector)
4595
{
4596
	struct intel_connector *intel_connector = to_intel_connector(connector);
4597

4598
	kfree(intel_connector->detect_edid);
4599

4600 4601 4602
	if (!IS_ERR_OR_NULL(intel_connector->edid))
		kfree(intel_connector->edid);

4603 4604 4605
	/* Can't call is_edp() since the encoder may have been destroyed
	 * already. */
	if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4606
		intel_panel_fini(&intel_connector->panel);
4607

4608
	drm_connector_cleanup(connector);
4609
	kfree(connector);
4610 4611
}

P
Paulo Zanoni 已提交
4612
void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4613
{
4614 4615
	struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
	struct intel_dp *intel_dp = &intel_dig_port->dp;
4616

4617
	drm_dp_aux_unregister(&intel_dp->aux);
4618
	intel_dp_mst_encoder_cleanup(intel_dig_port);
4619
	drm_encoder_cleanup(encoder);
4620 4621
	if (is_edp(intel_dp)) {
		cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4622 4623 4624 4625
		/*
		 * vdd might still be enabled do to the delayed vdd off.
		 * Make sure vdd is actually turned off here.
		 */
4626
		pps_lock(intel_dp);
4627
		edp_panel_vdd_off_sync(intel_dp);
4628 4629
		pps_unlock(intel_dp);

4630 4631 4632 4633
		if (intel_dp->edp_notifier.notifier_call) {
			unregister_reboot_notifier(&intel_dp->edp_notifier);
			intel_dp->edp_notifier.notifier_call = NULL;
		}
4634
	}
4635
	kfree(intel_dig_port);
4636 4637
}

4638 4639 4640 4641 4642 4643 4644
static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
{
	struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);

	if (!is_edp(intel_dp))
		return;

4645 4646 4647 4648
	/*
	 * vdd might still be enabled do to the delayed vdd off.
	 * Make sure vdd is actually turned off here.
	 */
4649
	pps_lock(intel_dp);
4650
	edp_panel_vdd_off_sync(intel_dp);
4651
	pps_unlock(intel_dp);
4652 4653
}

4654 4655 4656 4657 4658
static void intel_dp_encoder_reset(struct drm_encoder *encoder)
{
	intel_edp_panel_vdd_sanitize(to_intel_encoder(encoder));
}

4659
static const struct drm_connector_funcs intel_dp_connector_funcs = {
4660
	.dpms = intel_connector_dpms,
4661
	.detect = intel_dp_detect,
4662
	.force = intel_dp_force,
4663
	.fill_modes = drm_helper_probe_single_connector_modes,
4664
	.set_property = intel_dp_set_property,
4665
	.destroy = intel_dp_connector_destroy,
4666 4667 4668 4669 4670
};

static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
	.get_modes = intel_dp_get_modes,
	.mode_valid = intel_dp_mode_valid,
4671
	.best_encoder = intel_best_encoder,
4672 4673 4674
};

static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4675
	.reset = intel_dp_encoder_reset,
4676
	.destroy = intel_dp_encoder_destroy,
4677 4678
};

4679
void
4680
intel_dp_hot_plug(struct intel_encoder *intel_encoder)
4681
{
4682
	return;
4683
}
4684

4685 4686 4687 4688
bool
intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
{
	struct intel_dp *intel_dp = &intel_dig_port->dp;
4689
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
4690 4691
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
4692 4693 4694
	enum intel_display_power_domain power_domain;
	bool ret = true;

4695 4696
	if (intel_dig_port->base.type != INTEL_OUTPUT_EDP)
		intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4697

4698 4699
	DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
		      port_name(intel_dig_port->port),
4700
		      long_hpd ? "long" : "short");
4701

4702 4703 4704
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);

4705
	if (long_hpd) {
4706 4707 4708 4709 4710 4711 4712 4713

		if (HAS_PCH_SPLIT(dev)) {
			if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
				goto mst_fail;
		} else {
			if (g4x_digital_port_connected(dev, intel_dig_port) != 1)
				goto mst_fail;
		}
4714 4715 4716 4717 4718 4719 4720 4721 4722 4723 4724 4725

		if (!intel_dp_get_dpcd(intel_dp)) {
			goto mst_fail;
		}

		intel_dp_probe_oui(intel_dp);

		if (!intel_dp_probe_mst(intel_dp))
			goto mst_fail;

	} else {
		if (intel_dp->is_mst) {
4726
			if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
4727 4728 4729 4730 4731 4732 4733 4734
				goto mst_fail;
		}

		if (!intel_dp->is_mst) {
			/*
			 * we'll check the link status via the normal hot plug path later -
			 * but for short hpds we should check it now
			 */
4735
			drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4736
			intel_dp_check_link_status(intel_dp);
4737
			drm_modeset_unlock(&dev->mode_config.connection_mutex);
4738 4739
		}
	}
4740 4741
	ret = false;
	goto put_power;
4742 4743 4744 4745 4746 4747 4748
mst_fail:
	/* if we were in MST mode, and device is not there get out of MST mode */
	if (intel_dp->is_mst) {
		DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
		intel_dp->is_mst = false;
		drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
	}
4749 4750 4751 4752
put_power:
	intel_display_power_put(dev_priv, power_domain);

	return ret;
4753 4754
}

4755 4756
/* Return which DP Port should be selected for Transcoder DP control */
int
4757
intel_trans_dp_port_sel(struct drm_crtc *crtc)
4758 4759
{
	struct drm_device *dev = crtc->dev;
4760 4761
	struct intel_encoder *intel_encoder;
	struct intel_dp *intel_dp;
4762

4763 4764
	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
		intel_dp = enc_to_intel_dp(&intel_encoder->base);
4765

4766 4767
		if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
		    intel_encoder->type == INTEL_OUTPUT_EDP)
C
Chris Wilson 已提交
4768
			return intel_dp->output_reg;
4769
	}
C
Chris Wilson 已提交
4770

4771 4772 4773
	return -1;
}

4774
/* check the VBT to see whether the eDP is on DP-D port */
4775
bool intel_dp_is_edp(struct drm_device *dev, enum port port)
4776 4777
{
	struct drm_i915_private *dev_priv = dev->dev_private;
4778
	union child_device_config *p_child;
4779
	int i;
4780 4781 4782 4783 4784
	static const short port_mapping[] = {
		[PORT_B] = PORT_IDPB,
		[PORT_C] = PORT_IDPC,
		[PORT_D] = PORT_IDPD,
	};
4785

4786 4787 4788
	if (port == PORT_A)
		return true;

4789
	if (!dev_priv->vbt.child_dev_num)
4790 4791
		return false;

4792 4793
	for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
		p_child = dev_priv->vbt.child_dev + i;
4794

4795
		if (p_child->common.dvo_port == port_mapping[port] &&
4796 4797
		    (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
		    (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
4798 4799 4800 4801 4802
			return true;
	}
	return false;
}

4803
void
4804 4805
intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
{
4806 4807
	struct intel_connector *intel_connector = to_intel_connector(connector);

4808
	intel_attach_force_audio_property(connector);
4809
	intel_attach_broadcast_rgb_property(connector);
4810
	intel_dp->color_range_auto = true;
4811 4812 4813

	if (is_edp(intel_dp)) {
		drm_mode_create_scaling_mode_property(connector->dev);
4814 4815
		drm_object_attach_property(
			&connector->base,
4816
			connector->dev->mode_config.scaling_mode_property,
4817 4818
			DRM_MODE_SCALE_ASPECT);
		intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
4819
	}
4820 4821
}

4822 4823 4824 4825 4826 4827 4828
static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
{
	intel_dp->last_power_cycle = jiffies;
	intel_dp->last_power_on = jiffies;
	intel_dp->last_backlight_off = jiffies;
}

4829 4830
static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
4831
				    struct intel_dp *intel_dp)
4832 4833
{
	struct drm_i915_private *dev_priv = dev->dev_private;
4834 4835
	struct edp_power_seq cur, vbt, spec,
		*final = &intel_dp->pps_delays;
4836
	u32 pp_on, pp_off, pp_div, pp;
4837
	int pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
4838

V
Ville Syrjälä 已提交
4839 4840
	lockdep_assert_held(&dev_priv->pps_mutex);

4841 4842 4843 4844
	/* already initialized? */
	if (final->t11_t12 != 0)
		return;

4845
	if (HAS_PCH_SPLIT(dev)) {
4846
		pp_ctrl_reg = PCH_PP_CONTROL;
4847 4848 4849 4850
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
4851 4852 4853 4854 4855 4856
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

		pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4857
	}
4858 4859 4860

	/* Workaround: Need to write PP_CONTROL with the unlock key as
	 * the very first thing. */
4861
	pp = ironlake_get_pp_control(intel_dp);
4862
	I915_WRITE(pp_ctrl_reg, pp);
4863

4864 4865 4866
	pp_on = I915_READ(pp_on_reg);
	pp_off = I915_READ(pp_off_reg);
	pp_div = I915_READ(pp_div_reg);
4867 4868 4869 4870 4871 4872 4873 4874 4875 4876 4877 4878 4879 4880 4881 4882 4883 4884 4885 4886

	/* Pull timing values out of registers */
	cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
		PANEL_POWER_UP_DELAY_SHIFT;

	cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
		PANEL_LIGHT_ON_DELAY_SHIFT;

	cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
		PANEL_LIGHT_OFF_DELAY_SHIFT;

	cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
		PANEL_POWER_DOWN_DELAY_SHIFT;

	cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
		       PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;

	DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);

4887
	vbt = dev_priv->vbt.edp_pps;
4888 4889 4890 4891 4892 4893 4894 4895 4896 4897 4898 4899 4900 4901 4902 4903 4904 4905

	/* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
	 * our hw here, which are all in 100usec. */
	spec.t1_t3 = 210 * 10;
	spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
	spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
	spec.t10 = 500 * 10;
	/* This one is special and actually in units of 100ms, but zero
	 * based in the hw (so we need to add 100 ms). But the sw vbt
	 * table multiplies it with 1000 to make it in units of 100usec,
	 * too. */
	spec.t11_t12 = (510 + 100) * 10;

	DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
		      vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);

	/* Use the max of the register settings and vbt. If both are
	 * unset, fall back to the spec limits. */
4906
#define assign_final(field)	final->field = (max(cur.field, vbt.field) == 0 ? \
4907 4908 4909 4910 4911 4912 4913 4914 4915
				       spec.field : \
				       max(cur.field, vbt.field))
	assign_final(t1_t3);
	assign_final(t8);
	assign_final(t9);
	assign_final(t10);
	assign_final(t11_t12);
#undef assign_final

4916
#define get_delay(field)	(DIV_ROUND_UP(final->field, 10))
4917 4918 4919 4920 4921 4922 4923
	intel_dp->panel_power_up_delay = get_delay(t1_t3);
	intel_dp->backlight_on_delay = get_delay(t8);
	intel_dp->backlight_off_delay = get_delay(t9);
	intel_dp->panel_power_down_delay = get_delay(t10);
	intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
#undef get_delay

4924 4925 4926 4927 4928 4929 4930 4931 4932 4933
	DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
		      intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
		      intel_dp->panel_power_cycle_delay);

	DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
		      intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
}

static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
4934
					      struct intel_dp *intel_dp)
4935 4936
{
	struct drm_i915_private *dev_priv = dev->dev_private;
4937 4938 4939
	u32 pp_on, pp_off, pp_div, port_sel = 0;
	int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
	int pp_on_reg, pp_off_reg, pp_div_reg;
4940
	enum port port = dp_to_dig_port(intel_dp)->port;
4941
	const struct edp_power_seq *seq = &intel_dp->pps_delays;
4942

V
Ville Syrjälä 已提交
4943
	lockdep_assert_held(&dev_priv->pps_mutex);
4944 4945 4946 4947 4948 4949

	if (HAS_PCH_SPLIT(dev)) {
		pp_on_reg = PCH_PP_ON_DELAYS;
		pp_off_reg = PCH_PP_OFF_DELAYS;
		pp_div_reg = PCH_PP_DIVISOR;
	} else {
4950 4951 4952 4953 4954
		enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);

		pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
		pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
		pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
4955 4956
	}

4957 4958 4959 4960 4961 4962 4963 4964
	/*
	 * And finally store the new values in the power sequencer. The
	 * backlight delays are set to 1 because we do manual waits on them. For
	 * T8, even BSpec recommends doing it. For T9, if we don't do this,
	 * we'll end up waiting for the backlight off delay twice: once when we
	 * do the manual sleep, and once when we disable the panel and wait for
	 * the PP_STATUS bit to become zero.
	 */
4965
	pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
4966 4967
		(1 << PANEL_LIGHT_ON_DELAY_SHIFT);
	pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
4968
		 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
4969 4970
	/* Compute the divisor for the pp clock, simply match the Bspec
	 * formula. */
4971
	pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
4972
	pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
4973 4974 4975 4976
			<< PANEL_POWER_CYCLE_DELAY_SHIFT);

	/* Haswell doesn't have any port selection bits for the panel
	 * power sequencer any more. */
4977
	if (IS_VALLEYVIEW(dev)) {
4978
		port_sel = PANEL_PORT_SELECT_VLV(port);
4979
	} else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
4980
		if (port == PORT_A)
4981
			port_sel = PANEL_PORT_SELECT_DPA;
4982
		else
4983
			port_sel = PANEL_PORT_SELECT_DPD;
4984 4985
	}

4986 4987 4988 4989 4990
	pp_on |= port_sel;

	I915_WRITE(pp_on_reg, pp_on);
	I915_WRITE(pp_off_reg, pp_off);
	I915_WRITE(pp_div_reg, pp_div);
4991 4992

	DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
4993 4994 4995
		      I915_READ(pp_on_reg),
		      I915_READ(pp_off_reg),
		      I915_READ(pp_div_reg));
4996 4997
}

4998 4999 5000 5001 5002 5003 5004 5005 5006 5007 5008 5009 5010 5011 5012 5013 5014 5015 5016 5017 5018
void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_encoder *encoder;
	struct intel_dp *intel_dp = NULL;
	struct intel_crtc_config *config = NULL;
	struct intel_crtc *intel_crtc = NULL;
	struct intel_connector *intel_connector = dev_priv->drrs.connector;
	u32 reg, val;
	enum edp_drrs_refresh_rate_type index = DRRS_HIGH_RR;

	if (refresh_rate <= 0) {
		DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
		return;
	}

	if (intel_connector == NULL) {
		DRM_DEBUG_KMS("DRRS supported for eDP only.\n");
		return;
	}

5019 5020 5021 5022 5023
	/*
	 * FIXME: This needs proper synchronization with psr state. But really
	 * hard to tell without seeing the user of this function of this code.
	 * Check locking and ordering once that lands.
	 */
5024 5025 5026 5027 5028 5029 5030 5031 5032 5033 5034 5035 5036 5037 5038 5039 5040 5041 5042 5043 5044 5045 5046 5047 5048 5049 5050 5051 5052 5053 5054 5055 5056 5057 5058 5059 5060 5061 5062 5063
	if (INTEL_INFO(dev)->gen < 8 && intel_edp_is_psr_enabled(dev)) {
		DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n");
		return;
	}

	encoder = intel_attached_encoder(&intel_connector->base);
	intel_dp = enc_to_intel_dp(&encoder->base);
	intel_crtc = encoder->new_crtc;

	if (!intel_crtc) {
		DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
		return;
	}

	config = &intel_crtc->config;

	if (intel_dp->drrs_state.type < SEAMLESS_DRRS_SUPPORT) {
		DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
		return;
	}

	if (intel_connector->panel.downclock_mode->vrefresh == refresh_rate)
		index = DRRS_LOW_RR;

	if (index == intel_dp->drrs_state.refresh_rate_type) {
		DRM_DEBUG_KMS(
			"DRRS requested for previously set RR...ignoring\n");
		return;
	}

	if (!intel_crtc->active) {
		DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
		return;
	}

	if (INTEL_INFO(dev)->gen > 6 && INTEL_INFO(dev)->gen < 8) {
		reg = PIPECONF(intel_crtc->config.cpu_transcoder);
		val = I915_READ(reg);
		if (index > DRRS_HIGH_RR) {
			val |= PIPECONF_EDP_RR_MODE_SWITCH;
5064
			intel_dp_set_m_n(intel_crtc);
5065 5066 5067 5068 5069 5070 5071 5072 5073 5074 5075 5076 5077 5078 5079 5080 5081 5082 5083 5084 5085 5086
		} else {
			val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
		}
		I915_WRITE(reg, val);
	}

	/*
	 * mutex taken to ensure that there is no race between differnt
	 * drrs calls trying to update refresh rate. This scenario may occur
	 * in future when idleness detection based DRRS in kernel and
	 * possible calls from user space to set differnt RR are made.
	 */

	mutex_lock(&intel_dp->drrs_state.mutex);

	intel_dp->drrs_state.refresh_rate_type = index;

	mutex_unlock(&intel_dp->drrs_state.mutex);

	DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
}

5087 5088 5089 5090 5091 5092 5093 5094 5095 5096 5097 5098 5099 5100 5101 5102 5103
static struct drm_display_mode *
intel_dp_drrs_init(struct intel_digital_port *intel_dig_port,
			struct intel_connector *intel_connector,
			struct drm_display_mode *fixed_mode)
{
	struct drm_connector *connector = &intel_connector->base;
	struct intel_dp *intel_dp = &intel_dig_port->dp;
	struct drm_device *dev = intel_dig_port->base.base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_display_mode *downclock_mode = NULL;

	if (INTEL_INFO(dev)->gen <= 6) {
		DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
		return NULL;
	}

	if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5104
		DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5105 5106 5107 5108 5109 5110 5111
		return NULL;
	}

	downclock_mode = intel_find_panel_downclock
					(dev, fixed_mode, connector);

	if (!downclock_mode) {
5112
		DRM_DEBUG_KMS("DRRS not supported\n");
5113 5114 5115
		return NULL;
	}

5116 5117 5118 5119
	dev_priv->drrs.connector = intel_connector;

	mutex_init(&intel_dp->drrs_state.mutex);

5120 5121 5122
	intel_dp->drrs_state.type = dev_priv->vbt.drrs_type;

	intel_dp->drrs_state.refresh_rate_type = DRRS_HIGH_RR;
5123
	DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5124 5125 5126
	return downclock_mode;
}

5127 5128 5129 5130 5131 5132 5133 5134 5135 5136 5137
void intel_edp_panel_vdd_sanitize(struct intel_encoder *intel_encoder)
{
	struct drm_device *dev = intel_encoder->base.dev;
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct intel_dp *intel_dp;
	enum intel_display_power_domain power_domain;

	if (intel_encoder->type != INTEL_OUTPUT_EDP)
		return;

	intel_dp = enc_to_intel_dp(&intel_encoder->base);
5138 5139 5140

	pps_lock(intel_dp);

5141
	if (!edp_have_panel_vdd(intel_dp))
V
Ville Syrjälä 已提交
5142
		goto out;
5143 5144 5145 5146 5147 5148 5149 5150 5151 5152 5153
	/*
	 * The VDD bit needs a power domain reference, so if the bit is
	 * already enabled when we boot or resume, grab this reference and
	 * schedule a vdd off, so we don't hold on to the reference
	 * indefinitely.
	 */
	DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
	power_domain = intel_display_port_power_domain(intel_encoder);
	intel_display_power_get(dev_priv, power_domain);

	edp_panel_vdd_schedule_off(intel_dp);
V
Ville Syrjälä 已提交
5154
 out:
5155
	pps_unlock(intel_dp);
5156 5157
}

5158
static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5159
				     struct intel_connector *intel_connector)
5160 5161 5162
{
	struct drm_connector *connector = &intel_connector->base;
	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5163 5164
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
5165 5166
	struct drm_i915_private *dev_priv = dev->dev_private;
	struct drm_display_mode *fixed_mode = NULL;
5167
	struct drm_display_mode *downclock_mode = NULL;
5168 5169 5170 5171
	bool has_dpcd;
	struct drm_display_mode *scan;
	struct edid *edid;

5172 5173
	intel_dp->drrs_state.type = DRRS_NOT_SUPPORTED;

5174 5175 5176
	if (!is_edp(intel_dp))
		return true;

5177
	intel_edp_panel_vdd_sanitize(intel_encoder);
5178

5179 5180 5181 5182 5183 5184 5185 5186 5187 5188 5189 5190 5191 5192 5193
	/* Cache DPCD and EDID for edp. */
	has_dpcd = intel_dp_get_dpcd(intel_dp);

	if (has_dpcd) {
		if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
			dev_priv->no_aux_handshake =
				intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
				DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
	} else {
		/* if this fails, presume the device is a ghost */
		DRM_INFO("failed to retrieve link info, disabling eDP\n");
		return false;
	}

	/* We now know it's not a ghost, init power sequence regs. */
5194
	pps_lock(intel_dp);
5195
	intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5196
	pps_unlock(intel_dp);
5197

5198
	mutex_lock(&dev->mode_config.mutex);
5199
	edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5200 5201 5202 5203 5204 5205 5206 5207 5208 5209 5210 5211 5212 5213 5214 5215 5216 5217
	if (edid) {
		if (drm_add_edid_modes(connector, edid)) {
			drm_mode_connector_update_edid_property(connector,
								edid);
			drm_edid_to_eld(connector, edid);
		} else {
			kfree(edid);
			edid = ERR_PTR(-EINVAL);
		}
	} else {
		edid = ERR_PTR(-ENOENT);
	}
	intel_connector->edid = edid;

	/* prefer fixed mode from EDID if available */
	list_for_each_entry(scan, &connector->probed_modes, head) {
		if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
			fixed_mode = drm_mode_duplicate(dev, scan);
5218 5219 5220
			downclock_mode = intel_dp_drrs_init(
						intel_dig_port,
						intel_connector, fixed_mode);
5221 5222 5223 5224 5225 5226 5227 5228 5229 5230 5231
			break;
		}
	}

	/* fallback to VBT if available for eDP */
	if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
		fixed_mode = drm_mode_duplicate(dev,
					dev_priv->vbt.lfp_lvds_vbt_mode);
		if (fixed_mode)
			fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
	}
5232
	mutex_unlock(&dev->mode_config.mutex);
5233

5234 5235 5236 5237 5238
	if (IS_VALLEYVIEW(dev)) {
		intel_dp->edp_notifier.notifier_call = edp_notify_handler;
		register_reboot_notifier(&intel_dp->edp_notifier);
	}

5239
	intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5240
	intel_connector->panel.backlight_power = intel_edp_backlight_power;
5241 5242 5243 5244 5245
	intel_panel_setup_backlight(connector);

	return true;
}

5246
bool
5247 5248
intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
			struct intel_connector *intel_connector)
5249
{
5250 5251 5252 5253
	struct drm_connector *connector = &intel_connector->base;
	struct intel_dp *intel_dp = &intel_dig_port->dp;
	struct intel_encoder *intel_encoder = &intel_dig_port->base;
	struct drm_device *dev = intel_encoder->base.dev;
5254
	struct drm_i915_private *dev_priv = dev->dev_private;
5255
	enum port port = intel_dig_port->port;
5256
	int type;
5257

5258 5259
	intel_dp->pps_pipe = INVALID_PIPE;

5260
	/* intel_dp vfuncs */
5261 5262 5263
	if (INTEL_INFO(dev)->gen >= 9)
		intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
	else if (IS_VALLEYVIEW(dev))
5264 5265 5266 5267 5268 5269 5270 5271
		intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
	else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
		intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
	else if (HAS_PCH_SPLIT(dev))
		intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
	else
		intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;

5272 5273 5274 5275
	if (INTEL_INFO(dev)->gen >= 9)
		intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
	else
		intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
5276

5277 5278
	/* Preserve the current hw state. */
	intel_dp->DP = I915_READ(intel_dp->output_reg);
5279
	intel_dp->attached_connector = intel_connector;
5280

5281
	if (intel_dp_is_edp(dev, port))
5282
		type = DRM_MODE_CONNECTOR_eDP;
5283 5284
	else
		type = DRM_MODE_CONNECTOR_DisplayPort;
5285

5286 5287 5288 5289 5290 5291 5292 5293
	/*
	 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
	 * for DP the encoder type can be set by the caller to
	 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
	 */
	if (type == DRM_MODE_CONNECTOR_eDP)
		intel_encoder->type = INTEL_OUTPUT_EDP;

5294 5295 5296 5297 5298
	/* eDP only on port B and/or C on vlv/chv */
	if (WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) &&
		    port != PORT_B && port != PORT_C))
		return false;

5299 5300 5301 5302
	DRM_DEBUG_KMS("Adding %s connector on port %c\n",
			type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
			port_name(port));

5303
	drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5304 5305 5306 5307 5308
	drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);

	connector->interlace_allowed = true;
	connector->doublescan_allowed = 0;

5309
	INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5310
			  edp_panel_vdd_work);
5311

5312
	intel_connector_attach_encoder(intel_connector, intel_encoder);
5313
	drm_connector_register(connector);
5314

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Paulo Zanoni 已提交
5315
	if (HAS_DDI(dev))
5316 5317 5318
		intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
	else
		intel_connector->get_hw_state = intel_connector_get_hw_state;
5319
	intel_connector->unregister = intel_dp_connector_unregister;
5320

5321
	/* Set up the hotplug pin. */
5322 5323
	switch (port) {
	case PORT_A:
5324
		intel_encoder->hpd_pin = HPD_PORT_A;
5325 5326
		break;
	case PORT_B:
5327
		intel_encoder->hpd_pin = HPD_PORT_B;
5328 5329
		break;
	case PORT_C:
5330
		intel_encoder->hpd_pin = HPD_PORT_C;
5331 5332
		break;
	case PORT_D:
5333
		intel_encoder->hpd_pin = HPD_PORT_D;
5334 5335
		break;
	default:
5336
		BUG();
5337 5338
	}

5339
	if (is_edp(intel_dp)) {
5340
		pps_lock(intel_dp);
5341 5342 5343 5344
		if (IS_VALLEYVIEW(dev)) {
			vlv_initial_power_sequencer_setup(intel_dp);
		} else {
			intel_dp_init_panel_power_timestamps(intel_dp);
5345
			intel_dp_init_panel_power_sequencer(dev, intel_dp);
5346
		}
5347
		pps_unlock(intel_dp);
5348
	}
5349

5350
	intel_dp_aux_init(intel_dp, intel_connector);
5351

5352 5353 5354
	/* init MST on ports that can support it */
	if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
		if (port == PORT_B || port == PORT_C || port == PORT_D) {
5355 5356
			intel_dp_mst_encoder_init(intel_dig_port,
						  intel_connector->base.base.id);
5357 5358 5359
		}
	}

5360
	if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5361
		drm_dp_aux_unregister(&intel_dp->aux);
5362 5363
		if (is_edp(intel_dp)) {
			cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5364 5365 5366 5367
			/*
			 * vdd might still be enabled do to the delayed vdd off.
			 * Make sure vdd is actually turned off here.
			 */
5368
			pps_lock(intel_dp);
5369
			edp_panel_vdd_off_sync(intel_dp);
5370
			pps_unlock(intel_dp);
5371
		}
5372
		drm_connector_unregister(connector);
5373
		drm_connector_cleanup(connector);
5374
		return false;
5375
	}
5376

5377 5378
	intel_dp_add_properties(intel_dp, connector);

5379 5380 5381 5382 5383 5384 5385 5386
	/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
	 * 0xd.  Failure to do so will result in spurious interrupts being
	 * generated on the port when a cable is not attached.
	 */
	if (IS_G4X(dev) && !IS_GM45(dev)) {
		u32 temp = I915_READ(PEG_BAND_GAP_DATA);
		I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
	}
5387 5388

	return true;
5389
}
5390 5391 5392 5393

void
intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
{
5394
	struct drm_i915_private *dev_priv = dev->dev_private;
5395 5396 5397 5398 5399
	struct intel_digital_port *intel_dig_port;
	struct intel_encoder *intel_encoder;
	struct drm_encoder *encoder;
	struct intel_connector *intel_connector;

5400
	intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
5401 5402 5403
	if (!intel_dig_port)
		return;

5404
	intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
5405 5406 5407 5408 5409 5410 5411 5412 5413 5414 5415
	if (!intel_connector) {
		kfree(intel_dig_port);
		return;
	}

	intel_encoder = &intel_dig_port->base;
	encoder = &intel_encoder->base;

	drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
			 DRM_MODE_ENCODER_TMDS);

5416
	intel_encoder->compute_config = intel_dp_compute_config;
P
Paulo Zanoni 已提交
5417 5418
	intel_encoder->disable = intel_disable_dp;
	intel_encoder->get_hw_state = intel_dp_get_hw_state;
5419
	intel_encoder->get_config = intel_dp_get_config;
5420
	intel_encoder->suspend = intel_dp_encoder_suspend;
5421
	if (IS_CHERRYVIEW(dev)) {
5422
		intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
5423 5424
		intel_encoder->pre_enable = chv_pre_enable_dp;
		intel_encoder->enable = vlv_enable_dp;
5425
		intel_encoder->post_disable = chv_post_disable_dp;
5426
	} else if (IS_VALLEYVIEW(dev)) {
5427
		intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
5428 5429
		intel_encoder->pre_enable = vlv_pre_enable_dp;
		intel_encoder->enable = vlv_enable_dp;
5430
		intel_encoder->post_disable = vlv_post_disable_dp;
5431
	} else {
5432 5433
		intel_encoder->pre_enable = g4x_pre_enable_dp;
		intel_encoder->enable = g4x_enable_dp;
5434 5435
		if (INTEL_INFO(dev)->gen >= 5)
			intel_encoder->post_disable = ilk_post_disable_dp;
5436
	}
5437

5438
	intel_dig_port->port = port;
5439 5440
	intel_dig_port->dp.output_reg = output_reg;

P
Paulo Zanoni 已提交
5441
	intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
5442 5443 5444 5445 5446 5447 5448 5449
	if (IS_CHERRYVIEW(dev)) {
		if (port == PORT_D)
			intel_encoder->crtc_mask = 1 << 2;
		else
			intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
	} else {
		intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
	}
5450
	intel_encoder->cloneable = 0;
5451 5452
	intel_encoder->hot_plug = intel_dp_hot_plug;

5453 5454 5455
	intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
	dev_priv->hpd_irq_port[port] = intel_dig_port;

5456 5457 5458
	if (!intel_dp_init_connector(intel_dig_port, intel_connector)) {
		drm_encoder_cleanup(encoder);
		kfree(intel_dig_port);
5459
		kfree(intel_connector);
5460
	}
5461
}
5462 5463 5464 5465 5466 5467 5468 5469 5470 5471 5472 5473 5474 5475 5476 5477 5478 5479 5480 5481 5482 5483 5484 5485 5486 5487 5488 5489 5490 5491 5492 5493 5494 5495 5496 5497 5498 5499 5500 5501 5502 5503 5504

void intel_dp_mst_suspend(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	/* disable MST */
	for (i = 0; i < I915_MAX_PORTS; i++) {
		struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
		if (!intel_dig_port)
			continue;

		if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
			if (!intel_dig_port->dp.can_mst)
				continue;
			if (intel_dig_port->dp.is_mst)
				drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
		}
	}
}

void intel_dp_mst_resume(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	for (i = 0; i < I915_MAX_PORTS; i++) {
		struct intel_digital_port *intel_dig_port = dev_priv->hpd_irq_port[i];
		if (!intel_dig_port)
			continue;
		if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
			int ret;

			if (!intel_dig_port->dp.can_mst)
				continue;

			ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
			if (ret != 0) {
				intel_dp_check_mst_status(&intel_dig_port->dp);
			}
		}
	}
}