i915_drv.h 112.4 KB
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/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#ifndef _I915_DRV_H_
#define _I915_DRV_H_

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#include <uapi/drm/i915_drm.h>
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#include <uapi/drm/drm_fourcc.h>
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#include <linux/io-mapping.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/backlight.h>
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#include <linux/hashtable.h>
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#include <linux/intel-iommu.h>
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#include <linux/kref.h>
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#include <linux/pm_qos.h>
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#include <linux/shmem_fs.h>

#include <drm/drmP.h>
#include <drm/intel-gtt.h>
#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
#include <drm/drm_gem.h>

#include "i915_params.h"
#include "i915_reg.h"

#include "intel_bios.h"
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#include "intel_dpll_mgr.h"
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#include "intel_guc.h"
#include "intel_lrc.h"
#include "intel_ringbuffer.h"

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#include "i915_gem.h"
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#include "i915_gem_gtt.h"
#include "i915_gem_render_state.h"
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/* General customization:
 */

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
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#define DRIVER_DATE		"20160425"
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#undef WARN_ON
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/* Many gcc seem to no see through this and fall over :( */
#if 0
#define WARN_ON(x) ({ \
	bool __i915_warn_cond = (x); \
	if (__builtin_constant_p(__i915_warn_cond)) \
		BUILD_BUG_ON(__i915_warn_cond); \
	WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
#else
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#define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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#endif

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#undef WARN_ON_ONCE
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#define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
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#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
			     (long) (x), __func__);
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/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 * which may not necessarily be a user visible problem.  This will either
 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 * enable distros and users to tailor their preferred amount of i915 abrt
 * spam.
 */
#define I915_STATE_WARN(condition, format...) ({			\
	int __ret_warn_on = !!(condition);				\
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	if (unlikely(__ret_warn_on))					\
		if (!WARN(i915.verbose_state_checks, format))		\
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			DRM_ERROR(format);				\
	unlikely(__ret_warn_on);					\
})

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#define I915_STATE_WARN_ON(x)						\
	I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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bool __i915_inject_load_failure(const char *func, int line);
#define i915_inject_load_failure() \
	__i915_inject_load_failure(__func__, __LINE__)

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static inline const char *yesno(bool v)
{
	return v ? "yes" : "no";
}

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static inline const char *onoff(bool v)
{
	return v ? "on" : "off";
}

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enum pipe {
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	INVALID_PIPE = -1,
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	PIPE_A = 0,
	PIPE_B,
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	PIPE_C,
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	_PIPE_EDP,
	I915_MAX_PIPES = _PIPE_EDP
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};
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#define pipe_name(p) ((p) + 'A')
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enum transcoder {
	TRANSCODER_A = 0,
	TRANSCODER_B,
	TRANSCODER_C,
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	TRANSCODER_EDP,
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	TRANSCODER_DSI_A,
	TRANSCODER_DSI_C,
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	I915_MAX_TRANSCODERS
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};
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static inline const char *transcoder_name(enum transcoder transcoder)
{
	switch (transcoder) {
	case TRANSCODER_A:
		return "A";
	case TRANSCODER_B:
		return "B";
	case TRANSCODER_C:
		return "C";
	case TRANSCODER_EDP:
		return "EDP";
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	case TRANSCODER_DSI_A:
		return "DSI A";
	case TRANSCODER_DSI_C:
		return "DSI C";
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	default:
		return "<invalid>";
	}
}
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static inline bool transcoder_is_dsi(enum transcoder transcoder)
{
	return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
}

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/*
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 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 * number of planes per CRTC.  Not all platforms really have this many planes,
 * which means some arrays of size I915_MAX_PLANES may have unused entries
 * between the topmost sprite plane and the cursor plane.
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 */
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enum plane {
	PLANE_A = 0,
	PLANE_B,
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	PLANE_C,
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	PLANE_CURSOR,
	I915_MAX_PLANES,
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};
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#define plane_name(p) ((p) + 'A')
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#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
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enum port {
	PORT_A = 0,
	PORT_B,
	PORT_C,
	PORT_D,
	PORT_E,
	I915_MAX_PORTS
};
#define port_name(p) ((p) + 'A')

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#define I915_NUM_PHYS_VLV 2
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enum dpio_channel {
	DPIO_CH0,
	DPIO_CH1
};

enum dpio_phy {
	DPIO_PHY0,
	DPIO_PHY1
};

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enum intel_display_power_domain {
	POWER_DOMAIN_PIPE_A,
	POWER_DOMAIN_PIPE_B,
	POWER_DOMAIN_PIPE_C,
	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
	POWER_DOMAIN_TRANSCODER_A,
	POWER_DOMAIN_TRANSCODER_B,
	POWER_DOMAIN_TRANSCODER_C,
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	POWER_DOMAIN_TRANSCODER_EDP,
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	POWER_DOMAIN_TRANSCODER_DSI_A,
	POWER_DOMAIN_TRANSCODER_DSI_C,
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	POWER_DOMAIN_PORT_DDI_A_LANES,
	POWER_DOMAIN_PORT_DDI_B_LANES,
	POWER_DOMAIN_PORT_DDI_C_LANES,
	POWER_DOMAIN_PORT_DDI_D_LANES,
	POWER_DOMAIN_PORT_DDI_E_LANES,
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	POWER_DOMAIN_PORT_DSI,
	POWER_DOMAIN_PORT_CRT,
	POWER_DOMAIN_PORT_OTHER,
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	POWER_DOMAIN_VGA,
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	POWER_DOMAIN_AUDIO,
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	POWER_DOMAIN_PLLS,
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	POWER_DOMAIN_AUX_A,
	POWER_DOMAIN_AUX_B,
	POWER_DOMAIN_AUX_C,
	POWER_DOMAIN_AUX_D,
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	POWER_DOMAIN_GMBUS,
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	POWER_DOMAIN_MODESET,
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	POWER_DOMAIN_INIT,
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	POWER_DOMAIN_NUM,
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};

#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
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#define POWER_DOMAIN_TRANSCODER(tran) \
	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
	 (tran) + POWER_DOMAIN_TRANSCODER_A)
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enum hpd_pin {
	HPD_NONE = 0,
	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
	HPD_CRT,
	HPD_SDVO_B,
	HPD_SDVO_C,
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	HPD_PORT_A,
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	HPD_PORT_B,
	HPD_PORT_C,
	HPD_PORT_D,
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	HPD_PORT_E,
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	HPD_NUM_PINS
};

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#define for_each_hpd_pin(__pin) \
	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)

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struct i915_hotplug {
	struct work_struct hotplug_work;

	struct {
		unsigned long last_jiffies;
		int count;
		enum {
			HPD_ENABLED = 0,
			HPD_DISABLED = 1,
			HPD_MARK_DISABLED = 2
		} state;
	} stats[HPD_NUM_PINS];
	u32 event_bits;
	struct delayed_work reenable_work;

	struct intel_digital_port *irq_port[I915_MAX_PORTS];
	u32 long_port_mask;
	u32 short_port_mask;
	struct work_struct dig_port_work;

	/*
	 * if we get a HPD irq from DP and a HPD irq from non-DP
	 * the non-DP HPD could block the workqueue on a mode config
	 * mutex getting, that userspace may have taken. However
	 * userspace is waiting on the DP workqueue to run which is
	 * blocked behind the non-DP one.
	 */
	struct workqueue_struct *dp_wq;
};

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#define I915_GEM_GPU_DOMAINS \
	(I915_GEM_DOMAIN_RENDER | \
	 I915_GEM_DOMAIN_SAMPLER | \
	 I915_GEM_DOMAIN_COMMAND | \
	 I915_GEM_DOMAIN_INSTRUCTION | \
	 I915_GEM_DOMAIN_VERTEX)
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#define for_each_pipe(__dev_priv, __p) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
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#define for_each_pipe_masked(__dev_priv, __p, __mask) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
		for_each_if ((__mask) & (1 << (__p)))
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#define for_each_plane(__dev_priv, __pipe, __p)				\
	for ((__p) = 0;							\
	     (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;	\
	     (__p)++)
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#define for_each_sprite(__dev_priv, __p, __s)				\
	for ((__s) = 0;							\
	     (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];	\
	     (__s)++)
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#define for_each_port_masked(__port, __ports_mask) \
	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	\
		for_each_if ((__ports_mask) & (1 << (__port)))

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#define for_each_crtc(dev, crtc) \
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)

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#define for_each_intel_plane(dev, intel_plane) \
	list_for_each_entry(intel_plane,			\
			    &dev->mode_config.plane_list,	\
			    base.head)

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#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)	\
	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
			    base.head)					\
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		for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
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#define for_each_intel_crtc(dev, intel_crtc) \
	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)

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#define for_each_intel_encoder(dev, intel_encoder)		\
	list_for_each_entry(intel_encoder,			\
			    &(dev)->mode_config.encoder_list,	\
			    base.head)

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#define for_each_intel_connector(dev, intel_connector)		\
	list_for_each_entry(intel_connector,			\
			    &dev->mode_config.connector_list,	\
			    base.head)

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#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
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		for_each_if ((intel_encoder)->base.crtc == (__crtc))
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#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
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		for_each_if ((intel_connector)->base.encoder == (__encoder))
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#define for_each_power_domain(domain, mask)				\
	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
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		for_each_if ((1 << (domain)) & (mask))
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struct drm_i915_private;
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struct i915_mm_struct;
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struct i915_mmu_object;
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struct drm_i915_file_private {
	struct drm_i915_private *dev_priv;
	struct drm_file *file;

	struct {
		spinlock_t lock;
		struct list_head request_list;
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/* 20ms is a fairly arbitrary limit (greater than the average frame time)
 * chosen to prevent the CPU getting more than a frame ahead of the GPU
 * (when using lax throttling for the frontbuffer). We also use it to
 * offer free GPU waitboosts for severely congested workloads.
 */
#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
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	} mm;
	struct idr context_idr;

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	struct intel_rps_client {
		struct list_head link;
		unsigned boosts;
	} rps;
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	unsigned int bsd_ring;
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};

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/* Used by dp and fdi links */
struct intel_link_m_n {
	uint32_t	tu;
	uint32_t	gmch_m;
	uint32_t	gmch_n;
	uint32_t	link_m;
	uint32_t	link_n;
};

void intel_link_compute_m_n(int bpp, int nlanes,
			    int pixel_clock, int link_clock,
			    struct intel_link_m_n *m_n);

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/* Interface history:
 *
 * 1.1: Original.
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 * 1.2: Add Power Management
 * 1.3: Add vblank support
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 * 1.4: Fix cmdbuffer path, add heap destroy
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 * 1.5: Add vblank pipe configuration
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 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
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 */
#define DRIVER_MAJOR		1
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#define DRIVER_MINOR		6
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#define DRIVER_PATCHLEVEL	0

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#define WATCH_LISTS	0
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struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
struct opregion_asle;

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struct intel_opregion {
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	struct opregion_header *header;
	struct opregion_acpi *acpi;
	struct opregion_swsci *swsci;
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	u32 swsci_gbda_sub_functions;
	u32 swsci_sbcb_sub_functions;
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	struct opregion_asle *asle;
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	void *rvda;
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	const void *vbt;
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	u32 vbt_size;
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	u32 *lid_state;
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	struct work_struct asle_work;
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};
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#define OPREGION_SIZE            (8*1024)
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struct intel_overlay;
struct intel_overlay_error_state;

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#define I915_FENCE_REG_NONE -1
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#define I915_MAX_NUM_FENCES 32
/* 32 fences + sign bit for FENCE_REG_NONE */
#define I915_MAX_NUM_FENCE_BITS 6
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struct drm_i915_fence_reg {
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	struct list_head lru_list;
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	struct drm_i915_gem_object *obj;
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	int pin_count;
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};
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struct sdvo_device_mapping {
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	u8 initialized;
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	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
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	u8 i2c_pin;
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	u8 ddc_pin;
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};

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struct intel_display_error_state;

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struct drm_i915_error_state {
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	struct kref ref;
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	struct timeval time;

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	char error_msg[128];
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	int iommu;
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	u32 reset_count;
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	u32 suspend_count;
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	/* Generic register state */
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	u32 eir;
	u32 pgtbl_er;
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	u32 ier;
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	u32 gtier[4];
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	u32 ccid;
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	u32 derrmr;
	u32 forcewake;
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	u32 error; /* gen6+ */
	u32 err_int; /* gen7 */
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	u32 fault_data0; /* gen8, gen9 */
	u32 fault_data1; /* gen8, gen9 */
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	u32 done_reg;
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	u32 gac_eco;
	u32 gam_ecochk;
	u32 gab_ctl;
	u32 gfx_mode;
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	u32 extra_instdone[I915_NUM_INSTDONE_REG];
	u64 fence[I915_MAX_NUM_FENCES];
	struct intel_overlay_error_state *overlay;
	struct intel_display_error_state *display;
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	struct drm_i915_error_object *semaphore_obj;
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	struct drm_i915_error_ring {
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		bool valid;
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		/* Software tracked state */
		bool waiting;
		int hangcheck_score;
		enum intel_ring_hangcheck_action hangcheck_action;
		int num_requests;

		/* our own tracking of ring head and tail */
		u32 cpu_ring_head;
		u32 cpu_ring_tail;

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		u32 last_seqno;
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		u32 semaphore_seqno[I915_NUM_ENGINES - 1];
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		/* Register state */
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		u32 start;
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		u32 tail;
		u32 head;
		u32 ctl;
		u32 hws;
		u32 ipeir;
		u32 ipehr;
		u32 instdone;
		u32 bbstate;
		u32 instpm;
		u32 instps;
		u32 seqno;
		u64 bbaddr;
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		u64 acthd;
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		u32 fault_reg;
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		u64 faddr;
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		u32 rc_psmi; /* sleep state */
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		u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
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		struct drm_i915_error_object {
			int page_count;
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			u64 gtt_offset;
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			u32 *pages[0];
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		} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
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		struct drm_i915_error_object *wa_ctx;

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		struct drm_i915_error_request {
			long jiffies;
			u32 seqno;
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			u32 tail;
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		} *requests;
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		struct {
			u32 gfx_mode;
			union {
				u64 pdp[4];
				u32 pp_dir_base;
			};
		} vm_info;
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		pid_t pid;
		char comm[TASK_COMM_LEN];
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	} ring[I915_NUM_ENGINES];
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	struct drm_i915_error_buffer {
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		u32 size;
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		u32 name;
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		u32 rseqno[I915_NUM_ENGINES], wseqno;
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		u64 gtt_offset;
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		u32 read_domains;
		u32 write_domain;
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		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
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		s32 pinned:2;
		u32 tiling:2;
		u32 dirty:1;
		u32 purgeable:1;
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		u32 userptr:1;
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		s32 ring:4;
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		u32 cache_level:3;
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	} **active_bo, **pinned_bo;
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	u32 *active_bo_count, *pinned_bo_count;
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	u32 vm_count;
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};

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struct intel_connector;
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struct intel_encoder;
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struct intel_crtc_state;
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struct intel_initial_plane_config;
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struct intel_crtc;
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struct intel_limit;
struct dpll;
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struct drm_i915_display_funcs {
	int (*get_display_clock_speed)(struct drm_device *dev);
	int (*get_fifo_size)(struct drm_device *dev, int plane);
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	int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
586 587 588 589 590
	int (*compute_intermediate_wm)(struct drm_device *dev,
				       struct intel_crtc *intel_crtc,
				       struct intel_crtc_state *newstate);
	void (*initial_watermarks)(struct intel_crtc_state *cstate);
	void (*optimize_watermarks)(struct intel_crtc_state *cstate);
591
	void (*update_wm)(struct drm_crtc *crtc);
592 593
	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
	void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
594 595 596
	/* Returns the active state of the crtc, and if the crtc is active,
	 * fills out the pipe-config with the hw state. */
	bool (*get_pipe_config)(struct intel_crtc *,
597
				struct intel_crtc_state *);
598 599
	void (*get_initial_plane_config)(struct intel_crtc *,
					 struct intel_initial_plane_config *);
600 601
	int (*crtc_compute_clock)(struct intel_crtc *crtc,
				  struct intel_crtc_state *crtc_state);
602 603
	void (*crtc_enable)(struct drm_crtc *crtc);
	void (*crtc_disable)(struct drm_crtc *crtc);
604 605
	void (*audio_codec_enable)(struct drm_connector *connector,
				   struct intel_encoder *encoder,
606
				   const struct drm_display_mode *adjusted_mode);
607
	void (*audio_codec_disable)(struct intel_encoder *encoder);
608
	void (*fdi_link_train)(struct drm_crtc *crtc);
609
	void (*init_clock_gating)(struct drm_device *dev);
610 611
	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
			  struct drm_framebuffer *fb,
612
			  struct drm_i915_gem_object *obj,
613
			  struct drm_i915_gem_request *req,
614
			  uint32_t flags);
615
	void (*hpd_irq_setup)(struct drm_device *dev);
616 617 618 619 620
	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
621

622 623
	void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
	void (*load_luts)(struct drm_crtc_state *crtc_state);
624 625
};

626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642
enum forcewake_domain_id {
	FW_DOMAIN_ID_RENDER = 0,
	FW_DOMAIN_ID_BLITTER,
	FW_DOMAIN_ID_MEDIA,

	FW_DOMAIN_ID_COUNT
};

enum forcewake_domains {
	FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
	FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
	FORCEWAKE_MEDIA	= (1 << FW_DOMAIN_ID_MEDIA),
	FORCEWAKE_ALL = (FORCEWAKE_RENDER |
			 FORCEWAKE_BLITTER |
			 FORCEWAKE_MEDIA)
};

643 644 645 646 647 648 649
#define FW_REG_READ  (1)
#define FW_REG_WRITE (2)

enum forcewake_domains
intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
			       i915_reg_t reg, unsigned int op);

650
struct intel_uncore_funcs {
651
	void (*force_wake_get)(struct drm_i915_private *dev_priv,
652
							enum forcewake_domains domains);
653
	void (*force_wake_put)(struct drm_i915_private *dev_priv,
654
							enum forcewake_domains domains);
655

656 657 658 659
	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
660

661
	void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
662
				uint8_t val, bool trace);
663
	void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
664
				uint16_t val, bool trace);
665
	void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
666
				uint32_t val, bool trace);
667
	void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
668
				uint64_t val, bool trace);
669 670
};

671 672 673 674 675 676
struct intel_uncore {
	spinlock_t lock; /** lock is also taken in irq contexts. */

	struct intel_uncore_funcs funcs;

	unsigned fifo_count;
677
	enum forcewake_domains fw_domains;
678 679 680

	struct intel_uncore_forcewake_domain {
		struct drm_i915_private *i915;
681
		enum forcewake_domain_id id;
682
		enum forcewake_domains mask;
683
		unsigned wake_count;
684
		struct hrtimer timer;
685
		i915_reg_t reg_set;
686 687
		u32 val_set;
		u32 val_clear;
688 689
		i915_reg_t reg_ack;
		i915_reg_t reg_post;
690
		u32 val_reset;
691
	} fw_domain[FW_DOMAIN_ID_COUNT];
692 693

	int unclaimed_mmio_check;
694 695 696
};

/* Iterate over initialised fw domains */
697 698 699 700 701 702 703 704
#define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
	for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
	     (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
	     (domain__)++) \
		for_each_if ((mask__) & (domain__)->mask)

#define for_each_fw_domain(domain__, dev_priv__) \
	for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
705

706 707 708 709
#define CSR_VERSION(major, minor)	((major) << 16 | (minor))
#define CSR_VERSION_MAJOR(version)	((version) >> 16)
#define CSR_VERSION_MINOR(version)	((version) & 0xffff)

710
struct intel_csr {
711
	struct work_struct work;
712
	const char *fw_path;
713
	uint32_t *dmc_payload;
714
	uint32_t dmc_fw_size;
715
	uint32_t version;
716
	uint32_t mmio_count;
717
	i915_reg_t mmioaddr[8];
718
	uint32_t mmiodata[8];
719
	uint32_t dc_state;
720
	uint32_t allowed_dc_mask;
721 722
};

723 724 725 726 727 728 729 730 731 732 733 734 735
#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
	func(is_mobile) sep \
	func(is_i85x) sep \
	func(is_i915g) sep \
	func(is_i945gm) sep \
	func(is_g33) sep \
	func(need_gfx_hws) sep \
	func(is_g4x) sep \
	func(is_pineview) sep \
	func(is_broadwater) sep \
	func(is_crestline) sep \
	func(is_ivybridge) sep \
	func(is_valleyview) sep \
736
	func(is_cherryview) sep \
737
	func(is_haswell) sep \
738
	func(is_skylake) sep \
739
	func(is_broxton) sep \
740
	func(is_kabylake) sep \
741
	func(is_preliminary) sep \
742 743 744 745 746 747 748
	func(has_fbc) sep \
	func(has_pipe_cxsr) sep \
	func(has_hotplug) sep \
	func(cursor_needs_physical) sep \
	func(has_overlay) sep \
	func(overlay_needs_physical) sep \
	func(supports_tv) sep \
749
	func(has_llc) sep \
750
	func(has_snoop) sep \
751 752
	func(has_ddi) sep \
	func(has_fpga_dbg)
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Daniel Vetter 已提交
753

754 755
#define DEFINE_FLAG(name) u8 name:1
#define SEP_SEMICOLON ;
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Daniel Vetter 已提交
756

757
struct intel_device_info {
758
	u32 display_mmio_offset;
759
	u16 device_id;
760
	u8 num_pipes:3;
761
	u8 num_sprites[I915_MAX_PIPES];
762
	u8 gen;
763
	u8 ring_mask; /* Rings supported by the HW */
764
	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
765 766 767 768
	/* Register offsets for the various display pipes and transcoders */
	int pipe_offsets[I915_MAX_TRANSCODERS];
	int trans_offsets[I915_MAX_TRANSCODERS];
	int palette_offsets[I915_MAX_PIPES];
769
	int cursor_offsets[I915_MAX_PIPES];
770 771 772 773 774 775 776

	/* Slice/subslice/EU info */
	u8 slice_total;
	u8 subslice_total;
	u8 subslice_per_slice;
	u8 eu_total;
	u8 eu_per_subslice;
777 778
	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
	u8 subslice_7eu[3];
779 780 781
	u8 has_slice_pg:1;
	u8 has_subslice_pg:1;
	u8 has_eu_pg:1;
782 783 784 785 786

	struct color_luts {
		u16 degamma_lut_size;
		u16 gamma_lut_size;
	} color;
787 788
};

789 790 791
#undef DEFINE_FLAG
#undef SEP_SEMICOLON

792 793
enum i915_cache_level {
	I915_CACHE_NONE = 0,
794 795 796 797 798
	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
			      caches, eg sampler/render caches, and the
			      large Last-Level-Cache. LLC is coherent with
			      the CPU, but L3 is only visible to the GPU. */
799
	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
800 801
};

802 803 804 805 806 807
struct i915_ctx_hang_stats {
	/* This context had batch pending when hang was declared */
	unsigned batch_pending;

	/* This context had batch active when hang was declared */
	unsigned batch_active;
808 809 810 811

	/* Time when this context was last blamed for a GPU reset */
	unsigned long guilty_ts;

812 813 814 815 816
	/* If the contexts causes a second GPU hang within this time,
	 * it is permanently banned from submitting any more work.
	 */
	unsigned long ban_period_seconds;

817 818
	/* This context is banned to submit more work */
	bool banned;
819
};
820 821

/* This must match up with the value previously used for execbuf2.rsvd1. */
822
#define DEFAULT_CONTEXT_HANDLE 0
823 824

#define CONTEXT_NO_ZEROMAP (1<<0)
825 826 827 828 829
/**
 * struct intel_context - as the name implies, represents a context.
 * @ref: reference count.
 * @user_handle: userspace tracking identity for this context.
 * @remap_slice: l3 row remapping information.
830 831
 * @flags: context specific flags:
 *         CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
832 833 834 835
 * @file_priv: filp associated with this context (NULL for global default
 *	       context).
 * @hang_stats: information about the role of this context in possible GPU
 *		hangs.
836
 * @ppgtt: virtual memory space used by this context.
837 838 839 840 841 842 843
 * @legacy_hw_ctx: render context backing object and whether it is correctly
 *                initialized (legacy ring submission mechanism only).
 * @link: link in the global list of contexts.
 *
 * Contexts are memory images used by the hardware to store copies of their
 * internal state.
 */
844
struct intel_context {
845
	struct kref ref;
846
	int user_handle;
847
	uint8_t remap_slice;
848
	struct drm_i915_private *i915;
849
	int flags;
850
	struct drm_i915_file_private *file_priv;
851
	struct i915_ctx_hang_stats hang_stats;
852
	struct i915_hw_ppgtt *ppgtt;
853

854
	/* Legacy ring buffer submission */
855 856 857 858 859
	struct {
		struct drm_i915_gem_object *rcs_state;
		bool initialized;
	} legacy_hw_ctx;

860 861 862
	/* Execlists */
	struct {
		struct drm_i915_gem_object *state;
863
		struct intel_ringbuffer *ringbuf;
864
		int pin_count;
865 866
		struct i915_vma *lrc_vma;
		u64 lrc_desc;
867
		uint32_t *lrc_reg_state;
868
	} engine[I915_NUM_ENGINES];
869

870
	struct list_head link;
871 872
};

873 874 875 876 877
enum fb_op_origin {
	ORIGIN_GTT,
	ORIGIN_CPU,
	ORIGIN_CS,
	ORIGIN_FLIP,
878
	ORIGIN_DIRTYFB,
879 880
};

881
struct intel_fbc {
P
Paulo Zanoni 已提交
882 883 884
	/* This is always the inner lock when overlapping with struct_mutex and
	 * it's the outer lock when overlapping with stolen_lock. */
	struct mutex lock;
B
Ben Widawsky 已提交
885
	unsigned threshold;
886 887
	unsigned int possible_framebuffer_bits;
	unsigned int busy_bits;
888
	unsigned int visible_pipes_mask;
889
	struct intel_crtc *crtc;
890

891
	struct drm_mm_node compressed_fb;
892 893
	struct drm_mm_node *compressed_llb;

894 895
	bool false_color;

896
	bool enabled;
897
	bool active;
898

899 900 901 902 903 904 905 906 907 908 909 910 911 912 913 914 915 916 917 918 919 920
	struct intel_fbc_state_cache {
		struct {
			unsigned int mode_flags;
			uint32_t hsw_bdw_pixel_rate;
		} crtc;

		struct {
			unsigned int rotation;
			int src_w;
			int src_h;
			bool visible;
		} plane;

		struct {
			u64 ilk_ggtt_offset;
			uint32_t pixel_format;
			unsigned int stride;
			int fence_reg;
			unsigned int tiling_mode;
		} fb;
	} state_cache;

921 922 923 924 925 926 927 928 929 930 931 932 933 934 935 936 937
	struct intel_fbc_reg_params {
		struct {
			enum pipe pipe;
			enum plane plane;
			unsigned int fence_y_offset;
		} crtc;

		struct {
			u64 ggtt_offset;
			uint32_t pixel_format;
			unsigned int stride;
			int fence_reg;
		} fb;

		int cfb_size;
	} params;

938
	struct intel_fbc_work {
939
		bool scheduled;
940
		u32 scheduled_vblank;
941 942
		struct work_struct work;
	} work;
943

944
	const char *no_fbc_reason;
945 946
};

947 948 949 950 951 952 953 954 955 956 957 958 959 960 961
/**
 * HIGH_RR is the highest eDP panel refresh rate read from EDID
 * LOW_RR is the lowest eDP panel refresh rate found from EDID
 * parsing for same resolution.
 */
enum drrs_refresh_rate_type {
	DRRS_HIGH_RR,
	DRRS_LOW_RR,
	DRRS_MAX_RR, /* RR count */
};

enum drrs_support_type {
	DRRS_NOT_SUPPORTED = 0,
	STATIC_DRRS_SUPPORT = 1,
	SEAMLESS_DRRS_SUPPORT = 2
962 963
};

964
struct intel_dp;
965 966 967 968 969 970 971 972 973
struct i915_drrs {
	struct mutex mutex;
	struct delayed_work work;
	struct intel_dp *dp;
	unsigned busy_frontbuffer_bits;
	enum drrs_refresh_rate_type refresh_rate_type;
	enum drrs_support_type type;
};

R
Rodrigo Vivi 已提交
974
struct i915_psr {
975
	struct mutex lock;
R
Rodrigo Vivi 已提交
976 977
	bool sink_support;
	bool source_ok;
978
	struct intel_dp *enabled;
979 980
	bool active;
	struct delayed_work work;
981
	unsigned busy_frontbuffer_bits;
982 983
	bool psr2_support;
	bool aux_frame_sync;
984
	bool link_standby;
985
};
986

987
enum intel_pch {
988
	PCH_NONE = 0,	/* No PCH present */
989 990
	PCH_IBX,	/* Ibexpeak PCH */
	PCH_CPT,	/* Cougarpoint PCH */
991
	PCH_LPT,	/* Lynxpoint PCH */
992
	PCH_SPT,        /* Sunrisepoint PCH */
B
Ben Widawsky 已提交
993
	PCH_NOP,
994 995
};

996 997 998 999 1000
enum intel_sbi_destination {
	SBI_ICLK,
	SBI_MPHY,
};

1001
#define QUIRK_PIPEA_FORCE (1<<0)
1002
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
1003
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
1004
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
1005
#define QUIRK_PIPEB_FORCE (1<<4)
1006
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1007

1008
struct intel_fbdev;
1009
struct intel_fbc_work;
1010

1011 1012
struct intel_gmbus {
	struct i2c_adapter adapter;
1013
#define GMBUS_FORCE_BIT_RETRY (1U << 31)
1014
	u32 force_bit;
1015
	u32 reg0;
1016
	i915_reg_t gpio_reg;
1017
	struct i2c_algo_bit_data bit_algo;
1018 1019 1020
	struct drm_i915_private *dev_priv;
};

1021
struct i915_suspend_saved_registers {
1022
	u32 saveDSPARB;
J
Jesse Barnes 已提交
1023
	u32 saveLVDS;
1024 1025
	u32 savePP_ON_DELAYS;
	u32 savePP_OFF_DELAYS;
J
Jesse Barnes 已提交
1026 1027 1028
	u32 savePP_ON;
	u32 savePP_OFF;
	u32 savePP_CONTROL;
1029
	u32 savePP_DIVISOR;
J
Jesse Barnes 已提交
1030
	u32 saveFBC_CONTROL;
1031 1032
	u32 saveCACHE_MODE_0;
	u32 saveMI_ARB_STATE;
J
Jesse Barnes 已提交
1033 1034
	u32 saveSWF0[16];
	u32 saveSWF1[16];
1035
	u32 saveSWF3[3];
1036
	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1037
	u32 savePCH_PORT_HOTPLUG;
1038
	u16 saveGCDGMBUS;
1039
};
1040

1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 1051 1052 1053 1054 1055 1056 1057 1058 1059 1060 1061 1062 1063 1064 1065 1066 1067 1068 1069 1070 1071 1072 1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098
struct vlv_s0ix_state {
	/* GAM */
	u32 wr_watermark;
	u32 gfx_prio_ctrl;
	u32 arb_mode;
	u32 gfx_pend_tlb0;
	u32 gfx_pend_tlb1;
	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
	u32 media_max_req_count;
	u32 gfx_max_req_count;
	u32 render_hwsp;
	u32 ecochk;
	u32 bsd_hwsp;
	u32 blt_hwsp;
	u32 tlb_rd_addr;

	/* MBC */
	u32 g3dctl;
	u32 gsckgctl;
	u32 mbctl;

	/* GCP */
	u32 ucgctl1;
	u32 ucgctl3;
	u32 rcgctl1;
	u32 rcgctl2;
	u32 rstctl;
	u32 misccpctl;

	/* GPM */
	u32 gfxpause;
	u32 rpdeuhwtc;
	u32 rpdeuc;
	u32 ecobus;
	u32 pwrdwnupctl;
	u32 rp_down_timeout;
	u32 rp_deucsw;
	u32 rcubmabdtmr;
	u32 rcedata;
	u32 spare2gh;

	/* Display 1 CZ domain */
	u32 gt_imr;
	u32 gt_ier;
	u32 pm_imr;
	u32 pm_ier;
	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

	/* GT SA CZ domain */
	u32 tilectl;
	u32 gt_fifoctl;
	u32 gtlc_wake_ctrl;
	u32 gtlc_survive;
	u32 pmwgicz;

	/* Display 2 CZ domain */
	u32 gu_ctl0;
	u32 gu_ctl1;
1099
	u32 pcbr;
1100 1101 1102
	u32 clock_gate_dis2;
};

1103 1104 1105 1106
struct intel_rps_ei {
	u32 cz_clock;
	u32 render_c0;
	u32 media_c0;
1107 1108
};

1109
struct intel_gen6_power_mgmt {
I
Imre Deak 已提交
1110 1111 1112 1113
	/*
	 * work, interrupts_enabled and pm_iir are protected by
	 * dev_priv->irq_lock
	 */
1114
	struct work_struct work;
I
Imre Deak 已提交
1115
	bool interrupts_enabled;
1116
	u32 pm_iir;
1117

1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132
	/* Frequencies are stored in potentially platform dependent multiples.
	 * In other words, *_freq needs to be multiplied by X to be interesting.
	 * Soft limits are those which are used for the dynamic reclocking done
	 * by the driver (raise frequencies under heavy loads, and lower for
	 * lighter loads). Hard limits are those imposed by the hardware.
	 *
	 * A distinction is made for overclocking, which is never enabled by
	 * default, and is considered to be above the hard limit if it's
	 * possible at all.
	 */
	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
	u8 min_freq;		/* AKA RPn. Minimum frequency */
1133
	u8 idle_freq;		/* Frequency to request when we are idle */
1134 1135 1136
	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
	u8 rp1_freq;		/* "less than" RP0 power/freqency */
	u8 rp0_freq;		/* Non-overclocked max frequency. */
1137
	u16 gpll_ref_freq;	/* vlv/chv GPLL reference frequency */
1138

1139 1140 1141
	u8 up_threshold; /* Current %busy required to uplock */
	u8 down_threshold; /* Current %busy required to downclock */

1142 1143 1144
	int last_adj;
	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;

1145 1146 1147 1148
	spinlock_t client_lock;
	struct list_head clients;
	bool client_boost;

1149
	bool enabled;
1150
	struct delayed_work delayed_resume_work;
1151
	unsigned boosts;
1152

1153
	struct intel_rps_client semaphores, mmioflips;
1154

1155 1156 1157
	/* manual wa residency calculations */
	struct intel_rps_ei up_ei, down_ei;

1158 1159
	/*
	 * Protects RPS/RC6 register access and PCU communication.
1160 1161 1162
	 * Must be taken after struct_mutex if nested. Note that
	 * this lock may be held for long periods of time when
	 * talking to hw - so only take it when talking to hw!
1163 1164
	 */
	struct mutex hw_lock;
1165 1166
};

D
Daniel Vetter 已提交
1167 1168 1169
/* defined intel_pm.c */
extern spinlock_t mchdev_lock;

1170 1171 1172 1173 1174 1175 1176 1177 1178 1179 1180
struct intel_ilk_power_mgmt {
	u8 cur_delay;
	u8 min_delay;
	u8 max_delay;
	u8 fmax;
	u8 fstart;

	u64 last_count1;
	unsigned long last_time1;
	unsigned long chipset_power;
	u64 last_count2;
1181
	u64 last_time2;
1182 1183 1184 1185 1186 1187 1188
	unsigned long gfx_power;
	u8 corr;

	int c_m;
	int r_t;
};

1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211 1212 1213 1214 1215 1216 1217 1218
struct drm_i915_private;
struct i915_power_well;

struct i915_power_well_ops {
	/*
	 * Synchronize the well's hw state to match the current sw state, for
	 * example enable/disable it based on the current refcount. Called
	 * during driver init and resume time, possibly after first calling
	 * the enable/disable handlers.
	 */
	void (*sync_hw)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/*
	 * Enable the well and resources that depend on it (for example
	 * interrupts located on the well). Called after the 0->1 refcount
	 * transition.
	 */
	void (*enable)(struct drm_i915_private *dev_priv,
		       struct i915_power_well *power_well);
	/*
	 * Disable the well and resources that depend on it. Called after
	 * the 1->0 refcount transition.
	 */
	void (*disable)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/* Returns the hw enabled state. */
	bool (*is_enabled)(struct drm_i915_private *dev_priv,
			   struct i915_power_well *power_well);
};

1219 1220
/* Power well structure for haswell */
struct i915_power_well {
1221
	const char *name;
1222
	bool always_on;
1223 1224
	/* power well enable/disable usage count */
	int count;
1225 1226
	/* cached hw enabled state */
	bool hw_enabled;
1227
	unsigned long domains;
1228
	unsigned long data;
1229
	const struct i915_power_well_ops *ops;
1230 1231
};

1232
struct i915_power_domains {
1233 1234 1235 1236 1237
	/*
	 * Power wells needed for initialization at driver init and suspend
	 * time are on. They are kept on until after the first modeset.
	 */
	bool init_power_on;
1238
	bool initializing;
1239
	int power_well_count;
1240

1241
	struct mutex lock;
1242
	int domain_use_count[POWER_DOMAIN_NUM];
1243
	struct i915_power_well *power_wells;
1244 1245
};

1246
#define MAX_L3_SLICES 2
1247
struct intel_l3_parity {
1248
	u32 *remap_info[MAX_L3_SLICES];
1249
	struct work_struct error_work;
1250
	int which_slice;
1251 1252
};

1253 1254 1255
struct i915_gem_mm {
	/** Memory allocator for GTT stolen memory */
	struct drm_mm stolen;
1256 1257 1258 1259
	/** Protects the usage of the GTT stolen memory allocator. This is
	 * always the inner lock when overlapping with struct_mutex. */
	struct mutex stolen_lock;

1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275
	/** List of all objects in gtt_space. Used to restore gtt
	 * mappings on resume */
	struct list_head bound_list;
	/**
	 * List of objects which are not bound to the GTT (thus
	 * are idle and not used by the GPU) but still have
	 * (presumably uncached) pages still attached.
	 */
	struct list_head unbound_list;

	/** Usable portion of the GTT for GEM */
	unsigned long stolen_base; /* limited to low memory (32-bit) */

	/** PPGTT used for aliasing the PPGTT with the GTT */
	struct i915_hw_ppgtt *aliasing_ppgtt;

1276
	struct notifier_block oom_notifier;
1277
	struct notifier_block vmap_notifier;
1278
	struct shrinker shrinker;
1279 1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 1292
	bool shrinker_no_lock_stealing;

	/** LRU list of objects with fence regs on them. */
	struct list_head fence_list;

	/**
	 * We leave the user IRQ off as much as possible,
	 * but this means that requests will finish and never
	 * be retired once the system goes idle. Set a timer to
	 * fire periodically while the ring is running. When it
	 * fires, go retire requests.
	 */
	struct delayed_work retire_work;

1293 1294 1295 1296 1297 1298 1299 1300 1301
	/**
	 * When we detect an idle GPU, we want to turn on
	 * powersaving features. So once we see that there
	 * are no more requests outstanding and no more
	 * arrive within a small period of time, we fire
	 * off the idle_work.
	 */
	struct delayed_work idle_work;

1302 1303 1304 1305 1306 1307
	/**
	 * Are we in a non-interruptible section of code like
	 * modesetting?
	 */
	bool interruptible;

1308 1309 1310 1311 1312 1313 1314 1315
	/**
	 * Is the GPU currently considered idle, or busy executing userspace
	 * requests?  Whilst idle, we attempt to power down the hardware and
	 * display clocks. In order to reduce the effect on performance, there
	 * is a slight delay before we do so.
	 */
	bool busy;

1316
	/* the indicator for dispatch video commands on two BSD rings */
1317
	unsigned int bsd_ring_dispatch_index;
1318

1319 1320 1321 1322 1323 1324
	/** Bit 6 swizzling required for X tiling */
	uint32_t bit_6_swizzle_x;
	/** Bit 6 swizzling required for Y tiling */
	uint32_t bit_6_swizzle_y;

	/* accounting, useful for userland debugging */
1325
	spinlock_t object_stat_lock;
1326 1327 1328 1329
	size_t object_memory;
	u32 object_count;
};

1330
struct drm_i915_error_state_buf {
1331
	struct drm_i915_private *i915;
1332 1333 1334 1335 1336 1337 1338 1339
	unsigned bytes;
	unsigned size;
	int err;
	u8 *buf;
	loff_t start;
	loff_t pos;
};

1340 1341 1342 1343 1344
struct i915_error_state_file_priv {
	struct drm_device *dev;
	struct drm_i915_error_state *error;
};

1345 1346 1347 1348
struct i915_gpu_error {
	/* For hangcheck timer */
#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1349 1350 1351
	/* Hang gpu twice in this window and your context gets banned */
#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)

1352 1353
	struct workqueue_struct *hangcheck_wq;
	struct delayed_work hangcheck_work;
1354 1355 1356 1357 1358

	/* For reset and error_state handling. */
	spinlock_t lock;
	/* Protected by the above dev->gpu_error.lock. */
	struct drm_i915_error_state *first_error;
1359 1360 1361

	unsigned long missed_irq_rings;

1362
	/**
M
Mika Kuoppala 已提交
1363
	 * State variable controlling the reset flow and count
1364
	 *
M
Mika Kuoppala 已提交
1365 1366 1367 1368 1369 1370 1371 1372 1373 1374 1375 1376 1377
	 * This is a counter which gets incremented when reset is triggered,
	 * and again when reset has been handled. So odd values (lowest bit set)
	 * means that reset is in progress and even values that
	 * (reset_counter >> 1):th reset was successfully completed.
	 *
	 * If reset is not completed succesfully, the I915_WEDGE bit is
	 * set meaning that hardware is terminally sour and there is no
	 * recovery. All waiters on the reset_queue will be woken when
	 * that happens.
	 *
	 * This counter is used by the wait_seqno code to notice that reset
	 * event happened and it needs to restart the entire ioctl (since most
	 * likely the seqno it waited for won't ever signal anytime soon).
1378 1379 1380 1381
	 *
	 * This is important for lock-free wait paths, where no contended lock
	 * naturally enforces the correct ordering between the bail-out of the
	 * waiter and the gpu reset work code.
1382 1383 1384 1385
	 */
	atomic_t reset_counter;

#define I915_RESET_IN_PROGRESS_FLAG	1
M
Mika Kuoppala 已提交
1386
#define I915_WEDGED			(1 << 31)
1387 1388 1389 1390 1391 1392

	/**
	 * Waitqueue to signal when the reset has completed. Used by clients
	 * that wait for dev_priv->mm.wedged to settle.
	 */
	wait_queue_head_t reset_queue;
1393

1394 1395 1396 1397 1398 1399
	/* Userspace knobs for gpu hang simulation;
	 * combines both a ring mask, and extra flags
	 */
	u32 stop_rings;
#define I915_STOP_RING_ALLOW_BAN       (1 << 31)
#define I915_STOP_RING_ALLOW_WARN      (1 << 30)
1400 1401 1402

	/* For missed irq/seqno simulation. */
	unsigned int test_irq_rings;
1403 1404
};

1405 1406 1407 1408 1409 1410
enum modeset_restore {
	MODESET_ON_LID_OPEN,
	MODESET_DONE,
	MODESET_SUSPENDED,
};

1411 1412 1413 1414 1415
#define DP_AUX_A 0x40
#define DP_AUX_B 0x10
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30

X
Xiong Zhang 已提交
1416 1417 1418 1419
#define DDC_PIN_B  0x05
#define DDC_PIN_C  0x04
#define DDC_PIN_D  0x06

1420
struct ddi_vbt_port_info {
1421 1422 1423 1424 1425 1426
	/*
	 * This is an index in the HDMI/DVI DDI buffer translation table.
	 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
	 * populate this field.
	 */
#define HDMI_LEVEL_SHIFT_UNKNOWN	0xff
1427
	uint8_t hdmi_level_shift;
1428 1429 1430 1431

	uint8_t supports_dvi:1;
	uint8_t supports_hdmi:1;
	uint8_t supports_dp:1;
1432 1433

	uint8_t alternate_aux_channel;
X
Xiong Zhang 已提交
1434
	uint8_t alternate_ddc_pin;
1435 1436 1437

	uint8_t dp_boost_level;
	uint8_t hdmi_boost_level;
1438 1439
};

R
Rodrigo Vivi 已提交
1440 1441 1442 1443 1444
enum psr_lines_to_wait {
	PSR_0_LINES_TO_WAIT = 0,
	PSR_1_LINE_TO_WAIT,
	PSR_4_LINES_TO_WAIT,
	PSR_8_LINES_TO_WAIT
1445 1446
};

1447 1448 1449 1450 1451 1452 1453 1454 1455 1456 1457 1458
struct intel_vbt_data {
	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits */
	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int lvds_vbt:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
	unsigned int display_clock_mode:1;
	unsigned int fdi_rx_polarity_inverted:1;
1459
	unsigned int panel_type:4;
1460 1461 1462
	int lvds_ssc_freq;
	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

1463 1464
	enum drrs_support_type drrs_type;

1465 1466 1467 1468 1469
	struct {
		int rate;
		int lanes;
		int preemphasis;
		int vswing;
1470
		bool low_vswing;
1471 1472 1473 1474 1475
		bool initialized;
		bool support;
		int bpp;
		struct edp_power_seq pps;
	} edp;
1476

R
Rodrigo Vivi 已提交
1477 1478 1479 1480 1481 1482 1483 1484 1485
	struct {
		bool full_link;
		bool require_aux_wakeup;
		int idle_frames;
		enum psr_lines_to_wait lines_to_wait;
		int tp1_wakeup_time;
		int tp2_tp3_wakeup_time;
	} psr;

1486 1487
	struct {
		u16 pwm_freq_hz;
1488
		bool present;
1489
		bool active_low_pwm;
1490
		u8 min_brightness;	/* min_brightness/255 of max */
1491 1492
	} backlight;

1493 1494 1495
	/* MIPI DSI */
	struct {
		u16 panel_id;
1496 1497 1498 1499 1500
		struct mipi_config *config;
		struct mipi_pps_data *pps;
		u8 seq_version;
		u32 size;
		u8 *data;
1501
		const u8 *sequence[MIPI_SEQ_MAX];
1502 1503
	} dsi;

1504 1505 1506
	int crt_ddc_pin;

	int child_dev_num;
1507
	union child_device_config *child_dev;
1508 1509

	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1510
	struct sdvo_device_mapping sdvo_mappings[2];
1511 1512
};

1513 1514 1515 1516 1517
enum intel_ddb_partitioning {
	INTEL_DDB_PART_1_2,
	INTEL_DDB_PART_5_6, /* IVB+ */
};

1518 1519 1520 1521 1522 1523 1524 1525
struct intel_wm_level {
	bool enable;
	uint32_t pri_val;
	uint32_t spr_val;
	uint32_t cur_val;
	uint32_t fbc_val;
};

1526
struct ilk_wm_values {
1527 1528 1529 1530 1531 1532 1533 1534
	uint32_t wm_pipe[3];
	uint32_t wm_lp[3];
	uint32_t wm_lp_spr[3];
	uint32_t wm_linetime[3];
	bool enable_fbc_wm;
	enum intel_ddb_partitioning partitioning;
};

1535 1536 1537 1538 1539
struct vlv_pipe_wm {
	uint16_t primary;
	uint16_t sprite[2];
	uint8_t cursor;
};
1540

1541 1542 1543 1544
struct vlv_sr_wm {
	uint16_t plane;
	uint8_t cursor;
};
1545

1546 1547 1548
struct vlv_wm_values {
	struct vlv_pipe_wm pipe[3];
	struct vlv_sr_wm sr;
1549 1550 1551 1552 1553
	struct {
		uint8_t cursor;
		uint8_t sprite[2];
		uint8_t primary;
	} ddl[3];
1554 1555
	uint8_t level;
	bool cxsr;
1556 1557
};

1558
struct skl_ddb_entry {
1559
	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
1560 1561 1562 1563
};

static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
{
1564
	return entry->end - entry->start;
1565 1566
}

1567 1568 1569 1570 1571 1572 1573 1574 1575
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
				       const struct skl_ddb_entry *e2)
{
	if (e1->start == e2->start && e1->end == e2->end)
		return true;

	return false;
}

1576
struct skl_ddb_allocation {
1577
	struct skl_ddb_entry pipe[I915_MAX_PIPES];
1578
	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1579
	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1580 1581
};

1582 1583
struct skl_wm_values {
	bool dirty[I915_MAX_PIPES];
1584
	struct skl_ddb_allocation ddb;
1585 1586 1587 1588 1589 1590 1591 1592 1593 1594 1595
	uint32_t wm_linetime[I915_MAX_PIPES];
	uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
	uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
};

struct skl_wm_level {
	bool plane_en[I915_MAX_PLANES];
	uint16_t plane_res_b[I915_MAX_PLANES];
	uint8_t plane_res_l[I915_MAX_PLANES];
};

1596
/*
1597 1598 1599 1600
 * This struct helps tracking the state needed for runtime PM, which puts the
 * device in PCI D3 state. Notice that when this happens, nothing on the
 * graphics device works, even register access, so we don't get interrupts nor
 * anything else.
1601
 *
1602 1603 1604
 * Every piece of our code that needs to actually touch the hardware needs to
 * either call intel_runtime_pm_get or call intel_display_power_get with the
 * appropriate power domain.
1605
 *
1606 1607
 * Our driver uses the autosuspend delay feature, which means we'll only really
 * suspend if we stay with zero refcount for a certain amount of time. The
1608
 * default value is currently very conservative (see intel_runtime_pm_enable), but
1609
 * it can be changed with the standard runtime PM files from sysfs.
1610 1611 1612 1613 1614
 *
 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
 * goes back to false exactly before we reenable the IRQs. We use this variable
 * to check if someone is trying to enable/disable IRQs while they're supposed
 * to be disabled. This shouldn't happen and we'll print some error messages in
1615
 * case it happens.
1616
 *
1617
 * For more, read the Documentation/power/runtime_pm.txt.
1618
 */
1619
struct i915_runtime_pm {
1620
	atomic_t wakeref_count;
1621
	atomic_t atomic_seq;
1622
	bool suspended;
1623
	bool irqs_enabled;
1624 1625
};

1626 1627 1628 1629 1630
enum intel_pipe_crc_source {
	INTEL_PIPE_CRC_SOURCE_NONE,
	INTEL_PIPE_CRC_SOURCE_PLANE1,
	INTEL_PIPE_CRC_SOURCE_PLANE2,
	INTEL_PIPE_CRC_SOURCE_PF,
1631
	INTEL_PIPE_CRC_SOURCE_PIPE,
D
Daniel Vetter 已提交
1632 1633 1634 1635 1636
	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
	INTEL_PIPE_CRC_SOURCE_TV,
	INTEL_PIPE_CRC_SOURCE_DP_B,
	INTEL_PIPE_CRC_SOURCE_DP_C,
	INTEL_PIPE_CRC_SOURCE_DP_D,
1637
	INTEL_PIPE_CRC_SOURCE_AUTO,
1638 1639 1640
	INTEL_PIPE_CRC_SOURCE_MAX,
};

1641
struct intel_pipe_crc_entry {
1642
	uint32_t frame;
1643 1644 1645
	uint32_t crc[5];
};

1646
#define INTEL_PIPE_CRC_ENTRIES_NR	128
1647
struct intel_pipe_crc {
1648 1649
	spinlock_t lock;
	bool opened;		/* exclusive access to the result file */
1650
	struct intel_pipe_crc_entry *entries;
1651
	enum intel_pipe_crc_source source;
1652
	int head, tail;
1653
	wait_queue_head_t wq;
1654 1655
};

1656 1657 1658 1659 1660 1661 1662 1663 1664 1665 1666
struct i915_frontbuffer_tracking {
	struct mutex lock;

	/*
	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
	 * scheduled flips.
	 */
	unsigned busy_bits;
	unsigned flip_bits;
};

1667
struct i915_wa_reg {
1668
	i915_reg_t addr;
1669 1670 1671 1672 1673
	u32 value;
	/* bitmask representing WA bits */
	u32 mask;
};

1674 1675 1676 1677 1678 1679 1680
/*
 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
 * allowing it for RCS as we don't foresee any requirement of having
 * a whitelist for other engines. When it is really required for
 * other engines then the limit need to be increased.
 */
#define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1681 1682 1683 1684

struct i915_workarounds {
	struct i915_wa_reg reg[I915_MAX_WA_REGS];
	u32 count;
1685
	u32 hw_whitelist_count[I915_NUM_ENGINES];
1686 1687
};

1688 1689 1690 1691
struct i915_virtual_gpu {
	bool active;
};

1692 1693 1694 1695 1696
struct i915_execbuffer_params {
	struct drm_device               *dev;
	struct drm_file                 *file;
	uint32_t                        dispatch_flags;
	uint32_t                        args_batch_start_offset;
1697
	uint64_t                        batch_obj_vm_offset;
1698
	struct intel_engine_cs *engine;
1699 1700
	struct drm_i915_gem_object      *batch_obj;
	struct intel_context            *ctx;
1701
	struct drm_i915_gem_request     *request;
1702 1703
};

1704 1705 1706 1707 1708 1709 1710
/* used in computing the new watermarks state */
struct intel_wm_config {
	unsigned int num_pipes_active;
	bool sprites_enabled;
	bool sprites_scaled;
};

1711
struct drm_i915_private {
1712
	struct drm_device *dev;
1713
	struct kmem_cache *objects;
1714
	struct kmem_cache *vmas;
1715
	struct kmem_cache *requests;
1716

1717
	const struct intel_device_info info;
1718 1719 1720 1721 1722

	int relative_constants_mode;

	void __iomem *regs;

1723
	struct intel_uncore uncore;
1724

1725 1726
	struct i915_virtual_gpu vgpu;

1727 1728
	struct intel_guc guc;

1729 1730
	struct intel_csr csr;

1731
	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1732

1733 1734 1735 1736 1737 1738 1739 1740 1741
	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
	 * controller on different i2c buses. */
	struct mutex gmbus_mutex;

	/**
	 * Base address of the gmbus and gpio block.
	 */
	uint32_t gpio_mmio_base;

1742 1743 1744
	/* MMIO base address for MIPI regs */
	uint32_t mipi_mmio_base;

1745 1746
	uint32_t psr_mmio_base;

1747 1748
	wait_queue_head_t gmbus_wait_queue;

1749
	struct pci_dev *bridge_dev;
1750
	struct intel_engine_cs engine[I915_NUM_ENGINES];
1751
	struct drm_i915_gem_object *semaphore_obj;
1752
	uint32_t last_seqno, next_seqno;
1753

1754
	struct drm_dma_handle *status_page_dmah;
1755 1756 1757 1758 1759
	struct resource mch_res;

	/* protects the irq masks */
	spinlock_t irq_lock;

1760 1761 1762
	/* protects the mmio flip data */
	spinlock_t mmio_flip_lock;

1763 1764
	bool display_irqs_enabled;

1765 1766 1767
	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
	struct pm_qos_request pm_qos;

V
Ville Syrjälä 已提交
1768 1769
	/* Sideband mailbox protection */
	struct mutex sb_lock;
1770 1771

	/** Cached value of IMR to avoid reads in updating the bitfield */
1772 1773 1774 1775
	union {
		u32 irq_mask;
		u32 de_irq_mask[I915_MAX_PIPES];
	};
1776
	u32 gt_irq_mask;
1777
	u32 pm_irq_mask;
1778
	u32 pm_rps_events;
1779
	u32 pipestat_irq_mask[I915_MAX_PIPES];
1780

1781
	struct i915_hotplug hotplug;
1782
	struct intel_fbc fbc;
1783
	struct i915_drrs drrs;
1784
	struct intel_opregion opregion;
1785
	struct intel_vbt_data vbt;
1786

1787 1788
	bool preserve_bios_swizzle;

1789 1790 1791
	/* overlay */
	struct intel_overlay *overlay;

1792
	/* backlight registers and fields in struct intel_panel */
1793
	struct mutex backlight_lock;
1794

1795 1796 1797
	/* LVDS info */
	bool no_aux_handshake;

V
Ville Syrjälä 已提交
1798 1799 1800
	/* protects panel power sequencer state */
	struct mutex pps_mutex;

1801 1802 1803 1804
	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */

	unsigned int fsb_freq, mem_freq, is_ddr3;
1805
	unsigned int skl_boot_cdclk;
1806
	unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
M
Mika Kahola 已提交
1807
	unsigned int max_dotclk_freq;
1808
	unsigned int rawclk_freq;
1809
	unsigned int hpll_freq;
1810
	unsigned int czclk_freq;
1811

1812 1813 1814 1815 1816 1817 1818
	/**
	 * wq - Driver workqueue for GEM.
	 *
	 * NOTE: Work items scheduled here are not allowed to grab any modeset
	 * locks, for otherwise the flushing done in the pageflip code will
	 * result in deadlocks.
	 */
1819 1820 1821 1822 1823 1824 1825
	struct workqueue_struct *wq;

	/* Display functions */
	struct drm_i915_display_funcs display;

	/* PCH chipset type */
	enum intel_pch pch_type;
1826
	unsigned short pch_id;
1827 1828 1829

	unsigned long quirks;

1830 1831
	enum modeset_restore modeset_restore;
	struct mutex modeset_restore_lock;
1832
	struct drm_atomic_state *modeset_restore_state;
1833

1834
	struct list_head vm_list; /* Global list of all address spaces */
1835
	struct i915_ggtt ggtt; /* VM representing the global address space */
B
Ben Widawsky 已提交
1836

1837
	struct i915_gem_mm mm;
1838 1839
	DECLARE_HASHTABLE(mm_structs, 7);
	struct mutex mm_lock;
1840 1841 1842

	/* Kernel Modesetting */

1843 1844
	struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
	struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1845 1846
	wait_queue_head_t pending_flip_queue;

1847 1848 1849 1850
#ifdef CONFIG_DEBUG_FS
	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif

1851
	/* dpll and cdclk state is protected by connection_mutex */
D
Daniel Vetter 已提交
1852 1853
	int num_shared_dpll;
	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1854
	const struct intel_dpll_mgr *dpll_mgr;
1855

1856 1857 1858 1859 1860 1861 1862
	/*
	 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
	 * Must be global rather than per dpll, because on some platforms
	 * plls share registers.
	 */
	struct mutex dpll_lock;

1863 1864 1865
	unsigned int active_crtcs;
	unsigned int min_pixclk[I915_MAX_PIPES];

1866
	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1867

1868
	struct i915_workarounds workarounds;
1869

1870 1871
	struct i915_frontbuffer_tracking fb_tracking;

1872
	u16 orig_clock;
1873

1874
	bool mchbar_need_disable;
1875

1876 1877
	struct intel_l3_parity l3_parity;

B
Ben Widawsky 已提交
1878
	/* Cannot be determined by PCIID. You must always read a register. */
1879
	u32 edram_cap;
B
Ben Widawsky 已提交
1880

1881
	/* gen6+ rps state */
1882
	struct intel_gen6_power_mgmt rps;
1883

1884 1885
	/* ilk-only ips/rps state. Everything in here is protected by the global
	 * mchdev_lock in intel_pm.c */
1886
	struct intel_ilk_power_mgmt ips;
1887

1888
	struct i915_power_domains power_domains;
1889

R
Rodrigo Vivi 已提交
1890
	struct i915_psr psr;
1891

1892
	struct i915_gpu_error gpu_error;
1893

1894 1895
	struct drm_i915_gem_object *vlv_pctx;

1896
#ifdef CONFIG_DRM_FBDEV_EMULATION
1897 1898
	/* list of fbdev register on this device */
	struct intel_fbdev *fbdev;
1899
	struct work_struct fbdev_suspend_work;
1900
#endif
1901 1902

	struct drm_property *broadcast_rgb_property;
1903
	struct drm_property *force_audio_property;
1904

I
Imre Deak 已提交
1905
	/* hda/i915 audio component */
1906
	struct i915_audio_component *audio_component;
I
Imre Deak 已提交
1907
	bool audio_component_registered;
1908 1909 1910 1911 1912
	/**
	 * av_mutex - mutex for audio/video sync
	 *
	 */
	struct mutex av_mutex;
I
Imre Deak 已提交
1913

1914
	uint32_t hw_context_size;
1915
	struct list_head context_list;
1916

1917
	u32 fdi_rx_config;
1918

1919
	/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1920
	u32 chv_phy_control;
1921 1922 1923 1924 1925 1926
	/*
	 * Shadows for CHV DPLL_MD regs to keep the state
	 * checker somewhat working in the presence hardware
	 * crappiness (can't read out DPLL_MD for pipes B & C).
	 */
	u32 chv_dpll_md[I915_MAX_PIPES];
1927
	u32 bxt_phy_grc;
1928

1929
	u32 suspend_count;
1930
	bool suspended_to_idle;
1931
	struct i915_suspend_saved_registers regfile;
1932
	struct vlv_s0ix_state vlv_s0ix_state;
1933

1934 1935 1936 1937 1938 1939 1940 1941 1942 1943 1944 1945
	struct {
		/*
		 * Raw watermark latency values:
		 * in 0.1us units for WM0,
		 * in 0.5us units for WM1+.
		 */
		/* primary */
		uint16_t pri_latency[5];
		/* sprite */
		uint16_t spr_latency[5];
		/* cursor */
		uint16_t cur_latency[5];
1946 1947 1948 1949 1950 1951
		/*
		 * Raw watermark memory latency values
		 * for SKL for all 8 levels
		 * in 1us units.
		 */
		uint16_t skl_latency[8];
1952

1953 1954 1955
		/* Committed wm config */
		struct intel_wm_config config;

1956 1957 1958 1959 1960 1961 1962
		/*
		 * The skl_wm_values structure is a bit too big for stack
		 * allocation, so we keep the staging struct where we store
		 * intermediate results here instead.
		 */
		struct skl_wm_values skl_results;

1963
		/* current hardware state */
1964 1965 1966
		union {
			struct ilk_wm_values hw;
			struct skl_wm_values skl_hw;
1967
			struct vlv_wm_values vlv;
1968
		};
1969 1970

		uint8_t max_level;
1971 1972 1973 1974 1975 1976 1977

		/*
		 * Should be held around atomic WM register writing; also
		 * protects * intel_crtc->wm.active and
		 * cstate->wm.need_postvbl_update.
		 */
		struct mutex wm_mutex;
1978 1979
	} wm;

1980 1981
	struct i915_runtime_pm pm;

1982 1983
	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
	struct {
1984
		int (*execbuf_submit)(struct i915_execbuffer_params *params,
1985
				      struct drm_i915_gem_execbuffer2 *args,
1986
				      struct list_head *vmas);
1987 1988 1989
		int (*init_engines)(struct drm_device *dev);
		void (*cleanup_engine)(struct intel_engine_cs *engine);
		void (*stop_engine)(struct intel_engine_cs *engine);
1990 1991
	} gt;

1992 1993
	struct intel_context *kernel_context;

1994 1995 1996
	/* perform PHY state sanity checks? */
	bool chv_phy_assert[2];

1997 1998
	struct intel_encoder *dig_port_map[I915_MAX_PORTS];

1999 2000 2001 2002
	/*
	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
	 * will be rejected. Instead look for a better place.
	 */
2003
};
L
Linus Torvalds 已提交
2004

2005 2006 2007 2008 2009
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
	return dev->dev_private;
}

I
Imre Deak 已提交
2010 2011 2012 2013 2014
static inline struct drm_i915_private *dev_to_i915(struct device *dev)
{
	return to_i915(dev_get_drvdata(dev));
}

2015 2016 2017 2018 2019
static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
{
	return container_of(guc, struct drm_i915_private, guc);
}

2020 2021 2022 2023 2024 2025
/* Simple iterator over all initialised engines */
#define for_each_engine(engine__, dev_priv__) \
	for ((engine__) = &(dev_priv__)->engine[0]; \
	     (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
	     (engine__)++) \
		for_each_if (intel_engine_initialized(engine__))
2026

2027 2028 2029 2030 2031 2032 2033 2034 2035
/* Iterator with engine_id */
#define for_each_engine_id(engine__, dev_priv__, id__) \
	for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
	     (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
	     (engine__)++) \
		for_each_if (((id__) = (engine__)->id, \
			      intel_engine_initialized(engine__)))

/* Iterator over subset of engines selected by mask */
2036
#define for_each_engine_masked(engine__, dev_priv__, mask__) \
2037 2038 2039 2040 2041
	for ((engine__) = &(dev_priv__)->engine[0]; \
	     (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
	     (engine__)++) \
		for_each_if (((mask__) & intel_engine_flag(engine__)) && \
			     intel_engine_initialized(engine__))
2042

2043 2044 2045 2046 2047 2048 2049
enum hdmi_force_audio {
	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
	HDMI_AUDIO_AUTO,		/* trust EDID */
	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
};

2050
#define I915_GTT_OFFSET_NONE ((u32)-1)
2051

2052
struct drm_i915_gem_object_ops {
2053 2054 2055
	unsigned int flags;
#define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1

2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070
	/* Interface between the GEM object and its backing storage.
	 * get_pages() is called once prior to the use of the associated set
	 * of pages before to binding them into the GTT, and put_pages() is
	 * called after we no longer need them. As we expect there to be
	 * associated cost with migrating pages between the backing storage
	 * and making them available for the GPU (e.g. clflush), we may hold
	 * onto the pages after they are no longer referenced by the GPU
	 * in case they may be used again shortly (for example migrating the
	 * pages to a different memory domain within the GTT). put_pages()
	 * will therefore most likely be called when the object itself is
	 * being released or under memory pressure (where we attempt to
	 * reap pages for the shrinker).
	 */
	int (*get_pages)(struct drm_i915_gem_object *);
	void (*put_pages)(struct drm_i915_gem_object *);
2071

2072 2073
	int (*dmabuf_export)(struct drm_i915_gem_object *);
	void (*release)(struct drm_i915_gem_object *);
2074 2075
};

2076 2077
/*
 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2078
 * considered to be the frontbuffer for the given plane interface-wise. This
2079 2080 2081 2082 2083
 * doesn't mean that the hw necessarily already scans it out, but that any
 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
 *
 * We have one bit per pipe and per scanout plane type.
 */
2084 2085
#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2086 2087 2088 2089 2090
#define INTEL_FRONTBUFFER_BITS \
	(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
#define INTEL_FRONTBUFFER_CURSOR(pipe) \
2091 2092 2093
	(1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
	(1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2094
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2095
	(1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2096
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2097
	(0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2098

2099
struct drm_i915_gem_object {
2100
	struct drm_gem_object base;
2101

2102 2103
	const struct drm_i915_gem_object_ops *ops;

B
Ben Widawsky 已提交
2104 2105 2106
	/** List of VMAs backed by this object */
	struct list_head vma_list;

2107 2108
	/** Stolen memory for this object, instead of being backed by shmem. */
	struct drm_mm_node *stolen;
2109
	struct list_head global_list;
2110

2111
	struct list_head engine_list[I915_NUM_ENGINES];
2112 2113
	/** Used in execbuf to temporarily hold a ref */
	struct list_head obj_exec_link;
2114

2115
	struct list_head batch_pool_link;
2116

2117
	/**
2118 2119 2120
	 * This is set if the object is on the active lists (has pending
	 * rendering and so a non-zero seqno), and is not set if it i s on
	 * inactive (ready to be unbound) list.
2121
	 */
2122
	unsigned int active:I915_NUM_ENGINES;
2123 2124 2125 2126 2127

	/**
	 * This is set if the object has been written to since last bound
	 * to the GTT
	 */
2128
	unsigned int dirty:1;
2129 2130 2131 2132 2133 2134

	/**
	 * Fence register bits (if any) for this object.  Will be set
	 * as needed when mapped into the GTT.
	 * Protected by dev->struct_mutex.
	 */
2135
	signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2136 2137 2138 2139

	/**
	 * Advice: are the backing pages purgeable?
	 */
2140
	unsigned int madv:2;
2141 2142 2143 2144

	/**
	 * Current tiling mode for the object.
	 */
2145
	unsigned int tiling_mode:2;
2146 2147 2148 2149 2150 2151 2152 2153
	/**
	 * Whether the tiling parameters for the currently associated fence
	 * register have changed. Note that for the purposes of tracking
	 * tiling changes we also treat the unfenced register, the register
	 * slot that the object occupies whilst it executes a fenced
	 * command (such as BLT on gen2/3), as a "fence".
	 */
	unsigned int fence_dirty:1;
2154

2155 2156 2157 2158
	/**
	 * Is the object at the current location in the gtt mappable and
	 * fenceable? Used to avoid costly recalculations.
	 */
2159
	unsigned int map_and_fenceable:1;
2160

2161 2162 2163 2164 2165
	/**
	 * Whether the current gtt mapping needs to be mappable (and isn't just
	 * mappable by accident). Track pin and fault separate for a more
	 * accurate mappable working set.
	 */
2166
	unsigned int fault_mappable:1;
2167

2168 2169 2170 2171 2172
	/*
	 * Is the object to be mapped as read-only to the GPU
	 * Only honoured if hardware has relevant pte bit
	 */
	unsigned long gt_ro:1;
2173
	unsigned int cache_level:3;
2174
	unsigned int cache_dirty:1;
2175

2176 2177
	unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;

2178 2179
	unsigned int pin_display;

2180
	struct sg_table *pages;
2181
	int pages_pin_count;
2182 2183 2184 2185
	struct get_page {
		struct scatterlist *sg;
		int last;
	} get_page;
2186
	void *mapping;
2187

2188 2189 2190 2191 2192 2193 2194 2195 2196 2197
	/** Breadcrumb of last rendering to the buffer.
	 * There can only be one writer, but we allow for multiple readers.
	 * If there is a writer that necessarily implies that all other
	 * read requests are complete - but we may only be lazily clearing
	 * the read requests. A read request is naturally the most recent
	 * request on a ring, so we may have two different write and read
	 * requests on one ring where the write request is older than the
	 * read request. This allows for the CPU to read from an active
	 * buffer by only waiting for the write to complete.
	 * */
2198
	struct drm_i915_gem_request *last_read_req[I915_NUM_ENGINES];
2199
	struct drm_i915_gem_request *last_write_req;
2200
	/** Breadcrumb of last fenced GPU access to the buffer. */
2201
	struct drm_i915_gem_request *last_fenced_req;
2202

2203
	/** Current tiling stride for the object, if it's tiled. */
2204
	uint32_t stride;
2205

2206 2207 2208
	/** References from framebuffers, locks out tiling changes. */
	unsigned long framebuffer_references;

2209
	/** Record of address bit 17 of each page at last unbind. */
2210
	unsigned long *bit_17;
2211

2212
	union {
2213 2214 2215
		/** for phy allocated objects */
		struct drm_dma_handle *phys_handle;

2216 2217 2218 2219 2220 2221
		struct i915_gem_userptr {
			uintptr_t ptr;
			unsigned read_only :1;
			unsigned workers :4;
#define I915_GEM_USERPTR_MAX_WORKERS 15

2222 2223
			struct i915_mm_struct *mm;
			struct i915_mmu_object *mmu_object;
2224 2225 2226 2227
			struct work_struct *work;
		} userptr;
	};
};
2228
#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2229

2230 2231 2232 2233
void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits);

2234 2235 2236 2237 2238 2239
/**
 * Request queue structure.
 *
 * The request queue allows us to note sequence numbers that have been emitted
 * and may be associated with active buffers to be retired.
 *
2240 2241 2242 2243
 * By keeping this list, we can avoid having to do questionable sequence
 * number comparisons on buffer last_read|write_seqno. It also allows an
 * emission time to be associated with the request for tracking how far ahead
 * of the GPU the submission is.
2244 2245 2246
 *
 * The requests are reference counted, so upon creation they should have an
 * initial reference taken using kref_init
2247 2248
 */
struct drm_i915_gem_request {
2249 2250
	struct kref ref;

2251
	/** On Which ring this request was generated */
2252
	struct drm_i915_private *i915;
2253
	struct intel_engine_cs *engine;
2254
	unsigned reset_counter;
2255

2256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266
	 /** GEM sequence number associated with the previous request,
	  * when the HWS breadcrumb is equal to this the GPU is processing
	  * this request.
	  */
	u32 previous_seqno;

	 /** GEM sequence number associated with this request,
	  * when the HWS breadcrumb is equal or greater than this the GPU
	  * has finished processing this request.
	  */
	u32 seqno;
2267

2268 2269 2270
	/** Position in the ringbuffer of the start of the request */
	u32 head;

2271 2272 2273 2274 2275 2276 2277 2278
	/**
	 * Position in the ringbuffer of the start of the postfix.
	 * This is required to calculate the maximum available ringbuffer
	 * space without overwriting the postfix.
	 */
	 u32 postfix;

	/** Position in the ringbuffer of the end of the whole request */
2279 2280
	u32 tail;

2281
	/**
D
Dave Airlie 已提交
2282
	 * Context and ring buffer related to this request
2283 2284 2285 2286 2287 2288 2289 2290
	 * Contexts are refcounted, so when this request is associated with a
	 * context, we must increment the context's refcount, to guarantee that
	 * it persists while any request is linked to it. Requests themselves
	 * are also refcounted, so the request will only be freed when the last
	 * reference to it is dismissed, and the code in
	 * i915_gem_request_free() will then decrement the refcount on the
	 * context.
	 */
2291
	struct intel_context *ctx;
2292
	struct intel_ringbuffer *ringbuf;
2293

2294 2295
	/** Batch buffer related to this request if any (used for
	    error state dump only) */
2296 2297
	struct drm_i915_gem_object *batch_obj;

2298 2299 2300
	/** Time at which this request was emitted, in jiffies. */
	unsigned long emitted_jiffies;

2301
	/** global list entry for this request */
2302
	struct list_head list;
2303

2304
	struct drm_i915_file_private *file_priv;
2305 2306
	/** file_priv list entry for this request */
	struct list_head client_list;
2307

2308 2309 2310
	/** process identifier submitting this request */
	struct pid *pid;

2311 2312 2313 2314 2315 2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329
	/**
	 * The ELSP only accepts two elements at a time, so we queue
	 * context/tail pairs on a given queue (ring->execlist_queue) until the
	 * hardware is available. The queue serves a double purpose: we also use
	 * it to keep track of the up to 2 contexts currently in the hardware
	 * (usually one in execution and the other queued up by the GPU): We
	 * only remove elements from the head of the queue when the hardware
	 * informs us that an element has been completed.
	 *
	 * All accesses to the queue are mediated by a spinlock
	 * (ring->execlist_lock).
	 */

	/** Execlist link in the submission queue.*/
	struct list_head execlist_link;

	/** Execlists no. of times this request has been sent to the ELSP */
	int elsp_submitted;

2330 2331
};

2332 2333 2334
struct drm_i915_gem_request * __must_check
i915_gem_request_alloc(struct intel_engine_cs *engine,
		       struct intel_context *ctx);
2335
void i915_gem_request_free(struct kref *req_ref);
2336 2337
int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
				   struct drm_file *file);
2338

2339 2340 2341 2342 2343 2344 2345
static inline uint32_t
i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
{
	return req ? req->seqno : 0;
}

static inline struct intel_engine_cs *
2346
i915_gem_request_get_engine(struct drm_i915_gem_request *req)
2347
{
2348
	return req ? req->engine : NULL;
2349 2350
}

2351
static inline struct drm_i915_gem_request *
2352 2353
i915_gem_request_reference(struct drm_i915_gem_request *req)
{
2354 2355 2356
	if (req)
		kref_get(&req->ref);
	return req;
2357 2358 2359 2360 2361
}

static inline void
i915_gem_request_unreference(struct drm_i915_gem_request *req)
{
2362
	WARN_ON(!mutex_is_locked(&req->engine->dev->struct_mutex));
2363 2364 2365
	kref_put(&req->ref, i915_gem_request_free);
}

2366 2367 2368
static inline void
i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
{
2369 2370 2371 2372
	struct drm_device *dev;

	if (!req)
		return;
2373

2374
	dev = req->engine->dev;
2375
	if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2376 2377 2378
		mutex_unlock(&dev->struct_mutex);
}

2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390
static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
					   struct drm_i915_gem_request *src)
{
	if (src)
		i915_gem_request_reference(src);

	if (*pdst)
		i915_gem_request_unreference(*pdst);

	*pdst = src;
}

2391 2392 2393 2394 2395 2396
/*
 * XXX: i915_gem_request_completed should be here but currently needs the
 * definition of i915_seqno_passed() which is below. It will be moved in
 * a later patch when the call to i915_seqno_passed() is obsoleted...
 */

2397 2398 2399 2400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448
/*
 * A command that requires special handling by the command parser.
 */
struct drm_i915_cmd_descriptor {
	/*
	 * Flags describing how the command parser processes the command.
	 *
	 * CMD_DESC_FIXED: The command has a fixed length if this is set,
	 *                 a length mask if not set
	 * CMD_DESC_SKIP: The command is allowed but does not follow the
	 *                standard length encoding for the opcode range in
	 *                which it falls
	 * CMD_DESC_REJECT: The command is never allowed
	 * CMD_DESC_REGISTER: The command should be checked against the
	 *                    register whitelist for the appropriate ring
	 * CMD_DESC_MASTER: The command is allowed if the submitting process
	 *                  is the DRM master
	 */
	u32 flags;
#define CMD_DESC_FIXED    (1<<0)
#define CMD_DESC_SKIP     (1<<1)
#define CMD_DESC_REJECT   (1<<2)
#define CMD_DESC_REGISTER (1<<3)
#define CMD_DESC_BITMASK  (1<<4)
#define CMD_DESC_MASTER   (1<<5)

	/*
	 * The command's unique identification bits and the bitmask to get them.
	 * This isn't strictly the opcode field as defined in the spec and may
	 * also include type, subtype, and/or subop fields.
	 */
	struct {
		u32 value;
		u32 mask;
	} cmd;

	/*
	 * The command's length. The command is either fixed length (i.e. does
	 * not include a length field) or has a length field mask. The flag
	 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
	 * a length mask. All command entries in a command table must include
	 * length information.
	 */
	union {
		u32 fixed;
		u32 mask;
	} length;

	/*
	 * Describes where to find a register address in the command to check
	 * against the ring's register whitelist. Only valid if flags has the
	 * CMD_DESC_REGISTER bit set.
2449 2450 2451 2452
	 *
	 * A non-zero step value implies that the command may access multiple
	 * registers in sequence (e.g. LRI), in that case step gives the
	 * distance in dwords between individual offset fields.
2453 2454 2455 2456
	 */
	struct {
		u32 offset;
		u32 mask;
2457
		u32 step;
2458 2459 2460 2461 2462 2463 2464 2465 2466
	} reg;

#define MAX_CMD_DESC_BITMASKS 3
	/*
	 * Describes command checks where a particular dword is masked and
	 * compared against an expected value. If the command does not match
	 * the expected value, the parser rejects it. Only valid if flags has
	 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
	 * are valid.
2467 2468 2469 2470
	 *
	 * If the check specifies a non-zero condition_mask then the parser
	 * only performs the check when the bits specified by condition_mask
	 * are non-zero.
2471 2472 2473 2474 2475
	 */
	struct {
		u32 offset;
		u32 mask;
		u32 expected;
2476 2477
		u32 condition_offset;
		u32 condition_mask;
2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491
	} bits[MAX_CMD_DESC_BITMASKS];
};

/*
 * A table of commands requiring special handling by the command parser.
 *
 * Each ring has an array of tables. Each table consists of an array of command
 * descriptors, which must be sorted with command opcodes in ascending order.
 */
struct drm_i915_cmd_table {
	const struct drm_i915_cmd_descriptor *table;
	int count;
};

C
Chris Wilson 已提交
2492
/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2493 2494 2495 2496 2497 2498 2499 2500 2501 2502
#define __I915__(p) ({ \
	struct drm_i915_private *__p; \
	if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
		__p = (struct drm_i915_private *)p; \
	else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
		__p = to_i915((struct drm_device *)p); \
	else \
		BUILD_BUG(); \
	__p; \
})
C
Chris Wilson 已提交
2503
#define INTEL_INFO(p) 	(&__I915__(p)->info)
2504
#define INTEL_GEN(p)	(INTEL_INFO(p)->gen)
2505
#define INTEL_DEVID(p)	(INTEL_INFO(p)->device_id)
2506
#define INTEL_REVID(p)	(__I915__(p)->dev->pdev->revision)
2507

2508 2509 2510 2511 2512 2513 2514 2515 2516
#define REVID_FOREVER		0xff
/*
 * Return true if revision is in range [since,until] inclusive.
 *
 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
 */
#define IS_REVID(p, since, until) \
	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))

2517 2518
#define IS_I830(dev)		(INTEL_DEVID(dev) == 0x3577)
#define IS_845G(dev)		(INTEL_DEVID(dev) == 0x2562)
2519
#define IS_I85X(dev)		(INTEL_INFO(dev)->is_i85x)
2520
#define IS_I865G(dev)		(INTEL_DEVID(dev) == 0x2572)
2521
#define IS_I915G(dev)		(INTEL_INFO(dev)->is_i915g)
2522 2523
#define IS_I915GM(dev)		(INTEL_DEVID(dev) == 0x2592)
#define IS_I945G(dev)		(INTEL_DEVID(dev) == 0x2772)
2524 2525 2526
#define IS_I945GM(dev)		(INTEL_INFO(dev)->is_i945gm)
#define IS_BROADWATER(dev)	(INTEL_INFO(dev)->is_broadwater)
#define IS_CRESTLINE(dev)	(INTEL_INFO(dev)->is_crestline)
2527
#define IS_GM45(dev)		(INTEL_DEVID(dev) == 0x2A42)
2528
#define IS_G4X(dev)		(INTEL_INFO(dev)->is_g4x)
2529 2530
#define IS_PINEVIEW_G(dev)	(INTEL_DEVID(dev) == 0xa001)
#define IS_PINEVIEW_M(dev)	(INTEL_DEVID(dev) == 0xa011)
2531 2532
#define IS_PINEVIEW(dev)	(INTEL_INFO(dev)->is_pineview)
#define IS_G33(dev)		(INTEL_INFO(dev)->is_g33)
2533
#define IS_IRONLAKE_M(dev)	(INTEL_DEVID(dev) == 0x0046)
2534
#define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
2535 2536 2537
#define IS_IVB_GT1(dev)		(INTEL_DEVID(dev) == 0x0156 || \
				 INTEL_DEVID(dev) == 0x0152 || \
				 INTEL_DEVID(dev) == 0x015a)
2538
#define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
2539
#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_cherryview)
2540
#define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
2541
#define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
2542
#define IS_SKYLAKE(dev)	(INTEL_INFO(dev)->is_skylake)
2543
#define IS_BROXTON(dev)		(INTEL_INFO(dev)->is_broxton)
2544
#define IS_KABYLAKE(dev)	(INTEL_INFO(dev)->is_kabylake)
2545
#define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
2546
#define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \
2547
				 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
B
Ben Widawsky 已提交
2548
#define IS_BDW_ULT(dev)		(IS_BROADWELL(dev) && \
2549
				 ((INTEL_DEVID(dev) & 0xf) == 0x6 ||	\
2550
				 (INTEL_DEVID(dev) & 0xf) == 0xb ||	\
2551
				 (INTEL_DEVID(dev) & 0xf) == 0xe))
V
Ville Syrjälä 已提交
2552 2553 2554
/* ULX machines are also considered ULT. */
#define IS_BDW_ULX(dev)		(IS_BROADWELL(dev) && \
				 (INTEL_DEVID(dev) & 0xf) == 0xe)
R
Rodrigo Vivi 已提交
2555 2556
#define IS_BDW_GT3(dev)		(IS_BROADWELL(dev) && \
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
B
Ben Widawsky 已提交
2557
#define IS_HSW_ULT(dev)		(IS_HASWELL(dev) && \
2558
				 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2559
#define IS_HSW_GT3(dev)		(IS_HASWELL(dev) && \
2560
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2561
/* ULX machines are also considered ULT. */
2562 2563
#define IS_HSW_ULX(dev)		(INTEL_DEVID(dev) == 0x0A0E || \
				 INTEL_DEVID(dev) == 0x0A1E)
2564 2565 2566 2567 2568 2569 2570 2571
#define IS_SKL_ULT(dev)		(INTEL_DEVID(dev) == 0x1906 || \
				 INTEL_DEVID(dev) == 0x1913 || \
				 INTEL_DEVID(dev) == 0x1916 || \
				 INTEL_DEVID(dev) == 0x1921 || \
				 INTEL_DEVID(dev) == 0x1926)
#define IS_SKL_ULX(dev)		(INTEL_DEVID(dev) == 0x190E || \
				 INTEL_DEVID(dev) == 0x1915 || \
				 INTEL_DEVID(dev) == 0x191E)
2572 2573 2574 2575 2576 2577 2578 2579
#define IS_KBL_ULT(dev)		(INTEL_DEVID(dev) == 0x5906 || \
				 INTEL_DEVID(dev) == 0x5913 || \
				 INTEL_DEVID(dev) == 0x5916 || \
				 INTEL_DEVID(dev) == 0x5921 || \
				 INTEL_DEVID(dev) == 0x5926)
#define IS_KBL_ULX(dev)		(INTEL_DEVID(dev) == 0x590E || \
				 INTEL_DEVID(dev) == 0x5915 || \
				 INTEL_DEVID(dev) == 0x591E)
2580 2581 2582 2583 2584
#define IS_SKL_GT3(dev)		(IS_SKYLAKE(dev) && \
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
#define IS_SKL_GT4(dev)		(IS_SKYLAKE(dev) && \
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)

2585
#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2586

2587 2588 2589 2590 2591 2592 2593
#define SKL_REVID_A0		0x0
#define SKL_REVID_B0		0x1
#define SKL_REVID_C0		0x2
#define SKL_REVID_D0		0x3
#define SKL_REVID_E0		0x4
#define SKL_REVID_F0		0x5

2594 2595
#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))

2596
#define BXT_REVID_A0		0x0
2597
#define BXT_REVID_A1		0x1
2598 2599
#define BXT_REVID_B0		0x3
#define BXT_REVID_C0		0x9
N
Nick Hoath 已提交
2600

2601 2602
#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))

2603 2604 2605 2606 2607 2608
/*
 * The genX designation typically refers to the render engine, so render
 * capability related checks should use IS_GEN, while display and other checks
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 * chips, etc.).
 */
2609 2610 2611 2612 2613
#define IS_GEN2(dev)	(INTEL_INFO(dev)->gen == 2)
#define IS_GEN3(dev)	(INTEL_INFO(dev)->gen == 3)
#define IS_GEN4(dev)	(INTEL_INFO(dev)->gen == 4)
#define IS_GEN5(dev)	(INTEL_INFO(dev)->gen == 5)
#define IS_GEN6(dev)	(INTEL_INFO(dev)->gen == 6)
2614
#define IS_GEN7(dev)	(INTEL_INFO(dev)->gen == 7)
B
Ben Widawsky 已提交
2615
#define IS_GEN8(dev)	(INTEL_INFO(dev)->gen == 8)
2616
#define IS_GEN9(dev)	(INTEL_INFO(dev)->gen == 9)
2617

2618 2619 2620 2621
#define RENDER_RING		(1<<RCS)
#define BSD_RING		(1<<VCS)
#define BLT_RING		(1<<BCS)
#define VEBOX_RING		(1<<VECS)
2622
#define BSD2_RING		(1<<VCS2)
2623 2624
#define ALL_ENGINES		(~0)

2625
#define HAS_BSD(dev)		(INTEL_INFO(dev)->ring_mask & BSD_RING)
2626
#define HAS_BSD2(dev)		(INTEL_INFO(dev)->ring_mask & BSD2_RING)
2627 2628 2629
#define HAS_BLT(dev)		(INTEL_INFO(dev)->ring_mask & BLT_RING)
#define HAS_VEBOX(dev)		(INTEL_INFO(dev)->ring_mask & VEBOX_RING)
#define HAS_LLC(dev)		(INTEL_INFO(dev)->has_llc)
2630
#define HAS_SNOOP(dev)		(INTEL_INFO(dev)->has_snoop)
2631
#define HAS_EDRAM(dev)		(__I915__(dev)->edram_cap & EDRAM_ENABLED)
2632
#define HAS_WT(dev)		((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2633
				 HAS_EDRAM(dev))
2634 2635
#define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)

2636
#define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 6)
2637
#define HAS_LOGICAL_RING_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 8)
2638
#define USES_PPGTT(dev)		(i915.enable_ppgtt)
2639 2640
#define USES_FULL_PPGTT(dev)	(i915.enable_ppgtt >= 2)
#define USES_FULL_48BIT_PPGTT(dev)	(i915.enable_ppgtt == 3)
2641

2642
#define HAS_OVERLAY(dev)		(INTEL_INFO(dev)->has_overlay)
2643 2644
#define OVERLAY_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->overlay_needs_physical)

2645 2646
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
#define HAS_BROKEN_CS_TLB(dev)		(IS_I830(dev) || IS_845G(dev))
2647 2648 2649

/* WaRsDisableCoarsePowerGating:skl,bxt */
#define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
2650 2651 2652
						 IS_SKL_GT3(dev) || \
						 IS_SKL_GT4(dev))

2653 2654 2655 2656 2657 2658 2659 2660
/*
 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
 * even when in MSI mode. This results in spurious interrupt warnings if the
 * legacy irq no. is shared with another device. The kernel then disables that
 * interrupt source and so prevents the other device from working properly.
 */
#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2661

2662 2663 2664 2665 2666 2667 2668 2669 2670 2671
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
						      IS_I915GM(dev)))
#define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)
#define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)

#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2672
#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2673

2674
#define HAS_IPS(dev)		(IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2675

2676 2677 2678
#define HAS_DP_MST(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \
				 INTEL_INFO(dev)->gen >= 9)

2679
#define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
2680
#define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
2681
#define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2682
				 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2683
				 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2684
#define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
S
Suketu Shah 已提交
2685
				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2686
				 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
I
Imre Deak 已提交
2687
				 IS_KABYLAKE(dev) || IS_BROXTON(dev))
2688 2689
#define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
#define HAS_RC6p(dev)		(INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
P
Paulo Zanoni 已提交
2690

2691
#define HAS_CSR(dev)	(IS_GEN9(dev))
2692

2693 2694
#define HAS_GUC_UCODE(dev)	(IS_GEN9(dev) && !IS_KABYLAKE(dev))
#define HAS_GUC_SCHED(dev)	(IS_GEN9(dev) && !IS_KABYLAKE(dev))
2695

2696 2697 2698
#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
				    INTEL_INFO(dev)->gen >= 8)

2699
#define HAS_CORE_RING_FREQ(dev)	(INTEL_INFO(dev)->gen >= 6 && \
2700 2701
				 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
				 !IS_BROXTON(dev))
2702

2703 2704 2705 2706 2707 2708
#define INTEL_PCH_DEVICE_ID_MASK		0xff00
#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
2709 2710
#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
2711
#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
2712
#define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
2713
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
2714

2715
#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2716
#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2717
#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2718
#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
V
Ville Syrjälä 已提交
2719
#define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2720 2721
#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
B
Ben Widawsky 已提交
2722
#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2723
#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2724

2725 2726
#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
			       IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2727

2728 2729 2730
/* DPF == dynamic parity feature */
#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2731

2732
#define GT_FREQUENCY_MULTIPLIER 50
A
Akash Goel 已提交
2733
#define GEN9_FREQ_SCALER 3
2734

2735 2736
#include "i915_trace.h"

R
Rob Clark 已提交
2737
extern const struct drm_ioctl_desc i915_ioctls[];
2738 2739
extern int i915_max_ioctl;

2740 2741
extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
extern int i915_resume_switcheroo(struct drm_device *dev);
2742

2743
/* i915_dma.c */
2744 2745 2746 2747 2748 2749 2750
void __printf(3, 4)
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
	      const char *fmt, ...);

#define i915_report_error(dev_priv, fmt, ...)				   \
	__i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)

2751
extern int i915_driver_load(struct drm_device *, unsigned long flags);
J
Jesse Barnes 已提交
2752
extern int i915_driver_unload(struct drm_device *);
2753
extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2754
extern void i915_driver_lastclose(struct drm_device * dev);
2755
extern void i915_driver_preclose(struct drm_device *dev,
2756
				 struct drm_file *file);
2757
extern void i915_driver_postclose(struct drm_device *dev,
2758
				  struct drm_file *file);
2759
#ifdef CONFIG_COMPAT
D
Dave Airlie 已提交
2760 2761
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);
2762
#endif
2763
extern int intel_gpu_reset(struct drm_device *dev, u32 engine_mask);
2764
extern bool intel_has_gpu_reset(struct drm_device *dev);
2765
extern int i915_reset(struct drm_device *dev);
2766
extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2767
extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2768 2769 2770 2771
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2772
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2773

2774 2775 2776 2777 2778
/* intel_hotplug.c */
void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
void intel_hpd_init(struct drm_i915_private *dev_priv);
void intel_hpd_init_work(struct drm_i915_private *dev_priv);
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2779
bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2780

L
Linus Torvalds 已提交
2781
/* i915_irq.c */
2782
void i915_queue_hangcheck(struct drm_device *dev);
2783
__printf(3, 4)
2784
void i915_handle_error(struct drm_device *dev, u32 engine_mask,
2785
		       const char *fmt, ...);
L
Linus Torvalds 已提交
2786

2787
extern void intel_irq_init(struct drm_i915_private *dev_priv);
2788 2789
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2790 2791

extern void intel_uncore_sanitize(struct drm_device *dev);
2792 2793
extern void intel_uncore_early_sanitize(struct drm_device *dev,
					bool restore_forcewake);
2794
extern void intel_uncore_init(struct drm_device *dev);
2795
extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2796
extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2797
extern void intel_uncore_fini(struct drm_device *dev);
2798
extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2799
const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2800
void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2801
				enum forcewake_domains domains);
2802
void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2803
				enum forcewake_domains domains);
2804 2805 2806 2807 2808 2809 2810
/* Like above but the caller must manage the uncore.lock itself.
 * Must be used with I915_READ_FW and friends.
 */
void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
2811 2812
u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);

2813
void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2814 2815 2816 2817
static inline bool intel_vgpu_active(struct drm_device *dev)
{
	return to_i915(dev)->vgpu.active;
}
2818

2819
void
2820
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2821
		     u32 status_mask);
2822 2823

void
2824
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2825
		      u32 status_mask);
2826

2827 2828
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2829 2830 2831
void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
				   uint32_t mask,
				   uint32_t bits);
2832 2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844
void ilk_update_display_irq(struct drm_i915_private *dev_priv,
			    uint32_t interrupt_mask,
			    uint32_t enabled_irq_mask);
static inline void
ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, bits);
}
static inline void
ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, 0);
}
2845 2846 2847 2848 2849 2850 2851 2852 2853 2854 2855 2856 2857 2858
void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
			 enum pipe pipe,
			 uint32_t interrupt_mask,
			 uint32_t enabled_irq_mask);
static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
				       enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
}
static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
					enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
}
2859 2860 2861
void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask);
2862 2863 2864 2865 2866 2867 2868 2869 2870 2871 2872
static inline void
ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, bits);
}
static inline void
ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, 0);
}

2873

2874 2875 2876 2877 2878 2879 2880 2881 2882
/* i915_gem.c */
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2883 2884
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2885 2886 2887 2888
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
			     struct drm_file *file_priv);
2889
void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2890
					struct drm_i915_gem_request *req);
2891
int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
2892
				   struct drm_i915_gem_execbuffer2 *args,
2893
				   struct list_head *vmas);
2894 2895
int i915_gem_execbuffer(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
J
Jesse Barnes 已提交
2896 2897
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
2898 2899
int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
B
Ben Widawsky 已提交
2900 2901 2902 2903
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
2904 2905
int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
2906 2907
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
2908 2909 2910 2911
int i915_gem_set_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
int i915_gem_get_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2912 2913 2914
int i915_gem_init_userptr(struct drm_device *dev);
int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file);
2915 2916
int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
2917 2918
int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2919 2920
void i915_gem_load_init(struct drm_device *dev);
void i915_gem_load_cleanup(struct drm_device *dev);
2921
void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
2922 2923
void *i915_gem_object_alloc(struct drm_device *dev);
void i915_gem_object_free(struct drm_i915_gem_object *obj);
2924 2925
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			 const struct drm_i915_gem_object_ops *ops);
2926 2927
struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
						  size_t size);
2928 2929
struct drm_i915_gem_object *i915_gem_object_create_from_data(
		struct drm_device *dev, const void *data, size_t size);
2930
void i915_gem_free_object(struct drm_gem_object *obj);
B
Ben Widawsky 已提交
2931
void i915_gem_vma_destroy(struct i915_vma *vma);
2932

2933 2934 2935 2936 2937 2938 2939
/* Flags used by pin/bind&friends. */
#define PIN_MAPPABLE	(1<<0)
#define PIN_NONBLOCK	(1<<1)
#define PIN_GLOBAL	(1<<2)
#define PIN_OFFSET_BIAS	(1<<3)
#define PIN_USER	(1<<4)
#define PIN_UPDATE	(1<<5)
2940 2941
#define PIN_ZONE_4G	(1<<6)
#define PIN_HIGH	(1<<7)
2942
#define PIN_OFFSET_FIXED	(1<<8)
2943
#define PIN_OFFSET_MASK (~4095)
2944 2945 2946 2947 2948 2949 2950 2951 2952 2953
int __must_check
i915_gem_object_pin(struct drm_i915_gem_object *obj,
		    struct i915_address_space *vm,
		    uint32_t alignment,
		    uint64_t flags);
int __must_check
i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
			 const struct i915_ggtt_view *view,
			 uint32_t alignment,
			 uint64_t flags);
2954 2955 2956

int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
		  u32 flags);
2957
void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
2958
int __must_check i915_vma_unbind(struct i915_vma *vma);
2959 2960 2961 2962 2963
/*
 * BEWARE: Do not use the function below unless you can _absolutely_
 * _guarantee_ VMA in question is _not in use_ anywhere.
 */
int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
2964
int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2965
void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2966
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2967

2968 2969 2970
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
				    int *needs_clflush);

2971
int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2972 2973

static inline int __sg_page_count(struct scatterlist *sg)
2974
{
2975 2976
	return sg->length >> PAGE_SHIFT;
}
2977

2978 2979 2980
struct page *
i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);

2981 2982
static inline struct page *
i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2983
{
2984 2985
	if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
		return NULL;
2986

2987 2988 2989 2990
	if (n < obj->get_page.last) {
		obj->get_page.sg = obj->pages->sgl;
		obj->get_page.last = 0;
	}
2991

2992 2993 2994 2995 2996
	while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
		obj->get_page.last += __sg_page_count(obj->get_page.sg++);
		if (unlikely(sg_is_chain(obj->get_page.sg)))
			obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
	}
2997

2998
	return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2999
}
3000

3001 3002 3003 3004 3005
static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
{
	BUG_ON(obj->pages == NULL);
	obj->pages_pin_count++;
}
3006

3007 3008 3009 3010 3011 3012
static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
{
	BUG_ON(obj->pages_pin_count == 0);
	obj->pages_pin_count--;
}

3013 3014 3015 3016 3017 3018 3019 3020
/**
 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
 * @obj - the object to map into kernel address space
 *
 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
 * pages and then returns a contiguous mapping of the backing storage into
 * the kernel address space.
 *
3021 3022
 * The caller must hold the struct_mutex, and is responsible for calling
 * i915_gem_object_unpin_map() when the mapping is no longer required.
3023
 *
3024 3025
 * Returns the pointer through which to access the mapped object, or an
 * ERR_PTR() on error.
3026 3027 3028 3029 3030 3031 3032 3033 3034 3035 3036 3037 3038 3039 3040 3041 3042 3043 3044 3045
 */
void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj);

/**
 * i915_gem_object_unpin_map - releases an earlier mapping
 * @obj - the object to unmap
 *
 * After pinning the object and mapping its pages, once you are finished
 * with your access, call i915_gem_object_unpin_map() to release the pin
 * upon the mapping. Once the pin count reaches zero, that mapping may be
 * removed.
 *
 * The caller must hold the struct_mutex.
 */
static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
{
	lockdep_assert_held(&obj->base.dev->struct_mutex);
	i915_gem_object_unpin_pages(obj);
}

3046
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3047
int i915_gem_object_sync(struct drm_i915_gem_object *obj,
3048 3049
			 struct intel_engine_cs *to,
			 struct drm_i915_gem_request **to_req);
B
Ben Widawsky 已提交
3050
void i915_vma_move_to_active(struct i915_vma *vma,
3051
			     struct drm_i915_gem_request *req);
3052 3053 3054
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
3055 3056
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
		      uint32_t handle, uint64_t *offset);
3057 3058 3059 3060 3061 3062 3063 3064 3065
/**
 * Returns true if seq1 is later than seq2.
 */
static inline bool
i915_seqno_passed(uint32_t seq1, uint32_t seq2)
{
	return (int32_t)(seq1 - seq2) >= 0;
}

3066 3067 3068
static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
					   bool lazy_coherency)
{
3069 3070 3071 3072
	if (!lazy_coherency && req->engine->irq_seqno_barrier)
		req->engine->irq_seqno_barrier(req->engine);
	return i915_seqno_passed(req->engine->get_seqno(req->engine),
				 req->previous_seqno);
3073 3074
}

3075 3076 3077
static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
					      bool lazy_coherency)
{
3078 3079 3080 3081
	if (!lazy_coherency && req->engine->irq_seqno_barrier)
		req->engine->irq_seqno_barrier(req->engine);
	return i915_seqno_passed(req->engine->get_seqno(req->engine),
				 req->seqno);
3082 3083
}

3084 3085
int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3086

3087
struct drm_i915_gem_request *
3088
i915_gem_find_active_request(struct intel_engine_cs *engine);
3089

3090
bool i915_gem_retire_requests(struct drm_device *dev);
3091
void i915_gem_retire_requests_ring(struct intel_engine_cs *engine);
3092

3093 3094 3095 3096 3097 3098 3099 3100 3101 3102 3103 3104 3105 3106 3107 3108 3109 3110 3111 3112
static inline u32 i915_reset_counter(struct i915_gpu_error *error)
{
	return atomic_read(&error->reset_counter);
}

static inline bool __i915_reset_in_progress(u32 reset)
{
	return unlikely(reset & I915_RESET_IN_PROGRESS_FLAG);
}

static inline bool __i915_reset_in_progress_or_wedged(u32 reset)
{
	return unlikely(reset & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
}

static inline bool __i915_terminally_wedged(u32 reset)
{
	return unlikely(reset & I915_WEDGED);
}

3113 3114
static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
{
3115 3116 3117 3118 3119 3120
	return __i915_reset_in_progress(i915_reset_counter(error));
}

static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
{
	return __i915_reset_in_progress_or_wedged(i915_reset_counter(error));
3121 3122 3123 3124
}

static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
{
3125
	return __i915_terminally_wedged(i915_reset_counter(error));
M
Mika Kuoppala 已提交
3126 3127 3128 3129
}

static inline u32 i915_reset_count(struct i915_gpu_error *error)
{
3130
	return ((i915_reset_counter(error) & ~I915_WEDGED) + 1) / 2;
3131
}
3132

3133 3134 3135 3136 3137 3138 3139 3140 3141 3142 3143 3144
static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
{
	return dev_priv->gpu_error.stop_rings == 0 ||
		dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
}

static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
{
	return dev_priv->gpu_error.stop_rings == 0 ||
		dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
}

3145
void i915_gem_reset(struct drm_device *dev);
3146
bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3147
int __must_check i915_gem_init(struct drm_device *dev);
3148
int i915_gem_init_engines(struct drm_device *dev);
3149
int __must_check i915_gem_init_hw(struct drm_device *dev);
3150
int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
3151
void i915_gem_init_swizzling(struct drm_device *dev);
3152
void i915_gem_cleanup_engines(struct drm_device *dev);
3153
int __must_check i915_gpu_idle(struct drm_device *dev);
3154
int __must_check i915_gem_suspend(struct drm_device *dev);
3155
void __i915_add_request(struct drm_i915_gem_request *req,
3156 3157
			struct drm_i915_gem_object *batch_obj,
			bool flush_caches);
3158
#define i915_add_request(req) \
3159
	__i915_add_request(req, NULL, true)
3160
#define i915_add_request_no_flush(req) \
3161
	__i915_add_request(req, NULL, false)
3162
int __i915_wait_request(struct drm_i915_gem_request *req,
3163 3164
			bool interruptible,
			s64 *timeout,
3165
			struct intel_rps_client *rps);
3166
int __must_check i915_wait_request(struct drm_i915_gem_request *req);
3167
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3168
int __must_check
3169 3170 3171
i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
			       bool readonly);
int __must_check
3172 3173 3174
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
				  bool write);
int __must_check
3175 3176
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
int __must_check
3177 3178
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
3179 3180 3181
				     const struct i915_ggtt_view *view);
void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
					      const struct i915_ggtt_view *view);
3182
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3183
				int align);
3184
int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3185
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3186

3187 3188
uint32_t
i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3189
uint32_t
3190 3191
i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
			    int tiling_mode, bool fenced);
3192

3193 3194 3195
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);

3196 3197 3198 3199 3200 3201
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
				struct dma_buf *dma_buf);

struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
				struct drm_gem_object *gem_obj, int flags);

3202 3203 3204 3205 3206
u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
				  const struct i915_ggtt_view *view);
u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
			struct i915_address_space *vm);
static inline u64
3207
i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3208
{
3209
	return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3210
}
3211

3212
bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3213
bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3214
				  const struct i915_ggtt_view *view);
3215
bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3216
			struct i915_address_space *vm);
3217

3218 3219
unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
				struct i915_address_space *vm);
3220
struct i915_vma *
3221 3222 3223 3224 3225
i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
		    struct i915_address_space *vm);
struct i915_vma *
i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
			  const struct i915_ggtt_view *view);
3226

3227 3228
struct i915_vma *
i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3229 3230 3231 3232
				  struct i915_address_space *vm);
struct i915_vma *
i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
				       const struct i915_ggtt_view *view);
3233

3234 3235 3236 3237
static inline struct i915_vma *
i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
{
	return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
B
Ben Widawsky 已提交
3238
}
3239
bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3240

3241
/* Some GGTT VM helpers */
3242 3243 3244 3245 3246 3247 3248
static inline struct i915_hw_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space *vm)
{
	return container_of(vm, struct i915_hw_ppgtt, base);
}


3249 3250
static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
{
3251
	return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3252 3253 3254 3255 3256
}

static inline unsigned long
i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
{
3257 3258 3259 3260
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
	struct i915_ggtt *ggtt = &dev_priv->ggtt;

	return i915_gem_obj_size(obj, &ggtt->base);
3261
}
B
Ben Widawsky 已提交
3262 3263 3264 3265

static inline int __must_check
i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
		      uint32_t alignment,
3266
		      unsigned flags)
B
Ben Widawsky 已提交
3267
{
3268 3269 3270 3271
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
	struct i915_ggtt *ggtt = &dev_priv->ggtt;

	return i915_gem_object_pin(obj, &ggtt->base,
3272
				   alignment, flags | PIN_GLOBAL);
B
Ben Widawsky 已提交
3273
}
3274

3275 3276 3277 3278 3279 3280
static inline int
i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
{
	return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
}

3281 3282 3283 3284 3285 3286 3287
void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
				     const struct i915_ggtt_view *view);
static inline void
i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
{
	i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
}
3288

3289 3290 3291 3292 3293 3294 3295 3296 3297
/* i915_gem_fence.c */
int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);

bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);

void i915_gem_restore_fences(struct drm_device *dev);

3298 3299 3300 3301
void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);

3302
/* i915_gem_context.c */
3303
int __must_check i915_gem_context_init(struct drm_device *dev);
3304
void i915_gem_context_fini(struct drm_device *dev);
3305
void i915_gem_context_reset(struct drm_device *dev);
3306
int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3307
int i915_gem_context_enable(struct drm_i915_gem_request *req);
3308
void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3309
int i915_switch_context(struct drm_i915_gem_request *req);
3310
struct intel_context *
3311
i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3312
void i915_gem_context_free(struct kref *ctx_ref);
3313 3314
struct drm_i915_gem_object *
i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3315
static inline void i915_gem_context_reference(struct intel_context *ctx)
3316
{
3317
	kref_get(&ctx->ref);
3318 3319
}

3320
static inline void i915_gem_context_unreference(struct intel_context *ctx)
3321
{
3322
	kref_put(&ctx->ref, i915_gem_context_free);
3323 3324
}

3325
static inline bool i915_gem_context_is_default(const struct intel_context *c)
3326
{
3327
	return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3328 3329
}

3330 3331 3332 3333
int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
				  struct drm_file *file);
int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
				   struct drm_file *file);
3334 3335 3336 3337
int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file_priv);
int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file_priv);
3338

3339 3340 3341 3342 3343 3344
/* i915_gem_evict.c */
int __must_check i915_gem_evict_something(struct drm_device *dev,
					  struct i915_address_space *vm,
					  int min_size,
					  unsigned alignment,
					  unsigned cache_level,
3345 3346
					  unsigned long start,
					  unsigned long end,
3347
					  unsigned flags);
3348
int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3349
int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3350

3351
/* belongs in i915_gem_gtt.h */
3352
static inline void i915_gem_chipset_flush(struct drm_device *dev)
3353 3354 3355 3356
{
	if (INTEL_INFO(dev)->gen < 6)
		intel_gtt_chipset_flush();
}
3357

3358
/* i915_gem_stolen.c */
3359 3360 3361
int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
				struct drm_mm_node *node, u64 size,
				unsigned alignment);
3362 3363 3364 3365
int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
					 struct drm_mm_node *node, u64 size,
					 unsigned alignment, u64 start,
					 u64 end);
3366 3367
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
				 struct drm_mm_node *node);
3368 3369
int i915_gem_init_stolen(struct drm_device *dev);
void i915_gem_cleanup_stolen(struct drm_device *dev);
3370 3371
struct drm_i915_gem_object *
i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3372 3373 3374 3375 3376
struct drm_i915_gem_object *
i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
					       u32 stolen_offset,
					       u32 gtt_offset,
					       u32 size);
3377

3378 3379
/* i915_gem_shrinker.c */
unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3380
			      unsigned long target,
3381 3382 3383 3384
			      unsigned flags);
#define I915_SHRINK_PURGEABLE 0x1
#define I915_SHRINK_UNBOUND 0x2
#define I915_SHRINK_BOUND 0x4
3385
#define I915_SHRINK_ACTIVE 0x8
3386
#define I915_SHRINK_VMAPS 0x10
3387 3388
unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3389
void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3390 3391


3392
/* i915_gem_tiling.c */
3393
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3394
{
3395
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3396 3397 3398 3399 3400

	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
		obj->tiling_mode != I915_TILING_NONE;
}

3401
/* i915_gem_debug.c */
3402 3403
#if WATCH_LISTS
int i915_verify_lists(struct drm_device *dev);
3404
#else
3405
#define i915_verify_lists(dev) 0
3406
#endif
L
Linus Torvalds 已提交
3407

3408
/* i915_debugfs.c */
3409 3410
int i915_debugfs_init(struct drm_minor *minor);
void i915_debugfs_cleanup(struct drm_minor *minor);
3411
#ifdef CONFIG_DEBUG_FS
J
Jani Nikula 已提交
3412
int i915_debugfs_connector_add(struct drm_connector *connector);
3413 3414
void intel_display_crc_init(struct drm_device *dev);
#else
3415 3416
static inline int i915_debugfs_connector_add(struct drm_connector *connector)
{ return 0; }
3417
static inline void intel_display_crc_init(struct drm_device *dev) {}
3418
#endif
3419 3420

/* i915_gpu_error.c */
3421 3422
__printf(2, 3)
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3423 3424
int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
			    const struct i915_error_state_file_priv *error);
3425
int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3426
			      struct drm_i915_private *i915,
3427 3428 3429 3430 3431 3432
			      size_t count, loff_t pos);
static inline void i915_error_state_buf_release(
	struct drm_i915_error_state_buf *eb)
{
	kfree(eb->buf);
}
3433
void i915_capture_error_state(struct drm_device *dev, u32 engine_mask,
3434
			      const char *error_msg);
3435 3436 3437 3438 3439 3440
void i915_error_state_get(struct drm_device *dev,
			  struct i915_error_state_file_priv *error_priv);
void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
void i915_destroy_error_state(struct drm_device *dev);

void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3441
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3442

3443
/* i915_cmd_parser.c */
3444
int i915_cmd_parser_get_version(void);
3445 3446 3447 3448
int i915_cmd_parser_init_ring(struct intel_engine_cs *engine);
void i915_cmd_parser_fini_ring(struct intel_engine_cs *engine);
bool i915_needs_cmd_parser(struct intel_engine_cs *engine);
int i915_parse_cmds(struct intel_engine_cs *engine,
3449
		    struct drm_i915_gem_object *batch_obj,
3450
		    struct drm_i915_gem_object *shadow_batch_obj,
3451
		    u32 batch_start_offset,
3452
		    u32 batch_len,
3453 3454
		    bool is_master);

3455 3456 3457
/* i915_suspend.c */
extern int i915_save_state(struct drm_device *dev);
extern int i915_restore_state(struct drm_device *dev);
3458

B
Ben Widawsky 已提交
3459 3460 3461 3462
/* i915_sysfs.c */
void i915_setup_sysfs(struct drm_device *dev_priv);
void i915_teardown_sysfs(struct drm_device *dev_priv);

3463 3464 3465
/* intel_i2c.c */
extern int intel_setup_gmbus(struct drm_device *dev);
extern void intel_teardown_gmbus(struct drm_device *dev);
3466 3467
extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
				     unsigned int pin);
3468

3469 3470
extern struct i2c_adapter *
intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
C
Chris Wilson 已提交
3471 3472
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3473
static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3474 3475 3476
{
	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
}
3477 3478
extern void intel_i2c_reset(struct drm_device *dev);

3479
/* intel_bios.c */
3480
int intel_bios_init(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3481
bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3482
bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3483
bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3484
bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3485
bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3486 3487
bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
				     enum port port);
3488

3489
/* intel_opregion.c */
3490
#ifdef CONFIG_ACPI
3491
extern int intel_opregion_setup(struct drm_device *dev);
3492 3493
extern void intel_opregion_init(struct drm_device *dev);
extern void intel_opregion_fini(struct drm_device *dev);
3494
extern void intel_opregion_asle_intr(struct drm_device *dev);
3495 3496
extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
					 bool enable);
3497 3498
extern int intel_opregion_notify_adapter(struct drm_device *dev,
					 pci_power_t state);
3499
extern int intel_opregion_get_panel_type(struct drm_device *dev);
3500
#else
3501
static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3502 3503
static inline void intel_opregion_init(struct drm_device *dev) { return; }
static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3504
static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3505 3506 3507 3508 3509
static inline int
intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
{
	return 0;
}
3510 3511 3512 3513 3514
static inline int
intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
{
	return 0;
}
3515 3516 3517 3518
static inline int intel_opregion_get_panel_type(struct drm_device *dev)
{
	return -ENODEV;
}
3519
#endif
3520

J
Jesse Barnes 已提交
3521 3522 3523 3524 3525 3526 3527 3528 3529
/* intel_acpi.c */
#ifdef CONFIG_ACPI
extern void intel_register_dsm_handler(void);
extern void intel_unregister_dsm_handler(void);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */

J
Jesse Barnes 已提交
3530
/* modesetting */
3531
extern void intel_modeset_init_hw(struct drm_device *dev);
J
Jesse Barnes 已提交
3532
extern void intel_modeset_init(struct drm_device *dev);
3533
extern void intel_modeset_gem_init(struct drm_device *dev);
J
Jesse Barnes 已提交
3534
extern void intel_modeset_cleanup(struct drm_device *dev);
3535
extern void intel_connector_unregister(struct intel_connector *);
3536
extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3537
extern void intel_display_resume(struct drm_device *dev);
3538
extern void i915_redisable_vga(struct drm_device *dev);
3539
extern void i915_redisable_vga_power_on(struct drm_device *dev);
3540
extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
P
Paulo Zanoni 已提交
3541
extern void intel_init_pch_refclk(struct drm_device *dev);
3542
extern void intel_set_rps(struct drm_device *dev, u8 val);
3543 3544
extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
				  bool enable);
3545
extern void intel_detect_pch(struct drm_device *dev);
B
Ben Widawsky 已提交
3546
extern int intel_enable_rc6(const struct drm_device *dev);
3547

3548
extern bool i915_semaphore_is_enabled(struct drm_device *dev);
B
Ben Widawsky 已提交
3549 3550
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file);
3551 3552
int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
3553

3554 3555
/* overlay */
extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3556 3557
extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
					    struct intel_overlay_error_state *error);
3558 3559

extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3560
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3561 3562
					    struct drm_device *dev,
					    struct intel_display_error_state *error);
3563

3564 3565
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3566 3567

/* intel_sideband.c */
3568 3569
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3570
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3571 3572
u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3573 3574 3575 3576
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3577 3578
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3579 3580
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3581 3582 3583 3584
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		   enum intel_sbi_destination destination);
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		     enum intel_sbi_destination destination);
3585 3586
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3587

3588 3589
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3590

3591 3592 3593 3594 3595 3596 3597 3598 3599 3600 3601 3602 3603
#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

#define I915_READ16(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
#define I915_WRITE16(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
#define I915_READ16_NOTRACE(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
#define I915_WRITE16_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)

#define I915_READ(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
#define I915_WRITE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
#define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
#define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)

3604 3605 3606 3607 3608 3609
/* Be very careful with read/write 64-bit values. On 32-bit machines, they
 * will be implemented using 2 32-bit writes in an arbitrary order with
 * an arbitrary delay between them. This can cause the hardware to
 * act upon the intermediate value, possibly leading to corruption and
 * machine death. You have been warned.
 */
3610 3611
#define I915_WRITE64(reg, val)	dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
#define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3612

3613
#define I915_READ64_2x32(lower_reg, upper_reg) ({			\
3614 3615
	u32 upper, lower, old_upper, loop = 0;				\
	upper = I915_READ(upper_reg);					\
3616
	do {								\
3617
		old_upper = upper;					\
3618
		lower = I915_READ(lower_reg);				\
3619 3620
		upper = I915_READ(upper_reg);				\
	} while (upper != old_upper && loop++ < 2);			\
3621
	(u64)upper << 32 | lower; })
3622

3623 3624 3625
#define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)

3626 3627
#define __raw_read(x, s) \
static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3628
					     i915_reg_t reg) \
3629
{ \
3630
	return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3631 3632 3633 3634
}

#define __raw_write(x, s) \
static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3635
				       i915_reg_t reg, uint##x##_t val) \
3636
{ \
3637
	write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3638 3639 3640 3641 3642 3643 3644 3645 3646 3647 3648 3649 3650 3651
}
__raw_read(8, b)
__raw_read(16, w)
__raw_read(32, l)
__raw_read(64, q)

__raw_write(8, b)
__raw_write(16, w)
__raw_write(32, l)
__raw_write(64, q)

#undef __raw_read
#undef __raw_write

3652 3653 3654 3655 3656 3657 3658
/* These are untraced mmio-accessors that are only valid to be used inside
 * criticial sections inside IRQ handlers where forcewake is explicitly
 * controlled.
 * Think twice, and think again, before using these.
 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
 * intel_uncore_forcewake_irqunlock().
 */
3659 3660
#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3661 3662
#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)

3663 3664 3665 3666
/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
#define INTEL_BROADCAST_RGB_FULL 1
#define INTEL_BROADCAST_RGB_LIMITED 2
3667

3668
static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3669
{
3670
	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3671
		return VLV_VGACNTRL;
3672 3673
	else if (INTEL_INFO(dev)->gen >= 5)
		return CPU_VGACNTRL;
3674 3675 3676 3677
	else
		return VGACNTRL;
}

V
Ville Syrjälä 已提交
3678 3679 3680 3681 3682
static inline void __user *to_user_ptr(u64 address)
{
	return (void __user *)(uintptr_t)address;
}

3683 3684 3685 3686 3687 3688 3689
static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
{
	unsigned long j = msecs_to_jiffies(m);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3690 3691 3692 3693 3694
static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
{
        return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
}

3695 3696 3697 3698 3699 3700 3701 3702
static inline unsigned long
timespec_to_jiffies_timeout(const struct timespec *value)
{
	unsigned long j = timespec_to_jiffies(value);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3703 3704 3705 3706 3707 3708 3709 3710 3711
/*
 * If you need to wait X milliseconds between events A and B, but event B
 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
 * when event A happened, then just before event B you call this function and
 * pass the timestamp as the first argument, and X as the second argument.
 */
static inline void
wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
{
3712
	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3713 3714 3715 3716 3717 3718 3719 3720 3721 3722

	/*
	 * Don't re-read the value of "jiffies" every time since it may change
	 * behind our back and break the math.
	 */
	tmp_jiffies = jiffies;
	target_jiffies = timestamp_jiffies +
			 msecs_to_jiffies_timeout(to_wait_ms);

	if (time_after(target_jiffies, tmp_jiffies)) {
3723 3724 3725 3726
		remaining_jiffies = target_jiffies - tmp_jiffies;
		while (remaining_jiffies)
			remaining_jiffies =
			    schedule_timeout_uninterruptible(remaining_jiffies);
3727 3728 3729
	}
}

3730
static inline void i915_trace_irq_get(struct intel_engine_cs *engine,
3731 3732
				      struct drm_i915_gem_request *req)
{
3733 3734
	if (engine->trace_irq_req == NULL && engine->irq_get(engine))
		i915_gem_request_assign(&engine->trace_irq_req, req);
3735 3736
}

L
Linus Torvalds 已提交
3737
#endif