i915_drv.h 109.5 KB
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/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#ifndef _I915_DRV_H_
#define _I915_DRV_H_

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#include <uapi/drm/i915_drm.h>
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#include <uapi/drm/drm_fourcc.h>
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#include <drm/drmP.h>
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#include "i915_params.h"
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#include "i915_reg.h"
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#include "intel_bios.h"
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#include "intel_ringbuffer.h"
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#include "intel_lrc.h"
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#include "i915_gem_gtt.h"
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#include "i915_gem_render_state.h"
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#include <linux/io-mapping.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <drm/intel-gtt.h>
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#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
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#include <drm/drm_gem.h>
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#include <linux/backlight.h>
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#include <linux/hashtable.h>
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#include <linux/intel-iommu.h>
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#include <linux/kref.h>
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#include <linux/pm_qos.h>
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#include "intel_guc.h"
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/* General customization:
 */

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
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#define DRIVER_DATE		"20160229"
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#undef WARN_ON
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/* Many gcc seem to no see through this and fall over :( */
#if 0
#define WARN_ON(x) ({ \
	bool __i915_warn_cond = (x); \
	if (__builtin_constant_p(__i915_warn_cond)) \
		BUILD_BUG_ON(__i915_warn_cond); \
	WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
#else
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#define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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#endif

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#undef WARN_ON_ONCE
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#define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
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#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
			     (long) (x), __func__);
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/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 * which may not necessarily be a user visible problem.  This will either
 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 * enable distros and users to tailor their preferred amount of i915 abrt
 * spam.
 */
#define I915_STATE_WARN(condition, format...) ({			\
	int __ret_warn_on = !!(condition);				\
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	if (unlikely(__ret_warn_on))					\
		if (!WARN(i915.verbose_state_checks, format))		\
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			DRM_ERROR(format);				\
	unlikely(__ret_warn_on);					\
})

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#define I915_STATE_WARN_ON(x)						\
	I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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static inline const char *yesno(bool v)
{
	return v ? "yes" : "no";
}

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static inline const char *onoff(bool v)
{
	return v ? "on" : "off";
}

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enum pipe {
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	INVALID_PIPE = -1,
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	PIPE_A = 0,
	PIPE_B,
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	PIPE_C,
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	_PIPE_EDP,
	I915_MAX_PIPES = _PIPE_EDP
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};
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#define pipe_name(p) ((p) + 'A')
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enum transcoder {
	TRANSCODER_A = 0,
	TRANSCODER_B,
	TRANSCODER_C,
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	TRANSCODER_EDP,
	I915_MAX_TRANSCODERS
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};
#define transcoder_name(t) ((t) + 'A')

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/*
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 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 * number of planes per CRTC.  Not all platforms really have this many planes,
 * which means some arrays of size I915_MAX_PLANES may have unused entries
 * between the topmost sprite plane and the cursor plane.
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 */
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enum plane {
	PLANE_A = 0,
	PLANE_B,
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	PLANE_C,
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	PLANE_CURSOR,
	I915_MAX_PLANES,
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};
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#define plane_name(p) ((p) + 'A')
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#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
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enum port {
	PORT_A = 0,
	PORT_B,
	PORT_C,
	PORT_D,
	PORT_E,
	I915_MAX_PORTS
};
#define port_name(p) ((p) + 'A')

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#define I915_NUM_PHYS_VLV 2
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enum dpio_channel {
	DPIO_CH0,
	DPIO_CH1
};

enum dpio_phy {
	DPIO_PHY0,
	DPIO_PHY1
};

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enum intel_display_power_domain {
	POWER_DOMAIN_PIPE_A,
	POWER_DOMAIN_PIPE_B,
	POWER_DOMAIN_PIPE_C,
	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
	POWER_DOMAIN_TRANSCODER_A,
	POWER_DOMAIN_TRANSCODER_B,
	POWER_DOMAIN_TRANSCODER_C,
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	POWER_DOMAIN_TRANSCODER_EDP,
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	POWER_DOMAIN_PORT_DDI_A_LANES,
	POWER_DOMAIN_PORT_DDI_B_LANES,
	POWER_DOMAIN_PORT_DDI_C_LANES,
	POWER_DOMAIN_PORT_DDI_D_LANES,
	POWER_DOMAIN_PORT_DDI_E_LANES,
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	POWER_DOMAIN_PORT_DSI,
	POWER_DOMAIN_PORT_CRT,
	POWER_DOMAIN_PORT_OTHER,
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	POWER_DOMAIN_VGA,
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	POWER_DOMAIN_AUDIO,
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	POWER_DOMAIN_PLLS,
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	POWER_DOMAIN_AUX_A,
	POWER_DOMAIN_AUX_B,
	POWER_DOMAIN_AUX_C,
	POWER_DOMAIN_AUX_D,
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	POWER_DOMAIN_GMBUS,
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	POWER_DOMAIN_MODESET,
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	POWER_DOMAIN_INIT,
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	POWER_DOMAIN_NUM,
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};

#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
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#define POWER_DOMAIN_TRANSCODER(tran) \
	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
	 (tran) + POWER_DOMAIN_TRANSCODER_A)
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enum hpd_pin {
	HPD_NONE = 0,
	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
	HPD_CRT,
	HPD_SDVO_B,
	HPD_SDVO_C,
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	HPD_PORT_A,
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	HPD_PORT_B,
	HPD_PORT_C,
	HPD_PORT_D,
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	HPD_PORT_E,
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	HPD_NUM_PINS
};

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#define for_each_hpd_pin(__pin) \
	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)

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struct i915_hotplug {
	struct work_struct hotplug_work;

	struct {
		unsigned long last_jiffies;
		int count;
		enum {
			HPD_ENABLED = 0,
			HPD_DISABLED = 1,
			HPD_MARK_DISABLED = 2
		} state;
	} stats[HPD_NUM_PINS];
	u32 event_bits;
	struct delayed_work reenable_work;

	struct intel_digital_port *irq_port[I915_MAX_PORTS];
	u32 long_port_mask;
	u32 short_port_mask;
	struct work_struct dig_port_work;

	/*
	 * if we get a HPD irq from DP and a HPD irq from non-DP
	 * the non-DP HPD could block the workqueue on a mode config
	 * mutex getting, that userspace may have taken. However
	 * userspace is waiting on the DP workqueue to run which is
	 * blocked behind the non-DP one.
	 */
	struct workqueue_struct *dp_wq;
};

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#define I915_GEM_GPU_DOMAINS \
	(I915_GEM_DOMAIN_RENDER | \
	 I915_GEM_DOMAIN_SAMPLER | \
	 I915_GEM_DOMAIN_COMMAND | \
	 I915_GEM_DOMAIN_INSTRUCTION | \
	 I915_GEM_DOMAIN_VERTEX)
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#define for_each_pipe(__dev_priv, __p) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
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#define for_each_pipe_masked(__dev_priv, __p, __mask) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
		for_each_if ((__mask) & (1 << (__p)))
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#define for_each_plane(__dev_priv, __pipe, __p)				\
	for ((__p) = 0;							\
	     (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;	\
	     (__p)++)
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#define for_each_sprite(__dev_priv, __p, __s)				\
	for ((__s) = 0;							\
	     (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];	\
	     (__s)++)
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#define for_each_crtc(dev, crtc) \
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)

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#define for_each_intel_plane(dev, intel_plane) \
	list_for_each_entry(intel_plane,			\
			    &dev->mode_config.plane_list,	\
			    base.head)

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#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)	\
	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
			    base.head)					\
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		for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
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#define for_each_intel_crtc(dev, intel_crtc) \
	list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)

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#define for_each_intel_encoder(dev, intel_encoder)		\
	list_for_each_entry(intel_encoder,			\
			    &(dev)->mode_config.encoder_list,	\
			    base.head)

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#define for_each_intel_connector(dev, intel_connector)		\
	list_for_each_entry(intel_connector,			\
			    &dev->mode_config.connector_list,	\
			    base.head)

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#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
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		for_each_if ((intel_encoder)->base.crtc == (__crtc))
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#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
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		for_each_if ((intel_connector)->base.encoder == (__encoder))
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#define for_each_power_domain(domain, mask)				\
	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
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		for_each_if ((1 << (domain)) & (mask))
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struct drm_i915_private;
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struct i915_mm_struct;
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struct i915_mmu_object;
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struct drm_i915_file_private {
	struct drm_i915_private *dev_priv;
	struct drm_file *file;

	struct {
		spinlock_t lock;
		struct list_head request_list;
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/* 20ms is a fairly arbitrary limit (greater than the average frame time)
 * chosen to prevent the CPU getting more than a frame ahead of the GPU
 * (when using lax throttling for the frontbuffer). We also use it to
 * offer free GPU waitboosts for severely congested workloads.
 */
#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
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	} mm;
	struct idr context_idr;

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	struct intel_rps_client {
		struct list_head link;
		unsigned boosts;
	} rps;
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	unsigned int bsd_ring;
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};

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enum intel_dpll_id {
	DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
	/* real shared dpll ids must be >= 0 */
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	DPLL_ID_PCH_PLL_A = 0,
	DPLL_ID_PCH_PLL_B = 1,
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	/* hsw/bdw */
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	DPLL_ID_WRPLL1 = 0,
	DPLL_ID_WRPLL2 = 1,
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	DPLL_ID_SPLL = 2,

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	/* skl */
	DPLL_ID_SKL_DPLL1 = 0,
	DPLL_ID_SKL_DPLL2 = 1,
	DPLL_ID_SKL_DPLL3 = 2,
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};
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#define I915_NUM_PLLS 3
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struct intel_dpll_hw_state {
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	/* i9xx, pch plls */
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	uint32_t dpll;
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	uint32_t dpll_md;
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	uint32_t fp0;
	uint32_t fp1;
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	/* hsw, bdw */
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	uint32_t wrpll;
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	uint32_t spll;
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	/* skl */
	/*
	 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
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	 * lower part of ctrl1 and they get shifted into position when writing
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	 * the register.  This allows us to easily compare the state to share
	 * the DPLL.
	 */
	uint32_t ctrl1;
	/* HDMI only, 0 when used for DP */
	uint32_t cfgcr1, cfgcr2;
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	/* bxt */
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	uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
		 pcsdw12;
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};

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struct intel_shared_dpll_config {
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	unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
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	struct intel_dpll_hw_state hw_state;
};

struct intel_shared_dpll {
	struct intel_shared_dpll_config config;
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	int active; /* count of number of active CRTCs (i.e. DPMS on) */
	bool on; /* is the PLL actually active? Disabled during modeset */
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	const char *name;
	/* should match the index in the dev_priv->shared_dplls array */
	enum intel_dpll_id id;
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	/* The mode_set hook is optional and should be used together with the
	 * intel_prepare_shared_dpll function. */
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	void (*mode_set)(struct drm_i915_private *dev_priv,
			 struct intel_shared_dpll *pll);
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	void (*enable)(struct drm_i915_private *dev_priv,
		       struct intel_shared_dpll *pll);
	void (*disable)(struct drm_i915_private *dev_priv,
			struct intel_shared_dpll *pll);
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	bool (*get_hw_state)(struct drm_i915_private *dev_priv,
			     struct intel_shared_dpll *pll,
			     struct intel_dpll_hw_state *hw_state);
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};

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#define SKL_DPLL0 0
#define SKL_DPLL1 1
#define SKL_DPLL2 2
#define SKL_DPLL3 3

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/* Used by dp and fdi links */
struct intel_link_m_n {
	uint32_t	tu;
	uint32_t	gmch_m;
	uint32_t	gmch_n;
	uint32_t	link_m;
	uint32_t	link_n;
};

void intel_link_compute_m_n(int bpp, int nlanes,
			    int pixel_clock, int link_clock,
			    struct intel_link_m_n *m_n);

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/* Interface history:
 *
 * 1.1: Original.
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 * 1.2: Add Power Management
 * 1.3: Add vblank support
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 * 1.4: Fix cmdbuffer path, add heap destroy
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 * 1.5: Add vblank pipe configuration
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 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
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 */
#define DRIVER_MAJOR		1
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#define DRIVER_MINOR		6
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#define DRIVER_PATCHLEVEL	0

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#define WATCH_LISTS	0
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struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
struct opregion_asle;

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struct intel_opregion {
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	struct opregion_header *header;
	struct opregion_acpi *acpi;
	struct opregion_swsci *swsci;
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	u32 swsci_gbda_sub_functions;
	u32 swsci_sbcb_sub_functions;
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	struct opregion_asle *asle;
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	void *rvda;
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	const void *vbt;
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	u32 vbt_size;
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	u32 *lid_state;
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	struct work_struct asle_work;
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};
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#define OPREGION_SIZE            (8*1024)
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struct intel_overlay;
struct intel_overlay_error_state;

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#define I915_FENCE_REG_NONE -1
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#define I915_MAX_NUM_FENCES 32
/* 32 fences + sign bit for FENCE_REG_NONE */
#define I915_MAX_NUM_FENCE_BITS 6
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struct drm_i915_fence_reg {
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	struct list_head lru_list;
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	struct drm_i915_gem_object *obj;
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	int pin_count;
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};
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struct sdvo_device_mapping {
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	u8 initialized;
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	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
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	u8 i2c_pin;
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	u8 ddc_pin;
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};

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struct intel_display_error_state;

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struct drm_i915_error_state {
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	struct kref ref;
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	struct timeval time;

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	char error_msg[128];
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	int iommu;
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	u32 reset_count;
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	u32 suspend_count;
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	/* Generic register state */
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	u32 eir;
	u32 pgtbl_er;
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	u32 ier;
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	u32 gtier[4];
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	u32 ccid;
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	u32 derrmr;
	u32 forcewake;
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	u32 error; /* gen6+ */
	u32 err_int; /* gen7 */
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	u32 fault_data0; /* gen8, gen9 */
	u32 fault_data1; /* gen8, gen9 */
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	u32 done_reg;
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	u32 gac_eco;
	u32 gam_ecochk;
	u32 gab_ctl;
	u32 gfx_mode;
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	u32 extra_instdone[I915_NUM_INSTDONE_REG];
	u64 fence[I915_MAX_NUM_FENCES];
	struct intel_overlay_error_state *overlay;
	struct intel_display_error_state *display;
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	struct drm_i915_error_object *semaphore_obj;
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	struct drm_i915_error_ring {
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		bool valid;
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		/* Software tracked state */
		bool waiting;
		int hangcheck_score;
		enum intel_ring_hangcheck_action hangcheck_action;
		int num_requests;

		/* our own tracking of ring head and tail */
		u32 cpu_ring_head;
		u32 cpu_ring_tail;

		u32 semaphore_seqno[I915_NUM_RINGS - 1];

		/* Register state */
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		u32 start;
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		u32 tail;
		u32 head;
		u32 ctl;
		u32 hws;
		u32 ipeir;
		u32 ipehr;
		u32 instdone;
		u32 bbstate;
		u32 instpm;
		u32 instps;
		u32 seqno;
		u64 bbaddr;
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		u64 acthd;
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		u32 fault_reg;
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		u64 faddr;
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		u32 rc_psmi; /* sleep state */
		u32 semaphore_mboxes[I915_NUM_RINGS - 1];

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		struct drm_i915_error_object {
			int page_count;
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			u64 gtt_offset;
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			u32 *pages[0];
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		} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
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		struct drm_i915_error_object *wa_ctx;

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		struct drm_i915_error_request {
			long jiffies;
			u32 seqno;
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			u32 tail;
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		} *requests;
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		struct {
			u32 gfx_mode;
			union {
				u64 pdp[4];
				u32 pp_dir_base;
			};
		} vm_info;
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		pid_t pid;
		char comm[TASK_COMM_LEN];
582
	} ring[I915_NUM_RINGS];
583

584
	struct drm_i915_error_buffer {
585
		u32 size;
586
		u32 name;
587
		u32 rseqno[I915_NUM_RINGS], wseqno;
588
		u64 gtt_offset;
589 590
		u32 read_domains;
		u32 write_domain;
591
		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
592 593 594 595
		s32 pinned:2;
		u32 tiling:2;
		u32 dirty:1;
		u32 purgeable:1;
596
		u32 userptr:1;
597
		s32 ring:4;
598
		u32 cache_level:3;
599
	} **active_bo, **pinned_bo;
600

601
	u32 *active_bo_count, *pinned_bo_count;
602
	u32 vm_count;
603 604
};

605
struct intel_connector;
606
struct intel_encoder;
607
struct intel_crtc_state;
608
struct intel_initial_plane_config;
609
struct intel_crtc;
610 611
struct intel_limit;
struct dpll;
612

613 614 615
struct drm_i915_display_funcs {
	int (*get_display_clock_speed)(struct drm_device *dev);
	int (*get_fifo_size)(struct drm_device *dev, int plane);
616 617 618 619 620 621 622 623 624 625 626 627 628 629
	/**
	 * find_dpll() - Find the best values for the PLL
	 * @limit: limits for the PLL
	 * @crtc: current CRTC
	 * @target: target frequency in kHz
	 * @refclk: reference clock frequency in kHz
	 * @match_clock: if provided, @best_clock P divider must
	 *               match the P divider from @match_clock
	 *               used for LVDS downclocking
	 * @best_clock: best PLL values found
	 *
	 * Returns true on success, false on failure.
	 */
	bool (*find_dpll)(const struct intel_limit *limit,
630
			  struct intel_crtc_state *crtc_state,
631 632 633
			  int target, int refclk,
			  struct dpll *match_clock,
			  struct dpll *best_clock);
634 635
	int (*compute_pipe_wm)(struct intel_crtc *crtc,
			       struct drm_atomic_state *state);
636 637 638 639 640
	int (*compute_intermediate_wm)(struct drm_device *dev,
				       struct intel_crtc *intel_crtc,
				       struct intel_crtc_state *newstate);
	void (*initial_watermarks)(struct intel_crtc_state *cstate);
	void (*optimize_watermarks)(struct intel_crtc_state *cstate);
641
	void (*update_wm)(struct drm_crtc *crtc);
642 643
	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
	void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
644 645 646
	/* Returns the active state of the crtc, and if the crtc is active,
	 * fills out the pipe-config with the hw state. */
	bool (*get_pipe_config)(struct intel_crtc *,
647
				struct intel_crtc_state *);
648 649
	void (*get_initial_plane_config)(struct intel_crtc *,
					 struct intel_initial_plane_config *);
650 651
	int (*crtc_compute_clock)(struct intel_crtc *crtc,
				  struct intel_crtc_state *crtc_state);
652 653
	void (*crtc_enable)(struct drm_crtc *crtc);
	void (*crtc_disable)(struct drm_crtc *crtc);
654 655
	void (*audio_codec_enable)(struct drm_connector *connector,
				   struct intel_encoder *encoder,
656
				   const struct drm_display_mode *adjusted_mode);
657
	void (*audio_codec_disable)(struct intel_encoder *encoder);
658
	void (*fdi_link_train)(struct drm_crtc *crtc);
659
	void (*init_clock_gating)(struct drm_device *dev);
660 661
	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
			  struct drm_framebuffer *fb,
662
			  struct drm_i915_gem_object *obj,
663
			  struct drm_i915_gem_request *req,
664
			  uint32_t flags);
665
	void (*hpd_irq_setup)(struct drm_device *dev);
666 667 668 669 670 671 672
	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
};

673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689
enum forcewake_domain_id {
	FW_DOMAIN_ID_RENDER = 0,
	FW_DOMAIN_ID_BLITTER,
	FW_DOMAIN_ID_MEDIA,

	FW_DOMAIN_ID_COUNT
};

enum forcewake_domains {
	FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
	FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
	FORCEWAKE_MEDIA	= (1 << FW_DOMAIN_ID_MEDIA),
	FORCEWAKE_ALL = (FORCEWAKE_RENDER |
			 FORCEWAKE_BLITTER |
			 FORCEWAKE_MEDIA)
};

690
struct intel_uncore_funcs {
691
	void (*force_wake_get)(struct drm_i915_private *dev_priv,
692
							enum forcewake_domains domains);
693
	void (*force_wake_put)(struct drm_i915_private *dev_priv,
694
							enum forcewake_domains domains);
695

696 697 698 699
	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
700

701
	void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
702
				uint8_t val, bool trace);
703
	void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
704
				uint16_t val, bool trace);
705
	void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
706
				uint32_t val, bool trace);
707
	void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
708
				uint64_t val, bool trace);
709 710
};

711 712 713 714 715 716
struct intel_uncore {
	spinlock_t lock; /** lock is also taken in irq contexts. */

	struct intel_uncore_funcs funcs;

	unsigned fifo_count;
717
	enum forcewake_domains fw_domains;
718 719 720

	struct intel_uncore_forcewake_domain {
		struct drm_i915_private *i915;
721
		enum forcewake_domain_id id;
722 723
		unsigned wake_count;
		struct timer_list timer;
724
		i915_reg_t reg_set;
725 726
		u32 val_set;
		u32 val_clear;
727 728
		i915_reg_t reg_ack;
		i915_reg_t reg_post;
729
		u32 val_reset;
730
	} fw_domain[FW_DOMAIN_ID_COUNT];
731 732

	int unclaimed_mmio_check;
733 734 735 736 737 738 739
};

/* Iterate over initialised fw domains */
#define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
	for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
	     (i__) < FW_DOMAIN_ID_COUNT; \
	     (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
740
		for_each_if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
741 742 743

#define for_each_fw_domain(domain__, dev_priv__, i__) \
	for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
744

745 746 747 748
#define CSR_VERSION(major, minor)	((major) << 16 | (minor))
#define CSR_VERSION_MAJOR(version)	((version) >> 16)
#define CSR_VERSION_MINOR(version)	((version) & 0xffff)

749
struct intel_csr {
750
	struct work_struct work;
751
	const char *fw_path;
752
	uint32_t *dmc_payload;
753
	uint32_t dmc_fw_size;
754
	uint32_t version;
755
	uint32_t mmio_count;
756
	i915_reg_t mmioaddr[8];
757
	uint32_t mmiodata[8];
758
	uint32_t dc_state;
759
	uint32_t allowed_dc_mask;
760 761
};

762 763 764 765 766 767 768 769 770 771 772 773 774
#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
	func(is_mobile) sep \
	func(is_i85x) sep \
	func(is_i915g) sep \
	func(is_i945gm) sep \
	func(is_g33) sep \
	func(need_gfx_hws) sep \
	func(is_g4x) sep \
	func(is_pineview) sep \
	func(is_broadwater) sep \
	func(is_crestline) sep \
	func(is_ivybridge) sep \
	func(is_valleyview) sep \
775
	func(is_cherryview) sep \
776
	func(is_haswell) sep \
777
	func(is_skylake) sep \
778
	func(is_broxton) sep \
779
	func(is_kabylake) sep \
780
	func(is_preliminary) sep \
781 782 783 784 785 786 787
	func(has_fbc) sep \
	func(has_pipe_cxsr) sep \
	func(has_hotplug) sep \
	func(cursor_needs_physical) sep \
	func(has_overlay) sep \
	func(overlay_needs_physical) sep \
	func(supports_tv) sep \
788
	func(has_llc) sep \
789 790
	func(has_ddi) sep \
	func(has_fpga_dbg)
D
Daniel Vetter 已提交
791

792 793
#define DEFINE_FLAG(name) u8 name:1
#define SEP_SEMICOLON ;
D
Daniel Vetter 已提交
794

795
struct intel_device_info {
796
	u32 display_mmio_offset;
797
	u16 device_id;
798
	u8 num_pipes:3;
799
	u8 num_sprites[I915_MAX_PIPES];
800
	u8 gen;
801
	u8 ring_mask; /* Rings supported by the HW */
802
	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
803 804 805 806
	/* Register offsets for the various display pipes and transcoders */
	int pipe_offsets[I915_MAX_TRANSCODERS];
	int trans_offsets[I915_MAX_TRANSCODERS];
	int palette_offsets[I915_MAX_PIPES];
807
	int cursor_offsets[I915_MAX_PIPES];
808 809 810 811 812 813 814

	/* Slice/subslice/EU info */
	u8 slice_total;
	u8 subslice_total;
	u8 subslice_per_slice;
	u8 eu_total;
	u8 eu_per_subslice;
815 816
	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
	u8 subslice_7eu[3];
817 818 819
	u8 has_slice_pg:1;
	u8 has_subslice_pg:1;
	u8 has_eu_pg:1;
820 821
};

822 823 824
#undef DEFINE_FLAG
#undef SEP_SEMICOLON

825 826
enum i915_cache_level {
	I915_CACHE_NONE = 0,
827 828 829 830 831
	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
			      caches, eg sampler/render caches, and the
			      large Last-Level-Cache. LLC is coherent with
			      the CPU, but L3 is only visible to the GPU. */
832
	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
833 834
};

835 836 837 838 839 840
struct i915_ctx_hang_stats {
	/* This context had batch pending when hang was declared */
	unsigned batch_pending;

	/* This context had batch active when hang was declared */
	unsigned batch_active;
841 842 843 844

	/* Time when this context was last blamed for a GPU reset */
	unsigned long guilty_ts;

845 846 847 848 849
	/* If the contexts causes a second GPU hang within this time,
	 * it is permanently banned from submitting any more work.
	 */
	unsigned long ban_period_seconds;

850 851
	/* This context is banned to submit more work */
	bool banned;
852
};
853 854

/* This must match up with the value previously used for execbuf2.rsvd1. */
855
#define DEFAULT_CONTEXT_HANDLE 0
856 857

#define CONTEXT_NO_ZEROMAP (1<<0)
858 859 860 861 862
/**
 * struct intel_context - as the name implies, represents a context.
 * @ref: reference count.
 * @user_handle: userspace tracking identity for this context.
 * @remap_slice: l3 row remapping information.
863 864
 * @flags: context specific flags:
 *         CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
865 866 867 868
 * @file_priv: filp associated with this context (NULL for global default
 *	       context).
 * @hang_stats: information about the role of this context in possible GPU
 *		hangs.
869
 * @ppgtt: virtual memory space used by this context.
870 871 872 873 874 875 876
 * @legacy_hw_ctx: render context backing object and whether it is correctly
 *                initialized (legacy ring submission mechanism only).
 * @link: link in the global list of contexts.
 *
 * Contexts are memory images used by the hardware to store copies of their
 * internal state.
 */
877
struct intel_context {
878
	struct kref ref;
879
	int user_handle;
880
	uint8_t remap_slice;
881
	struct drm_i915_private *i915;
882
	int flags;
883
	struct drm_i915_file_private *file_priv;
884
	struct i915_ctx_hang_stats hang_stats;
885
	struct i915_hw_ppgtt *ppgtt;
886

887
	/* Legacy ring buffer submission */
888 889 890 891 892
	struct {
		struct drm_i915_gem_object *rcs_state;
		bool initialized;
	} legacy_hw_ctx;

893 894 895
	/* Execlists */
	struct {
		struct drm_i915_gem_object *state;
896
		struct intel_ringbuffer *ringbuf;
897
		int pin_count;
898 899
		struct i915_vma *lrc_vma;
		u64 lrc_desc;
900
		uint32_t *lrc_reg_state;
901 902
	} engine[I915_NUM_RINGS];

903
	struct list_head link;
904 905
};

906 907 908 909 910
enum fb_op_origin {
	ORIGIN_GTT,
	ORIGIN_CPU,
	ORIGIN_CS,
	ORIGIN_FLIP,
911
	ORIGIN_DIRTYFB,
912 913
};

914
struct intel_fbc {
P
Paulo Zanoni 已提交
915 916 917
	/* This is always the inner lock when overlapping with struct_mutex and
	 * it's the outer lock when overlapping with stolen_lock. */
	struct mutex lock;
B
Ben Widawsky 已提交
918
	unsigned threshold;
919 920
	unsigned int possible_framebuffer_bits;
	unsigned int busy_bits;
921
	unsigned int visible_pipes_mask;
922
	struct intel_crtc *crtc;
923

924
	struct drm_mm_node compressed_fb;
925 926
	struct drm_mm_node *compressed_llb;

927 928
	bool false_color;

929
	bool enabled;
930
	bool active;
931

932 933 934 935 936 937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953
	struct intel_fbc_state_cache {
		struct {
			unsigned int mode_flags;
			uint32_t hsw_bdw_pixel_rate;
		} crtc;

		struct {
			unsigned int rotation;
			int src_w;
			int src_h;
			bool visible;
		} plane;

		struct {
			u64 ilk_ggtt_offset;
			uint32_t pixel_format;
			unsigned int stride;
			int fence_reg;
			unsigned int tiling_mode;
		} fb;
	} state_cache;

954 955 956 957 958 959 960 961 962 963 964 965 966 967 968 969 970
	struct intel_fbc_reg_params {
		struct {
			enum pipe pipe;
			enum plane plane;
			unsigned int fence_y_offset;
		} crtc;

		struct {
			u64 ggtt_offset;
			uint32_t pixel_format;
			unsigned int stride;
			int fence_reg;
		} fb;

		int cfb_size;
	} params;

971
	struct intel_fbc_work {
972
		bool scheduled;
973
		u32 scheduled_vblank;
974 975
		struct work_struct work;
	} work;
976

977
	const char *no_fbc_reason;
978 979
};

980 981 982 983 984 985 986 987 988 989 990 991 992 993 994
/**
 * HIGH_RR is the highest eDP panel refresh rate read from EDID
 * LOW_RR is the lowest eDP panel refresh rate found from EDID
 * parsing for same resolution.
 */
enum drrs_refresh_rate_type {
	DRRS_HIGH_RR,
	DRRS_LOW_RR,
	DRRS_MAX_RR, /* RR count */
};

enum drrs_support_type {
	DRRS_NOT_SUPPORTED = 0,
	STATIC_DRRS_SUPPORT = 1,
	SEAMLESS_DRRS_SUPPORT = 2
995 996
};

997
struct intel_dp;
998 999 1000 1001 1002 1003 1004 1005 1006
struct i915_drrs {
	struct mutex mutex;
	struct delayed_work work;
	struct intel_dp *dp;
	unsigned busy_frontbuffer_bits;
	enum drrs_refresh_rate_type refresh_rate_type;
	enum drrs_support_type type;
};

R
Rodrigo Vivi 已提交
1007
struct i915_psr {
1008
	struct mutex lock;
R
Rodrigo Vivi 已提交
1009 1010
	bool sink_support;
	bool source_ok;
1011
	struct intel_dp *enabled;
1012 1013
	bool active;
	struct delayed_work work;
1014
	unsigned busy_frontbuffer_bits;
1015 1016
	bool psr2_support;
	bool aux_frame_sync;
1017
	bool link_standby;
1018
};
1019

1020
enum intel_pch {
1021
	PCH_NONE = 0,	/* No PCH present */
1022 1023
	PCH_IBX,	/* Ibexpeak PCH */
	PCH_CPT,	/* Cougarpoint PCH */
1024
	PCH_LPT,	/* Lynxpoint PCH */
1025
	PCH_SPT,        /* Sunrisepoint PCH */
B
Ben Widawsky 已提交
1026
	PCH_NOP,
1027 1028
};

1029 1030 1031 1032 1033
enum intel_sbi_destination {
	SBI_ICLK,
	SBI_MPHY,
};

1034
#define QUIRK_PIPEA_FORCE (1<<0)
1035
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
1036
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
1037
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
1038
#define QUIRK_PIPEB_FORCE (1<<4)
1039
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1040

1041
struct intel_fbdev;
1042
struct intel_fbc_work;
1043

1044 1045
struct intel_gmbus {
	struct i2c_adapter adapter;
1046
	u32 force_bit;
1047
	u32 reg0;
1048
	i915_reg_t gpio_reg;
1049
	struct i2c_algo_bit_data bit_algo;
1050 1051 1052
	struct drm_i915_private *dev_priv;
};

1053
struct i915_suspend_saved_registers {
1054
	u32 saveDSPARB;
J
Jesse Barnes 已提交
1055
	u32 saveLVDS;
1056 1057
	u32 savePP_ON_DELAYS;
	u32 savePP_OFF_DELAYS;
J
Jesse Barnes 已提交
1058 1059 1060
	u32 savePP_ON;
	u32 savePP_OFF;
	u32 savePP_CONTROL;
1061
	u32 savePP_DIVISOR;
J
Jesse Barnes 已提交
1062
	u32 saveFBC_CONTROL;
1063 1064
	u32 saveCACHE_MODE_0;
	u32 saveMI_ARB_STATE;
J
Jesse Barnes 已提交
1065 1066
	u32 saveSWF0[16];
	u32 saveSWF1[16];
1067
	u32 saveSWF3[3];
1068
	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1069
	u32 savePCH_PORT_HOTPLUG;
1070
	u16 saveGCDGMBUS;
1071
};
1072

1073 1074 1075 1076 1077 1078 1079 1080 1081 1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130
struct vlv_s0ix_state {
	/* GAM */
	u32 wr_watermark;
	u32 gfx_prio_ctrl;
	u32 arb_mode;
	u32 gfx_pend_tlb0;
	u32 gfx_pend_tlb1;
	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
	u32 media_max_req_count;
	u32 gfx_max_req_count;
	u32 render_hwsp;
	u32 ecochk;
	u32 bsd_hwsp;
	u32 blt_hwsp;
	u32 tlb_rd_addr;

	/* MBC */
	u32 g3dctl;
	u32 gsckgctl;
	u32 mbctl;

	/* GCP */
	u32 ucgctl1;
	u32 ucgctl3;
	u32 rcgctl1;
	u32 rcgctl2;
	u32 rstctl;
	u32 misccpctl;

	/* GPM */
	u32 gfxpause;
	u32 rpdeuhwtc;
	u32 rpdeuc;
	u32 ecobus;
	u32 pwrdwnupctl;
	u32 rp_down_timeout;
	u32 rp_deucsw;
	u32 rcubmabdtmr;
	u32 rcedata;
	u32 spare2gh;

	/* Display 1 CZ domain */
	u32 gt_imr;
	u32 gt_ier;
	u32 pm_imr;
	u32 pm_ier;
	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

	/* GT SA CZ domain */
	u32 tilectl;
	u32 gt_fifoctl;
	u32 gtlc_wake_ctrl;
	u32 gtlc_survive;
	u32 pmwgicz;

	/* Display 2 CZ domain */
	u32 gu_ctl0;
	u32 gu_ctl1;
1131
	u32 pcbr;
1132 1133 1134
	u32 clock_gate_dis2;
};

1135 1136 1137 1138
struct intel_rps_ei {
	u32 cz_clock;
	u32 render_c0;
	u32 media_c0;
1139 1140
};

1141
struct intel_gen6_power_mgmt {
I
Imre Deak 已提交
1142 1143 1144 1145
	/*
	 * work, interrupts_enabled and pm_iir are protected by
	 * dev_priv->irq_lock
	 */
1146
	struct work_struct work;
I
Imre Deak 已提交
1147
	bool interrupts_enabled;
1148
	u32 pm_iir;
1149

1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163 1164
	/* Frequencies are stored in potentially platform dependent multiples.
	 * In other words, *_freq needs to be multiplied by X to be interesting.
	 * Soft limits are those which are used for the dynamic reclocking done
	 * by the driver (raise frequencies under heavy loads, and lower for
	 * lighter loads). Hard limits are those imposed by the hardware.
	 *
	 * A distinction is made for overclocking, which is never enabled by
	 * default, and is considered to be above the hard limit if it's
	 * possible at all.
	 */
	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
	u8 min_freq;		/* AKA RPn. Minimum frequency */
1165
	u8 idle_freq;		/* Frequency to request when we are idle */
1166 1167 1168
	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
	u8 rp1_freq;		/* "less than" RP0 power/freqency */
	u8 rp0_freq;		/* Non-overclocked max frequency. */
1169

1170 1171 1172
	u8 up_threshold; /* Current %busy required to uplock */
	u8 down_threshold; /* Current %busy required to downclock */

1173 1174 1175
	int last_adj;
	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;

1176 1177 1178 1179
	spinlock_t client_lock;
	struct list_head clients;
	bool client_boost;

1180
	bool enabled;
1181
	struct delayed_work delayed_resume_work;
1182
	unsigned boosts;
1183

1184
	struct intel_rps_client semaphores, mmioflips;
1185

1186 1187 1188
	/* manual wa residency calculations */
	struct intel_rps_ei up_ei, down_ei;

1189 1190
	/*
	 * Protects RPS/RC6 register access and PCU communication.
1191 1192 1193
	 * Must be taken after struct_mutex if nested. Note that
	 * this lock may be held for long periods of time when
	 * talking to hw - so only take it when talking to hw!
1194 1195
	 */
	struct mutex hw_lock;
1196 1197
};

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Daniel Vetter 已提交
1198 1199 1200
/* defined intel_pm.c */
extern spinlock_t mchdev_lock;

1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211
struct intel_ilk_power_mgmt {
	u8 cur_delay;
	u8 min_delay;
	u8 max_delay;
	u8 fmax;
	u8 fstart;

	u64 last_count1;
	unsigned long last_time1;
	unsigned long chipset_power;
	u64 last_count2;
1212
	u64 last_time2;
1213 1214 1215 1216 1217 1218 1219
	unsigned long gfx_power;
	u8 corr;

	int c_m;
	int r_t;
};

1220 1221 1222 1223 1224 1225 1226 1227 1228 1229 1230 1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249
struct drm_i915_private;
struct i915_power_well;

struct i915_power_well_ops {
	/*
	 * Synchronize the well's hw state to match the current sw state, for
	 * example enable/disable it based on the current refcount. Called
	 * during driver init and resume time, possibly after first calling
	 * the enable/disable handlers.
	 */
	void (*sync_hw)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/*
	 * Enable the well and resources that depend on it (for example
	 * interrupts located on the well). Called after the 0->1 refcount
	 * transition.
	 */
	void (*enable)(struct drm_i915_private *dev_priv,
		       struct i915_power_well *power_well);
	/*
	 * Disable the well and resources that depend on it. Called after
	 * the 1->0 refcount transition.
	 */
	void (*disable)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/* Returns the hw enabled state. */
	bool (*is_enabled)(struct drm_i915_private *dev_priv,
			   struct i915_power_well *power_well);
};

1250 1251
/* Power well structure for haswell */
struct i915_power_well {
1252
	const char *name;
1253
	bool always_on;
1254 1255
	/* power well enable/disable usage count */
	int count;
1256 1257
	/* cached hw enabled state */
	bool hw_enabled;
1258
	unsigned long domains;
1259
	unsigned long data;
1260
	const struct i915_power_well_ops *ops;
1261 1262
};

1263
struct i915_power_domains {
1264 1265 1266 1267 1268
	/*
	 * Power wells needed for initialization at driver init and suspend
	 * time are on. They are kept on until after the first modeset.
	 */
	bool init_power_on;
1269
	bool initializing;
1270
	int power_well_count;
1271

1272
	struct mutex lock;
1273
	int domain_use_count[POWER_DOMAIN_NUM];
1274
	struct i915_power_well *power_wells;
1275 1276
};

1277
#define MAX_L3_SLICES 2
1278
struct intel_l3_parity {
1279
	u32 *remap_info[MAX_L3_SLICES];
1280
	struct work_struct error_work;
1281
	int which_slice;
1282 1283
};

1284 1285 1286
struct i915_gem_mm {
	/** Memory allocator for GTT stolen memory */
	struct drm_mm stolen;
1287 1288 1289 1290
	/** Protects the usage of the GTT stolen memory allocator. This is
	 * always the inner lock when overlapping with struct_mutex. */
	struct mutex stolen_lock;

1291 1292 1293 1294 1295 1296 1297 1298 1299 1300 1301 1302 1303 1304 1305 1306
	/** List of all objects in gtt_space. Used to restore gtt
	 * mappings on resume */
	struct list_head bound_list;
	/**
	 * List of objects which are not bound to the GTT (thus
	 * are idle and not used by the GPU) but still have
	 * (presumably uncached) pages still attached.
	 */
	struct list_head unbound_list;

	/** Usable portion of the GTT for GEM */
	unsigned long stolen_base; /* limited to low memory (32-bit) */

	/** PPGTT used for aliasing the PPGTT with the GTT */
	struct i915_hw_ppgtt *aliasing_ppgtt;

1307
	struct notifier_block oom_notifier;
1308
	struct shrinker shrinker;
1309 1310 1311 1312 1313 1314 1315 1316 1317 1318 1319 1320 1321 1322
	bool shrinker_no_lock_stealing;

	/** LRU list of objects with fence regs on them. */
	struct list_head fence_list;

	/**
	 * We leave the user IRQ off as much as possible,
	 * but this means that requests will finish and never
	 * be retired once the system goes idle. Set a timer to
	 * fire periodically while the ring is running. When it
	 * fires, go retire requests.
	 */
	struct delayed_work retire_work;

1323 1324 1325 1326 1327 1328 1329 1330 1331
	/**
	 * When we detect an idle GPU, we want to turn on
	 * powersaving features. So once we see that there
	 * are no more requests outstanding and no more
	 * arrive within a small period of time, we fire
	 * off the idle_work.
	 */
	struct delayed_work idle_work;

1332 1333 1334 1335 1336 1337
	/**
	 * Are we in a non-interruptible section of code like
	 * modesetting?
	 */
	bool interruptible;

1338 1339 1340 1341 1342 1343 1344 1345
	/**
	 * Is the GPU currently considered idle, or busy executing userspace
	 * requests?  Whilst idle, we attempt to power down the hardware and
	 * display clocks. In order to reduce the effect on performance, there
	 * is a slight delay before we do so.
	 */
	bool busy;

1346
	/* the indicator for dispatch video commands on two BSD rings */
1347
	unsigned int bsd_ring_dispatch_index;
1348

1349 1350 1351 1352 1353 1354
	/** Bit 6 swizzling required for X tiling */
	uint32_t bit_6_swizzle_x;
	/** Bit 6 swizzling required for Y tiling */
	uint32_t bit_6_swizzle_y;

	/* accounting, useful for userland debugging */
1355
	spinlock_t object_stat_lock;
1356 1357 1358 1359
	size_t object_memory;
	u32 object_count;
};

1360
struct drm_i915_error_state_buf {
1361
	struct drm_i915_private *i915;
1362 1363 1364 1365 1366 1367 1368 1369
	unsigned bytes;
	unsigned size;
	int err;
	u8 *buf;
	loff_t start;
	loff_t pos;
};

1370 1371 1372 1373 1374
struct i915_error_state_file_priv {
	struct drm_device *dev;
	struct drm_i915_error_state *error;
};

1375 1376 1377 1378
struct i915_gpu_error {
	/* For hangcheck timer */
#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1379 1380 1381
	/* Hang gpu twice in this window and your context gets banned */
#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)

1382 1383
	struct workqueue_struct *hangcheck_wq;
	struct delayed_work hangcheck_work;
1384 1385 1386 1387 1388

	/* For reset and error_state handling. */
	spinlock_t lock;
	/* Protected by the above dev->gpu_error.lock. */
	struct drm_i915_error_state *first_error;
1389 1390 1391

	unsigned long missed_irq_rings;

1392
	/**
M
Mika Kuoppala 已提交
1393
	 * State variable controlling the reset flow and count
1394
	 *
M
Mika Kuoppala 已提交
1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407
	 * This is a counter which gets incremented when reset is triggered,
	 * and again when reset has been handled. So odd values (lowest bit set)
	 * means that reset is in progress and even values that
	 * (reset_counter >> 1):th reset was successfully completed.
	 *
	 * If reset is not completed succesfully, the I915_WEDGE bit is
	 * set meaning that hardware is terminally sour and there is no
	 * recovery. All waiters on the reset_queue will be woken when
	 * that happens.
	 *
	 * This counter is used by the wait_seqno code to notice that reset
	 * event happened and it needs to restart the entire ioctl (since most
	 * likely the seqno it waited for won't ever signal anytime soon).
1408 1409 1410 1411
	 *
	 * This is important for lock-free wait paths, where no contended lock
	 * naturally enforces the correct ordering between the bail-out of the
	 * waiter and the gpu reset work code.
1412 1413 1414 1415
	 */
	atomic_t reset_counter;

#define I915_RESET_IN_PROGRESS_FLAG	1
M
Mika Kuoppala 已提交
1416
#define I915_WEDGED			(1 << 31)
1417 1418 1419 1420 1421 1422

	/**
	 * Waitqueue to signal when the reset has completed. Used by clients
	 * that wait for dev_priv->mm.wedged to settle.
	 */
	wait_queue_head_t reset_queue;
1423

1424 1425 1426 1427 1428 1429
	/* Userspace knobs for gpu hang simulation;
	 * combines both a ring mask, and extra flags
	 */
	u32 stop_rings;
#define I915_STOP_RING_ALLOW_BAN       (1 << 31)
#define I915_STOP_RING_ALLOW_WARN      (1 << 30)
1430 1431 1432

	/* For missed irq/seqno simulation. */
	unsigned int test_irq_rings;
1433 1434 1435

	/* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset   */
	bool reload_in_reset;
1436 1437
};

1438 1439 1440 1441 1442 1443
enum modeset_restore {
	MODESET_ON_LID_OPEN,
	MODESET_DONE,
	MODESET_SUSPENDED,
};

1444 1445 1446 1447 1448
#define DP_AUX_A 0x40
#define DP_AUX_B 0x10
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30

X
Xiong Zhang 已提交
1449 1450 1451 1452
#define DDC_PIN_B  0x05
#define DDC_PIN_C  0x04
#define DDC_PIN_D  0x06

1453
struct ddi_vbt_port_info {
1454 1455 1456 1457 1458 1459
	/*
	 * This is an index in the HDMI/DVI DDI buffer translation table.
	 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
	 * populate this field.
	 */
#define HDMI_LEVEL_SHIFT_UNKNOWN	0xff
1460
	uint8_t hdmi_level_shift;
1461 1462 1463 1464

	uint8_t supports_dvi:1;
	uint8_t supports_hdmi:1;
	uint8_t supports_dp:1;
1465 1466

	uint8_t alternate_aux_channel;
X
Xiong Zhang 已提交
1467
	uint8_t alternate_ddc_pin;
1468 1469 1470

	uint8_t dp_boost_level;
	uint8_t hdmi_boost_level;
1471 1472
};

R
Rodrigo Vivi 已提交
1473 1474 1475 1476 1477
enum psr_lines_to_wait {
	PSR_0_LINES_TO_WAIT = 0,
	PSR_1_LINE_TO_WAIT,
	PSR_4_LINES_TO_WAIT,
	PSR_8_LINES_TO_WAIT
1478 1479
};

1480 1481 1482 1483 1484 1485 1486 1487 1488 1489 1490 1491
struct intel_vbt_data {
	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits */
	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int lvds_vbt:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
	unsigned int display_clock_mode:1;
	unsigned int fdi_rx_polarity_inverted:1;
1492
	unsigned int has_mipi:1;
1493 1494 1495
	int lvds_ssc_freq;
	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

1496 1497
	enum drrs_support_type drrs_type;

1498 1499 1500 1501 1502 1503 1504 1505 1506 1507
	/* eDP */
	int edp_rate;
	int edp_lanes;
	int edp_preemphasis;
	int edp_vswing;
	bool edp_initialized;
	bool edp_support;
	int edp_bpp;
	struct edp_power_seq edp_pps;

R
Rodrigo Vivi 已提交
1508 1509 1510 1511 1512 1513 1514 1515 1516
	struct {
		bool full_link;
		bool require_aux_wakeup;
		int idle_frames;
		enum psr_lines_to_wait lines_to_wait;
		int tp1_wakeup_time;
		int tp2_tp3_wakeup_time;
	} psr;

1517 1518
	struct {
		u16 pwm_freq_hz;
1519
		bool present;
1520
		bool active_low_pwm;
1521
		u8 min_brightness;	/* min_brightness/255 of max */
1522 1523
	} backlight;

1524 1525
	/* MIPI DSI */
	struct {
1526
		u16 port;
1527
		u16 panel_id;
1528 1529 1530 1531 1532
		struct mipi_config *config;
		struct mipi_pps_data *pps;
		u8 seq_version;
		u32 size;
		u8 *data;
1533
		const u8 *sequence[MIPI_SEQ_MAX];
1534 1535
	} dsi;

1536 1537 1538
	int crt_ddc_pin;

	int child_dev_num;
1539
	union child_device_config *child_dev;
1540 1541

	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1542 1543
};

1544 1545 1546 1547 1548
enum intel_ddb_partitioning {
	INTEL_DDB_PART_1_2,
	INTEL_DDB_PART_5_6, /* IVB+ */
};

1549 1550 1551 1552 1553 1554 1555 1556
struct intel_wm_level {
	bool enable;
	uint32_t pri_val;
	uint32_t spr_val;
	uint32_t cur_val;
	uint32_t fbc_val;
};

1557
struct ilk_wm_values {
1558 1559 1560 1561 1562 1563 1564 1565
	uint32_t wm_pipe[3];
	uint32_t wm_lp[3];
	uint32_t wm_lp_spr[3];
	uint32_t wm_linetime[3];
	bool enable_fbc_wm;
	enum intel_ddb_partitioning partitioning;
};

1566 1567 1568 1569 1570
struct vlv_pipe_wm {
	uint16_t primary;
	uint16_t sprite[2];
	uint8_t cursor;
};
1571

1572 1573 1574 1575
struct vlv_sr_wm {
	uint16_t plane;
	uint8_t cursor;
};
1576

1577 1578 1579
struct vlv_wm_values {
	struct vlv_pipe_wm pipe[3];
	struct vlv_sr_wm sr;
1580 1581 1582 1583 1584
	struct {
		uint8_t cursor;
		uint8_t sprite[2];
		uint8_t primary;
	} ddl[3];
1585 1586
	uint8_t level;
	bool cxsr;
1587 1588
};

1589
struct skl_ddb_entry {
1590
	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
1591 1592 1593 1594
};

static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
{
1595
	return entry->end - entry->start;
1596 1597
}

1598 1599 1600 1601 1602 1603 1604 1605 1606
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
				       const struct skl_ddb_entry *e2)
{
	if (e1->start == e2->start && e1->end == e2->end)
		return true;

	return false;
}

1607
struct skl_ddb_allocation {
1608
	struct skl_ddb_entry pipe[I915_MAX_PIPES];
1609
	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1610
	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1611 1612
};

1613 1614
struct skl_wm_values {
	bool dirty[I915_MAX_PIPES];
1615
	struct skl_ddb_allocation ddb;
1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626
	uint32_t wm_linetime[I915_MAX_PIPES];
	uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
	uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
};

struct skl_wm_level {
	bool plane_en[I915_MAX_PLANES];
	uint16_t plane_res_b[I915_MAX_PLANES];
	uint8_t plane_res_l[I915_MAX_PLANES];
};

1627
/*
1628 1629 1630 1631
 * This struct helps tracking the state needed for runtime PM, which puts the
 * device in PCI D3 state. Notice that when this happens, nothing on the
 * graphics device works, even register access, so we don't get interrupts nor
 * anything else.
1632
 *
1633 1634 1635
 * Every piece of our code that needs to actually touch the hardware needs to
 * either call intel_runtime_pm_get or call intel_display_power_get with the
 * appropriate power domain.
1636
 *
1637 1638
 * Our driver uses the autosuspend delay feature, which means we'll only really
 * suspend if we stay with zero refcount for a certain amount of time. The
1639
 * default value is currently very conservative (see intel_runtime_pm_enable), but
1640
 * it can be changed with the standard runtime PM files from sysfs.
1641 1642 1643 1644 1645
 *
 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
 * goes back to false exactly before we reenable the IRQs. We use this variable
 * to check if someone is trying to enable/disable IRQs while they're supposed
 * to be disabled. This shouldn't happen and we'll print some error messages in
1646
 * case it happens.
1647
 *
1648
 * For more, read the Documentation/power/runtime_pm.txt.
1649
 */
1650
struct i915_runtime_pm {
1651
	atomic_t wakeref_count;
1652
	atomic_t atomic_seq;
1653
	bool suspended;
1654
	bool irqs_enabled;
1655 1656
};

1657 1658 1659 1660 1661
enum intel_pipe_crc_source {
	INTEL_PIPE_CRC_SOURCE_NONE,
	INTEL_PIPE_CRC_SOURCE_PLANE1,
	INTEL_PIPE_CRC_SOURCE_PLANE2,
	INTEL_PIPE_CRC_SOURCE_PF,
1662
	INTEL_PIPE_CRC_SOURCE_PIPE,
D
Daniel Vetter 已提交
1663 1664 1665 1666 1667
	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
	INTEL_PIPE_CRC_SOURCE_TV,
	INTEL_PIPE_CRC_SOURCE_DP_B,
	INTEL_PIPE_CRC_SOURCE_DP_C,
	INTEL_PIPE_CRC_SOURCE_DP_D,
1668
	INTEL_PIPE_CRC_SOURCE_AUTO,
1669 1670 1671
	INTEL_PIPE_CRC_SOURCE_MAX,
};

1672
struct intel_pipe_crc_entry {
1673
	uint32_t frame;
1674 1675 1676
	uint32_t crc[5];
};

1677
#define INTEL_PIPE_CRC_ENTRIES_NR	128
1678
struct intel_pipe_crc {
1679 1680
	spinlock_t lock;
	bool opened;		/* exclusive access to the result file */
1681
	struct intel_pipe_crc_entry *entries;
1682
	enum intel_pipe_crc_source source;
1683
	int head, tail;
1684
	wait_queue_head_t wq;
1685 1686
};

1687 1688 1689 1690 1691 1692 1693 1694 1695 1696 1697
struct i915_frontbuffer_tracking {
	struct mutex lock;

	/*
	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
	 * scheduled flips.
	 */
	unsigned busy_bits;
	unsigned flip_bits;
};

1698
struct i915_wa_reg {
1699
	i915_reg_t addr;
1700 1701 1702 1703 1704
	u32 value;
	/* bitmask representing WA bits */
	u32 mask;
};

1705 1706 1707 1708 1709 1710 1711
/*
 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
 * allowing it for RCS as we don't foresee any requirement of having
 * a whitelist for other engines. When it is really required for
 * other engines then the limit need to be increased.
 */
#define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1712 1713 1714 1715

struct i915_workarounds {
	struct i915_wa_reg reg[I915_MAX_WA_REGS];
	u32 count;
1716
	u32 hw_whitelist_count[I915_NUM_RINGS];
1717 1718
};

1719 1720 1721 1722
struct i915_virtual_gpu {
	bool active;
};

1723 1724 1725 1726 1727
struct i915_execbuffer_params {
	struct drm_device               *dev;
	struct drm_file                 *file;
	uint32_t                        dispatch_flags;
	uint32_t                        args_batch_start_offset;
1728
	uint64_t                        batch_obj_vm_offset;
1729 1730 1731
	struct intel_engine_cs          *ring;
	struct drm_i915_gem_object      *batch_obj;
	struct intel_context            *ctx;
1732
	struct drm_i915_gem_request     *request;
1733 1734
};

1735 1736 1737 1738 1739 1740 1741
/* used in computing the new watermarks state */
struct intel_wm_config {
	unsigned int num_pipes_active;
	bool sprites_enabled;
	bool sprites_scaled;
};

1742
struct drm_i915_private {
1743
	struct drm_device *dev;
1744
	struct kmem_cache *objects;
1745
	struct kmem_cache *vmas;
1746
	struct kmem_cache *requests;
1747

1748
	const struct intel_device_info info;
1749 1750 1751 1752 1753

	int relative_constants_mode;

	void __iomem *regs;

1754
	struct intel_uncore uncore;
1755

1756 1757
	struct i915_virtual_gpu vgpu;

1758 1759
	struct intel_guc guc;

1760 1761
	struct intel_csr csr;

1762
	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1763

1764 1765 1766 1767 1768 1769 1770 1771 1772
	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
	 * controller on different i2c buses. */
	struct mutex gmbus_mutex;

	/**
	 * Base address of the gmbus and gpio block.
	 */
	uint32_t gpio_mmio_base;

1773 1774 1775
	/* MMIO base address for MIPI regs */
	uint32_t mipi_mmio_base;

1776 1777
	uint32_t psr_mmio_base;

1778 1779
	wait_queue_head_t gmbus_wait_queue;

1780
	struct pci_dev *bridge_dev;
1781
	struct intel_engine_cs ring[I915_NUM_RINGS];
1782
	struct drm_i915_gem_object *semaphore_obj;
1783
	uint32_t last_seqno, next_seqno;
1784

1785
	struct drm_dma_handle *status_page_dmah;
1786 1787 1788 1789 1790
	struct resource mch_res;

	/* protects the irq masks */
	spinlock_t irq_lock;

1791 1792 1793
	/* protects the mmio flip data */
	spinlock_t mmio_flip_lock;

1794 1795
	bool display_irqs_enabled;

1796 1797 1798
	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
	struct pm_qos_request pm_qos;

V
Ville Syrjälä 已提交
1799 1800
	/* Sideband mailbox protection */
	struct mutex sb_lock;
1801 1802

	/** Cached value of IMR to avoid reads in updating the bitfield */
1803 1804 1805 1806
	union {
		u32 irq_mask;
		u32 de_irq_mask[I915_MAX_PIPES];
	};
1807
	u32 gt_irq_mask;
1808
	u32 pm_irq_mask;
1809
	u32 pm_rps_events;
1810
	u32 pipestat_irq_mask[I915_MAX_PIPES];
1811

1812
	struct i915_hotplug hotplug;
1813
	struct intel_fbc fbc;
1814
	struct i915_drrs drrs;
1815
	struct intel_opregion opregion;
1816
	struct intel_vbt_data vbt;
1817

1818 1819
	bool preserve_bios_swizzle;

1820 1821 1822
	/* overlay */
	struct intel_overlay *overlay;

1823
	/* backlight registers and fields in struct intel_panel */
1824
	struct mutex backlight_lock;
1825

1826 1827 1828
	/* LVDS info */
	bool no_aux_handshake;

V
Ville Syrjälä 已提交
1829 1830 1831
	/* protects panel power sequencer state */
	struct mutex pps_mutex;

1832 1833 1834 1835
	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */

	unsigned int fsb_freq, mem_freq, is_ddr3;
1836
	unsigned int skl_boot_cdclk;
1837
	unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
M
Mika Kahola 已提交
1838
	unsigned int max_dotclk_freq;
1839
	unsigned int hpll_freq;
1840
	unsigned int czclk_freq;
1841

1842 1843 1844 1845 1846 1847 1848
	/**
	 * wq - Driver workqueue for GEM.
	 *
	 * NOTE: Work items scheduled here are not allowed to grab any modeset
	 * locks, for otherwise the flushing done in the pageflip code will
	 * result in deadlocks.
	 */
1849 1850 1851 1852 1853 1854 1855
	struct workqueue_struct *wq;

	/* Display functions */
	struct drm_i915_display_funcs display;

	/* PCH chipset type */
	enum intel_pch pch_type;
1856
	unsigned short pch_id;
1857 1858 1859

	unsigned long quirks;

1860 1861
	enum modeset_restore modeset_restore;
	struct mutex modeset_restore_lock;
1862
	struct drm_atomic_state *modeset_restore_state;
1863

1864
	struct list_head vm_list; /* Global list of all address spaces */
1865
	struct i915_gtt gtt; /* VM representing the global address space */
B
Ben Widawsky 已提交
1866

1867
	struct i915_gem_mm mm;
1868 1869
	DECLARE_HASHTABLE(mm_structs, 7);
	struct mutex mm_lock;
1870 1871 1872

	/* Kernel Modesetting */

1873
	struct sdvo_device_mapping sdvo_mappings[2];
1874

1875 1876
	struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
	struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1877 1878
	wait_queue_head_t pending_flip_queue;

1879 1880 1881 1882
#ifdef CONFIG_DEBUG_FS
	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif

1883
	/* dpll and cdclk state is protected by connection_mutex */
D
Daniel Vetter 已提交
1884 1885
	int num_shared_dpll;
	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1886 1887 1888 1889

	unsigned int active_crtcs;
	unsigned int min_pixclk[I915_MAX_PIPES];

1890
	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1891

1892
	struct i915_workarounds workarounds;
1893

1894 1895
	/* Reclocking support */
	bool render_reclock_avail;
1896 1897 1898

	struct i915_frontbuffer_tracking fb_tracking;

1899
	u16 orig_clock;
1900

1901
	bool mchbar_need_disable;
1902

1903 1904
	struct intel_l3_parity l3_parity;

B
Ben Widawsky 已提交
1905 1906 1907
	/* Cannot be determined by PCIID. You must always read a register. */
	size_t ellc_size;

1908
	/* gen6+ rps state */
1909
	struct intel_gen6_power_mgmt rps;
1910

1911 1912
	/* ilk-only ips/rps state. Everything in here is protected by the global
	 * mchdev_lock in intel_pm.c */
1913
	struct intel_ilk_power_mgmt ips;
1914

1915
	struct i915_power_domains power_domains;
1916

R
Rodrigo Vivi 已提交
1917
	struct i915_psr psr;
1918

1919
	struct i915_gpu_error gpu_error;
1920

1921 1922
	struct drm_i915_gem_object *vlv_pctx;

1923
#ifdef CONFIG_DRM_FBDEV_EMULATION
1924 1925
	/* list of fbdev register on this device */
	struct intel_fbdev *fbdev;
1926
	struct work_struct fbdev_suspend_work;
1927
#endif
1928 1929

	struct drm_property *broadcast_rgb_property;
1930
	struct drm_property *force_audio_property;
1931

I
Imre Deak 已提交
1932
	/* hda/i915 audio component */
1933
	struct i915_audio_component *audio_component;
I
Imre Deak 已提交
1934
	bool audio_component_registered;
1935 1936 1937 1938 1939
	/**
	 * av_mutex - mutex for audio/video sync
	 *
	 */
	struct mutex av_mutex;
I
Imre Deak 已提交
1940

1941
	uint32_t hw_context_size;
1942
	struct list_head context_list;
1943

1944
	u32 fdi_rx_config;
1945

1946 1947
	u32 chv_phy_control;

1948
	u32 suspend_count;
1949
	bool suspended_to_idle;
1950
	struct i915_suspend_saved_registers regfile;
1951
	struct vlv_s0ix_state vlv_s0ix_state;
1952

1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963 1964
	struct {
		/*
		 * Raw watermark latency values:
		 * in 0.1us units for WM0,
		 * in 0.5us units for WM1+.
		 */
		/* primary */
		uint16_t pri_latency[5];
		/* sprite */
		uint16_t spr_latency[5];
		/* cursor */
		uint16_t cur_latency[5];
1965 1966 1967 1968 1969 1970
		/*
		 * Raw watermark memory latency values
		 * for SKL for all 8 levels
		 * in 1us units.
		 */
		uint16_t skl_latency[8];
1971

1972 1973 1974
		/* Committed wm config */
		struct intel_wm_config config;

1975 1976 1977 1978 1979 1980 1981
		/*
		 * The skl_wm_values structure is a bit too big for stack
		 * allocation, so we keep the staging struct where we store
		 * intermediate results here instead.
		 */
		struct skl_wm_values skl_results;

1982
		/* current hardware state */
1983 1984 1985
		union {
			struct ilk_wm_values hw;
			struct skl_wm_values skl_hw;
1986
			struct vlv_wm_values vlv;
1987
		};
1988 1989

		uint8_t max_level;
1990 1991 1992 1993 1994 1995 1996

		/*
		 * Should be held around atomic WM register writing; also
		 * protects * intel_crtc->wm.active and
		 * cstate->wm.need_postvbl_update.
		 */
		struct mutex wm_mutex;
1997 1998
	} wm;

1999 2000
	struct i915_runtime_pm pm;

2001 2002
	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
	struct {
2003
		int (*execbuf_submit)(struct i915_execbuffer_params *params,
2004
				      struct drm_i915_gem_execbuffer2 *args,
2005
				      struct list_head *vmas);
2006 2007 2008 2009 2010
		int (*init_rings)(struct drm_device *dev);
		void (*cleanup_ring)(struct intel_engine_cs *ring);
		void (*stop_ring)(struct intel_engine_cs *ring);
	} gt;

2011 2012
	struct intel_context *kernel_context;

2013 2014
	bool edp_low_vswing;

2015 2016 2017
	/* perform PHY state sanity checks? */
	bool chv_phy_assert[2];

2018 2019
	struct intel_encoder *dig_port_map[I915_MAX_PORTS];

2020 2021 2022 2023
	/*
	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
	 * will be rejected. Instead look for a better place.
	 */
2024
};
L
Linus Torvalds 已提交
2025

2026 2027 2028 2029 2030
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
	return dev->dev_private;
}

I
Imre Deak 已提交
2031 2032 2033 2034 2035
static inline struct drm_i915_private *dev_to_i915(struct device *dev)
{
	return to_i915(dev_get_drvdata(dev));
}

2036 2037 2038 2039 2040
static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
{
	return container_of(guc, struct drm_i915_private, guc);
}

2041 2042 2043
/* Iterate over initialised rings */
#define for_each_ring(ring__, dev_priv__, i__) \
	for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
2044
		for_each_if ((((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))))
2045

2046 2047 2048 2049 2050 2051 2052
enum hdmi_force_audio {
	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
	HDMI_AUDIO_AUTO,		/* trust EDID */
	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
};

2053
#define I915_GTT_OFFSET_NONE ((u32)-1)
2054

2055
struct drm_i915_gem_object_ops {
2056 2057 2058
	unsigned int flags;
#define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1

2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073
	/* Interface between the GEM object and its backing storage.
	 * get_pages() is called once prior to the use of the associated set
	 * of pages before to binding them into the GTT, and put_pages() is
	 * called after we no longer need them. As we expect there to be
	 * associated cost with migrating pages between the backing storage
	 * and making them available for the GPU (e.g. clflush), we may hold
	 * onto the pages after they are no longer referenced by the GPU
	 * in case they may be used again shortly (for example migrating the
	 * pages to a different memory domain within the GTT). put_pages()
	 * will therefore most likely be called when the object itself is
	 * being released or under memory pressure (where we attempt to
	 * reap pages for the shrinker).
	 */
	int (*get_pages)(struct drm_i915_gem_object *);
	void (*put_pages)(struct drm_i915_gem_object *);
2074

2075 2076
	int (*dmabuf_export)(struct drm_i915_gem_object *);
	void (*release)(struct drm_i915_gem_object *);
2077 2078
};

2079 2080
/*
 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2081
 * considered to be the frontbuffer for the given plane interface-wise. This
2082 2083 2084 2085 2086
 * doesn't mean that the hw necessarily already scans it out, but that any
 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
 *
 * We have one bit per pipe and per scanout plane type.
 */
2087 2088
#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2089 2090 2091 2092 2093
#define INTEL_FRONTBUFFER_BITS \
	(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
#define INTEL_FRONTBUFFER_CURSOR(pipe) \
2094 2095 2096
	(1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
	(1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2097
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2098
	(1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2099
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2100
	(0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2101

2102
struct drm_i915_gem_object {
2103
	struct drm_gem_object base;
2104

2105 2106
	const struct drm_i915_gem_object_ops *ops;

B
Ben Widawsky 已提交
2107 2108 2109
	/** List of VMAs backed by this object */
	struct list_head vma_list;

2110 2111
	/** Stolen memory for this object, instead of being backed by shmem. */
	struct drm_mm_node *stolen;
2112
	struct list_head global_list;
2113

2114
	struct list_head ring_list[I915_NUM_RINGS];
2115 2116
	/** Used in execbuf to temporarily hold a ref */
	struct list_head obj_exec_link;
2117

2118
	struct list_head batch_pool_link;
2119

2120
	/**
2121 2122 2123
	 * This is set if the object is on the active lists (has pending
	 * rendering and so a non-zero seqno), and is not set if it i s on
	 * inactive (ready to be unbound) list.
2124
	 */
2125
	unsigned int active:I915_NUM_RINGS;
2126 2127 2128 2129 2130

	/**
	 * This is set if the object has been written to since last bound
	 * to the GTT
	 */
2131
	unsigned int dirty:1;
2132 2133 2134 2135 2136 2137

	/**
	 * Fence register bits (if any) for this object.  Will be set
	 * as needed when mapped into the GTT.
	 * Protected by dev->struct_mutex.
	 */
2138
	signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2139 2140 2141 2142

	/**
	 * Advice: are the backing pages purgeable?
	 */
2143
	unsigned int madv:2;
2144 2145 2146 2147

	/**
	 * Current tiling mode for the object.
	 */
2148
	unsigned int tiling_mode:2;
2149 2150 2151 2152 2153 2154 2155 2156
	/**
	 * Whether the tiling parameters for the currently associated fence
	 * register have changed. Note that for the purposes of tracking
	 * tiling changes we also treat the unfenced register, the register
	 * slot that the object occupies whilst it executes a fenced
	 * command (such as BLT on gen2/3), as a "fence".
	 */
	unsigned int fence_dirty:1;
2157

2158 2159 2160 2161
	/**
	 * Is the object at the current location in the gtt mappable and
	 * fenceable? Used to avoid costly recalculations.
	 */
2162
	unsigned int map_and_fenceable:1;
2163

2164 2165 2166 2167 2168
	/**
	 * Whether the current gtt mapping needs to be mappable (and isn't just
	 * mappable by accident). Track pin and fault separate for a more
	 * accurate mappable working set.
	 */
2169
	unsigned int fault_mappable:1;
2170

2171 2172 2173 2174 2175
	/*
	 * Is the object to be mapped as read-only to the GPU
	 * Only honoured if hardware has relevant pte bit
	 */
	unsigned long gt_ro:1;
2176
	unsigned int cache_level:3;
2177
	unsigned int cache_dirty:1;
2178

2179 2180
	unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;

2181 2182
	unsigned int pin_display;

2183
	struct sg_table *pages;
2184
	int pages_pin_count;
2185 2186 2187 2188
	struct get_page {
		struct scatterlist *sg;
		int last;
	} get_page;
2189

2190
	/* prime dma-buf support */
2191 2192 2193
	void *dma_buf_vmapping;
	int vmapping_count;

2194 2195 2196 2197 2198 2199 2200 2201 2202 2203 2204
	/** Breadcrumb of last rendering to the buffer.
	 * There can only be one writer, but we allow for multiple readers.
	 * If there is a writer that necessarily implies that all other
	 * read requests are complete - but we may only be lazily clearing
	 * the read requests. A read request is naturally the most recent
	 * request on a ring, so we may have two different write and read
	 * requests on one ring where the write request is older than the
	 * read request. This allows for the CPU to read from an active
	 * buffer by only waiting for the write to complete.
	 * */
	struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
2205
	struct drm_i915_gem_request *last_write_req;
2206
	/** Breadcrumb of last fenced GPU access to the buffer. */
2207
	struct drm_i915_gem_request *last_fenced_req;
2208

2209
	/** Current tiling stride for the object, if it's tiled. */
2210
	uint32_t stride;
2211

2212 2213 2214
	/** References from framebuffers, locks out tiling changes. */
	unsigned long framebuffer_references;

2215
	/** Record of address bit 17 of each page at last unbind. */
2216
	unsigned long *bit_17;
2217

2218
	union {
2219 2220 2221
		/** for phy allocated objects */
		struct drm_dma_handle *phys_handle;

2222 2223 2224 2225 2226 2227
		struct i915_gem_userptr {
			uintptr_t ptr;
			unsigned read_only :1;
			unsigned workers :4;
#define I915_GEM_USERPTR_MAX_WORKERS 15

2228 2229
			struct i915_mm_struct *mm;
			struct i915_mmu_object *mmu_object;
2230 2231 2232 2233
			struct work_struct *work;
		} userptr;
	};
};
2234
#define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2235

2236 2237 2238 2239
void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits);

2240 2241 2242 2243 2244 2245
/**
 * Request queue structure.
 *
 * The request queue allows us to note sequence numbers that have been emitted
 * and may be associated with active buffers to be retired.
 *
2246 2247 2248 2249
 * By keeping this list, we can avoid having to do questionable sequence
 * number comparisons on buffer last_read|write_seqno. It also allows an
 * emission time to be associated with the request for tracking how far ahead
 * of the GPU the submission is.
2250 2251 2252
 *
 * The requests are reference counted, so upon creation they should have an
 * initial reference taken using kref_init
2253 2254
 */
struct drm_i915_gem_request {
2255 2256
	struct kref ref;

2257
	/** On Which ring this request was generated */
2258
	struct drm_i915_private *i915;
2259
	struct intel_engine_cs *ring;
2260

2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 2271
	 /** GEM sequence number associated with the previous request,
	  * when the HWS breadcrumb is equal to this the GPU is processing
	  * this request.
	  */
	u32 previous_seqno;

	 /** GEM sequence number associated with this request,
	  * when the HWS breadcrumb is equal or greater than this the GPU
	  * has finished processing this request.
	  */
	u32 seqno;
2272

2273 2274 2275
	/** Position in the ringbuffer of the start of the request */
	u32 head;

2276 2277 2278 2279 2280 2281 2282 2283
	/**
	 * Position in the ringbuffer of the start of the postfix.
	 * This is required to calculate the maximum available ringbuffer
	 * space without overwriting the postfix.
	 */
	 u32 postfix;

	/** Position in the ringbuffer of the end of the whole request */
2284 2285
	u32 tail;

2286
	/**
D
Dave Airlie 已提交
2287
	 * Context and ring buffer related to this request
2288 2289 2290 2291 2292 2293 2294 2295
	 * Contexts are refcounted, so when this request is associated with a
	 * context, we must increment the context's refcount, to guarantee that
	 * it persists while any request is linked to it. Requests themselves
	 * are also refcounted, so the request will only be freed when the last
	 * reference to it is dismissed, and the code in
	 * i915_gem_request_free() will then decrement the refcount on the
	 * context.
	 */
2296
	struct intel_context *ctx;
2297
	struct intel_ringbuffer *ringbuf;
2298

2299 2300
	/** Batch buffer related to this request if any (used for
	    error state dump only) */
2301 2302
	struct drm_i915_gem_object *batch_obj;

2303 2304 2305
	/** Time at which this request was emitted, in jiffies. */
	unsigned long emitted_jiffies;

2306
	/** global list entry for this request */
2307
	struct list_head list;
2308

2309
	struct drm_i915_file_private *file_priv;
2310 2311
	/** file_priv list entry for this request */
	struct list_head client_list;
2312

2313 2314 2315
	/** process identifier submitting this request */
	struct pid *pid;

2316 2317 2318 2319 2320 2321 2322 2323 2324 2325 2326 2327 2328 2329 2330 2331 2332 2333 2334
	/**
	 * The ELSP only accepts two elements at a time, so we queue
	 * context/tail pairs on a given queue (ring->execlist_queue) until the
	 * hardware is available. The queue serves a double purpose: we also use
	 * it to keep track of the up to 2 contexts currently in the hardware
	 * (usually one in execution and the other queued up by the GPU): We
	 * only remove elements from the head of the queue when the hardware
	 * informs us that an element has been completed.
	 *
	 * All accesses to the queue are mediated by a spinlock
	 * (ring->execlist_lock).
	 */

	/** Execlist link in the submission queue.*/
	struct list_head execlist_link;

	/** Execlists no. of times this request has been sent to the ELSP */
	int elsp_submitted;

2335 2336
};

2337 2338 2339
struct drm_i915_gem_request * __must_check
i915_gem_request_alloc(struct intel_engine_cs *engine,
		       struct intel_context *ctx);
2340
void i915_gem_request_cancel(struct drm_i915_gem_request *req);
2341
void i915_gem_request_free(struct kref *req_ref);
2342 2343
int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
				   struct drm_file *file);
2344

2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356
static inline uint32_t
i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
{
	return req ? req->seqno : 0;
}

static inline struct intel_engine_cs *
i915_gem_request_get_ring(struct drm_i915_gem_request *req)
{
	return req ? req->ring : NULL;
}

2357
static inline struct drm_i915_gem_request *
2358 2359
i915_gem_request_reference(struct drm_i915_gem_request *req)
{
2360 2361 2362
	if (req)
		kref_get(&req->ref);
	return req;
2363 2364 2365 2366 2367
}

static inline void
i915_gem_request_unreference(struct drm_i915_gem_request *req)
{
2368
	WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2369 2370 2371
	kref_put(&req->ref, i915_gem_request_free);
}

2372 2373 2374
static inline void
i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
{
2375 2376 2377 2378
	struct drm_device *dev;

	if (!req)
		return;
2379

2380 2381
	dev = req->ring->dev;
	if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2382 2383 2384
		mutex_unlock(&dev->struct_mutex);
}

2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396
static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
					   struct drm_i915_gem_request *src)
{
	if (src)
		i915_gem_request_reference(src);

	if (*pdst)
		i915_gem_request_unreference(*pdst);

	*pdst = src;
}

2397 2398 2399 2400 2401 2402
/*
 * XXX: i915_gem_request_completed should be here but currently needs the
 * definition of i915_seqno_passed() which is below. It will be moved in
 * a later patch when the call to i915_seqno_passed() is obsoleted...
 */

2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454
/*
 * A command that requires special handling by the command parser.
 */
struct drm_i915_cmd_descriptor {
	/*
	 * Flags describing how the command parser processes the command.
	 *
	 * CMD_DESC_FIXED: The command has a fixed length if this is set,
	 *                 a length mask if not set
	 * CMD_DESC_SKIP: The command is allowed but does not follow the
	 *                standard length encoding for the opcode range in
	 *                which it falls
	 * CMD_DESC_REJECT: The command is never allowed
	 * CMD_DESC_REGISTER: The command should be checked against the
	 *                    register whitelist for the appropriate ring
	 * CMD_DESC_MASTER: The command is allowed if the submitting process
	 *                  is the DRM master
	 */
	u32 flags;
#define CMD_DESC_FIXED    (1<<0)
#define CMD_DESC_SKIP     (1<<1)
#define CMD_DESC_REJECT   (1<<2)
#define CMD_DESC_REGISTER (1<<3)
#define CMD_DESC_BITMASK  (1<<4)
#define CMD_DESC_MASTER   (1<<5)

	/*
	 * The command's unique identification bits and the bitmask to get them.
	 * This isn't strictly the opcode field as defined in the spec and may
	 * also include type, subtype, and/or subop fields.
	 */
	struct {
		u32 value;
		u32 mask;
	} cmd;

	/*
	 * The command's length. The command is either fixed length (i.e. does
	 * not include a length field) or has a length field mask. The flag
	 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
	 * a length mask. All command entries in a command table must include
	 * length information.
	 */
	union {
		u32 fixed;
		u32 mask;
	} length;

	/*
	 * Describes where to find a register address in the command to check
	 * against the ring's register whitelist. Only valid if flags has the
	 * CMD_DESC_REGISTER bit set.
2455 2456 2457 2458
	 *
	 * A non-zero step value implies that the command may access multiple
	 * registers in sequence (e.g. LRI), in that case step gives the
	 * distance in dwords between individual offset fields.
2459 2460 2461 2462
	 */
	struct {
		u32 offset;
		u32 mask;
2463
		u32 step;
2464 2465 2466 2467 2468 2469 2470 2471 2472
	} reg;

#define MAX_CMD_DESC_BITMASKS 3
	/*
	 * Describes command checks where a particular dword is masked and
	 * compared against an expected value. If the command does not match
	 * the expected value, the parser rejects it. Only valid if flags has
	 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
	 * are valid.
2473 2474 2475 2476
	 *
	 * If the check specifies a non-zero condition_mask then the parser
	 * only performs the check when the bits specified by condition_mask
	 * are non-zero.
2477 2478 2479 2480 2481
	 */
	struct {
		u32 offset;
		u32 mask;
		u32 expected;
2482 2483
		u32 condition_offset;
		u32 condition_mask;
2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497
	} bits[MAX_CMD_DESC_BITMASKS];
};

/*
 * A table of commands requiring special handling by the command parser.
 *
 * Each ring has an array of tables. Each table consists of an array of command
 * descriptors, which must be sorted with command opcodes in ascending order.
 */
struct drm_i915_cmd_table {
	const struct drm_i915_cmd_descriptor *table;
	int count;
};

C
Chris Wilson 已提交
2498
/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2499 2500 2501 2502 2503 2504 2505 2506 2507 2508
#define __I915__(p) ({ \
	struct drm_i915_private *__p; \
	if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
		__p = (struct drm_i915_private *)p; \
	else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
		__p = to_i915((struct drm_device *)p); \
	else \
		BUILD_BUG(); \
	__p; \
})
C
Chris Wilson 已提交
2509
#define INTEL_INFO(p) 	(&__I915__(p)->info)
2510
#define INTEL_DEVID(p)	(INTEL_INFO(p)->device_id)
2511
#define INTEL_REVID(p)	(__I915__(p)->dev->pdev->revision)
2512

2513 2514 2515 2516 2517 2518 2519 2520 2521
#define REVID_FOREVER		0xff
/*
 * Return true if revision is in range [since,until] inclusive.
 *
 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
 */
#define IS_REVID(p, since, until) \
	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))

2522 2523
#define IS_I830(dev)		(INTEL_DEVID(dev) == 0x3577)
#define IS_845G(dev)		(INTEL_DEVID(dev) == 0x2562)
2524
#define IS_I85X(dev)		(INTEL_INFO(dev)->is_i85x)
2525
#define IS_I865G(dev)		(INTEL_DEVID(dev) == 0x2572)
2526
#define IS_I915G(dev)		(INTEL_INFO(dev)->is_i915g)
2527 2528
#define IS_I915GM(dev)		(INTEL_DEVID(dev) == 0x2592)
#define IS_I945G(dev)		(INTEL_DEVID(dev) == 0x2772)
2529 2530 2531
#define IS_I945GM(dev)		(INTEL_INFO(dev)->is_i945gm)
#define IS_BROADWATER(dev)	(INTEL_INFO(dev)->is_broadwater)
#define IS_CRESTLINE(dev)	(INTEL_INFO(dev)->is_crestline)
2532
#define IS_GM45(dev)		(INTEL_DEVID(dev) == 0x2A42)
2533
#define IS_G4X(dev)		(INTEL_INFO(dev)->is_g4x)
2534 2535
#define IS_PINEVIEW_G(dev)	(INTEL_DEVID(dev) == 0xa001)
#define IS_PINEVIEW_M(dev)	(INTEL_DEVID(dev) == 0xa011)
2536 2537
#define IS_PINEVIEW(dev)	(INTEL_INFO(dev)->is_pineview)
#define IS_G33(dev)		(INTEL_INFO(dev)->is_g33)
2538
#define IS_IRONLAKE_M(dev)	(INTEL_DEVID(dev) == 0x0046)
2539
#define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
2540 2541 2542
#define IS_IVB_GT1(dev)		(INTEL_DEVID(dev) == 0x0156 || \
				 INTEL_DEVID(dev) == 0x0152 || \
				 INTEL_DEVID(dev) == 0x015a)
2543
#define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
2544
#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_cherryview)
2545
#define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
2546
#define IS_BROADWELL(dev)	(!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
2547
#define IS_SKYLAKE(dev)	(INTEL_INFO(dev)->is_skylake)
2548
#define IS_BROXTON(dev)		(INTEL_INFO(dev)->is_broxton)
2549
#define IS_KABYLAKE(dev)	(INTEL_INFO(dev)->is_kabylake)
2550
#define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
2551
#define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \
2552
				 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
B
Ben Widawsky 已提交
2553
#define IS_BDW_ULT(dev)		(IS_BROADWELL(dev) && \
2554
				 ((INTEL_DEVID(dev) & 0xf) == 0x6 ||	\
2555
				 (INTEL_DEVID(dev) & 0xf) == 0xb ||	\
2556
				 (INTEL_DEVID(dev) & 0xf) == 0xe))
V
Ville Syrjälä 已提交
2557 2558 2559
/* ULX machines are also considered ULT. */
#define IS_BDW_ULX(dev)		(IS_BROADWELL(dev) && \
				 (INTEL_DEVID(dev) & 0xf) == 0xe)
R
Rodrigo Vivi 已提交
2560 2561
#define IS_BDW_GT3(dev)		(IS_BROADWELL(dev) && \
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
B
Ben Widawsky 已提交
2562
#define IS_HSW_ULT(dev)		(IS_HASWELL(dev) && \
2563
				 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2564
#define IS_HSW_GT3(dev)		(IS_HASWELL(dev) && \
2565
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2566
/* ULX machines are also considered ULT. */
2567 2568
#define IS_HSW_ULX(dev)		(INTEL_DEVID(dev) == 0x0A0E || \
				 INTEL_DEVID(dev) == 0x0A1E)
2569 2570 2571 2572 2573 2574 2575 2576
#define IS_SKL_ULT(dev)		(INTEL_DEVID(dev) == 0x1906 || \
				 INTEL_DEVID(dev) == 0x1913 || \
				 INTEL_DEVID(dev) == 0x1916 || \
				 INTEL_DEVID(dev) == 0x1921 || \
				 INTEL_DEVID(dev) == 0x1926)
#define IS_SKL_ULX(dev)		(INTEL_DEVID(dev) == 0x190E || \
				 INTEL_DEVID(dev) == 0x1915 || \
				 INTEL_DEVID(dev) == 0x191E)
2577 2578 2579 2580 2581 2582 2583 2584
#define IS_KBL_ULT(dev)		(INTEL_DEVID(dev) == 0x5906 || \
				 INTEL_DEVID(dev) == 0x5913 || \
				 INTEL_DEVID(dev) == 0x5916 || \
				 INTEL_DEVID(dev) == 0x5921 || \
				 INTEL_DEVID(dev) == 0x5926)
#define IS_KBL_ULX(dev)		(INTEL_DEVID(dev) == 0x590E || \
				 INTEL_DEVID(dev) == 0x5915 || \
				 INTEL_DEVID(dev) == 0x591E)
2585 2586 2587 2588 2589
#define IS_SKL_GT3(dev)		(IS_SKYLAKE(dev) && \
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
#define IS_SKL_GT4(dev)		(IS_SKYLAKE(dev) && \
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)

2590
#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2591

2592 2593 2594 2595 2596 2597 2598
#define SKL_REVID_A0		0x0
#define SKL_REVID_B0		0x1
#define SKL_REVID_C0		0x2
#define SKL_REVID_D0		0x3
#define SKL_REVID_E0		0x4
#define SKL_REVID_F0		0x5

2599 2600
#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))

2601
#define BXT_REVID_A0		0x0
2602
#define BXT_REVID_A1		0x1
2603 2604
#define BXT_REVID_B0		0x3
#define BXT_REVID_C0		0x9
N
Nick Hoath 已提交
2605

2606 2607
#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))

2608 2609 2610 2611 2612 2613
/*
 * The genX designation typically refers to the render engine, so render
 * capability related checks should use IS_GEN, while display and other checks
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 * chips, etc.).
 */
2614 2615 2616 2617 2618
#define IS_GEN2(dev)	(INTEL_INFO(dev)->gen == 2)
#define IS_GEN3(dev)	(INTEL_INFO(dev)->gen == 3)
#define IS_GEN4(dev)	(INTEL_INFO(dev)->gen == 4)
#define IS_GEN5(dev)	(INTEL_INFO(dev)->gen == 5)
#define IS_GEN6(dev)	(INTEL_INFO(dev)->gen == 6)
2619
#define IS_GEN7(dev)	(INTEL_INFO(dev)->gen == 7)
B
Ben Widawsky 已提交
2620
#define IS_GEN8(dev)	(INTEL_INFO(dev)->gen == 8)
2621
#define IS_GEN9(dev)	(INTEL_INFO(dev)->gen == 9)
2622

2623 2624 2625 2626
#define RENDER_RING		(1<<RCS)
#define BSD_RING		(1<<VCS)
#define BLT_RING		(1<<BCS)
#define VEBOX_RING		(1<<VECS)
2627
#define BSD2_RING		(1<<VCS2)
2628
#define HAS_BSD(dev)		(INTEL_INFO(dev)->ring_mask & BSD_RING)
2629
#define HAS_BSD2(dev)		(INTEL_INFO(dev)->ring_mask & BSD2_RING)
2630 2631 2632 2633
#define HAS_BLT(dev)		(INTEL_INFO(dev)->ring_mask & BLT_RING)
#define HAS_VEBOX(dev)		(INTEL_INFO(dev)->ring_mask & VEBOX_RING)
#define HAS_LLC(dev)		(INTEL_INFO(dev)->has_llc)
#define HAS_WT(dev)		((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2634
				 __I915__(dev)->ellc_size)
2635 2636
#define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)

2637
#define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 6)
2638
#define HAS_LOGICAL_RING_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 8)
2639
#define USES_PPGTT(dev)		(i915.enable_ppgtt)
2640 2641
#define USES_FULL_PPGTT(dev)	(i915.enable_ppgtt >= 2)
#define USES_FULL_48BIT_PPGTT(dev)	(i915.enable_ppgtt == 3)
2642

2643
#define HAS_OVERLAY(dev)		(INTEL_INFO(dev)->has_overlay)
2644 2645
#define OVERLAY_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->overlay_needs_physical)

2646 2647
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
#define HAS_BROKEN_CS_TLB(dev)		(IS_I830(dev) || IS_845G(dev))
2648 2649 2650 2651 2652

/* WaRsDisableCoarsePowerGating:skl,bxt */
#define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
						 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && \
						  IS_SKL_REVID(dev, 0, SKL_REVID_F0)))
2653 2654 2655 2656 2657 2658 2659 2660
/*
 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
 * even when in MSI mode. This results in spurious interrupt warnings if the
 * legacy irq no. is shared with another device. The kernel then disables that
 * interrupt source and so prevents the other device from working properly.
 */
#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2661

2662 2663 2664 2665 2666 2667 2668 2669 2670 2671
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
						      IS_I915GM(dev)))
#define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)
#define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)

#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2672
#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2673

2674
#define HAS_IPS(dev)		(IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2675

2676 2677 2678
#define HAS_DP_MST(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \
				 INTEL_INFO(dev)->gen >= 9)

2679
#define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
2680
#define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
2681
#define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2682
				 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2683
				 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2684
#define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
S
Suketu Shah 已提交
2685
				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2686 2687
				 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
				 IS_KABYLAKE(dev))
2688 2689
#define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
#define HAS_RC6p(dev)		(INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
P
Paulo Zanoni 已提交
2690

2691
#define HAS_CSR(dev)	(IS_GEN9(dev))
2692

2693 2694
#define HAS_GUC_UCODE(dev)	(IS_GEN9(dev) && !IS_KABYLAKE(dev))
#define HAS_GUC_SCHED(dev)	(IS_GEN9(dev) && !IS_KABYLAKE(dev))
2695

2696 2697 2698
#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
				    INTEL_INFO(dev)->gen >= 8)

2699
#define HAS_CORE_RING_FREQ(dev)	(INTEL_INFO(dev)->gen >= 6 && \
2700 2701
				 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
				 !IS_BROXTON(dev))
2702

2703 2704 2705 2706 2707 2708
#define INTEL_PCH_DEVICE_ID_MASK		0xff00
#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
2709 2710
#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
2711
#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
2712
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
2713

2714
#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2715
#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2716
#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2717
#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
V
Ville Syrjälä 已提交
2718
#define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2719 2720
#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
B
Ben Widawsky 已提交
2721
#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2722
#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2723

2724 2725
#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
			       IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2726

2727 2728 2729
/* DPF == dynamic parity feature */
#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2730

2731
#define GT_FREQUENCY_MULTIPLIER 50
A
Akash Goel 已提交
2732
#define GEN9_FREQ_SCALER 3
2733

2734 2735
#include "i915_trace.h"

R
Rob Clark 已提交
2736
extern const struct drm_ioctl_desc i915_ioctls[];
2737 2738
extern int i915_max_ioctl;

2739 2740
extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
extern int i915_resume_switcheroo(struct drm_device *dev);
2741

2742
/* i915_dma.c */
2743
extern int i915_driver_load(struct drm_device *, unsigned long flags);
J
Jesse Barnes 已提交
2744
extern int i915_driver_unload(struct drm_device *);
2745
extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2746
extern void i915_driver_lastclose(struct drm_device * dev);
2747
extern void i915_driver_preclose(struct drm_device *dev,
2748
				 struct drm_file *file);
2749
extern void i915_driver_postclose(struct drm_device *dev,
2750
				  struct drm_file *file);
2751
#ifdef CONFIG_COMPAT
D
Dave Airlie 已提交
2752 2753
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);
2754
#endif
2755
extern int intel_gpu_reset(struct drm_device *dev);
2756
extern bool intel_has_gpu_reset(struct drm_device *dev);
2757
extern int i915_reset(struct drm_device *dev);
2758 2759 2760 2761
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2762
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2763

2764 2765 2766 2767 2768
/* intel_hotplug.c */
void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
void intel_hpd_init(struct drm_i915_private *dev_priv);
void intel_hpd_init_work(struct drm_i915_private *dev_priv);
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2769
bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2770

L
Linus Torvalds 已提交
2771
/* i915_irq.c */
2772
void i915_queue_hangcheck(struct drm_device *dev);
2773 2774 2775
__printf(3, 4)
void i915_handle_error(struct drm_device *dev, bool wedged,
		       const char *fmt, ...);
L
Linus Torvalds 已提交
2776

2777
extern void intel_irq_init(struct drm_i915_private *dev_priv);
2778 2779
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2780 2781

extern void intel_uncore_sanitize(struct drm_device *dev);
2782 2783
extern void intel_uncore_early_sanitize(struct drm_device *dev,
					bool restore_forcewake);
2784
extern void intel_uncore_init(struct drm_device *dev);
2785
extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2786
extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2787
extern void intel_uncore_fini(struct drm_device *dev);
2788
extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2789
const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2790
void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2791
				enum forcewake_domains domains);
2792
void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2793
				enum forcewake_domains domains);
2794 2795 2796 2797 2798 2799 2800
/* Like above but the caller must manage the uncore.lock itself.
 * Must be used with I915_READ_FW and friends.
 */
void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
2801
void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2802 2803 2804 2805
static inline bool intel_vgpu_active(struct drm_device *dev)
{
	return to_i915(dev)->vgpu.active;
}
2806

2807
void
2808
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2809
		     u32 status_mask);
2810 2811

void
2812
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2813
		      u32 status_mask);
2814

2815 2816
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2817 2818 2819
void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
				   uint32_t mask,
				   uint32_t bits);
2820 2821 2822 2823 2824 2825 2826 2827 2828 2829 2830 2831 2832
void ilk_update_display_irq(struct drm_i915_private *dev_priv,
			    uint32_t interrupt_mask,
			    uint32_t enabled_irq_mask);
static inline void
ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, bits);
}
static inline void
ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, 0);
}
2833 2834 2835 2836 2837 2838 2839 2840 2841 2842 2843 2844 2845 2846
void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
			 enum pipe pipe,
			 uint32_t interrupt_mask,
			 uint32_t enabled_irq_mask);
static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
				       enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
}
static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
					enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
}
2847 2848 2849
void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask);
2850 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860
static inline void
ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, bits);
}
static inline void
ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, 0);
}

2861

2862 2863 2864 2865 2866 2867 2868 2869 2870
/* i915_gem.c */
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2871 2872
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2873 2874 2875 2876
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
			     struct drm_file *file_priv);
2877
void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2878
					struct drm_i915_gem_request *req);
2879
void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
2880
int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
2881
				   struct drm_i915_gem_execbuffer2 *args,
2882
				   struct list_head *vmas);
2883 2884
int i915_gem_execbuffer(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
J
Jesse Barnes 已提交
2885 2886
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
2887 2888
int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
B
Ben Widawsky 已提交
2889 2890 2891 2892
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
2893 2894
int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
2895 2896
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
2897 2898 2899 2900
int i915_gem_set_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
int i915_gem_get_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2901 2902 2903
int i915_gem_init_userptr(struct drm_device *dev);
int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file);
2904 2905
int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
2906 2907
int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
2908 2909
void i915_gem_load_init(struct drm_device *dev);
void i915_gem_load_cleanup(struct drm_device *dev);
2910 2911
void *i915_gem_object_alloc(struct drm_device *dev);
void i915_gem_object_free(struct drm_i915_gem_object *obj);
2912 2913
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			 const struct drm_i915_gem_object_ops *ops);
2914 2915
struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
						  size_t size);
2916 2917
struct drm_i915_gem_object *i915_gem_object_create_from_data(
		struct drm_device *dev, const void *data, size_t size);
2918
void i915_gem_free_object(struct drm_gem_object *obj);
B
Ben Widawsky 已提交
2919
void i915_gem_vma_destroy(struct i915_vma *vma);
2920

2921 2922 2923 2924 2925 2926 2927
/* Flags used by pin/bind&friends. */
#define PIN_MAPPABLE	(1<<0)
#define PIN_NONBLOCK	(1<<1)
#define PIN_GLOBAL	(1<<2)
#define PIN_OFFSET_BIAS	(1<<3)
#define PIN_USER	(1<<4)
#define PIN_UPDATE	(1<<5)
2928 2929
#define PIN_ZONE_4G	(1<<6)
#define PIN_HIGH	(1<<7)
2930
#define PIN_OFFSET_FIXED	(1<<8)
2931
#define PIN_OFFSET_MASK (~4095)
2932 2933 2934 2935 2936 2937 2938 2939 2940 2941
int __must_check
i915_gem_object_pin(struct drm_i915_gem_object *obj,
		    struct i915_address_space *vm,
		    uint32_t alignment,
		    uint64_t flags);
int __must_check
i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
			 const struct i915_ggtt_view *view,
			 uint32_t alignment,
			 uint64_t flags);
2942 2943 2944

int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
		  u32 flags);
2945
void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
2946
int __must_check i915_vma_unbind(struct i915_vma *vma);
2947 2948 2949 2950 2951
/*
 * BEWARE: Do not use the function below unless you can _absolutely_
 * _guarantee_ VMA in question is _not in use_ anywhere.
 */
int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
2952
int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2953
void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2954
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2955

2956 2957 2958
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
				    int *needs_clflush);

2959
int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2960 2961

static inline int __sg_page_count(struct scatterlist *sg)
2962
{
2963 2964
	return sg->length >> PAGE_SHIFT;
}
2965

2966 2967 2968
struct page *
i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);

2969 2970
static inline struct page *
i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2971
{
2972 2973
	if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
		return NULL;
2974

2975 2976 2977 2978
	if (n < obj->get_page.last) {
		obj->get_page.sg = obj->pages->sgl;
		obj->get_page.last = 0;
	}
2979

2980 2981 2982 2983 2984
	while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
		obj->get_page.last += __sg_page_count(obj->get_page.sg++);
		if (unlikely(sg_is_chain(obj->get_page.sg)))
			obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
	}
2985

2986
	return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2987
}
2988

2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999
static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
{
	BUG_ON(obj->pages == NULL);
	obj->pages_pin_count++;
}
static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
{
	BUG_ON(obj->pages_pin_count == 0);
	obj->pages_pin_count--;
}

3000
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3001
int i915_gem_object_sync(struct drm_i915_gem_object *obj,
3002 3003
			 struct intel_engine_cs *to,
			 struct drm_i915_gem_request **to_req);
B
Ben Widawsky 已提交
3004
void i915_vma_move_to_active(struct i915_vma *vma,
3005
			     struct drm_i915_gem_request *req);
3006 3007 3008
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
3009 3010
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
		      uint32_t handle, uint64_t *offset);
3011 3012 3013 3014 3015 3016 3017 3018 3019
/**
 * Returns true if seq1 is later than seq2.
 */
static inline bool
i915_seqno_passed(uint32_t seq1, uint32_t seq2)
{
	return (int32_t)(seq1 - seq2) >= 0;
}

3020 3021 3022 3023 3024 3025 3026
static inline bool i915_gem_request_started(struct drm_i915_gem_request *req,
					   bool lazy_coherency)
{
	u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
	return i915_seqno_passed(seqno, req->previous_seqno);
}

3027 3028 3029
static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
					      bool lazy_coherency)
{
3030
	u32 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
3031 3032 3033
	return i915_seqno_passed(seqno, req->seqno);
}

3034 3035
int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3036

3037
struct drm_i915_gem_request *
3038
i915_gem_find_active_request(struct intel_engine_cs *ring);
3039

3040
bool i915_gem_retire_requests(struct drm_device *dev);
3041
void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
3042
int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
3043
				      bool interruptible);
3044

3045 3046 3047
static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
{
	return unlikely(atomic_read(&error->reset_counter)
M
Mika Kuoppala 已提交
3048
			& (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
3049 3050 3051 3052
}

static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
{
M
Mika Kuoppala 已提交
3053 3054 3055 3056 3057 3058
	return atomic_read(&error->reset_counter) & I915_WEDGED;
}

static inline u32 i915_reset_count(struct i915_gpu_error *error)
{
	return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
3059
}
3060

3061 3062 3063 3064 3065 3066 3067 3068 3069 3070 3071 3072
static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
{
	return dev_priv->gpu_error.stop_rings == 0 ||
		dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
}

static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
{
	return dev_priv->gpu_error.stop_rings == 0 ||
		dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
}

3073
void i915_gem_reset(struct drm_device *dev);
3074
bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3075
int __must_check i915_gem_init(struct drm_device *dev);
3076
int i915_gem_init_rings(struct drm_device *dev);
3077
int __must_check i915_gem_init_hw(struct drm_device *dev);
3078
int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
3079
void i915_gem_init_swizzling(struct drm_device *dev);
3080
void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
3081
int __must_check i915_gpu_idle(struct drm_device *dev);
3082
int __must_check i915_gem_suspend(struct drm_device *dev);
3083
void __i915_add_request(struct drm_i915_gem_request *req,
3084 3085
			struct drm_i915_gem_object *batch_obj,
			bool flush_caches);
3086
#define i915_add_request(req) \
3087
	__i915_add_request(req, NULL, true)
3088
#define i915_add_request_no_flush(req) \
3089
	__i915_add_request(req, NULL, false)
3090
int __i915_wait_request(struct drm_i915_gem_request *req,
3091 3092 3093
			unsigned reset_counter,
			bool interruptible,
			s64 *timeout,
3094
			struct intel_rps_client *rps);
3095
int __must_check i915_wait_request(struct drm_i915_gem_request *req);
3096
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3097
int __must_check
3098 3099 3100
i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
			       bool readonly);
int __must_check
3101 3102 3103
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
				  bool write);
int __must_check
3104 3105
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
int __must_check
3106 3107
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
3108 3109 3110
				     const struct i915_ggtt_view *view);
void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
					      const struct i915_ggtt_view *view);
3111
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3112
				int align);
3113
int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3114
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3115

3116 3117
uint32_t
i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3118
uint32_t
3119 3120
i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
			    int tiling_mode, bool fenced);
3121

3122 3123 3124
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);

3125 3126 3127 3128 3129 3130
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
				struct dma_buf *dma_buf);

struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
				struct drm_gem_object *gem_obj, int flags);

3131 3132 3133 3134 3135
u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
				  const struct i915_ggtt_view *view);
u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
			struct i915_address_space *vm);
static inline u64
3136
i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3137
{
3138
	return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3139
}
3140

3141
bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3142
bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3143
				  const struct i915_ggtt_view *view);
3144
bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3145
			struct i915_address_space *vm);
3146

3147 3148
unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
				struct i915_address_space *vm);
3149
struct i915_vma *
3150 3151 3152 3153 3154
i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
		    struct i915_address_space *vm);
struct i915_vma *
i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
			  const struct i915_ggtt_view *view);
3155

3156 3157
struct i915_vma *
i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3158 3159 3160 3161
				  struct i915_address_space *vm);
struct i915_vma *
i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
				       const struct i915_ggtt_view *view);
3162

3163 3164 3165 3166
static inline struct i915_vma *
i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
{
	return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
B
Ben Widawsky 已提交
3167
}
3168
bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3169

3170
/* Some GGTT VM helpers */
3171
#define i915_obj_to_ggtt(obj) \
3172 3173
	(&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)

3174 3175 3176 3177 3178 3179 3180 3181
static inline struct i915_hw_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space *vm)
{
	WARN_ON(i915_is_ggtt(vm));
	return container_of(vm, struct i915_hw_ppgtt, base);
}


3182 3183
static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
{
3184
	return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3185 3186 3187 3188 3189
}

static inline unsigned long
i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
{
3190
	return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
3191
}
B
Ben Widawsky 已提交
3192 3193 3194 3195

static inline int __must_check
i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
		      uint32_t alignment,
3196
		      unsigned flags)
B
Ben Widawsky 已提交
3197
{
3198 3199
	return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
				   alignment, flags | PIN_GLOBAL);
B
Ben Widawsky 已提交
3200
}
3201

3202 3203 3204 3205 3206 3207
static inline int
i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
{
	return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
}

3208 3209 3210 3211 3212 3213 3214
void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
				     const struct i915_ggtt_view *view);
static inline void
i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
{
	i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
}
3215

3216 3217 3218 3219 3220 3221 3222 3223 3224
/* i915_gem_fence.c */
int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);

bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);

void i915_gem_restore_fences(struct drm_device *dev);

3225 3226 3227 3228
void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);

3229
/* i915_gem_context.c */
3230
int __must_check i915_gem_context_init(struct drm_device *dev);
3231
void i915_gem_context_fini(struct drm_device *dev);
3232
void i915_gem_context_reset(struct drm_device *dev);
3233
int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3234
int i915_gem_context_enable(struct drm_i915_gem_request *req);
3235
void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3236
int i915_switch_context(struct drm_i915_gem_request *req);
3237
struct intel_context *
3238
i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3239
void i915_gem_context_free(struct kref *ctx_ref);
3240 3241
struct drm_i915_gem_object *
i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3242
static inline void i915_gem_context_reference(struct intel_context *ctx)
3243
{
3244
	kref_get(&ctx->ref);
3245 3246
}

3247
static inline void i915_gem_context_unreference(struct intel_context *ctx)
3248
{
3249
	kref_put(&ctx->ref, i915_gem_context_free);
3250 3251
}

3252
static inline bool i915_gem_context_is_default(const struct intel_context *c)
3253
{
3254
	return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3255 3256
}

3257 3258 3259 3260
int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
				  struct drm_file *file);
int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
				   struct drm_file *file);
3261 3262 3263 3264
int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file_priv);
int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file_priv);
3265

3266 3267 3268 3269 3270 3271
/* i915_gem_evict.c */
int __must_check i915_gem_evict_something(struct drm_device *dev,
					  struct i915_address_space *vm,
					  int min_size,
					  unsigned alignment,
					  unsigned cache_level,
3272 3273
					  unsigned long start,
					  unsigned long end,
3274
					  unsigned flags);
3275
int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3276
int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3277

3278
/* belongs in i915_gem_gtt.h */
3279
static inline void i915_gem_chipset_flush(struct drm_device *dev)
3280 3281 3282 3283
{
	if (INTEL_INFO(dev)->gen < 6)
		intel_gtt_chipset_flush();
}
3284

3285
/* i915_gem_stolen.c */
3286 3287 3288
int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
				struct drm_mm_node *node, u64 size,
				unsigned alignment);
3289 3290 3291 3292
int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
					 struct drm_mm_node *node, u64 size,
					 unsigned alignment, u64 start,
					 u64 end);
3293 3294
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
				 struct drm_mm_node *node);
3295 3296
int i915_gem_init_stolen(struct drm_device *dev);
void i915_gem_cleanup_stolen(struct drm_device *dev);
3297 3298
struct drm_i915_gem_object *
i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3299 3300 3301 3302 3303
struct drm_i915_gem_object *
i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
					       u32 stolen_offset,
					       u32 gtt_offset,
					       u32 size);
3304

3305 3306
/* i915_gem_shrinker.c */
unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3307
			      unsigned long target,
3308 3309 3310 3311
			      unsigned flags);
#define I915_SHRINK_PURGEABLE 0x1
#define I915_SHRINK_UNBOUND 0x2
#define I915_SHRINK_BOUND 0x4
3312
#define I915_SHRINK_ACTIVE 0x8
3313 3314
unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3315
void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3316 3317


3318
/* i915_gem_tiling.c */
3319
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3320
{
3321
	struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3322 3323 3324 3325 3326

	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
		obj->tiling_mode != I915_TILING_NONE;
}

3327
/* i915_gem_debug.c */
3328 3329
#if WATCH_LISTS
int i915_verify_lists(struct drm_device *dev);
3330
#else
3331
#define i915_verify_lists(dev) 0
3332
#endif
L
Linus Torvalds 已提交
3333

3334
/* i915_debugfs.c */
3335 3336
int i915_debugfs_init(struct drm_minor *minor);
void i915_debugfs_cleanup(struct drm_minor *minor);
3337
#ifdef CONFIG_DEBUG_FS
J
Jani Nikula 已提交
3338
int i915_debugfs_connector_add(struct drm_connector *connector);
3339 3340
void intel_display_crc_init(struct drm_device *dev);
#else
3341 3342
static inline int i915_debugfs_connector_add(struct drm_connector *connector)
{ return 0; }
3343
static inline void intel_display_crc_init(struct drm_device *dev) {}
3344
#endif
3345 3346

/* i915_gpu_error.c */
3347 3348
__printf(2, 3)
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3349 3350
int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
			    const struct i915_error_state_file_priv *error);
3351
int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3352
			      struct drm_i915_private *i915,
3353 3354 3355 3356 3357 3358
			      size_t count, loff_t pos);
static inline void i915_error_state_buf_release(
	struct drm_i915_error_state_buf *eb)
{
	kfree(eb->buf);
}
3359 3360
void i915_capture_error_state(struct drm_device *dev, bool wedge,
			      const char *error_msg);
3361 3362 3363 3364 3365 3366
void i915_error_state_get(struct drm_device *dev,
			  struct i915_error_state_file_priv *error_priv);
void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
void i915_destroy_error_state(struct drm_device *dev);

void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3367
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3368

3369
/* i915_cmd_parser.c */
3370
int i915_cmd_parser_get_version(void);
3371 3372 3373 3374
int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
int i915_parse_cmds(struct intel_engine_cs *ring,
3375
		    struct drm_i915_gem_object *batch_obj,
3376
		    struct drm_i915_gem_object *shadow_batch_obj,
3377
		    u32 batch_start_offset,
3378
		    u32 batch_len,
3379 3380
		    bool is_master);

3381 3382 3383
/* i915_suspend.c */
extern int i915_save_state(struct drm_device *dev);
extern int i915_restore_state(struct drm_device *dev);
3384

B
Ben Widawsky 已提交
3385 3386 3387 3388
/* i915_sysfs.c */
void i915_setup_sysfs(struct drm_device *dev_priv);
void i915_teardown_sysfs(struct drm_device *dev_priv);

3389 3390 3391
/* intel_i2c.c */
extern int intel_setup_gmbus(struct drm_device *dev);
extern void intel_teardown_gmbus(struct drm_device *dev);
3392 3393
extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
				     unsigned int pin);
3394

3395 3396
extern struct i2c_adapter *
intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
C
Chris Wilson 已提交
3397 3398
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3399
static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3400 3401 3402
{
	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
}
3403 3404
extern void intel_i2c_reset(struct drm_device *dev);

3405
/* intel_bios.c */
3406
int intel_bios_init(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3407
bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3408

3409
/* intel_opregion.c */
3410
#ifdef CONFIG_ACPI
3411
extern int intel_opregion_setup(struct drm_device *dev);
3412 3413
extern void intel_opregion_init(struct drm_device *dev);
extern void intel_opregion_fini(struct drm_device *dev);
3414
extern void intel_opregion_asle_intr(struct drm_device *dev);
3415 3416
extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
					 bool enable);
3417 3418
extern int intel_opregion_notify_adapter(struct drm_device *dev,
					 pci_power_t state);
3419
#else
3420
static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3421 3422
static inline void intel_opregion_init(struct drm_device *dev) { return; }
static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3423
static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3424 3425 3426 3427 3428
static inline int
intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
{
	return 0;
}
3429 3430 3431 3432 3433
static inline int
intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
{
	return 0;
}
3434
#endif
3435

J
Jesse Barnes 已提交
3436 3437 3438 3439 3440 3441 3442 3443 3444
/* intel_acpi.c */
#ifdef CONFIG_ACPI
extern void intel_register_dsm_handler(void);
extern void intel_unregister_dsm_handler(void);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */

J
Jesse Barnes 已提交
3445
/* modesetting */
3446
extern void intel_modeset_init_hw(struct drm_device *dev);
J
Jesse Barnes 已提交
3447
extern void intel_modeset_init(struct drm_device *dev);
3448
extern void intel_modeset_gem_init(struct drm_device *dev);
J
Jesse Barnes 已提交
3449
extern void intel_modeset_cleanup(struct drm_device *dev);
3450
extern void intel_connector_unregister(struct intel_connector *);
3451
extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3452
extern void intel_display_resume(struct drm_device *dev);
3453
extern void i915_redisable_vga(struct drm_device *dev);
3454
extern void i915_redisable_vga_power_on(struct drm_device *dev);
3455
extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
P
Paulo Zanoni 已提交
3456
extern void intel_init_pch_refclk(struct drm_device *dev);
3457
extern void intel_set_rps(struct drm_device *dev, u8 val);
3458 3459
extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
				  bool enable);
3460
extern void intel_detect_pch(struct drm_device *dev);
B
Ben Widawsky 已提交
3461
extern int intel_enable_rc6(const struct drm_device *dev);
3462

3463
extern bool i915_semaphore_is_enabled(struct drm_device *dev);
B
Ben Widawsky 已提交
3464 3465
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file);
3466 3467
int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
3468

3469 3470
/* overlay */
extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3471 3472
extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
					    struct intel_overlay_error_state *error);
3473 3474

extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3475
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3476 3477
					    struct drm_device *dev,
					    struct intel_display_error_state *error);
3478

3479 3480
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3481 3482

/* intel_sideband.c */
3483 3484
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3485
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3486 3487
u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3488 3489 3490 3491
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3492 3493
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3494 3495
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3496 3497 3498 3499
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		   enum intel_sbi_destination destination);
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		     enum intel_sbi_destination destination);
3500 3501
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3502

3503 3504
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3505

3506 3507 3508 3509 3510 3511 3512 3513 3514 3515 3516 3517 3518
#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

#define I915_READ16(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
#define I915_WRITE16(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
#define I915_READ16_NOTRACE(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
#define I915_WRITE16_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)

#define I915_READ(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
#define I915_WRITE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
#define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
#define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)

3519 3520 3521 3522 3523 3524
/* Be very careful with read/write 64-bit values. On 32-bit machines, they
 * will be implemented using 2 32-bit writes in an arbitrary order with
 * an arbitrary delay between them. This can cause the hardware to
 * act upon the intermediate value, possibly leading to corruption and
 * machine death. You have been warned.
 */
3525 3526
#define I915_WRITE64(reg, val)	dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
#define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3527

3528
#define I915_READ64_2x32(lower_reg, upper_reg) ({			\
3529 3530
	u32 upper, lower, old_upper, loop = 0;				\
	upper = I915_READ(upper_reg);					\
3531
	do {								\
3532
		old_upper = upper;					\
3533
		lower = I915_READ(lower_reg);				\
3534 3535
		upper = I915_READ(upper_reg);				\
	} while (upper != old_upper && loop++ < 2);			\
3536
	(u64)upper << 32 | lower; })
3537

3538 3539 3540
#define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)

3541 3542
#define __raw_read(x, s) \
static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3543
					     i915_reg_t reg) \
3544
{ \
3545
	return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3546 3547 3548 3549
}

#define __raw_write(x, s) \
static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3550
				       i915_reg_t reg, uint##x##_t val) \
3551
{ \
3552
	write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3553 3554 3555 3556 3557 3558 3559 3560 3561 3562 3563 3564 3565 3566
}
__raw_read(8, b)
__raw_read(16, w)
__raw_read(32, l)
__raw_read(64, q)

__raw_write(8, b)
__raw_write(16, w)
__raw_write(32, l)
__raw_write(64, q)

#undef __raw_read
#undef __raw_write

3567 3568 3569 3570 3571 3572 3573
/* These are untraced mmio-accessors that are only valid to be used inside
 * criticial sections inside IRQ handlers where forcewake is explicitly
 * controlled.
 * Think twice, and think again, before using these.
 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
 * intel_uncore_forcewake_irqunlock().
 */
3574 3575
#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3576 3577
#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)

3578 3579 3580 3581
/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
#define INTEL_BROADCAST_RGB_FULL 1
#define INTEL_BROADCAST_RGB_LIMITED 2
3582

3583
static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3584
{
3585
	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3586
		return VLV_VGACNTRL;
3587 3588
	else if (INTEL_INFO(dev)->gen >= 5)
		return CPU_VGACNTRL;
3589 3590 3591 3592
	else
		return VGACNTRL;
}

V
Ville Syrjälä 已提交
3593 3594 3595 3596 3597
static inline void __user *to_user_ptr(u64 address)
{
	return (void __user *)(uintptr_t)address;
}

3598 3599 3600 3601 3602 3603 3604
static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
{
	unsigned long j = msecs_to_jiffies(m);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3605 3606 3607 3608 3609
static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
{
        return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
}

3610 3611 3612 3613 3614 3615 3616 3617
static inline unsigned long
timespec_to_jiffies_timeout(const struct timespec *value)
{
	unsigned long j = timespec_to_jiffies(value);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3618 3619 3620 3621 3622 3623 3624 3625 3626
/*
 * If you need to wait X milliseconds between events A and B, but event B
 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
 * when event A happened, then just before event B you call this function and
 * pass the timestamp as the first argument, and X as the second argument.
 */
static inline void
wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
{
3627
	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3628 3629 3630 3631 3632 3633 3634 3635 3636 3637

	/*
	 * Don't re-read the value of "jiffies" every time since it may change
	 * behind our back and break the math.
	 */
	tmp_jiffies = jiffies;
	target_jiffies = timestamp_jiffies +
			 msecs_to_jiffies_timeout(to_wait_ms);

	if (time_after(target_jiffies, tmp_jiffies)) {
3638 3639 3640 3641
		remaining_jiffies = target_jiffies - tmp_jiffies;
		while (remaining_jiffies)
			remaining_jiffies =
			    schedule_timeout_uninterruptible(remaining_jiffies);
3642 3643 3644
	}
}

3645 3646 3647 3648 3649 3650 3651
static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
				      struct drm_i915_gem_request *req)
{
	if (ring->trace_irq_req == NULL && ring->irq_get(ring))
		i915_gem_request_assign(&ring->trace_irq_req, req);
}

L
Linus Torvalds 已提交
3652
#endif