i915_drv.h 119.0 KB
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/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#ifndef _I915_DRV_H_
#define _I915_DRV_H_

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#include <uapi/drm/i915_drm.h>
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#include <uapi/drm/drm_fourcc.h>
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#include <linux/io-mapping.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/backlight.h>
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#include <linux/hashtable.h>
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#include <linux/intel-iommu.h>
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#include <linux/kref.h>
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#include <linux/pm_qos.h>
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#include <linux/shmem_fs.h>

#include <drm/drmP.h>
#include <drm/intel-gtt.h>
#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
#include <drm/drm_gem.h>
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#include <drm/drm_auth.h>
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#include "i915_params.h"
#include "i915_reg.h"

#include "intel_bios.h"
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#include "intel_dpll_mgr.h"
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#include "intel_guc.h"
#include "intel_lrc.h"
#include "intel_ringbuffer.h"

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#include "i915_gem.h"
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#include "i915_gem_gtt.h"
#include "i915_gem_render_state.h"
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#include "i915_gem_request.h"
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#include "intel_gvt.h"

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/* General customization:
 */

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
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#define DRIVER_DATE		"20160902"
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#undef WARN_ON
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/* Many gcc seem to no see through this and fall over :( */
#if 0
#define WARN_ON(x) ({ \
	bool __i915_warn_cond = (x); \
	if (__builtin_constant_p(__i915_warn_cond)) \
		BUILD_BUG_ON(__i915_warn_cond); \
	WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
#else
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#define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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#endif

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#undef WARN_ON_ONCE
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#define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
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#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
			     (long) (x), __func__);
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/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 * which may not necessarily be a user visible problem.  This will either
 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 * enable distros and users to tailor their preferred amount of i915 abrt
 * spam.
 */
#define I915_STATE_WARN(condition, format...) ({			\
	int __ret_warn_on = !!(condition);				\
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	if (unlikely(__ret_warn_on))					\
		if (!WARN(i915.verbose_state_checks, format))		\
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			DRM_ERROR(format);				\
	unlikely(__ret_warn_on);					\
})

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#define I915_STATE_WARN_ON(x)						\
	I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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bool __i915_inject_load_failure(const char *func, int line);
#define i915_inject_load_failure() \
	__i915_inject_load_failure(__func__, __LINE__)

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static inline const char *yesno(bool v)
{
	return v ? "yes" : "no";
}

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static inline const char *onoff(bool v)
{
	return v ? "on" : "off";
}

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enum pipe {
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	INVALID_PIPE = -1,
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	PIPE_A = 0,
	PIPE_B,
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	PIPE_C,
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	_PIPE_EDP,
	I915_MAX_PIPES = _PIPE_EDP
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};
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#define pipe_name(p) ((p) + 'A')
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enum transcoder {
	TRANSCODER_A = 0,
	TRANSCODER_B,
	TRANSCODER_C,
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	TRANSCODER_EDP,
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	TRANSCODER_DSI_A,
	TRANSCODER_DSI_C,
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	I915_MAX_TRANSCODERS
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};
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static inline const char *transcoder_name(enum transcoder transcoder)
{
	switch (transcoder) {
	case TRANSCODER_A:
		return "A";
	case TRANSCODER_B:
		return "B";
	case TRANSCODER_C:
		return "C";
	case TRANSCODER_EDP:
		return "EDP";
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	case TRANSCODER_DSI_A:
		return "DSI A";
	case TRANSCODER_DSI_C:
		return "DSI C";
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	default:
		return "<invalid>";
	}
}
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static inline bool transcoder_is_dsi(enum transcoder transcoder)
{
	return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
}

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/*
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 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 * number of planes per CRTC.  Not all platforms really have this many planes,
 * which means some arrays of size I915_MAX_PLANES may have unused entries
 * between the topmost sprite plane and the cursor plane.
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 */
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enum plane {
	PLANE_A = 0,
	PLANE_B,
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	PLANE_C,
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	PLANE_CURSOR,
	I915_MAX_PLANES,
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};
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#define plane_name(p) ((p) + 'A')
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#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
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enum port {
	PORT_A = 0,
	PORT_B,
	PORT_C,
	PORT_D,
	PORT_E,
	I915_MAX_PORTS
};
#define port_name(p) ((p) + 'A')

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#define I915_NUM_PHYS_VLV 2
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enum dpio_channel {
	DPIO_CH0,
	DPIO_CH1
};

enum dpio_phy {
	DPIO_PHY0,
	DPIO_PHY1
};

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enum intel_display_power_domain {
	POWER_DOMAIN_PIPE_A,
	POWER_DOMAIN_PIPE_B,
	POWER_DOMAIN_PIPE_C,
	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
	POWER_DOMAIN_TRANSCODER_A,
	POWER_DOMAIN_TRANSCODER_B,
	POWER_DOMAIN_TRANSCODER_C,
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	POWER_DOMAIN_TRANSCODER_EDP,
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	POWER_DOMAIN_TRANSCODER_DSI_A,
	POWER_DOMAIN_TRANSCODER_DSI_C,
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	POWER_DOMAIN_PORT_DDI_A_LANES,
	POWER_DOMAIN_PORT_DDI_B_LANES,
	POWER_DOMAIN_PORT_DDI_C_LANES,
	POWER_DOMAIN_PORT_DDI_D_LANES,
	POWER_DOMAIN_PORT_DDI_E_LANES,
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	POWER_DOMAIN_PORT_DSI,
	POWER_DOMAIN_PORT_CRT,
	POWER_DOMAIN_PORT_OTHER,
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	POWER_DOMAIN_VGA,
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	POWER_DOMAIN_AUDIO,
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	POWER_DOMAIN_PLLS,
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	POWER_DOMAIN_AUX_A,
	POWER_DOMAIN_AUX_B,
	POWER_DOMAIN_AUX_C,
	POWER_DOMAIN_AUX_D,
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	POWER_DOMAIN_GMBUS,
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	POWER_DOMAIN_MODESET,
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	POWER_DOMAIN_INIT,
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	POWER_DOMAIN_NUM,
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};

#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
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#define POWER_DOMAIN_TRANSCODER(tran) \
	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
	 (tran) + POWER_DOMAIN_TRANSCODER_A)
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enum hpd_pin {
	HPD_NONE = 0,
	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
	HPD_CRT,
	HPD_SDVO_B,
	HPD_SDVO_C,
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	HPD_PORT_A,
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	HPD_PORT_B,
	HPD_PORT_C,
	HPD_PORT_D,
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	HPD_PORT_E,
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	HPD_NUM_PINS
};

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#define for_each_hpd_pin(__pin) \
	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)

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struct i915_hotplug {
	struct work_struct hotplug_work;

	struct {
		unsigned long last_jiffies;
		int count;
		enum {
			HPD_ENABLED = 0,
			HPD_DISABLED = 1,
			HPD_MARK_DISABLED = 2
		} state;
	} stats[HPD_NUM_PINS];
	u32 event_bits;
	struct delayed_work reenable_work;

	struct intel_digital_port *irq_port[I915_MAX_PORTS];
	u32 long_port_mask;
	u32 short_port_mask;
	struct work_struct dig_port_work;

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	struct work_struct poll_init_work;
	bool poll_enabled;

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	/*
	 * if we get a HPD irq from DP and a HPD irq from non-DP
	 * the non-DP HPD could block the workqueue on a mode config
	 * mutex getting, that userspace may have taken. However
	 * userspace is waiting on the DP workqueue to run which is
	 * blocked behind the non-DP one.
	 */
	struct workqueue_struct *dp_wq;
};

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#define I915_GEM_GPU_DOMAINS \
	(I915_GEM_DOMAIN_RENDER | \
	 I915_GEM_DOMAIN_SAMPLER | \
	 I915_GEM_DOMAIN_COMMAND | \
	 I915_GEM_DOMAIN_INSTRUCTION | \
	 I915_GEM_DOMAIN_VERTEX)
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#define for_each_pipe(__dev_priv, __p) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
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#define for_each_pipe_masked(__dev_priv, __p, __mask) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
		for_each_if ((__mask) & (1 << (__p)))
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#define for_each_plane(__dev_priv, __pipe, __p)				\
	for ((__p) = 0;							\
	     (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;	\
	     (__p)++)
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#define for_each_sprite(__dev_priv, __p, __s)				\
	for ((__s) = 0;							\
	     (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];	\
	     (__s)++)
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#define for_each_port_masked(__port, __ports_mask) \
	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	\
		for_each_if ((__ports_mask) & (1 << (__port)))

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#define for_each_crtc(dev, crtc) \
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	list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
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#define for_each_intel_plane(dev, intel_plane) \
	list_for_each_entry(intel_plane,			\
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			    &(dev)->mode_config.plane_list,	\
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			    base.head)

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#define for_each_intel_plane_mask(dev, intel_plane, plane_mask)		\
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	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
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			    base.head)					\
		for_each_if ((plane_mask) &				\
			     (1 << drm_plane_index(&intel_plane->base)))

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#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)	\
	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
			    base.head)					\
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		for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
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#define for_each_intel_crtc(dev, intel_crtc)				\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)
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#define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)		\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)					\
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		for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))

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#define for_each_intel_encoder(dev, intel_encoder)		\
	list_for_each_entry(intel_encoder,			\
			    &(dev)->mode_config.encoder_list,	\
			    base.head)

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#define for_each_intel_connector(dev, intel_connector)		\
	list_for_each_entry(intel_connector,			\
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			    &(dev)->mode_config.connector_list,	\
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			    base.head)

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#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
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		for_each_if ((intel_encoder)->base.crtc == (__crtc))
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#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
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		for_each_if ((intel_connector)->base.encoder == (__encoder))
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#define for_each_power_domain(domain, mask)				\
	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
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		for_each_if ((1 << (domain)) & (mask))
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struct drm_i915_private;
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struct i915_mm_struct;
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struct i915_mmu_object;
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struct drm_i915_file_private {
	struct drm_i915_private *dev_priv;
	struct drm_file *file;

	struct {
		spinlock_t lock;
		struct list_head request_list;
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/* 20ms is a fairly arbitrary limit (greater than the average frame time)
 * chosen to prevent the CPU getting more than a frame ahead of the GPU
 * (when using lax throttling for the frontbuffer). We also use it to
 * offer free GPU waitboosts for severely congested workloads.
 */
#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
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	} mm;
	struct idr context_idr;

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	struct intel_rps_client {
		struct list_head link;
		unsigned boosts;
	} rps;
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	unsigned int bsd_engine;
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};

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/* Used by dp and fdi links */
struct intel_link_m_n {
	uint32_t	tu;
	uint32_t	gmch_m;
	uint32_t	gmch_n;
	uint32_t	link_m;
	uint32_t	link_n;
};

void intel_link_compute_m_n(int bpp, int nlanes,
			    int pixel_clock, int link_clock,
			    struct intel_link_m_n *m_n);

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/* Interface history:
 *
 * 1.1: Original.
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 * 1.2: Add Power Management
 * 1.3: Add vblank support
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 * 1.4: Fix cmdbuffer path, add heap destroy
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 * 1.5: Add vblank pipe configuration
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 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
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 */
#define DRIVER_MAJOR		1
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#define DRIVER_MINOR		6
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#define DRIVER_PATCHLEVEL	0

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struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
struct opregion_asle;

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struct intel_opregion {
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	struct opregion_header *header;
	struct opregion_acpi *acpi;
	struct opregion_swsci *swsci;
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	u32 swsci_gbda_sub_functions;
	u32 swsci_sbcb_sub_functions;
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	struct opregion_asle *asle;
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	void *rvda;
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	const void *vbt;
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	u32 vbt_size;
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	u32 *lid_state;
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	struct work_struct asle_work;
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};
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#define OPREGION_SIZE            (8*1024)
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struct intel_overlay;
struct intel_overlay_error_state;

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struct drm_i915_fence_reg {
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	struct list_head link;
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	struct drm_i915_private *i915;
	struct i915_vma *vma;
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	int pin_count;
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	int id;
	/**
	 * Whether the tiling parameters for the currently
	 * associated fence register have changed. Note that
	 * for the purposes of tracking tiling changes we also
	 * treat the unfenced register, the register slot that
	 * the object occupies whilst it executes a fenced
	 * command (such as BLT on gen2/3), as a "fence".
	 */
	bool dirty;
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};
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struct sdvo_device_mapping {
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	u8 initialized;
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	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
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	u8 i2c_pin;
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	u8 ddc_pin;
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};

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struct intel_connector;
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struct intel_encoder;
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struct intel_crtc_state;
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struct intel_initial_plane_config;
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struct intel_crtc;
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struct intel_limit;
struct dpll;
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struct drm_i915_display_funcs {
	int (*get_display_clock_speed)(struct drm_device *dev);
	int (*get_fifo_size)(struct drm_device *dev, int plane);
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	int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
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	int (*compute_intermediate_wm)(struct drm_device *dev,
				       struct intel_crtc *intel_crtc,
				       struct intel_crtc_state *newstate);
	void (*initial_watermarks)(struct intel_crtc_state *cstate);
	void (*optimize_watermarks)(struct intel_crtc_state *cstate);
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	int (*compute_global_watermarks)(struct drm_atomic_state *state);
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	void (*update_wm)(struct drm_crtc *crtc);
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	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
	void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
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	/* Returns the active state of the crtc, and if the crtc is active,
	 * fills out the pipe-config with the hw state. */
	bool (*get_pipe_config)(struct intel_crtc *,
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				struct intel_crtc_state *);
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	void (*get_initial_plane_config)(struct intel_crtc *,
					 struct intel_initial_plane_config *);
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	int (*crtc_compute_clock)(struct intel_crtc *crtc,
				  struct intel_crtc_state *crtc_state);
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	void (*crtc_enable)(struct intel_crtc_state *pipe_config,
			    struct drm_atomic_state *old_state);
	void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
			     struct drm_atomic_state *old_state);
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	void (*update_crtcs)(struct drm_atomic_state *state,
			     unsigned int *crtc_vblank_mask);
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	void (*audio_codec_enable)(struct drm_connector *connector,
				   struct intel_encoder *encoder,
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				   const struct drm_display_mode *adjusted_mode);
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	void (*audio_codec_disable)(struct intel_encoder *encoder);
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	void (*fdi_link_train)(struct drm_crtc *crtc);
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	void (*init_clock_gating)(struct drm_device *dev);
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	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
			  struct drm_framebuffer *fb,
			  struct drm_i915_gem_object *obj,
			  struct drm_i915_gem_request *req,
			  uint32_t flags);
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	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
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	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
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	void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
	void (*load_luts)(struct drm_crtc_state *crtc_state);
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};

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enum forcewake_domain_id {
	FW_DOMAIN_ID_RENDER = 0,
	FW_DOMAIN_ID_BLITTER,
	FW_DOMAIN_ID_MEDIA,

	FW_DOMAIN_ID_COUNT
};

enum forcewake_domains {
	FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
	FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
	FORCEWAKE_MEDIA	= (1 << FW_DOMAIN_ID_MEDIA),
	FORCEWAKE_ALL = (FORCEWAKE_RENDER |
			 FORCEWAKE_BLITTER |
			 FORCEWAKE_MEDIA)
};

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#define FW_REG_READ  (1)
#define FW_REG_WRITE (2)

enum forcewake_domains
intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
			       i915_reg_t reg, unsigned int op);

565
struct intel_uncore_funcs {
566
	void (*force_wake_get)(struct drm_i915_private *dev_priv,
567
							enum forcewake_domains domains);
568
	void (*force_wake_put)(struct drm_i915_private *dev_priv,
569
							enum forcewake_domains domains);
570

571 572 573 574
	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
575

576
	void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
577
				uint8_t val, bool trace);
578
	void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
579
				uint16_t val, bool trace);
580
	void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
581
				uint32_t val, bool trace);
582 583
};

584 585 586 587 588 589
struct intel_uncore {
	spinlock_t lock; /** lock is also taken in irq contexts. */

	struct intel_uncore_funcs funcs;

	unsigned fifo_count;
590
	enum forcewake_domains fw_domains;
591 592 593

	struct intel_uncore_forcewake_domain {
		struct drm_i915_private *i915;
594
		enum forcewake_domain_id id;
595
		enum forcewake_domains mask;
596
		unsigned wake_count;
597
		struct hrtimer timer;
598
		i915_reg_t reg_set;
599 600
		u32 val_set;
		u32 val_clear;
601 602
		i915_reg_t reg_ack;
		i915_reg_t reg_post;
603
		u32 val_reset;
604
	} fw_domain[FW_DOMAIN_ID_COUNT];
605 606

	int unclaimed_mmio_check;
607 608 609
};

/* Iterate over initialised fw domains */
610 611 612 613 614 615 616 617
#define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
	for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
	     (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
	     (domain__)++) \
		for_each_if ((mask__) & (domain__)->mask)

#define for_each_fw_domain(domain__, dev_priv__) \
	for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
618

619 620 621 622
#define CSR_VERSION(major, minor)	((major) << 16 | (minor))
#define CSR_VERSION_MAJOR(version)	((version) >> 16)
#define CSR_VERSION_MINOR(version)	((version) & 0xffff)

623
struct intel_csr {
624
	struct work_struct work;
625
	const char *fw_path;
626
	uint32_t *dmc_payload;
627
	uint32_t dmc_fw_size;
628
	uint32_t version;
629
	uint32_t mmio_count;
630
	i915_reg_t mmioaddr[8];
631
	uint32_t mmiodata[8];
632
	uint32_t dc_state;
633
	uint32_t allowed_dc_mask;
634 635
};

636 637 638 639 640 641 642 643 644 645 646 647 648
#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
	func(is_mobile) sep \
	func(is_i85x) sep \
	func(is_i915g) sep \
	func(is_i945gm) sep \
	func(is_g33) sep \
	func(need_gfx_hws) sep \
	func(is_g4x) sep \
	func(is_pineview) sep \
	func(is_broadwater) sep \
	func(is_crestline) sep \
	func(is_ivybridge) sep \
	func(is_valleyview) sep \
649
	func(is_cherryview) sep \
650
	func(is_haswell) sep \
651
	func(is_broadwell) sep \
652
	func(is_skylake) sep \
653
	func(is_broxton) sep \
654
	func(is_kabylake) sep \
655
	func(is_preliminary) sep \
656
	func(has_fbc) sep \
657
	func(has_psr) sep \
658
	func(has_runtime_pm) sep \
659
	func(has_csr) sep \
660
	func(has_resource_streamer) sep \
661
	func(has_rc6) sep \
662
	func(has_rc6p) sep \
663
	func(has_dp_mst) sep \
664
	func(has_gmbus_irq) sep \
665
	func(has_hw_contexts) sep \
666 667 668 669 670 671
	func(has_pipe_cxsr) sep \
	func(has_hotplug) sep \
	func(cursor_needs_physical) sep \
	func(has_overlay) sep \
	func(overlay_needs_physical) sep \
	func(supports_tv) sep \
672
	func(has_llc) sep \
673
	func(has_snoop) sep \
674
	func(has_ddi) sep \
675 676
	func(has_fpga_dbg) sep \
	func(has_pooled_eu)
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Daniel Vetter 已提交
677

678 679
#define DEFINE_FLAG(name) u8 name:1
#define SEP_SEMICOLON ;
D
Daniel Vetter 已提交
680

681
struct sseu_dev_info {
682
	u8 slice_mask;
683
	u8 subslice_mask;
684 685
	u8 eu_total;
	u8 eu_per_subslice;
686 687 688 689 690 691
	u8 min_eu_in_pool;
	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
	u8 subslice_7eu[3];
	u8 has_slice_pg:1;
	u8 has_subslice_pg:1;
	u8 has_eu_pg:1;
692 693
};

694 695 696 697 698
static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu)
{
	return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask);
}

699
struct intel_device_info {
700
	u32 display_mmio_offset;
701
	u16 device_id;
702
	u8 num_pipes;
703
	u8 num_sprites[I915_MAX_PIPES];
704
	u8 gen;
705
	u16 gen_mask;
706
	u8 ring_mask; /* Rings supported by the HW */
707
	u8 num_rings;
708
	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
709 710 711 712
	/* Register offsets for the various display pipes and transcoders */
	int pipe_offsets[I915_MAX_TRANSCODERS];
	int trans_offsets[I915_MAX_TRANSCODERS];
	int palette_offsets[I915_MAX_PIPES];
713
	int cursor_offsets[I915_MAX_PIPES];
714 715

	/* Slice/subslice/EU info */
716
	struct sseu_dev_info sseu;
717 718 719 720 721

	struct color_luts {
		u16 degamma_lut_size;
		u16 gamma_lut_size;
	} color;
722 723
};

724 725 726
#undef DEFINE_FLAG
#undef SEP_SEMICOLON

727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760
struct intel_display_error_state;

struct drm_i915_error_state {
	struct kref ref;
	struct timeval time;

	char error_msg[128];
	bool simulated;
	int iommu;
	u32 reset_count;
	u32 suspend_count;
	struct intel_device_info device_info;

	/* Generic register state */
	u32 eir;
	u32 pgtbl_er;
	u32 ier;
	u32 gtier[4];
	u32 ccid;
	u32 derrmr;
	u32 forcewake;
	u32 error; /* gen6+ */
	u32 err_int; /* gen7 */
	u32 fault_data0; /* gen8, gen9 */
	u32 fault_data1; /* gen8, gen9 */
	u32 done_reg;
	u32 gac_eco;
	u32 gam_ecochk;
	u32 gab_ctl;
	u32 gfx_mode;
	u32 extra_instdone[I915_NUM_INSTDONE_REG];
	u64 fence[I915_MAX_NUM_FENCES];
	struct intel_overlay_error_state *overlay;
	struct intel_display_error_state *display;
761
	struct drm_i915_error_object *semaphore;
762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784

	struct drm_i915_error_engine {
		int engine_id;
		/* Software tracked state */
		bool waiting;
		int num_waiters;
		int hangcheck_score;
		enum intel_engine_hangcheck_action hangcheck_action;
		struct i915_address_space *vm;
		int num_requests;

		/* our own tracking of ring head and tail */
		u32 cpu_ring_head;
		u32 cpu_ring_tail;

		u32 last_seqno;
		u32 semaphore_seqno[I915_NUM_ENGINES - 1];

		/* Register state */
		u32 start;
		u32 tail;
		u32 head;
		u32 ctl;
785
		u32 mode;
786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803
		u32 hws;
		u32 ipeir;
		u32 ipehr;
		u32 instdone;
		u32 bbstate;
		u32 instpm;
		u32 instps;
		u32 seqno;
		u64 bbaddr;
		u64 acthd;
		u32 fault_reg;
		u64 faddr;
		u32 rc_psmi; /* sleep state */
		u32 semaphore_mboxes[I915_NUM_ENGINES - 1];

		struct drm_i915_error_object {
			int page_count;
			u64 gtt_offset;
804
			u64 gtt_size;
805 806 807 808 809 810 811
			u32 *pages[0];
		} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;

		struct drm_i915_error_object *wa_ctx;

		struct drm_i915_error_request {
			long jiffies;
812
			pid_t pid;
813 814 815 816 817 818 819 820 821 822 823 824 825 826 827 828 829 830 831 832 833 834 835 836 837 838 839 840 841 842 843 844 845 846 847 848 849 850 851 852 853 854
			u32 seqno;
			u32 head;
			u32 tail;
		} *requests;

		struct drm_i915_error_waiter {
			char comm[TASK_COMM_LEN];
			pid_t pid;
			u32 seqno;
		} *waiters;

		struct {
			u32 gfx_mode;
			union {
				u64 pdp[4];
				u32 pp_dir_base;
			};
		} vm_info;

		pid_t pid;
		char comm[TASK_COMM_LEN];
	} engine[I915_NUM_ENGINES];

	struct drm_i915_error_buffer {
		u32 size;
		u32 name;
		u32 rseqno[I915_NUM_ENGINES], wseqno;
		u64 gtt_offset;
		u32 read_domains;
		u32 write_domain;
		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
		u32 tiling:2;
		u32 dirty:1;
		u32 purgeable:1;
		u32 userptr:1;
		s32 engine:4;
		u32 cache_level:3;
	} *active_bo[I915_NUM_ENGINES], *pinned_bo;
	u32 active_bo_count[I915_NUM_ENGINES], pinned_bo_count;
	struct i915_address_space *active_vm[I915_NUM_ENGINES];
};

855 856
enum i915_cache_level {
	I915_CACHE_NONE = 0,
857 858 859 860 861
	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
			      caches, eg sampler/render caches, and the
			      large Last-Level-Cache. LLC is coherent with
			      the CPU, but L3 is only visible to the GPU. */
862
	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
863 864
};

865 866 867 868 869 870
struct i915_ctx_hang_stats {
	/* This context had batch pending when hang was declared */
	unsigned batch_pending;

	/* This context had batch active when hang was declared */
	unsigned batch_active;
871 872 873 874

	/* Time when this context was last blamed for a GPU reset */
	unsigned long guilty_ts;

875 876 877 878 879
	/* If the contexts causes a second GPU hang within this time,
	 * it is permanently banned from submitting any more work.
	 */
	unsigned long ban_period_seconds;

880 881
	/* This context is banned to submit more work */
	bool banned;
882
};
883 884

/* This must match up with the value previously used for execbuf2.rsvd1. */
885
#define DEFAULT_CONTEXT_HANDLE 0
886

887
/**
888
 * struct i915_gem_context - as the name implies, represents a context.
889 890 891
 * @ref: reference count.
 * @user_handle: userspace tracking identity for this context.
 * @remap_slice: l3 row remapping information.
892 893
 * @flags: context specific flags:
 *         CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
894 895 896 897
 * @file_priv: filp associated with this context (NULL for global default
 *	       context).
 * @hang_stats: information about the role of this context in possible GPU
 *		hangs.
898
 * @ppgtt: virtual memory space used by this context.
899 900 901 902 903 904 905
 * @legacy_hw_ctx: render context backing object and whether it is correctly
 *                initialized (legacy ring submission mechanism only).
 * @link: link in the global list of contexts.
 *
 * Contexts are memory images used by the hardware to store copies of their
 * internal state.
 */
906
struct i915_gem_context {
907
	struct kref ref;
908
	struct drm_i915_private *i915;
909
	struct drm_i915_file_private *file_priv;
910
	struct i915_hw_ppgtt *ppgtt;
911
	struct pid *pid;
912

913 914 915
	struct i915_ctx_hang_stats hang_stats;

	unsigned long flags;
916 917
#define CONTEXT_NO_ZEROMAP		BIT(0)
#define CONTEXT_NO_ERROR_CAPTURE	BIT(1)
918 919 920

	/* Unique identifier for this context, used by the hw for tracking */
	unsigned int hw_id;
921
	u32 user_handle;
922

923 924
	u32 ggtt_alignment;

925
	struct intel_context {
926
		struct i915_vma *state;
927
		struct intel_ring *ring;
928
		uint32_t *lrc_reg_state;
929 930
		u64 lrc_desc;
		int pin_count;
931
		bool initialised;
932
	} engine[I915_NUM_ENGINES];
933
	u32 ring_size;
934
	u32 desc_template;
935
	struct atomic_notifier_head status_notifier;
936
	bool execlists_force_single_submission;
937

938
	struct list_head link;
939 940

	u8 remap_slice;
941
	bool closed:1;
942 943
};

944 945 946 947 948
enum fb_op_origin {
	ORIGIN_GTT,
	ORIGIN_CPU,
	ORIGIN_CS,
	ORIGIN_FLIP,
949
	ORIGIN_DIRTYFB,
950 951
};

952
struct intel_fbc {
P
Paulo Zanoni 已提交
953 954 955
	/* This is always the inner lock when overlapping with struct_mutex and
	 * it's the outer lock when overlapping with stolen_lock. */
	struct mutex lock;
B
Ben Widawsky 已提交
956
	unsigned threshold;
957 958
	unsigned int possible_framebuffer_bits;
	unsigned int busy_bits;
959
	unsigned int visible_pipes_mask;
960
	struct intel_crtc *crtc;
961

962
	struct drm_mm_node compressed_fb;
963 964
	struct drm_mm_node *compressed_llb;

965 966
	bool false_color;

967
	bool enabled;
968
	bool active;
969

970 971 972 973 974 975 976 977 978 979 980 981 982 983 984 985 986 987 988 989 990 991
	struct intel_fbc_state_cache {
		struct {
			unsigned int mode_flags;
			uint32_t hsw_bdw_pixel_rate;
		} crtc;

		struct {
			unsigned int rotation;
			int src_w;
			int src_h;
			bool visible;
		} plane;

		struct {
			u64 ilk_ggtt_offset;
			uint32_t pixel_format;
			unsigned int stride;
			int fence_reg;
			unsigned int tiling_mode;
		} fb;
	} state_cache;

992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005 1006 1007 1008
	struct intel_fbc_reg_params {
		struct {
			enum pipe pipe;
			enum plane plane;
			unsigned int fence_y_offset;
		} crtc;

		struct {
			u64 ggtt_offset;
			uint32_t pixel_format;
			unsigned int stride;
			int fence_reg;
		} fb;

		int cfb_size;
	} params;

1009
	struct intel_fbc_work {
1010
		bool scheduled;
1011
		u32 scheduled_vblank;
1012 1013
		struct work_struct work;
	} work;
1014

1015
	const char *no_fbc_reason;
1016 1017
};

1018 1019 1020 1021 1022 1023 1024 1025 1026 1027 1028 1029 1030 1031 1032
/**
 * HIGH_RR is the highest eDP panel refresh rate read from EDID
 * LOW_RR is the lowest eDP panel refresh rate found from EDID
 * parsing for same resolution.
 */
enum drrs_refresh_rate_type {
	DRRS_HIGH_RR,
	DRRS_LOW_RR,
	DRRS_MAX_RR, /* RR count */
};

enum drrs_support_type {
	DRRS_NOT_SUPPORTED = 0,
	STATIC_DRRS_SUPPORT = 1,
	SEAMLESS_DRRS_SUPPORT = 2
1033 1034
};

1035
struct intel_dp;
1036 1037 1038 1039 1040 1041 1042 1043 1044
struct i915_drrs {
	struct mutex mutex;
	struct delayed_work work;
	struct intel_dp *dp;
	unsigned busy_frontbuffer_bits;
	enum drrs_refresh_rate_type refresh_rate_type;
	enum drrs_support_type type;
};

R
Rodrigo Vivi 已提交
1045
struct i915_psr {
1046
	struct mutex lock;
R
Rodrigo Vivi 已提交
1047 1048
	bool sink_support;
	bool source_ok;
1049
	struct intel_dp *enabled;
1050 1051
	bool active;
	struct delayed_work work;
1052
	unsigned busy_frontbuffer_bits;
1053 1054
	bool psr2_support;
	bool aux_frame_sync;
1055
	bool link_standby;
1056
};
1057

1058
enum intel_pch {
1059
	PCH_NONE = 0,	/* No PCH present */
1060 1061
	PCH_IBX,	/* Ibexpeak PCH */
	PCH_CPT,	/* Cougarpoint PCH */
1062
	PCH_LPT,	/* Lynxpoint PCH */
1063
	PCH_SPT,        /* Sunrisepoint PCH */
1064
	PCH_KBP,        /* Kabypoint PCH */
B
Ben Widawsky 已提交
1065
	PCH_NOP,
1066 1067
};

1068 1069 1070 1071 1072
enum intel_sbi_destination {
	SBI_ICLK,
	SBI_MPHY,
};

1073
#define QUIRK_PIPEA_FORCE (1<<0)
1074
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
1075
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
1076
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
1077
#define QUIRK_PIPEB_FORCE (1<<4)
1078
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1079

1080
struct intel_fbdev;
1081
struct intel_fbc_work;
1082

1083 1084
struct intel_gmbus {
	struct i2c_adapter adapter;
1085
#define GMBUS_FORCE_BIT_RETRY (1U << 31)
1086
	u32 force_bit;
1087
	u32 reg0;
1088
	i915_reg_t gpio_reg;
1089
	struct i2c_algo_bit_data bit_algo;
1090 1091 1092
	struct drm_i915_private *dev_priv;
};

1093
struct i915_suspend_saved_registers {
1094
	u32 saveDSPARB;
J
Jesse Barnes 已提交
1095
	u32 saveFBC_CONTROL;
1096 1097
	u32 saveCACHE_MODE_0;
	u32 saveMI_ARB_STATE;
J
Jesse Barnes 已提交
1098 1099
	u32 saveSWF0[16];
	u32 saveSWF1[16];
1100
	u32 saveSWF3[3];
1101
	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1102
	u32 savePCH_PORT_HOTPLUG;
1103
	u16 saveGCDGMBUS;
1104
};
1105

1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153 1154 1155 1156 1157 1158 1159 1160 1161 1162 1163
struct vlv_s0ix_state {
	/* GAM */
	u32 wr_watermark;
	u32 gfx_prio_ctrl;
	u32 arb_mode;
	u32 gfx_pend_tlb0;
	u32 gfx_pend_tlb1;
	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
	u32 media_max_req_count;
	u32 gfx_max_req_count;
	u32 render_hwsp;
	u32 ecochk;
	u32 bsd_hwsp;
	u32 blt_hwsp;
	u32 tlb_rd_addr;

	/* MBC */
	u32 g3dctl;
	u32 gsckgctl;
	u32 mbctl;

	/* GCP */
	u32 ucgctl1;
	u32 ucgctl3;
	u32 rcgctl1;
	u32 rcgctl2;
	u32 rstctl;
	u32 misccpctl;

	/* GPM */
	u32 gfxpause;
	u32 rpdeuhwtc;
	u32 rpdeuc;
	u32 ecobus;
	u32 pwrdwnupctl;
	u32 rp_down_timeout;
	u32 rp_deucsw;
	u32 rcubmabdtmr;
	u32 rcedata;
	u32 spare2gh;

	/* Display 1 CZ domain */
	u32 gt_imr;
	u32 gt_ier;
	u32 pm_imr;
	u32 pm_ier;
	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

	/* GT SA CZ domain */
	u32 tilectl;
	u32 gt_fifoctl;
	u32 gtlc_wake_ctrl;
	u32 gtlc_survive;
	u32 pmwgicz;

	/* Display 2 CZ domain */
	u32 gu_ctl0;
	u32 gu_ctl1;
1164
	u32 pcbr;
1165 1166 1167
	u32 clock_gate_dis2;
};

1168 1169 1170 1171
struct intel_rps_ei {
	u32 cz_clock;
	u32 render_c0;
	u32 media_c0;
1172 1173
};

1174
struct intel_gen6_power_mgmt {
I
Imre Deak 已提交
1175 1176 1177 1178
	/*
	 * work, interrupts_enabled and pm_iir are protected by
	 * dev_priv->irq_lock
	 */
1179
	struct work_struct work;
I
Imre Deak 已提交
1180
	bool interrupts_enabled;
1181
	u32 pm_iir;
1182

1183 1184
	u32 pm_intr_keep;

1185 1186 1187 1188 1189 1190 1191 1192 1193 1194 1195 1196 1197 1198 1199
	/* Frequencies are stored in potentially platform dependent multiples.
	 * In other words, *_freq needs to be multiplied by X to be interesting.
	 * Soft limits are those which are used for the dynamic reclocking done
	 * by the driver (raise frequencies under heavy loads, and lower for
	 * lighter loads). Hard limits are those imposed by the hardware.
	 *
	 * A distinction is made for overclocking, which is never enabled by
	 * default, and is considered to be above the hard limit if it's
	 * possible at all.
	 */
	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
	u8 min_freq;		/* AKA RPn. Minimum frequency */
1200
	u8 boost_freq;		/* Frequency to request when wait boosting */
1201
	u8 idle_freq;		/* Frequency to request when we are idle */
1202 1203 1204
	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
	u8 rp1_freq;		/* "less than" RP0 power/freqency */
	u8 rp0_freq;		/* Non-overclocked max frequency. */
1205
	u16 gpll_ref_freq;	/* vlv/chv GPLL reference frequency */
1206

1207 1208 1209
	u8 up_threshold; /* Current %busy required to uplock */
	u8 down_threshold; /* Current %busy required to downclock */

1210 1211 1212
	int last_adj;
	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;

1213 1214 1215 1216
	spinlock_t client_lock;
	struct list_head clients;
	bool client_boost;

1217
	bool enabled;
1218
	struct delayed_work autoenable_work;
1219
	unsigned boosts;
1220

1221 1222 1223
	/* manual wa residency calculations */
	struct intel_rps_ei up_ei, down_ei;

1224 1225
	/*
	 * Protects RPS/RC6 register access and PCU communication.
1226 1227 1228
	 * Must be taken after struct_mutex if nested. Note that
	 * this lock may be held for long periods of time when
	 * talking to hw - so only take it when talking to hw!
1229 1230
	 */
	struct mutex hw_lock;
1231 1232
};

D
Daniel Vetter 已提交
1233 1234 1235
/* defined intel_pm.c */
extern spinlock_t mchdev_lock;

1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246
struct intel_ilk_power_mgmt {
	u8 cur_delay;
	u8 min_delay;
	u8 max_delay;
	u8 fmax;
	u8 fstart;

	u64 last_count1;
	unsigned long last_time1;
	unsigned long chipset_power;
	u64 last_count2;
1247
	u64 last_time2;
1248 1249 1250 1251 1252 1253 1254
	unsigned long gfx_power;
	u8 corr;

	int c_m;
	int r_t;
};

1255 1256 1257 1258 1259 1260 1261 1262 1263 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279 1280 1281 1282 1283 1284
struct drm_i915_private;
struct i915_power_well;

struct i915_power_well_ops {
	/*
	 * Synchronize the well's hw state to match the current sw state, for
	 * example enable/disable it based on the current refcount. Called
	 * during driver init and resume time, possibly after first calling
	 * the enable/disable handlers.
	 */
	void (*sync_hw)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/*
	 * Enable the well and resources that depend on it (for example
	 * interrupts located on the well). Called after the 0->1 refcount
	 * transition.
	 */
	void (*enable)(struct drm_i915_private *dev_priv,
		       struct i915_power_well *power_well);
	/*
	 * Disable the well and resources that depend on it. Called after
	 * the 1->0 refcount transition.
	 */
	void (*disable)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/* Returns the hw enabled state. */
	bool (*is_enabled)(struct drm_i915_private *dev_priv,
			   struct i915_power_well *power_well);
};

1285 1286
/* Power well structure for haswell */
struct i915_power_well {
1287
	const char *name;
1288
	bool always_on;
1289 1290
	/* power well enable/disable usage count */
	int count;
1291 1292
	/* cached hw enabled state */
	bool hw_enabled;
1293
	unsigned long domains;
1294
	unsigned long data;
1295
	const struct i915_power_well_ops *ops;
1296 1297
};

1298
struct i915_power_domains {
1299 1300 1301 1302 1303
	/*
	 * Power wells needed for initialization at driver init and suspend
	 * time are on. They are kept on until after the first modeset.
	 */
	bool init_power_on;
1304
	bool initializing;
1305
	int power_well_count;
1306

1307
	struct mutex lock;
1308
	int domain_use_count[POWER_DOMAIN_NUM];
1309
	struct i915_power_well *power_wells;
1310 1311
};

1312
#define MAX_L3_SLICES 2
1313
struct intel_l3_parity {
1314
	u32 *remap_info[MAX_L3_SLICES];
1315
	struct work_struct error_work;
1316
	int which_slice;
1317 1318
};

1319 1320 1321
struct i915_gem_mm {
	/** Memory allocator for GTT stolen memory */
	struct drm_mm stolen;
1322 1323 1324 1325
	/** Protects the usage of the GTT stolen memory allocator. This is
	 * always the inner lock when overlapping with struct_mutex. */
	struct mutex stolen_lock;

1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337 1338 1339 1340 1341
	/** List of all objects in gtt_space. Used to restore gtt
	 * mappings on resume */
	struct list_head bound_list;
	/**
	 * List of objects which are not bound to the GTT (thus
	 * are idle and not used by the GPU) but still have
	 * (presumably uncached) pages still attached.
	 */
	struct list_head unbound_list;

	/** Usable portion of the GTT for GEM */
	unsigned long stolen_base; /* limited to low memory (32-bit) */

	/** PPGTT used for aliasing the PPGTT with the GTT */
	struct i915_hw_ppgtt *aliasing_ppgtt;

1342
	struct notifier_block oom_notifier;
1343
	struct notifier_block vmap_notifier;
1344
	struct shrinker shrinker;
1345 1346 1347 1348 1349 1350 1351 1352 1353 1354

	/** LRU list of objects with fence regs on them. */
	struct list_head fence_list;

	/**
	 * Are we in a non-interruptible section of code like
	 * modesetting?
	 */
	bool interruptible;

1355
	/* the indicator for dispatch video commands on two BSD rings */
1356
	atomic_t bsd_engine_dispatch_index;
1357

1358 1359 1360 1361 1362 1363
	/** Bit 6 swizzling required for X tiling */
	uint32_t bit_6_swizzle_x;
	/** Bit 6 swizzling required for Y tiling */
	uint32_t bit_6_swizzle_y;

	/* accounting, useful for userland debugging */
1364
	spinlock_t object_stat_lock;
1365 1366 1367 1368
	size_t object_memory;
	u32 object_count;
};

1369
struct drm_i915_error_state_buf {
1370
	struct drm_i915_private *i915;
1371 1372 1373 1374 1375 1376 1377 1378
	unsigned bytes;
	unsigned size;
	int err;
	u8 *buf;
	loff_t start;
	loff_t pos;
};

1379 1380 1381 1382 1383
struct i915_error_state_file_priv {
	struct drm_device *dev;
	struct drm_i915_error_state *error;
};

1384 1385 1386 1387
struct i915_gpu_error {
	/* For hangcheck timer */
#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1388 1389 1390
	/* Hang gpu twice in this window and your context gets banned */
#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)

1391
	struct delayed_work hangcheck_work;
1392 1393 1394 1395 1396

	/* For reset and error_state handling. */
	spinlock_t lock;
	/* Protected by the above dev->gpu_error.lock. */
	struct drm_i915_error_state *first_error;
1397 1398 1399

	unsigned long missed_irq_rings;

1400
	/**
M
Mika Kuoppala 已提交
1401
	 * State variable controlling the reset flow and count
1402
	 *
M
Mika Kuoppala 已提交
1403 1404 1405 1406 1407 1408 1409 1410 1411 1412 1413 1414 1415
	 * This is a counter which gets incremented when reset is triggered,
	 * and again when reset has been handled. So odd values (lowest bit set)
	 * means that reset is in progress and even values that
	 * (reset_counter >> 1):th reset was successfully completed.
	 *
	 * If reset is not completed succesfully, the I915_WEDGE bit is
	 * set meaning that hardware is terminally sour and there is no
	 * recovery. All waiters on the reset_queue will be woken when
	 * that happens.
	 *
	 * This counter is used by the wait_seqno code to notice that reset
	 * event happened and it needs to restart the entire ioctl (since most
	 * likely the seqno it waited for won't ever signal anytime soon).
1416 1417 1418 1419
	 *
	 * This is important for lock-free wait paths, where no contended lock
	 * naturally enforces the correct ordering between the bail-out of the
	 * waiter and the gpu reset work code.
1420 1421 1422 1423
	 */
	atomic_t reset_counter;

#define I915_RESET_IN_PROGRESS_FLAG	1
M
Mika Kuoppala 已提交
1424
#define I915_WEDGED			(1 << 31)
1425

1426 1427 1428 1429 1430 1431
	/**
	 * Waitqueue to signal when a hang is detected. Used to for waiters
	 * to release the struct_mutex for the reset to procede.
	 */
	wait_queue_head_t wait_queue;

1432 1433 1434 1435 1436
	/**
	 * Waitqueue to signal when the reset has completed. Used by clients
	 * that wait for dev_priv->mm.wedged to settle.
	 */
	wait_queue_head_t reset_queue;
1437

1438
	/* For missed irq/seqno simulation. */
1439
	unsigned long test_irq_rings;
1440 1441
};

1442 1443 1444 1445 1446 1447
enum modeset_restore {
	MODESET_ON_LID_OPEN,
	MODESET_DONE,
	MODESET_SUSPENDED,
};

1448 1449 1450 1451 1452
#define DP_AUX_A 0x40
#define DP_AUX_B 0x10
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30

X
Xiong Zhang 已提交
1453 1454 1455 1456
#define DDC_PIN_B  0x05
#define DDC_PIN_C  0x04
#define DDC_PIN_D  0x06

1457
struct ddi_vbt_port_info {
1458 1459 1460 1461 1462 1463
	/*
	 * This is an index in the HDMI/DVI DDI buffer translation table.
	 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
	 * populate this field.
	 */
#define HDMI_LEVEL_SHIFT_UNKNOWN	0xff
1464
	uint8_t hdmi_level_shift;
1465 1466 1467 1468

	uint8_t supports_dvi:1;
	uint8_t supports_hdmi:1;
	uint8_t supports_dp:1;
1469 1470

	uint8_t alternate_aux_channel;
X
Xiong Zhang 已提交
1471
	uint8_t alternate_ddc_pin;
1472 1473 1474

	uint8_t dp_boost_level;
	uint8_t hdmi_boost_level;
1475 1476
};

R
Rodrigo Vivi 已提交
1477 1478 1479 1480 1481
enum psr_lines_to_wait {
	PSR_0_LINES_TO_WAIT = 0,
	PSR_1_LINE_TO_WAIT,
	PSR_4_LINES_TO_WAIT,
	PSR_8_LINES_TO_WAIT
1482 1483
};

1484 1485 1486 1487 1488 1489 1490 1491 1492 1493 1494 1495
struct intel_vbt_data {
	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits */
	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int lvds_vbt:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
	unsigned int display_clock_mode:1;
	unsigned int fdi_rx_polarity_inverted:1;
1496
	unsigned int panel_type:4;
1497 1498 1499
	int lvds_ssc_freq;
	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

1500 1501
	enum drrs_support_type drrs_type;

1502 1503 1504 1505 1506
	struct {
		int rate;
		int lanes;
		int preemphasis;
		int vswing;
1507
		bool low_vswing;
1508 1509 1510 1511 1512
		bool initialized;
		bool support;
		int bpp;
		struct edp_power_seq pps;
	} edp;
1513

R
Rodrigo Vivi 已提交
1514 1515 1516 1517 1518 1519 1520 1521 1522
	struct {
		bool full_link;
		bool require_aux_wakeup;
		int idle_frames;
		enum psr_lines_to_wait lines_to_wait;
		int tp1_wakeup_time;
		int tp2_tp3_wakeup_time;
	} psr;

1523 1524
	struct {
		u16 pwm_freq_hz;
1525
		bool present;
1526
		bool active_low_pwm;
1527
		u8 min_brightness;	/* min_brightness/255 of max */
1528
		enum intel_backlight_type type;
1529 1530
	} backlight;

1531 1532 1533
	/* MIPI DSI */
	struct {
		u16 panel_id;
1534 1535 1536 1537 1538
		struct mipi_config *config;
		struct mipi_pps_data *pps;
		u8 seq_version;
		u32 size;
		u8 *data;
1539
		const u8 *sequence[MIPI_SEQ_MAX];
1540 1541
	} dsi;

1542 1543 1544
	int crt_ddc_pin;

	int child_dev_num;
1545
	union child_device_config *child_dev;
1546 1547

	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1548
	struct sdvo_device_mapping sdvo_mappings[2];
1549 1550
};

1551 1552 1553 1554 1555
enum intel_ddb_partitioning {
	INTEL_DDB_PART_1_2,
	INTEL_DDB_PART_5_6, /* IVB+ */
};

1556 1557 1558 1559 1560 1561 1562 1563
struct intel_wm_level {
	bool enable;
	uint32_t pri_val;
	uint32_t spr_val;
	uint32_t cur_val;
	uint32_t fbc_val;
};

1564
struct ilk_wm_values {
1565 1566 1567 1568 1569 1570 1571 1572
	uint32_t wm_pipe[3];
	uint32_t wm_lp[3];
	uint32_t wm_lp_spr[3];
	uint32_t wm_linetime[3];
	bool enable_fbc_wm;
	enum intel_ddb_partitioning partitioning;
};

1573 1574 1575 1576 1577
struct vlv_pipe_wm {
	uint16_t primary;
	uint16_t sprite[2];
	uint8_t cursor;
};
1578

1579 1580 1581 1582
struct vlv_sr_wm {
	uint16_t plane;
	uint8_t cursor;
};
1583

1584 1585 1586
struct vlv_wm_values {
	struct vlv_pipe_wm pipe[3];
	struct vlv_sr_wm sr;
1587 1588 1589 1590 1591
	struct {
		uint8_t cursor;
		uint8_t sprite[2];
		uint8_t primary;
	} ddl[3];
1592 1593
	uint8_t level;
	bool cxsr;
1594 1595
};

1596
struct skl_ddb_entry {
1597
	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
1598 1599 1600 1601
};

static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
{
1602
	return entry->end - entry->start;
1603 1604
}

1605 1606 1607 1608 1609 1610 1611 1612 1613
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
				       const struct skl_ddb_entry *e2)
{
	if (e1->start == e2->start && e1->end == e2->end)
		return true;

	return false;
}

1614
struct skl_ddb_allocation {
1615
	struct skl_ddb_entry pipe[I915_MAX_PIPES];
1616
	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1617
	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1618 1619
};

1620
struct skl_wm_values {
1621
	unsigned dirty_pipes;
1622
	struct skl_ddb_allocation ddb;
1623 1624 1625 1626 1627 1628 1629 1630 1631 1632 1633
	uint32_t wm_linetime[I915_MAX_PIPES];
	uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
	uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
};

struct skl_wm_level {
	bool plane_en[I915_MAX_PLANES];
	uint16_t plane_res_b[I915_MAX_PLANES];
	uint8_t plane_res_l[I915_MAX_PLANES];
};

1634
/*
1635 1636 1637 1638
 * This struct helps tracking the state needed for runtime PM, which puts the
 * device in PCI D3 state. Notice that when this happens, nothing on the
 * graphics device works, even register access, so we don't get interrupts nor
 * anything else.
1639
 *
1640 1641 1642
 * Every piece of our code that needs to actually touch the hardware needs to
 * either call intel_runtime_pm_get or call intel_display_power_get with the
 * appropriate power domain.
1643
 *
1644 1645
 * Our driver uses the autosuspend delay feature, which means we'll only really
 * suspend if we stay with zero refcount for a certain amount of time. The
1646
 * default value is currently very conservative (see intel_runtime_pm_enable), but
1647
 * it can be changed with the standard runtime PM files from sysfs.
1648 1649 1650 1651 1652
 *
 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
 * goes back to false exactly before we reenable the IRQs. We use this variable
 * to check if someone is trying to enable/disable IRQs while they're supposed
 * to be disabled. This shouldn't happen and we'll print some error messages in
1653
 * case it happens.
1654
 *
1655
 * For more, read the Documentation/power/runtime_pm.txt.
1656
 */
1657
struct i915_runtime_pm {
1658
	atomic_t wakeref_count;
1659
	atomic_t atomic_seq;
1660
	bool suspended;
1661
	bool irqs_enabled;
1662 1663
};

1664 1665 1666 1667 1668
enum intel_pipe_crc_source {
	INTEL_PIPE_CRC_SOURCE_NONE,
	INTEL_PIPE_CRC_SOURCE_PLANE1,
	INTEL_PIPE_CRC_SOURCE_PLANE2,
	INTEL_PIPE_CRC_SOURCE_PF,
1669
	INTEL_PIPE_CRC_SOURCE_PIPE,
D
Daniel Vetter 已提交
1670 1671 1672 1673 1674
	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
	INTEL_PIPE_CRC_SOURCE_TV,
	INTEL_PIPE_CRC_SOURCE_DP_B,
	INTEL_PIPE_CRC_SOURCE_DP_C,
	INTEL_PIPE_CRC_SOURCE_DP_D,
1675
	INTEL_PIPE_CRC_SOURCE_AUTO,
1676 1677 1678
	INTEL_PIPE_CRC_SOURCE_MAX,
};

1679
struct intel_pipe_crc_entry {
1680
	uint32_t frame;
1681 1682 1683
	uint32_t crc[5];
};

1684
#define INTEL_PIPE_CRC_ENTRIES_NR	128
1685
struct intel_pipe_crc {
1686 1687
	spinlock_t lock;
	bool opened;		/* exclusive access to the result file */
1688
	struct intel_pipe_crc_entry *entries;
1689
	enum intel_pipe_crc_source source;
1690
	int head, tail;
1691
	wait_queue_head_t wq;
1692 1693
};

1694
struct i915_frontbuffer_tracking {
1695
	spinlock_t lock;
1696 1697 1698 1699 1700 1701 1702 1703 1704

	/*
	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
	 * scheduled flips.
	 */
	unsigned busy_bits;
	unsigned flip_bits;
};

1705
struct i915_wa_reg {
1706
	i915_reg_t addr;
1707 1708 1709 1710 1711
	u32 value;
	/* bitmask representing WA bits */
	u32 mask;
};

1712 1713 1714 1715 1716 1717 1718
/*
 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
 * allowing it for RCS as we don't foresee any requirement of having
 * a whitelist for other engines. When it is really required for
 * other engines then the limit need to be increased.
 */
#define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1719 1720 1721 1722

struct i915_workarounds {
	struct i915_wa_reg reg[I915_MAX_WA_REGS];
	u32 count;
1723
	u32 hw_whitelist_count[I915_NUM_ENGINES];
1724 1725
};

1726 1727 1728 1729
struct i915_virtual_gpu {
	bool active;
};

1730 1731 1732 1733 1734 1735 1736
/* used in computing the new watermarks state */
struct intel_wm_config {
	unsigned int num_pipes_active;
	bool sprites_enabled;
	bool sprites_scaled;
};

1737
struct drm_i915_private {
1738 1739
	struct drm_device drm;

1740
	struct kmem_cache *objects;
1741
	struct kmem_cache *vmas;
1742
	struct kmem_cache *requests;
1743

1744
	const struct intel_device_info info;
1745 1746 1747 1748 1749

	int relative_constants_mode;

	void __iomem *regs;

1750
	struct intel_uncore uncore;
1751

1752 1753
	struct i915_virtual_gpu vgpu;

1754 1755
	struct intel_gvt gvt;

1756 1757
	struct intel_guc guc;

1758 1759
	struct intel_csr csr;

1760
	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1761

1762 1763 1764 1765 1766 1767 1768 1769 1770
	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
	 * controller on different i2c buses. */
	struct mutex gmbus_mutex;

	/**
	 * Base address of the gmbus and gpio block.
	 */
	uint32_t gpio_mmio_base;

1771 1772 1773
	/* MMIO base address for MIPI regs */
	uint32_t mipi_mmio_base;

1774 1775
	uint32_t psr_mmio_base;

1776 1777
	uint32_t pps_mmio_base;

1778 1779
	wait_queue_head_t gmbus_wait_queue;

1780
	struct pci_dev *bridge_dev;
1781
	struct i915_gem_context *kernel_context;
1782
	struct intel_engine_cs engine[I915_NUM_ENGINES];
1783
	struct i915_vma *semaphore;
1784
	u32 next_seqno;
1785

1786
	struct drm_dma_handle *status_page_dmah;
1787 1788 1789 1790 1791
	struct resource mch_res;

	/* protects the irq masks */
	spinlock_t irq_lock;

1792 1793 1794
	/* protects the mmio flip data */
	spinlock_t mmio_flip_lock;

1795 1796
	bool display_irqs_enabled;

1797 1798 1799
	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
	struct pm_qos_request pm_qos;

V
Ville Syrjälä 已提交
1800 1801
	/* Sideband mailbox protection */
	struct mutex sb_lock;
1802 1803

	/** Cached value of IMR to avoid reads in updating the bitfield */
1804 1805 1806 1807
	union {
		u32 irq_mask;
		u32 de_irq_mask[I915_MAX_PIPES];
	};
1808
	u32 gt_irq_mask;
1809
	u32 pm_irq_mask;
1810
	u32 pm_rps_events;
1811
	u32 pipestat_irq_mask[I915_MAX_PIPES];
1812

1813
	struct i915_hotplug hotplug;
1814
	struct intel_fbc fbc;
1815
	struct i915_drrs drrs;
1816
	struct intel_opregion opregion;
1817
	struct intel_vbt_data vbt;
1818

1819 1820
	bool preserve_bios_swizzle;

1821 1822 1823
	/* overlay */
	struct intel_overlay *overlay;

1824
	/* backlight registers and fields in struct intel_panel */
1825
	struct mutex backlight_lock;
1826

1827 1828 1829
	/* LVDS info */
	bool no_aux_handshake;

V
Ville Syrjälä 已提交
1830 1831 1832
	/* protects panel power sequencer state */
	struct mutex pps_mutex;

1833 1834 1835 1836
	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */

	unsigned int fsb_freq, mem_freq, is_ddr3;
1837
	unsigned int skl_preferred_vco_freq;
1838
	unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
M
Mika Kahola 已提交
1839
	unsigned int max_dotclk_freq;
1840
	unsigned int rawclk_freq;
1841
	unsigned int hpll_freq;
1842
	unsigned int czclk_freq;
1843

1844
	struct {
1845
		unsigned int vco, ref;
1846 1847
	} cdclk_pll;

1848 1849 1850 1851 1852 1853 1854
	/**
	 * wq - Driver workqueue for GEM.
	 *
	 * NOTE: Work items scheduled here are not allowed to grab any modeset
	 * locks, for otherwise the flushing done in the pageflip code will
	 * result in deadlocks.
	 */
1855 1856 1857 1858 1859 1860 1861
	struct workqueue_struct *wq;

	/* Display functions */
	struct drm_i915_display_funcs display;

	/* PCH chipset type */
	enum intel_pch pch_type;
1862
	unsigned short pch_id;
1863 1864 1865

	unsigned long quirks;

1866 1867
	enum modeset_restore modeset_restore;
	struct mutex modeset_restore_lock;
1868
	struct drm_atomic_state *modeset_restore_state;
1869
	struct drm_modeset_acquire_ctx reset_ctx;
1870

1871
	struct list_head vm_list; /* Global list of all address spaces */
1872
	struct i915_ggtt ggtt; /* VM representing the global address space */
B
Ben Widawsky 已提交
1873

1874
	struct i915_gem_mm mm;
1875 1876
	DECLARE_HASHTABLE(mm_structs, 7);
	struct mutex mm_lock;
1877

1878 1879 1880 1881 1882 1883 1884
	/* The hw wants to have a stable context identifier for the lifetime
	 * of the context (for OA, PASID, faults, etc). This is limited
	 * in execlists to 21 bits.
	 */
	struct ida context_hw_ida;
#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */

1885 1886
	/* Kernel Modesetting */

1887 1888
	struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
	struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1889 1890
	wait_queue_head_t pending_flip_queue;

1891 1892 1893 1894
#ifdef CONFIG_DEBUG_FS
	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif

1895
	/* dpll and cdclk state is protected by connection_mutex */
D
Daniel Vetter 已提交
1896 1897
	int num_shared_dpll;
	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1898
	const struct intel_dpll_mgr *dpll_mgr;
1899

1900 1901 1902 1903 1904 1905 1906
	/*
	 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
	 * Must be global rather than per dpll, because on some platforms
	 * plls share registers.
	 */
	struct mutex dpll_lock;

1907 1908 1909
	unsigned int active_crtcs;
	unsigned int min_pixclk[I915_MAX_PIPES];

1910
	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1911

1912
	struct i915_workarounds workarounds;
1913

1914 1915
	struct i915_frontbuffer_tracking fb_tracking;

1916
	u16 orig_clock;
1917

1918
	bool mchbar_need_disable;
1919

1920 1921
	struct intel_l3_parity l3_parity;

B
Ben Widawsky 已提交
1922
	/* Cannot be determined by PCIID. You must always read a register. */
1923
	u32 edram_cap;
B
Ben Widawsky 已提交
1924

1925
	/* gen6+ rps state */
1926
	struct intel_gen6_power_mgmt rps;
1927

1928 1929
	/* ilk-only ips/rps state. Everything in here is protected by the global
	 * mchdev_lock in intel_pm.c */
1930
	struct intel_ilk_power_mgmt ips;
1931

1932
	struct i915_power_domains power_domains;
1933

R
Rodrigo Vivi 已提交
1934
	struct i915_psr psr;
1935

1936
	struct i915_gpu_error gpu_error;
1937

1938 1939
	struct drm_i915_gem_object *vlv_pctx;

1940
#ifdef CONFIG_DRM_FBDEV_EMULATION
1941 1942
	/* list of fbdev register on this device */
	struct intel_fbdev *fbdev;
1943
	struct work_struct fbdev_suspend_work;
1944
#endif
1945 1946

	struct drm_property *broadcast_rgb_property;
1947
	struct drm_property *force_audio_property;
1948

I
Imre Deak 已提交
1949
	/* hda/i915 audio component */
1950
	struct i915_audio_component *audio_component;
I
Imre Deak 已提交
1951
	bool audio_component_registered;
1952 1953 1954 1955 1956
	/**
	 * av_mutex - mutex for audio/video sync
	 *
	 */
	struct mutex av_mutex;
I
Imre Deak 已提交
1957

1958
	uint32_t hw_context_size;
1959
	struct list_head context_list;
1960

1961
	u32 fdi_rx_config;
1962

1963
	/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1964
	u32 chv_phy_control;
1965 1966 1967 1968 1969 1970
	/*
	 * Shadows for CHV DPLL_MD regs to keep the state
	 * checker somewhat working in the presence hardware
	 * crappiness (can't read out DPLL_MD for pipes B & C).
	 */
	u32 chv_dpll_md[I915_MAX_PIPES];
1971
	u32 bxt_phy_grc;
1972

1973
	u32 suspend_count;
1974
	bool suspended_to_idle;
1975
	struct i915_suspend_saved_registers regfile;
1976
	struct vlv_s0ix_state vlv_s0ix_state;
1977

1978 1979 1980 1981 1982 1983 1984
	enum {
		I915_SKL_SAGV_UNKNOWN = 0,
		I915_SKL_SAGV_DISABLED,
		I915_SKL_SAGV_ENABLED,
		I915_SKL_SAGV_NOT_CONTROLLED
	} skl_sagv_status;

1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996
	struct {
		/*
		 * Raw watermark latency values:
		 * in 0.1us units for WM0,
		 * in 0.5us units for WM1+.
		 */
		/* primary */
		uint16_t pri_latency[5];
		/* sprite */
		uint16_t spr_latency[5];
		/* cursor */
		uint16_t cur_latency[5];
1997 1998 1999 2000 2001 2002
		/*
		 * Raw watermark memory latency values
		 * for SKL for all 8 levels
		 * in 1us units.
		 */
		uint16_t skl_latency[8];
2003

2004 2005 2006 2007 2008 2009 2010
		/*
		 * The skl_wm_values structure is a bit too big for stack
		 * allocation, so we keep the staging struct where we store
		 * intermediate results here instead.
		 */
		struct skl_wm_values skl_results;

2011
		/* current hardware state */
2012 2013 2014
		union {
			struct ilk_wm_values hw;
			struct skl_wm_values skl_hw;
2015
			struct vlv_wm_values vlv;
2016
		};
2017 2018

		uint8_t max_level;
2019 2020 2021 2022 2023 2024 2025

		/*
		 * Should be held around atomic WM register writing; also
		 * protects * intel_crtc->wm.active and
		 * cstate->wm.need_postvbl_update.
		 */
		struct mutex wm_mutex;
2026 2027 2028 2029 2030 2031 2032

		/*
		 * Set during HW readout of watermarks/DDB.  Some platforms
		 * need to know when we're still using BIOS-provided values
		 * (which we don't fully trust).
		 */
		bool distrust_bios_wm;
2033 2034
	} wm;

2035 2036
	struct i915_runtime_pm pm;

2037 2038
	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
	struct {
2039
		void (*cleanup_engine)(struct intel_engine_cs *engine);
2040 2041 2042 2043 2044 2045 2046 2047 2048 2049 2050 2051 2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067

		/**
		 * Is the GPU currently considered idle, or busy executing
		 * userspace requests? Whilst idle, we allow runtime power
		 * management to power down the hardware and display clocks.
		 * In order to reduce the effect on performance, there
		 * is a slight delay before we do so.
		 */
		unsigned int active_engines;
		bool awake;

		/**
		 * We leave the user IRQ off as much as possible,
		 * but this means that requests will finish and never
		 * be retired once the system goes idle. Set a timer to
		 * fire periodically while the ring is running. When it
		 * fires, go retire requests.
		 */
		struct delayed_work retire_work;

		/**
		 * When we detect an idle GPU, we want to turn on
		 * powersaving features. So once we see that there
		 * are no more requests outstanding and no more
		 * arrive within a small period of time, we fire
		 * off the idle_work.
		 */
		struct delayed_work idle_work;
2068 2069
	} gt;

2070 2071 2072
	/* perform PHY state sanity checks? */
	bool chv_phy_assert[2];

2073 2074
	struct intel_encoder *dig_port_map[I915_MAX_PORTS];

2075 2076 2077 2078
	/*
	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
	 * will be rejected. Instead look for a better place.
	 */
2079
};
L
Linus Torvalds 已提交
2080

2081 2082
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
2083
	return container_of(dev, struct drm_i915_private, drm);
2084 2085
}

2086
static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
I
Imre Deak 已提交
2087
{
2088
	return to_i915(dev_get_drvdata(kdev));
I
Imre Deak 已提交
2089 2090
}

2091 2092 2093 2094 2095
static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
{
	return container_of(guc, struct drm_i915_private, guc);
}

2096 2097 2098 2099 2100 2101
/* Simple iterator over all initialised engines */
#define for_each_engine(engine__, dev_priv__) \
	for ((engine__) = &(dev_priv__)->engine[0]; \
	     (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
	     (engine__)++) \
		for_each_if (intel_engine_initialized(engine__))
2102

2103 2104 2105 2106 2107 2108 2109 2110
/* Iterator with engine_id */
#define for_each_engine_id(engine__, dev_priv__, id__) \
	for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
	     (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
	     (engine__)++) \
		for_each_if (((id__) = (engine__)->id, \
			      intel_engine_initialized(engine__)))

2111 2112 2113 2114 2115 2116
#define __mask_next_bit(mask) ({					\
	int __idx = ffs(mask) - 1;					\
	mask &= ~BIT(__idx);						\
	__idx;								\
})

2117
/* Iterator over subset of engines selected by mask */
2118 2119 2120
#define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \
	for (tmp__ = mask__ & INTEL_INFO(dev_priv__)->ring_mask;	\
	     tmp__ ? (engine__ = &(dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : 0; )
2121

2122 2123 2124 2125 2126 2127 2128
enum hdmi_force_audio {
	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
	HDMI_AUDIO_AUTO,		/* trust EDID */
	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
};

2129
#define I915_GTT_OFFSET_NONE ((u32)-1)
2130

2131
struct drm_i915_gem_object_ops {
2132 2133 2134
	unsigned int flags;
#define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1

2135 2136 2137 2138 2139 2140 2141 2142 2143 2144 2145 2146 2147 2148 2149
	/* Interface between the GEM object and its backing storage.
	 * get_pages() is called once prior to the use of the associated set
	 * of pages before to binding them into the GTT, and put_pages() is
	 * called after we no longer need them. As we expect there to be
	 * associated cost with migrating pages between the backing storage
	 * and making them available for the GPU (e.g. clflush), we may hold
	 * onto the pages after they are no longer referenced by the GPU
	 * in case they may be used again shortly (for example migrating the
	 * pages to a different memory domain within the GTT). put_pages()
	 * will therefore most likely be called when the object itself is
	 * being released or under memory pressure (where we attempt to
	 * reap pages for the shrinker).
	 */
	int (*get_pages)(struct drm_i915_gem_object *);
	void (*put_pages)(struct drm_i915_gem_object *);
2150

2151 2152
	int (*dmabuf_export)(struct drm_i915_gem_object *);
	void (*release)(struct drm_i915_gem_object *);
2153 2154
};

2155 2156
/*
 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2157
 * considered to be the frontbuffer for the given plane interface-wise. This
2158 2159 2160 2161 2162
 * doesn't mean that the hw necessarily already scans it out, but that any
 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
 *
 * We have one bit per pipe and per scanout plane type.
 */
2163 2164
#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2165 2166 2167
#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
#define INTEL_FRONTBUFFER_CURSOR(pipe) \
2168 2169 2170
	(1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
	(1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2171
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2172
	(1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2173
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2174
	(0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2175

2176
struct drm_i915_gem_object {
2177
	struct drm_gem_object base;
2178

2179 2180
	const struct drm_i915_gem_object_ops *ops;

B
Ben Widawsky 已提交
2181 2182 2183
	/** List of VMAs backed by this object */
	struct list_head vma_list;

2184 2185
	/** Stolen memory for this object, instead of being backed by shmem. */
	struct drm_mm_node *stolen;
2186
	struct list_head global_list;
2187

2188 2189
	/** Used in execbuf to temporarily hold a ref */
	struct list_head obj_exec_link;
2190

2191
	struct list_head batch_pool_link;
2192

2193
	unsigned long flags;
2194
	/**
2195 2196 2197
	 * This is set if the object is on the active lists (has pending
	 * rendering and so a non-zero seqno), and is not set if it i s on
	 * inactive (ready to be unbound) list.
2198
	 */
2199 2200 2201 2202
#define I915_BO_ACTIVE_SHIFT 0
#define I915_BO_ACTIVE_MASK ((1 << I915_NUM_ENGINES) - 1)
#define __I915_BO_ACTIVE(bo) \
	((READ_ONCE((bo)->flags) >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK)
2203 2204 2205 2206 2207

	/**
	 * This is set if the object has been written to since last bound
	 * to the GTT
	 */
2208
	unsigned int dirty:1;
2209 2210 2211 2212

	/**
	 * Advice: are the backing pages purgeable?
	 */
2213
	unsigned int madv:2;
2214

2215 2216 2217 2218 2219
	/**
	 * Whether the current gtt mapping needs to be mappable (and isn't just
	 * mappable by accident). Track pin and fault separate for a more
	 * accurate mappable working set.
	 */
2220
	unsigned int fault_mappable:1;
2221

2222 2223 2224 2225 2226
	/*
	 * Is the object to be mapped as read-only to the GPU
	 * Only honoured if hardware has relevant pte bit
	 */
	unsigned long gt_ro:1;
2227
	unsigned int cache_level:3;
2228
	unsigned int cache_dirty:1;
2229

2230
	atomic_t frontbuffer_bits;
2231
	unsigned int frontbuffer_ggtt_origin; /* write once */
2232

2233
	/** Current tiling stride for the object, if it's tiled. */
2234 2235 2236 2237
	unsigned int tiling_and_stride;
#define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */
#define TILING_MASK (FENCE_MINIMUM_STRIDE-1)
#define STRIDE_MASK (~TILING_MASK)
2238

2239 2240
	/** Count of VMA actually bound by this object */
	unsigned int bind_count;
2241 2242
	unsigned int pin_display;

2243
	struct sg_table *pages;
2244
	int pages_pin_count;
2245 2246 2247 2248
	struct get_page {
		struct scatterlist *sg;
		int last;
	} get_page;
2249
	void *mapping;
2250

2251 2252 2253 2254 2255 2256 2257 2258 2259
	/** Breadcrumb of last rendering to the buffer.
	 * There can only be one writer, but we allow for multiple readers.
	 * If there is a writer that necessarily implies that all other
	 * read requests are complete - but we may only be lazily clearing
	 * the read requests. A read request is naturally the most recent
	 * request on a ring, so we may have two different write and read
	 * requests on one ring where the write request is older than the
	 * read request. This allows for the CPU to read from an active
	 * buffer by only waiting for the write to complete.
2260 2261 2262
	 */
	struct i915_gem_active last_read[I915_NUM_ENGINES];
	struct i915_gem_active last_write;
2263

2264 2265 2266
	/** References from framebuffers, locks out tiling changes. */
	unsigned long framebuffer_references;

2267
	/** Record of address bit 17 of each page at last unbind. */
2268
	unsigned long *bit_17;
2269

2270
	union {
2271 2272 2273
		/** for phy allocated objects */
		struct drm_dma_handle *phys_handle;

2274 2275 2276 2277 2278 2279
		struct i915_gem_userptr {
			uintptr_t ptr;
			unsigned read_only :1;
			unsigned workers :4;
#define I915_GEM_USERPTR_MAX_WORKERS 15

2280 2281
			struct i915_mm_struct *mm;
			struct i915_mmu_object *mmu_object;
2282 2283 2284 2285
			struct work_struct *work;
		} userptr;
	};
};
2286 2287 2288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304

static inline struct drm_i915_gem_object *
to_intel_bo(struct drm_gem_object *gem)
{
	/* Assert that to_intel_bo(NULL) == NULL */
	BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base));

	return container_of(gem, struct drm_i915_gem_object, base);
}

static inline struct drm_i915_gem_object *
i915_gem_object_lookup(struct drm_file *file, u32 handle)
{
	return to_intel_bo(drm_gem_object_lookup(file, handle));
}

__deprecated
extern struct drm_gem_object *
drm_gem_object_lookup(struct drm_file *file, u32 handle);
2305

2306 2307 2308 2309 2310 2311 2312 2313 2314 2315 2316
__attribute__((nonnull))
static inline struct drm_i915_gem_object *
i915_gem_object_get(struct drm_i915_gem_object *obj)
{
	drm_gem_object_reference(&obj->base);
	return obj;
}

__deprecated
extern void drm_gem_object_reference(struct drm_gem_object *);

2317 2318 2319 2320 2321 2322 2323 2324 2325 2326
__attribute__((nonnull))
static inline void
i915_gem_object_put(struct drm_i915_gem_object *obj)
{
	drm_gem_object_unreference(&obj->base);
}

__deprecated
extern void drm_gem_object_unreference(struct drm_gem_object *);

2327 2328 2329 2330 2331 2332 2333 2334 2335 2336
__attribute__((nonnull))
static inline void
i915_gem_object_put_unlocked(struct drm_i915_gem_object *obj)
{
	drm_gem_object_unreference_unlocked(&obj->base);
}

__deprecated
extern void drm_gem_object_unreference_unlocked(struct drm_gem_object *);

2337 2338 2339 2340 2341 2342
static inline bool
i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
{
	return obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE;
}

2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361 2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373
static inline unsigned long
i915_gem_object_get_active(const struct drm_i915_gem_object *obj)
{
	return (obj->flags >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK;
}

static inline bool
i915_gem_object_is_active(const struct drm_i915_gem_object *obj)
{
	return i915_gem_object_get_active(obj);
}

static inline void
i915_gem_object_set_active(struct drm_i915_gem_object *obj, int engine)
{
	obj->flags |= BIT(engine + I915_BO_ACTIVE_SHIFT);
}

static inline void
i915_gem_object_clear_active(struct drm_i915_gem_object *obj, int engine)
{
	obj->flags &= ~BIT(engine + I915_BO_ACTIVE_SHIFT);
}

static inline bool
i915_gem_object_has_active_engine(const struct drm_i915_gem_object *obj,
				  int engine)
{
	return obj->flags & BIT(engine + I915_BO_ACTIVE_SHIFT);
}

2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387 2388 2389 2390 2391
static inline unsigned int
i915_gem_object_get_tiling(struct drm_i915_gem_object *obj)
{
	return obj->tiling_and_stride & TILING_MASK;
}

static inline bool
i915_gem_object_is_tiled(struct drm_i915_gem_object *obj)
{
	return i915_gem_object_get_tiling(obj) != I915_TILING_NONE;
}

static inline unsigned int
i915_gem_object_get_stride(struct drm_i915_gem_object *obj)
{
	return obj->tiling_and_stride & STRIDE_MASK;
}

2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403
static inline struct i915_vma *i915_vma_get(struct i915_vma *vma)
{
	i915_gem_object_get(vma->obj);
	return vma;
}

static inline void i915_vma_put(struct i915_vma *vma)
{
	lockdep_assert_held(&vma->vm->dev->struct_mutex);
	i915_gem_object_put(vma->obj);
}

2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 2415 2416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429
/*
 * Optimised SGL iterator for GEM objects
 */
static __always_inline struct sgt_iter {
	struct scatterlist *sgp;
	union {
		unsigned long pfn;
		dma_addr_t dma;
	};
	unsigned int curr;
	unsigned int max;
} __sgt_iter(struct scatterlist *sgl, bool dma) {
	struct sgt_iter s = { .sgp = sgl };

	if (s.sgp) {
		s.max = s.curr = s.sgp->offset;
		s.max += s.sgp->length;
		if (dma)
			s.dma = sg_dma_address(s.sgp);
		else
			s.pfn = page_to_pfn(sg_page(s.sgp));
	}

	return s;
}

2430 2431 2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448
/**
 * __sg_next - return the next scatterlist entry in a list
 * @sg:		The current sg entry
 *
 * Description:
 *   If the entry is the last, return NULL; otherwise, step to the next
 *   element in the array (@sg@+1). If that's a chain pointer, follow it;
 *   otherwise just return the pointer to the current element.
 **/
static inline struct scatterlist *__sg_next(struct scatterlist *sg)
{
#ifdef CONFIG_DEBUG_SG
	BUG_ON(sg->sg_magic != SG_MAGIC);
#endif
	return sg_is_last(sg) ? NULL :
		likely(!sg_is_chain(++sg)) ? sg :
		sg_chain_ptr(sg);
}

2449 2450 2451 2452 2453 2454 2455 2456 2457 2458
/**
 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
 * @__dmap:	DMA address (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_dma(__dmap, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, true);			\
	     ((__dmap) = (__iter).dma + (__iter).curr);			\
	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
2459
	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471

/**
 * for_each_sgt_page - iterate over the pages of the given sg_table
 * @__pp:	page pointer (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_page(__pp, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, false);		\
	     ((__pp) = (__iter).pfn == 0 ? NULL :			\
	      pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
2472
	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2473

2474 2475 2476 2477 2478 2479 2480 2481 2482 2483 2484 2485 2486 2487 2488 2489 2490 2491 2492 2493 2494 2495 2496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 2510 2511 2512 2513 2514 2515 2516 2517 2518 2519 2520 2521 2522 2523 2524 2525
/*
 * A command that requires special handling by the command parser.
 */
struct drm_i915_cmd_descriptor {
	/*
	 * Flags describing how the command parser processes the command.
	 *
	 * CMD_DESC_FIXED: The command has a fixed length if this is set,
	 *                 a length mask if not set
	 * CMD_DESC_SKIP: The command is allowed but does not follow the
	 *                standard length encoding for the opcode range in
	 *                which it falls
	 * CMD_DESC_REJECT: The command is never allowed
	 * CMD_DESC_REGISTER: The command should be checked against the
	 *                    register whitelist for the appropriate ring
	 * CMD_DESC_MASTER: The command is allowed if the submitting process
	 *                  is the DRM master
	 */
	u32 flags;
#define CMD_DESC_FIXED    (1<<0)
#define CMD_DESC_SKIP     (1<<1)
#define CMD_DESC_REJECT   (1<<2)
#define CMD_DESC_REGISTER (1<<3)
#define CMD_DESC_BITMASK  (1<<4)
#define CMD_DESC_MASTER   (1<<5)

	/*
	 * The command's unique identification bits and the bitmask to get them.
	 * This isn't strictly the opcode field as defined in the spec and may
	 * also include type, subtype, and/or subop fields.
	 */
	struct {
		u32 value;
		u32 mask;
	} cmd;

	/*
	 * The command's length. The command is either fixed length (i.e. does
	 * not include a length field) or has a length field mask. The flag
	 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
	 * a length mask. All command entries in a command table must include
	 * length information.
	 */
	union {
		u32 fixed;
		u32 mask;
	} length;

	/*
	 * Describes where to find a register address in the command to check
	 * against the ring's register whitelist. Only valid if flags has the
	 * CMD_DESC_REGISTER bit set.
2526 2527 2528 2529
	 *
	 * A non-zero step value implies that the command may access multiple
	 * registers in sequence (e.g. LRI), in that case step gives the
	 * distance in dwords between individual offset fields.
2530 2531 2532 2533
	 */
	struct {
		u32 offset;
		u32 mask;
2534
		u32 step;
2535 2536 2537 2538 2539 2540 2541 2542 2543
	} reg;

#define MAX_CMD_DESC_BITMASKS 3
	/*
	 * Describes command checks where a particular dword is masked and
	 * compared against an expected value. If the command does not match
	 * the expected value, the parser rejects it. Only valid if flags has
	 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
	 * are valid.
2544 2545 2546 2547
	 *
	 * If the check specifies a non-zero condition_mask then the parser
	 * only performs the check when the bits specified by condition_mask
	 * are non-zero.
2548 2549 2550 2551 2552
	 */
	struct {
		u32 offset;
		u32 mask;
		u32 expected;
2553 2554
		u32 condition_offset;
		u32 condition_mask;
2555 2556 2557 2558 2559 2560
	} bits[MAX_CMD_DESC_BITMASKS];
};

/*
 * A table of commands requiring special handling by the command parser.
 *
2561 2562 2563
 * Each engine has an array of tables. Each table consists of an array of
 * command descriptors, which must be sorted with command opcodes in
 * ascending order.
2564 2565 2566 2567 2568 2569
 */
struct drm_i915_cmd_table {
	const struct drm_i915_cmd_descriptor *table;
	int count;
};

C
Chris Wilson 已提交
2570
/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2571 2572 2573 2574 2575 2576 2577 2578 2579 2580
#define __I915__(p) ({ \
	struct drm_i915_private *__p; \
	if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
		__p = (struct drm_i915_private *)p; \
	else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
		__p = to_i915((struct drm_device *)p); \
	else \
		BUILD_BUG(); \
	__p; \
})
2581
#define INTEL_INFO(p)	(&__I915__(p)->info)
2582
#define INTEL_GEN(p)	(INTEL_INFO(p)->gen)
2583
#define INTEL_DEVID(p)	(INTEL_INFO(p)->device_id)
2584

2585
#define REVID_FOREVER		0xff
2586
#define INTEL_REVID(p)	(__I915__(p)->drm.pdev->revision)
2587 2588 2589 2590 2591 2592 2593 2594 2595 2596 2597 2598 2599 2600 2601 2602 2603 2604 2605 2606

#define GEN_FOREVER (0)
/*
 * Returns true if Gen is in inclusive range [Start, End].
 *
 * Use GEN_FOREVER for unbound start and or end.
 */
#define IS_GEN(p, s, e) ({ \
	unsigned int __s = (s), __e = (e); \
	BUILD_BUG_ON(!__builtin_constant_p(s)); \
	BUILD_BUG_ON(!__builtin_constant_p(e)); \
	if ((__s) != GEN_FOREVER) \
		__s = (s) - 1; \
	if ((__e) == GEN_FOREVER) \
		__e = BITS_PER_LONG - 1; \
	else \
		__e = (e) - 1; \
	!!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \
})

2607 2608 2609 2610 2611 2612 2613 2614
/*
 * Return true if revision is in range [since,until] inclusive.
 *
 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
 */
#define IS_REVID(p, since, until) \
	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))

2615 2616
#define IS_I830(dev)		(INTEL_DEVID(dev) == 0x3577)
#define IS_845G(dev)		(INTEL_DEVID(dev) == 0x2562)
2617
#define IS_I85X(dev)		(INTEL_INFO(dev)->is_i85x)
2618
#define IS_I865G(dev)		(INTEL_DEVID(dev) == 0x2572)
2619
#define IS_I915G(dev)		(INTEL_INFO(dev)->is_i915g)
2620 2621
#define IS_I915GM(dev)		(INTEL_DEVID(dev) == 0x2592)
#define IS_I945G(dev)		(INTEL_DEVID(dev) == 0x2772)
2622 2623 2624
#define IS_I945GM(dev)		(INTEL_INFO(dev)->is_i945gm)
#define IS_BROADWATER(dev)	(INTEL_INFO(dev)->is_broadwater)
#define IS_CRESTLINE(dev)	(INTEL_INFO(dev)->is_crestline)
2625
#define IS_GM45(dev)		(INTEL_DEVID(dev) == 0x2A42)
2626
#define IS_G4X(dev)		(INTEL_INFO(dev)->is_g4x)
2627 2628
#define IS_PINEVIEW_G(dev)	(INTEL_DEVID(dev) == 0xa001)
#define IS_PINEVIEW_M(dev)	(INTEL_DEVID(dev) == 0xa011)
2629 2630
#define IS_PINEVIEW(dev)	(INTEL_INFO(dev)->is_pineview)
#define IS_G33(dev)		(INTEL_INFO(dev)->is_g33)
2631
#define IS_IRONLAKE_M(dev)	(INTEL_DEVID(dev) == 0x0046)
2632
#define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
2633 2634 2635
#define IS_IVB_GT1(dev)		(INTEL_DEVID(dev) == 0x0156 || \
				 INTEL_DEVID(dev) == 0x0152 || \
				 INTEL_DEVID(dev) == 0x015a)
2636
#define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
2637
#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_cherryview)
2638
#define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
2639
#define IS_BROADWELL(dev)	(INTEL_INFO(dev)->is_broadwell)
2640
#define IS_SKYLAKE(dev)	(INTEL_INFO(dev)->is_skylake)
2641
#define IS_BROXTON(dev)		(INTEL_INFO(dev)->is_broxton)
2642
#define IS_KABYLAKE(dev)	(INTEL_INFO(dev)->is_kabylake)
2643
#define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
2644
#define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \
2645
				 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
B
Ben Widawsky 已提交
2646
#define IS_BDW_ULT(dev)		(IS_BROADWELL(dev) && \
2647
				 ((INTEL_DEVID(dev) & 0xf) == 0x6 ||	\
2648
				 (INTEL_DEVID(dev) & 0xf) == 0xb ||	\
2649
				 (INTEL_DEVID(dev) & 0xf) == 0xe))
V
Ville Syrjälä 已提交
2650 2651 2652
/* ULX machines are also considered ULT. */
#define IS_BDW_ULX(dev)		(IS_BROADWELL(dev) && \
				 (INTEL_DEVID(dev) & 0xf) == 0xe)
R
Rodrigo Vivi 已提交
2653 2654
#define IS_BDW_GT3(dev)		(IS_BROADWELL(dev) && \
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
B
Ben Widawsky 已提交
2655
#define IS_HSW_ULT(dev)		(IS_HASWELL(dev) && \
2656
				 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2657
#define IS_HSW_GT3(dev)		(IS_HASWELL(dev) && \
2658
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2659
/* ULX machines are also considered ULT. */
2660 2661
#define IS_HSW_ULX(dev)		(INTEL_DEVID(dev) == 0x0A0E || \
				 INTEL_DEVID(dev) == 0x0A1E)
2662 2663 2664 2665 2666 2667 2668 2669
#define IS_SKL_ULT(dev)		(INTEL_DEVID(dev) == 0x1906 || \
				 INTEL_DEVID(dev) == 0x1913 || \
				 INTEL_DEVID(dev) == 0x1916 || \
				 INTEL_DEVID(dev) == 0x1921 || \
				 INTEL_DEVID(dev) == 0x1926)
#define IS_SKL_ULX(dev)		(INTEL_DEVID(dev) == 0x190E || \
				 INTEL_DEVID(dev) == 0x1915 || \
				 INTEL_DEVID(dev) == 0x191E)
2670 2671 2672 2673 2674 2675 2676 2677
#define IS_KBL_ULT(dev)		(INTEL_DEVID(dev) == 0x5906 || \
				 INTEL_DEVID(dev) == 0x5913 || \
				 INTEL_DEVID(dev) == 0x5916 || \
				 INTEL_DEVID(dev) == 0x5921 || \
				 INTEL_DEVID(dev) == 0x5926)
#define IS_KBL_ULX(dev)		(INTEL_DEVID(dev) == 0x590E || \
				 INTEL_DEVID(dev) == 0x5915 || \
				 INTEL_DEVID(dev) == 0x591E)
2678 2679 2680 2681 2682
#define IS_SKL_GT3(dev)		(IS_SKYLAKE(dev) && \
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
#define IS_SKL_GT4(dev)		(IS_SKYLAKE(dev) && \
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)

2683
#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2684

2685 2686 2687 2688 2689 2690
#define SKL_REVID_A0		0x0
#define SKL_REVID_B0		0x1
#define SKL_REVID_C0		0x2
#define SKL_REVID_D0		0x3
#define SKL_REVID_E0		0x4
#define SKL_REVID_F0		0x5
2691 2692
#define SKL_REVID_G0		0x6
#define SKL_REVID_H0		0x7
2693

2694 2695
#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))

2696
#define BXT_REVID_A0		0x0
2697
#define BXT_REVID_A1		0x1
2698 2699
#define BXT_REVID_B0		0x3
#define BXT_REVID_C0		0x9
N
Nick Hoath 已提交
2700

2701 2702
#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))

M
Mika Kuoppala 已提交
2703 2704
#define KBL_REVID_A0		0x0
#define KBL_REVID_B0		0x1
2705 2706 2707
#define KBL_REVID_C0		0x2
#define KBL_REVID_D0		0x3
#define KBL_REVID_E0		0x4
M
Mika Kuoppala 已提交
2708 2709 2710 2711

#define IS_KBL_REVID(p, since, until) \
	(IS_KABYLAKE(p) && IS_REVID(p, since, until))

2712 2713 2714 2715 2716 2717
/*
 * The genX designation typically refers to the render engine, so render
 * capability related checks should use IS_GEN, while display and other checks
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 * chips, etc.).
 */
2718 2719 2720 2721 2722 2723 2724 2725
#define IS_GEN2(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(1)))
#define IS_GEN3(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(2)))
#define IS_GEN4(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(3)))
#define IS_GEN5(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(4)))
#define IS_GEN6(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(5)))
#define IS_GEN7(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(6)))
#define IS_GEN8(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(7)))
#define IS_GEN9(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(8)))
2726

2727 2728 2729 2730 2731 2732 2733 2734 2735
#define ENGINE_MASK(id)	BIT(id)
#define RENDER_RING	ENGINE_MASK(RCS)
#define BSD_RING	ENGINE_MASK(VCS)
#define BLT_RING	ENGINE_MASK(BCS)
#define VEBOX_RING	ENGINE_MASK(VECS)
#define BSD2_RING	ENGINE_MASK(VCS2)
#define ALL_ENGINES	(~0)

#define HAS_ENGINE(dev_priv, id) \
2736
	(!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))
2737 2738 2739 2740 2741 2742

#define HAS_BSD(dev_priv)	HAS_ENGINE(dev_priv, VCS)
#define HAS_BSD2(dev_priv)	HAS_ENGINE(dev_priv, VCS2)
#define HAS_BLT(dev_priv)	HAS_ENGINE(dev_priv, BCS)
#define HAS_VEBOX(dev_priv)	HAS_ENGINE(dev_priv, VECS)

2743
#define HAS_LLC(dev)		(INTEL_INFO(dev)->has_llc)
2744
#define HAS_SNOOP(dev)		(INTEL_INFO(dev)->has_snoop)
2745
#define HAS_EDRAM(dev)		(!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
2746
#define HAS_WT(dev)		((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2747
				 HAS_EDRAM(dev))
2748 2749
#define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)

2750
#define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->has_hw_contexts)
2751
#define HAS_LOGICAL_RING_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 8)
2752
#define USES_PPGTT(dev)		(i915.enable_ppgtt)
2753 2754
#define USES_FULL_PPGTT(dev)	(i915.enable_ppgtt >= 2)
#define USES_FULL_48BIT_PPGTT(dev)	(i915.enable_ppgtt == 3)
2755

2756
#define HAS_OVERLAY(dev)		(INTEL_INFO(dev)->has_overlay)
2757 2758
#define OVERLAY_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->overlay_needs_physical)

2759 2760
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
#define HAS_BROKEN_CS_TLB(dev)		(IS_I830(dev) || IS_845G(dev))
2761 2762

/* WaRsDisableCoarsePowerGating:skl,bxt */
2763 2764 2765 2766
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
	(IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
	 IS_SKL_GT3(dev_priv) || \
	 IS_SKL_GT4(dev_priv))
2767

2768 2769 2770 2771 2772 2773 2774
/*
 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
 * even when in MSI mode. This results in spurious interrupt warnings if the
 * legacy irq no. is shared with another device. The kernel then disables that
 * interrupt source and so prevents the other device from working properly.
 */
#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2775
#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->has_gmbus_irq)
2776

2777 2778 2779 2780 2781 2782 2783 2784 2785 2786
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
						      IS_I915GM(dev)))
#define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)
#define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)

#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2787
#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2788

2789
#define HAS_IPS(dev)		(IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2790

2791
#define HAS_DP_MST(dev)	(INTEL_INFO(dev)->has_dp_mst)
2792

2793
#define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
2794
#define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
2795
#define HAS_PSR(dev)		(INTEL_INFO(dev)->has_psr)
2796
#define HAS_RUNTIME_PM(dev)	(INTEL_INFO(dev)->has_runtime_pm)
2797
#define HAS_RC6(dev)		(INTEL_INFO(dev)->has_rc6)
2798
#define HAS_RC6p(dev)		(INTEL_INFO(dev)->has_rc6p)
P
Paulo Zanoni 已提交
2799

2800
#define HAS_CSR(dev)	(INTEL_INFO(dev)->has_csr)
2801

2802 2803 2804 2805 2806
/*
 * For now, anything with a GuC requires uCode loading, and then supports
 * command submission once loaded. But these are logically independent
 * properties, so we have separate macros to test them.
 */
2807
#define HAS_GUC(dev)		(IS_GEN9(dev))
2808 2809
#define HAS_GUC_UCODE(dev)	(HAS_GUC(dev))
#define HAS_GUC_SCHED(dev)	(HAS_GUC(dev))
2810

2811
#define HAS_RESOURCE_STREAMER(dev) (INTEL_INFO(dev)->has_resource_streamer)
2812

2813 2814
#define HAS_POOLED_EU(dev)	(INTEL_INFO(dev)->has_pooled_eu)

2815 2816 2817 2818 2819 2820
#define INTEL_PCH_DEVICE_ID_MASK		0xff00
#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
2821 2822
#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
2823
#define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA200
2824
#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
2825
#define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
2826
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
2827

2828
#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2829
#define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
2830
#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2831
#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2832
#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
V
Ville Syrjälä 已提交
2833
#define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2834 2835
#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
B
Ben Widawsky 已提交
2836
#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2837
#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2838

2839 2840
#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
			       IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2841

2842 2843 2844
/* DPF == dynamic parity feature */
#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2845

2846
#define GT_FREQUENCY_MULTIPLIER 50
A
Akash Goel 已提交
2847
#define GEN9_FREQ_SCALER 3
2848

2849 2850
#include "i915_trace.h"

2851 2852 2853 2854 2855 2856 2857 2858 2859
static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
#ifdef CONFIG_INTEL_IOMMU
	if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
		return true;
#endif
	return false;
}

2860 2861
extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
extern int i915_resume_switcheroo(struct drm_device *dev);
2862

2863
int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
2864
				int enable_ppgtt);
2865

2866 2867
bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);

2868
/* i915_drv.c */
2869 2870 2871 2872 2873 2874 2875
void __printf(3, 4)
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
	      const char *fmt, ...);

#define i915_report_error(dev_priv, fmt, ...)				   \
	__i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)

2876
#ifdef CONFIG_COMPAT
D
Dave Airlie 已提交
2877 2878
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);
2879
#endif
2880 2881
extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2882
extern int i915_reset(struct drm_i915_private *dev_priv);
2883
extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2884
extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2885 2886 2887 2888
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2889
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2890

2891
/* intel_hotplug.c */
2892 2893
void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
			   u32 pin_mask, u32 long_mask);
2894 2895 2896
void intel_hpd_init(struct drm_i915_private *dev_priv);
void intel_hpd_init_work(struct drm_i915_private *dev_priv);
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2897
bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2898 2899
bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2900

L
Linus Torvalds 已提交
2901
/* i915_irq.c */
2902 2903 2904 2905 2906 2907 2908 2909 2910 2911 2912 2913 2914 2915 2916 2917 2918
static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
{
	unsigned long delay;

	if (unlikely(!i915.enable_hangcheck))
		return;

	/* Don't continually defer the hangcheck so that it is always run at
	 * least once after work has been scheduled on any ring. Otherwise,
	 * we will ignore a hung ring if a second ring is kept busy.
	 */

	delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
	queue_delayed_work(system_long_wq,
			   &dev_priv->gpu_error.hangcheck_work, delay);
}

2919
__printf(3, 4)
2920 2921
void i915_handle_error(struct drm_i915_private *dev_priv,
		       u32 engine_mask,
2922
		       const char *fmt, ...);
L
Linus Torvalds 已提交
2923

2924
extern void intel_irq_init(struct drm_i915_private *dev_priv);
2925 2926
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2927

2928 2929
extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
2930
					bool restore_forcewake);
2931
extern void intel_uncore_init(struct drm_i915_private *dev_priv);
2932
extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2933
extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2934 2935 2936
extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
					 bool restore);
2937
const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2938
void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2939
				enum forcewake_domains domains);
2940
void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2941
				enum forcewake_domains domains);
2942 2943 2944 2945 2946 2947 2948
/* Like above but the caller must manage the uncore.lock itself.
 * Must be used with I915_READ_FW and friends.
 */
void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
2949 2950
u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);

2951
void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2952

2953 2954 2955 2956 2957 2958 2959 2960 2961 2962 2963
int intel_wait_for_register(struct drm_i915_private *dev_priv,
			    i915_reg_t reg,
			    const u32 mask,
			    const u32 value,
			    const unsigned long timeout_ms);
int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
			       i915_reg_t reg,
			       const u32 mask,
			       const u32 value,
			       const unsigned long timeout_ms);

2964 2965 2966 2967 2968
static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
{
	return dev_priv->gvt.initialized;
}

2969
static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2970
{
2971
	return dev_priv->vgpu.active;
2972
}
2973

2974
void
2975
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2976
		     u32 status_mask);
2977 2978

void
2979
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2980
		      u32 status_mask);
2981

2982 2983
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2984 2985 2986
void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
				   uint32_t mask,
				   uint32_t bits);
2987 2988 2989 2990 2991 2992 2993 2994 2995 2996 2997 2998 2999
void ilk_update_display_irq(struct drm_i915_private *dev_priv,
			    uint32_t interrupt_mask,
			    uint32_t enabled_irq_mask);
static inline void
ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, bits);
}
static inline void
ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, 0);
}
3000 3001 3002 3003 3004 3005 3006 3007 3008 3009 3010 3011 3012 3013
void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
			 enum pipe pipe,
			 uint32_t interrupt_mask,
			 uint32_t enabled_irq_mask);
static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
				       enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
}
static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
					enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
}
3014 3015 3016
void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask);
3017 3018 3019 3020 3021 3022 3023 3024 3025 3026 3027
static inline void
ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, bits);
}
static inline void
ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, 0);
}

3028 3029 3030 3031 3032 3033 3034 3035 3036
/* i915_gem.c */
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3037 3038
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3039 3040 3041 3042 3043 3044
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
			     struct drm_file *file_priv);
int i915_gem_execbuffer(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
J
Jesse Barnes 已提交
3045 3046
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
3047 3048
int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
B
Ben Widawsky 已提交
3049 3050 3051 3052
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
3053 3054
int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
3055 3056
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
3057 3058 3059 3060
int i915_gem_set_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
int i915_gem_get_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3061
void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3062 3063
int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file);
3064 3065
int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
3066 3067
int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3068 3069
void i915_gem_load_init(struct drm_device *dev);
void i915_gem_load_cleanup(struct drm_device *dev);
3070
void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3071 3072
int i915_gem_freeze_late(struct drm_i915_private *dev_priv);

3073 3074
void *i915_gem_object_alloc(struct drm_device *dev);
void i915_gem_object_free(struct drm_i915_gem_object *obj);
3075 3076
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			 const struct drm_i915_gem_object_ops *ops);
3077
struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev,
3078
						  size_t size);
3079 3080
struct drm_i915_gem_object *i915_gem_object_create_from_data(
		struct drm_device *dev, const void *data, size_t size);
3081
void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3082
void i915_gem_free_object(struct drm_gem_object *obj);
3083

C
Chris Wilson 已提交
3084
struct i915_vma * __must_check
3085 3086
i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
			 const struct i915_ggtt_view *view,
3087
			 u64 size,
3088 3089
			 u64 alignment,
			 u64 flags);
3090 3091 3092

int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
		  u32 flags);
3093
void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
3094
int __must_check i915_vma_unbind(struct i915_vma *vma);
3095 3096
void i915_vma_close(struct i915_vma *vma);
void i915_vma_destroy(struct i915_vma *vma);
3097 3098

int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3099
int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
3100
void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
3101
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3102

3103
int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3104 3105

static inline int __sg_page_count(struct scatterlist *sg)
3106
{
3107 3108
	return sg->length >> PAGE_SHIFT;
}
3109

3110 3111 3112
struct page *
i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);

3113 3114 3115 3116 3117 3118 3119 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129
static inline dma_addr_t
i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, int n)
{
	if (n < obj->get_page.last) {
		obj->get_page.sg = obj->pages->sgl;
		obj->get_page.last = 0;
	}

	while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
		obj->get_page.last += __sg_page_count(obj->get_page.sg++);
		if (unlikely(sg_is_chain(obj->get_page.sg)))
			obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
	}

	return sg_dma_address(obj->get_page.sg) + ((n - obj->get_page.last) << PAGE_SHIFT);
}

3130 3131
static inline struct page *
i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
3132
{
3133 3134
	if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
		return NULL;
3135

3136 3137 3138 3139
	if (n < obj->get_page.last) {
		obj->get_page.sg = obj->pages->sgl;
		obj->get_page.last = 0;
	}
3140

3141 3142 3143 3144 3145
	while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
		obj->get_page.last += __sg_page_count(obj->get_page.sg++);
		if (unlikely(sg_is_chain(obj->get_page.sg)))
			obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
	}
3146

3147
	return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
3148
}
3149

3150 3151 3152 3153 3154
static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
{
	BUG_ON(obj->pages == NULL);
	obj->pages_pin_count++;
}
3155

3156 3157 3158 3159 3160 3161
static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
{
	BUG_ON(obj->pages_pin_count == 0);
	obj->pages_pin_count--;
}

3162 3163 3164 3165 3166
enum i915_map_type {
	I915_MAP_WB = 0,
	I915_MAP_WC,
};

3167 3168 3169
/**
 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
 * @obj - the object to map into kernel address space
3170
 * @type - the type of mapping, used to select pgprot_t
3171 3172 3173
 *
 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
 * pages and then returns a contiguous mapping of the backing storage into
3174 3175
 * the kernel address space. Based on the @type of mapping, the PTE will be
 * set to either WriteBack or WriteCombine (via pgprot_t).
3176
 *
3177 3178
 * The caller must hold the struct_mutex, and is responsible for calling
 * i915_gem_object_unpin_map() when the mapping is no longer required.
3179
 *
3180 3181
 * Returns the pointer through which to access the mapped object, or an
 * ERR_PTR() on error.
3182
 */
3183 3184
void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj,
					   enum i915_map_type type);
3185 3186 3187 3188 3189 3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202

/**
 * i915_gem_object_unpin_map - releases an earlier mapping
 * @obj - the object to unmap
 *
 * After pinning the object and mapping its pages, once you are finished
 * with your access, call i915_gem_object_unpin_map() to release the pin
 * upon the mapping. Once the pin count reaches zero, that mapping may be
 * removed.
 *
 * The caller must hold the struct_mutex.
 */
static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
{
	lockdep_assert_held(&obj->base.dev->struct_mutex);
	i915_gem_object_unpin_pages(obj);
}

3203 3204 3205 3206 3207 3208 3209 3210 3211 3212 3213 3214 3215 3216
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
				    unsigned int *needs_clflush);
int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj,
				     unsigned int *needs_clflush);
#define CLFLUSH_BEFORE 0x1
#define CLFLUSH_AFTER 0x2
#define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER)

static inline void
i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj)
{
	i915_gem_object_unpin_pages(obj);
}

3217
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3218
int i915_gem_object_sync(struct drm_i915_gem_object *obj,
3219
			 struct drm_i915_gem_request *to);
B
Ben Widawsky 已提交
3220
void i915_vma_move_to_active(struct i915_vma *vma,
3221 3222
			     struct drm_i915_gem_request *req,
			     unsigned int flags);
3223 3224 3225
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
3226 3227
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
		      uint32_t handle, uint64_t *offset);
3228
int i915_gem_mmap_gtt_version(void);
3229 3230 3231 3232 3233

void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits);

3234
int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3235

3236
struct drm_i915_gem_request *
3237
i915_gem_find_active_request(struct intel_engine_cs *engine);
3238

3239
void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3240

3241 3242 3243 3244 3245 3246 3247 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260
static inline u32 i915_reset_counter(struct i915_gpu_error *error)
{
	return atomic_read(&error->reset_counter);
}

static inline bool __i915_reset_in_progress(u32 reset)
{
	return unlikely(reset & I915_RESET_IN_PROGRESS_FLAG);
}

static inline bool __i915_reset_in_progress_or_wedged(u32 reset)
{
	return unlikely(reset & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
}

static inline bool __i915_terminally_wedged(u32 reset)
{
	return unlikely(reset & I915_WEDGED);
}

3261 3262
static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
{
3263 3264 3265 3266 3267 3268
	return __i915_reset_in_progress(i915_reset_counter(error));
}

static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
{
	return __i915_reset_in_progress_or_wedged(i915_reset_counter(error));
3269 3270 3271 3272
}

static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
{
3273
	return __i915_terminally_wedged(i915_reset_counter(error));
M
Mika Kuoppala 已提交
3274 3275 3276 3277
}

static inline u32 i915_reset_count(struct i915_gpu_error *error)
{
3278
	return ((i915_reset_counter(error) & ~I915_WEDGED) + 1) / 2;
3279
}
3280

3281
void i915_gem_reset(struct drm_device *dev);
3282
bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3283
int __must_check i915_gem_init(struct drm_device *dev);
3284 3285
int __must_check i915_gem_init_hw(struct drm_device *dev);
void i915_gem_init_swizzling(struct drm_device *dev);
3286
void i915_gem_cleanup_engines(struct drm_device *dev);
3287 3288
int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv,
					bool interruptible);
3289
int __must_check i915_gem_suspend(struct drm_device *dev);
3290
void i915_gem_resume(struct drm_device *dev);
3291
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3292
int __must_check
3293 3294 3295
i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
			       bool readonly);
int __must_check
3296 3297 3298
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
				  bool write);
int __must_check
3299
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
C
Chris Wilson 已提交
3300
struct i915_vma * __must_check
3301 3302
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
3303
				     const struct i915_ggtt_view *view);
C
Chris Wilson 已提交
3304
void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma);
3305
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3306
				int align);
3307
int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3308
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3309

3310 3311 3312
u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u64 size,
			   int tiling_mode);
u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
3313
				int tiling_mode, bool fenced);
3314

3315 3316 3317
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);

3318 3319 3320 3321 3322 3323
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
				struct dma_buf *dma_buf);

struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
				struct drm_gem_object *gem_obj, int flags);

3324
struct i915_vma *
3325
i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
C
Chris Wilson 已提交
3326 3327
		     struct i915_address_space *vm,
		     const struct i915_ggtt_view *view);
3328

3329 3330
struct i915_vma *
i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
C
Chris Wilson 已提交
3331 3332
				  struct i915_address_space *vm,
				  const struct i915_ggtt_view *view);
3333

3334 3335 3336 3337 3338 3339
static inline struct i915_hw_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space *vm)
{
	return container_of(vm, struct i915_hw_ppgtt, base);
}

C
Chris Wilson 已提交
3340 3341 3342
static inline struct i915_vma *
i915_gem_object_to_ggtt(struct drm_i915_gem_object *obj,
			const struct i915_ggtt_view *view)
3343
{
C
Chris Wilson 已提交
3344
	return i915_gem_obj_to_vma(obj, &to_i915(obj->base.dev)->ggtt.base, view);
3345 3346
}

C
Chris Wilson 已提交
3347 3348 3349
static inline unsigned long
i915_gem_object_ggtt_offset(struct drm_i915_gem_object *o,
			    const struct i915_ggtt_view *view)
3350
{
3351
	return i915_ggtt_offset(i915_gem_object_to_ggtt(o, view));
3352
}
3353

3354
/* i915_gem_fence.c */
3355 3356 3357 3358 3359 3360 3361 3362 3363 3364 3365 3366 3367 3368 3369 3370 3371 3372 3373 3374 3375 3376 3377 3378 3379 3380 3381
int __must_check i915_vma_get_fence(struct i915_vma *vma);
int __must_check i915_vma_put_fence(struct i915_vma *vma);

/**
 * i915_vma_pin_fence - pin fencing state
 * @vma: vma to pin fencing for
 *
 * This pins the fencing state (whether tiled or untiled) to make sure the
 * vma (and its object) is ready to be used as a scanout target. Fencing
 * status must be synchronize first by calling i915_vma_get_fence():
 *
 * The resulting fence pin reference must be released again with
 * i915_vma_unpin_fence().
 *
 * Returns:
 *
 * True if the vma has a fence, false otherwise.
 */
static inline bool
i915_vma_pin_fence(struct i915_vma *vma)
{
	if (vma->fence) {
		vma->fence->pin_count++;
		return true;
	} else
		return false;
}
3382

3383 3384 3385 3386 3387 3388 3389 3390 3391 3392 3393 3394 3395 3396 3397 3398
/**
 * i915_vma_unpin_fence - unpin fencing state
 * @vma: vma to unpin fencing for
 *
 * This releases the fence pin reference acquired through
 * i915_vma_pin_fence. It will handle both objects with and without an
 * attached fence correctly, callers do not need to distinguish this.
 */
static inline void
i915_vma_unpin_fence(struct i915_vma *vma)
{
	if (vma->fence) {
		GEM_BUG_ON(vma->fence->pin_count <= 0);
		vma->fence->pin_count--;
	}
}
3399 3400 3401

void i915_gem_restore_fences(struct drm_device *dev);

3402 3403 3404 3405
void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);

3406
/* i915_gem_context.c */
3407
int __must_check i915_gem_context_init(struct drm_device *dev);
3408
void i915_gem_context_lost(struct drm_i915_private *dev_priv);
3409
void i915_gem_context_fini(struct drm_device *dev);
3410
void i915_gem_context_reset(struct drm_device *dev);
3411
int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3412
void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3413
int i915_switch_context(struct drm_i915_gem_request *req);
3414
int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv);
3415
void i915_gem_context_free(struct kref *ctx_ref);
3416 3417
struct drm_i915_gem_object *
i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3418 3419
struct i915_gem_context *
i915_gem_context_create_gvt(struct drm_device *dev);
3420 3421 3422 3423 3424 3425

static inline struct i915_gem_context *
i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
{
	struct i915_gem_context *ctx;

3426
	lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3427 3428 3429 3430 3431 3432 3433 3434

	ctx = idr_find(&file_priv->context_idr, id);
	if (!ctx)
		return ERR_PTR(-ENOENT);

	return ctx;
}

3435 3436
static inline struct i915_gem_context *
i915_gem_context_get(struct i915_gem_context *ctx)
3437
{
3438
	kref_get(&ctx->ref);
3439
	return ctx;
3440 3441
}

3442
static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3443
{
3444
	lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3445
	kref_put(&ctx->ref, i915_gem_context_free);
3446 3447
}

3448
static inline bool i915_gem_context_is_default(const struct i915_gem_context *c)
3449
{
3450
	return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3451 3452
}

3453 3454 3455 3456
int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
				  struct drm_file *file);
int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
				   struct drm_file *file);
3457 3458 3459 3460
int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file_priv);
int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file_priv);
3461 3462
int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
				       struct drm_file *file);
3463

3464
/* i915_gem_evict.c */
3465
int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3466
					  u64 min_size, u64 alignment,
3467
					  unsigned cache_level,
3468
					  u64 start, u64 end,
3469
					  unsigned flags);
3470
int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3471
int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3472

3473
/* belongs in i915_gem_gtt.h */
3474
static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3475
{
3476
	wmb();
3477
	if (INTEL_GEN(dev_priv) < 6)
3478 3479
		intel_gtt_chipset_flush();
}
3480

3481
/* i915_gem_stolen.c */
3482 3483 3484
int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
				struct drm_mm_node *node, u64 size,
				unsigned alignment);
3485 3486 3487 3488
int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
					 struct drm_mm_node *node, u64 size,
					 unsigned alignment, u64 start,
					 u64 end);
3489 3490
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
				 struct drm_mm_node *node);
3491 3492
int i915_gem_init_stolen(struct drm_device *dev);
void i915_gem_cleanup_stolen(struct drm_device *dev);
3493 3494
struct drm_i915_gem_object *
i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3495 3496 3497 3498 3499
struct drm_i915_gem_object *
i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
					       u32 stolen_offset,
					       u32 gtt_offset,
					       u32 size);
3500

3501 3502
/* i915_gem_shrinker.c */
unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3503
			      unsigned long target,
3504 3505 3506 3507
			      unsigned flags);
#define I915_SHRINK_PURGEABLE 0x1
#define I915_SHRINK_UNBOUND 0x2
#define I915_SHRINK_BOUND 0x4
3508
#define I915_SHRINK_ACTIVE 0x8
3509
#define I915_SHRINK_VMAPS 0x10
3510 3511
unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3512
void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3513 3514


3515
/* i915_gem_tiling.c */
3516
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3517
{
3518
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3519 3520

	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3521
		i915_gem_object_is_tiled(obj);
3522 3523
}

3524
/* i915_debugfs.c */
3525
#ifdef CONFIG_DEBUG_FS
3526 3527
int i915_debugfs_register(struct drm_i915_private *dev_priv);
void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3528
int i915_debugfs_connector_add(struct drm_connector *connector);
3529
void intel_display_crc_init(struct drm_i915_private *dev_priv);
3530
#else
3531 3532
static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {}
3533 3534
static inline int i915_debugfs_connector_add(struct drm_connector *connector)
{ return 0; }
3535
static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {}
3536
#endif
3537 3538

/* i915_gpu_error.c */
3539 3540
__printf(2, 3)
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3541 3542
int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
			    const struct i915_error_state_file_priv *error);
3543
int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3544
			      struct drm_i915_private *i915,
3545 3546 3547 3548 3549 3550
			      size_t count, loff_t pos);
static inline void i915_error_state_buf_release(
	struct drm_i915_error_state_buf *eb)
{
	kfree(eb->buf);
}
3551 3552
void i915_capture_error_state(struct drm_i915_private *dev_priv,
			      u32 engine_mask,
3553
			      const char *error_msg);
3554 3555 3556 3557 3558
void i915_error_state_get(struct drm_device *dev,
			  struct i915_error_state_file_priv *error_priv);
void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
void i915_destroy_error_state(struct drm_device *dev);

3559
void i915_get_extra_instdone(struct drm_i915_private *dev_priv, uint32_t *instdone);
3560
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3561

3562
/* i915_cmd_parser.c */
3563
int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3564
void intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
3565 3566 3567 3568 3569 3570 3571 3572
void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine);
int intel_engine_cmd_parser(struct intel_engine_cs *engine,
			    struct drm_i915_gem_object *batch_obj,
			    struct drm_i915_gem_object *shadow_batch_obj,
			    u32 batch_start_offset,
			    u32 batch_len,
			    bool is_master);
3573

3574 3575 3576
/* i915_suspend.c */
extern int i915_save_state(struct drm_device *dev);
extern int i915_restore_state(struct drm_device *dev);
3577

B
Ben Widawsky 已提交
3578
/* i915_sysfs.c */
D
David Weinehall 已提交
3579 3580
void i915_setup_sysfs(struct drm_i915_private *dev_priv);
void i915_teardown_sysfs(struct drm_i915_private *dev_priv);
B
Ben Widawsky 已提交
3581

3582 3583 3584
/* intel_i2c.c */
extern int intel_setup_gmbus(struct drm_device *dev);
extern void intel_teardown_gmbus(struct drm_device *dev);
3585 3586
extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
				     unsigned int pin);
3587

3588 3589
extern struct i2c_adapter *
intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
C
Chris Wilson 已提交
3590 3591
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3592
static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3593 3594 3595
{
	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
}
3596 3597
extern void intel_i2c_reset(struct drm_device *dev);

3598
/* intel_bios.c */
3599
int intel_bios_init(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3600
bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3601
bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3602
bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3603
bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3604
bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3605
bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3606
bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3607 3608
bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
				     enum port port);
3609

3610
/* intel_opregion.c */
3611
#ifdef CONFIG_ACPI
3612
extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3613 3614
extern void intel_opregion_register(struct drm_i915_private *dev_priv);
extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3615
extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3616 3617
extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
					 bool enable);
3618
extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3619
					 pci_power_t state);
3620
extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3621
#else
3622
static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3623 3624
static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3625 3626 3627
static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
{
}
3628 3629 3630 3631 3632
static inline int
intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
{
	return 0;
}
3633
static inline int
3634
intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3635 3636 3637
{
	return 0;
}
3638
static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3639 3640 3641
{
	return -ENODEV;
}
3642
#endif
3643

J
Jesse Barnes 已提交
3644 3645 3646 3647 3648 3649 3650 3651 3652
/* intel_acpi.c */
#ifdef CONFIG_ACPI
extern void intel_register_dsm_handler(void);
extern void intel_unregister_dsm_handler(void);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */

3653 3654 3655 3656 3657 3658 3659 3660 3661 3662
/* intel_device_info.c */
static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private *dev_priv)
{
	return (struct intel_device_info *)&dev_priv->info;
}

void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
void intel_device_info_dump(struct drm_i915_private *dev_priv);

J
Jesse Barnes 已提交
3663
/* modesetting */
3664
extern void intel_modeset_init_hw(struct drm_device *dev);
J
Jesse Barnes 已提交
3665
extern void intel_modeset_init(struct drm_device *dev);
3666
extern void intel_modeset_gem_init(struct drm_device *dev);
J
Jesse Barnes 已提交
3667
extern void intel_modeset_cleanup(struct drm_device *dev);
3668
extern int intel_connector_register(struct drm_connector *);
3669
extern void intel_connector_unregister(struct drm_connector *);
3670
extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3671
extern void intel_display_resume(struct drm_device *dev);
3672
extern void i915_redisable_vga(struct drm_device *dev);
3673
extern void i915_redisable_vga_power_on(struct drm_device *dev);
3674
extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
P
Paulo Zanoni 已提交
3675
extern void intel_init_pch_refclk(struct drm_device *dev);
3676
extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3677 3678
extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
				  bool enable);
3679

B
Ben Widawsky 已提交
3680 3681
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file);
3682

3683
/* overlay */
3684 3685
extern struct intel_overlay_error_state *
intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3686 3687
extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
					    struct intel_overlay_error_state *error);
3688

3689 3690
extern struct intel_display_error_state *
intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3691
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3692 3693
					    struct drm_device *dev,
					    struct intel_display_error_state *error);
3694

3695 3696
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3697 3698

/* intel_sideband.c */
3699 3700
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3701
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3702 3703
u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3704 3705 3706 3707
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3708 3709
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3710 3711
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3712 3713 3714 3715
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		   enum intel_sbi_destination destination);
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		     enum intel_sbi_destination destination);
3716 3717
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3718

3719 3720 3721 3722
/* intel_dpio_phy.c */
void chv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 deemph_reg_value, u32 margin_reg_value,
			      bool uniq_trans_scale);
3723 3724
void chv_data_lane_soft_reset(struct intel_encoder *encoder,
			      bool reset);
3725
void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3726 3727
void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3728
void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3729

3730 3731 3732
void vlv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 demph_reg_value, u32 preemph_reg_value,
			      u32 uniqtranscale_reg_value, u32 tx3_demph);
3733
void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3734
void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3735
void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3736

3737 3738
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3739

3740 3741 3742 3743 3744 3745 3746 3747 3748 3749 3750 3751 3752
#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

#define I915_READ16(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
#define I915_WRITE16(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
#define I915_READ16_NOTRACE(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
#define I915_WRITE16_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)

#define I915_READ(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
#define I915_WRITE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
#define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
#define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)

3753 3754 3755 3756
/* Be very careful with read/write 64-bit values. On 32-bit machines, they
 * will be implemented using 2 32-bit writes in an arbitrary order with
 * an arbitrary delay between them. This can cause the hardware to
 * act upon the intermediate value, possibly leading to corruption and
3757 3758 3759 3760 3761 3762 3763 3764 3765
 * machine death. For this reason we do not support I915_WRITE64, or
 * dev_priv->uncore.funcs.mmio_writeq.
 *
 * When reading a 64-bit value as two 32-bit values, the delay may cause
 * the two reads to mismatch, e.g. a timestamp overflowing. Also note that
 * occasionally a 64-bit register does not actualy support a full readq
 * and must be read using two 32-bit reads.
 *
 * You have been warned.
3766
 */
3767
#define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3768

3769
#define I915_READ64_2x32(lower_reg, upper_reg) ({			\
3770 3771
	u32 upper, lower, old_upper, loop = 0;				\
	upper = I915_READ(upper_reg);					\
3772
	do {								\
3773
		old_upper = upper;					\
3774
		lower = I915_READ(lower_reg);				\
3775 3776
		upper = I915_READ(upper_reg);				\
	} while (upper != old_upper && loop++ < 2);			\
3777
	(u64)upper << 32 | lower; })
3778

3779 3780 3781
#define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)

3782 3783
#define __raw_read(x, s) \
static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3784
					     i915_reg_t reg) \
3785
{ \
3786
	return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3787 3788 3789 3790
}

#define __raw_write(x, s) \
static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3791
				       i915_reg_t reg, uint##x##_t val) \
3792
{ \
3793
	write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 3807
}
__raw_read(8, b)
__raw_read(16, w)
__raw_read(32, l)
__raw_read(64, q)

__raw_write(8, b)
__raw_write(16, w)
__raw_write(32, l)
__raw_write(64, q)

#undef __raw_read
#undef __raw_write

3808
/* These are untraced mmio-accessors that are only valid to be used inside
3809
 * critical sections inside IRQ handlers where forcewake is explicitly
3810 3811 3812 3813 3814
 * controlled.
 * Think twice, and think again, before using these.
 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
 * intel_uncore_forcewake_irqunlock().
 */
3815 3816
#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3817
#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3818 3819
#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)

3820 3821 3822 3823
/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
#define INTEL_BROADCAST_RGB_FULL 1
#define INTEL_BROADCAST_RGB_LIMITED 2
3824

3825
static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3826
{
3827
	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3828
		return VLV_VGACNTRL;
3829 3830
	else if (INTEL_INFO(dev)->gen >= 5)
		return CPU_VGACNTRL;
3831 3832 3833 3834
	else
		return VGACNTRL;
}

3835 3836 3837 3838 3839 3840 3841
static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
{
	unsigned long j = msecs_to_jiffies(m);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3842 3843 3844 3845 3846
static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
{
        return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
}

3847 3848 3849 3850 3851 3852 3853 3854
static inline unsigned long
timespec_to_jiffies_timeout(const struct timespec *value)
{
	unsigned long j = timespec_to_jiffies(value);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3855 3856 3857 3858 3859 3860 3861 3862 3863
/*
 * If you need to wait X milliseconds between events A and B, but event B
 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
 * when event A happened, then just before event B you call this function and
 * pass the timestamp as the first argument, and X as the second argument.
 */
static inline void
wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
{
3864
	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3865 3866 3867 3868 3869 3870 3871 3872 3873 3874

	/*
	 * Don't re-read the value of "jiffies" every time since it may change
	 * behind our back and break the math.
	 */
	tmp_jiffies = jiffies;
	target_jiffies = timestamp_jiffies +
			 msecs_to_jiffies_timeout(to_wait_ms);

	if (time_after(target_jiffies, tmp_jiffies)) {
3875 3876 3877 3878
		remaining_jiffies = target_jiffies - tmp_jiffies;
		while (remaining_jiffies)
			remaining_jiffies =
			    schedule_timeout_uninterruptible(remaining_jiffies);
3879 3880
	}
}
3881 3882
static inline bool __i915_request_irq_complete(struct drm_i915_gem_request *req)
{
3883 3884
	struct intel_engine_cs *engine = req->engine;

3885 3886 3887 3888 3889 3890
	/* Before we do the heavier coherent read of the seqno,
	 * check the value (hopefully) in the CPU cacheline.
	 */
	if (i915_gem_request_completed(req))
		return true;

3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901
	/* Ensure our read of the seqno is coherent so that we
	 * do not "miss an interrupt" (i.e. if this is the last
	 * request and the seqno write from the GPU is not visible
	 * by the time the interrupt fires, we will see that the
	 * request is incomplete and go back to sleep awaiting
	 * another interrupt that will never come.)
	 *
	 * Strictly, we only need to do this once after an interrupt,
	 * but it is easier and safer to do it every time the waiter
	 * is woken.
	 */
3902
	if (engine->irq_seqno_barrier &&
3903
	    rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current &&
3904
	    cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) {
3905 3906
		struct task_struct *tsk;

3907 3908 3909 3910 3911 3912 3913 3914 3915 3916 3917 3918
		/* The ordering of irq_posted versus applying the barrier
		 * is crucial. The clearing of the current irq_posted must
		 * be visible before we perform the barrier operation,
		 * such that if a subsequent interrupt arrives, irq_posted
		 * is reasserted and our task rewoken (which causes us to
		 * do another __i915_request_irq_complete() immediately
		 * and reapply the barrier). Conversely, if the clear
		 * occurs after the barrier, then an interrupt that arrived
		 * whilst we waited on the barrier would not trigger a
		 * barrier on the next pass, and the read may not see the
		 * seqno update.
		 */
3919
		engine->irq_seqno_barrier(engine);
3920 3921 3922 3923 3924 3925 3926 3927

		/* If we consume the irq, but we are no longer the bottom-half,
		 * the real bottom-half may not have serialised their own
		 * seqno check with the irq-barrier (i.e. may have inspected
		 * the seqno before we believe it coherent since they see
		 * irq_posted == false but we are still running).
		 */
		rcu_read_lock();
3928
		tsk = rcu_dereference(engine->breadcrumbs.irq_seqno_bh);
3929 3930 3931 3932 3933 3934 3935 3936 3937 3938
		if (tsk && tsk != current)
			/* Note that if the bottom-half is changed as we
			 * are sending the wake-up, the new bottom-half will
			 * be woken by whomever made the change. We only have
			 * to worry about when we steal the irq-posted for
			 * ourself.
			 */
			wake_up_process(tsk);
		rcu_read_unlock();

3939 3940 3941
		if (i915_gem_request_completed(req))
			return true;
	}
3942 3943 3944 3945 3946 3947 3948 3949 3950 3951 3952 3953 3954 3955 3956

	/* We need to check whether any gpu reset happened in between
	 * the request being submitted and now. If a reset has occurred,
	 * the seqno will have been advance past ours and our request
	 * is complete. If we are in the process of handling a reset,
	 * the request is effectively complete as the rendering will
	 * be discarded, but we need to return in order to drop the
	 * struct_mutex.
	 */
	if (i915_reset_in_progress(&req->i915->gpu_error))
		return true;

	return false;
}

3957 3958 3959
void i915_memcpy_init_early(struct drm_i915_private *dev_priv);
bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len);

3960 3961 3962 3963 3964
/* i915_mm.c */
int remap_io_mapping(struct vm_area_struct *vma,
		     unsigned long addr, unsigned long pfn, unsigned long size,
		     struct io_mapping *iomap);

3965 3966 3967 3968 3969
#define ptr_mask_bits(ptr) ({						\
	unsigned long __v = (unsigned long)(ptr);			\
	(typeof(ptr))(__v & PAGE_MASK);					\
})

3970 3971 3972 3973 3974 3975 3976 3977 3978
#define ptr_unpack_bits(ptr, bits) ({					\
	unsigned long __v = (unsigned long)(ptr);			\
	(bits) = __v & ~PAGE_MASK;					\
	(typeof(ptr))(__v & PAGE_MASK);					\
})

#define ptr_pack_bits(ptr, bits)					\
	((typeof(ptr))((unsigned long)(ptr) | (bits)))

3979 3980 3981 3982 3983 3984
#define fetch_and_zero(ptr) ({						\
	typeof(*ptr) __T = *(ptr);					\
	*(ptr) = (typeof(*ptr))0;					\
	__T;								\
})

L
Linus Torvalds 已提交
3985
#endif