i915_drv.h 116.8 KB
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/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
 */
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/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
 * All Rights Reserved.
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 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sub license, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial portions
 * of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
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 */
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#ifndef _I915_DRV_H_
#define _I915_DRV_H_

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#include <uapi/drm/i915_drm.h>
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#include <uapi/drm/drm_fourcc.h>
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#include <linux/io-mapping.h>
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/backlight.h>
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#include <linux/hashtable.h>
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#include <linux/intel-iommu.h>
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#include <linux/kref.h>
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#include <linux/pm_qos.h>
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#include <linux/shmem_fs.h>

#include <drm/drmP.h>
#include <drm/intel-gtt.h>
#include <drm/drm_legacy.h> /* for struct drm_dma_handle */
#include <drm/drm_gem.h>
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#include <drm/drm_auth.h>
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#include "i915_params.h"
#include "i915_reg.h"

#include "intel_bios.h"
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#include "intel_dpll_mgr.h"
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#include "intel_guc.h"
#include "intel_lrc.h"
#include "intel_ringbuffer.h"

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#include "i915_gem.h"
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#include "i915_gem_gtt.h"
#include "i915_gem_render_state.h"
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#include "i915_gem_request.h"
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#include "intel_gvt.h"

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/* General customization:
 */

#define DRIVER_NAME		"i915"
#define DRIVER_DESC		"Intel Graphics"
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#define DRIVER_DATE		"20160725"
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#undef WARN_ON
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/* Many gcc seem to no see through this and fall over :( */
#if 0
#define WARN_ON(x) ({ \
	bool __i915_warn_cond = (x); \
	if (__builtin_constant_p(__i915_warn_cond)) \
		BUILD_BUG_ON(__i915_warn_cond); \
	WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
#else
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#define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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#endif

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#undef WARN_ON_ONCE
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#define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
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#define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
			     (long) (x), __func__);
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/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
 * which may not necessarily be a user visible problem.  This will either
 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
 * enable distros and users to tailor their preferred amount of i915 abrt
 * spam.
 */
#define I915_STATE_WARN(condition, format...) ({			\
	int __ret_warn_on = !!(condition);				\
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	if (unlikely(__ret_warn_on))					\
		if (!WARN(i915.verbose_state_checks, format))		\
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			DRM_ERROR(format);				\
	unlikely(__ret_warn_on);					\
})

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#define I915_STATE_WARN_ON(x)						\
	I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
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bool __i915_inject_load_failure(const char *func, int line);
#define i915_inject_load_failure() \
	__i915_inject_load_failure(__func__, __LINE__)

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static inline const char *yesno(bool v)
{
	return v ? "yes" : "no";
}

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static inline const char *onoff(bool v)
{
	return v ? "on" : "off";
}

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enum pipe {
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	INVALID_PIPE = -1,
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	PIPE_A = 0,
	PIPE_B,
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	PIPE_C,
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	_PIPE_EDP,
	I915_MAX_PIPES = _PIPE_EDP
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};
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#define pipe_name(p) ((p) + 'A')
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enum transcoder {
	TRANSCODER_A = 0,
	TRANSCODER_B,
	TRANSCODER_C,
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	TRANSCODER_EDP,
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	TRANSCODER_DSI_A,
	TRANSCODER_DSI_C,
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	I915_MAX_TRANSCODERS
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};
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static inline const char *transcoder_name(enum transcoder transcoder)
{
	switch (transcoder) {
	case TRANSCODER_A:
		return "A";
	case TRANSCODER_B:
		return "B";
	case TRANSCODER_C:
		return "C";
	case TRANSCODER_EDP:
		return "EDP";
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	case TRANSCODER_DSI_A:
		return "DSI A";
	case TRANSCODER_DSI_C:
		return "DSI C";
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	default:
		return "<invalid>";
	}
}
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static inline bool transcoder_is_dsi(enum transcoder transcoder)
{
	return transcoder == TRANSCODER_DSI_A || transcoder == TRANSCODER_DSI_C;
}

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/*
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 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
 * number of planes per CRTC.  Not all platforms really have this many planes,
 * which means some arrays of size I915_MAX_PLANES may have unused entries
 * between the topmost sprite plane and the cursor plane.
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 */
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enum plane {
	PLANE_A = 0,
	PLANE_B,
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	PLANE_C,
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	PLANE_CURSOR,
	I915_MAX_PLANES,
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};
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#define plane_name(p) ((p) + 'A')
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#define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
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enum port {
	PORT_A = 0,
	PORT_B,
	PORT_C,
	PORT_D,
	PORT_E,
	I915_MAX_PORTS
};
#define port_name(p) ((p) + 'A')

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#define I915_NUM_PHYS_VLV 2
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enum dpio_channel {
	DPIO_CH0,
	DPIO_CH1
};

enum dpio_phy {
	DPIO_PHY0,
	DPIO_PHY1
};

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enum intel_display_power_domain {
	POWER_DOMAIN_PIPE_A,
	POWER_DOMAIN_PIPE_B,
	POWER_DOMAIN_PIPE_C,
	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
	POWER_DOMAIN_TRANSCODER_A,
	POWER_DOMAIN_TRANSCODER_B,
	POWER_DOMAIN_TRANSCODER_C,
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	POWER_DOMAIN_TRANSCODER_EDP,
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	POWER_DOMAIN_TRANSCODER_DSI_A,
	POWER_DOMAIN_TRANSCODER_DSI_C,
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	POWER_DOMAIN_PORT_DDI_A_LANES,
	POWER_DOMAIN_PORT_DDI_B_LANES,
	POWER_DOMAIN_PORT_DDI_C_LANES,
	POWER_DOMAIN_PORT_DDI_D_LANES,
	POWER_DOMAIN_PORT_DDI_E_LANES,
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	POWER_DOMAIN_PORT_DSI,
	POWER_DOMAIN_PORT_CRT,
	POWER_DOMAIN_PORT_OTHER,
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	POWER_DOMAIN_VGA,
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	POWER_DOMAIN_AUDIO,
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	POWER_DOMAIN_PLLS,
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	POWER_DOMAIN_AUX_A,
	POWER_DOMAIN_AUX_B,
	POWER_DOMAIN_AUX_C,
	POWER_DOMAIN_AUX_D,
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	POWER_DOMAIN_GMBUS,
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	POWER_DOMAIN_MODESET,
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	POWER_DOMAIN_INIT,
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	POWER_DOMAIN_NUM,
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};

#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
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#define POWER_DOMAIN_TRANSCODER(tran) \
	((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
	 (tran) + POWER_DOMAIN_TRANSCODER_A)
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enum hpd_pin {
	HPD_NONE = 0,
	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
	HPD_CRT,
	HPD_SDVO_B,
	HPD_SDVO_C,
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	HPD_PORT_A,
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	HPD_PORT_B,
	HPD_PORT_C,
	HPD_PORT_D,
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	HPD_PORT_E,
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	HPD_NUM_PINS
};

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#define for_each_hpd_pin(__pin) \
	for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)

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struct i915_hotplug {
	struct work_struct hotplug_work;

	struct {
		unsigned long last_jiffies;
		int count;
		enum {
			HPD_ENABLED = 0,
			HPD_DISABLED = 1,
			HPD_MARK_DISABLED = 2
		} state;
	} stats[HPD_NUM_PINS];
	u32 event_bits;
	struct delayed_work reenable_work;

	struct intel_digital_port *irq_port[I915_MAX_PORTS];
	u32 long_port_mask;
	u32 short_port_mask;
	struct work_struct dig_port_work;

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	struct work_struct poll_init_work;
	bool poll_enabled;

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	/*
	 * if we get a HPD irq from DP and a HPD irq from non-DP
	 * the non-DP HPD could block the workqueue on a mode config
	 * mutex getting, that userspace may have taken. However
	 * userspace is waiting on the DP workqueue to run which is
	 * blocked behind the non-DP one.
	 */
	struct workqueue_struct *dp_wq;
};

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#define I915_GEM_GPU_DOMAINS \
	(I915_GEM_DOMAIN_RENDER | \
	 I915_GEM_DOMAIN_SAMPLER | \
	 I915_GEM_DOMAIN_COMMAND | \
	 I915_GEM_DOMAIN_INSTRUCTION | \
	 I915_GEM_DOMAIN_VERTEX)
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#define for_each_pipe(__dev_priv, __p) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
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#define for_each_pipe_masked(__dev_priv, __p, __mask) \
	for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
		for_each_if ((__mask) & (1 << (__p)))
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#define for_each_plane(__dev_priv, __pipe, __p)				\
	for ((__p) = 0;							\
	     (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1;	\
	     (__p)++)
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#define for_each_sprite(__dev_priv, __p, __s)				\
	for ((__s) = 0;							\
	     (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)];	\
	     (__s)++)
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#define for_each_port_masked(__port, __ports_mask) \
	for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)	\
		for_each_if ((__ports_mask) & (1 << (__port)))

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#define for_each_crtc(dev, crtc) \
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	list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
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#define for_each_intel_plane(dev, intel_plane) \
	list_for_each_entry(intel_plane,			\
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			    &(dev)->mode_config.plane_list,	\
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			    base.head)

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#define for_each_intel_plane_mask(dev, intel_plane, plane_mask)		\
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	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
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			    base.head)					\
		for_each_if ((plane_mask) &				\
			     (1 << drm_plane_index(&intel_plane->base)))

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#define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane)	\
	list_for_each_entry(intel_plane,				\
			    &(dev)->mode_config.plane_list,		\
			    base.head)					\
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		for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
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#define for_each_intel_crtc(dev, intel_crtc)				\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)
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#define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask)		\
	list_for_each_entry(intel_crtc,					\
			    &(dev)->mode_config.crtc_list,		\
			    base.head)					\
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		for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))

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#define for_each_intel_encoder(dev, intel_encoder)		\
	list_for_each_entry(intel_encoder,			\
			    &(dev)->mode_config.encoder_list,	\
			    base.head)

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#define for_each_intel_connector(dev, intel_connector)		\
	list_for_each_entry(intel_connector,			\
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			    &(dev)->mode_config.connector_list,	\
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			    base.head)

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#define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
	list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
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		for_each_if ((intel_encoder)->base.crtc == (__crtc))
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#define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
	list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
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		for_each_if ((intel_connector)->base.encoder == (__encoder))
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#define for_each_power_domain(domain, mask)				\
	for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)	\
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		for_each_if ((1 << (domain)) & (mask))
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struct drm_i915_private;
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struct i915_mm_struct;
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struct i915_mmu_object;
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struct drm_i915_file_private {
	struct drm_i915_private *dev_priv;
	struct drm_file *file;

	struct {
		spinlock_t lock;
		struct list_head request_list;
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/* 20ms is a fairly arbitrary limit (greater than the average frame time)
 * chosen to prevent the CPU getting more than a frame ahead of the GPU
 * (when using lax throttling for the frontbuffer). We also use it to
 * offer free GPU waitboosts for severely congested workloads.
 */
#define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
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	} mm;
	struct idr context_idr;

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	struct intel_rps_client {
		struct list_head link;
		unsigned boosts;
	} rps;
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	unsigned int bsd_engine;
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};

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/* Used by dp and fdi links */
struct intel_link_m_n {
	uint32_t	tu;
	uint32_t	gmch_m;
	uint32_t	gmch_n;
	uint32_t	link_m;
	uint32_t	link_n;
};

void intel_link_compute_m_n(int bpp, int nlanes,
			    int pixel_clock, int link_clock,
			    struct intel_link_m_n *m_n);

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/* Interface history:
 *
 * 1.1: Original.
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 * 1.2: Add Power Management
 * 1.3: Add vblank support
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 * 1.4: Fix cmdbuffer path, add heap destroy
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 * 1.5: Add vblank pipe configuration
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 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 *      - Support vertical blank on secondary display pipe
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 */
#define DRIVER_MAJOR		1
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#define DRIVER_MINOR		6
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#define DRIVER_PATCHLEVEL	0

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struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
struct opregion_asle;

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struct intel_opregion {
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	struct opregion_header *header;
	struct opregion_acpi *acpi;
	struct opregion_swsci *swsci;
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	u32 swsci_gbda_sub_functions;
	u32 swsci_sbcb_sub_functions;
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	struct opregion_asle *asle;
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	void *rvda;
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	const void *vbt;
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	u32 vbt_size;
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	u32 *lid_state;
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	struct work_struct asle_work;
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};
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#define OPREGION_SIZE            (8*1024)
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struct intel_overlay;
struct intel_overlay_error_state;

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#define I915_FENCE_REG_NONE -1
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#define I915_MAX_NUM_FENCES 32
/* 32 fences + sign bit for FENCE_REG_NONE */
#define I915_MAX_NUM_FENCE_BITS 6
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struct drm_i915_fence_reg {
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	struct list_head lru_list;
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	struct drm_i915_gem_object *obj;
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	int pin_count;
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};
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struct sdvo_device_mapping {
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	u8 initialized;
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	u8 dvo_port;
	u8 slave_addr;
	u8 dvo_wiring;
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	u8 i2c_pin;
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	u8 ddc_pin;
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};

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struct intel_display_error_state;

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struct drm_i915_error_state {
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	struct kref ref;
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	struct timeval time;

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	char error_msg[128];
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	bool simulated;
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	int iommu;
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	u32 reset_count;
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	u32 suspend_count;
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	/* Generic register state */
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	u32 eir;
	u32 pgtbl_er;
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	u32 ier;
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	u32 gtier[4];
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	u32 ccid;
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	u32 derrmr;
	u32 forcewake;
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	u32 error; /* gen6+ */
	u32 err_int; /* gen7 */
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	u32 fault_data0; /* gen8, gen9 */
	u32 fault_data1; /* gen8, gen9 */
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	u32 done_reg;
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	u32 gac_eco;
	u32 gam_ecochk;
	u32 gab_ctl;
	u32 gfx_mode;
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	u32 extra_instdone[I915_NUM_INSTDONE_REG];
	u64 fence[I915_MAX_NUM_FENCES];
	struct intel_overlay_error_state *overlay;
	struct intel_display_error_state *display;
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	struct drm_i915_error_object *semaphore_obj;
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	struct drm_i915_error_engine {
		int engine_id;
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		/* Software tracked state */
		bool waiting;
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		int num_waiters;
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		int hangcheck_score;
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		enum intel_engine_hangcheck_action hangcheck_action;
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		int num_requests;

		/* our own tracking of ring head and tail */
		u32 cpu_ring_head;
		u32 cpu_ring_tail;

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		u32 last_seqno;
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		u32 semaphore_seqno[I915_NUM_ENGINES - 1];
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		/* Register state */
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		u32 start;
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		u32 tail;
		u32 head;
		u32 ctl;
		u32 hws;
		u32 ipeir;
		u32 ipehr;
		u32 instdone;
		u32 bbstate;
		u32 instpm;
		u32 instps;
		u32 seqno;
		u64 bbaddr;
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		u64 acthd;
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		u32 fault_reg;
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		u64 faddr;
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		u32 rc_psmi; /* sleep state */
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		u32 semaphore_mboxes[I915_NUM_ENGINES - 1];
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		struct drm_i915_error_object {
			int page_count;
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			u64 gtt_offset;
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			u32 *pages[0];
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		} *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
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		struct drm_i915_error_object *wa_ctx;

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		struct drm_i915_error_request {
			long jiffies;
			u32 seqno;
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			u32 tail;
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		} *requests;
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		struct drm_i915_error_waiter {
			char comm[TASK_COMM_LEN];
			pid_t pid;
			u32 seqno;
		} *waiters;

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		struct {
			u32 gfx_mode;
			union {
				u64 pdp[4];
				u32 pp_dir_base;
			};
		} vm_info;
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		pid_t pid;
		char comm[TASK_COMM_LEN];
579
	} engine[I915_NUM_ENGINES];
580

581
	struct drm_i915_error_buffer {
582
		u32 size;
583
		u32 name;
584
		u32 rseqno[I915_NUM_ENGINES], wseqno;
585
		u64 gtt_offset;
586 587
		u32 read_domains;
		u32 write_domain;
588
		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
589 590 591 592
		s32 pinned:2;
		u32 tiling:2;
		u32 dirty:1;
		u32 purgeable:1;
593
		u32 userptr:1;
594
		s32 engine:4;
595
		u32 cache_level:3;
596
	} **active_bo, **pinned_bo;
597

598
	u32 *active_bo_count, *pinned_bo_count;
599
	u32 vm_count;
600 601
};

602
struct intel_connector;
603
struct intel_encoder;
604
struct intel_crtc_state;
605
struct intel_initial_plane_config;
606
struct intel_crtc;
607 608
struct intel_limit;
struct dpll;
609

610 611 612
struct drm_i915_display_funcs {
	int (*get_display_clock_speed)(struct drm_device *dev);
	int (*get_fifo_size)(struct drm_device *dev, int plane);
613
	int (*compute_pipe_wm)(struct intel_crtc_state *cstate);
614 615 616 617 618
	int (*compute_intermediate_wm)(struct drm_device *dev,
				       struct intel_crtc *intel_crtc,
				       struct intel_crtc_state *newstate);
	void (*initial_watermarks)(struct intel_crtc_state *cstate);
	void (*optimize_watermarks)(struct intel_crtc_state *cstate);
619
	int (*compute_global_watermarks)(struct drm_atomic_state *state);
620
	void (*update_wm)(struct drm_crtc *crtc);
621 622
	int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
	void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
623 624 625
	/* Returns the active state of the crtc, and if the crtc is active,
	 * fills out the pipe-config with the hw state. */
	bool (*get_pipe_config)(struct intel_crtc *,
626
				struct intel_crtc_state *);
627 628
	void (*get_initial_plane_config)(struct intel_crtc *,
					 struct intel_initial_plane_config *);
629 630
	int (*crtc_compute_clock)(struct intel_crtc *crtc,
				  struct intel_crtc_state *crtc_state);
631 632
	void (*crtc_enable)(struct drm_crtc *crtc);
	void (*crtc_disable)(struct drm_crtc *crtc);
633 634
	void (*audio_codec_enable)(struct drm_connector *connector,
				   struct intel_encoder *encoder,
635
				   const struct drm_display_mode *adjusted_mode);
636
	void (*audio_codec_disable)(struct intel_encoder *encoder);
637
	void (*fdi_link_train)(struct drm_crtc *crtc);
638
	void (*init_clock_gating)(struct drm_device *dev);
639 640 641 642 643
	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
			  struct drm_framebuffer *fb,
			  struct drm_i915_gem_object *obj,
			  struct drm_i915_gem_request *req,
			  uint32_t flags);
644
	void (*hpd_irq_setup)(struct drm_i915_private *dev_priv);
645 646 647 648 649
	/* clock updates for mode set */
	/* cursor updates */
	/* render clock increase/decrease */
	/* display clock increase/decrease */
	/* pll clock increase/decrease */
650

651 652
	void (*load_csc_matrix)(struct drm_crtc_state *crtc_state);
	void (*load_luts)(struct drm_crtc_state *crtc_state);
653 654
};

655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671
enum forcewake_domain_id {
	FW_DOMAIN_ID_RENDER = 0,
	FW_DOMAIN_ID_BLITTER,
	FW_DOMAIN_ID_MEDIA,

	FW_DOMAIN_ID_COUNT
};

enum forcewake_domains {
	FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
	FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
	FORCEWAKE_MEDIA	= (1 << FW_DOMAIN_ID_MEDIA),
	FORCEWAKE_ALL = (FORCEWAKE_RENDER |
			 FORCEWAKE_BLITTER |
			 FORCEWAKE_MEDIA)
};

672 673 674 675 676 677 678
#define FW_REG_READ  (1)
#define FW_REG_WRITE (2)

enum forcewake_domains
intel_uncore_forcewake_for_reg(struct drm_i915_private *dev_priv,
			       i915_reg_t reg, unsigned int op);

679
struct intel_uncore_funcs {
680
	void (*force_wake_get)(struct drm_i915_private *dev_priv,
681
							enum forcewake_domains domains);
682
	void (*force_wake_put)(struct drm_i915_private *dev_priv,
683
							enum forcewake_domains domains);
684

685 686 687 688
	uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
	uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
689

690
	void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
691
				uint8_t val, bool trace);
692
	void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
693
				uint16_t val, bool trace);
694
	void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
695
				uint32_t val, bool trace);
696
	void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
697
				uint64_t val, bool trace);
698 699
};

700 701 702 703 704 705
struct intel_uncore {
	spinlock_t lock; /** lock is also taken in irq contexts. */

	struct intel_uncore_funcs funcs;

	unsigned fifo_count;
706
	enum forcewake_domains fw_domains;
707 708 709

	struct intel_uncore_forcewake_domain {
		struct drm_i915_private *i915;
710
		enum forcewake_domain_id id;
711
		enum forcewake_domains mask;
712
		unsigned wake_count;
713
		struct hrtimer timer;
714
		i915_reg_t reg_set;
715 716
		u32 val_set;
		u32 val_clear;
717 718
		i915_reg_t reg_ack;
		i915_reg_t reg_post;
719
		u32 val_reset;
720
	} fw_domain[FW_DOMAIN_ID_COUNT];
721 722

	int unclaimed_mmio_check;
723 724 725
};

/* Iterate over initialised fw domains */
726 727 728 729 730 731 732 733
#define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
	for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
	     (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
	     (domain__)++) \
		for_each_if ((mask__) & (domain__)->mask)

#define for_each_fw_domain(domain__, dev_priv__) \
	for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
734

735 736 737 738
#define CSR_VERSION(major, minor)	((major) << 16 | (minor))
#define CSR_VERSION_MAJOR(version)	((version) >> 16)
#define CSR_VERSION_MINOR(version)	((version) & 0xffff)

739
struct intel_csr {
740
	struct work_struct work;
741
	const char *fw_path;
742
	uint32_t *dmc_payload;
743
	uint32_t dmc_fw_size;
744
	uint32_t version;
745
	uint32_t mmio_count;
746
	i915_reg_t mmioaddr[8];
747
	uint32_t mmiodata[8];
748
	uint32_t dc_state;
749
	uint32_t allowed_dc_mask;
750 751
};

752 753 754 755 756 757 758 759 760 761 762 763 764
#define DEV_INFO_FOR_EACH_FLAG(func, sep) \
	func(is_mobile) sep \
	func(is_i85x) sep \
	func(is_i915g) sep \
	func(is_i945gm) sep \
	func(is_g33) sep \
	func(need_gfx_hws) sep \
	func(is_g4x) sep \
	func(is_pineview) sep \
	func(is_broadwater) sep \
	func(is_crestline) sep \
	func(is_ivybridge) sep \
	func(is_valleyview) sep \
765
	func(is_cherryview) sep \
766
	func(is_haswell) sep \
767
	func(is_broadwell) sep \
768
	func(is_skylake) sep \
769
	func(is_broxton) sep \
770
	func(is_kabylake) sep \
771
	func(is_preliminary) sep \
772 773 774 775 776 777 778
	func(has_fbc) sep \
	func(has_pipe_cxsr) sep \
	func(has_hotplug) sep \
	func(cursor_needs_physical) sep \
	func(has_overlay) sep \
	func(overlay_needs_physical) sep \
	func(supports_tv) sep \
779
	func(has_llc) sep \
780
	func(has_snoop) sep \
781
	func(has_ddi) sep \
782 783
	func(has_fpga_dbg) sep \
	func(has_pooled_eu)
D
Daniel Vetter 已提交
784

785 786
#define DEFINE_FLAG(name) u8 name:1
#define SEP_SEMICOLON ;
D
Daniel Vetter 已提交
787

788
struct intel_device_info {
789
	u32 display_mmio_offset;
790
	u16 device_id;
791
	u8 num_pipes;
792
	u8 num_sprites[I915_MAX_PIPES];
793
	u8 gen;
794
	u16 gen_mask;
795
	u8 ring_mask; /* Rings supported by the HW */
796
	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
797 798 799 800
	/* Register offsets for the various display pipes and transcoders */
	int pipe_offsets[I915_MAX_TRANSCODERS];
	int trans_offsets[I915_MAX_TRANSCODERS];
	int palette_offsets[I915_MAX_PIPES];
801
	int cursor_offsets[I915_MAX_PIPES];
802 803 804 805 806 807 808

	/* Slice/subslice/EU info */
	u8 slice_total;
	u8 subslice_total;
	u8 subslice_per_slice;
	u8 eu_total;
	u8 eu_per_subslice;
809
	u8 min_eu_in_pool;
810 811
	/* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
	u8 subslice_7eu[3];
812 813 814
	u8 has_slice_pg:1;
	u8 has_subslice_pg:1;
	u8 has_eu_pg:1;
815 816 817 818 819

	struct color_luts {
		u16 degamma_lut_size;
		u16 gamma_lut_size;
	} color;
820 821
};

822 823 824
#undef DEFINE_FLAG
#undef SEP_SEMICOLON

825 826
enum i915_cache_level {
	I915_CACHE_NONE = 0,
827 828 829 830 831
	I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
	I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
			      caches, eg sampler/render caches, and the
			      large Last-Level-Cache. LLC is coherent with
			      the CPU, but L3 is only visible to the GPU. */
832
	I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
833 834
};

835 836 837 838 839 840
struct i915_ctx_hang_stats {
	/* This context had batch pending when hang was declared */
	unsigned batch_pending;

	/* This context had batch active when hang was declared */
	unsigned batch_active;
841 842 843 844

	/* Time when this context was last blamed for a GPU reset */
	unsigned long guilty_ts;

845 846 847 848 849
	/* If the contexts causes a second GPU hang within this time,
	 * it is permanently banned from submitting any more work.
	 */
	unsigned long ban_period_seconds;

850 851
	/* This context is banned to submit more work */
	bool banned;
852
};
853 854

/* This must match up with the value previously used for execbuf2.rsvd1. */
855
#define DEFAULT_CONTEXT_HANDLE 0
856

857
/**
858
 * struct i915_gem_context - as the name implies, represents a context.
859 860 861
 * @ref: reference count.
 * @user_handle: userspace tracking identity for this context.
 * @remap_slice: l3 row remapping information.
862 863
 * @flags: context specific flags:
 *         CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
864 865 866 867
 * @file_priv: filp associated with this context (NULL for global default
 *	       context).
 * @hang_stats: information about the role of this context in possible GPU
 *		hangs.
868
 * @ppgtt: virtual memory space used by this context.
869 870 871 872 873 874 875
 * @legacy_hw_ctx: render context backing object and whether it is correctly
 *                initialized (legacy ring submission mechanism only).
 * @link: link in the global list of contexts.
 *
 * Contexts are memory images used by the hardware to store copies of their
 * internal state.
 */
876
struct i915_gem_context {
877
	struct kref ref;
878
	struct drm_i915_private *i915;
879
	struct drm_i915_file_private *file_priv;
880
	struct i915_hw_ppgtt *ppgtt;
881

882 883
	struct i915_ctx_hang_stats hang_stats;

884
	/* Unique identifier for this context, used by the hw for tracking */
885
	unsigned long flags;
886 887
#define CONTEXT_NO_ZEROMAP		BIT(0)
#define CONTEXT_NO_ERROR_CAPTURE	BIT(1)
888
	unsigned hw_id;
889
	u32 user_handle;
890

891 892
	u32 ggtt_alignment;

893
	struct intel_context {
894
		struct drm_i915_gem_object *state;
895
		struct intel_ring *ring;
896
		struct i915_vma *lrc_vma;
897
		uint32_t *lrc_reg_state;
898 899
		u64 lrc_desc;
		int pin_count;
900
		bool initialised;
901
	} engine[I915_NUM_ENGINES];
902
	u32 ring_size;
903
	u32 desc_template;
904
	struct atomic_notifier_head status_notifier;
905
	bool execlists_force_single_submission;
906

907
	struct list_head link;
908 909

	u8 remap_slice;
910
	bool closed:1;
911 912
};

913 914 915 916 917
enum fb_op_origin {
	ORIGIN_GTT,
	ORIGIN_CPU,
	ORIGIN_CS,
	ORIGIN_FLIP,
918
	ORIGIN_DIRTYFB,
919 920
};

921
struct intel_fbc {
P
Paulo Zanoni 已提交
922 923 924
	/* This is always the inner lock when overlapping with struct_mutex and
	 * it's the outer lock when overlapping with stolen_lock. */
	struct mutex lock;
B
Ben Widawsky 已提交
925
	unsigned threshold;
926 927
	unsigned int possible_framebuffer_bits;
	unsigned int busy_bits;
928
	unsigned int visible_pipes_mask;
929
	struct intel_crtc *crtc;
930

931
	struct drm_mm_node compressed_fb;
932 933
	struct drm_mm_node *compressed_llb;

934 935
	bool false_color;

936
	bool enabled;
937
	bool active;
938

939 940 941 942 943 944 945 946 947 948 949 950 951 952 953 954 955 956 957 958 959 960
	struct intel_fbc_state_cache {
		struct {
			unsigned int mode_flags;
			uint32_t hsw_bdw_pixel_rate;
		} crtc;

		struct {
			unsigned int rotation;
			int src_w;
			int src_h;
			bool visible;
		} plane;

		struct {
			u64 ilk_ggtt_offset;
			uint32_t pixel_format;
			unsigned int stride;
			int fence_reg;
			unsigned int tiling_mode;
		} fb;
	} state_cache;

961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977
	struct intel_fbc_reg_params {
		struct {
			enum pipe pipe;
			enum plane plane;
			unsigned int fence_y_offset;
		} crtc;

		struct {
			u64 ggtt_offset;
			uint32_t pixel_format;
			unsigned int stride;
			int fence_reg;
		} fb;

		int cfb_size;
	} params;

978
	struct intel_fbc_work {
979
		bool scheduled;
980
		u32 scheduled_vblank;
981 982
		struct work_struct work;
	} work;
983

984
	const char *no_fbc_reason;
985 986
};

987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001
/**
 * HIGH_RR is the highest eDP panel refresh rate read from EDID
 * LOW_RR is the lowest eDP panel refresh rate found from EDID
 * parsing for same resolution.
 */
enum drrs_refresh_rate_type {
	DRRS_HIGH_RR,
	DRRS_LOW_RR,
	DRRS_MAX_RR, /* RR count */
};

enum drrs_support_type {
	DRRS_NOT_SUPPORTED = 0,
	STATIC_DRRS_SUPPORT = 1,
	SEAMLESS_DRRS_SUPPORT = 2
1002 1003
};

1004
struct intel_dp;
1005 1006 1007 1008 1009 1010 1011 1012 1013
struct i915_drrs {
	struct mutex mutex;
	struct delayed_work work;
	struct intel_dp *dp;
	unsigned busy_frontbuffer_bits;
	enum drrs_refresh_rate_type refresh_rate_type;
	enum drrs_support_type type;
};

R
Rodrigo Vivi 已提交
1014
struct i915_psr {
1015
	struct mutex lock;
R
Rodrigo Vivi 已提交
1016 1017
	bool sink_support;
	bool source_ok;
1018
	struct intel_dp *enabled;
1019 1020
	bool active;
	struct delayed_work work;
1021
	unsigned busy_frontbuffer_bits;
1022 1023
	bool psr2_support;
	bool aux_frame_sync;
1024
	bool link_standby;
1025
};
1026

1027
enum intel_pch {
1028
	PCH_NONE = 0,	/* No PCH present */
1029 1030
	PCH_IBX,	/* Ibexpeak PCH */
	PCH_CPT,	/* Cougarpoint PCH */
1031
	PCH_LPT,	/* Lynxpoint PCH */
1032
	PCH_SPT,        /* Sunrisepoint PCH */
1033
	PCH_KBP,        /* Kabypoint PCH */
B
Ben Widawsky 已提交
1034
	PCH_NOP,
1035 1036
};

1037 1038 1039 1040 1041
enum intel_sbi_destination {
	SBI_ICLK,
	SBI_MPHY,
};

1042
#define QUIRK_PIPEA_FORCE (1<<0)
1043
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
1044
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
1045
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
1046
#define QUIRK_PIPEB_FORCE (1<<4)
1047
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1048

1049
struct intel_fbdev;
1050
struct intel_fbc_work;
1051

1052 1053
struct intel_gmbus {
	struct i2c_adapter adapter;
1054
#define GMBUS_FORCE_BIT_RETRY (1U << 31)
1055
	u32 force_bit;
1056
	u32 reg0;
1057
	i915_reg_t gpio_reg;
1058
	struct i2c_algo_bit_data bit_algo;
1059 1060 1061
	struct drm_i915_private *dev_priv;
};

1062
struct i915_suspend_saved_registers {
1063
	u32 saveDSPARB;
J
Jesse Barnes 已提交
1064
	u32 saveLVDS;
1065 1066
	u32 savePP_ON_DELAYS;
	u32 savePP_OFF_DELAYS;
J
Jesse Barnes 已提交
1067 1068 1069
	u32 savePP_ON;
	u32 savePP_OFF;
	u32 savePP_CONTROL;
1070
	u32 savePP_DIVISOR;
J
Jesse Barnes 已提交
1071
	u32 saveFBC_CONTROL;
1072 1073
	u32 saveCACHE_MODE_0;
	u32 saveMI_ARB_STATE;
J
Jesse Barnes 已提交
1074 1075
	u32 saveSWF0[16];
	u32 saveSWF1[16];
1076
	u32 saveSWF3[3];
1077
	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1078
	u32 savePCH_PORT_HOTPLUG;
1079
	u16 saveGCDGMBUS;
1080
};
1081

1082 1083 1084 1085 1086 1087 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 1103 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 1135 1136 1137 1138 1139
struct vlv_s0ix_state {
	/* GAM */
	u32 wr_watermark;
	u32 gfx_prio_ctrl;
	u32 arb_mode;
	u32 gfx_pend_tlb0;
	u32 gfx_pend_tlb1;
	u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
	u32 media_max_req_count;
	u32 gfx_max_req_count;
	u32 render_hwsp;
	u32 ecochk;
	u32 bsd_hwsp;
	u32 blt_hwsp;
	u32 tlb_rd_addr;

	/* MBC */
	u32 g3dctl;
	u32 gsckgctl;
	u32 mbctl;

	/* GCP */
	u32 ucgctl1;
	u32 ucgctl3;
	u32 rcgctl1;
	u32 rcgctl2;
	u32 rstctl;
	u32 misccpctl;

	/* GPM */
	u32 gfxpause;
	u32 rpdeuhwtc;
	u32 rpdeuc;
	u32 ecobus;
	u32 pwrdwnupctl;
	u32 rp_down_timeout;
	u32 rp_deucsw;
	u32 rcubmabdtmr;
	u32 rcedata;
	u32 spare2gh;

	/* Display 1 CZ domain */
	u32 gt_imr;
	u32 gt_ier;
	u32 pm_imr;
	u32 pm_ier;
	u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];

	/* GT SA CZ domain */
	u32 tilectl;
	u32 gt_fifoctl;
	u32 gtlc_wake_ctrl;
	u32 gtlc_survive;
	u32 pmwgicz;

	/* Display 2 CZ domain */
	u32 gu_ctl0;
	u32 gu_ctl1;
1140
	u32 pcbr;
1141 1142 1143
	u32 clock_gate_dis2;
};

1144 1145 1146 1147
struct intel_rps_ei {
	u32 cz_clock;
	u32 render_c0;
	u32 media_c0;
1148 1149
};

1150
struct intel_gen6_power_mgmt {
I
Imre Deak 已提交
1151 1152 1153 1154
	/*
	 * work, interrupts_enabled and pm_iir are protected by
	 * dev_priv->irq_lock
	 */
1155
	struct work_struct work;
I
Imre Deak 已提交
1156
	bool interrupts_enabled;
1157
	u32 pm_iir;
1158

1159 1160
	u32 pm_intr_keep;

1161 1162 1163 1164 1165 1166 1167 1168 1169 1170 1171 1172 1173 1174 1175
	/* Frequencies are stored in potentially platform dependent multiples.
	 * In other words, *_freq needs to be multiplied by X to be interesting.
	 * Soft limits are those which are used for the dynamic reclocking done
	 * by the driver (raise frequencies under heavy loads, and lower for
	 * lighter loads). Hard limits are those imposed by the hardware.
	 *
	 * A distinction is made for overclocking, which is never enabled by
	 * default, and is considered to be above the hard limit if it's
	 * possible at all.
	 */
	u8 cur_freq;		/* Current frequency (cached, may not == HW) */
	u8 min_freq_softlimit;	/* Minimum frequency permitted by the driver */
	u8 max_freq_softlimit;	/* Max frequency permitted by the driver */
	u8 max_freq;		/* Maximum frequency, RP0 if not overclocking */
	u8 min_freq;		/* AKA RPn. Minimum frequency */
1176
	u8 boost_freq;		/* Frequency to request when wait boosting */
1177
	u8 idle_freq;		/* Frequency to request when we are idle */
1178 1179 1180
	u8 efficient_freq;	/* AKA RPe. Pre-determined balanced frequency */
	u8 rp1_freq;		/* "less than" RP0 power/freqency */
	u8 rp0_freq;		/* Non-overclocked max frequency. */
1181
	u16 gpll_ref_freq;	/* vlv/chv GPLL reference frequency */
1182

1183 1184 1185
	u8 up_threshold; /* Current %busy required to uplock */
	u8 down_threshold; /* Current %busy required to downclock */

1186 1187 1188
	int last_adj;
	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;

1189 1190 1191 1192
	spinlock_t client_lock;
	struct list_head clients;
	bool client_boost;

1193
	bool enabled;
1194
	struct delayed_work autoenable_work;
1195
	unsigned boosts;
1196

1197 1198 1199
	/* manual wa residency calculations */
	struct intel_rps_ei up_ei, down_ei;

1200 1201
	/*
	 * Protects RPS/RC6 register access and PCU communication.
1202 1203 1204
	 * Must be taken after struct_mutex if nested. Note that
	 * this lock may be held for long periods of time when
	 * talking to hw - so only take it when talking to hw!
1205 1206
	 */
	struct mutex hw_lock;
1207 1208
};

D
Daniel Vetter 已提交
1209 1210 1211
/* defined intel_pm.c */
extern spinlock_t mchdev_lock;

1212 1213 1214 1215 1216 1217 1218 1219 1220 1221 1222
struct intel_ilk_power_mgmt {
	u8 cur_delay;
	u8 min_delay;
	u8 max_delay;
	u8 fmax;
	u8 fstart;

	u64 last_count1;
	unsigned long last_time1;
	unsigned long chipset_power;
	u64 last_count2;
1223
	u64 last_time2;
1224 1225 1226 1227 1228 1229 1230
	unsigned long gfx_power;
	u8 corr;

	int c_m;
	int r_t;
};

1231 1232 1233 1234 1235 1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 1247 1248 1249 1250 1251 1252 1253 1254 1255 1256 1257 1258 1259 1260
struct drm_i915_private;
struct i915_power_well;

struct i915_power_well_ops {
	/*
	 * Synchronize the well's hw state to match the current sw state, for
	 * example enable/disable it based on the current refcount. Called
	 * during driver init and resume time, possibly after first calling
	 * the enable/disable handlers.
	 */
	void (*sync_hw)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/*
	 * Enable the well and resources that depend on it (for example
	 * interrupts located on the well). Called after the 0->1 refcount
	 * transition.
	 */
	void (*enable)(struct drm_i915_private *dev_priv,
		       struct i915_power_well *power_well);
	/*
	 * Disable the well and resources that depend on it. Called after
	 * the 1->0 refcount transition.
	 */
	void (*disable)(struct drm_i915_private *dev_priv,
			struct i915_power_well *power_well);
	/* Returns the hw enabled state. */
	bool (*is_enabled)(struct drm_i915_private *dev_priv,
			   struct i915_power_well *power_well);
};

1261 1262
/* Power well structure for haswell */
struct i915_power_well {
1263
	const char *name;
1264
	bool always_on;
1265 1266
	/* power well enable/disable usage count */
	int count;
1267 1268
	/* cached hw enabled state */
	bool hw_enabled;
1269
	unsigned long domains;
1270
	unsigned long data;
1271
	const struct i915_power_well_ops *ops;
1272 1273
};

1274
struct i915_power_domains {
1275 1276 1277 1278 1279
	/*
	 * Power wells needed for initialization at driver init and suspend
	 * time are on. They are kept on until after the first modeset.
	 */
	bool init_power_on;
1280
	bool initializing;
1281
	int power_well_count;
1282

1283
	struct mutex lock;
1284
	int domain_use_count[POWER_DOMAIN_NUM];
1285
	struct i915_power_well *power_wells;
1286 1287
};

1288
#define MAX_L3_SLICES 2
1289
struct intel_l3_parity {
1290
	u32 *remap_info[MAX_L3_SLICES];
1291
	struct work_struct error_work;
1292
	int which_slice;
1293 1294
};

1295 1296 1297
struct i915_gem_mm {
	/** Memory allocator for GTT stolen memory */
	struct drm_mm stolen;
1298 1299 1300 1301
	/** Protects the usage of the GTT stolen memory allocator. This is
	 * always the inner lock when overlapping with struct_mutex. */
	struct mutex stolen_lock;

1302 1303 1304 1305 1306 1307 1308 1309 1310 1311 1312 1313 1314 1315 1316 1317
	/** List of all objects in gtt_space. Used to restore gtt
	 * mappings on resume */
	struct list_head bound_list;
	/**
	 * List of objects which are not bound to the GTT (thus
	 * are idle and not used by the GPU) but still have
	 * (presumably uncached) pages still attached.
	 */
	struct list_head unbound_list;

	/** Usable portion of the GTT for GEM */
	unsigned long stolen_base; /* limited to low memory (32-bit) */

	/** PPGTT used for aliasing the PPGTT with the GTT */
	struct i915_hw_ppgtt *aliasing_ppgtt;

1318
	struct notifier_block oom_notifier;
1319
	struct notifier_block vmap_notifier;
1320
	struct shrinker shrinker;
1321 1322 1323 1324 1325 1326 1327 1328 1329 1330 1331
	bool shrinker_no_lock_stealing;

	/** LRU list of objects with fence regs on them. */
	struct list_head fence_list;

	/**
	 * Are we in a non-interruptible section of code like
	 * modesetting?
	 */
	bool interruptible;

1332
	/* the indicator for dispatch video commands on two BSD rings */
1333
	unsigned int bsd_engine_dispatch_index;
1334

1335 1336 1337 1338 1339 1340
	/** Bit 6 swizzling required for X tiling */
	uint32_t bit_6_swizzle_x;
	/** Bit 6 swizzling required for Y tiling */
	uint32_t bit_6_swizzle_y;

	/* accounting, useful for userland debugging */
1341
	spinlock_t object_stat_lock;
1342 1343 1344 1345
	size_t object_memory;
	u32 object_count;
};

1346
struct drm_i915_error_state_buf {
1347
	struct drm_i915_private *i915;
1348 1349 1350 1351 1352 1353 1354 1355
	unsigned bytes;
	unsigned size;
	int err;
	u8 *buf;
	loff_t start;
	loff_t pos;
};

1356 1357 1358 1359 1360
struct i915_error_state_file_priv {
	struct drm_device *dev;
	struct drm_i915_error_state *error;
};

1361 1362 1363 1364
struct i915_gpu_error {
	/* For hangcheck timer */
#define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
#define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1365 1366 1367
	/* Hang gpu twice in this window and your context gets banned */
#define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)

1368
	struct delayed_work hangcheck_work;
1369 1370 1371 1372 1373

	/* For reset and error_state handling. */
	spinlock_t lock;
	/* Protected by the above dev->gpu_error.lock. */
	struct drm_i915_error_state *first_error;
1374 1375 1376

	unsigned long missed_irq_rings;

1377
	/**
M
Mika Kuoppala 已提交
1378
	 * State variable controlling the reset flow and count
1379
	 *
M
Mika Kuoppala 已提交
1380 1381 1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 1392
	 * This is a counter which gets incremented when reset is triggered,
	 * and again when reset has been handled. So odd values (lowest bit set)
	 * means that reset is in progress and even values that
	 * (reset_counter >> 1):th reset was successfully completed.
	 *
	 * If reset is not completed succesfully, the I915_WEDGE bit is
	 * set meaning that hardware is terminally sour and there is no
	 * recovery. All waiters on the reset_queue will be woken when
	 * that happens.
	 *
	 * This counter is used by the wait_seqno code to notice that reset
	 * event happened and it needs to restart the entire ioctl (since most
	 * likely the seqno it waited for won't ever signal anytime soon).
1393 1394 1395 1396
	 *
	 * This is important for lock-free wait paths, where no contended lock
	 * naturally enforces the correct ordering between the bail-out of the
	 * waiter and the gpu reset work code.
1397 1398 1399 1400
	 */
	atomic_t reset_counter;

#define I915_RESET_IN_PROGRESS_FLAG	1
M
Mika Kuoppala 已提交
1401
#define I915_WEDGED			(1 << 31)
1402

1403 1404 1405 1406 1407 1408
	/**
	 * Waitqueue to signal when a hang is detected. Used to for waiters
	 * to release the struct_mutex for the reset to procede.
	 */
	wait_queue_head_t wait_queue;

1409 1410 1411 1412 1413
	/**
	 * Waitqueue to signal when the reset has completed. Used by clients
	 * that wait for dev_priv->mm.wedged to settle.
	 */
	wait_queue_head_t reset_queue;
1414

1415
	/* For missed irq/seqno simulation. */
1416
	unsigned long test_irq_rings;
1417 1418
};

1419 1420 1421 1422 1423 1424
enum modeset_restore {
	MODESET_ON_LID_OPEN,
	MODESET_DONE,
	MODESET_SUSPENDED,
};

1425 1426 1427 1428 1429
#define DP_AUX_A 0x40
#define DP_AUX_B 0x10
#define DP_AUX_C 0x20
#define DP_AUX_D 0x30

X
Xiong Zhang 已提交
1430 1431 1432 1433
#define DDC_PIN_B  0x05
#define DDC_PIN_C  0x04
#define DDC_PIN_D  0x06

1434
struct ddi_vbt_port_info {
1435 1436 1437 1438 1439 1440
	/*
	 * This is an index in the HDMI/DVI DDI buffer translation table.
	 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
	 * populate this field.
	 */
#define HDMI_LEVEL_SHIFT_UNKNOWN	0xff
1441
	uint8_t hdmi_level_shift;
1442 1443 1444 1445

	uint8_t supports_dvi:1;
	uint8_t supports_hdmi:1;
	uint8_t supports_dp:1;
1446 1447

	uint8_t alternate_aux_channel;
X
Xiong Zhang 已提交
1448
	uint8_t alternate_ddc_pin;
1449 1450 1451

	uint8_t dp_boost_level;
	uint8_t hdmi_boost_level;
1452 1453
};

R
Rodrigo Vivi 已提交
1454 1455 1456 1457 1458
enum psr_lines_to_wait {
	PSR_0_LINES_TO_WAIT = 0,
	PSR_1_LINE_TO_WAIT,
	PSR_4_LINES_TO_WAIT,
	PSR_8_LINES_TO_WAIT
1459 1460
};

1461 1462 1463 1464 1465 1466 1467 1468 1469 1470 1471 1472
struct intel_vbt_data {
	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */

	/* Feature bits */
	unsigned int int_tv_support:1;
	unsigned int lvds_dither:1;
	unsigned int lvds_vbt:1;
	unsigned int int_crt_support:1;
	unsigned int lvds_use_ssc:1;
	unsigned int display_clock_mode:1;
	unsigned int fdi_rx_polarity_inverted:1;
1473
	unsigned int panel_type:4;
1474 1475 1476
	int lvds_ssc_freq;
	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */

1477 1478
	enum drrs_support_type drrs_type;

1479 1480 1481 1482 1483
	struct {
		int rate;
		int lanes;
		int preemphasis;
		int vswing;
1484
		bool low_vswing;
1485 1486 1487 1488 1489
		bool initialized;
		bool support;
		int bpp;
		struct edp_power_seq pps;
	} edp;
1490

R
Rodrigo Vivi 已提交
1491 1492 1493 1494 1495 1496 1497 1498 1499
	struct {
		bool full_link;
		bool require_aux_wakeup;
		int idle_frames;
		enum psr_lines_to_wait lines_to_wait;
		int tp1_wakeup_time;
		int tp2_tp3_wakeup_time;
	} psr;

1500 1501
	struct {
		u16 pwm_freq_hz;
1502
		bool present;
1503
		bool active_low_pwm;
1504
		u8 min_brightness;	/* min_brightness/255 of max */
1505
		enum intel_backlight_type type;
1506 1507
	} backlight;

1508 1509 1510
	/* MIPI DSI */
	struct {
		u16 panel_id;
1511 1512 1513 1514 1515
		struct mipi_config *config;
		struct mipi_pps_data *pps;
		u8 seq_version;
		u32 size;
		u8 *data;
1516
		const u8 *sequence[MIPI_SEQ_MAX];
1517 1518
	} dsi;

1519 1520 1521
	int crt_ddc_pin;

	int child_dev_num;
1522
	union child_device_config *child_dev;
1523 1524

	struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1525
	struct sdvo_device_mapping sdvo_mappings[2];
1526 1527
};

1528 1529 1530 1531 1532
enum intel_ddb_partitioning {
	INTEL_DDB_PART_1_2,
	INTEL_DDB_PART_5_6, /* IVB+ */
};

1533 1534 1535 1536 1537 1538 1539 1540
struct intel_wm_level {
	bool enable;
	uint32_t pri_val;
	uint32_t spr_val;
	uint32_t cur_val;
	uint32_t fbc_val;
};

1541
struct ilk_wm_values {
1542 1543 1544 1545 1546 1547 1548 1549
	uint32_t wm_pipe[3];
	uint32_t wm_lp[3];
	uint32_t wm_lp_spr[3];
	uint32_t wm_linetime[3];
	bool enable_fbc_wm;
	enum intel_ddb_partitioning partitioning;
};

1550 1551 1552 1553 1554
struct vlv_pipe_wm {
	uint16_t primary;
	uint16_t sprite[2];
	uint8_t cursor;
};
1555

1556 1557 1558 1559
struct vlv_sr_wm {
	uint16_t plane;
	uint8_t cursor;
};
1560

1561 1562 1563
struct vlv_wm_values {
	struct vlv_pipe_wm pipe[3];
	struct vlv_sr_wm sr;
1564 1565 1566 1567 1568
	struct {
		uint8_t cursor;
		uint8_t sprite[2];
		uint8_t primary;
	} ddl[3];
1569 1570
	uint8_t level;
	bool cxsr;
1571 1572
};

1573
struct skl_ddb_entry {
1574
	uint16_t start, end;	/* in number of blocks, 'end' is exclusive */
1575 1576 1577 1578
};

static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
{
1579
	return entry->end - entry->start;
1580 1581
}

1582 1583 1584 1585 1586 1587 1588 1589 1590
static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
				       const struct skl_ddb_entry *e2)
{
	if (e1->start == e2->start && e1->end == e2->end)
		return true;

	return false;
}

1591
struct skl_ddb_allocation {
1592
	struct skl_ddb_entry pipe[I915_MAX_PIPES];
1593
	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1594
	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1595 1596
};

1597
struct skl_wm_values {
1598
	unsigned dirty_pipes;
1599
	struct skl_ddb_allocation ddb;
1600 1601 1602 1603 1604 1605 1606 1607 1608 1609 1610
	uint32_t wm_linetime[I915_MAX_PIPES];
	uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
	uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
};

struct skl_wm_level {
	bool plane_en[I915_MAX_PLANES];
	uint16_t plane_res_b[I915_MAX_PLANES];
	uint8_t plane_res_l[I915_MAX_PLANES];
};

1611
/*
1612 1613 1614 1615
 * This struct helps tracking the state needed for runtime PM, which puts the
 * device in PCI D3 state. Notice that when this happens, nothing on the
 * graphics device works, even register access, so we don't get interrupts nor
 * anything else.
1616
 *
1617 1618 1619
 * Every piece of our code that needs to actually touch the hardware needs to
 * either call intel_runtime_pm_get or call intel_display_power_get with the
 * appropriate power domain.
1620
 *
1621 1622
 * Our driver uses the autosuspend delay feature, which means we'll only really
 * suspend if we stay with zero refcount for a certain amount of time. The
1623
 * default value is currently very conservative (see intel_runtime_pm_enable), but
1624
 * it can be changed with the standard runtime PM files from sysfs.
1625 1626 1627 1628 1629
 *
 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
 * goes back to false exactly before we reenable the IRQs. We use this variable
 * to check if someone is trying to enable/disable IRQs while they're supposed
 * to be disabled. This shouldn't happen and we'll print some error messages in
1630
 * case it happens.
1631
 *
1632
 * For more, read the Documentation/power/runtime_pm.txt.
1633
 */
1634
struct i915_runtime_pm {
1635
	atomic_t wakeref_count;
1636
	atomic_t atomic_seq;
1637
	bool suspended;
1638
	bool irqs_enabled;
1639 1640
};

1641 1642 1643 1644 1645
enum intel_pipe_crc_source {
	INTEL_PIPE_CRC_SOURCE_NONE,
	INTEL_PIPE_CRC_SOURCE_PLANE1,
	INTEL_PIPE_CRC_SOURCE_PLANE2,
	INTEL_PIPE_CRC_SOURCE_PF,
1646
	INTEL_PIPE_CRC_SOURCE_PIPE,
D
Daniel Vetter 已提交
1647 1648 1649 1650 1651
	/* TV/DP on pre-gen5/vlv can't use the pipe source. */
	INTEL_PIPE_CRC_SOURCE_TV,
	INTEL_PIPE_CRC_SOURCE_DP_B,
	INTEL_PIPE_CRC_SOURCE_DP_C,
	INTEL_PIPE_CRC_SOURCE_DP_D,
1652
	INTEL_PIPE_CRC_SOURCE_AUTO,
1653 1654 1655
	INTEL_PIPE_CRC_SOURCE_MAX,
};

1656
struct intel_pipe_crc_entry {
1657
	uint32_t frame;
1658 1659 1660
	uint32_t crc[5];
};

1661
#define INTEL_PIPE_CRC_ENTRIES_NR	128
1662
struct intel_pipe_crc {
1663 1664
	spinlock_t lock;
	bool opened;		/* exclusive access to the result file */
1665
	struct intel_pipe_crc_entry *entries;
1666
	enum intel_pipe_crc_source source;
1667
	int head, tail;
1668
	wait_queue_head_t wq;
1669 1670
};

1671
struct i915_frontbuffer_tracking {
1672
	spinlock_t lock;
1673 1674 1675 1676 1677 1678 1679 1680 1681

	/*
	 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
	 * scheduled flips.
	 */
	unsigned busy_bits;
	unsigned flip_bits;
};

1682
struct i915_wa_reg {
1683
	i915_reg_t addr;
1684 1685 1686 1687 1688
	u32 value;
	/* bitmask representing WA bits */
	u32 mask;
};

1689 1690 1691 1692 1693 1694 1695
/*
 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
 * allowing it for RCS as we don't foresee any requirement of having
 * a whitelist for other engines. When it is really required for
 * other engines then the limit need to be increased.
 */
#define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1696 1697 1698 1699

struct i915_workarounds {
	struct i915_wa_reg reg[I915_MAX_WA_REGS];
	u32 count;
1700
	u32 hw_whitelist_count[I915_NUM_ENGINES];
1701 1702
};

1703 1704 1705 1706
struct i915_virtual_gpu {
	bool active;
};

1707 1708 1709 1710 1711 1712 1713
/* used in computing the new watermarks state */
struct intel_wm_config {
	unsigned int num_pipes_active;
	bool sprites_enabled;
	bool sprites_scaled;
};

1714
struct drm_i915_private {
1715 1716
	struct drm_device drm;

1717
	struct kmem_cache *objects;
1718
	struct kmem_cache *vmas;
1719
	struct kmem_cache *requests;
1720

1721
	const struct intel_device_info info;
1722 1723 1724 1725 1726

	int relative_constants_mode;

	void __iomem *regs;

1727
	struct intel_uncore uncore;
1728

1729 1730
	struct i915_virtual_gpu vgpu;

1731 1732
	struct intel_gvt gvt;

1733 1734
	struct intel_guc guc;

1735 1736
	struct intel_csr csr;

1737
	struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1738

1739 1740 1741 1742 1743 1744 1745 1746 1747
	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
	 * controller on different i2c buses. */
	struct mutex gmbus_mutex;

	/**
	 * Base address of the gmbus and gpio block.
	 */
	uint32_t gpio_mmio_base;

1748 1749 1750
	/* MMIO base address for MIPI regs */
	uint32_t mipi_mmio_base;

1751 1752
	uint32_t psr_mmio_base;

1753 1754
	wait_queue_head_t gmbus_wait_queue;

1755
	struct pci_dev *bridge_dev;
1756
	struct i915_gem_context *kernel_context;
1757
	struct intel_engine_cs engine[I915_NUM_ENGINES];
1758
	struct drm_i915_gem_object *semaphore_obj;
1759
	u32 next_seqno;
1760

1761
	struct drm_dma_handle *status_page_dmah;
1762 1763 1764 1765 1766
	struct resource mch_res;

	/* protects the irq masks */
	spinlock_t irq_lock;

1767 1768 1769
	/* protects the mmio flip data */
	spinlock_t mmio_flip_lock;

1770 1771
	bool display_irqs_enabled;

1772 1773 1774
	/* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
	struct pm_qos_request pm_qos;

V
Ville Syrjälä 已提交
1775 1776
	/* Sideband mailbox protection */
	struct mutex sb_lock;
1777 1778

	/** Cached value of IMR to avoid reads in updating the bitfield */
1779 1780 1781 1782
	union {
		u32 irq_mask;
		u32 de_irq_mask[I915_MAX_PIPES];
	};
1783
	u32 gt_irq_mask;
1784
	u32 pm_irq_mask;
1785
	u32 pm_rps_events;
1786
	u32 pipestat_irq_mask[I915_MAX_PIPES];
1787

1788
	struct i915_hotplug hotplug;
1789
	struct intel_fbc fbc;
1790
	struct i915_drrs drrs;
1791
	struct intel_opregion opregion;
1792
	struct intel_vbt_data vbt;
1793

1794 1795
	bool preserve_bios_swizzle;

1796 1797 1798
	/* overlay */
	struct intel_overlay *overlay;

1799
	/* backlight registers and fields in struct intel_panel */
1800
	struct mutex backlight_lock;
1801

1802 1803 1804
	/* LVDS info */
	bool no_aux_handshake;

V
Ville Syrjälä 已提交
1805 1806 1807
	/* protects panel power sequencer state */
	struct mutex pps_mutex;

1808 1809 1810 1811
	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
	int num_fence_regs; /* 8 on pre-965, 16 otherwise */

	unsigned int fsb_freq, mem_freq, is_ddr3;
1812
	unsigned int skl_preferred_vco_freq;
1813
	unsigned int cdclk_freq, max_cdclk_freq, atomic_cdclk_freq;
M
Mika Kahola 已提交
1814
	unsigned int max_dotclk_freq;
1815
	unsigned int rawclk_freq;
1816
	unsigned int hpll_freq;
1817
	unsigned int czclk_freq;
1818

1819
	struct {
1820
		unsigned int vco, ref;
1821 1822
	} cdclk_pll;

1823 1824 1825 1826 1827 1828 1829
	/**
	 * wq - Driver workqueue for GEM.
	 *
	 * NOTE: Work items scheduled here are not allowed to grab any modeset
	 * locks, for otherwise the flushing done in the pageflip code will
	 * result in deadlocks.
	 */
1830 1831 1832 1833 1834 1835 1836
	struct workqueue_struct *wq;

	/* Display functions */
	struct drm_i915_display_funcs display;

	/* PCH chipset type */
	enum intel_pch pch_type;
1837
	unsigned short pch_id;
1838 1839 1840

	unsigned long quirks;

1841 1842
	enum modeset_restore modeset_restore;
	struct mutex modeset_restore_lock;
1843
	struct drm_atomic_state *modeset_restore_state;
1844

1845
	struct list_head vm_list; /* Global list of all address spaces */
1846
	struct i915_ggtt ggtt; /* VM representing the global address space */
B
Ben Widawsky 已提交
1847

1848
	struct i915_gem_mm mm;
1849 1850
	DECLARE_HASHTABLE(mm_structs, 7);
	struct mutex mm_lock;
1851

1852 1853 1854 1855 1856 1857 1858
	/* The hw wants to have a stable context identifier for the lifetime
	 * of the context (for OA, PASID, faults, etc). This is limited
	 * in execlists to 21 bits.
	 */
	struct ida context_hw_ida;
#define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */

1859 1860
	/* Kernel Modesetting */

1861 1862
	struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
	struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1863 1864
	wait_queue_head_t pending_flip_queue;

1865 1866 1867 1868
#ifdef CONFIG_DEBUG_FS
	struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
#endif

1869
	/* dpll and cdclk state is protected by connection_mutex */
D
Daniel Vetter 已提交
1870 1871
	int num_shared_dpll;
	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1872
	const struct intel_dpll_mgr *dpll_mgr;
1873

1874 1875 1876 1877 1878 1879 1880
	/*
	 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
	 * Must be global rather than per dpll, because on some platforms
	 * plls share registers.
	 */
	struct mutex dpll_lock;

1881 1882 1883
	unsigned int active_crtcs;
	unsigned int min_pixclk[I915_MAX_PIPES];

1884
	int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1885

1886
	struct i915_workarounds workarounds;
1887

1888 1889
	struct i915_frontbuffer_tracking fb_tracking;

1890
	u16 orig_clock;
1891

1892
	bool mchbar_need_disable;
1893

1894 1895
	struct intel_l3_parity l3_parity;

B
Ben Widawsky 已提交
1896
	/* Cannot be determined by PCIID. You must always read a register. */
1897
	u32 edram_cap;
B
Ben Widawsky 已提交
1898

1899
	/* gen6+ rps state */
1900
	struct intel_gen6_power_mgmt rps;
1901

1902 1903
	/* ilk-only ips/rps state. Everything in here is protected by the global
	 * mchdev_lock in intel_pm.c */
1904
	struct intel_ilk_power_mgmt ips;
1905

1906
	struct i915_power_domains power_domains;
1907

R
Rodrigo Vivi 已提交
1908
	struct i915_psr psr;
1909

1910
	struct i915_gpu_error gpu_error;
1911

1912 1913
	struct drm_i915_gem_object *vlv_pctx;

1914
#ifdef CONFIG_DRM_FBDEV_EMULATION
1915 1916
	/* list of fbdev register on this device */
	struct intel_fbdev *fbdev;
1917
	struct work_struct fbdev_suspend_work;
1918
#endif
1919 1920

	struct drm_property *broadcast_rgb_property;
1921
	struct drm_property *force_audio_property;
1922

I
Imre Deak 已提交
1923
	/* hda/i915 audio component */
1924
	struct i915_audio_component *audio_component;
I
Imre Deak 已提交
1925
	bool audio_component_registered;
1926 1927 1928 1929 1930
	/**
	 * av_mutex - mutex for audio/video sync
	 *
	 */
	struct mutex av_mutex;
I
Imre Deak 已提交
1931

1932
	uint32_t hw_context_size;
1933
	struct list_head context_list;
1934

1935
	u32 fdi_rx_config;
1936

1937
	/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1938
	u32 chv_phy_control;
1939 1940 1941 1942 1943 1944
	/*
	 * Shadows for CHV DPLL_MD regs to keep the state
	 * checker somewhat working in the presence hardware
	 * crappiness (can't read out DPLL_MD for pipes B & C).
	 */
	u32 chv_dpll_md[I915_MAX_PIPES];
1945
	u32 bxt_phy_grc;
1946

1947
	u32 suspend_count;
1948
	bool suspended_to_idle;
1949
	struct i915_suspend_saved_registers regfile;
1950
	struct vlv_s0ix_state vlv_s0ix_state;
1951

1952 1953 1954 1955 1956 1957 1958 1959 1960 1961 1962 1963
	struct {
		/*
		 * Raw watermark latency values:
		 * in 0.1us units for WM0,
		 * in 0.5us units for WM1+.
		 */
		/* primary */
		uint16_t pri_latency[5];
		/* sprite */
		uint16_t spr_latency[5];
		/* cursor */
		uint16_t cur_latency[5];
1964 1965 1966 1967 1968 1969
		/*
		 * Raw watermark memory latency values
		 * for SKL for all 8 levels
		 * in 1us units.
		 */
		uint16_t skl_latency[8];
1970

1971 1972 1973 1974 1975 1976 1977
		/*
		 * The skl_wm_values structure is a bit too big for stack
		 * allocation, so we keep the staging struct where we store
		 * intermediate results here instead.
		 */
		struct skl_wm_values skl_results;

1978
		/* current hardware state */
1979 1980 1981
		union {
			struct ilk_wm_values hw;
			struct skl_wm_values skl_hw;
1982
			struct vlv_wm_values vlv;
1983
		};
1984 1985

		uint8_t max_level;
1986 1987 1988 1989 1990 1991 1992

		/*
		 * Should be held around atomic WM register writing; also
		 * protects * intel_crtc->wm.active and
		 * cstate->wm.need_postvbl_update.
		 */
		struct mutex wm_mutex;
1993 1994 1995 1996 1997 1998 1999

		/*
		 * Set during HW readout of watermarks/DDB.  Some platforms
		 * need to know when we're still using BIOS-provided values
		 * (which we don't fully trust).
		 */
		bool distrust_bios_wm;
2000 2001
	} wm;

2002 2003
	struct i915_runtime_pm pm;

2004 2005
	/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
	struct {
2006
		void (*cleanup_engine)(struct intel_engine_cs *engine);
2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034

		/**
		 * Is the GPU currently considered idle, or busy executing
		 * userspace requests? Whilst idle, we allow runtime power
		 * management to power down the hardware and display clocks.
		 * In order to reduce the effect on performance, there
		 * is a slight delay before we do so.
		 */
		unsigned int active_engines;
		bool awake;

		/**
		 * We leave the user IRQ off as much as possible,
		 * but this means that requests will finish and never
		 * be retired once the system goes idle. Set a timer to
		 * fire periodically while the ring is running. When it
		 * fires, go retire requests.
		 */
		struct delayed_work retire_work;

		/**
		 * When we detect an idle GPU, we want to turn on
		 * powersaving features. So once we see that there
		 * are no more requests outstanding and no more
		 * arrive within a small period of time, we fire
		 * off the idle_work.
		 */
		struct delayed_work idle_work;
2035 2036
	} gt;

2037 2038 2039
	/* perform PHY state sanity checks? */
	bool chv_phy_assert[2];

2040 2041
	struct intel_encoder *dig_port_map[I915_MAX_PORTS];

2042 2043 2044 2045
	/*
	 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
	 * will be rejected. Instead look for a better place.
	 */
2046
};
L
Linus Torvalds 已提交
2047

2048 2049
static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
{
2050
	return container_of(dev, struct drm_i915_private, drm);
2051 2052
}

I
Imre Deak 已提交
2053 2054 2055 2056 2057
static inline struct drm_i915_private *dev_to_i915(struct device *dev)
{
	return to_i915(dev_get_drvdata(dev));
}

2058 2059 2060 2061 2062
static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
{
	return container_of(guc, struct drm_i915_private, guc);
}

2063 2064 2065 2066 2067 2068
/* Simple iterator over all initialised engines */
#define for_each_engine(engine__, dev_priv__) \
	for ((engine__) = &(dev_priv__)->engine[0]; \
	     (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
	     (engine__)++) \
		for_each_if (intel_engine_initialized(engine__))
2069

2070 2071 2072 2073 2074 2075 2076 2077 2078
/* Iterator with engine_id */
#define for_each_engine_id(engine__, dev_priv__, id__) \
	for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
	     (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
	     (engine__)++) \
		for_each_if (((id__) = (engine__)->id, \
			      intel_engine_initialized(engine__)))

/* Iterator over subset of engines selected by mask */
2079
#define for_each_engine_masked(engine__, dev_priv__, mask__) \
2080 2081 2082 2083 2084
	for ((engine__) = &(dev_priv__)->engine[0]; \
	     (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
	     (engine__)++) \
		for_each_if (((mask__) & intel_engine_flag(engine__)) && \
			     intel_engine_initialized(engine__))
2085

2086 2087 2088 2089 2090 2091 2092
enum hdmi_force_audio {
	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
	HDMI_AUDIO_AUTO,		/* trust EDID */
	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
};

2093
#define I915_GTT_OFFSET_NONE ((u32)-1)
2094

2095
struct drm_i915_gem_object_ops {
2096 2097 2098
	unsigned int flags;
#define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1

2099 2100 2101 2102 2103 2104 2105 2106 2107 2108 2109 2110 2111 2112 2113
	/* Interface between the GEM object and its backing storage.
	 * get_pages() is called once prior to the use of the associated set
	 * of pages before to binding them into the GTT, and put_pages() is
	 * called after we no longer need them. As we expect there to be
	 * associated cost with migrating pages between the backing storage
	 * and making them available for the GPU (e.g. clflush), we may hold
	 * onto the pages after they are no longer referenced by the GPU
	 * in case they may be used again shortly (for example migrating the
	 * pages to a different memory domain within the GTT). put_pages()
	 * will therefore most likely be called when the object itself is
	 * being released or under memory pressure (where we attempt to
	 * reap pages for the shrinker).
	 */
	int (*get_pages)(struct drm_i915_gem_object *);
	void (*put_pages)(struct drm_i915_gem_object *);
2114

2115 2116
	int (*dmabuf_export)(struct drm_i915_gem_object *);
	void (*release)(struct drm_i915_gem_object *);
2117 2118
};

2119 2120
/*
 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2121
 * considered to be the frontbuffer for the given plane interface-wise. This
2122 2123 2124 2125 2126
 * doesn't mean that the hw necessarily already scans it out, but that any
 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
 *
 * We have one bit per pipe and per scanout plane type.
 */
2127 2128
#define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
#define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2129 2130 2131
#define INTEL_FRONTBUFFER_PRIMARY(pipe) \
	(1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
#define INTEL_FRONTBUFFER_CURSOR(pipe) \
2132 2133 2134
	(1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
#define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
	(1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2135
#define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2136
	(1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2137
#define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2138
	(0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2139

2140
struct drm_i915_gem_object {
2141
	struct drm_gem_object base;
2142

2143 2144
	const struct drm_i915_gem_object_ops *ops;

B
Ben Widawsky 已提交
2145 2146 2147
	/** List of VMAs backed by this object */
	struct list_head vma_list;

2148 2149
	/** Stolen memory for this object, instead of being backed by shmem. */
	struct drm_mm_node *stolen;
2150
	struct list_head global_list;
2151

2152 2153
	/** Used in execbuf to temporarily hold a ref */
	struct list_head obj_exec_link;
2154

2155
	struct list_head batch_pool_link;
2156

2157
	unsigned long flags;
2158
	/**
2159 2160 2161
	 * This is set if the object is on the active lists (has pending
	 * rendering and so a non-zero seqno), and is not set if it i s on
	 * inactive (ready to be unbound) list.
2162
	 */
2163 2164 2165 2166
#define I915_BO_ACTIVE_SHIFT 0
#define I915_BO_ACTIVE_MASK ((1 << I915_NUM_ENGINES) - 1)
#define __I915_BO_ACTIVE(bo) \
	((READ_ONCE((bo)->flags) >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK)
2167 2168 2169 2170 2171

	/**
	 * This is set if the object has been written to since last bound
	 * to the GTT
	 */
2172
	unsigned int dirty:1;
2173 2174 2175 2176 2177 2178

	/**
	 * Fence register bits (if any) for this object.  Will be set
	 * as needed when mapped into the GTT.
	 * Protected by dev->struct_mutex.
	 */
2179
	signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2180 2181 2182 2183

	/**
	 * Advice: are the backing pages purgeable?
	 */
2184
	unsigned int madv:2;
2185 2186 2187 2188

	/**
	 * Current tiling mode for the object.
	 */
2189
	unsigned int tiling_mode:2;
2190 2191 2192 2193 2194 2195 2196 2197
	/**
	 * Whether the tiling parameters for the currently associated fence
	 * register have changed. Note that for the purposes of tracking
	 * tiling changes we also treat the unfenced register, the register
	 * slot that the object occupies whilst it executes a fenced
	 * command (such as BLT on gen2/3), as a "fence".
	 */
	unsigned int fence_dirty:1;
2198

2199 2200 2201 2202
	/**
	 * Is the object at the current location in the gtt mappable and
	 * fenceable? Used to avoid costly recalculations.
	 */
2203
	unsigned int map_and_fenceable:1;
2204

2205 2206 2207 2208 2209
	/**
	 * Whether the current gtt mapping needs to be mappable (and isn't just
	 * mappable by accident). Track pin and fault separate for a more
	 * accurate mappable working set.
	 */
2210
	unsigned int fault_mappable:1;
2211

2212 2213 2214 2215 2216
	/*
	 * Is the object to be mapped as read-only to the GPU
	 * Only honoured if hardware has relevant pte bit
	 */
	unsigned long gt_ro:1;
2217
	unsigned int cache_level:3;
2218
	unsigned int cache_dirty:1;
2219

2220
	atomic_t frontbuffer_bits;
2221

2222
	unsigned int has_wc_mmap;
2223 2224
	/** Count of VMA actually bound by this object */
	unsigned int bind_count;
2225 2226
	unsigned int pin_display;

2227
	struct sg_table *pages;
2228
	int pages_pin_count;
2229 2230 2231 2232
	struct get_page {
		struct scatterlist *sg;
		int last;
	} get_page;
2233
	void *mapping;
2234

2235 2236 2237 2238 2239 2240 2241 2242 2243
	/** Breadcrumb of last rendering to the buffer.
	 * There can only be one writer, but we allow for multiple readers.
	 * If there is a writer that necessarily implies that all other
	 * read requests are complete - but we may only be lazily clearing
	 * the read requests. A read request is naturally the most recent
	 * request on a ring, so we may have two different write and read
	 * requests on one ring where the write request is older than the
	 * read request. This allows for the CPU to read from an active
	 * buffer by only waiting for the write to complete.
2244 2245 2246 2247
	 */
	struct i915_gem_active last_read[I915_NUM_ENGINES];
	struct i915_gem_active last_write;
	struct i915_gem_active last_fence;
2248

2249
	/** Current tiling stride for the object, if it's tiled. */
2250
	uint32_t stride;
2251

2252 2253 2254
	/** References from framebuffers, locks out tiling changes. */
	unsigned long framebuffer_references;

2255
	/** Record of address bit 17 of each page at last unbind. */
2256
	unsigned long *bit_17;
2257

2258
	union {
2259 2260 2261
		/** for phy allocated objects */
		struct drm_dma_handle *phys_handle;

2262 2263 2264 2265 2266 2267
		struct i915_gem_userptr {
			uintptr_t ptr;
			unsigned read_only :1;
			unsigned workers :4;
#define I915_GEM_USERPTR_MAX_WORKERS 15

2268 2269
			struct i915_mm_struct *mm;
			struct i915_mmu_object *mmu_object;
2270 2271 2272 2273
			struct work_struct *work;
		} userptr;
	};
};
2274 2275 2276 2277 2278 2279 2280 2281 2282 2283 2284 2285 2286 2287 2288 2289 2290 2291 2292

static inline struct drm_i915_gem_object *
to_intel_bo(struct drm_gem_object *gem)
{
	/* Assert that to_intel_bo(NULL) == NULL */
	BUILD_BUG_ON(offsetof(struct drm_i915_gem_object, base));

	return container_of(gem, struct drm_i915_gem_object, base);
}

static inline struct drm_i915_gem_object *
i915_gem_object_lookup(struct drm_file *file, u32 handle)
{
	return to_intel_bo(drm_gem_object_lookup(file, handle));
}

__deprecated
extern struct drm_gem_object *
drm_gem_object_lookup(struct drm_file *file, u32 handle);
2293

2294 2295 2296 2297 2298 2299 2300 2301 2302 2303 2304
__attribute__((nonnull))
static inline struct drm_i915_gem_object *
i915_gem_object_get(struct drm_i915_gem_object *obj)
{
	drm_gem_object_reference(&obj->base);
	return obj;
}

__deprecated
extern void drm_gem_object_reference(struct drm_gem_object *);

2305 2306 2307 2308 2309 2310 2311 2312 2313 2314
__attribute__((nonnull))
static inline void
i915_gem_object_put(struct drm_i915_gem_object *obj)
{
	drm_gem_object_unreference(&obj->base);
}

__deprecated
extern void drm_gem_object_unreference(struct drm_gem_object *);

2315 2316 2317 2318 2319 2320 2321 2322 2323 2324
__attribute__((nonnull))
static inline void
i915_gem_object_put_unlocked(struct drm_i915_gem_object *obj)
{
	drm_gem_object_unreference_unlocked(&obj->base);
}

__deprecated
extern void drm_gem_object_unreference_unlocked(struct drm_gem_object *);

2325 2326 2327 2328 2329 2330
static inline bool
i915_gem_object_has_struct_page(const struct drm_i915_gem_object *obj)
{
	return obj->ops->flags & I915_GEM_OBJECT_HAS_STRUCT_PAGE;
}

2331 2332 2333 2334 2335 2336 2337 2338 2339 2340 2341 2342 2343 2344 2345 2346 2347 2348 2349 2350 2351 2352 2353 2354 2355 2356 2357 2358 2359 2360 2361
static inline unsigned long
i915_gem_object_get_active(const struct drm_i915_gem_object *obj)
{
	return (obj->flags >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK;
}

static inline bool
i915_gem_object_is_active(const struct drm_i915_gem_object *obj)
{
	return i915_gem_object_get_active(obj);
}

static inline void
i915_gem_object_set_active(struct drm_i915_gem_object *obj, int engine)
{
	obj->flags |= BIT(engine + I915_BO_ACTIVE_SHIFT);
}

static inline void
i915_gem_object_clear_active(struct drm_i915_gem_object *obj, int engine)
{
	obj->flags &= ~BIT(engine + I915_BO_ACTIVE_SHIFT);
}

static inline bool
i915_gem_object_has_active_engine(const struct drm_i915_gem_object *obj,
				  int engine)
{
	return obj->flags & BIT(engine + I915_BO_ACTIVE_SHIFT);
}

2362 2363 2364 2365 2366 2367 2368 2369 2370 2371 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 2383 2384 2385 2386 2387
/*
 * Optimised SGL iterator for GEM objects
 */
static __always_inline struct sgt_iter {
	struct scatterlist *sgp;
	union {
		unsigned long pfn;
		dma_addr_t dma;
	};
	unsigned int curr;
	unsigned int max;
} __sgt_iter(struct scatterlist *sgl, bool dma) {
	struct sgt_iter s = { .sgp = sgl };

	if (s.sgp) {
		s.max = s.curr = s.sgp->offset;
		s.max += s.sgp->length;
		if (dma)
			s.dma = sg_dma_address(s.sgp);
		else
			s.pfn = page_to_pfn(sg_page(s.sgp));
	}

	return s;
}

2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 2399 2400 2401 2402 2403 2404 2405 2406
/**
 * __sg_next - return the next scatterlist entry in a list
 * @sg:		The current sg entry
 *
 * Description:
 *   If the entry is the last, return NULL; otherwise, step to the next
 *   element in the array (@sg@+1). If that's a chain pointer, follow it;
 *   otherwise just return the pointer to the current element.
 **/
static inline struct scatterlist *__sg_next(struct scatterlist *sg)
{
#ifdef CONFIG_DEBUG_SG
	BUG_ON(sg->sg_magic != SG_MAGIC);
#endif
	return sg_is_last(sg) ? NULL :
		likely(!sg_is_chain(++sg)) ? sg :
		sg_chain_ptr(sg);
}

2407 2408 2409 2410 2411 2412 2413 2414 2415 2416
/**
 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
 * @__dmap:	DMA address (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_dma(__dmap, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, true);			\
	     ((__dmap) = (__iter).dma + (__iter).curr);			\
	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
2417
	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429

/**
 * for_each_sgt_page - iterate over the pages of the given sg_table
 * @__pp:	page pointer (output)
 * @__iter:	'struct sgt_iter' (iterator state, internal)
 * @__sgt:	sg_table to iterate over (input)
 */
#define for_each_sgt_page(__pp, __iter, __sgt)				\
	for ((__iter) = __sgt_iter((__sgt)->sgl, false);		\
	     ((__pp) = (__iter).pfn == 0 ? NULL :			\
	      pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
	     (((__iter).curr += PAGE_SIZE) < (__iter).max) ||		\
2430
	     ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2431

2432 2433 2434 2435 2436 2437 2438 2439 2440 2441 2442 2443 2444 2445 2446 2447 2448 2449 2450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 2463 2464 2465 2466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479 2480 2481 2482 2483
/*
 * A command that requires special handling by the command parser.
 */
struct drm_i915_cmd_descriptor {
	/*
	 * Flags describing how the command parser processes the command.
	 *
	 * CMD_DESC_FIXED: The command has a fixed length if this is set,
	 *                 a length mask if not set
	 * CMD_DESC_SKIP: The command is allowed but does not follow the
	 *                standard length encoding for the opcode range in
	 *                which it falls
	 * CMD_DESC_REJECT: The command is never allowed
	 * CMD_DESC_REGISTER: The command should be checked against the
	 *                    register whitelist for the appropriate ring
	 * CMD_DESC_MASTER: The command is allowed if the submitting process
	 *                  is the DRM master
	 */
	u32 flags;
#define CMD_DESC_FIXED    (1<<0)
#define CMD_DESC_SKIP     (1<<1)
#define CMD_DESC_REJECT   (1<<2)
#define CMD_DESC_REGISTER (1<<3)
#define CMD_DESC_BITMASK  (1<<4)
#define CMD_DESC_MASTER   (1<<5)

	/*
	 * The command's unique identification bits and the bitmask to get them.
	 * This isn't strictly the opcode field as defined in the spec and may
	 * also include type, subtype, and/or subop fields.
	 */
	struct {
		u32 value;
		u32 mask;
	} cmd;

	/*
	 * The command's length. The command is either fixed length (i.e. does
	 * not include a length field) or has a length field mask. The flag
	 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
	 * a length mask. All command entries in a command table must include
	 * length information.
	 */
	union {
		u32 fixed;
		u32 mask;
	} length;

	/*
	 * Describes where to find a register address in the command to check
	 * against the ring's register whitelist. Only valid if flags has the
	 * CMD_DESC_REGISTER bit set.
2484 2485 2486 2487
	 *
	 * A non-zero step value implies that the command may access multiple
	 * registers in sequence (e.g. LRI), in that case step gives the
	 * distance in dwords between individual offset fields.
2488 2489 2490 2491
	 */
	struct {
		u32 offset;
		u32 mask;
2492
		u32 step;
2493 2494 2495 2496 2497 2498 2499 2500 2501
	} reg;

#define MAX_CMD_DESC_BITMASKS 3
	/*
	 * Describes command checks where a particular dword is masked and
	 * compared against an expected value. If the command does not match
	 * the expected value, the parser rejects it. Only valid if flags has
	 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
	 * are valid.
2502 2503 2504 2505
	 *
	 * If the check specifies a non-zero condition_mask then the parser
	 * only performs the check when the bits specified by condition_mask
	 * are non-zero.
2506 2507 2508 2509 2510
	 */
	struct {
		u32 offset;
		u32 mask;
		u32 expected;
2511 2512
		u32 condition_offset;
		u32 condition_mask;
2513 2514 2515 2516 2517 2518
	} bits[MAX_CMD_DESC_BITMASKS];
};

/*
 * A table of commands requiring special handling by the command parser.
 *
2519 2520 2521
 * Each engine has an array of tables. Each table consists of an array of
 * command descriptors, which must be sorted with command opcodes in
 * ascending order.
2522 2523 2524 2525 2526 2527
 */
struct drm_i915_cmd_table {
	const struct drm_i915_cmd_descriptor *table;
	int count;
};

C
Chris Wilson 已提交
2528
/* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2529 2530 2531 2532 2533 2534 2535 2536 2537 2538
#define __I915__(p) ({ \
	struct drm_i915_private *__p; \
	if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
		__p = (struct drm_i915_private *)p; \
	else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
		__p = to_i915((struct drm_device *)p); \
	else \
		BUILD_BUG(); \
	__p; \
})
C
Chris Wilson 已提交
2539
#define INTEL_INFO(p) 	(&__I915__(p)->info)
2540
#define INTEL_GEN(p)	(INTEL_INFO(p)->gen)
2541
#define INTEL_DEVID(p)	(INTEL_INFO(p)->device_id)
2542

2543
#define REVID_FOREVER		0xff
2544
#define INTEL_REVID(p)	(__I915__(p)->drm.pdev->revision)
2545 2546 2547 2548 2549 2550 2551 2552 2553 2554 2555 2556 2557 2558 2559 2560 2561 2562 2563 2564

#define GEN_FOREVER (0)
/*
 * Returns true if Gen is in inclusive range [Start, End].
 *
 * Use GEN_FOREVER for unbound start and or end.
 */
#define IS_GEN(p, s, e) ({ \
	unsigned int __s = (s), __e = (e); \
	BUILD_BUG_ON(!__builtin_constant_p(s)); \
	BUILD_BUG_ON(!__builtin_constant_p(e)); \
	if ((__s) != GEN_FOREVER) \
		__s = (s) - 1; \
	if ((__e) == GEN_FOREVER) \
		__e = BITS_PER_LONG - 1; \
	else \
		__e = (e) - 1; \
	!!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \
})

2565 2566 2567 2568 2569 2570 2571 2572
/*
 * Return true if revision is in range [since,until] inclusive.
 *
 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
 */
#define IS_REVID(p, since, until) \
	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))

2573 2574
#define IS_I830(dev)		(INTEL_DEVID(dev) == 0x3577)
#define IS_845G(dev)		(INTEL_DEVID(dev) == 0x2562)
2575
#define IS_I85X(dev)		(INTEL_INFO(dev)->is_i85x)
2576
#define IS_I865G(dev)		(INTEL_DEVID(dev) == 0x2572)
2577
#define IS_I915G(dev)		(INTEL_INFO(dev)->is_i915g)
2578 2579
#define IS_I915GM(dev)		(INTEL_DEVID(dev) == 0x2592)
#define IS_I945G(dev)		(INTEL_DEVID(dev) == 0x2772)
2580 2581 2582
#define IS_I945GM(dev)		(INTEL_INFO(dev)->is_i945gm)
#define IS_BROADWATER(dev)	(INTEL_INFO(dev)->is_broadwater)
#define IS_CRESTLINE(dev)	(INTEL_INFO(dev)->is_crestline)
2583
#define IS_GM45(dev)		(INTEL_DEVID(dev) == 0x2A42)
2584
#define IS_G4X(dev)		(INTEL_INFO(dev)->is_g4x)
2585 2586
#define IS_PINEVIEW_G(dev)	(INTEL_DEVID(dev) == 0xa001)
#define IS_PINEVIEW_M(dev)	(INTEL_DEVID(dev) == 0xa011)
2587 2588
#define IS_PINEVIEW(dev)	(INTEL_INFO(dev)->is_pineview)
#define IS_G33(dev)		(INTEL_INFO(dev)->is_g33)
2589
#define IS_IRONLAKE_M(dev)	(INTEL_DEVID(dev) == 0x0046)
2590
#define IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
2591 2592 2593
#define IS_IVB_GT1(dev)		(INTEL_DEVID(dev) == 0x0156 || \
				 INTEL_DEVID(dev) == 0x0152 || \
				 INTEL_DEVID(dev) == 0x015a)
2594
#define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
2595
#define IS_CHERRYVIEW(dev)	(INTEL_INFO(dev)->is_cherryview)
2596
#define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
2597
#define IS_BROADWELL(dev)	(INTEL_INFO(dev)->is_broadwell)
2598
#define IS_SKYLAKE(dev)	(INTEL_INFO(dev)->is_skylake)
2599
#define IS_BROXTON(dev)		(INTEL_INFO(dev)->is_broxton)
2600
#define IS_KABYLAKE(dev)	(INTEL_INFO(dev)->is_kabylake)
2601
#define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
2602
#define IS_HSW_EARLY_SDV(dev)	(IS_HASWELL(dev) && \
2603
				 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
B
Ben Widawsky 已提交
2604
#define IS_BDW_ULT(dev)		(IS_BROADWELL(dev) && \
2605
				 ((INTEL_DEVID(dev) & 0xf) == 0x6 ||	\
2606
				 (INTEL_DEVID(dev) & 0xf) == 0xb ||	\
2607
				 (INTEL_DEVID(dev) & 0xf) == 0xe))
V
Ville Syrjälä 已提交
2608 2609 2610
/* ULX machines are also considered ULT. */
#define IS_BDW_ULX(dev)		(IS_BROADWELL(dev) && \
				 (INTEL_DEVID(dev) & 0xf) == 0xe)
R
Rodrigo Vivi 已提交
2611 2612
#define IS_BDW_GT3(dev)		(IS_BROADWELL(dev) && \
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
B
Ben Widawsky 已提交
2613
#define IS_HSW_ULT(dev)		(IS_HASWELL(dev) && \
2614
				 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2615
#define IS_HSW_GT3(dev)		(IS_HASWELL(dev) && \
2616
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2617
/* ULX machines are also considered ULT. */
2618 2619
#define IS_HSW_ULX(dev)		(INTEL_DEVID(dev) == 0x0A0E || \
				 INTEL_DEVID(dev) == 0x0A1E)
2620 2621 2622 2623 2624 2625 2626 2627
#define IS_SKL_ULT(dev)		(INTEL_DEVID(dev) == 0x1906 || \
				 INTEL_DEVID(dev) == 0x1913 || \
				 INTEL_DEVID(dev) == 0x1916 || \
				 INTEL_DEVID(dev) == 0x1921 || \
				 INTEL_DEVID(dev) == 0x1926)
#define IS_SKL_ULX(dev)		(INTEL_DEVID(dev) == 0x190E || \
				 INTEL_DEVID(dev) == 0x1915 || \
				 INTEL_DEVID(dev) == 0x191E)
2628 2629 2630 2631 2632 2633 2634 2635
#define IS_KBL_ULT(dev)		(INTEL_DEVID(dev) == 0x5906 || \
				 INTEL_DEVID(dev) == 0x5913 || \
				 INTEL_DEVID(dev) == 0x5916 || \
				 INTEL_DEVID(dev) == 0x5921 || \
				 INTEL_DEVID(dev) == 0x5926)
#define IS_KBL_ULX(dev)		(INTEL_DEVID(dev) == 0x590E || \
				 INTEL_DEVID(dev) == 0x5915 || \
				 INTEL_DEVID(dev) == 0x591E)
2636 2637 2638 2639 2640
#define IS_SKL_GT3(dev)		(IS_SKYLAKE(dev) && \
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
#define IS_SKL_GT4(dev)		(IS_SKYLAKE(dev) && \
				 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)

2641
#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2642

2643 2644 2645 2646 2647 2648
#define SKL_REVID_A0		0x0
#define SKL_REVID_B0		0x1
#define SKL_REVID_C0		0x2
#define SKL_REVID_D0		0x3
#define SKL_REVID_E0		0x4
#define SKL_REVID_F0		0x5
2649 2650
#define SKL_REVID_G0		0x6
#define SKL_REVID_H0		0x7
2651

2652 2653
#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))

2654
#define BXT_REVID_A0		0x0
2655
#define BXT_REVID_A1		0x1
2656 2657
#define BXT_REVID_B0		0x3
#define BXT_REVID_C0		0x9
N
Nick Hoath 已提交
2658

2659 2660
#define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))

M
Mika Kuoppala 已提交
2661 2662
#define KBL_REVID_A0		0x0
#define KBL_REVID_B0		0x1
2663 2664 2665
#define KBL_REVID_C0		0x2
#define KBL_REVID_D0		0x3
#define KBL_REVID_E0		0x4
M
Mika Kuoppala 已提交
2666 2667 2668 2669

#define IS_KBL_REVID(p, since, until) \
	(IS_KABYLAKE(p) && IS_REVID(p, since, until))

2670 2671 2672 2673 2674 2675
/*
 * The genX designation typically refers to the render engine, so render
 * capability related checks should use IS_GEN, while display and other checks
 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 * chips, etc.).
 */
2676 2677 2678 2679 2680 2681 2682 2683
#define IS_GEN2(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(1)))
#define IS_GEN3(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(2)))
#define IS_GEN4(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(3)))
#define IS_GEN5(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(4)))
#define IS_GEN6(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(5)))
#define IS_GEN7(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(6)))
#define IS_GEN8(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(7)))
#define IS_GEN9(dev)	(!!(INTEL_INFO(dev)->gen_mask & BIT(8)))
2684

2685 2686 2687 2688 2689 2690 2691 2692 2693
#define ENGINE_MASK(id)	BIT(id)
#define RENDER_RING	ENGINE_MASK(RCS)
#define BSD_RING	ENGINE_MASK(VCS)
#define BLT_RING	ENGINE_MASK(BCS)
#define VEBOX_RING	ENGINE_MASK(VECS)
#define BSD2_RING	ENGINE_MASK(VCS2)
#define ALL_ENGINES	(~0)

#define HAS_ENGINE(dev_priv, id) \
2694
	(!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))
2695 2696 2697 2698 2699 2700

#define HAS_BSD(dev_priv)	HAS_ENGINE(dev_priv, VCS)
#define HAS_BSD2(dev_priv)	HAS_ENGINE(dev_priv, VCS2)
#define HAS_BLT(dev_priv)	HAS_ENGINE(dev_priv, BCS)
#define HAS_VEBOX(dev_priv)	HAS_ENGINE(dev_priv, VECS)

2701
#define HAS_LLC(dev)		(INTEL_INFO(dev)->has_llc)
2702
#define HAS_SNOOP(dev)		(INTEL_INFO(dev)->has_snoop)
2703
#define HAS_EDRAM(dev)		(!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
2704
#define HAS_WT(dev)		((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2705
				 HAS_EDRAM(dev))
2706 2707
#define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)

2708
#define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 6)
2709
#define HAS_LOGICAL_RING_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 8)
2710
#define USES_PPGTT(dev)		(i915.enable_ppgtt)
2711 2712
#define USES_FULL_PPGTT(dev)	(i915.enable_ppgtt >= 2)
#define USES_FULL_48BIT_PPGTT(dev)	(i915.enable_ppgtt == 3)
2713

2714
#define HAS_OVERLAY(dev)		(INTEL_INFO(dev)->has_overlay)
2715 2716
#define OVERLAY_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->overlay_needs_physical)

2717 2718
/* Early gen2 have a totally busted CS tlb and require pinned batches. */
#define HAS_BROKEN_CS_TLB(dev)		(IS_I830(dev) || IS_845G(dev))
2719 2720

/* WaRsDisableCoarsePowerGating:skl,bxt */
2721 2722 2723 2724
#define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
	(IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
	 IS_SKL_GT3(dev_priv) || \
	 IS_SKL_GT4(dev_priv))
2725

2726 2727 2728 2729 2730 2731 2732 2733
/*
 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
 * even when in MSI mode. This results in spurious interrupt warnings if the
 * legacy irq no. is shared with another device. The kernel then disables that
 * interrupt source and so prevents the other device from working properly.
 */
#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2734

2735 2736 2737 2738 2739 2740 2741 2742 2743 2744
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 * rows, which changed the alignment requirements and fence programming.
 */
#define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
						      IS_I915GM(dev)))
#define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)
#define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)

#define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2745
#define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2746

2747
#define HAS_IPS(dev)		(IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2748

2749 2750 2751
#define HAS_DP_MST(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \
				 INTEL_INFO(dev)->gen >= 9)

2752
#define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
2753
#define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
2754
#define HAS_PSR(dev)		(IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2755
				 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2756
				 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2757
#define HAS_RUNTIME_PM(dev)	(IS_GEN6(dev) || IS_HASWELL(dev) || \
S
Suketu Shah 已提交
2758
				 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2759
				 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
I
Imre Deak 已提交
2760
				 IS_KABYLAKE(dev) || IS_BROXTON(dev))
2761
#define HAS_RC6(dev)		(INTEL_INFO(dev)->gen >= 6)
2762
#define HAS_RC6p(dev)		(IS_GEN6(dev) || IS_IVYBRIDGE(dev))
P
Paulo Zanoni 已提交
2763

2764
#define HAS_CSR(dev)	(IS_GEN9(dev))
2765

2766 2767 2768 2769 2770
/*
 * For now, anything with a GuC requires uCode loading, and then supports
 * command submission once loaded. But these are logically independent
 * properties, so we have separate macros to test them.
 */
2771
#define HAS_GUC(dev)		(IS_GEN9(dev))
2772 2773
#define HAS_GUC_UCODE(dev)	(HAS_GUC(dev))
#define HAS_GUC_SCHED(dev)	(HAS_GUC(dev))
2774

2775 2776 2777
#define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
				    INTEL_INFO(dev)->gen >= 8)

2778
#define HAS_CORE_RING_FREQ(dev)	(INTEL_INFO(dev)->gen >= 6 && \
2779 2780
				 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
				 !IS_BROXTON(dev))
2781

2782 2783
#define HAS_POOLED_EU(dev)	(INTEL_INFO(dev)->has_pooled_eu)

2784 2785 2786 2787 2788 2789
#define INTEL_PCH_DEVICE_ID_MASK		0xff00
#define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
#define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
#define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
#define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
2790 2791
#define INTEL_PCH_SPT_DEVICE_ID_TYPE		0xA100
#define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE		0x9D00
2792
#define INTEL_PCH_KBP_DEVICE_ID_TYPE		0xA200
2793
#define INTEL_PCH_P2X_DEVICE_ID_TYPE		0x7100
2794
#define INTEL_PCH_P3X_DEVICE_ID_TYPE		0x7000
2795
#define INTEL_PCH_QEMU_DEVICE_ID_TYPE		0x2900 /* qemu q35 has 2918 */
2796

2797
#define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2798
#define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
2799
#define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2800
#define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2801
#define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
V
Ville Syrjälä 已提交
2802
#define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2803 2804
#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
#define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
B
Ben Widawsky 已提交
2805
#define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2806
#define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2807

2808 2809
#define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
			       IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2810

2811 2812 2813
/* DPF == dynamic parity feature */
#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2814

2815
#define GT_FREQUENCY_MULTIPLIER 50
A
Akash Goel 已提交
2816
#define GEN9_FREQ_SCALER 3
2817

2818 2819
#include "i915_trace.h"

2820 2821 2822 2823 2824 2825 2826 2827 2828
static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv)
{
#ifdef CONFIG_INTEL_IOMMU
	if (INTEL_GEN(dev_priv) >= 6 && intel_iommu_gfx_mapped)
		return true;
#endif
	return false;
}

2829 2830
extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
extern int i915_resume_switcheroo(struct drm_device *dev);
2831

2832 2833
int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv,
			       	int enable_ppgtt);
2834

2835 2836
bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value);

2837
/* i915_drv.c */
2838 2839 2840 2841 2842 2843 2844
void __printf(3, 4)
__i915_printk(struct drm_i915_private *dev_priv, const char *level,
	      const char *fmt, ...);

#define i915_report_error(dev_priv, fmt, ...)				   \
	__i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)

2845
#ifdef CONFIG_COMPAT
D
Dave Airlie 已提交
2846 2847
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
			      unsigned long arg);
2848
#endif
2849 2850
extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask);
extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv);
2851
extern int i915_reset(struct drm_i915_private *dev_priv);
2852
extern int intel_guc_reset(struct drm_i915_private *dev_priv);
2853
extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine);
2854 2855 2856 2857
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2858
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2859

2860
/* intel_hotplug.c */
2861 2862
void intel_hpd_irq_handler(struct drm_i915_private *dev_priv,
			   u32 pin_mask, u32 long_mask);
2863 2864 2865
void intel_hpd_init(struct drm_i915_private *dev_priv);
void intel_hpd_init_work(struct drm_i915_private *dev_priv);
void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2866
bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2867 2868
bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin);
2869

L
Linus Torvalds 已提交
2870
/* i915_irq.c */
2871 2872 2873 2874 2875 2876 2877 2878 2879 2880 2881 2882 2883 2884 2885 2886 2887
static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv)
{
	unsigned long delay;

	if (unlikely(!i915.enable_hangcheck))
		return;

	/* Don't continually defer the hangcheck so that it is always run at
	 * least once after work has been scheduled on any ring. Otherwise,
	 * we will ignore a hung ring if a second ring is kept busy.
	 */

	delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES);
	queue_delayed_work(system_long_wq,
			   &dev_priv->gpu_error.hangcheck_work, delay);
}

2888
__printf(3, 4)
2889 2890
void i915_handle_error(struct drm_i915_private *dev_priv,
		       u32 engine_mask,
2891
		       const char *fmt, ...);
L
Linus Torvalds 已提交
2892

2893
extern void intel_irq_init(struct drm_i915_private *dev_priv);
2894 2895
int intel_irq_install(struct drm_i915_private *dev_priv);
void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2896

2897 2898
extern void intel_uncore_sanitize(struct drm_i915_private *dev_priv);
extern void intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
2899
					bool restore_forcewake);
2900
extern void intel_uncore_init(struct drm_i915_private *dev_priv);
2901
extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private *dev_priv);
2902
extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private *dev_priv);
2903 2904 2905
extern void intel_uncore_fini(struct drm_i915_private *dev_priv);
extern void intel_uncore_forcewake_reset(struct drm_i915_private *dev_priv,
					 bool restore);
2906
const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2907
void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2908
				enum forcewake_domains domains);
2909
void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2910
				enum forcewake_domains domains);
2911 2912 2913 2914 2915 2916 2917
/* Like above but the caller must manage the uncore.lock itself.
 * Must be used with I915_READ_FW and friends.
 */
void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
					enum forcewake_domains domains);
2918 2919
u64 intel_uncore_edram_size(struct drm_i915_private *dev_priv);

2920
void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2921

2922 2923 2924 2925 2926 2927 2928 2929 2930 2931 2932
int intel_wait_for_register(struct drm_i915_private *dev_priv,
			    i915_reg_t reg,
			    const u32 mask,
			    const u32 value,
			    const unsigned long timeout_ms);
int intel_wait_for_register_fw(struct drm_i915_private *dev_priv,
			       i915_reg_t reg,
			       const u32 mask,
			       const u32 value,
			       const unsigned long timeout_ms);

2933 2934 2935 2936 2937
static inline bool intel_gvt_active(struct drm_i915_private *dev_priv)
{
	return dev_priv->gvt.initialized;
}

2938
static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv)
2939
{
2940
	return dev_priv->vgpu.active;
2941
}
2942

2943
void
2944
i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2945
		     u32 status_mask);
2946 2947

void
2948
i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2949
		      u32 status_mask);
2950

2951 2952
void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2953 2954 2955
void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
				   uint32_t mask,
				   uint32_t bits);
2956 2957 2958 2959 2960 2961 2962 2963 2964 2965 2966 2967 2968
void ilk_update_display_irq(struct drm_i915_private *dev_priv,
			    uint32_t interrupt_mask,
			    uint32_t enabled_irq_mask);
static inline void
ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, bits);
}
static inline void
ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ilk_update_display_irq(dev_priv, bits, 0);
}
2969 2970 2971 2972 2973 2974 2975 2976 2977 2978 2979 2980 2981 2982
void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
			 enum pipe pipe,
			 uint32_t interrupt_mask,
			 uint32_t enabled_irq_mask);
static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
				       enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
}
static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
					enum pipe pipe, uint32_t bits)
{
	bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
}
2983 2984 2985
void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
				  uint32_t interrupt_mask,
				  uint32_t enabled_irq_mask);
2986 2987 2988 2989 2990 2991 2992 2993 2994 2995 2996
static inline void
ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, bits);
}
static inline void
ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
{
	ibx_display_interrupt_update(dev_priv, bits, 0);
}

2997 2998 2999 3000 3001 3002 3003 3004 3005
/* i915_gem.c */
int i915_gem_create_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
			  struct drm_file *file_priv);
int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3006 3007
int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3008 3009 3010 3011 3012 3013
int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
			      struct drm_file *file_priv);
int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
			     struct drm_file *file_priv);
int i915_gem_execbuffer(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
J
Jesse Barnes 已提交
3014 3015
int i915_gem_execbuffer2(struct drm_device *dev, void *data,
			 struct drm_file *file_priv);
3016 3017
int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
B
Ben Widawsky 已提交
3018 3019 3020 3021
int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
			       struct drm_file *file);
3022 3023
int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
			    struct drm_file *file_priv);
3024 3025
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file_priv);
3026 3027 3028 3029
int i915_gem_set_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
int i915_gem_get_tiling(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3030
void i915_gem_init_userptr(struct drm_i915_private *dev_priv);
3031 3032
int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
			   struct drm_file *file);
3033 3034
int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
				struct drm_file *file_priv);
3035 3036
int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file_priv);
3037 3038
void i915_gem_load_init(struct drm_device *dev);
void i915_gem_load_cleanup(struct drm_device *dev);
3039
void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
3040 3041
int i915_gem_freeze_late(struct drm_i915_private *dev_priv);

3042 3043
void *i915_gem_object_alloc(struct drm_device *dev);
void i915_gem_object_free(struct drm_i915_gem_object *obj);
3044 3045
void i915_gem_object_init(struct drm_i915_gem_object *obj,
			 const struct drm_i915_gem_object_ops *ops);
3046
struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev,
3047
						  size_t size);
3048 3049
struct drm_i915_gem_object *i915_gem_object_create_from_data(
		struct drm_device *dev, const void *data, size_t size);
3050
void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file);
3051
void i915_gem_free_object(struct drm_gem_object *obj);
3052

3053 3054 3055
int __must_check
i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
			 const struct i915_ggtt_view *view,
3056
			 u64 size,
3057 3058
			 u64 alignment,
			 u64 flags);
3059 3060 3061

int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
		  u32 flags);
3062
void __i915_vma_set_map_and_fenceable(struct i915_vma *vma);
3063
int __must_check i915_vma_unbind(struct i915_vma *vma);
3064 3065
void i915_vma_close(struct i915_vma *vma);
void i915_vma_destroy(struct i915_vma *vma);
3066 3067

int i915_gem_object_unbind(struct drm_i915_gem_object *obj);
3068
int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
3069
void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
3070
void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
3071

3072 3073 3074
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
				    int *needs_clflush);

3075
int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
3076 3077

static inline int __sg_page_count(struct scatterlist *sg)
3078
{
3079 3080
	return sg->length >> PAGE_SHIFT;
}
3081

3082 3083 3084
struct page *
i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n);

3085 3086 3087 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097 3098 3099 3100 3101
static inline dma_addr_t
i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, int n)
{
	if (n < obj->get_page.last) {
		obj->get_page.sg = obj->pages->sgl;
		obj->get_page.last = 0;
	}

	while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
		obj->get_page.last += __sg_page_count(obj->get_page.sg++);
		if (unlikely(sg_is_chain(obj->get_page.sg)))
			obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
	}

	return sg_dma_address(obj->get_page.sg) + ((n - obj->get_page.last) << PAGE_SHIFT);
}

3102 3103
static inline struct page *
i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
3104
{
3105 3106
	if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
		return NULL;
3107

3108 3109 3110 3111
	if (n < obj->get_page.last) {
		obj->get_page.sg = obj->pages->sgl;
		obj->get_page.last = 0;
	}
3112

3113 3114 3115 3116 3117
	while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
		obj->get_page.last += __sg_page_count(obj->get_page.sg++);
		if (unlikely(sg_is_chain(obj->get_page.sg)))
			obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
	}
3118

3119
	return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
3120
}
3121

3122 3123 3124 3125 3126
static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
{
	BUG_ON(obj->pages == NULL);
	obj->pages_pin_count++;
}
3127

3128 3129 3130 3131 3132 3133
static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
{
	BUG_ON(obj->pages_pin_count == 0);
	obj->pages_pin_count--;
}

3134 3135 3136 3137 3138 3139 3140 3141
/**
 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
 * @obj - the object to map into kernel address space
 *
 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
 * pages and then returns a contiguous mapping of the backing storage into
 * the kernel address space.
 *
3142 3143
 * The caller must hold the struct_mutex, and is responsible for calling
 * i915_gem_object_unpin_map() when the mapping is no longer required.
3144
 *
3145 3146
 * Returns the pointer through which to access the mapped object, or an
 * ERR_PTR() on error.
3147 3148 3149 3150 3151 3152 3153 3154 3155 3156 3157 3158 3159 3160 3161 3162 3163 3164 3165 3166
 */
void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj);

/**
 * i915_gem_object_unpin_map - releases an earlier mapping
 * @obj - the object to unmap
 *
 * After pinning the object and mapping its pages, once you are finished
 * with your access, call i915_gem_object_unpin_map() to release the pin
 * upon the mapping. Once the pin count reaches zero, that mapping may be
 * removed.
 *
 * The caller must hold the struct_mutex.
 */
static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj)
{
	lockdep_assert_held(&obj->base.dev->struct_mutex);
	i915_gem_object_unpin_pages(obj);
}

3167
int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
3168
int i915_gem_object_sync(struct drm_i915_gem_object *obj,
3169
			 struct drm_i915_gem_request *to);
B
Ben Widawsky 已提交
3170
void i915_vma_move_to_active(struct i915_vma *vma,
3171 3172
			     struct drm_i915_gem_request *req,
			     unsigned int flags);
3173 3174 3175
int i915_gem_dumb_create(struct drm_file *file_priv,
			 struct drm_device *dev,
			 struct drm_mode_create_dumb *args);
3176 3177
int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
		      uint32_t handle, uint64_t *offset);
3178 3179 3180 3181 3182

void i915_gem_track_fb(struct drm_i915_gem_object *old,
		       struct drm_i915_gem_object *new,
		       unsigned frontbuffer_bits);

3183
int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
3184

3185
struct drm_i915_gem_request *
3186
i915_gem_find_active_request(struct intel_engine_cs *engine);
3187

3188
void i915_gem_retire_requests(struct drm_i915_private *dev_priv);
3189

3190 3191 3192 3193 3194 3195 3196 3197 3198 3199 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209
static inline u32 i915_reset_counter(struct i915_gpu_error *error)
{
	return atomic_read(&error->reset_counter);
}

static inline bool __i915_reset_in_progress(u32 reset)
{
	return unlikely(reset & I915_RESET_IN_PROGRESS_FLAG);
}

static inline bool __i915_reset_in_progress_or_wedged(u32 reset)
{
	return unlikely(reset & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
}

static inline bool __i915_terminally_wedged(u32 reset)
{
	return unlikely(reset & I915_WEDGED);
}

3210 3211
static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
{
3212 3213 3214 3215 3216 3217
	return __i915_reset_in_progress(i915_reset_counter(error));
}

static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error *error)
{
	return __i915_reset_in_progress_or_wedged(i915_reset_counter(error));
3218 3219 3220 3221
}

static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
{
3222
	return __i915_terminally_wedged(i915_reset_counter(error));
M
Mika Kuoppala 已提交
3223 3224 3225 3226
}

static inline u32 i915_reset_count(struct i915_gpu_error *error)
{
3227
	return ((i915_reset_counter(error) & ~I915_WEDGED) + 1) / 2;
3228
}
3229

3230
void i915_gem_reset(struct drm_device *dev);
3231
bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
3232
int __must_check i915_gem_init(struct drm_device *dev);
3233 3234
int __must_check i915_gem_init_hw(struct drm_device *dev);
void i915_gem_init_swizzling(struct drm_device *dev);
3235
void i915_gem_cleanup_engines(struct drm_device *dev);
3236
int __must_check i915_gem_wait_for_idle(struct drm_i915_private *dev_priv);
3237
int __must_check i915_gem_suspend(struct drm_device *dev);
3238
void i915_gem_resume(struct drm_device *dev);
3239
int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3240
int __must_check
3241 3242 3243
i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
			       bool readonly);
int __must_check
3244 3245 3246
i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
				  bool write);
int __must_check
3247 3248
i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
int __must_check
3249 3250
i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
				     u32 alignment,
3251 3252 3253
				     const struct i915_ggtt_view *view);
void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
					      const struct i915_ggtt_view *view);
3254
int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3255
				int align);
3256
int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3257
void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3258

3259 3260 3261
u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u64 size,
			   int tiling_mode);
u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
3262
				int tiling_mode, bool fenced);
3263

3264 3265 3266
int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
				    enum i915_cache_level cache_level);

3267 3268 3269 3270 3271 3272
struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
				struct dma_buf *dma_buf);

struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
				struct drm_gem_object *gem_obj, int flags);

3273 3274 3275 3276 3277
u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
				  const struct i915_ggtt_view *view);
u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
			struct i915_address_space *vm);
static inline u64
3278
i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3279
{
3280
	return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3281
}
3282 3283

bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3284
				  const struct i915_ggtt_view *view);
3285
bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3286
			struct i915_address_space *vm);
3287 3288

struct i915_vma *
3289 3290 3291 3292 3293
i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
		    struct i915_address_space *vm);
struct i915_vma *
i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
			  const struct i915_ggtt_view *view);
3294

3295 3296
struct i915_vma *
i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3297 3298 3299 3300
				  struct i915_address_space *vm);
struct i915_vma *
i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
				       const struct i915_ggtt_view *view);
3301

3302 3303 3304 3305
static inline struct i915_vma *
i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
{
	return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
B
Ben Widawsky 已提交
3306
}
3307
bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3308

3309
/* Some GGTT VM helpers */
3310 3311 3312 3313 3314 3315
static inline struct i915_hw_ppgtt *
i915_vm_to_ppgtt(struct i915_address_space *vm)
{
	return container_of(vm, struct i915_hw_ppgtt, base);
}

3316 3317
static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
{
3318
	return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3319 3320
}

3321 3322
unsigned long
i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj);
B
Ben Widawsky 已提交
3323

3324 3325 3326 3327 3328 3329 3330
void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
				     const struct i915_ggtt_view *view);
static inline void
i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
{
	i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
}
3331

3332 3333 3334 3335 3336 3337 3338 3339 3340
/* i915_gem_fence.c */
int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);

bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);

void i915_gem_restore_fences(struct drm_device *dev);

3341 3342 3343 3344
void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);

3345
/* i915_gem_context.c */
3346
int __must_check i915_gem_context_init(struct drm_device *dev);
3347
void i915_gem_context_lost(struct drm_i915_private *dev_priv);
3348
void i915_gem_context_fini(struct drm_device *dev);
3349
void i915_gem_context_reset(struct drm_device *dev);
3350
int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3351
void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3352
int i915_switch_context(struct drm_i915_gem_request *req);
3353
int i915_gem_switch_to_kernel_context(struct drm_i915_private *dev_priv);
3354
void i915_gem_context_free(struct kref *ctx_ref);
3355 3356
struct drm_i915_gem_object *
i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3357 3358
struct i915_gem_context *
i915_gem_context_create_gvt(struct drm_device *dev);
3359 3360 3361 3362 3363 3364

static inline struct i915_gem_context *
i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id)
{
	struct i915_gem_context *ctx;

3365
	lockdep_assert_held(&file_priv->dev_priv->drm.struct_mutex);
3366 3367 3368 3369 3370 3371 3372 3373

	ctx = idr_find(&file_priv->context_idr, id);
	if (!ctx)
		return ERR_PTR(-ENOENT);

	return ctx;
}

3374 3375
static inline struct i915_gem_context *
i915_gem_context_get(struct i915_gem_context *ctx)
3376
{
3377
	kref_get(&ctx->ref);
3378
	return ctx;
3379 3380
}

3381
static inline void i915_gem_context_put(struct i915_gem_context *ctx)
3382
{
3383
	lockdep_assert_held(&ctx->i915->drm.struct_mutex);
3384
	kref_put(&ctx->ref, i915_gem_context_free);
3385 3386
}

3387
static inline bool i915_gem_context_is_default(const struct i915_gem_context *c)
3388
{
3389
	return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3390 3391
}

3392 3393 3394 3395
int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
				  struct drm_file *file);
int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
				   struct drm_file *file);
3396 3397 3398 3399
int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file_priv);
int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
				    struct drm_file *file_priv);
3400 3401
int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
				       struct drm_file *file);
3402

3403
/* i915_gem_evict.c */
3404
int __must_check i915_gem_evict_something(struct i915_address_space *vm,
3405
					  u64 min_size, u64 alignment,
3406
					  unsigned cache_level,
3407
					  u64 start, u64 end,
3408
					  unsigned flags);
3409
int __must_check i915_gem_evict_for_vma(struct i915_vma *target);
3410
int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3411

3412
/* belongs in i915_gem_gtt.h */
3413
static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv)
3414
{
3415
	if (INTEL_GEN(dev_priv) < 6)
3416 3417
		intel_gtt_chipset_flush();
}
3418

3419
/* i915_gem_stolen.c */
3420 3421 3422
int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
				struct drm_mm_node *node, u64 size,
				unsigned alignment);
3423 3424 3425 3426
int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
					 struct drm_mm_node *node, u64 size,
					 unsigned alignment, u64 start,
					 u64 end);
3427 3428
void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
				 struct drm_mm_node *node);
3429 3430
int i915_gem_init_stolen(struct drm_device *dev);
void i915_gem_cleanup_stolen(struct drm_device *dev);
3431 3432
struct drm_i915_gem_object *
i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3433 3434 3435 3436 3437
struct drm_i915_gem_object *
i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
					       u32 stolen_offset,
					       u32 gtt_offset,
					       u32 size);
3438

3439 3440
/* i915_gem_shrinker.c */
unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3441
			      unsigned long target,
3442 3443 3444 3445
			      unsigned flags);
#define I915_SHRINK_PURGEABLE 0x1
#define I915_SHRINK_UNBOUND 0x2
#define I915_SHRINK_BOUND 0x4
3446
#define I915_SHRINK_ACTIVE 0x8
3447
#define I915_SHRINK_VMAPS 0x10
3448 3449
unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3450
void i915_gem_shrinker_cleanup(struct drm_i915_private *dev_priv);
3451 3452


3453
/* i915_gem_tiling.c */
3454
static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3455
{
3456
	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
3457 3458 3459 3460 3461

	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
		obj->tiling_mode != I915_TILING_NONE;
}

3462
/* i915_debugfs.c */
3463
#ifdef CONFIG_DEBUG_FS
3464 3465
int i915_debugfs_register(struct drm_i915_private *dev_priv);
void i915_debugfs_unregister(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3466
int i915_debugfs_connector_add(struct drm_connector *connector);
3467 3468
void intel_display_crc_init(struct drm_device *dev);
#else
3469 3470
static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;}
static inline void i915_debugfs_unregister(struct drm_i915_private *dev_priv) {}
3471 3472
static inline int i915_debugfs_connector_add(struct drm_connector *connector)
{ return 0; }
3473
static inline void intel_display_crc_init(struct drm_device *dev) {}
3474
#endif
3475 3476

/* i915_gpu_error.c */
3477 3478
__printf(2, 3)
void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3479 3480
int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
			    const struct i915_error_state_file_priv *error);
3481
int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3482
			      struct drm_i915_private *i915,
3483 3484 3485 3486 3487 3488
			      size_t count, loff_t pos);
static inline void i915_error_state_buf_release(
	struct drm_i915_error_state_buf *eb)
{
	kfree(eb->buf);
}
3489 3490
void i915_capture_error_state(struct drm_i915_private *dev_priv,
			      u32 engine_mask,
3491
			      const char *error_msg);
3492 3493 3494 3495 3496
void i915_error_state_get(struct drm_device *dev,
			  struct i915_error_state_file_priv *error_priv);
void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
void i915_destroy_error_state(struct drm_device *dev);

3497
void i915_get_extra_instdone(struct drm_i915_private *dev_priv, uint32_t *instdone);
3498
const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3499

3500
/* i915_cmd_parser.c */
3501
int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv);
3502 3503 3504 3505 3506 3507 3508 3509 3510
int intel_engine_init_cmd_parser(struct intel_engine_cs *engine);
void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine);
bool intel_engine_needs_cmd_parser(struct intel_engine_cs *engine);
int intel_engine_cmd_parser(struct intel_engine_cs *engine,
			    struct drm_i915_gem_object *batch_obj,
			    struct drm_i915_gem_object *shadow_batch_obj,
			    u32 batch_start_offset,
			    u32 batch_len,
			    bool is_master);
3511

3512 3513 3514
/* i915_suspend.c */
extern int i915_save_state(struct drm_device *dev);
extern int i915_restore_state(struct drm_device *dev);
3515

B
Ben Widawsky 已提交
3516 3517 3518 3519
/* i915_sysfs.c */
void i915_setup_sysfs(struct drm_device *dev_priv);
void i915_teardown_sysfs(struct drm_device *dev_priv);

3520 3521 3522
/* intel_i2c.c */
extern int intel_setup_gmbus(struct drm_device *dev);
extern void intel_teardown_gmbus(struct drm_device *dev);
3523 3524
extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
				     unsigned int pin);
3525

3526 3527
extern struct i2c_adapter *
intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
C
Chris Wilson 已提交
3528 3529
extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3530
static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3531 3532 3533
{
	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
}
3534 3535
extern void intel_i2c_reset(struct drm_device *dev);

3536
/* intel_bios.c */
3537
int intel_bios_init(struct drm_i915_private *dev_priv);
J
Jani Nikula 已提交
3538
bool intel_bios_is_valid_vbt(const void *buf, size_t size);
3539
bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv);
3540
bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin);
3541
bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port);
3542
bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port);
3543
bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port);
3544
bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port);
3545 3546
bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv,
				     enum port port);
3547

3548
/* intel_opregion.c */
3549
#ifdef CONFIG_ACPI
3550
extern int intel_opregion_setup(struct drm_i915_private *dev_priv);
3551 3552
extern void intel_opregion_register(struct drm_i915_private *dev_priv);
extern void intel_opregion_unregister(struct drm_i915_private *dev_priv);
3553
extern void intel_opregion_asle_intr(struct drm_i915_private *dev_priv);
3554 3555
extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
					 bool enable);
3556
extern int intel_opregion_notify_adapter(struct drm_i915_private *dev_priv,
3557
					 pci_power_t state);
3558
extern int intel_opregion_get_panel_type(struct drm_i915_private *dev_priv);
3559
#else
3560
static inline int intel_opregion_setup(struct drm_i915_private *dev) { return 0; }
3561 3562
static inline void intel_opregion_register(struct drm_i915_private *dev_priv) { }
static inline void intel_opregion_unregister(struct drm_i915_private *dev_priv) { }
3563 3564 3565
static inline void intel_opregion_asle_intr(struct drm_i915_private *dev_priv)
{
}
3566 3567 3568 3569 3570
static inline int
intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
{
	return 0;
}
3571
static inline int
3572
intel_opregion_notify_adapter(struct drm_i915_private *dev, pci_power_t state)
3573 3574 3575
{
	return 0;
}
3576
static inline int intel_opregion_get_panel_type(struct drm_i915_private *dev)
3577 3578 3579
{
	return -ENODEV;
}
3580
#endif
3581

J
Jesse Barnes 已提交
3582 3583 3584 3585 3586 3587 3588 3589 3590
/* intel_acpi.c */
#ifdef CONFIG_ACPI
extern void intel_register_dsm_handler(void);
extern void intel_unregister_dsm_handler(void);
#else
static inline void intel_register_dsm_handler(void) { return; }
static inline void intel_unregister_dsm_handler(void) { return; }
#endif /* CONFIG_ACPI */

3591 3592 3593 3594 3595 3596 3597 3598 3599 3600
/* intel_device_info.c */
static inline struct intel_device_info *
mkwrite_device_info(struct drm_i915_private *dev_priv)
{
	return (struct intel_device_info *)&dev_priv->info;
}

void intel_device_info_runtime_init(struct drm_i915_private *dev_priv);
void intel_device_info_dump(struct drm_i915_private *dev_priv);

J
Jesse Barnes 已提交
3601
/* modesetting */
3602
extern void intel_modeset_init_hw(struct drm_device *dev);
J
Jesse Barnes 已提交
3603
extern void intel_modeset_init(struct drm_device *dev);
3604
extern void intel_modeset_gem_init(struct drm_device *dev);
J
Jesse Barnes 已提交
3605
extern void intel_modeset_cleanup(struct drm_device *dev);
3606
extern int intel_connector_register(struct drm_connector *);
3607
extern void intel_connector_unregister(struct drm_connector *);
3608
extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3609
extern void intel_display_resume(struct drm_device *dev);
3610
extern void i915_redisable_vga(struct drm_device *dev);
3611
extern void i915_redisable_vga_power_on(struct drm_device *dev);
3612
extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);
P
Paulo Zanoni 已提交
3613
extern void intel_init_pch_refclk(struct drm_device *dev);
3614
extern void intel_set_rps(struct drm_i915_private *dev_priv, u8 val);
3615 3616
extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
				  bool enable);
3617

B
Ben Widawsky 已提交
3618 3619
int i915_reg_read_ioctl(struct drm_device *dev, void *data,
			struct drm_file *file);
3620

3621
/* overlay */
3622 3623
extern struct intel_overlay_error_state *
intel_overlay_capture_error_state(struct drm_i915_private *dev_priv);
3624 3625
extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
					    struct intel_overlay_error_state *error);
3626

3627 3628
extern struct intel_display_error_state *
intel_display_capture_error_state(struct drm_i915_private *dev_priv);
3629
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3630 3631
					    struct drm_device *dev,
					    struct intel_display_error_state *error);
3632

3633 3634
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3635 3636

/* intel_sideband.c */
3637 3638
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3639
u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3640 3641
u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
3642 3643 3644 3645
u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3646 3647
u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3648 3649
u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3650 3651 3652 3653
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
		   enum intel_sbi_destination destination);
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
		     enum intel_sbi_destination destination);
3654 3655
u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3656

3657 3658 3659 3660
/* intel_dpio_phy.c */
void chv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 deemph_reg_value, u32 margin_reg_value,
			      bool uniq_trans_scale);
3661 3662
void chv_data_lane_soft_reset(struct intel_encoder *encoder,
			      bool reset);
3663
void chv_phy_pre_pll_enable(struct intel_encoder *encoder);
3664 3665
void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
void chv_phy_release_cl2_override(struct intel_encoder *encoder);
3666
void chv_phy_post_pll_disable(struct intel_encoder *encoder);
3667

3668 3669 3670
void vlv_set_phy_signal_level(struct intel_encoder *encoder,
			      u32 demph_reg_value, u32 preemph_reg_value,
			      u32 uniqtranscale_reg_value, u32 tx3_demph);
3671
void vlv_phy_pre_pll_enable(struct intel_encoder *encoder);
3672
void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder);
3673
void vlv_phy_reset_lanes(struct intel_encoder *encoder);
3674

3675 3676
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3677

3678 3679 3680 3681 3682 3683 3684 3685 3686 3687 3688 3689 3690
#define I915_READ8(reg)		dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
#define I915_WRITE8(reg, val)	dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)

#define I915_READ16(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
#define I915_WRITE16(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
#define I915_READ16_NOTRACE(reg)	dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
#define I915_WRITE16_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)

#define I915_READ(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
#define I915_WRITE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
#define I915_READ_NOTRACE(reg)		dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
#define I915_WRITE_NOTRACE(reg, val)	dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)

3691 3692 3693 3694 3695 3696
/* Be very careful with read/write 64-bit values. On 32-bit machines, they
 * will be implemented using 2 32-bit writes in an arbitrary order with
 * an arbitrary delay between them. This can cause the hardware to
 * act upon the intermediate value, possibly leading to corruption and
 * machine death. You have been warned.
 */
3697 3698
#define I915_WRITE64(reg, val)	dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
#define I915_READ64(reg)	dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3699

3700
#define I915_READ64_2x32(lower_reg, upper_reg) ({			\
3701 3702
	u32 upper, lower, old_upper, loop = 0;				\
	upper = I915_READ(upper_reg);					\
3703
	do {								\
3704
		old_upper = upper;					\
3705
		lower = I915_READ(lower_reg);				\
3706 3707
		upper = I915_READ(upper_reg);				\
	} while (upper != old_upper && loop++ < 2);			\
3708
	(u64)upper << 32 | lower; })
3709

3710 3711 3712
#define POSTING_READ(reg)	(void)I915_READ_NOTRACE(reg)
#define POSTING_READ16(reg)	(void)I915_READ16_NOTRACE(reg)

3713 3714
#define __raw_read(x, s) \
static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3715
					     i915_reg_t reg) \
3716
{ \
3717
	return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3718 3719 3720 3721
}

#define __raw_write(x, s) \
static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3722
				       i915_reg_t reg, uint##x##_t val) \
3723
{ \
3724
	write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3725 3726 3727 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738
}
__raw_read(8, b)
__raw_read(16, w)
__raw_read(32, l)
__raw_read(64, q)

__raw_write(8, b)
__raw_write(16, w)
__raw_write(32, l)
__raw_write(64, q)

#undef __raw_read
#undef __raw_write

3739 3740 3741 3742 3743 3744 3745
/* These are untraced mmio-accessors that are only valid to be used inside
 * criticial sections inside IRQ handlers where forcewake is explicitly
 * controlled.
 * Think twice, and think again, before using these.
 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
 * intel_uncore_forcewake_irqunlock().
 */
3746 3747
#define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
#define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3748
#define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3749 3750
#define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)

3751 3752 3753 3754
/* "Broadcast RGB" property */
#define INTEL_BROADCAST_RGB_AUTO 0
#define INTEL_BROADCAST_RGB_FULL 1
#define INTEL_BROADCAST_RGB_LIMITED 2
3755

3756
static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3757
{
3758
	if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3759
		return VLV_VGACNTRL;
3760 3761
	else if (INTEL_INFO(dev)->gen >= 5)
		return CPU_VGACNTRL;
3762 3763 3764 3765
	else
		return VGACNTRL;
}

3766 3767 3768 3769 3770 3771 3772
static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
{
	unsigned long j = msecs_to_jiffies(m);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3773 3774 3775 3776 3777
static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
{
        return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
}

3778 3779 3780 3781 3782 3783 3784 3785
static inline unsigned long
timespec_to_jiffies_timeout(const struct timespec *value)
{
	unsigned long j = timespec_to_jiffies(value);

	return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
}

3786 3787 3788 3789 3790 3791 3792 3793 3794
/*
 * If you need to wait X milliseconds between events A and B, but event B
 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
 * when event A happened, then just before event B you call this function and
 * pass the timestamp as the first argument, and X as the second argument.
 */
static inline void
wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
{
3795
	unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3796 3797 3798 3799 3800 3801 3802 3803 3804 3805

	/*
	 * Don't re-read the value of "jiffies" every time since it may change
	 * behind our back and break the math.
	 */
	tmp_jiffies = jiffies;
	target_jiffies = timestamp_jiffies +
			 msecs_to_jiffies_timeout(to_wait_ms);

	if (time_after(target_jiffies, tmp_jiffies)) {
3806 3807 3808 3809
		remaining_jiffies = target_jiffies - tmp_jiffies;
		while (remaining_jiffies)
			remaining_jiffies =
			    schedule_timeout_uninterruptible(remaining_jiffies);
3810 3811
	}
}
3812 3813
static inline bool __i915_request_irq_complete(struct drm_i915_gem_request *req)
{
3814 3815
	struct intel_engine_cs *engine = req->engine;

3816 3817 3818 3819 3820 3821
	/* Before we do the heavier coherent read of the seqno,
	 * check the value (hopefully) in the CPU cacheline.
	 */
	if (i915_gem_request_completed(req))
		return true;

3822 3823 3824 3825 3826 3827 3828 3829 3830 3831 3832
	/* Ensure our read of the seqno is coherent so that we
	 * do not "miss an interrupt" (i.e. if this is the last
	 * request and the seqno write from the GPU is not visible
	 * by the time the interrupt fires, we will see that the
	 * request is incomplete and go back to sleep awaiting
	 * another interrupt that will never come.)
	 *
	 * Strictly, we only need to do this once after an interrupt,
	 * but it is easier and safer to do it every time the waiter
	 * is woken.
	 */
3833
	if (engine->irq_seqno_barrier &&
3834 3835
	    READ_ONCE(engine->breadcrumbs.irq_seqno_bh) == current &&
	    cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) {
3836 3837
		struct task_struct *tsk;

3838 3839 3840 3841 3842 3843 3844 3845 3846 3847 3848 3849
		/* The ordering of irq_posted versus applying the barrier
		 * is crucial. The clearing of the current irq_posted must
		 * be visible before we perform the barrier operation,
		 * such that if a subsequent interrupt arrives, irq_posted
		 * is reasserted and our task rewoken (which causes us to
		 * do another __i915_request_irq_complete() immediately
		 * and reapply the barrier). Conversely, if the clear
		 * occurs after the barrier, then an interrupt that arrived
		 * whilst we waited on the barrier would not trigger a
		 * barrier on the next pass, and the read may not see the
		 * seqno update.
		 */
3850
		engine->irq_seqno_barrier(engine);
3851 3852 3853 3854 3855 3856 3857 3858

		/* If we consume the irq, but we are no longer the bottom-half,
		 * the real bottom-half may not have serialised their own
		 * seqno check with the irq-barrier (i.e. may have inspected
		 * the seqno before we believe it coherent since they see
		 * irq_posted == false but we are still running).
		 */
		rcu_read_lock();
3859
		tsk = READ_ONCE(engine->breadcrumbs.irq_seqno_bh);
3860 3861 3862 3863 3864 3865 3866 3867 3868 3869
		if (tsk && tsk != current)
			/* Note that if the bottom-half is changed as we
			 * are sending the wake-up, the new bottom-half will
			 * be woken by whomever made the change. We only have
			 * to worry about when we steal the irq-posted for
			 * ourself.
			 */
			wake_up_process(tsk);
		rcu_read_unlock();

3870 3871 3872
		if (i915_gem_request_completed(req))
			return true;
	}
3873 3874 3875 3876 3877 3878 3879 3880 3881 3882 3883 3884 3885 3886 3887

	/* We need to check whether any gpu reset happened in between
	 * the request being submitted and now. If a reset has occurred,
	 * the seqno will have been advance past ours and our request
	 * is complete. If we are in the process of handling a reset,
	 * the request is effectively complete as the rendering will
	 * be discarded, but we need to return in order to drop the
	 * struct_mutex.
	 */
	if (i915_reset_in_progress(&req->i915->gpu_error))
		return true;

	return false;
}

L
Linus Torvalds 已提交
3888
#endif