intel_lrc.c 65.7 KB
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/*
 * Copyright © 2014 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Ben Widawsky <ben@bwidawsk.net>
 *    Michel Thierry <michel.thierry@intel.com>
 *    Thomas Daniel <thomas.daniel@intel.com>
 *    Oscar Mateo <oscar.mateo@intel.com>
 *
 */

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/**
 * DOC: Logical Rings, Logical Ring Contexts and Execlists
 *
 * Motivation:
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 * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts".
 * These expanded contexts enable a number of new abilities, especially
 * "Execlists" (also implemented in this file).
 *
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 * One of the main differences with the legacy HW contexts is that logical
 * ring contexts incorporate many more things to the context's state, like
 * PDPs or ringbuffer control registers:
 *
 * The reason why PDPs are included in the context is straightforward: as
 * PPGTTs (per-process GTTs) are actually per-context, having the PDPs
 * contained there mean you don't need to do a ppgtt->switch_mm yourself,
 * instead, the GPU will do it for you on the context switch.
 *
 * But, what about the ringbuffer control registers (head, tail, etc..)?
 * shouldn't we just need a set of those per engine command streamer? This is
 * where the name "Logical Rings" starts to make sense: by virtualizing the
 * rings, the engine cs shifts to a new "ring buffer" with every context
 * switch. When you want to submit a workload to the GPU you: A) choose your
 * context, B) find its appropriate virtualized ring, C) write commands to it
 * and then, finally, D) tell the GPU to switch to that context.
 *
 * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch
 * to a contexts is via a context execution list, ergo "Execlists".
 *
 * LRC implementation:
 * Regarding the creation of contexts, we have:
 *
 * - One global default context.
 * - One local default context for each opened fd.
 * - One local extra context for each context create ioctl call.
 *
 * Now that ringbuffers belong per-context (and not per-engine, like before)
 * and that contexts are uniquely tied to a given engine (and not reusable,
 * like before) we need:
 *
 * - One ringbuffer per-engine inside each context.
 * - One backing object per-engine inside each context.
 *
 * The global default context starts its life with these new objects fully
 * allocated and populated. The local default context for each opened fd is
 * more complex, because we don't know at creation time which engine is going
 * to use them. To handle this, we have implemented a deferred creation of LR
 * contexts:
 *
 * The local context starts its life as a hollow or blank holder, that only
 * gets populated for a given engine once we receive an execbuffer. If later
 * on we receive another execbuffer ioctl for the same context but a different
 * engine, we allocate/populate a new ringbuffer and context backing object and
 * so on.
 *
 * Finally, regarding local contexts created using the ioctl call: as they are
 * only allowed with the render ring, we can allocate & populate them right
 * away (no need to defer anything, at least for now).
 *
 * Execlists implementation:
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 * Execlists are the new method by which, on gen8+ hardware, workloads are
 * submitted for execution (as opposed to the legacy, ringbuffer-based, method).
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 * This method works as follows:
 *
 * When a request is committed, its commands (the BB start and any leading or
 * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer
 * for the appropriate context. The tail pointer in the hardware context is not
 * updated at this time, but instead, kept by the driver in the ringbuffer
 * structure. A structure representing this request is added to a request queue
 * for the appropriate engine: this structure contains a copy of the context's
 * tail after the request was written to the ring buffer and a pointer to the
 * context itself.
 *
 * If the engine's request queue was empty before the request was added, the
 * queue is processed immediately. Otherwise the queue will be processed during
 * a context switch interrupt. In any case, elements on the queue will get sent
 * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a
 * globally unique 20-bits submission ID.
 *
 * When execution of a request completes, the GPU updates the context status
 * buffer with a context complete event and generates a context switch interrupt.
 * During the interrupt handling, the driver examines the events in the buffer:
 * for each context complete event, if the announced ID matches that on the head
 * of the request queue, then that request is retired and removed from the queue.
 *
 * After processing, if any requests were retired and the queue is not empty
 * then a new execution list can be submitted. The two requests at the front of
 * the queue are next to be submitted but since a context may not occur twice in
 * an execution list, if subsequent requests have the same ID as the first then
 * the two requests must be combined. This is done simply by discarding requests
 * at the head of the queue until either only one requests is left (in which case
 * we use a NULL second context) or the first two requests have unique IDs.
 *
 * By always executing the first two requests in the queue the driver ensures
 * that the GPU is kept as busy as possible. In the case where a single context
 * completes but a second context is still executing, the request for this second
 * context will be at the head of the queue when we remove the first one. This
 * request will then be resubmitted along with a new request for a different context,
 * which will cause the hardware to continue executing the second request and queue
 * the new request (the GPU detects the condition of a context getting preempted
 * with the same context and optimizes the context switch flow by not doing
 * preemption, but just sampling the new tail pointer).
 *
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 */
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#include <linux/interrupt.h>
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#include <drm/drmP.h>
#include <drm/i915_drm.h>
#include "i915_drv.h"
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#include "intel_mocs.h"
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#define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE)
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#define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE)
#define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE)

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#define RING_EXECLIST_QFULL		(1 << 0x2)
#define RING_EXECLIST1_VALID		(1 << 0x3)
#define RING_EXECLIST0_VALID		(1 << 0x4)
#define RING_EXECLIST_ACTIVE_STATUS	(3 << 0xE)
#define RING_EXECLIST1_ACTIVE		(1 << 0x11)
#define RING_EXECLIST0_ACTIVE		(1 << 0x12)

#define GEN8_CTX_STATUS_IDLE_ACTIVE	(1 << 0)
#define GEN8_CTX_STATUS_PREEMPTED	(1 << 1)
#define GEN8_CTX_STATUS_ELEMENT_SWITCH	(1 << 2)
#define GEN8_CTX_STATUS_ACTIVE_IDLE	(1 << 3)
#define GEN8_CTX_STATUS_COMPLETE	(1 << 4)
#define GEN8_CTX_STATUS_LITE_RESTORE	(1 << 15)
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#define GEN8_CTX_STATUS_COMPLETED_MASK \
	 (GEN8_CTX_STATUS_ACTIVE_IDLE | \
	  GEN8_CTX_STATUS_PREEMPTED | \
	  GEN8_CTX_STATUS_ELEMENT_SWITCH)

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#define CTX_LRI_HEADER_0		0x01
#define CTX_CONTEXT_CONTROL		0x02
#define CTX_RING_HEAD			0x04
#define CTX_RING_TAIL			0x06
#define CTX_RING_BUFFER_START		0x08
#define CTX_RING_BUFFER_CONTROL		0x0a
#define CTX_BB_HEAD_U			0x0c
#define CTX_BB_HEAD_L			0x0e
#define CTX_BB_STATE			0x10
#define CTX_SECOND_BB_HEAD_U		0x12
#define CTX_SECOND_BB_HEAD_L		0x14
#define CTX_SECOND_BB_STATE		0x16
#define CTX_BB_PER_CTX_PTR		0x18
#define CTX_RCS_INDIRECT_CTX		0x1a
#define CTX_RCS_INDIRECT_CTX_OFFSET	0x1c
#define CTX_LRI_HEADER_1		0x21
#define CTX_CTX_TIMESTAMP		0x22
#define CTX_PDP3_UDW			0x24
#define CTX_PDP3_LDW			0x26
#define CTX_PDP2_UDW			0x28
#define CTX_PDP2_LDW			0x2a
#define CTX_PDP1_UDW			0x2c
#define CTX_PDP1_LDW			0x2e
#define CTX_PDP0_UDW			0x30
#define CTX_PDP0_LDW			0x32
#define CTX_LRI_HEADER_2		0x41
#define CTX_R_PWR_CLK_STATE		0x42
#define CTX_GPGPU_CSR_BASE_ADDRESS	0x44

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#define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \
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	(reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \
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	(reg_state)[(pos)+1] = (val); \
} while (0)

#define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do {		\
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	const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n));	\
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	reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \
	reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \
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} while (0)
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#define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \
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	reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \
	reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \
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} while (0)
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#define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x17
#define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT	0x26
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/* Typical size of the average request (2 pipecontrols and a MI_BB) */
#define EXECLISTS_REQUEST_SIZE 64 /* bytes */

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#define WA_TAIL_DWORDS 2

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static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
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					    struct intel_engine_cs *engine);
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static void execlists_init_reg_state(u32 *reg_state,
				     struct i915_gem_context *ctx,
				     struct intel_engine_cs *engine,
				     struct intel_ring *ring);
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/**
 * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
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 * @dev_priv: i915 device private
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 * @enable_execlists: value of i915.enable_execlists module parameter.
 *
 * Only certain platforms support Execlists (the prerequisites being
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 * support for Logical Ring Contexts and Aliasing PPGTT or better).
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 *
 * Return: 1 if Execlists is supported and has to be enabled.
 */
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int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists)
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{
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	/* On platforms with execlist available, vGPU will only
	 * support execlist mode, no ring buffer mode.
	 */
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	if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv))
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		return 1;

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	if (INTEL_GEN(dev_priv) >= 9)
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		return 1;

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	if (enable_execlists == 0)
		return 0;

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	if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) &&
	    USES_PPGTT(dev_priv) &&
	    i915.use_mmio_flip >= 0)
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		return 1;

	return 0;
}
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/**
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 * intel_lr_context_descriptor_update() - calculate & cache the descriptor
 * 					  descriptor for a pinned context
 * @ctx: Context to work on
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 * @engine: Engine the descriptor will be used with
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 *
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 * The context descriptor encodes various attributes of a context,
 * including its GTT address and some flags. Because it's fairly
 * expensive to calculate, we'll just do it once and cache the result,
 * which remains valid until the context is unpinned.
 *
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 * This is what a descriptor looks like, from LSB to MSB::
 *
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 *      bits  0-11:    flags, GEN8_CTX_* (cached in ctx->desc_template)
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 *      bits 12-31:    LRCA, GTT address of (the HWSP of) this context
 *      bits 32-52:    ctx ID, a globally unique tag
 *      bits 53-54:    mbz, reserved for use by hardware
 *      bits 55-63:    group ID, currently unused and set to 0
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 */
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static void
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intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
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				   struct intel_engine_cs *engine)
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{
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	struct intel_context *ce = &ctx->engine[engine->id];
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	u64 desc;
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	BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH));
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	desc = ctx->desc_template;				/* bits  0-11 */
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	desc |= i915_ggtt_offset(ce->state) + LRC_PPHWSP_PN * PAGE_SIZE;
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								/* bits 12-31 */
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	desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT;		/* bits 32-52 */
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	ce->lrc_desc = desc;
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}

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uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx,
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				     struct intel_engine_cs *engine)
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{
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	return ctx->engine[engine->id].lrc_desc;
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}
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static inline void
execlists_context_status_change(struct drm_i915_gem_request *rq,
				unsigned long status)
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{
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	/*
	 * Only used when GVT-g is enabled now. When GVT-g is disabled,
	 * The compiler should eliminate this function as dead-code.
	 */
	if (!IS_ENABLED(CONFIG_DRM_I915_GVT))
		return;
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	atomic_notifier_call_chain(&rq->ctx->status_notifier, status, rq);
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}

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static void
execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state)
{
	ASSIGN_CTX_PDP(ppgtt, reg_state, 3);
	ASSIGN_CTX_PDP(ppgtt, reg_state, 2);
	ASSIGN_CTX_PDP(ppgtt, reg_state, 1);
	ASSIGN_CTX_PDP(ppgtt, reg_state, 0);
}

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static u64 execlists_update_context(struct drm_i915_gem_request *rq)
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{
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	struct intel_context *ce = &rq->ctx->engine[rq->engine->id];
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	struct i915_hw_ppgtt *ppgtt =
		rq->ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
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	u32 *reg_state = ce->lrc_reg_state;
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	reg_state[CTX_RING_TAIL+1] = rq->tail;
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	/* True 32b PPGTT with dynamic page allocation: update PDP
	 * registers and point the unallocated PDPs to scratch page.
	 * PML4 is allocated during ppgtt init, so this is not needed
	 * in 48-bit mode.
	 */
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	if (ppgtt && !i915_vm_is_48bit(&ppgtt->base))
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		execlists_update_context_pdps(ppgtt, reg_state);
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	return ce->lrc_desc;
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}

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static void execlists_submit_ports(struct intel_engine_cs *engine)
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{
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	struct drm_i915_private *dev_priv = engine->i915;
	struct execlist_port *port = engine->execlist_port;
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	u32 __iomem *elsp =
		dev_priv->regs + i915_mmio_reg_offset(RING_ELSP(engine));
	u64 desc[2];

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	GEM_BUG_ON(port[0].count > 1);
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	if (!port[0].count)
		execlists_context_status_change(port[0].request,
						INTEL_CONTEXT_SCHEDULE_IN);
	desc[0] = execlists_update_context(port[0].request);
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	GEM_DEBUG_EXEC(port[0].context_id = upper_32_bits(desc[0]));
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	port[0].count++;
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	if (port[1].request) {
		GEM_BUG_ON(port[1].count);
		execlists_context_status_change(port[1].request,
						INTEL_CONTEXT_SCHEDULE_IN);
		desc[1] = execlists_update_context(port[1].request);
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		GEM_DEBUG_EXEC(port[1].context_id = upper_32_bits(desc[1]));
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		port[1].count = 1;
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	} else {
		desc[1] = 0;
	}
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	GEM_BUG_ON(desc[0] == desc[1]);
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	/* You must always write both descriptors in the order below. */
	writel(upper_32_bits(desc[1]), elsp);
	writel(lower_32_bits(desc[1]), elsp);

	writel(upper_32_bits(desc[0]), elsp);
	/* The context is automatically loaded after the following */
	writel(lower_32_bits(desc[0]), elsp);
}

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static bool ctx_single_port_submission(const struct i915_gem_context *ctx)
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{
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	return (IS_ENABLED(CONFIG_DRM_I915_GVT) &&
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		i915_gem_context_force_single_submission(ctx));
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}
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static bool can_merge_ctx(const struct i915_gem_context *prev,
			  const struct i915_gem_context *next)
{
	if (prev != next)
		return false;
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	if (ctx_single_port_submission(prev))
		return false;
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	return true;
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}

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static void execlists_dequeue(struct intel_engine_cs *engine)
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{
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	struct drm_i915_gem_request *last;
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	struct execlist_port *port = engine->execlist_port;
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	unsigned long flags;
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	struct rb_node *rb;
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	bool submit = false;

	last = port->request;
	if (last)
		/* WaIdleLiteRestore:bdw,skl
		 * Apply the wa NOOPs to prevent ring:HEAD == req:TAIL
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		 * as we resubmit the request. See gen8_emit_breadcrumb()
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		 * for where we prepare the padding after the end of the
		 * request.
		 */
		last->tail = last->wa_tail;
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	GEM_BUG_ON(port[1].request);
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	/* Hardware submission is through 2 ports. Conceptually each port
	 * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is
	 * static for a context, and unique to each, so we only execute
	 * requests belonging to a single context from each ring. RING_HEAD
	 * is maintained by the CS in the context image, it marks the place
	 * where it got up to last time, and through RING_TAIL we tell the CS
	 * where we want to execute up to this time.
	 *
	 * In this list the requests are in order of execution. Consecutive
	 * requests from the same context are adjacent in the ringbuffer. We
	 * can combine these requests into a single RING_TAIL update:
	 *
	 *              RING_HEAD...req1...req2
	 *                                    ^- RING_TAIL
	 * since to execute req2 the CS must first execute req1.
	 *
	 * Our goal then is to point each port to the end of a consecutive
	 * sequence of requests as being the most optimal (fewest wake ups
	 * and context switches) submission.
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	 */
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	spin_lock_irqsave(&engine->timeline->lock, flags);
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	rb = engine->execlist_first;
	while (rb) {
		struct drm_i915_gem_request *cursor =
			rb_entry(rb, typeof(*cursor), priotree.node);

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		/* Can we combine this request with the current port? It has to
		 * be the same context/ringbuffer and not have any exceptions
		 * (e.g. GVT saying never to combine contexts).
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		 *
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		 * If we can combine the requests, we can execute both by
		 * updating the RING_TAIL to point to the end of the second
		 * request, and so we never need to tell the hardware about
		 * the first.
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		 */
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		if (last && !can_merge_ctx(cursor->ctx, last->ctx)) {
			/* If we are on the second port and cannot combine
			 * this request with the last, then we are done.
			 */
			if (port != engine->execlist_port)
				break;

			/* If GVT overrides us we only ever submit port[0],
			 * leaving port[1] empty. Note that we also have
			 * to be careful that we don't queue the same
			 * context (even though a different request) to
			 * the second port.
			 */
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			if (ctx_single_port_submission(last->ctx) ||
			    ctx_single_port_submission(cursor->ctx))
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				break;

			GEM_BUG_ON(last->ctx == cursor->ctx);

			i915_gem_request_assign(&port->request, last);
			port++;
		}
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		rb = rb_next(rb);
		rb_erase(&cursor->priotree.node, &engine->execlist_queue);
		RB_CLEAR_NODE(&cursor->priotree.node);
		cursor->priotree.priority = INT_MAX;

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		__i915_gem_request_submit(cursor);
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		last = cursor;
		submit = true;
	}
	if (submit) {
		i915_gem_request_assign(&port->request, last);
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		engine->execlist_first = rb;
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	}
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	spin_unlock_irqrestore(&engine->timeline->lock, flags);
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	if (submit)
		execlists_submit_ports(engine);
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}

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static bool execlists_elsp_idle(struct intel_engine_cs *engine)
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{
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	return !engine->execlist_port[0].request;
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}

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/**
 * intel_execlists_idle() - Determine if all engine submission ports are idle
 * @dev_priv: i915 device private
 *
 * Return true if there are no requests pending on any of the submission ports
 * of any engines.
 */
bool intel_execlists_idle(struct drm_i915_private *dev_priv)
{
	struct intel_engine_cs *engine;
	enum intel_engine_id id;

	if (!i915.enable_execlists)
		return true;

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	for_each_engine(engine, dev_priv, id) {
		/* Interrupt/tasklet pending? */
		if (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted))
			return false;

		/* Both ports drained, no more ELSP submission? */
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		if (!execlists_elsp_idle(engine))
			return false;
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	}
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	return true;
}

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static bool execlists_elsp_ready(const struct intel_engine_cs *engine)
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{
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	const struct execlist_port *port = engine->execlist_port;
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	return port[0].count + port[1].count < 2;
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}

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/*
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 * Check the unread Context Status Buffers and manage the submission of new
 * contexts to the ELSP accordingly.
 */
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static void intel_lrc_irq_handler(unsigned long data)
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{
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	struct intel_engine_cs *engine = (struct intel_engine_cs *)data;
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	struct execlist_port *port = engine->execlist_port;
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	struct drm_i915_private *dev_priv = engine->i915;
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	intel_uncore_forcewake_get(dev_priv, engine->fw_domains);
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	while (test_and_clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) {
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		u32 __iomem *csb_mmio =
			dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine));
		u32 __iomem *buf =
			dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0));
		unsigned int csb, head, tail;

		csb = readl(csb_mmio);
		head = GEN8_CSB_READ_PTR(csb);
		tail = GEN8_CSB_WRITE_PTR(csb);
556 557 558
		if (head == tail)
			break;

559 560
		if (tail < head)
			tail += GEN8_CSB_ENTRIES;
561
		do {
562 563 564
			unsigned int idx = ++head % GEN8_CSB_ENTRIES;
			unsigned int status = readl(buf + 2 * idx);

565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581
			/* We are flying near dragons again.
			 *
			 * We hold a reference to the request in execlist_port[]
			 * but no more than that. We are operating in softirq
			 * context and so cannot hold any mutex or sleep. That
			 * prevents us stopping the requests we are processing
			 * in port[] from being retired simultaneously (the
			 * breadcrumb will be complete before we see the
			 * context-switch). As we only hold the reference to the
			 * request, any pointer chasing underneath the request
			 * is subject to a potential use-after-free. Thus we
			 * store all of the bookkeeping within port[] as
			 * required, and avoid using unguarded pointers beneath
			 * request itself. The same applies to the atomic
			 * status notifier.
			 */

582 583 584
			if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK))
				continue;

585
			/* Check the context/desc id for this event matches */
586 587
			GEM_DEBUG_BUG_ON(readl(buf + 2 * idx + 1) !=
					 port[0].context_id);
588

589 590 591 592 593 594 595 596 597 598
			GEM_BUG_ON(port[0].count == 0);
			if (--port[0].count == 0) {
				GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED);
				execlists_context_status_change(port[0].request,
								INTEL_CONTEXT_SCHEDULE_OUT);

				i915_gem_request_put(port[0].request);
				port[0] = port[1];
				memset(&port[1], 0, sizeof(port[1]));
			}
599

600 601
			GEM_BUG_ON(port[0].count == 0 &&
				   !(status & GEN8_CTX_STATUS_ACTIVE_IDLE));
602
		} while (head < tail);
603

604 605 606
		writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK,
				     GEN8_CSB_WRITE_PTR(csb) << 8),
		       csb_mmio);
607 608
	}

609 610
	if (execlists_elsp_ready(engine))
		execlists_dequeue(engine);
611

612
	intel_uncore_forcewake_put(dev_priv, engine->fw_domains);
613 614
}

615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640
static bool insert_request(struct i915_priotree *pt, struct rb_root *root)
{
	struct rb_node **p, *rb;
	bool first = true;

	/* most positive priority is scheduled first, equal priorities fifo */
	rb = NULL;
	p = &root->rb_node;
	while (*p) {
		struct i915_priotree *pos;

		rb = *p;
		pos = rb_entry(rb, typeof(*pos), node);
		if (pt->priority > pos->priority) {
			p = &rb->rb_left;
		} else {
			p = &rb->rb_right;
			first = false;
		}
	}
	rb_link_node(&pt->node, rb, p);
	rb_insert_color(&pt->node, root);

	return first;
}

641
static void execlists_submit_request(struct drm_i915_gem_request *request)
642
{
643
	struct intel_engine_cs *engine = request->engine;
644
	unsigned long flags;
645

646 647
	/* Will be called from irq-context when using foreign fences. */
	spin_lock_irqsave(&engine->timeline->lock, flags);
648

649
	if (insert_request(&request->priotree, &engine->execlist_queue)) {
650
		engine->execlist_first = &request->priotree.node;
651
		if (execlists_elsp_ready(engine))
652 653
			tasklet_hi_schedule(&engine->irq_tasklet);
	}
654

655
	spin_unlock_irqrestore(&engine->timeline->lock, flags);
656 657
}

658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684
static struct intel_engine_cs *
pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked)
{
	struct intel_engine_cs *engine;

	engine = container_of(pt,
			      struct drm_i915_gem_request,
			      priotree)->engine;
	if (engine != locked) {
		if (locked)
			spin_unlock_irq(&locked->timeline->lock);
		spin_lock_irq(&engine->timeline->lock);
	}

	return engine;
}

static void execlists_schedule(struct drm_i915_gem_request *request, int prio)
{
	struct intel_engine_cs *engine = NULL;
	struct i915_dependency *dep, *p;
	struct i915_dependency stack;
	LIST_HEAD(dfs);

	if (prio <= READ_ONCE(request->priotree.priority))
		return;

685 686
	/* Need BKL in order to use the temporary link inside i915_dependency */
	lockdep_assert_held(&request->i915->drm.struct_mutex);
687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714

	stack.signaler = &request->priotree;
	list_add(&stack.dfs_link, &dfs);

	/* Recursively bump all dependent priorities to match the new request.
	 *
	 * A naive approach would be to use recursion:
	 * static void update_priorities(struct i915_priotree *pt, prio) {
	 *	list_for_each_entry(dep, &pt->signalers_list, signal_link)
	 *		update_priorities(dep->signal, prio)
	 *	insert_request(pt);
	 * }
	 * but that may have unlimited recursion depth and so runs a very
	 * real risk of overunning the kernel stack. Instead, we build
	 * a flat list of all dependencies starting with the current request.
	 * As we walk the list of dependencies, we add all of its dependencies
	 * to the end of the list (this may include an already visited
	 * request) and continue to walk onwards onto the new dependencies. The
	 * end result is a topological list of requests in reverse order, the
	 * last element in the list is the request we must execute first.
	 */
	list_for_each_entry_safe(dep, p, &dfs, dfs_link) {
		struct i915_priotree *pt = dep->signaler;

		list_for_each_entry(p, &pt->signalers_list, signal_link)
			if (prio > READ_ONCE(p->signaler->priority))
				list_move_tail(&p->dfs_link, &dfs);

715
		list_safe_reset_next(dep, p, dfs_link);
716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755
		if (!RB_EMPTY_NODE(&pt->node))
			continue;

		engine = pt_lock_engine(pt, engine);

		/* If it is not already in the rbtree, we can update the
		 * priority inplace and skip over it (and its dependencies)
		 * if it is referenced *again* as we descend the dfs.
		 */
		if (prio > pt->priority && RB_EMPTY_NODE(&pt->node)) {
			pt->priority = prio;
			list_del_init(&dep->dfs_link);
		}
	}

	/* Fifo and depth-first replacement ensure our deps execute before us */
	list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) {
		struct i915_priotree *pt = dep->signaler;

		INIT_LIST_HEAD(&dep->dfs_link);

		engine = pt_lock_engine(pt, engine);

		if (prio <= pt->priority)
			continue;

		GEM_BUG_ON(RB_EMPTY_NODE(&pt->node));

		pt->priority = prio;
		rb_erase(&pt->node, &engine->execlist_queue);
		if (insert_request(pt, &engine->execlist_queue))
			engine->execlist_first = &pt->node;
	}

	if (engine)
		spin_unlock_irq(&engine->timeline->lock);

	/* XXX Do we need to preempt to make room for us and our deps? */
}

756 757
static int execlists_context_pin(struct intel_engine_cs *engine,
				 struct i915_gem_context *ctx)
758
{
759
	struct intel_context *ce = &ctx->engine[engine->id];
760
	unsigned int flags;
761
	void *vaddr;
762
	int ret;
763

764
	lockdep_assert_held(&ctx->i915->drm.struct_mutex);
765

766
	if (ce->pin_count++)
767 768
		return 0;

769 770 771 772 773
	if (!ce->state) {
		ret = execlists_context_deferred_alloc(ctx, engine);
		if (ret)
			goto err;
	}
774
	GEM_BUG_ON(!ce->state);
775

776
	flags = PIN_GLOBAL | PIN_HIGH;
777 778
	if (ctx->ggtt_offset_bias)
		flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias;
779 780

	ret = i915_vma_pin(ce->state, 0, GEN8_LR_CONTEXT_ALIGN, flags);
781
	if (ret)
782
		goto err;
783

784
	vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB);
785 786
	if (IS_ERR(vaddr)) {
		ret = PTR_ERR(vaddr);
787
		goto unpin_vma;
788 789
	}

790
	ret = intel_ring_pin(ce->ring, ctx->ggtt_offset_bias);
791
	if (ret)
792
		goto unpin_map;
793

794
	intel_lr_context_descriptor_update(ctx, engine);
795

796 797
	ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
	ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
798
		i915_ggtt_offset(ce->ring->vma);
799

C
Chris Wilson 已提交
800
	ce->state->obj->mm.dirty = true;
801

802
	i915_gem_context_get(ctx);
803
	return 0;
804

805
unpin_map:
806 807 808
	i915_gem_object_unpin_map(ce->state->obj);
unpin_vma:
	__i915_vma_unpin(ce->state);
809
err:
810
	ce->pin_count = 0;
811 812 813
	return ret;
}

814 815
static void execlists_context_unpin(struct intel_engine_cs *engine,
				    struct i915_gem_context *ctx)
816
{
817
	struct intel_context *ce = &ctx->engine[engine->id];
818

819
	lockdep_assert_held(&ctx->i915->drm.struct_mutex);
820
	GEM_BUG_ON(ce->pin_count == 0);
821

822
	if (--ce->pin_count)
823
		return;
824

825
	intel_ring_unpin(ce->ring);
826

827 828
	i915_gem_object_unpin_map(ce->state->obj);
	i915_vma_unpin(ce->state);
829

830
	i915_gem_context_put(ctx);
831 832
}

833
static int execlists_request_alloc(struct drm_i915_gem_request *request)
834 835 836
{
	struct intel_engine_cs *engine = request->engine;
	struct intel_context *ce = &request->ctx->engine[engine->id];
837
	u32 *cs;
838 839
	int ret;

840 841
	GEM_BUG_ON(!ce->pin_count);

842 843 844 845 846 847
	/* Flush enough space to reduce the likelihood of waiting after
	 * we start building the request - in which case we will just
	 * have to repeat work.
	 */
	request->reserved_space += EXECLISTS_REQUEST_SIZE;

848
	GEM_BUG_ON(!ce->ring);
849 850 851 852 853 854 855 856 857 858
	request->ring = ce->ring;

	if (i915.enable_guc_submission) {
		/*
		 * Check that the GuC has space for the request before
		 * going any further, as the i915_add_request() call
		 * later on mustn't fail ...
		 */
		ret = i915_guc_wq_reserve(request);
		if (ret)
859
			goto err;
860 861
	}

862 863 864
	cs = intel_ring_begin(request, 0);
	if (IS_ERR(cs)) {
		ret = PTR_ERR(cs);
865
		goto err_unreserve;
866
	}
867 868 869 870 871 872 873 874 875 876 877 878 879 880 881 882 883 884 885 886 887 888

	if (!ce->initialised) {
		ret = engine->init_context(request);
		if (ret)
			goto err_unreserve;

		ce->initialised = true;
	}

	/* Note that after this point, we have committed to using
	 * this request as it is being used to both track the
	 * state of engine initialisation and liveness of the
	 * golden renderstate above. Think twice before you try
	 * to cancel/unwind this request now.
	 */

	request->reserved_space -= EXECLISTS_REQUEST_SIZE;
	return 0;

err_unreserve:
	if (i915.enable_guc_submission)
		i915_guc_wq_unreserve(request);
889
err:
890 891 892
	return ret;
}

893
static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
894
{
895
	struct i915_workarounds *w = &req->i915->workarounds;
896 897
	u32 *cs;
	int ret, i;
898

899
	if (w->count == 0)
900 901
		return 0;

902
	ret = req->engine->emit_flush(req, EMIT_BARRIER);
903 904 905
	if (ret)
		return ret;

906 907 908
	cs = intel_ring_begin(req, w->count * 2 + 2);
	if (IS_ERR(cs))
		return PTR_ERR(cs);
909

910
	*cs++ = MI_LOAD_REGISTER_IMM(w->count);
911
	for (i = 0; i < w->count; i++) {
912 913
		*cs++ = i915_mmio_reg_offset(w->reg[i].addr);
		*cs++ = w->reg[i].value;
914
	}
915
	*cs++ = MI_NOOP;
916

917
	intel_ring_advance(req, cs);
918

919
	ret = req->engine->emit_flush(req, EMIT_BARRIER);
920 921 922 923 924 925
	if (ret)
		return ret;

	return 0;
}

926
#define wa_ctx_emit(batch, index, cmd)					\
927
	do {								\
928 929
		int __index = (index)++;				\
		if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \
930 931
			return -ENOSPC;					\
		}							\
932
		batch[__index] = (cmd);					\
933 934
	} while (0)

V
Ville Syrjälä 已提交
935
#define wa_ctx_emit_reg(batch, index, reg) \
936
	wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg))
937 938 939 940 941 942 943 944 945 946 947 948 949 950 951 952 953

/*
 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
 * but there is a slight complication as this is applied in WA batch where the
 * values are only initialized once so we cannot take register value at the
 * beginning and reuse it further; hence we save its value to memory, upload a
 * constant value with bit21 set and then we restore it back with the saved value.
 * To simplify the WA, a constant value is formed by using the default value
 * of this register. This shouldn't be a problem because we are only modifying
 * it for a short period and this batch in non-premptible. We can ofcourse
 * use additional instructions that read the actual value of the register
 * at that time and set our bit of interest but it makes the WA complicated.
 *
 * This WA is also required for Gen9 so extracting as a function avoids
 * code duplication.
 */
954
static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
955
						uint32_t *batch,
956 957 958 959
						uint32_t index)
{
	uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);

960
	wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 |
961
				   MI_SRM_LRM_GLOBAL_GTT));
V
Ville Syrjälä 已提交
962
	wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
963
	wa_ctx_emit(batch, index, i915_ggtt_offset(engine->scratch) + 256);
964 965 966
	wa_ctx_emit(batch, index, 0);

	wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
V
Ville Syrjälä 已提交
967
	wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
968 969 970 971 972 973 974 975 976 977
	wa_ctx_emit(batch, index, l3sqc4_flush);

	wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
	wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL |
				   PIPE_CONTROL_DC_FLUSH_ENABLE));
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);

978
	wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 |
979
				   MI_SRM_LRM_GLOBAL_GTT));
V
Ville Syrjälä 已提交
980
	wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4);
981
	wa_ctx_emit(batch, index, i915_ggtt_offset(engine->scratch) + 256);
982
	wa_ctx_emit(batch, index, 0);
983 984 985 986

	return index;
}

987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003 1004 1005
static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx,
				    uint32_t offset,
				    uint32_t start_alignment)
{
	return wa_ctx->offset = ALIGN(offset, start_alignment);
}

static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
			     uint32_t offset,
			     uint32_t size_alignment)
{
	wa_ctx->size = offset - wa_ctx->offset;

	WARN(wa_ctx->size % size_alignment,
	     "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n",
	     wa_ctx->size, size_alignment);
	return 0;
}

1006 1007 1008 1009 1010 1011
/*
 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
 * initialized at the beginning and shared across all contexts but this field
 * helps us to have multiple batches at different offsets and select them based
 * on a criteria. At the moment this batch always start at the beginning of the page
 * and at this point we don't have multiple wa_ctx batch buffers.
1012
 *
1013 1014
 * The number of WA applied are not known at the beginning; we use this field
 * to return the no of DWORDS written.
1015
 *
1016 1017 1018 1019
 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
 * so it adds NOOPs as padding to make it cacheline aligned.
 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
 * makes a complete batch buffer.
1020
 */
1021
static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine,
1022
				    struct i915_wa_ctx_bb *wa_ctx,
1023
				    uint32_t *batch,
1024 1025
				    uint32_t *offset)
{
1026
	uint32_t scratch_addr;
1027 1028
	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);

1029
	/* WaDisableCtxRestoreArbitration:bdw,chv */
1030
	wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE);
1031

1032
	/* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1033
	if (IS_BROADWELL(engine->i915)) {
1034
		int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index);
1035 1036 1037
		if (rc < 0)
			return rc;
		index = rc;
1038 1039
	}

1040 1041
	/* WaClearSlmSpaceAtContextSwitch:bdw,chv */
	/* Actual scratch location is at 128 bytes offset */
1042
	scratch_addr = i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
1043

1044 1045 1046 1047 1048 1049 1050 1051 1052
	wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
	wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
				   PIPE_CONTROL_GLOBAL_GTT_IVB |
				   PIPE_CONTROL_CS_STALL |
				   PIPE_CONTROL_QW_WRITE));
	wa_ctx_emit(batch, index, scratch_addr);
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);
	wa_ctx_emit(batch, index, 0);
1053

1054 1055
	/* Pad to end of cacheline */
	while (index % CACHELINE_DWORDS)
1056
		wa_ctx_emit(batch, index, MI_NOOP);
1057 1058 1059 1060 1061 1062 1063 1064 1065 1066

	/*
	 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
	 * execution depends on the length specified in terms of cache lines
	 * in the register CTX_RCS_INDIRECT_CTX
	 */

	return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
}

1067 1068 1069
/*
 *  This batch is started immediately after indirect_ctx batch. Since we ensure
 *  that indirect_ctx ends on a cacheline this batch is aligned automatically.
1070
 *
1071
 *  The number of DWORDS written are returned using this field.
1072 1073 1074 1075
 *
 *  This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
 *  to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
 */
1076
static int gen8_init_perctx_bb(struct intel_engine_cs *engine,
1077
			       struct i915_wa_ctx_bb *wa_ctx,
1078
			       uint32_t *batch,
1079 1080 1081 1082
			       uint32_t *offset)
{
	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);

1083
	/* WaDisableCtxRestoreArbitration:bdw,chv */
1084
	wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE);
1085

1086
	wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
1087 1088 1089 1090

	return wa_ctx_end(wa_ctx, *offset = index, 1);
}

1091
static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
1092
				    struct i915_wa_ctx_bb *wa_ctx,
1093
				    uint32_t *batch,
1094 1095
				    uint32_t *offset)
{
1096
	int ret;
D
Dave Airlie 已提交
1097
	struct drm_i915_private *dev_priv = engine->i915;
1098 1099
	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);

1100
	/* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
1101
	ret = gen8_emit_flush_coherentl3_wa(engine, batch, index);
1102 1103 1104 1105
	if (ret < 0)
		return ret;
	index = ret;

1106
	/* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
1107 1108 1109 1110 1111 1112
	wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
	wa_ctx_emit_reg(batch, index, COMMON_SLICE_CHICKEN2);
	wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(
			    GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE));
	wa_ctx_emit(batch, index, MI_NOOP);

1113 1114
	/* WaClearSlmSpaceAtContextSwitch:kbl */
	/* Actual scratch location is at 128 bytes offset */
1115
	if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0)) {
1116
		u32 scratch_addr =
1117
			i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
1118 1119 1120 1121 1122 1123 1124 1125 1126 1127 1128

		wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6));
		wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 |
					   PIPE_CONTROL_GLOBAL_GTT_IVB |
					   PIPE_CONTROL_CS_STALL |
					   PIPE_CONTROL_QW_WRITE));
		wa_ctx_emit(batch, index, scratch_addr);
		wa_ctx_emit(batch, index, 0);
		wa_ctx_emit(batch, index, 0);
		wa_ctx_emit(batch, index, 0);
	}
1129

1130
	/* WaMediaPoolStateCmdInWABB:bxt,glk */
1131 1132 1133 1134 1135 1136 1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152 1153
	if (HAS_POOLED_EU(engine->i915)) {
		/*
		 * EU pool configuration is setup along with golden context
		 * during context initialization. This value depends on
		 * device type (2x6 or 3x6) and needs to be updated based
		 * on which subslice is disabled especially for 2x6
		 * devices, however it is safe to load default
		 * configuration of 3x6 device instead of masking off
		 * corresponding bits because HW ignores bits of a disabled
		 * subslice and drops down to appropriate config. Please
		 * see render_state_setup() in i915_gem_render_state.c for
		 * possible configurations, to avoid duplication they are
		 * not shown here again.
		 */
		u32 eu_pool_config = 0x00777000;
		wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_STATE);
		wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_ENABLE);
		wa_ctx_emit(batch, index, eu_pool_config);
		wa_ctx_emit(batch, index, 0);
		wa_ctx_emit(batch, index, 0);
		wa_ctx_emit(batch, index, 0);
	}

1154 1155 1156 1157 1158 1159 1160
	/* Pad to end of cacheline */
	while (index % CACHELINE_DWORDS)
		wa_ctx_emit(batch, index, MI_NOOP);

	return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
}

1161
static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
1162
			       struct i915_wa_ctx_bb *wa_ctx,
1163
			       uint32_t *batch,
1164 1165 1166 1167 1168 1169 1170 1171 1172
			       uint32_t *offset)
{
	uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);

	wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);

	return wa_ctx_end(wa_ctx, *offset = index, 1);
}

1173
static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size)
1174
{
1175 1176 1177
	struct drm_i915_gem_object *obj;
	struct i915_vma *vma;
	int err;
1178

1179
	obj = i915_gem_object_create(engine->i915, PAGE_ALIGN(size));
1180 1181
	if (IS_ERR(obj))
		return PTR_ERR(obj);
1182

1183
	vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL);
1184 1185 1186
	if (IS_ERR(vma)) {
		err = PTR_ERR(vma);
		goto err;
1187 1188
	}

1189 1190 1191 1192 1193
	err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH);
	if (err)
		goto err;

	engine->wa_ctx.vma = vma;
1194
	return 0;
1195 1196 1197 1198

err:
	i915_gem_object_put(obj);
	return err;
1199 1200
}

1201
static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *engine)
1202
{
1203
	i915_vma_unpin_and_release(&engine->wa_ctx.vma);
1204 1205
}

1206
static int intel_init_workaround_bb(struct intel_engine_cs *engine)
1207
{
1208
	struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1209 1210 1211
	uint32_t *batch;
	uint32_t offset;
	struct page *page;
1212
	int ret;
1213

1214
	WARN_ON(engine->id != RCS);
1215

1216
	/* update this when WA for higher Gen are added */
1217
	if (INTEL_GEN(engine->i915) > 9) {
1218
		DRM_ERROR("WA batch buffer is not initialized for Gen%d\n",
1219
			  INTEL_GEN(engine->i915));
1220
		return 0;
1221
	}
1222

1223
	/* some WA perform writes to scratch page, ensure it is valid */
1224
	if (!engine->scratch) {
1225
		DRM_ERROR("scratch page not allocated for %s\n", engine->name);
1226 1227 1228
		return -EINVAL;
	}

1229
	ret = lrc_setup_wa_ctx_obj(engine, PAGE_SIZE);
1230 1231 1232 1233 1234
	if (ret) {
		DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
		return ret;
	}

1235
	page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0);
1236 1237 1238
	batch = kmap_atomic(page);
	offset = 0;

1239
	if (IS_GEN8(engine->i915)) {
1240
		ret = gen8_init_indirectctx_bb(engine,
1241 1242 1243 1244 1245 1246
					       &wa_ctx->indirect_ctx,
					       batch,
					       &offset);
		if (ret)
			goto out;

1247
		ret = gen8_init_perctx_bb(engine,
1248 1249 1250 1251 1252
					  &wa_ctx->per_ctx,
					  batch,
					  &offset);
		if (ret)
			goto out;
1253
	} else if (IS_GEN9(engine->i915)) {
1254
		ret = gen9_init_indirectctx_bb(engine,
1255 1256 1257 1258 1259 1260
					       &wa_ctx->indirect_ctx,
					       batch,
					       &offset);
		if (ret)
			goto out;

1261
		ret = gen9_init_perctx_bb(engine,
1262 1263 1264 1265 1266
					  &wa_ctx->per_ctx,
					  batch,
					  &offset);
		if (ret)
			goto out;
1267 1268 1269 1270 1271
	}

out:
	kunmap_atomic(batch);
	if (ret)
1272
		lrc_destroy_wa_ctx_obj(engine);
1273 1274 1275 1276

	return ret;
}

1277 1278 1279 1280 1281
static u32 port_seqno(struct execlist_port *port)
{
	return port->request ? port->request->global_seqno : 0;
}

1282
static int gen8_init_common_ring(struct intel_engine_cs *engine)
1283
{
1284
	struct drm_i915_private *dev_priv = engine->i915;
1285 1286 1287 1288 1289
	int ret;

	ret = intel_mocs_init_engine(engine);
	if (ret)
		return ret;
1290

1291
	intel_engine_reset_breadcrumbs(engine);
1292
	intel_engine_init_hangcheck(engine);
1293

1294 1295
	I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
	I915_WRITE(RING_MODE_GEN7(engine),
1296 1297
		   _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
		   _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
1298 1299 1300
	I915_WRITE(RING_HWS_PGA(engine->mmio_base),
		   engine->status_page.ggtt_offset);
	POSTING_READ(RING_HWS_PGA(engine->mmio_base));
1301

1302
	DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name);
1303

1304
	/* After a GPU reset, we may have requests to replay */
1305
	clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
1306
	if (!execlists_elsp_idle(engine)) {
1307 1308 1309 1310
		DRM_DEBUG_DRIVER("Restarting %s from requests [0x%x, 0x%x]\n",
				 engine->name,
				 port_seqno(&engine->execlist_port[0]),
				 port_seqno(&engine->execlist_port[1]));
1311 1312
		engine->execlist_port[0].count = 0;
		engine->execlist_port[1].count = 0;
1313
		execlists_submit_ports(engine);
1314
	}
1315 1316

	return 0;
1317 1318
}

1319
static int gen8_init_render_ring(struct intel_engine_cs *engine)
1320
{
1321
	struct drm_i915_private *dev_priv = engine->i915;
1322 1323
	int ret;

1324
	ret = gen8_init_common_ring(engine);
1325 1326 1327 1328 1329 1330 1331 1332 1333 1334 1335 1336 1337
	if (ret)
		return ret;

	/* We need to disable the AsyncFlip performance optimisations in order
	 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
	 * programmed to '1' on all products.
	 *
	 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv
	 */
	I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));

	I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));

1338
	return init_workarounds_ring(engine);
1339 1340
}

1341
static int gen9_init_render_ring(struct intel_engine_cs *engine)
1342 1343 1344
{
	int ret;

1345
	ret = gen8_init_common_ring(engine);
1346 1347 1348
	if (ret)
		return ret;

1349
	return init_workarounds_ring(engine);
1350 1351
}

1352 1353 1354 1355
static void reset_common_ring(struct intel_engine_cs *engine,
			      struct drm_i915_gem_request *request)
{
	struct execlist_port *port = engine->execlist_port;
1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369
	struct intel_context *ce;

	/* If the request was innocent, we leave the request in the ELSP
	 * and will try to replay it on restarting. The context image may
	 * have been corrupted by the reset, in which case we may have
	 * to service a new GPU hang, but more likely we can continue on
	 * without impact.
	 *
	 * If the request was guilty, we presume the context is corrupt
	 * and have to at least restore the RING register in the context
	 * image back to the expected values to skip over the guilty request.
	 */
	if (!request || request->fence.error != -EIO)
		return;
1370

1371 1372 1373 1374 1375 1376 1377
	/* We want a simple context + ring to execute the breadcrumb update.
	 * We cannot rely on the context being intact across the GPU hang,
	 * so clear it and rebuild just what we need for the breadcrumb.
	 * All pending requests for this context will be zapped, and any
	 * future request will be after userspace has had the opportunity
	 * to recreate its own state.
	 */
1378
	ce = &request->ctx->engine[engine->id];
1379 1380 1381
	execlists_init_reg_state(ce->lrc_reg_state,
				 request->ctx, engine, ce->ring);

1382
	/* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
1383 1384
	ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
		i915_ggtt_offset(ce->ring->vma);
1385
	ce->lrc_reg_state[CTX_RING_HEAD+1] = request->postfix;
1386

1387 1388 1389 1390 1391 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401
	request->ring->head = request->postfix;
	request->ring->last_retired_head = -1;
	intel_ring_update_space(request->ring);

	if (i915.enable_guc_submission)
		return;

	/* Catch up with any missed context-switch interrupts */
	if (request->ctx != port[0].request->ctx) {
		i915_gem_request_put(port[0].request);
		port[0] = port[1];
		memset(&port[1], 0, sizeof(port[1]));
	}

	GEM_BUG_ON(request->ctx != port[0].request->ctx);
1402 1403 1404

	/* Reset WaIdleLiteRestore:bdw,skl as well */
	request->tail = request->wa_tail - WA_TAIL_DWORDS * sizeof(u32);
1405 1406
}

1407 1408 1409
static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
{
	struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt;
1410
	struct intel_engine_cs *engine = req->engine;
1411
	const int num_lri_cmds = GEN8_LEGACY_PDPES * 2;
1412 1413
	u32 *cs;
	int i;
1414

1415 1416 1417
	cs = intel_ring_begin(req, num_lri_cmds * 2 + 2);
	if (IS_ERR(cs))
		return PTR_ERR(cs);
1418

1419
	*cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds);
1420 1421 1422
	for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) {
		const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i);

1423 1424 1425 1426
		*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i));
		*cs++ = upper_32_bits(pd_daddr);
		*cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i));
		*cs++ = lower_32_bits(pd_daddr);
1427 1428
	}

1429 1430
	*cs++ = MI_NOOP;
	intel_ring_advance(req, cs);
1431 1432 1433 1434

	return 0;
}

1435
static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
1436 1437
			      u64 offset, u32 len,
			      unsigned int dispatch_flags)
1438
{
1439
	bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE);
1440
	u32 *cs;
1441 1442
	int ret;

1443 1444 1445 1446
	/* Don't rely in hw updating PDPs, specially in lite-restore.
	 * Ideally, we should set Force PD Restore in ctx descriptor,
	 * but we can't. Force Restore would be a second option, but
	 * it is unsafe in case of lite-restore (because the ctx is
1447 1448
	 * not idle). PML4 is allocated during ppgtt init so this is
	 * not needed in 48-bit.*/
1449
	if (req->ctx->ppgtt &&
1450
	    (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) {
1451
		if (!i915_vm_is_48bit(&req->ctx->ppgtt->base) &&
1452
		    !intel_vgpu_active(req->i915)) {
1453 1454 1455 1456
			ret = intel_logical_ring_emit_pdps(req);
			if (ret)
				return ret;
		}
1457

1458
		req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine);
1459 1460
	}

1461 1462 1463
	cs = intel_ring_begin(req, 4);
	if (IS_ERR(cs))
		return PTR_ERR(cs);
1464 1465

	/* FIXME(BDW): Address space and security selectors. */
1466 1467 1468 1469 1470 1471
	*cs++ = MI_BATCH_BUFFER_START_GEN8 | (ppgtt << 8) | (dispatch_flags &
		I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0);
	*cs++ = lower_32_bits(offset);
	*cs++ = upper_32_bits(offset);
	*cs++ = MI_NOOP;
	intel_ring_advance(req, cs);
1472 1473 1474 1475

	return 0;
}

1476
static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine)
1477
{
1478
	struct drm_i915_private *dev_priv = engine->i915;
1479 1480 1481
	I915_WRITE_IMR(engine,
		       ~(engine->irq_enable_mask | engine->irq_keep_mask));
	POSTING_READ_FW(RING_IMR(engine->mmio_base));
1482 1483
}

1484
static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine)
1485
{
1486
	struct drm_i915_private *dev_priv = engine->i915;
1487
	I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
1488 1489
}

1490
static int gen8_emit_flush(struct drm_i915_gem_request *request, u32 mode)
1491
{
1492
	u32 cmd, *cs;
1493

1494 1495 1496
	cs = intel_ring_begin(request, 4);
	if (IS_ERR(cs))
		return PTR_ERR(cs);
1497 1498 1499

	cmd = MI_FLUSH_DW + 1;

1500 1501 1502 1503 1504 1505 1506
	/* We always require a command barrier so that subsequent
	 * commands, such as breadcrumb interrupts, are strictly ordered
	 * wrt the contents of the write cache being flushed to memory
	 * (and thus being coherent from the CPU).
	 */
	cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;

1507
	if (mode & EMIT_INVALIDATE) {
1508
		cmd |= MI_INVALIDATE_TLB;
1509
		if (request->engine->id == VCS)
1510
			cmd |= MI_INVALIDATE_BSD;
1511 1512
	}

1513 1514 1515 1516 1517
	*cs++ = cmd;
	*cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
	*cs++ = 0; /* upper addr */
	*cs++ = 0; /* value */
	intel_ring_advance(request, cs);
1518 1519 1520 1521

	return 0;
}

1522
static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
1523
				  u32 mode)
1524
{
1525
	struct intel_engine_cs *engine = request->engine;
1526 1527
	u32 scratch_addr =
		i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES;
M
Mika Kuoppala 已提交
1528
	bool vf_flush_wa = false, dc_flush_wa = false;
1529
	u32 *cs, flags = 0;
M
Mika Kuoppala 已提交
1530
	int len;
1531 1532 1533

	flags |= PIPE_CONTROL_CS_STALL;

1534
	if (mode & EMIT_FLUSH) {
1535 1536
		flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
		flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
1537
		flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
1538
		flags |= PIPE_CONTROL_FLUSH_ENABLE;
1539 1540
	}

1541
	if (mode & EMIT_INVALIDATE) {
1542 1543 1544 1545 1546 1547 1548 1549 1550
		flags |= PIPE_CONTROL_TLB_INVALIDATE;
		flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
		flags |= PIPE_CONTROL_QW_WRITE;
		flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;

1551 1552 1553 1554
		/*
		 * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
		 * pipe control.
		 */
1555
		if (IS_GEN9(request->i915))
1556
			vf_flush_wa = true;
M
Mika Kuoppala 已提交
1557 1558 1559 1560

		/* WaForGAMHang:kbl */
		if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0))
			dc_flush_wa = true;
1561
	}
1562

M
Mika Kuoppala 已提交
1563 1564 1565 1566 1567 1568 1569 1570
	len = 6;

	if (vf_flush_wa)
		len += 6;

	if (dc_flush_wa)
		len += 12;

1571 1572 1573
	cs = intel_ring_begin(request, len);
	if (IS_ERR(cs))
		return PTR_ERR(cs);
1574

1575
	if (vf_flush_wa) {
1576 1577 1578 1579 1580 1581
		*cs++ = GFX_OP_PIPE_CONTROL(6);
		*cs++ = 0;
		*cs++ = 0;
		*cs++ = 0;
		*cs++ = 0;
		*cs++ = 0;
1582 1583
	}

M
Mika Kuoppala 已提交
1584
	if (dc_flush_wa) {
1585 1586 1587 1588 1589 1590
		*cs++ = GFX_OP_PIPE_CONTROL(6);
		*cs++ = PIPE_CONTROL_DC_FLUSH_ENABLE;
		*cs++ = 0;
		*cs++ = 0;
		*cs++ = 0;
		*cs++ = 0;
M
Mika Kuoppala 已提交
1591 1592
	}

1593 1594 1595 1596 1597 1598
	*cs++ = GFX_OP_PIPE_CONTROL(6);
	*cs++ = flags;
	*cs++ = scratch_addr;
	*cs++ = 0;
	*cs++ = 0;
	*cs++ = 0;
M
Mika Kuoppala 已提交
1599 1600

	if (dc_flush_wa) {
1601 1602 1603 1604 1605 1606
		*cs++ = GFX_OP_PIPE_CONTROL(6);
		*cs++ = PIPE_CONTROL_CS_STALL;
		*cs++ = 0;
		*cs++ = 0;
		*cs++ = 0;
		*cs++ = 0;
M
Mika Kuoppala 已提交
1607 1608
	}

1609
	intel_ring_advance(request, cs);
1610 1611 1612 1613

	return 0;
}

1614 1615 1616 1617 1618
/*
 * Reserve space for 2 NOOPs at the end of each request to be
 * used as a workaround for not being allowed to do lite
 * restore with HEAD==TAIL (WaIdleLiteRestore).
 */
1619
static void gen8_emit_wa_tail(struct drm_i915_gem_request *request, u32 *cs)
1620
{
1621 1622 1623
	*cs++ = MI_NOOP;
	*cs++ = MI_NOOP;
	request->wa_tail = intel_ring_offset(request, cs);
C
Chris Wilson 已提交
1624
}
1625

1626
static void gen8_emit_breadcrumb(struct drm_i915_gem_request *request, u32 *cs)
C
Chris Wilson 已提交
1627
{
1628 1629
	/* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */
	BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5));
1630

1631 1632 1633 1634 1635 1636 1637
	*cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW;
	*cs++ = intel_hws_seqno_address(request->engine) | MI_FLUSH_DW_USE_GTT;
	*cs++ = 0;
	*cs++ = request->global_seqno;
	*cs++ = MI_USER_INTERRUPT;
	*cs++ = MI_NOOP;
	request->tail = intel_ring_offset(request, cs);
C
Chris Wilson 已提交
1638

1639
	gen8_emit_wa_tail(request, cs);
1640
}
1641

1642 1643
static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS;

C
Chris Wilson 已提交
1644
static void gen8_emit_breadcrumb_render(struct drm_i915_gem_request *request,
1645
					u32 *cs)
1646
{
1647 1648 1649
	/* We're using qword write, seqno should be aligned to 8 bytes. */
	BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1);

1650 1651 1652 1653
	/* w/a for post sync ops following a GPGPU operation we
	 * need a prior CS_STALL, which is emitted by the flush
	 * following the batch.
	 */
1654 1655 1656 1657 1658 1659
	*cs++ = GFX_OP_PIPE_CONTROL(6);
	*cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL |
		PIPE_CONTROL_QW_WRITE;
	*cs++ = intel_hws_seqno_address(request->engine);
	*cs++ = 0;
	*cs++ = request->global_seqno;
1660
	/* We're thrashing one dword of HWS. */
1661 1662 1663 1664
	*cs++ = 0;
	*cs++ = MI_USER_INTERRUPT;
	*cs++ = MI_NOOP;
	request->tail = intel_ring_offset(request, cs);
C
Chris Wilson 已提交
1665

1666
	gen8_emit_wa_tail(request, cs);
1667 1668
}

1669 1670
static const int gen8_emit_breadcrumb_render_sz = 8 + WA_TAIL_DWORDS;

1671
static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
1672 1673 1674
{
	int ret;

1675
	ret = intel_logical_ring_workarounds_emit(req);
1676 1677 1678
	if (ret)
		return ret;

1679 1680 1681 1682 1683 1684 1685 1686
	ret = intel_rcs_context_init_mocs(req);
	/*
	 * Failing to program the MOCS is non-fatal.The system will not
	 * run at peak performance. So generate an error and carry on.
	 */
	if (ret)
		DRM_ERROR("MOCS failed to program: expect performance issues.\n");

1687
	return i915_gem_render_state_emit(req);
1688 1689
}

1690 1691
/**
 * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
1692
 * @engine: Engine Command Streamer.
1693
 */
1694
void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
1695
{
1696
	struct drm_i915_private *dev_priv;
1697

1698 1699 1700 1701 1702 1703 1704
	/*
	 * Tasklet cannot be active at this point due intel_mark_active/idle
	 * so this is just for documentation.
	 */
	if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state)))
		tasklet_kill(&engine->irq_tasklet);

1705
	dev_priv = engine->i915;
1706

1707 1708
	if (engine->buffer) {
		WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
1709
	}
1710

1711 1712
	if (engine->cleanup)
		engine->cleanup(engine);
1713

1714 1715 1716
	if (engine->status_page.vma) {
		i915_gem_object_unpin_map(engine->status_page.vma->obj);
		engine->status_page.vma = NULL;
1717
	}
1718 1719

	intel_engine_cleanup_common(engine);
1720

1721
	lrc_destroy_wa_ctx_obj(engine);
1722
	engine->i915 = NULL;
1723 1724
	dev_priv->engine[engine->id] = NULL;
	kfree(engine);
1725 1726
}

1727 1728 1729
void intel_execlists_enable_submission(struct drm_i915_private *dev_priv)
{
	struct intel_engine_cs *engine;
1730
	enum intel_engine_id id;
1731

1732
	for_each_engine(engine, dev_priv, id) {
1733
		engine->submit_request = execlists_submit_request;
1734 1735
		engine->schedule = execlists_schedule;
	}
1736 1737
}

1738
static void
1739
logical_ring_default_vfuncs(struct intel_engine_cs *engine)
1740 1741
{
	/* Default vfuncs which can be overriden by each engine. */
1742
	engine->init_hw = gen8_init_common_ring;
1743
	engine->reset_hw = reset_common_ring;
1744 1745 1746 1747

	engine->context_pin = execlists_context_pin;
	engine->context_unpin = execlists_context_unpin;

1748 1749
	engine->request_alloc = execlists_request_alloc;

1750
	engine->emit_flush = gen8_emit_flush;
1751
	engine->emit_breadcrumb = gen8_emit_breadcrumb;
1752
	engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz;
1753
	engine->submit_request = execlists_submit_request;
1754
	engine->schedule = execlists_schedule;
1755

1756 1757
	engine->irq_enable = gen8_logical_ring_enable_irq;
	engine->irq_disable = gen8_logical_ring_disable_irq;
1758
	engine->emit_bb_start = gen8_emit_bb_start;
1759 1760
}

1761
static inline void
1762
logical_ring_default_irqs(struct intel_engine_cs *engine)
1763
{
1764
	unsigned shift = engine->irq_shift;
1765 1766
	engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
	engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
1767 1768
}

1769
static int
1770
lrc_setup_hws(struct intel_engine_cs *engine, struct i915_vma *vma)
1771
{
1772
	const int hws_offset = LRC_PPHWSP_PN * PAGE_SIZE;
1773
	void *hws;
1774 1775

	/* The HWSP is part of the default context object in LRC mode. */
1776
	hws = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
1777 1778
	if (IS_ERR(hws))
		return PTR_ERR(hws);
1779 1780

	engine->status_page.page_addr = hws + hws_offset;
1781
	engine->status_page.ggtt_offset = i915_ggtt_offset(vma) + hws_offset;
1782
	engine->status_page.vma = vma;
1783 1784

	return 0;
1785 1786
}

1787 1788 1789 1790 1791 1792
static void
logical_ring_setup(struct intel_engine_cs *engine)
{
	struct drm_i915_private *dev_priv = engine->i915;
	enum forcewake_domains fw_domains;

1793 1794
	intel_engine_setup_common(engine);

1795 1796 1797 1798 1799 1800 1801 1802 1803 1804 1805 1806 1807 1808 1809 1810 1811 1812 1813 1814 1815 1816 1817 1818
	/* Intentionally left blank. */
	engine->buffer = NULL;

	fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
						    RING_ELSP(engine),
						    FW_REG_WRITE);

	fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
						     RING_CONTEXT_STATUS_PTR(engine),
						     FW_REG_READ | FW_REG_WRITE);

	fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
						     RING_CONTEXT_STATUS_BUF_BASE(engine),
						     FW_REG_READ);

	engine->fw_domains = fw_domains;

	tasklet_init(&engine->irq_tasklet,
		     intel_lrc_irq_handler, (unsigned long)engine);

	logical_ring_default_vfuncs(engine);
	logical_ring_default_irqs(engine);
}

1819 1820 1821 1822 1823 1824
static int
logical_ring_init(struct intel_engine_cs *engine)
{
	struct i915_gem_context *dctx = engine->i915->kernel_context;
	int ret;

1825
	ret = intel_engine_init_common(engine);
1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842
	if (ret)
		goto error;

	/* And setup the hardware status page. */
	ret = lrc_setup_hws(engine, dctx->engine[engine->id].state);
	if (ret) {
		DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret);
		goto error;
	}

	return 0;

error:
	intel_logical_ring_cleanup(engine);
	return ret;
}

1843
int logical_render_ring_init(struct intel_engine_cs *engine)
1844 1845 1846 1847
{
	struct drm_i915_private *dev_priv = engine->i915;
	int ret;

1848 1849
	logical_ring_setup(engine);

1850 1851 1852 1853 1854 1855 1856 1857 1858 1859
	if (HAS_L3_DPF(dev_priv))
		engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT;

	/* Override some for render ring. */
	if (INTEL_GEN(dev_priv) >= 9)
		engine->init_hw = gen9_init_render_ring;
	else
		engine->init_hw = gen8_init_render_ring;
	engine->init_context = gen8_init_rcs_context;
	engine->emit_flush = gen8_emit_flush_render;
1860
	engine->emit_breadcrumb = gen8_emit_breadcrumb_render;
1861
	engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_render_sz;
1862

1863
	ret = intel_engine_create_scratch(engine, PAGE_SIZE);
1864 1865 1866 1867 1868 1869 1870 1871 1872 1873 1874 1875 1876 1877
	if (ret)
		return ret;

	ret = intel_init_workaround_bb(engine);
	if (ret) {
		/*
		 * We continue even if we fail to initialize WA batch
		 * because we only expect rare glitches but nothing
		 * critical to prevent us from using GPU
		 */
		DRM_ERROR("WA batch buffer initialization failed: %d\n",
			  ret);
	}

1878
	return logical_ring_init(engine);
1879 1880
}

1881
int logical_xcs_ring_init(struct intel_engine_cs *engine)
1882 1883 1884 1885
{
	logical_ring_setup(engine);

	return logical_ring_init(engine);
1886 1887
}

1888
static u32
1889
make_rpcs(struct drm_i915_private *dev_priv)
1890 1891 1892 1893 1894 1895 1896
{
	u32 rpcs = 0;

	/*
	 * No explicit RPCS request is needed to ensure full
	 * slice/subslice/EU enablement prior to Gen9.
	*/
1897
	if (INTEL_GEN(dev_priv) < 9)
1898 1899 1900 1901 1902 1903 1904 1905
		return 0;

	/*
	 * Starting in Gen9, render power gating can leave
	 * slice/subslice/EU in a partially enabled state. We
	 * must make an explicit request through RPCS for full
	 * enablement.
	*/
1906
	if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) {
1907
		rpcs |= GEN8_RPCS_S_CNT_ENABLE;
1908
		rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) <<
1909 1910 1911 1912
			GEN8_RPCS_S_CNT_SHIFT;
		rpcs |= GEN8_RPCS_ENABLE;
	}

1913
	if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) {
1914
		rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
1915
		rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask) <<
1916 1917 1918 1919
			GEN8_RPCS_SS_CNT_SHIFT;
		rpcs |= GEN8_RPCS_ENABLE;
	}

1920 1921
	if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) {
		rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
1922
			GEN8_RPCS_EU_MIN_SHIFT;
1923
		rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice <<
1924 1925 1926 1927 1928 1929 1930
			GEN8_RPCS_EU_MAX_SHIFT;
		rpcs |= GEN8_RPCS_ENABLE;
	}

	return rpcs;
}

1931
static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
1932 1933 1934
{
	u32 indirect_ctx_offset;

1935
	switch (INTEL_GEN(engine->i915)) {
1936
	default:
1937
		MISSING_CASE(INTEL_GEN(engine->i915));
1938 1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951
		/* fall through */
	case 9:
		indirect_ctx_offset =
			GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
		break;
	case 8:
		indirect_ctx_offset =
			GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
		break;
	}

	return indirect_ctx_offset;
}

1952 1953 1954 1955
static void execlists_init_reg_state(u32 *reg_state,
				     struct i915_gem_context *ctx,
				     struct intel_engine_cs *engine,
				     struct intel_ring *ring)
1956
{
1957 1958
	struct drm_i915_private *dev_priv = engine->i915;
	struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt;
1959 1960 1961 1962 1963 1964

	/* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
	 * commands followed by (reg, value) pairs. The values we are setting here are
	 * only for the first context restore: on a subsequent save, the GPU will
	 * recreate this batchbuffer with new values (including all the missing
	 * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */
1965
	reg_state[CTX_LRI_HEADER_0] =
1966 1967 1968
		MI_LOAD_REGISTER_IMM(engine->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED;
	ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL,
		       RING_CONTEXT_CONTROL(engine),
1969 1970
		       _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH |
					  CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT |
1971
					  (HAS_RESOURCE_STREAMER(dev_priv) ?
1972
					   CTX_CTRL_RS_CTX_ENABLE : 0)));
1973 1974 1975 1976 1977 1978 1979 1980
	ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(engine->mmio_base),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START,
		       RING_START(engine->mmio_base), 0);
	ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL,
		       RING_CTL(engine->mmio_base),
1981
		       RING_CTL_SIZE(ring->size) | RING_VALID);
1982 1983 1984 1985 1986 1987
	ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U,
		       RING_BBADDR_UDW(engine->mmio_base), 0);
	ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L,
		       RING_BBADDR(engine->mmio_base), 0);
	ASSIGN_CTX_REG(reg_state, CTX_BB_STATE,
		       RING_BBSTATE(engine->mmio_base),
1988
		       RING_BB_PPGTT);
1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 2001
	ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U,
		       RING_SBBADDR_UDW(engine->mmio_base), 0);
	ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L,
		       RING_SBBADDR(engine->mmio_base), 0);
	ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE,
		       RING_SBBSTATE(engine->mmio_base), 0);
	if (engine->id == RCS) {
		ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR,
			       RING_BB_PER_CTX_PTR(engine->mmio_base), 0);
		ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX,
			       RING_INDIRECT_CTX(engine->mmio_base), 0);
		ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET,
			       RING_INDIRECT_CTX_OFFSET(engine->mmio_base), 0);
2002
		if (engine->wa_ctx.vma) {
2003
			struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
2004
			u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
2005 2006 2007 2008 2009 2010

			reg_state[CTX_RCS_INDIRECT_CTX+1] =
				(ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) |
				(wa_ctx->indirect_ctx.size / CACHELINE_DWORDS);

			reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] =
2011
				intel_lr_indirect_ctx_offset(engine) << 6;
2012 2013 2014 2015 2016

			reg_state[CTX_BB_PER_CTX_PTR+1] =
				(ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) |
				0x01;
		}
2017
	}
2018
	reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;
2019 2020
	ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP,
		       RING_CTX_TIMESTAMP(engine->mmio_base), 0);
2021
	/* PDP values well be assigned later if needed */
2022 2023 2024 2025 2026 2027 2028 2029 2030 2031 2032 2033 2034 2035 2036 2037
	ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0),
		       0);
	ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0),
		       0);
2038

2039
	if (ppgtt && i915_vm_is_48bit(&ppgtt->base)) {
2040 2041 2042 2043 2044 2045 2046
		/* 64b PPGTT (48bit canonical)
		 * PDP0_DESCRIPTOR contains the base address to PML4 and
		 * other PDP Descriptors are ignored.
		 */
		ASSIGN_CTX_PML4(ppgtt, reg_state);
	}

2047
	if (engine->id == RCS) {
2048
		reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1);
2049
		ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
2050
			       make_rpcs(dev_priv));
2051
	}
2052 2053 2054 2055 2056 2057 2058 2059 2060 2061 2062 2063 2064 2065 2066 2067 2068 2069 2070 2071 2072 2073 2074
}

static int
populate_lr_context(struct i915_gem_context *ctx,
		    struct drm_i915_gem_object *ctx_obj,
		    struct intel_engine_cs *engine,
		    struct intel_ring *ring)
{
	void *vaddr;
	int ret;

	ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
	if (ret) {
		DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
		return ret;
	}

	vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
	if (IS_ERR(vaddr)) {
		ret = PTR_ERR(vaddr);
		DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
		return ret;
	}
C
Chris Wilson 已提交
2075
	ctx_obj->mm.dirty = true;
2076 2077 2078 2079 2080 2081

	/* The second page of the context object contains some fields which must
	 * be set up prior to the first execution. */

	execlists_init_reg_state(vaddr + LRC_STATE_PN * PAGE_SIZE,
				 ctx, engine, ring);
2082

2083
	i915_gem_object_unpin_map(ctx_obj);
2084 2085 2086 2087

	return 0;
}

2088 2089
/**
 * intel_lr_context_size() - return the size of the context for an engine
2090
 * @engine: which engine to find the context size for
2091 2092 2093 2094 2095 2096 2097 2098 2099 2100 2101
 *
 * Each engine may require a different amount of space for a context image,
 * so when allocating (or copying) an image, this function can be used to
 * find the right size for the specific engine.
 *
 * Return: size (in bytes) of an engine-specific context image
 *
 * Note: this size includes the HWSP, which is part of the context image
 * in LRC mode, but does not include the "shared data page" used with
 * GuC submission. The caller should account for this if using the GuC.
 */
2102
uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
2103 2104 2105
{
	int ret = 0;

2106
	WARN_ON(INTEL_GEN(engine->i915) < 8);
2107

2108
	switch (engine->id) {
2109
	case RCS:
2110
		if (INTEL_GEN(engine->i915) >= 9)
2111 2112 2113
			ret = GEN9_LR_CONTEXT_RENDER_SIZE;
		else
			ret = GEN8_LR_CONTEXT_RENDER_SIZE;
2114 2115 2116 2117 2118 2119 2120 2121 2122 2123
		break;
	case VCS:
	case BCS:
	case VECS:
	case VCS2:
		ret = GEN8_LR_CONTEXT_OTHER_SIZE;
		break;
	}

	return ret;
2124 2125
}

2126
static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
2127
					    struct intel_engine_cs *engine)
2128
{
2129
	struct drm_i915_gem_object *ctx_obj;
2130
	struct intel_context *ce = &ctx->engine[engine->id];
2131
	struct i915_vma *vma;
2132
	uint32_t context_size;
2133
	struct intel_ring *ring;
2134 2135
	int ret;

2136
	WARN_ON(ce->state);
2137

2138 2139
	context_size = round_up(intel_lr_context_size(engine),
				I915_GTT_PAGE_SIZE);
2140

2141 2142 2143
	/* One extra page as the sharing data between driver and GuC */
	context_size += PAGE_SIZE * LRC_PPHWSP_PN;

2144
	ctx_obj = i915_gem_object_create(ctx->i915, context_size);
2145
	if (IS_ERR(ctx_obj)) {
2146
		DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n");
2147
		return PTR_ERR(ctx_obj);
2148 2149
	}

2150
	vma = i915_vma_instance(ctx_obj, &ctx->i915->ggtt.base, NULL);
2151 2152 2153 2154 2155
	if (IS_ERR(vma)) {
		ret = PTR_ERR(vma);
		goto error_deref_obj;
	}

2156
	ring = intel_engine_create_ring(engine, ctx->ring_size);
2157 2158
	if (IS_ERR(ring)) {
		ret = PTR_ERR(ring);
2159
		goto error_deref_obj;
2160 2161
	}

2162
	ret = populate_lr_context(ctx, ctx_obj, engine, ring);
2163 2164
	if (ret) {
		DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
2165
		goto error_ring_free;
2166 2167
	}

2168
	ce->ring = ring;
2169
	ce->state = vma;
2170
	ce->initialised = engine->init_context == NULL;
2171 2172

	return 0;
2173

2174
error_ring_free:
2175
	intel_ring_free(ring);
2176
error_deref_obj:
2177
	i915_gem_object_put(ctx_obj);
2178
	return ret;
2179
}
2180

2181
void intel_lr_context_resume(struct drm_i915_private *dev_priv)
2182
{
2183
	struct intel_engine_cs *engine;
2184
	struct i915_gem_context *ctx;
2185
	enum intel_engine_id id;
2186 2187 2188 2189 2190 2191 2192 2193 2194 2195 2196 2197

	/* Because we emit WA_TAIL_DWORDS there may be a disparity
	 * between our bookkeeping in ce->ring->head and ce->ring->tail and
	 * that stored in context. As we only write new commands from
	 * ce->ring->tail onwards, everything before that is junk. If the GPU
	 * starts reading from its RING_HEAD from the context, it may try to
	 * execute that junk and die.
	 *
	 * So to avoid that we reset the context images upon resume. For
	 * simplicity, we just zero everything out.
	 */
	list_for_each_entry(ctx, &dev_priv->context_list, link) {
2198
		for_each_engine(engine, dev_priv, id) {
2199 2200
			struct intel_context *ce = &ctx->engine[engine->id];
			u32 *reg;
2201

2202 2203
			if (!ce->state)
				continue;
2204

2205 2206 2207 2208
			reg = i915_gem_object_pin_map(ce->state->obj,
						      I915_MAP_WB);
			if (WARN_ON(IS_ERR(reg)))
				continue;
2209

2210 2211 2212
			reg += LRC_STATE_PN * PAGE_SIZE / sizeof(*reg);
			reg[CTX_RING_HEAD+1] = 0;
			reg[CTX_RING_TAIL+1] = 0;
2213

C
Chris Wilson 已提交
2214
			ce->state->obj->mm.dirty = true;
2215
			i915_gem_object_unpin_map(ce->state->obj);
2216

2217 2218 2219 2220
			ce->ring->head = ce->ring->tail = 0;
			ce->ring->last_retired_head = -1;
			intel_ring_update_space(ce->ring);
		}
2221 2222
	}
}