last_may_be_rvi_call in case that a call comes after a taken branch

* add SRAM ready (resetfinish) condition for *Array (metaArray/dataArray)
req.ready

* fix mmio_resend_af wrong assignment
* fix wb_half_flush missOffset(using wb_lastIdx instead of PredictWidth
-1)
* change pipeline ready condition (this_ready =  this_stage_fire || this_stage_empty)
* delete 500-cycle ready condition (toICache(*).ready means the SRAM has
been reset and ready for read)

Previous logic checked the value of old_ctr to select between old target and
new target when updating ittage table. However, when we need to alloc a new
entry, the value of old_ctr is X because we do not reset ittage table. So we
would definitely write an X to the target field, which is the output of the
mux, as the selector is X.

* sc: fix a performance bug

* tage: fix number of use-alt-on-na counters

* tage: update provider u-bit according to provider results

* fix some typos
Signed-off-by: Ncuishuang <imcusg@gmail.com>

iprefetch uses vaddr instead of paddr.

* IFU <bug-fix>: deal with itlb miss for resend

* IFU <bug fix>: enable crossPageFault for resend-pf
Co-authored-by: NDeltaZero <lacrosseelis@gmail.com>

* ITLB <timing>: delay miss and flush req for ITLB

* add 2 ILTB requestor and delete tlb_arb

* Bump huancun

* ICacheMainPipe <bug-fix>: fix slot invalid condition

* ITLB <timing>: add port to 6

* ICacheMainPipe <bug-fix>: stop pipe when tlb miss

* ICacheMainPipe <bug-fix>: fix illegal flush
Co-authored-by: NLinJiawei <linjiawei20s@ict.ac.cn>

the mulitple-hit problem is yet to be solved (although it may be very rare)

* parameters: reduce ghr length and make it calculated using a formula

* bpu: add error checking for ghist ptr, support hist lengths that are not power of 2

* ICache <timing>: move parity decode to pipe

* ICacheMainPipe <timing>: remove parity af

* ReplacePipe <timing>: delay error generating

* ReplacePipe: block miss until get ReleaseAck

* IPrefetch: cancle prefetch req when meet MSHR

* Fetch <perf>: add fetch bubble performance counters

ftb,ftq: add a bit indicating there is an rvi call at the last 2 byte for ras to push the right address

* IFU <timing>: f2_data select signal optimization

* ICacheMainPipe <timing>: latch fetch req when tlb miss

* Frontend <timing>: add additional PMP checker

* Ftq <timing>: delete flush condition for prefetch.req

* ICacheMainPipe <timing>: move hit state change to s2

* ICache <bug-fix> delete PMP check assertion

* ICache <bug-fix> fix parity error condition

* ICacheMainPipe <bug-fix>: fix tlb resp condition

* when TLB req has been latched into tlb_slot, the
tlb_all_resp condition, which affects s0_fire should
depend on the slot result.

* when TLB req has been latched into tlb_slot, the
tlb_all_resp condition, which affects s0_fire should
depend on the slot result.