parameters: reduce ghr length and make it calculated using a formula (#1442)

* parameters: reduce ghr length and make it calculated using a formula

* bpu: add error checking for ghist ptr, support hist lengths that are not power of 2

src/main/scala/xiangshan/Parameters.scala

@@ -62,7 +62,7 @@ case class XSCoreParameters
   EnableJal: Boolean = false,
   EnableUBTB: Boolean = true,
   UbtbGHRLength: Int = 4,
-  HistoryLength: Int = 512,
+  // HistoryLength: Int = 512,
   EnableGHistDiff: Boolean = true,
   UbtbSize: Int = 256,
   FtbSize: Int = 2048,
@@ -241,6 +241,9 @@ case class XSCoreParameters
   usePTWRepeater: Boolean = false,
   softPTW: Boolean = false // dpi-c debug only
 ){
+  val allHistLens = SCHistLens ++ ITTageTableInfos.map(_._2) ++ TageTableInfos.map(_._2) :+ UbtbGHRLength
+  val HistoryLength = allHistLens.max + numBr * FtqSize + 9 // 256 for the predictor configs now
+
   val loadExuConfigs = Seq.fill(exuParameters.LduCnt)(LdExeUnitCfg)
   val storeExuConfigs = Seq.fill(exuParameters.StuCnt)(StaExeUnitCfg) ++ Seq.fill(exuParameters.StuCnt)(StdExeUnitCfg)
 
@@ -347,6 +350,8 @@ trait HasXSParameter {
     }.reduce(_++_) ++
       Set[FoldedHistoryInfo]((UbtbGHRLength, log2Ceil(UbtbSize)))
     ).toList
+  
+
 
   val CacheLineSize = coreParams.CacheLineSize
   val CacheLineHalfWord = CacheLineSize / 16

src/main/scala/xiangshan/frontend/BPU.scala

@@ -237,16 +237,11 @@ class PredictorIO(implicit p: Parameters) extends XSBundle {
 }
 
 @chiselName
-class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with HasPerfEvents {
+class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with HasPerfEvents with HasCircularQueuePtrHelper {
   val io = IO(new PredictorIO)
 
   val predictors = Module(if (useBPD) new Composer else new FakePredictor)
 
-  val folded_hist_infos = predictors.getFoldedHistoryInfo.getOrElse(Set()).toList
-  for ((len, compLen) <- folded_hist_infos) {
-    println(f"folded hist info: len $len, compLen $compLen")
-  }
-
   val s0_fire, s1_fire, s2_fire, s3_fire = Wire(Bool())
   val s1_valid, s2_valid, s3_valid = RegInit(false.B)
   val s1_ready, s2_ready, s3_ready = Wire(Bool())
@@ -290,7 +285,8 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with H
 
   val s0_ghist = WireInit(0.U.asTypeOf(UInt(HistoryLength.W)))
 
-  
+
+  println(f"history buffer length ${HistoryLength}")
   val ghv_write_datas = Wire(Vec(HistoryLength, Bool()))
   val ghv_wens = Wire(Vec(HistoryLength, Bool()))
   
@@ -413,13 +409,12 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with H
     }
   }
 
-  require(isPow2(HistoryLength))
   val s1_ghv_wens = (0 until HistoryLength).map(n =>
-    (0 until numBr).map(b => (s1_ghist_ptr).value === n.U(log2Ceil(HistoryLength).W) + b.U && resp.s1.shouldShiftVec(b) && s1_valid))
+    (0 until numBr).map(b => (s1_ghist_ptr).value === (CGHPtr(false.B, n.U) + b.U).value && resp.s1.shouldShiftVec(b) && s1_valid))
   val s1_ghv_wdatas = (0 until HistoryLength).map(n =>
     Mux1H(
       (0 until numBr).map(b => (
-        (s1_ghist_ptr).value === n.U(log2Ceil(HistoryLength).W) + b.U && resp.s1.shouldShiftVec(b),
+        (s1_ghist_ptr).value === (CGHPtr(false.B, n.U) + b.U).value && resp.s1.shouldShiftVec(b),
         resp.s1.brTaken && resp.s1.lastBrPosOH(b+1)
       ))
     )
@@ -471,11 +466,11 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with H
   }
 
   val s2_ghv_wens = (0 until HistoryLength).map(n =>
-    (0 until numBr).map(b => (s2_ghist_ptr).value === n.U(log2Ceil(HistoryLength).W) + b.U && resp.s2.shouldShiftVec(b) && s2_redirect))
+    (0 until numBr).map(b => (s2_ghist_ptr).value === (CGHPtr(false.B, n.U) + b.U).value && resp.s2.shouldShiftVec(b) && s2_redirect))
   val s2_ghv_wdatas = (0 until HistoryLength).map(n =>
     Mux1H(
       (0 until numBr).map(b => (
-        (s2_ghist_ptr).value === n.U(log2Ceil(HistoryLength).W) + b.U && resp.s2.shouldShiftVec(b),
+        (s2_ghist_ptr).value === (CGHPtr(false.B, n.U) + b.U).value && resp.s2.shouldShiftVec(b),
         resp.s2.full_pred.real_br_taken_mask()(b)
       ))
     )
@@ -535,11 +530,11 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with H
   }
 
   val s3_ghv_wens = (0 until HistoryLength).map(n =>
-    (0 until numBr).map(b => (s3_ghist_ptr).value === n.U(log2Ceil(HistoryLength).W) + b.U && resp.s3.shouldShiftVec(b) && s3_redirect))
+    (0 until numBr).map(b => (s3_ghist_ptr).value === (CGHPtr(false.B, n.U) + b.U).value && resp.s3.shouldShiftVec(b) && s3_redirect))
   val s3_ghv_wdatas = (0 until HistoryLength).map(n =>
     Mux1H(
       (0 until numBr).map(b => (
-        (s3_ghist_ptr).value === n.U(log2Ceil(HistoryLength).W) + b.U && resp.s3.shouldShiftVec(b),
+        (s3_ghist_ptr).value === (CGHPtr(false.B, n.U) + b.U).value && resp.s3.shouldShiftVec(b),
         resp.s3.full_pred.real_br_taken_mask()(b)
       ))
     )
@@ -611,10 +606,10 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with H
   val thisAheadFhOb = Wire(new AllAheadFoldedHistoryOldestBits(foldedGHistInfos))
   thisAheadFhOb.read(ghv, oldPtr)
   val redirect_ghv_wens = (0 until HistoryLength).map(n =>
-    (0 until numBr).map(b => oldPtr.value === (n.U(log2Ceil(HistoryLength).W) + b.U) && shouldShiftVec(b) && do_redirect.valid))
+    (0 until numBr).map(b => oldPtr.value === (CGHPtr(false.B, n.U) + b.U).value && shouldShiftVec(b) && do_redirect.valid))
   val redirect_ghv_wdatas = (0 until HistoryLength).map(n =>
     Mux1H(
-      (0 until numBr).map(b => oldPtr.value === (n.U(log2Ceil(HistoryLength).W) + b.U) && shouldShiftVec(b)),
+      (0 until numBr).map(b => oldPtr.value === (CGHPtr(false.B, n.U) + b.U).value && shouldShiftVec(b)),
       real_br_taken_mask
     )
   )
@@ -665,6 +660,10 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with H
     }
   }
 
+  XSError(isBefore(redirect.cfiUpdate.histPtr, s3_ghist_ptr) && do_redirect.valid, p"s3_ghist_ptr ${s3_ghist_ptr} exceeds redirect histPtr ${redirect.cfiUpdate.histPtr}\n")
+  XSError(isBefore(redirect.cfiUpdate.histPtr, s2_ghist_ptr) && do_redirect.valid, p"s2_ghist_ptr ${s2_ghist_ptr} exceeds redirect histPtr ${redirect.cfiUpdate.histPtr}\n")
+  XSError(isBefore(redirect.cfiUpdate.histPtr, s1_ghist_ptr) && do_redirect.valid, p"s1_ghist_ptr ${s1_ghist_ptr} exceeds redirect histPtr ${redirect.cfiUpdate.histPtr}\n")
+
   XSDebug(RegNext(reset.asBool) && !reset.asBool, "Reseting...\n")
   XSDebug(io.ftq_to_bpu.update.valid, p"Update from ftq\n")
   XSDebug(io.ftq_to_bpu.redirect.valid, p"Redirect from ftq\n")

src/main/scala/xiangshan/frontend/FrontendBundle.scala

@@ -144,6 +144,19 @@ class CGHPtr(implicit p: Parameters) extends CircularQueuePtr[CGHPtr](
 ){
   override def cloneType = (new CGHPtr).asInstanceOf[this.type]
 }
+
+object CGHPtr {
+  def apply(f: Bool, v: UInt)(implicit p: Parameters): CGHPtr = {
+    val ptr = Wire(new CGHPtr)
+    ptr.flag := f
+    ptr.value := v
+    ptr
+  }
+  def inverse(ptr: CGHPtr)(implicit p: Parameters): CGHPtr = {
+    apply(!ptr.flag, ptr.value)
+  }
+}
+
 class CircularGlobalHistory(implicit p: Parameters) extends GlobalHistory {
   val buffer = Vec(HistoryLength, Bool())
   type HistPtr = UInt