last_may_be_rvi_call in case that a call comes after a taken branch

* add SRAM ready (resetfinish) condition for *Array (metaArray/dataArray)
req.ready

* fix mmio_resend_af wrong assignment
* fix wb_half_flush missOffset(using wb_lastIdx instead of PredictWidth
-1)
* change pipeline ready condition (this_ready =  this_stage_fire || this_stage_empty)
* delete 500-cycle ready condition (toICache(*).ready means the SRAM has
been reset and ready for read)

* bump huancun, update Chisel3, revert sram hazard enhancement

* util.sram: rm a r/w hazard mux which is not needed. bump huancun

Previous logic checked the value of old_ctr to select between old target and
new target when updating ittage table. However, when we need to alloc a new
entry, the value of old_ctr is X because we do not reset ittage table. So we
would definitely write an X to the target field, which is the output of the
mux, as the selector is X.

* fix for chipsalliance/rocket-chip#2967

* decode: fix width of BitPat(?) in decode logic
Co-authored-by: NYinan Xu <xuyinan@ict.ac.cn>

Previously we made a mistake to connect rtc_clock to rtcTick for CLINT.

rtcTick should be on io_clock clock domain and asserted only one
clock cycle in io_clock for every cycle in rtc_clock. We add sampling
registers in this commit to fix this.

* difftest: disable runahead to make vcs happy

* difftest: bump huancun to make vcs happy

* difftest: bump difftest and ready-to-run

* difftest support ramsize and paddr base config
* 8GB/16GB nemu so are provided by ready-to-run

* ci: update nightly ci, manually set ram_size

* difftest: bump huancun to make vcs happy

* difftest,nemu: support run-time assign mem size

* ci: polish nightly ci script

An instruction with exceptions may have arbitrary instr values and
may be decoded into WFI instructions, which cause errors.

* sc: fix a performance bug

* tage: fix number of use-alt-on-na counters

* tage: update provider u-bit according to provider results

* feat: parameterize load/store pipeline, etc.

* fix: use LoadPipelineWidth rather than LoadQueueSize

* fix: parameterize `rdataPtrExtNext`

* SBuffer: fix idx update logic

* atomic: parameterize atomic logic in `MemBlock`

* StoreQueue: update allow enque requirement

* feat: support one load/store pipeline

* feat: parameterize `EnsbufferWidth`

* chore: resharp codes for better generated name

* chore: remove sc too many fail assertion

* chore: use XSWarn()

s1_tag_match_way is vaild iff tag_read.valid and meta_read.valid in s0
for the same req

XiangShan does not support fs=0 because when fs=0, all floating-point
states are not accessible. Spike supports fs=0. To diff with Spike,
we temporarily set fs to 1 when initialized.

This commit fixes the implementation of WFI. The WFI instruction
waits in the ROB until an interrupt might need servicing.

According to the RISC-V manual, the WFI must be unaffected by the
global interrupt bits in `mstatus` and the delegation register
`mideleg`.

To test WFI, we delay the interrupts for more cycles.

The RISC-V WFI instruction is previously decoded as NOP. This commit
adds support for the real wait-for-interrupt (WFI).

We add a state_wfi FSM in the ROB. After WFI leaves the ROB, the next
instruction will wait in the ROB until an interrupt.

* difftest: fix false-positive difftest intRF writeback, adapt to new difftest API

* csr: skip mip difftest

* bump difftest

* bump difftest

* fix some typos
Signed-off-by: Ncuishuang <imcusg@gmail.com>

old missqueue: cache req miss slot and mem access-er
Problem: these two func are totally different, make mq hard to handle in a single select policy.
Solution: divide these two funciton into two module.
  new MissQueue: only hold reqs that page cache miss and need re-req cache， a simple flushable queue
  llptw: Last level ptw, only access ptes, priorityMux queue

* mmu: rename PTW.scala to L2TLB.scala

* mmu: rename PTW to L2TLB

* mmu: rename PtwFsm to PTW

* mmu.l2tlb: divide missqueue into 'missqueue' and llptw

old missqueue: cache req miss slot and mem access-er
Problem: these two func are totally different, make mq hard to handle
  in single select policy.
Solution: divide these two funciton into two module.
  new MissQueue: only hold reqs that page cache miss and new re-req
  cache
  llptw: Last level ptw, only access ptes

* mmu.l2tlb: syntax bug that misses io assign

* mmu.l2tlb: fix bug that mistakes ptw's block signal

* mem: optimize missq reject to lq timing

DCache replay request is quite slow to generate, as it need to compare
load address with address in all valid miss queue entries.

Now we delay the usage of replay request from data cache.
Now replay request will not influence normal execuation flow until
load_s3 (1 cycle after load_s2, load result writeback to RS).

It is worth mentioning that "select refilling inst for load
writeback" will be disabled if dcacheRequireReplay in the
last cycle.

* dcache: compare probe block addr instead of full addr

* mem: do not replay from RS when ldld vio or fwd failed

ld-ld violation or forward failure will let an normal load inst replay
from fetch. If TLB hit and ld-ld violation / forward failure happens,
we write back that inst immediately. Meanwhile, such insts will not be
replayed from rs.

It should fix "mem: optimize missq reject to lq timing"

* mem: fix replay from rs condition

* mem: reduce refill to use latency

This commit update lq entry flag carefully in load_s3 to avoid extra
refill delay. It will remove the extra refill delay introduced by #1375
without harming memblock timing.

In #1375, we delayed load refill when dcache miss queue entry fails
to accept a miss. #1375 exchanges performance for better timing.

* mem: fix rs feedback priority

When dataInvalid && mshrFull, a succeed refill should not cancel
rs replay.

Corner Case that makes l2tlb's performance decrease sharply:
core may have mis-speculative memory access, which may cause tlb-miss and ptw req to l2tlb.
In l2tlb, the reqs may still miss and even have invalid pte that won't be stored in l2tlb.cache.
If the relative ptes are invalid, these reqs will be held by miss queue and wait for page walker performing
page table walk one by one. It's too slow and will raise time out assert in l2tlb.missqueue.

Solution:
store invalid entries(only super entries) into sp.
Bad news is that sp only has16 entries, so invaid entries will pollute sp as well.
Good news is that the invalid reqs are always in same super page, so only one entries is mostly enough.

* l2tlb.cache: sp entries now handles invalid entries

* l2tlb.cache: fix syntax error, forgot assgin some signals

* bump huancun

* sram: fix sram, keep rdata when w.valid

* tlb: when refill, just return miss at next cycle, rm unused assert

iprefetch uses vaddr instead of paddr.