ftb,ftq: add a bit indicating there is an rvi call at the last 2 byte for ras...

ftb,ftq: add a bit indicating there is an rvi call at the last 2 byte for ras to push the right address

src/main/scala/xiangshan/frontend/FTB.scala

@@ -141,7 +141,7 @@ class FTBEntry(implicit p: Parameters) extends XSBundle with FTBParams with BPUU
   val isRet       = Bool()
   val isJalr      = Bool()
 
-  val last_is_rvc = Bool()
+  val last_may_be_rvi_call = Bool()
 
   val always_taken = Vec(numBr, Bool())
 
@@ -221,7 +221,7 @@ class FTBEntry(implicit p: Parameters) extends XSBundle with FTBParams with BPUU
       p"lower=${Hexadecimal(tailSlot.lower)}, sharing=${tailSlot.sharing}}\n")
     XSDebug(cond, p"pftAddr=${Hexadecimal(pftAddr)}, carry=$carry\n")
     XSDebug(cond, p"isCall=$isCall, isRet=$isRet, isjalr=$isJalr\n")
-    XSDebug(cond, p"last_is_rvc=$last_is_rvc\n")
+    XSDebug(cond, p"last_may_be_rvi_call=$last_may_be_rvi_call\n")
     XSDebug(cond, p"------------------------------- \n")
   }
 

src/main/scala/xiangshan/frontend/FrontendBundle.scala

@@ -397,6 +397,7 @@ class FullBranchPrediction(implicit p: Parameters) extends XSBundle with HasBPUC
   val is_jalr = Bool()
   val is_call = Bool()
   val is_ret = Bool()
+  val last_may_be_rvi_call = Bool()
   val is_br_sharing = Bool()
 
   // val call_is_rvc = Bool()
@@ -487,6 +488,7 @@ class FullBranchPrediction(implicit p: Parameters) extends XSBundle with HasBPUC
     is_jalr := entry.tailSlot.valid && entry.isJalr
     is_call := entry.tailSlot.valid && entry.isCall
     is_ret := entry.tailSlot.valid && entry.isRet
+    last_may_be_rvi_call := entry.last_may_be_rvi_call
     is_br_sharing := entry.tailSlot.valid && entry.tailSlot.sharing
     
     val startLower        = Cat(0.U(1.W),    pc(instOffsetBits+log2Ceil(PredictWidth)-1, instOffsetBits))

src/main/scala/xiangshan/frontend/NewFtq.scala

@@ -306,7 +306,8 @@ class FTBEntryGen(implicit p: Parameters) extends XSModule with HasBackendRedire
   init_entry.isJalr := new_jmp_is_jalr
   init_entry.isCall := new_jmp_is_call
   init_entry.isRet  := new_jmp_is_ret
-  init_entry.last_is_rvc := DontCare
+  // that means fall thru points to the middle of an inst
+  init_entry.last_may_be_rvi_call := io.cfiIndex.bits === (PredictWidth-1).U && !pd.rvcMask(pd.jmpOffset)
 
   // if hit, check whether a new cfi(only br is possible) is detected
   val oe = io.old_entry
@@ -364,6 +365,7 @@ class FTBEntryGen(implicit p: Parameters) extends XSModule with HasBackendRedire
     // set jmp to invalid
     old_entry_modified.pftAddr := getLower(io.start_addr) + new_pft_offset
     old_entry_modified.carry := (getLower(io.start_addr) +& new_pft_offset).head(1).asBool
+    old_entry_modified.last_may_be_rvi_call := false.B
     old_entry_modified.isCall := false.B
     old_entry_modified.isRet := false.B
     old_entry_modified.isJalr := false.B

src/main/scala/xiangshan/frontend/RAS.scala

@@ -163,23 +163,22 @@ class RAS(implicit p: Parameters) extends BasePredictor {
 
   val s2_spec_push = WireInit(false.B)
   val s2_spec_pop = WireInit(false.B)
-  // val jump_is_first = io.callIdx.bits === 0.U
-  // val call_is_last_half = io.isLastHalfRVI && jump_is_first
-  // val spec_new_addr = packetAligned(io.pc.bits) + (io.callIdx.bits << instOffsetBits.U) + Mux( (io.isRVC | call_is_last_half) && HasCExtension.B, 2.U, 4.U)
-  val s2_spec_new_addr = io.in.bits.resp_in(0).s2.full_pred.fallThroughAddr
+  val s2_full_pred = io.in.bits.resp_in(0).s2.full_pred
+  // when last inst is an rvi call, fall through address would be set to the middle of it, so an addition is needed
+  val s2_spec_new_addr = s2_full_pred.fallThroughAddr + Mux(s2_full_pred.last_may_be_rvi_call, 2.U, 0.U)
   spec_ras.push_valid := s2_spec_push
   spec_ras.pop_valid  := s2_spec_pop
   spec_ras.spec_new_addr := s2_spec_new_addr
 
   // confirm that the call/ret is the taken cfi
-  s2_spec_push := io.s2_fire && io.in.bits.resp_in(0).s2.full_pred.hit_taken_on_call && !io.s3_redirect
-  s2_spec_pop  := io.s2_fire && io.in.bits.resp_in(0).s2.full_pred.hit_taken_on_ret  && !io.s3_redirect
+  s2_spec_push := io.s2_fire && s2_full_pred.hit_taken_on_call && !io.s3_redirect
+  s2_spec_pop  := io.s2_fire && s2_full_pred.hit_taken_on_ret  && !io.s3_redirect
 
   val s2_jalr_target = io.out.resp.s2.full_pred.jalr_target
-  val s2_last_target_in = io.in.bits.resp_in(0).s2.full_pred.targets.last
+  val s2_last_target_in = s2_full_pred.targets.last
   val s2_last_target_out = io.out.resp.s2.full_pred.targets.last
-  val s2_is_jalr = io.in.bits.resp_in(0).s2.full_pred.is_jalr
-  val s2_is_ret = io.in.bits.resp_in(0).s2.full_pred.is_ret
+  val s2_is_jalr = s2_full_pred.is_jalr
+  val s2_is_ret = s2_full_pred.is_ret
   // assert(is_jalr && is_ret || !is_ret)
   when(s2_is_ret) {
     s2_jalr_target := spec_top_addr