Frontend <timing>: add additional PMP checker

src/main/scala/xiangshan/frontend/Frontend.scala

@@ -73,21 +73,23 @@ class FrontendImp (outer: Frontend) extends LazyModuleImp(outer)
   val triggerEn = csrCtrl.trigger_enable
   ifu.io.csrTriggerEnable := VecInit(triggerEn(0), triggerEn(1), triggerEn(6), triggerEn(8))
 
-  // pmp
+// pmp
   val pmp = Module(new PMP())
-  val pmp_check = VecInit(Seq.fill(2)(Module(new PMPChecker(3, sameCycle = true)).io))
+  val pmp_check = VecInit(Seq.fill(4)(Module(new PMPChecker(3, sameCycle = true)).io))
   pmp.io.distribute_csr := csrCtrl.distribute_csr
-  val pmp_req_vec     = Wire(Vec(2, Valid(new PMPReqBundle())))
+  val pmp_req_vec     = Wire(Vec(4, Valid(new PMPReqBundle())))
   pmp_req_vec(0) <> icache.io.pmp(0).req
-  pmp_req_vec(1).valid  :=  icache.io.pmp(1).req.valid || ifu.io.pmp.req.valid 
-  pmp_req_vec(1).bits   := Mux(ifu.io.pmp.req.valid, ifu.io.pmp.req.bits, icache.io.pmp(1).req.bits)
+  pmp_req_vec(1) <> icache.io.pmp(1).req
+  pmp_req_vec(2) <> icache.io.pmp(2).req
+  pmp_req_vec(3) <> ifu.io.pmp.req
 
   for (i <- pmp_check.indices) {
     pmp_check(i).apply(tlbCsr.priv.imode, pmp.io.pmp, pmp.io.pma, pmp_req_vec(i))
-    icache.io.pmp(i).resp <> pmp_check(i).resp
   }
-  ifu.io.pmp.resp <> pmp_check(1).resp
-  ifu.io.pmp.req.ready := false.B
+  icache.io.pmp(0).resp <> pmp_check(0).resp
+  icache.io.pmp(1).resp <> pmp_check(1).resp
+  icache.io.pmp(2).resp <> pmp_check(2).resp
+  ifu.io.pmp.resp <> pmp_check(3 ).resp
 
   val tlb_req_arb     = Module(new Arbiter(new TlbReq, 2))
   tlb_req_arb.io.in(0) <> ifu.io.iTLBInter.req

src/main/scala/xiangshan/frontend/IFU.scala

@@ -66,7 +66,7 @@ class NewIFUIO(implicit p: Parameters) extends XSBundle {
   val csrTriggerEnable = Input(Vec(4, Bool()))
   val rob_commits = Flipped(Vec(CommitWidth, Valid(new RobCommitInfo)))
   val iTLBInter       = new BlockTlbRequestIO
-  val pmp             =   new IPrefetchPMPBundle
+  val pmp             =   new ICachePMPBundle
 }
 
 // record the situation in which fallThruAddr falls into
@@ -368,10 +368,11 @@ class NewIFU(implicit p: Parameters) extends XSModule
   val f3_mmio_to_commit_next = RegNext(f3_mmio_to_commit)
   val f3_mmio_can_go      = f3_mmio_to_commit && !f3_mmio_to_commit_next
 
-  val f3_ftq_flush_self     = fromFtq.redirect.valid && RedirectLevel.flushItself(fromFtq.redirect.bits.level)
-  val f3_ftq_flush_by_older = fromFtq.redirect.valid && isBefore(fromFtq.redirect.bits.ftqIdx, f3_ftq_req.ftqIdx)
+  val fromFtqRedirectReg = RegNext(fromFtq.redirect)
+  val f3_ftq_flush_self     = fromFtqRedirectReg.valid && RedirectLevel.flushItself(fromFtqRedirectReg.bits.level)
+  val f3_ftq_flush_by_older = fromFtqRedirectReg.valid && isBefore(fromFtqRedirectReg.bits.ftqIdx, f3_ftq_req.ftqIdx)
 
-  val f3_need_not_flush = f3_req_is_mmio && fromFtq.redirect.valid && !f3_ftq_flush_self && !f3_ftq_flush_by_older
+  val f3_need_not_flush = f3_req_is_mmio && fromFtqRedirectReg.valid && !f3_ftq_flush_self && !f3_ftq_flush_by_older
 
   when(f3_flush && !f3_need_not_flush)               {f3_valid := false.B}
   .elsewhen(f2_fire && !f2_flush )                   {f3_valid := true.B }
@@ -380,8 +381,8 @@ class NewIFU(implicit p: Parameters) extends XSModule
 
   val f3_mmio_use_seq_pc = RegInit(false.B)
 
-  val (redirect_ftqIdx, redirect_ftqOffset)  = (fromFtq.redirect.bits.ftqIdx,fromFtq.redirect.bits.ftqOffset)
-  val redirect_mmio_req = fromFtq.redirect.valid && redirect_ftqIdx === f3_ftq_req.ftqIdx && redirect_ftqOffset === 0.U
+  val (redirect_ftqIdx, redirect_ftqOffset)  = (fromFtqRedirectReg.bits.ftqIdx,fromFtqRedirectReg.bits.ftqOffset)
+  val redirect_mmio_req = fromFtqRedirectReg.valid && redirect_ftqIdx === f3_ftq_req.ftqIdx && redirect_ftqOffset === 0.U
 
   when(RegNext(f2_fire && !f2_flush) && f3_req_is_mmio)        { f3_mmio_use_seq_pc := true.B  }
   .elsewhen(redirect_mmio_req)                                 { f3_mmio_use_seq_pc := false.B }

src/main/scala/xiangshan/frontend/icache/ICache.scala

@@ -434,7 +434,7 @@ class ICacheIO(implicit p: Parameters) extends ICacheBundle
   val prefetch    = Flipped(new FtqPrefechBundle)
   val stop        = Input(Bool())
   val fetch       = Vec(PortNumber, new ICacheMainPipeBundle)
-  val pmp         = Vec(PortNumber, new ICachePMPBundle)
+  val pmp         = Vec(PortNumber + 1, new ICachePMPBundle)
   val itlb        = Vec(PortNumber, new BlockTlbRequestIO)
   val perfInfo    = Output(new ICachePerfInfo)
   val error       = new L1CacheErrorInfo
@@ -529,19 +529,13 @@ class ICacheImp(outer: ICache) extends LazyModuleImp(outer) with HasICacheParame
     prefetchPipe.io.fromFtq <> DontCare
   }
 
-  io.pmp(0).req.valid := mainPipe.io.pmp(0).req.valid ||  prefetchPipe.io.pmp.req.valid
-  io.pmp(0).req.bits := Mux(mainPipe.io.pmp(0).req.valid, mainPipe.io.pmp(0).req.bits, prefetchPipe.io.pmp.req.bits)
-  prefetchPipe.io.pmp.req.ready := !mainPipe.io.pmp(0).req.valid
-
-  mainPipe.io.pmp(0).resp <> io.pmp(0).resp
-  prefetchPipe.io.pmp.resp <> io.pmp(0).resp
+  io.pmp(0) <> mainPipe.io.pmp(0)
+  io.pmp(1) <> mainPipe.io.pmp(1)
+  io.pmp(2) <> prefetchPipe.io.pmp
 
   prefetchPipe.io.prefetchEnable := mainPipe.io.prefetchEnable
   prefetchPipe.io.prefetchDisable := mainPipe.io.prefetchDisable
 
-
-  io.pmp(1) <> mainPipe.io.pmp(1)
-
   when(mainPipe.io.pmp(0).req.valid && prefetchPipe.io.pmp.req.valid)
   {
     assert(false.B, "Both mainPipe PMP and prefetchPipe PMP valid!")

src/main/scala/xiangshan/frontend/icache/IPrefetch.scala

@@ -34,11 +34,6 @@ class PIQReq(implicit p: Parameters) extends IPrefetchBundle {
   val paddr      = UInt(PAddrBits.W)
 }
 
-class IPrefetchPMPBundle(implicit p: Parameters) extends ICacheBundle{
-  val req  = DecoupledIO(new PMPReqBundle())
-  val resp = Input(new PMPRespBundle())
-}
-
 
 class IPrefetchToMissUnit(implicit  p: Parameters) extends IPrefetchBundle{
   val enqReq  = DecoupledIO(new PIQReq)
@@ -47,7 +42,7 @@ class IPrefetchToMissUnit(implicit  p: Parameters) extends IPrefetchBundle{
 class IPredfetchIO(implicit p: Parameters) extends IPrefetchBundle {
   val fromFtq         = Flipped(new FtqPrefechBundle)
   val iTLBInter       = new BlockTlbRequestIO
-  val pmp             =   new IPrefetchPMPBundle
+  val pmp             =   new ICachePMPBundle
   val toIMeta         = Decoupled(new ICacheReadBundle)
   val fromIMeta       = Input(new ICacheMetaRespBundle)
   val toMissUnit     = new IPrefetchToMissUnit
@@ -151,7 +146,7 @@ class IPrefetchPipe(implicit p: Parameters) extends  IPrefetchModule
 
   /** Prefetch Stage 2: filtered req PIQ enqueue */
   val p2_valid =  generatePipeControl(lastFire = p1_fire, thisFire = p2_fire || p2_discard, thisFlush = false.B, lastFlush = false.B)
-  val p2_pmp_fire = p2_valid && io.pmp.req.ready
+  val p2_pmp_fire = p2_valid
   val pmpExcpAF = fromPMP.instr
 
   val p2_paddr     = RegEnable(next = tlb_resp_paddr,  enable = p1_fire)
@@ -169,7 +164,7 @@ class IPrefetchPipe(implicit p: Parameters) extends  IPrefetchModule
 
   p2_ready :=   p2_fire || p2_discard || !p2_valid
   p2_fire  :=   p2_valid && !p2_exception && p3_ready && p2_pmp_fire
-  p2_discard := p2_valid && ((p2_exception && p2_pmp_fire) || !io.pmp.req.ready)
+  p2_discard := p2_valid && (p2_exception && p2_pmp_fire)
 
   /** Prefetch Stage 2: filtered req PIQ enqueue */
   val p3_valid =  generatePipeControl(lastFire = p2_fire, thisFire = p3_fire || p3_discard, thisFlush = false.B, lastFlush = false.B)