Use fake Icache to fetch 8 instructions per cycle.

* microbench test fails even L2 is disabled

* Now we should read 8 times to fetch a whole cache line to writeback to
  memory. This seems a lot IPC degradation in emu: 0.543329 -> 0.532621.
  But it does not hurt too much on FPGA.
* Temporarily disable coherency.

TODO:
* Injecting interrupts in decode stage with NOP.
* Save mstatus.mie to mstatus.mpie

This reverts commit 7c95c717.

* The original bug is caused by 32-bit width of CacheProbeStage, which
  is merged after rv64 and forget to change the width to 64-bit.

* it seems the probe address is incorrectly shifted by 0x80 while
  probing dcache

* currently only support probe miss

* Now it will easily cause deadlock because the coherece probe requests
  are handled with the same pipeline of CPU access requests. When the
  Dcache is processing a miss request, it may form the following loop
  dependency:
    Icache.mem.resp -> CoherenceInterconnect.in(0).coh.resp ->
    Dcache.mem.resp -> CoherenceInterconnect (busy)
* To break the deadlock, we should give higher priority to coherence
  probe requests in L1 Cache. For example, we should add another state
  machine or pipeline to handle coherence probe requests. In this way,
  the coherence probe requests can be handled without waiting for the
  CPU access requests to finish.

* SimpleBusUL is used for MMIO and SimpleBusUH is used for memory
* should refactor SimpleBus2AXI4Converter to support SimpleBusUL and
  SimpleBusUH