Use fake Icache to fetch 8 instructions per cycle.

FPU can run at 200+MHz on axu3cg board now :)

[IntToFloat]: Count leading zeros of positive and negative number in parallel because IntToFloat is in the critical path

FPUv0.1 can pass all rvf/rvd tests in both riscv-tests and berkeley-softfloat
Signed-off-by: NLinJiawei <linjiav@outlook.com>

* refer to the RAS prediction hints in RV32I in the RISC-V manual

This reverts commit 2dfc501e.

This reverts merge request !72

* if we disable dcache, the compilation will fail

* This can help to generate desired frequency of timer interrupt, no
  matter what frequency of the clock is.

* According to The RISC-V Instruction Set Manual Volume II:
Privileged Architecture, for instruction-fetch access or
page-fault exceptions on systems with variable-length instructions,
m/stval will contain the virtual address of the portion
of the instruction that caused the fault while m/sepc will
point to the beginning of the instruction.

* To run more programs on debian, we use 256MB memory described in dts.
  But if the hardware still provides 128MB memory, the memory access
  will wrap around when Linux allocate a physical page excceed 128MB,
  which causes wrong memory access.

* after 4 hours, the command will be sent repeatly

* An instruciton fetch will set the A bit of the PTE, even this
  instruction will be flushed later due to branch mis-prediction.
  Although this will not cause correctness issue, it will introduce
  inconsistent behavior compared with NEMU.
* To run DiffTest while testing debian, a solution is to disable
  updating A bit and D bit in both NOOP and NEMU.

* this can reduce the idle time in Linux

* this is because we can not control the mip.mtip bit in NEMU

This reverts commit fd237745.

* This will skip instruction fetching from MMIO, which is hard to
  compare with NEMU.