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提交 4cd61964 编写于 作者: Z Zihao Yu
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fix indent

上级 f1ae1cd3
隐藏空白更改
内联 并排
Showing with 84 addition and 86 deletion
src/main/scala/bus/simplebus/SimpleBus.scala
浏览文件 @ 4cd61964
......@@ -18,7 +18,7 @@ object SimpleBusCmd {
def writeBurst = "b0011".U // write | refill
def writeLast = "b0111".U // write | refill
def probe = "b1000".U // read | do nothing
def prefetch = "b0100".U // read | refill
def prefetch = "b0100".U // read | refill
// resp
def readLast = "b0110".U
......@@ -53,11 +53,11 @@ class SimpleBusReqBundle(val userBits: Int = 0) extends SimpleBusBundle {
def isRead() = !cmd(0) && !cmd(3)
def isWrite() = cmd(0)
def isBurst() = cmd(1)
def isReadBurst() = cmd === SimpleBusCmd.readBurst
def isReadBurst() = cmd === SimpleBusCmd.readBurst
def isWriteSingle() = cmd === SimpleBusCmd.write
def isWriteLast() = cmd === SimpleBusCmd.writeLast
def isProbe() = cmd === SimpleBusCmd.probe
def isPrefetch() = cmd === SimpleBusCmd.prefetch
def isPrefetch() = cmd === SimpleBusCmd.prefetch
}
class SimpleBusRespBundle(val userBits: Int = 0) extends SimpleBusBundle {
......@@ -70,7 +70,7 @@ class SimpleBusRespBundle(val userBits: Int = 0) extends SimpleBusBundle {
def isReadLast() = cmd === SimpleBusCmd.readLast
def isProbeHit() = cmd === SimpleBusCmd.probeHit
def isProbeMiss() = cmd === SimpleBusCmd.probeMiss
def isPrefetch() = cmd === SimpleBusCmd.prefetch
def isPrefetch() = cmd === SimpleBusCmd.prefetch
}
// Uncache
......@@ -94,5 +94,5 @@ class SimpleBusC(val userBits: Int = 0) extends SimpleBusBundle {
val mem = new SimpleBusUC(userBits)
val coh = Flipped(new SimpleBusUC(userBits))
def memtoAXI4() = this.mem.toAXI4
def memtoAXI4() = this.mem.toAXI4
}
src/main/scala/noop/Cache.scala
浏览文件 @ 4cd61964
......@@ -12,7 +12,7 @@ case class CacheConfig (
ro: Boolean = false,
name: String = "cache",
userBits: Int = 0,
cacheLevel: Int = 1,
cacheLevel: Int = 1,
totalSize: Int = 32, // Kbytes
ways: Int = 4
......@@ -32,7 +32,7 @@ sealed trait HasCacheConst {
val hasCohInt = (if (hasCoh) 1 else 0)
val hasPrefetch = cacheName == "l2cache"
val cacheLevel = cacheConfig.cacheLevel
val cacheLevel = cacheConfig.cacheLevel
val TotalSize = cacheConfig.totalSize
val Ways = cacheConfig.ways
val LineSize = XLEN // byte
......@@ -118,7 +118,7 @@ sealed class CacheStage1(implicit val cacheConfig: CacheConfig) extends CacheMod
io.out.valid := io.in.valid && io.metaReadBus.req.ready && io.dataReadBus.req.ready
io.in.ready := (!io.in.valid || io.out.fire()) && io.metaReadBus.req.ready && io.dataReadBus.req.ready
Debug(debug) {
Debug(debug) {
printf("%d: [" + cacheName + " stage1]: in.ready = %d, in.valid = %d, out.valid = %d, out.ready = %d, addr = %x, cmd = %x, dataReadBus.req.valid = %d\n",
GTimer(), io.in.ready, io.in.valid, io.out.valid, io.out.ready, io.in.bits.addr, io.in.bits.cmd, io.dataReadBus.req.valid)
}
......@@ -185,7 +185,7 @@ sealed class CacheStage2(implicit val cacheConfig: CacheConfig) extends CacheMod
io.out.valid := io.in.valid
io.in.ready := !io.in.valid || io.out.fire()
Debug(debug) {
Debug(debug) {
printf("%d: [" + cacheName + " stage2]: in.ready = %d, in.valid = %d, out.valid = %d, out.ready = %d, addr = %x, waymask = %d\n",
GTimer(), io.in.ready, io.in.valid, io.out.valid, io.out.ready, req.addr, waymask)
}
......@@ -207,7 +207,7 @@ sealed class CacheStage3(implicit val cacheConfig: CacheConfig) extends CacheMod
val cohResp = Decoupled(new SimpleBusRespBundle)
// use to distinguish prefetch request and normal request
val dataReadRespToL1 = Output(Bool())
val dataReadRespToL1 = Output(Bool())
})
val metaWriteArb = Module(new Arbiter(CacheMetaArrayWriteBus().req.bits, 2))
......@@ -219,7 +219,7 @@ sealed class CacheStage3(implicit val cacheConfig: CacheConfig) extends CacheMod
val hit = io.in.valid && io.in.bits.hit
val miss = io.in.valid && !io.in.bits.hit
val probe = io.in.valid && hasCoh.B && req.isProbe()
val hitReadBurst = hit && req.isReadBurst()
val hitReadBurst = hit && req.isReadBurst()
val meta = Mux1H(io.in.bits.waymask, io.in.bits.metas)
assert(!(mmio && hit), "MMIO request should not hit in cache")
......@@ -228,10 +228,10 @@ sealed class CacheStage3(implicit val cacheConfig: CacheConfig) extends CacheMod
val dataRead = Mux(useForwardData, io.in.bits.forwardData.data.data, dataReadArray)
val wordMask = Mux(!ro.B && req.isWrite(), MaskExpand(req.wmask), 0.U(DataBits.W))
val writeL2BeatCnt = Counter(LineBeats)
when(io.out.fire() && (req.cmd === SimpleBusCmd.writeBurst || req.isWriteLast())) {
writeL2BeatCnt.inc()
}
val writeL2BeatCnt = Counter(LineBeats)
when(io.out.fire() && (req.cmd === SimpleBusCmd.writeBurst || req.isWriteLast())) {
writeL2BeatCnt.inc()
}
val hitWrite = hit && req.isWrite()
val dataHitWriteBus = Wire(CacheDataArrayWriteBus()).apply(
......@@ -251,8 +251,8 @@ sealed class CacheStage3(implicit val cacheConfig: CacheConfig) extends CacheMod
val readBeatCnt = Counter(LineBeats)
val writeBeatCnt = Counter(LineBeats)
val s2_idle :: s2_dataReadWait :: s2_dataOK :: Nil = Enum(3)
val s2_idle :: s2_dataReadWait :: s2_dataOK :: Nil = Enum(3)
val state2 = RegInit(s2_idle)
io.dataReadBus.apply(valid = (state === s_memWriteReq || state === s_release) && (state2 === s2_idle),
......@@ -296,12 +296,12 @@ sealed class CacheStage3(implicit val cacheConfig: CacheConfig) extends CacheMod
((state === s_release) && (state2 === s2_dataOK))
io.cohResp.bits.rdata := dataHitWay
val releaseLast = Counter(state === s_release && io.cohResp.fire(), LineBeats)._2
io.cohResp.bits.cmd := Mux(state === s_release, Mux(releaseLast, SimpleBusCmd.readLast, 0.U),
io.cohResp.bits.cmd := Mux(state === s_release, Mux(releaseLast, SimpleBusCmd.readLast, 0.U),
Mux(hit, SimpleBusCmd.probeHit, SimpleBusCmd.probeMiss))
val respToL1Fire = hitReadBurst && io.out.ready && state2 === s2_dataOK
val respToL1Last = Counter((state === s_idle || state === s_release && state2 === s2_dataOK) && hitReadBurst && io.out.ready, LineBeats)._2
val respToL1Fire = hitReadBurst && io.out.ready && state2 === s2_dataOK
val respToL1Last = Counter((state === s_idle || state === s_release && state2 === s2_dataOK) && hitReadBurst && io.out.ready, LineBeats)._2
switch (state) {
is (s_idle) {
afterFirstRead := false.B
......@@ -312,10 +312,10 @@ sealed class CacheStage3(implicit val cacheConfig: CacheConfig) extends CacheMod
state := Mux(hit, s_release, s_idle)
readBeatCnt.value := addr.wordIndex
}
}.elsewhen (hitReadBurst && io.out.ready) {
state := s_release
readBeatCnt.value := Mux(addr.wordIndex === (LineBeats - 1).U, 0.U, (addr.wordIndex + 1.U))
}.elsewhen ((miss || mmio) && !io.flush) {
} .elsewhen (hitReadBurst && io.out.ready) {
state := s_release
readBeatCnt.value := Mux(addr.wordIndex === (LineBeats - 1).U, 0.U, (addr.wordIndex + 1.U))
} .elsewhen ((miss || mmio) && !io.flush) {
state := Mux(mmio, s_mmioReq, Mux(!ro.B && meta.dirty, s_memWriteReq, s_memReadReq))
}
}
......@@ -326,7 +326,7 @@ sealed class CacheStage3(implicit val cacheConfig: CacheConfig) extends CacheMod
is (s_release) {
when (io.cohResp.fire() || respToL1Fire) { readBeatCnt.inc() }
when (probe && io.cohResp.fire() && releaseLast || respToL1Fire && respToL1Last) { state := s_idle }
}
}
is (s_memReadReq) { when (io.mem.req.fire()) {
state := s_memReadResp
......@@ -337,7 +337,7 @@ sealed class CacheStage3(implicit val cacheConfig: CacheConfig) extends CacheMod
when (io.mem.resp.fire()) {
afterFirstRead := true.B
readBeatCnt.inc()
when (req.cmd === SimpleBusCmd.writeBurst) { writeL2BeatCnt.value := 0.U }
when (req.cmd === SimpleBusCmd.writeBurst) { writeL2BeatCnt.value := 0.U }
when (io.mem.resp.bits.isReadLast()) { state := s_wait_resp }
}
}
......@@ -371,34 +371,34 @@ sealed class CacheStage3(implicit val cacheConfig: CacheConfig) extends CacheMod
io.metaWriteBus.req <> metaWriteArb.io.out
if (cacheLevel == 2) {
when ((state === s_memReadResp) && io.mem.resp.fire() && req.isReadBurst()) {
// readBurst request miss
io.out.bits.rdata := dataRefill
io.out.bits.cmd := Mux(io.mem.resp.bits.isReadLast(), SimpleBusCmd.readLast, SimpleBusCmd.readBurst)
}.elsewhen (req.isWriteLast() || req.cmd === SimpleBusCmd.writeBurst) {
// writeBurst/writeLast request, no matter hit or miss
io.out.bits.rdata := Mux(hit, dataRead, inRdataRegDemand)
io.out.bits.cmd := DontCare
}.elsewhen (hitReadBurst && state === s_release) {
// readBurst request hit
io.out.bits.rdata := dataHitWay
io.out.bits.cmd := Mux(respToL1Last, SimpleBusCmd.readLast, SimpleBusCmd.readBurst)
}.otherwise {
io.out.bits.rdata := Mux(hit, dataRead, inRdataRegDemand)
io.out.bits.cmd := req.cmd
}
when (req.isBurst()) {
io.out.valid := io.in.valid && (Mux(req.isWrite() && (hit || !hit && state === s_wait_resp), true.B, (state === s_memReadResp && io.mem.resp.fire() && req.cmd === SimpleBusCmd.readBurst)) || (respToL1Fire && respToL1Last && state === s_release))
}.otherwise {
io.out.valid := io.in.valid && Mux(probe, false.B, Mux(hit, true.B, Mux(req.isWrite() || mmio, state === s_wait_resp, afterFirstRead && !alreadyOutFire)))
}
} else {
io.out.bits.rdata := Mux(hit, dataRead, inRdataRegDemand)
when ((state === s_memReadResp) && io.mem.resp.fire() && req.isReadBurst()) {
// readBurst request miss
io.out.bits.rdata := dataRefill
io.out.bits.cmd := Mux(io.mem.resp.bits.isReadLast(), SimpleBusCmd.readLast, SimpleBusCmd.readBurst)
}.elsewhen (req.isWriteLast() || req.cmd === SimpleBusCmd.writeBurst) {
// writeBurst/writeLast request, no matter hit or miss
io.out.bits.rdata := Mux(hit, dataRead, inRdataRegDemand)
io.out.bits.cmd := DontCare
}.elsewhen (hitReadBurst && state === s_release) {
// readBurst request hit
io.out.bits.rdata := dataHitWay
io.out.bits.cmd := Mux(respToL1Last, SimpleBusCmd.readLast, SimpleBusCmd.readBurst)
}.otherwise {
io.out.bits.rdata := Mux(hit, dataRead, inRdataRegDemand)
io.out.bits.cmd := req.cmd
}
when (req.isBurst()) {
io.out.valid := io.in.valid && (Mux(req.isWrite() && (hit || !hit && state === s_wait_resp), true.B, (state === s_memReadResp && io.mem.resp.fire() && req.cmd === SimpleBusCmd.readBurst)) || (respToL1Fire && respToL1Last && state === s_release))
}.otherwise {
io.out.valid := io.in.valid && Mux(probe, false.B, Mux(hit, true.B, Mux(req.isWrite() || mmio, state === s_wait_resp, afterFirstRead && !alreadyOutFire)))
}
} else {
io.out.bits.rdata := Mux(hit, dataRead, inRdataRegDemand)
io.out.bits.cmd := DontCare
io.out.valid := io.in.valid && Mux(probe, false.B, Mux(hit, true.B, Mux(req.isWrite() || mmio, state === s_wait_resp, afterFirstRead && !alreadyOutFire)))
}
}
io.out.bits.user.zip(req.user).map { case (o,i) => o := i }
// With critical-word first, the pipeline registers between
......@@ -410,9 +410,9 @@ sealed class CacheStage3(implicit val cacheConfig: CacheConfig) extends CacheMod
)
io.in.ready := io.out.ready && (state === s_idle) && !miss && !probe
io.dataReadRespToL1 := hitReadBurst && (state === s_idle && io.out.ready || state === s_release && state2 === s2_dataOK)
io.dataReadRespToL1 := hitReadBurst && (state === s_idle && io.out.ready || state === s_release && state2 === s2_dataOK)
assert(!(metaHitWriteBus.req.valid && metaRefillWriteBus.req.valid))
assert(!(metaHitWriteBus.req.valid && metaRefillWriteBus.req.valid))
assert(!(dataHitWriteBus.req.valid && dataRefillWriteBus.req.valid))
assert(!(!ro.B && io.flush), "only allow to flush icache")
Debug(debug) {
......@@ -486,7 +486,7 @@ class Cache(implicit val cacheConfig: CacheConfig) extends CacheModule {
BoringUtils.addSource(s3.io.in.valid && s3.io.in.bits.hit, "perfCntCondM" + cacheName + "Hit")
Debug(debug) {
Debug(debug) {
io.in.dump(cacheName + ".in")
printf("%d: s1:(%d,%d), s2:(%d,%d), s3:(%d,%d)\n",
GTimer(), s1.io.in.valid, s1.io.in.ready, s2.io.in.valid, s2.io.in.ready, s3.io.in.valid, s3.io.in.ready)
......
src/main/scala/noop/EXU.scala
浏览文件 @ 4cd61964
......@@ -86,11 +86,7 @@ class EXU(implicit val p: NOOPConfig) extends NOOPModule {
io.forward.wb.rfDest := io.in.bits.ctrl.rfDest
io.forward.wb.rfData := Mux(alu.io.out.fire(), aluOut, lsuOut)
io.forward.fuType := io.in.bits.ctrl.fuType
/*
Debug(true) {
printf("[EXU] dmem.req.valid = %d, dmem.req.bits.addr = %x\n", io.dmem.req.valid, io.dmem.req.bits.addr)
}
*/
val isBru = ALUOpType.isBru(fuOpType)
BoringUtils.addSource(alu.io.out.fire() && !isBru, "perfCntCondMaluInstr")
BoringUtils.addSource(alu.io.out.fire() && isBru, "perfCntCondMbruInstr")
......
src/main/scala/noop/NOOP.scala
浏览文件 @ 4cd61964
......@@ -43,7 +43,7 @@ class NOOP(implicit val p: NOOPConfig) extends NOOPModule {
val imem = new SimpleBusC
val dmem = new SimpleBusC
val mmio = new SimpleBusUC
val prefetchReq = Decoupled(new SimpleBusReqBundle)
val prefetchReq = Decoupled(new SimpleBusReqBundle)
})
val ifu = Module(new IFU)
......@@ -79,7 +79,7 @@ class NOOP(implicit val p: NOOPConfig) extends NOOPModule {
when (idu2.io.in.valid) { printf("ID2: pc = 0x%x, instr = 0x%x, pnpc = 0x%x\n", idu2.io.in.bits.pc, idu2.io.in.bits.instr, idu2.io.in.bits.pnpc) }
when (isu.io.in.valid) { printf("ISU: pc = 0x%x, pnpc = 0x%x\n", isu.io.in.bits.cf.pc, isu.io.in.bits.cf.pnpc) }
when (exu.io.in.valid) { printf("EXU: pc = 0x%x, pnpc = 0x%x\n", exu.io.in.bits.cf.pc, exu.io.in.bits.cf.pnpc) }
when (wbu.io.in.valid) { printf("WBU: pc = 0x%x\n", wbu.io.in.bits.decode.cf.pc) }
when (wbu.io.in.valid) { printf("WBU: pc = 0x%x\n", wbu.io.in.bits.decode.cf.pc) }
}
isu.io.wb <> wbu.io.wb
......@@ -91,7 +91,7 @@ class NOOP(implicit val p: NOOPConfig) extends NOOPModule {
io.imem <> Cache(ifu.io.imem, mmioXbar.io.in(0), Fill(2, ifu.io.flushVec(0) | ifu.io.bpFlush))(
CacheConfig(ro = true, name = "icache", userBits = AddrBits*2 + 4)) // userBits = AddrBits + BrIdxBits
io.dmem <> Cache(exu.io.dmem, mmioXbar.io.in(1), "b00".U, enable = HasDcache)(CacheConfig(ro = false, name = "dcache"))
io.prefetchReq.bits := exu.io.dmem.req.bits
io.prefetchReq.valid := exu.io.dmem.req.valid
io.prefetchReq.bits := exu.io.dmem.req.bits
io.prefetchReq.valid := exu.io.dmem.req.valid
io.mmio <> mmioXbar.io.out
}
src/main/scala/noop/fu/CSR.scala
浏览文件 @ 4cd61964
......@@ -372,7 +372,7 @@ class CSR(implicit val p: NOOPConfig) extends NOOPModule with HasCSRConst {
"Custom6" -> (0xb20, "Custom6" ),
"Custom7" -> (0xb21, "Custom7" ),
"Custom8" -> (0xb22, "Custom8" ),
"Ml2cacheHit" -> (0xb23, "perfCntCondMl2cacheHit")
"Ml2cacheHit" -> (0xb23, "perfCntCondMl2cacheHit")
)
val perfCntCond = List.fill(0x80)(WireInit(false.B))
(perfCnts zip perfCntCond).map { case (c, e) => { when (e) { c := c + 1.U } } }
......
src/main/scala/system/SoC.scala
浏览文件 @ 4cd61964
......@@ -41,32 +41,34 @@ class NOOPSoC(implicit val p: NOOPConfig) extends Module with HasSoCParameter {
xbar.io.in(0) <> cohMg.io.out.mem
xbar.io.in(1) <> noop.io.dmem.mem
if (HasL2cache) {
if (HasL2cache) {
val l2cacheOut = Wire(new SimpleBusC)
if (HasPrefetch) {
val prefetcher = Module(new Prefetcher)
prefetcher.io.in <> noop.io.prefetchReq
val l2cacheIn = Wire(new SimpleBusUC)
val l2cacheInReqArb = Module(new Arbiter(chiselTypeOf(noop.io.prefetchReq.bits), 2))
l2cacheInReqArb.io.in(0) <> xbar.io.out.req
l2cacheInReqArb.io.in(1) <> prefetcher.io.out
l2cacheIn.req <> l2cacheInReqArb.io.out
xbar.io.out.resp <> l2cacheIn.resp
l2cacheOut <> Cache(in = l2cacheIn, mmio = 0.U.asTypeOf(new SimpleBusUC), flush = "b00".U, enable = true)(CacheConfig(ro = false, name = "l2cache", cacheLevel = 2))
} else {
l2cacheOut <> Cache(in = xbar.io.out, mmio = 0.U.asTypeOf(new SimpleBusUC), flush = "b00".U, enable = true)(CacheConfig(ro = false, name = "l2cache", cacheLevel = 2))
}
val prefetcher = Module(new Prefetcher)
prefetcher.io.in <> noop.io.prefetchReq
val l2cacheIn = Wire(new SimpleBusUC)
val l2cacheInReqArb = Module(new Arbiter(chiselTypeOf(noop.io.prefetchReq.bits), 2))
l2cacheInReqArb.io.in(0) <> xbar.io.out.req
l2cacheInReqArb.io.in(1) <> prefetcher.io.out
l2cacheIn.req <> l2cacheInReqArb.io.out
xbar.io.out.resp <> l2cacheIn.resp
l2cacheOut <> Cache(in = l2cacheIn, mmio = 0.U.asTypeOf(new SimpleBusUC), flush = "b00".U, enable = true)(
CacheConfig(name = "l2cache", totalSize = 128, cacheLevel = 2))
} else {
l2cacheOut <> Cache(in = xbar.io.out, mmio = 0.U.asTypeOf(new SimpleBusUC), flush = "b00".U, enable = true)(
CacheConfig(name = "l2cache", totalSize = 128, cacheLevel = 2))
}
io.mem <> l2cacheOut.mem.toAXI4()
l2cacheOut.coh.resp.ready := true.B
l2cacheOut.coh.req.valid := false.B
l2cacheOut.coh.req.bits := DontCare
l2cacheOut.coh.resp.ready := true.B
l2cacheOut.coh.req.valid := false.B
l2cacheOut.coh.req.bits := DontCare
} else {
io.mem <> xbar.io.out.toAXI4()
}
if (!HasPrefetch) {
noop.io.prefetchReq.ready := true.B
}
if (!HasPrefetch) {
noop.io.prefetchReq.ready := true.B
}
noop.io.imem.coh.resp.ready := true.B
noop.io.imem.coh.req.valid := false.B
......
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