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体验新版 GitCode,发现更多精彩内容 >>
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614aaf64
编写于
11月 15, 2019
作者:
Z
Zihao Yu
浏览文件
操作
浏览文件
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电子邮件补丁
差异文件
refactor some code
上级
4cd61964
变更
2
隐藏空白更改
内联
并排
Showing
2 changed file
with
10 addition
and
15 deletion
+10
-15
src/main/scala/noop/Cache.scala
src/main/scala/noop/Cache.scala
+5
-8
src/main/scala/system/SoC.scala
src/main/scala/system/SoC.scala
+5
-7
未找到文件。
src/main/scala/noop/Cache.scala
浏览文件 @
614aaf64
...
...
@@ -387,20 +387,17 @@ sealed class CacheStage3(implicit val cacheConfig: CacheConfig) extends CacheMod
io
.
out
.
bits
.
rdata
:=
Mux
(
hit
,
dataRead
,
inRdataRegDemand
)
io
.
out
.
bits
.
cmd
:=
req
.
cmd
}
when
(
req
.
isBurst
())
{
io
.
out
.
valid
:=
io
.
in
.
valid
&&
(
Mux
(
req
.
isWrite
()
&&
(
hit
||
!
hit
&&
state
===
s_wait_resp
),
true
.
B
,
(
state
===
s_memReadResp
&&
io
.
mem
.
resp
.
fire
()
&&
req
.
cmd
===
SimpleBusCmd
.
readBurst
))
||
(
respToL1Fire
&&
respToL1Last
&&
state
===
s_release
))
}.
otherwise
{
io
.
out
.
valid
:=
io
.
in
.
valid
&&
Mux
(
probe
,
false
.
B
,
Mux
(
hit
,
true
.
B
,
Mux
(
req
.
isWrite
()
||
mmio
,
state
===
s_wait_resp
,
afterFirstRead
&&
!
alreadyOutFire
)))
}
}
else
{
io
.
out
.
bits
.
rdata
:=
Mux
(
hit
,
dataRead
,
inRdataRegDemand
)
io
.
out
.
bits
.
cmd
:=
DontCare
io
.
out
.
valid
:=
io
.
in
.
valid
&&
Mux
(
probe
,
false
.
B
,
Mux
(
hit
,
true
.
B
,
Mux
(
req
.
isWrite
()
||
mmio
,
state
===
s_wait_resp
,
afterFirstRead
&&
!
alreadyOutFire
)))
}
io
.
out
.
bits
.
user
.
zip
(
req
.
user
).
map
{
case
(
o
,
i
)
=>
o
:=
i
}
io
.
out
.
valid
:=
io
.
in
.
valid
&&
Mux
(
req
.
isBurst
()
&&
(
cacheLevel
==
2
).
B
,
Mux
(
req
.
isWrite
()
&&
(
hit
||
!
hit
&&
state
===
s_wait_resp
),
true
.
B
,
(
state
===
s_memReadResp
&&
io
.
mem
.
resp
.
fire
()
&&
req
.
cmd
===
SimpleBusCmd
.
readBurst
))
||
(
respToL1Fire
&&
respToL1Last
&&
state
===
s_release
),
Mux
(
probe
,
false
.
B
,
Mux
(
hit
,
true
.
B
,
Mux
(
req
.
isWrite
()
||
mmio
,
state
===
s_wait_resp
,
afterFirstRead
&&
!
alreadyOutFire
)))
)
// With critical-word first, the pipeline registers between
// s2 and s3 can not be overwritten before a missing request
// is totally handled. We use io.isFinish to indicate when the
...
...
src/main/scala/system/SoC.scala
浏览文件 @
614aaf64
...
...
@@ -43,7 +43,7 @@ class NOOPSoC(implicit val p: NOOPConfig) extends Module with HasSoCParameter {
if
(
HasL2cache
)
{
val
l2cacheOut
=
Wire
(
new
SimpleBusC
)
if
(
HasPrefetch
)
{
val
l2cacheIn
=
if
(
HasPrefetch
)
{
val
prefetcher
=
Module
(
new
Prefetcher
)
prefetcher
.
io
.
in
<>
noop
.
io
.
prefetchReq
val
l2cacheIn
=
Wire
(
new
SimpleBusUC
)
...
...
@@ -52,12 +52,10 @@ class NOOPSoC(implicit val p: NOOPConfig) extends Module with HasSoCParameter {
l2cacheInReqArb
.
io
.
in
(
1
)
<>
prefetcher
.
io
.
out
l2cacheIn
.
req
<>
l2cacheInReqArb
.
io
.
out
xbar
.
io
.
out
.
resp
<>
l2cacheIn
.
resp
l2cacheOut
<>
Cache
(
in
=
l2cacheIn
,
mmio
=
0.
U
.
asTypeOf
(
new
SimpleBusUC
),
flush
=
"b00"
.
U
,
enable
=
true
)(
CacheConfig
(
name
=
"l2cache"
,
totalSize
=
128
,
cacheLevel
=
2
))
}
else
{
l2cacheOut
<>
Cache
(
in
=
xbar
.
io
.
out
,
mmio
=
0.
U
.
asTypeOf
(
new
SimpleBusUC
),
flush
=
"b00"
.
U
,
enable
=
true
)(
CacheConfig
(
name
=
"l2cache"
,
totalSize
=
128
,
cacheLevel
=
2
))
}
l2cacheIn
}
else
xbar
.
io
.
out
l2cacheOut
<>
Cache
(
in
=
l2cacheIn
,
mmio
=
0.
U
.
asTypeOf
(
new
SimpleBusUC
),
flush
=
"b00"
.
U
,
enable
=
true
)(
CacheConfig
(
name
=
"l2cache"
,
totalSize
=
128
,
cacheLevel
=
2
))
io
.
mem
<>
l2cacheOut
.
mem
.
toAXI4
()
l2cacheOut
.
coh
.
resp
.
ready
:=
true
.
B
l2cacheOut
.
coh
.
req
.
valid
:=
false
.
B
...
...
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