system,SoC: add meip

src/main/scala/device/AXI4Timer.scala

@@ -14,7 +14,7 @@ class AXI4Timer(sim: Boolean = false) extends AXI4SlaveModule(new AXI4Lite, new
   val mtime = RegInit(0.U(64.W))  // unit: ms
   val mtimecmp = RegInit(0.U(64.W))
 
-  val clk = (if (!sim) 40000 /* 40MHz / 1000 */ else 2000)
+  val clk = (if (!sim) 40000 /* 40MHz / 1000 */ else 10000)
   val tick = Counter(true.B, clk)._2
   when (tick) { mtime := mtime + 1.U }
 

src/main/scala/noop/fu/CSR.scala

@@ -108,8 +108,11 @@ class CSR(implicit val p: NOOPConfig) extends NOOPModule with HasCSRConst {
   val mip = WireInit(0.U.asTypeOf(new Interrupt))
 
   val mtip = WireInit(false.B)
+  val meip = WireInit(false.B)
   BoringUtils.addSink(mtip, "mtip")
+  BoringUtils.addSink(meip, "meip")
   mip.t.m := mtip
+  mip.e.m := meip
 
   val intrVec = mie(11,0) & mip.asUInt & Fill(12, mstatusStruct.ie.m)
   BoringUtils.addSource(intrVec, "intrVecIDU")

src/main/scala/system/SoC.scala

@@ -12,6 +12,7 @@ class NOOPSoC(implicit val p: NOOPConfig) extends Module {
     val mem = new AXI4
     val mmio = (if (p.FPGAPlatform) { new AXI4Lite } else { new SimpleBusUC })
     val mtip = Input(Bool())
+    val meip = Input(Bool())
   })
 
   val noop = Module(new NOOP)
@@ -24,5 +25,7 @@ class NOOPSoC(implicit val p: NOOPConfig) extends Module {
   else io.mmio <> noop.io.mmio
 
   val mtipSync = RegNext(RegNext(io.mtip))
+  val meipSync = RegNext(RegNext(io.meip))
   BoringUtils.addSource(mtipSync, "mtip")
+  BoringUtils.addSource(meipSync, "meip")
 }

src/test/scala/top/NOOPSim.scala

@@ -37,6 +37,8 @@ class NOOPSimTop extends Module {
   mmio.io.rw <> soc.io.mmio
   soc.io.mtip := mmio.io.mtip
 
+  soc.io.meip := Counter(true.B, 9973)._2  // use prime here to not overlapped by mtip
+
   val difftest = WireInit(0.U.asTypeOf(new DiffTestIO))
   BoringUtils.addSink(difftest.commit, "difftestCommit")
   BoringUtils.addSink(difftest.thisPC, "difftestThisPC")