system,SoC: now L2 cache works well

src/main/scala/system/SoC.scala

@@ -10,7 +10,7 @@ import chisel3.util.experimental.BoringUtils
 
 trait HasSoCParameter {
   val EnableILA = false
-  val HasL2cache = false
+  val HasL2cache = true
   val HasPrefetch = false
 }