system,SoC: add instruction trace signals for ILA

src/main/scala/noop/WBU.scala

@@ -26,5 +26,11 @@ class WBU(implicit val p: NOOPConfig) extends Module {
     BoringUtils.addSource(RegNext(io.in.bits.decode.cf.pc), "difftestThisPC")
     BoringUtils.addSource(RegNext(io.in.bits.isMMIO), "difftestIsMMIO")
     BoringUtils.addSource(RegNext(io.in.bits.intrNO), "difftestIntrNO")
+  } else {
+    BoringUtils.addSource(io.in.valid, "ilaWBUvalid")
+    BoringUtils.addSource(io.in.bits.decode.cf.pc, "ilaWBUpc")
+    BoringUtils.addSource(io.wb.rfWen, "ilaWBUrfWen")
+    BoringUtils.addSource(io.wb.rfDest, "ilaWBUrfDest")
+    BoringUtils.addSource(io.wb.rfData, "ilaWBUrfData")
   }
 }

src/main/scala/noop/fu/CSR.scala

@@ -224,9 +224,9 @@ class CSR(implicit val p: NOOPConfig) extends NOOPModule with HasCSRConst {
 
   val nooptrap = WireInit(false.B)
   BoringUtils.addSink(nooptrap, "nooptrap")
-  if (!p.FPGAPlatform) {
-    def readWithScala(addr: Int): UInt = mapping(addr)._1
+  def readWithScala(addr: Int): UInt = mapping(addr)._1
 
+  if (!p.FPGAPlatform) {
     // to monitor
     BoringUtils.addSource(readWithScala(perfCntList("Mcycle")._1), "simCycleCnt")
     BoringUtils.addSource(readWithScala(perfCntList("Minstret")._1), "simInstrCnt")
@@ -237,5 +237,7 @@ class CSR(implicit val p: NOOPConfig) extends NOOPModule with HasCSRConst {
       perfCntList.toSeq.sortBy(_._2._1).map { case (name, (addr, boringId)) =>
         printf("%d <- " + name + "\n", readWithScala(addr)) }
     }
+  } else {
+    BoringUtils.addSource(readWithScala(perfCntList("Minstret")._1), "ilaInstrCnt")
   }
 }

src/main/scala/system/SoC.scala

@@ -7,12 +7,26 @@ import bus.simplebus._
 import chisel3._
 import chisel3.util.experimental.BoringUtils
 
-class NOOPSoC(implicit val p: NOOPConfig) extends Module {
+trait HasILAParameter {
+  val enableILA = false
+}
+
+class ILABundle extends Bundle {
+  val WBUpc = UInt(32.W)
+  val WBUvalid = UInt(1.W)
+  val WBUrfWen = UInt(1.W)
+  val WBUrfDest = UInt(5.W)
+  val WBUrfData = UInt(64.W)
+  val InstrCnt = UInt(64.W)
+}
+
+class NOOPSoC(implicit val p: NOOPConfig) extends Module with HasILAParameter {
   val io = IO(new Bundle{
     val mem = new AXI4
     val mmio = (if (p.FPGAPlatform) { new AXI4Lite } else { new SimpleBusUC })
     val mtip = Input(Bool())
     val meip = Input(Bool())
+    val ila = if (p.FPGAPlatform && enableILA) Some(Output(new ILABundle)) else None
   })
 
   val noop = Module(new NOOP)
@@ -35,4 +49,22 @@ class NOOPSoC(implicit val p: NOOPConfig) extends Module {
   val meipSync = RegNext(RegNext(io.meip))
   BoringUtils.addSource(mtipSync, "mtip")
   BoringUtils.addSource(meipSync, "meip")
+
+  // ILA
+  if (p.FPGAPlatform) {
+    def BoringUtilsConnect(sink: UInt, id: String) {
+      val temp = WireInit(0.U(64.W))
+      BoringUtils.addSink(temp, id)
+      sink := temp
+    }
+
+    val dummy = WireInit(0.U.asTypeOf(new ILABundle))
+    val ila = io.ila.getOrElse(dummy)
+    BoringUtilsConnect(ila.WBUpc      ,"ilaWBUpc")
+    BoringUtilsConnect(ila.WBUvalid   ,"ilaWBUvalid")
+    BoringUtilsConnect(ila.WBUrfWen   ,"ilaWBUrfWen")
+    BoringUtilsConnect(ila.WBUrfDest  ,"ilaWBUrfDest")
+    BoringUtilsConnect(ila.WBUrfData  ,"ilaWBUrfData")
+    BoringUtilsConnect(ila.InstrCnt   ,"ilaInstrCnt")
+  }
 }