- 02 4月, 2022 1 次提交
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由 William Wang 提交于
* mem: optimize missq reject to lq timing DCache replay request is quite slow to generate, as it need to compare load address with address in all valid miss queue entries. Now we delay the usage of replay request from data cache. Now replay request will not influence normal execuation flow until load_s3 (1 cycle after load_s2, load result writeback to RS). It is worth mentioning that "select refilling inst for load writeback" will be disabled if dcacheRequireReplay in the last cycle. * dcache: compare probe block addr instead of full addr * mem: do not replay from RS when ldld vio or fwd failed ld-ld violation or forward failure will let an normal load inst replay from fetch. If TLB hit and ld-ld violation / forward failure happens, we write back that inst immediately. Meanwhile, such insts will not be replayed from rs. It should fix "mem: optimize missq reject to lq timing" * mem: fix replay from rs condition * mem: reduce refill to use latency This commit update lq entry flag carefully in load_s3 to avoid extra refill delay. It will remove the extra refill delay introduced by #1375 without harming memblock timing. In #1375, we delayed load refill when dcache miss queue entry fails to accept a miss. #1375 exchanges performance for better timing. * mem: fix rs feedback priority When dataInvalid && mshrFull, a succeed refill should not cancel rs replay.
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- 01 4月, 2022 2 次提交
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由 Lemover 提交于
Corner Case that makes l2tlb's performance decrease sharply: core may have mis-speculative memory access, which may cause tlb-miss and ptw req to l2tlb. In l2tlb, the reqs may still miss and even have invalid pte that won't be stored in l2tlb.cache. If the relative ptes are invalid, these reqs will be held by miss queue and wait for page walker performing page table walk one by one. It's too slow and will raise time out assert in l2tlb.missqueue. Solution: store invalid entries(only super entries) into sp. Bad news is that sp only has16 entries, so invaid entries will pollute sp as well. Good news is that the invalid reqs are always in same super page, so only one entries is mostly enough. * l2tlb.cache: sp entries now handles invalid entries * l2tlb.cache: fix syntax error, forgot assgin some signals
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由 Jiawei Lin 提交于
Add support for compiling XiangShan with CIRCT
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- 31 3月, 2022 3 次提交
- 30 3月, 2022 1 次提交
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由 Lemover 提交于
* bump huancun * sram: fix sram, keep rdata when w.valid * tlb: when refill, just return miss at next cycle, rm unused assert
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- 28 3月, 2022 2 次提交
- 27 3月, 2022 3 次提交
- 26 3月, 2022 1 次提交
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由 Jiawei Lin 提交于
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- 23 3月, 2022 2 次提交
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由 Jay 提交于
* IFU <bug-fix>: deal with itlb miss for resend * IFU <bug fix>: enable crossPageFault for resend-pf Co-authored-by: NDeltaZero <lacrosseelis@gmail.com>
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由 Leway Colin 提交于
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- 22 3月, 2022 1 次提交
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由 wakafa 提交于
* readme: update dir structure description and sync en/zh readme * readme: update fig of nanhu-arch * readme: update docs information * readme: fix md format
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- 15 3月, 2022 1 次提交
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由 wakafa 提交于
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- 06 3月, 2022 1 次提交
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由 Yinan Xu 提交于
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- 28 2月, 2022 3 次提交
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由 Steve Gou 提交于
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由 Steve Gou 提交于
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由 William Wang 提交于
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- 25 2月, 2022 1 次提交
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由 Jay 提交于
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- 24 2月, 2022 2 次提交
- 18 2月, 2022 3 次提交
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由 Jiawei Lin 提交于
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由 wakafa 提交于
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由 wakafa 提交于
* bump huancun * bump huancun * bump huancun * Insert 1 buffer betwwen L2 and L3 Co-authored-by: NLinJiawei <linjiawei20s@ict.ac.cn>
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- 16 2月, 2022 2 次提交
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由 Jay 提交于
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由 William Wang 提交于
* mem: opt dcache tag error check timing dcache.resp.bits.miss used to depend on tag_error, it causes severe timing problem. That dependence is now removed. Now when tag_error, we: * Set access fault bit in exception vec * Do not update miss queue. That is to say, if miss, that inst may not be refilled * Mark that inst as dataForwarded so it will not wait for refill * Report error to CSR and BEU If tag_error come with a miss, writeback taht inst from load queue. Otherwise, writeback it from load pipeline. * mem: opt tag error exception writeback logic
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- 14 2月, 2022 1 次提交
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由 Steve Gou 提交于
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- 13 2月, 2022 3 次提交
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由 William Wang 提交于
dcache.resp.bits.miss used to depend on tag_error, it causes severe timing problem. That dependence is now removed. Now when tag_error, we: * Set access fault bit in exception vec * Do not update miss queue. That is to say, if miss, that inst may not be refilled * Mark that inst as dataForwarded so it will not wait for refill * Report error to CSR and BEU If tag_error come with a miss, writeback taht inst from load queue. Otherwise, writeback it from load pipeline.
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由 Jay 提交于
* ITLB <timing>: delay miss and flush req for ITLB * add 2 ILTB requestor and delete tlb_arb * Bump huancun * ICacheMainPipe <bug-fix>: fix slot invalid condition * ITLB <timing>: add port to 6 * ICacheMainPipe <bug-fix>: stop pipe when tlb miss * ICacheMainPipe <bug-fix>: fix illegal flush Co-authored-by: NLinJiawei <linjiawei20s@ict.ac.cn>
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由 William Wang 提交于
* mem: fix ldld vio mask gen logic * mem: fix lq released flag update logic Make sure that every load before a probe has correct released flag See the PR of this commit for illustration * mem: fix ld-ld violation check logic * ci: clean up workspace before do real test * mem: reduce lq released flag update delay for 1 cycle * chore: bump difftest to run no-smp diff * ci: add mc test * mem: fix lq released flag update logic * chore: set difftest firstCommit_limit to 10000 * ci: use dual-nemu-so for mc test
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- 12 2月, 2022 1 次提交
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由 wakafa 提交于
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- 08 2月, 2022 2 次提交
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由 Steve Gou 提交于
the mulitple-hit problem is yet to be solved (although it may be very rare)
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由 Jiawei Lin 提交于
* SoC: remove error_xbar; add more buffers * Bump huancun * Misc: set timeout threshold to 10000 cycles * Bump huancun
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- 03 2月, 2022 1 次提交
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由 Steve Gou 提交于
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- 01 2月, 2022 3 次提交
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由 Lemover 提交于
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由 Jay 提交于
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由 Jiawei Lin 提交于
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